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1937 Commits

Author SHA1 Message Date
Leah Rowe 049ee793db nvmutil: macro safety
maximum safety.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-05-26 21:46:07 +01:00
Leah Rowe bc4bc4b67e nvmutil: fix error exits
ii used to rely on errno for exit status, but this was flawed.

when removing it, i neglected to adjust the actual error exits,
setting errno accordingly. this patch should fix it. this is
important for scripts that use nvmutil, which may rely on its
error status upon exit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-05-26 18:48:27 +01:00
Leah Rowe 0e1e0fd0e8 Reapply "coreboot/x2e_n150: fix mismatching fsp header"
This reverts commit 154c5ff319.

this one is still needed, for x2e n150
2026-05-19 12:07:03 +01:00
Leah Rowe ad2d082bc2 Revert "cb/default: use rev 62c8197dd25376cb7b18d272af167cb176d28bcf"
This reverts commit fedeb6ecd8.

this, along with several other updates, have been reverted.
dell 3050 micro had boot issues, on the update. i therefore
revert the recent revision update, pending further investigation.
2026-05-19 11:54:05 +01:00
Leah Rowe 9a132f96a2 Revert "coreboot: never, ever use Werror"
This reverts commit 2ecfe63b5f.
2026-05-19 11:53:54 +01:00
Leah Rowe e90e1df74d Revert "consolidate haswell iommu patches"
This reverts commit f60350344a.
2026-05-19 11:53:46 +01:00
Leah Rowe 154c5ff319 Revert "coreboot/x2e_n150: fix mismatching fsp header"
This reverts commit 0aa019d323.
2026-05-19 11:53:36 +01:00
Leah Rowe 0aa019d323 coreboot/x2e_n150: fix mismatching fsp header
thanks to sirlami on irc for pointing this out.

due to lbmk blob policy, we must not distribute
fsp except as the full, concatenated binary, thus
complying with intel's license. it is removed from
builds before release, re-inserted via vendor
inject scripts in the usual way.

a while ago, coreboot updated fsp but i had to keep
it on the earlier version for this board, lest old
releases no longer match vendor insertion; the new
fsp version also wasnet well tested, and didn't seem
to contain any changes reported that pertained to
our use of it.

the fsp headers do not match the fsp binary in use,
causing boot issues for users on topton x2e n150.
this patch should fix the issue, as reported by
sirlami who is the one who found and first tested
this fix; i'm simply changing the configuration,
as per sirlami's guidance.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-05-05 23:21:30 +01:00
Leah Rowe f60350344a consolidate haswell iommu patches
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-23 23:14:25 +01:00
Leah Rowe 2ecfe63b5f coreboot: never, ever use Werror
not even once

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-23 21:55:11 +01:00
Leah Rowe fedeb6ecd8 cb/default: use rev 62c8197dd25376cb7b18d272af167cb176d28bcf
this brings the following changes from upstream, since the previous revision:

* 62c8197dd2 mb/google/calypso: Implement ramstage boot logic and QUP firmware loading
* 86c6c748ed mainboard/google/calypso: Update board name in board_info.txt
* 4298078683 mb/google/calypso: Implement `platform_romstage_main` and `platform_romstage_postram`
* 1c79360b44 soc/qualcomm/calypso: Split CPUCP binary into RO and RW regions
* fc1ba3d9b3 soc/qualcomm/calypso: Add soc_prepare_bl31_handoff hook
* 03aaebef7e soc/qualcomm/calypso: Enable CBFS preloading for BL31 and BL32
* e242958a7d soc/qualcomm/calypso: Add weak mainboard_soc_init hook
* 24160f6e3d soc/qualcomm/calypso: Add late init boot state entry
* 10a2805216 soc/qualcomm/calypso: Implement cbmem_top_chipset()
* 9cb549b4e7 mb/google/calypso: Select SOC_QUALCOMM_CDT
* ef4aa128e2 soc/qc/calypso: Introduce CDT_DATA region
* d9c36cb483 soc/qualcomm/calypso: Include cdt.c in romstage compilation
* e2115d2079 soc/qualcomm/calypso: Update apdp.mbn path to use BLOB_VARIANT
* 9fc7c2e3b2 soc/qc/calypso: Implement frequency-based QSPI GPIO drive strength
* 6c566de88d soc/qualcomm/calypso: Make SPI bus frequency configurable via Kconfig
* ef24143cc4 editorconfig: Explicitly set indent_size
* 559eafd2c6 arch/x86/acpi_bert_storage: Add CPER_SEC_PLATFORM_MEM_GUID
* 967ac0be68 soc/amd/common/block/cpu/mcax: Fill generic HEST entry
* 6395a3f1a2 soc/amd/common/block/cpu/mcax: Add helper to identify bank
* 441926d0df soc/amd/common/block/cpu/mcax: Add method to read FRU text from MSR
* ff4ce4fa8a cbfstool: Rename COREBOOT_TS to COREBOOT_B
* 8a50ec739b nb/intel/gm45: Name IOMMU registers and addresses
* 4e56d573ae sb/intel/i82801gx: Drop `SPIBARx` macros
* df5e587623 soc/qc/x1p42100:: Select Secure OS options in X1P42100 Kconfig
* 8ce11782b3 vc/intel/fsp/fsp2_0/wildcatlake: Expose the VccsaShutdown UPD
* a3f7ec15e9 mb/google/nissa/var/pujjoniru: Modify RAM ID table
* 8cbaa8d894 mb/google/fatcat/var/ruby: Change fingerprint enable pin power state
* bf848a6f80 mb/google/bluey: Configure LID_OPEN_S3 GPIO as input without pull
* 0af0b50a3c mainboard/google/fatcat: Disable CPU ratio override on low battery
* 6082e79232 sb/intel/wildcatpoint: Use some Lynx Point ME code
* 1775f25ccc sb/intel/lynxpoint: Make `intel_me_finalize()` static
* 43abc2d1c2 sb/intel/lynxpoint/me.h: Align MKHI macros with Wildcat Point
* e357e3c6bb sb/intel/lynxpoint: Add `intel_me_hsio_version()`
* fab9b2ad97 sb/intel/lynxpoint/me.h: Move function declarations to bottom
* 5d23973369 sb/intel/wildcatpoint: Add parameters to `intel_me_status()`
* 5c1bf73ab9 sb/intel/lynxpoint/me_status.c: Better handle unknown values
* a66bd85e75 sb/intel/wildcatpoint: Replace ME structs with unions
* 7ff29551a4 sb/intel/wildcatpoint/me.h: Align with Lynx Point
* 18e29adc30 sb/intel/lynxpoint/early_me.c: Use northbridge defines
* 1f376aebde sb/intel/wildcatpoint/cfr.c: Use Lynx Point's file
* dccf924a2c sb/intel/lynxpoint: Split a few things off pch.h
* 917880c002 broadwell/wildcatpoint: Decouple headers
* 7812ceb6dc haswell/lynxpoint: Add `fixed_eq` to USB3 config
* 9f90e930cf nb/intel/broadwell: Drop temporary macros
* 9a587c54d7 nb/intel/broadwell: Drop `mainboard_fill_pei_data()`
* 1c2efb8f2b mb/hp/elitebook_820_g2: Set `ec_present` from devtree
* 99affc7f58 nb/intel/broadwell: Separate NB/PCH finalise steps
* 165261ba7d nb/intel/haswell: Tidy up includes
* f2e24e5230 nb/intel/haswell: Unify more cosmetics with Broadwell
* a1af3759cd sb/intel/{lynx,wildcat}point: Drop `SPIBARx` macros
* 9a45e0949f util/amdfwtool: Add PSP directory entry type 0x8e (SFDR)
* 40eb28ec6b mb/google/ocelot/var/ocicat: Enable UFS inline encryption
* 328534098f mb/google/ocelot/var/matsu: Enable UFS inline encryption
* 108006e49a sb/intel/*: Centralize BIOS_CNTL macros
* a22f97f3ff drivers/intel/touch/chip: Fix typo in *device* in comment
* 8121a3dd72 soc/amd/common/block/psp: Add mailbox interface for ROM Armor
* 367e323fd0 mb/google/rauru: Implement Priority Mutex for parallel boot alignment
* 5b49e6d976 soc/mediatek/common: Implement Shared Resource Mutex for DMA safety
* c5f901ba4b fw_config: Always declare fw_config_probe_mainboard_override
* c39b0318de mb/google/rauru/sapphire: Override PANEL_ID in fw_config
* 104aed9a5c lib/fw_config: Add mainboard override hook
* bcfd9a87ee mb/google/bluey: Add is_low_res_panel helper for logo scaling
* fd1ad83256 mb/google/bluey: Implement platform_use_secondary_logo
* 5b811635e7 lib: Add support for secondary resolution bootsplash logos
* a0502589a3 mb/google/bluey/mica: Add vdd and vtsp gpio to depthcharge
* 026e1f60b6 drv/i2c/{rv3028c7, rx6110sa}: Use bool for config options where possible
* cf7e468d32 payloads/Kconfig: fix dead default for PAYLOAD_FIT_SUPPORT
* a7ded1bea6 soc/qualcomm/x1p42100: Use mainboard-specific paths for ADSP blobs
* 387c317058 ec/starlabs/merlin: apply settings without enabled PNP devices
* c0ca77265b util/lint: fix miniconfig check for CONFIG_MAINBOARD_DIR/HAVE references
* 4064b5de37 payloads/external/edk2: build-local FMP cert PCD for capsule updates
* 6e95ade0cb nb/intel/haswell/gma.c: Add Broadwell IDs
* aa9ff8895f nb/intel/haswell/gma.c: Add Broadwell GT PM init
* b75d086f86 nb/intel/haswell/gma.c: Replace GT register tables
* 892d68a8c8 nb/intel/haswell/gma.c: Init CDCLK before gfxinit
* f7412bf209 nb/intel/haswell/gma.c: Add support for Broadwell CDCLK
* 65fdf4754e nb/intel/haswell/gma.c: Enable power well later
* 625ba6ed9d nb/intel/haswell: Drop native gfx init leftovers
* 8443582672 drivers/intel/gma: Drop unneeded DDI stuff
* 6ca4e93632 nb/intel/haswell/gma.c: Update PM init steps
* c8320ab9f6 nb/intel/haswell/gma.c: Avoid using invalid GTT resource
* a5e124b6d0 nb/intel/haswell/gma.c: Fix PCI driver variable name
* 5e0cf0e730 util/cbfstool: don't invalidate MH cache unnecessarily
* 1754d90560 cbfstool/bzImage: Fix out-of-bound read with very short input file
* df2afe0b22 cbfstool/fv: Fix out-of-bound read with very short input file
* 9e600ac8dd cbfstool/fit: Fix out-of-bound read with very short input file
* d9085c1a7b cbfstool/elfheaders: Fix out-of-bound read with very short input file
* 27cdca23c1 mb/google/ocelot: add alternate clock request support
* 5409e52b5f soc/qualcomm/x1p42100: Increase TTB size from to 64K for Bluey
* 07c6b36ab3 mb/google/bluey: Add support for PWM-based backlight control
* a3011baad1 soc/qualcomm/common: Correct GPIO offset for master PMIC
* eaad3ecd4d mainboard/google/bluey: Use generic naming for backlight PMIC GPIO
* f457508572 mainboard/google/bluey: Add touchscreen power control via GPIO
* bcaaac5804 soc/amd/cezanne/Kconfig: add FSP binaries for V2000A
* 5cff8485cb 3rdparty/amd_blobs: advance submodule pointer
* 45cc75fe50 soc/amd/common/pci: Add host bridge _PRT method for root-bus devices
* 434c92b908 acpi/acpigen_pci: Add devfn-based _PRT entry helpers
* 64193f07f6 mb/google/dedede/var/blipper: Add stop_gpio, stop_delays to GTCH7503
* f4b98a0ba3 drivers/amd/ftpm: Disable pre ramstage
* 5bbb46481f soc/mediatek: Refactor MT6685 PMIC driver to use lazy initialization
* cbd0b52c5e lib/delay: Optimize mdelay and delay in cooperative multitasking
* c8ac5953e9 ec/lenovo/h8: Respect H8_HAS_LEDLOGO configuration
* 643efabd2a mb/google/ocelot: enable BayHub & Genesys SD Card
* 87f9bd1235 Revert "soc/qualcomm/x1p42100: Select APDP and Ramdump configurations"
* 3b44256255 soc/amd/common/block/psp: Check backup flash busy flag
* c47cbaa3ac lib/cbfs.c: deduplicate checking/querying type on _cbfs*_alloc()
* 7f3a299dc8 mb/asus/h61-series: Add Asus P8H61-M LX2
* 054318251c mb/asus/h61m-a_usb3/hda_verb.c: Drop extraneous codec verbs
* ae9ffa965d acpi/acpigen_ps2_keybd: Map CONTEXTUAL_INSERT
* 0223a54137 include/input-event-codes.h: Update to upstream
* c61c56e2da soc/qualcomm/common: Adjust GPIO base for master PMIC
* 888d9a4170 mb/google/bluey: Initialize ADSP boot reason in boot
* 053ddab917 drv/i2c/{rv3028c7,rx6110sa}: Change date format in final-hook
* 4b8bb72cbb mb/siemens/mc_ehl{6,8}: Enable sync of external RTC to CMOS RTC
* 91e5644fb0 mb/siemens/mc_rpl1: Enable external RTC RV3028-C7
* baad6487e7 cbfstool: Improve lexer error message
* e8a3bb81db treewide: Remove WARNINGS_ARE_ERRORS
* a2d386749d soc/amd/glinda: Mark sleep button as control-method only
* f7d5afbc18 soc/amd/phoenix: Mark sleep button as control-method only
* 5b0dd4933a soc/amd/mendocino: Mark sleep button as control-method only
* 81f77fd608 soc/amd/picasso: Set ACPI_FADT_SLEEP_BUTTON flag at SoC level
* 30341a6d01 soc/amd/cezanne: Mark sleep button as control-method only
* d19104a3ba soc/qc/x1p42100: Implement frequency-based QSPI GPIO drive strength
* f75dc1b17c soc/qualcomm/common: Allow SoC override for QSPI GPIO configuration
* 48acc27551 mb/google/bluey: Select 75MHz SPI frequency for board models
* 4ce87ee626 soc/qualcomm/x1p42100: Make SPI bus frequency configurable via Kconfig
* bd89a3df97 soc/qc/x1p42100: Move Display and LPASS initialization to late stage
* 3d08ec12df soc/qualcomm/x1p42100: Enable CBFS preloading for BL31 and BL32
* 8e0e61c48f mb/google/bluey: Call setup_usb_late directly in mainboard_soc_init
* 1e6e64eeca payloads/ext/.gitignore: Add coreDOOM build directory
* be555d8614 payloads/ext/.gitignore: Sort alphabetically
* 2942c415db mb/asus: Add ASUS Z87-K (Haswell)
* 7721bb3b72 soc/amd/glinda: Pass SMMSTORE region to amdfwtool
* 9439a4e6f7 util/amdfwtool: Introduce table granularity
* a3bb1d2f21 ifdtool/ifdtool.c: Update FMAP template generation
* 246e795b13 amdfwtool: Support directories greater than 4MiB
* a8a682b430 mb/google/atria: Enable additional devices
* d888458899 mb/google/atria/var/atria: Add initial storage configuration
* 18e9062b88 mb/google/ocelot: Move HDMI GPIOs to early bootblock stage
* 1b61c8f721 google/fatcat: Provide hook at the entry of BS_DEV_INIT_CHIPS
* f40fc7b290 mb/google: Refactor MediaTek boards to use include/baseboard/ namespace
* 357f2c8350 mb/google/oak: Rename WRITE_PROTECT macro to GPIO_WP
* 63f2426042 mb/google/bluey: Enable DAM sink sensor Z1 optimization for Quartz
* b19b4f15d7 mb/google/bluey: Add support for DAM sink sensor Z1 optimization
* 8d51c6537a mb/siemens/mc_rpl1: Enable I2C1 bus
* 140cb7b6df drv/i2c/rv3028c7: Add feature to sync date and time into CMOS RTC
* d7c188f6c2 mb/starlabs/*: expose PS/2 keyboard ACPI node only
* 481657b45f mb/starlabs/common: Gate Intel-specific settings
* 5eb5f3a9bb mb/google/ocelot: Enable UFS inline encryption
* 18b960be65 soc/qualcomm/x1p42100: Remove unused cpucp_prepare() declaration
* b7bff5afea mb/amd/crater/devicetree_v2000a.cb: Update GPP port config
* b74ab281bd mb/google/fatcat/var/lapis: Disable touchpanel wake-up configuration
* 3bc8a9fec1 soc/amd/common/block/spi: Add ROM Armor checks
* acd79afe9a soc/amd/glinda: Fill in cache defaults
* e18df21852 soc/amd/cezanne/Kconfig: Add 64 Bit support for V2000A
* 842b74a0e4 mb/amd/crater/ec.c: Fix calculation of reg in log message
* 81de3098f8 mb/amd/crater: Disable PCIe feature programming
* 37a1035ddc soc/mediatek/common: Log firmware splash screen status
* 586389eafd mb/google/bluey: Skip SoC debug features in recovery mode
* 8aa6763cea soc/qualcomm: Allow skipping SoC debug features in recovery
* cb51506c64 mb/starlabs/adl: Correct selection of EC_STARLABS_FAN
* 8103a5ff9c mainboard/opencellular/elgon/Kconfig: fix dead default for FMDFILE
* ec0d1946e7 soc/qualcomm: Remove HAVE_CBFS_FILE_OPTION_BACKEND
* f8a7a5c02e mainboard/google/bluey: Move display startup to mainboard_soc_init
* 5fc9a1065b soc/qualcomm/x1p42100: Support board-specific SoC initialization
* a5fb73a737 soc/intel/pantherlake: Limit active displays for portrait panels
* d1c1627ede mb/google/bluey: Update GPIO configuraton for AMP enable pin
* 83442b749f mb/google/bluey: Refactor peripheral init and adjust display timing
* fb184d4f3d mb/google/bluey: Consolidate peripheral init and fix PCIe timing
* 5a24200a97 util/cbfstool: avoid creating an image with only COREBOOT_TS
* bf8a8a7aaf mb/google/fatcat: Enable CNVi WWAN coexistence for CELLULAR_PCIE
* d9956b0bcf soc/intel/pantherlake: Add CNVi WWAN coexistence support
* e71531558e acpi/acpigen_ps2_keybd: Map navigation shortcut keys without numpad
* a2bf34ee1c soc/mediatek/mt8196: Relocate FRAMEBUFFER to 0x90200000
* 19e69dde5f vc/intel/fsp/fsp2_0/pantherlake: Update the PTL FSP full headers
* 69f0093d54 mb/google/bluey: Optimize NVMe power sequencing in romstage
* 2a6b546ca2 soc/qualcomm/x1p42100: Add support to power off PCIe Endpoint
* 904aea246f soc/qc/x1p42100: Implement soc_prepare_bl31_handoff to throttle QSPI
* fb81f6f6ce arch/arm64: Add soc_prepare_bl31_handoff() hook
* 66c68e0168 soc/qualcomm/common: Add qspi_set_bus_clock() helper
* 86e45bf52d mb/apple/macbook21: Improve variant name and reintroduce overridetree.cb
* 198aabff32 soc/intel/xeon_sp: Add more defines for register SMM_FEATURE_CONTROL
* 4c3e63e7fd mb/asus/p8z77-v_lx2: Change super I/O chip to nct5535d
* d93eb115b0 util/liveiso: Update nixos to 25.11
* 54b518da64 mb/asus/h61-series: Add P8H61-I R2.0 variant (it8771e)
* 74105264e0 util/kconfig/confdata.c: fix -Werror=discarded-qualifiers
* ece067d8be util/amdtool/cpu.c: Report SME-HMK state
* 14824c7307 util/amdtool/cpu.c: Fix reporting of SEV features
* b7dd49d68d security/tpm/tspi/crtm.c: remove superfluous logging
* 371ef274f9 lib/cbfs.c: don't skip CBFS verification in SMM
* 9e04f49a7a x86: define toolchain for SMM
* 98b0fc0e56 mb/google/atria/var/atria: Add TPM configuration
* 0eadf8856e mb/google/atria/var/atria: Add initial I2C configuration
* 81cdb782f6 mb/google/atria: Add GPE configuration
* 7e0e36d412 mb/google/atria: Select configuration for CHROMEOS and VBOOT
* 1493066f74 mb/google/atria: Add EC support
* df8d6f9a57 mb/google/atria: Add memory initialization support
* 7402845e29 mb/google/atria: Add console UART configuration
* 3b6f1d3817 mb/google/atria/var/atria: Add initial GPIO configuration
* 5d4f18e412 mb/google/atria/var/atria: Add GPIO stub configuration
* 9bf6b9096e mb/google/atria: Add atria variant support
* f6caf8bf42 mb/google/atria: Add initial mainboard
* 6a5f9c8a23 util/intelmetool: Use separate src and build directories
* 7d7499449d soc/amd/cezanne: Drop selection of SOC_AMD_COMMON_BLOCK_SPI_DWORD_ACCESS
* ff0467b96e mb/google/brya: Set CFR storage default to CBI value on taeko/taniks
* 815dc9d445 mb/system76/mtl: Enable EnableTcssCovTypeA configs
* 49f9e95c8d util/lint/lint-stable-005-board-status: Add "All-in-One" category
* f4df60e306 intel/block/pcie/rtd3: Implement _PR3
* d3b7103c9d .gitignore: ignore extended-junit.xml files
* 2d8f4958c5 payloads/ext/.gitignore: match tint tarball
* 5ea3c7f7fa payloads/ext/.gitignore: match MemTest86+ new src dir
* 53c2fc39ac soc/intel/alderlake: Remove ADL_P_ID_9 from PCH SA device list
* 21f79fb69b util/intelmetool: Add Raptor Lake-S PCI ID
* b9399443c0 soc/intel/alderlake: Add Raptor Lake-S 8+12 (0xa740) support
* c9685501f5 mb/asus/maximus_vi(i)_impact: Update HDA codec name
* dfe5b08978 soc/intel/pantherlake: Add UFS inline encryption support
* 4e4a2f85bb mb/siemens/{mc_ehl6,mc_ehl7}: Set IccMax IA to 15A
* 76be626491 soc/intel/elkhartlake: Expose IccMax IA domain to devicetree
* 5267cae13a utils/crossgcc: Update NASM from 2.16.03 to 3.01
* 3ef459a968 utils/crossgcc: Update acpica from 20250807 to 20251212
* e518885dce utils/crossgcc: Update GCC from 14.2.0 to 15.2.0
* a425b57634 soc/qc/x1p42100: Update eDP lane/PHY handling and add BPC selection
* a309c042e2 mb/google/bluey: Log firmware splash screen status to BIOS and ELOG
* 52da3306cc mb/google/bluey: Refactor and clean up display initialization
* ab360c9195 mb/google/bluey: Guard Debug Access Port (DAP) configuration with Kconfig
* b11e7b4afa soc/qualcomm/x1p42100: Enable memory chip information filtering
* 722f8e630d soc/qualcomm/common: Filter undefined memory chip entries
* 4e1d6cee0c soc/qualcomm/x1p42100: Select APDP and Ramdump configurations
* 6d73c02606 soc/qualcomm/x1p42100: Use correct path for APDP binary
* 7dc8ae735a mb/google/bluey: Move apdp and ramdump regions to RW only
* 08bff09608 vc/amd/fsp/renoir/FspUpd.h: Fix comment for FSP signatures
* f2f1a5814f mb/amd/crater/Kconfig: Change SOC to V2000A
* 661a1aa5a2 mb/google/skywalker: Create R2d2 variant
* 9a59f1a5ac mb/asus: Add Maximus VII Ranger (Haswell/Broadwell)
* 87af5c2aef mb/asus: Add Maximus VI Hero (Haswell)
* ae3bec1c7c soc/amd/cezanne/Kconfig: Enable Cache on S3 resume
* ce444c4c76 soc/amd/cezanne: Add V2000A SOC
* 621d722ab8 soc/amd/cezanne/Kconfig: Extend bus numbers to 256 for renoir
* 0cbc9e9c57 soc/amd/cezanne/Kconfig: Remove ADD_FSP_BINARIES from RENOIR
* 4369c463fc soc/amd/common/block/spi: Increase SPI write speed by 27%
* 630a6e66c1 mb/asus/maximus_vii_impact: Update comment for USBDEBUG_HCD_INDEX
* f89717ecc3 soc/qualcomm/x1p42100: Remove dummy regions around framebuffer
* b6ca7755f3 utils/crossgcc: Update binutils from 2.45 to 2.45.1
* 2227096f55 arch/arm64: Add support for COOP_MULTITASKING
* e7d4cc6813 lib: Add comprehensive stack checking for cooperative threads
* 66cb3e79a4 util/find_usbdebug: Add missing 9 Series PCH rate matching hub IDs
* d1da8ec7bb util/autoport: Use official chipset names
* 40df3567c6 mb/google/bluey: Avoid using uninitialized EDID data
* 02e5c1c39c mb/google/calypso: Add dependency on I2C_TPM for DRIVER_TPM_I2C_ADDR
* b8bd5a5639 mb/google/calypso: Add Calypso board variant to Kconfig
* 201392d363 mb/google/calypso: Rename mensa mainboard directory to calypso
* b1a374e635 mb/google/mensa: Reduce RW_CDT partition size to 4K
* eaaa63791a mb/google/mensa: Change fingerprint interface from SPI to USB
* e187893fa9 mb/google/mensa: Rename Kconfig symbols from MENSA to CALYPSO
* c22ab9f535 mb/google/bluey: Select SOC_QUALCOMM_CDT and shrink RW_CDT partition
* a4ee53610f soc/qualcomm/x1p42100: Include cdt.c in romstage compilation
* 598504962e soc/qualcomm/common: Read and populate CDT data
* f3f8e7f61c memlayout: Introduce CDT_DATA region
* b6a87477d7 soc/qualcomm/common: Introduce SOC_QUALCOMM_CDT Kconfig option
* 681c5a219b mb/google/bluey: Enable DAP for Quenbi and Mica variants
* 8792766e05 mb/google/bluey: Support configurable DAP SMBs Slave IDs
* 7d863336bc mb/google/bluey: Increase charging rail stabilization delay to 5s
* 6fa8d2c415 mb/google/bluey: Select splash logo based on panel resolution
* 7a533becf2 soc/qualcomm/common: Add debug dump for mem_chip_info
* f502f316f2 mb/google/*: Add disable_heci1_at_pre_boot to CFR ME options
* e3111a3dc2 soc/intel/common/cse: Add CFR override for disabling HECI1 at end of boot
* 15529219c9 soc/amd/common/block/cpu: Enable cache on S3 resume
* 53561b7903 soc/amd/common/block/spi: Enable SPI_FLASH_SFDP for all SoC
* 4e522f49b6 drivers/ck505: Add pre and post hooks
* 83977273f1 mb/asus: Add ASUS Maximus VI Impact (Haswell)
* 1e49b5c385 mb/starlabs/starfighter: fix touchpad settings not being applied
* 1f05ba35b9 mb/starlabs/starfighter: Add missing WiFi and Bluetooth controls
* 049a580bbf mb/lenovo/sklkbl_thinkpad: Enable TBT support for T580
* ec6856785d sb/ricoh/rl5c476: Fix building for 64-bit targets
* 4a5422fb99 lib/thread: Use standard doubly linked list API
* 41d55fae84 commonlib/list: Add list_pop()
* 25d3809ea3 payloads/edk2: Update default MrChromebox branch from 2511 to 2603
* 577f30851d util/chromeos/crosfirmware: Update recovery inventory parsing
* 7dfe91fe0b soc/intel/cometlake: Always select PMC_IPC_ACPI_INTERFACE
* 653e2fee68 mb/amd/crater: add and use APCB recovery file
* 7222e5911b acpi/dsdt_top.asl: Add hook to enable routing in APIC mode
* 9f65c47ea7 lib/timestamp: Fix get_us_since_boot()
* 6bd55cf269 soc/amd/cezanne: Select SOC_AMD_COMMON_BLOCK_HDA
* 3cd83d2ce0 mb/google/bluey: Reset eDP and disable backlight on display stop
* e5a73dc9e6 mb/google/bluey: Use common APIs to configure PMIC GPIOs
* 4c784a6f3a soc/qualcomm/x1p42100: Define PMIC slave IDs
* 355658054a soc/qualcomm/x1p42100: Include new PMIC GPIO APIs in ramstage
* a3bf18f3b2 soc/qualcomm/common: Add APIs to configure PMIC GPIOs
* 1b2c0f8aca mb/google/bluey: Switch fingerprint sensor to USB interface
* 3976f8ed0d mb/supermicro/x11-lga1151-series: Enable SATA hotplug
* bc2092acd4  mb/google/jecht: Add CFR options for CPU undervolt
* 8d2e8295c5 mb/google/jecht: Add CFR PL1/PL2 package power overrides
* d1633f5cc1 mb/google/beltino: Add CFR options for CPU undervolt
* ef8f4d7ac5 mb/google/beltino: Add CFR PL1/PL2 package power overrides
* 32f16591aa mb/google/puff: Add CFR options for CPU undervolt
* a612fdce4f mb/google/puff: Add CFR PL1/PL2 package power overrides
* faf5f0ea9e mb/google/fizz: Add CFR options for CPU undervolt
* e9239d2308 soc/intel/skylake: Add support for OC mailbox programming
* 1654e0a1de soc/intel/cannonlake: Add support for OC mailbox programming
* aaa396d571 cpu/intel/haswell: Add support for OC mailbox programming
* fa68b66686 drivers/intel/oc_mailbox: Add OC_MAILBOX undervolt driver
* b137be4d8f soc/amd/cezanne: Fix USB3 port aliases and USB port order
* b9e6bc61ce soc/amd/cezanne/acpi: Guard RTC workaround with CONFIG(CHROMEOS)
* 912817d316 Revert "mb/google/bluey: Temporarily skip display init in normal mode"
* ce74ab0d21 soc/qc/x1p42100: Remove framebuffer from generic MMIO reporting
* 889c42c177 device/pciexp_device: Fix SR-IOV detection
* 5a3e8f3076 soc/amd/glinda: Use SPI_FLASH_SFDP
* 67845716da drivers/spi/spi_flash_sfdp: Parse JEDEC SFDP
* a95ee50a7b mb/starlabs/adl/{i5,hz}: increase speaker output power to 2.5W
* 601bbd87bd mb/google/zork/vilboz: Set proximity INT as GPI for non-ChromeOS
* cbbf961526 arch/x86/acpi_bert_storage: Clear allocated structure
* 84c1b81540 Revert "soc/intel/common/power_limit: Raise PsysPL1 when package PL1 is above TDP"
* a5941ba5f8 soc/amd/common/psp: add support for early PSP v2 access via SMN
* b514b1e671 soc/amd/common/psp/Makefile: make ftpm.c build more conditional
* 40e56f2358 soc/qc/x1p42100: Define and reserve framebuffer region
* 499ab15def mb/google/bluey: Implement display initialization hooks
* 382f5e0cd4 mb/google/bluey: Add support for firmware splash screen
* c120e1b9fc mb/google/bluey: Temporarily skip display init in normal mode
* c6e0f28814 soc/qualcomm/x1p42100: Add eDP display support
* 61706268a6 soc/intel/common: Replace numbers with mask constants in power limits
* 38addfb24f mb/google/bluey: Power on NVMe rail earlier in boot
* 2f752c6341 util/cbfstool/flashmap/fmap.c: Fix buffer overflow
* 96a91bbaf9 mb/siemens/mc_ehl8: Reduce I2C clock rate to 100kHz
* 012bf817a9 soc/intel/common/block/power_limit: Remove unnecessary rdmsr
* 654f328474 soc/intel/common/power_limit: Don't disable package PL1 in MCHBAR
* f7bb12e423 mb/google/bluey: Set GPIO206 as output low on Bluey
* f0211870e0 soc/amd/{turin,genoa}_poc: Select SOC_AMD_COMMON_BLOCK_HAS_ESPI1
* f6cd320061 acpi/acpigen_pci_root_resource_producer.c: Report TPM MMIO in domain 0
* bb0e107ebd soc/intel/common: Add hardware limit validation for power overrides
* c803ca2ed6 amd/common/block/pci/acpi_prt.c: Add SoC hook to get GSI base
* 8e57010d88 mb/google/bluey: Use slow charging if battery is less than 2%
* 432703dd7a mb/siemens/mc_ehl7: Deactivate IGD
* eda62af9dd mb/google/bluey: Implement slow-to-fast charging transition logic
* 1dc346e61e cpu/intel/haswell: Add option-backed PL1/PL2 overrides and package limit lock
* 0d95bb5158 mb/google/fizz: Add CFR PL1/PL2 package power overrides
* 6c10b07146 mb/google/fizz: Refactor mainboard_set_power_limits()
* 976149a2f7 soc/intel/common/power_limit: Raise PsysPL1 when package PL1 is above TDP
* bdf757aa86 soc/intel/common/power_limit: Add option-driven PL1/PL2 overrides and locking
* f45d6e696a mb/google/bluey: Configure sink sensor for DAM port
* 63fc231480 AUTHORS: Update with new authors from the 26.03 release
* f67b5ed6fd util/release: add get_new_authors helper
* 7bcb90047e mb/google/nissa/var/pujjoniru: Add 2 Micron modules to RAM id table
* c683673095 mb/google/nissa/var/yavilla: Add RAM ID H58G56BK8BX068
* 66ed61a73c b/google/brox/var/lotso: Add RAM ID for MT62F1G32D2DS-031RF WT:C
* 6d3e13a33a mb/google/bluey: Conditionally enable FP rails in normal boot
* 137b9c59ea mb/google/var/fatcat/lapis: adjust 'cirrus,detect-us' property to  improve the noise situation
* d381d33a39 soc/soc/amd/glinda: Hook up STX VBIOS
* 1b284012b8 mb/starlabs/starfighter: add configurable touchpad tuning
* 97d616b927 soc/amd/common/block/spi: Add helper functions
* 102b9b42ae mb/google/skyrim/var/frostflow: Add non-ChromeOS TBMC support
* d012a678e2 mb/google/guybrush/var/dewatt: Add non-ChromeOS TBMC support
* 7eb70b259b mb/google/zork: Set correct SYSTEM_TYPE for all variants
* dbd05fc2da mb/google/kahlee: Set correct SYSTEM_TYPE for all variants
* 45378e6fc2 mb/google/guybrush/dewatt: Mark board as convertible
* 227dbbad4a mb/google/skyrim: Use GpioInt wake for touchpad and fingerprint reader
* fe445f4b9d mb/google/skyrim: Use level-triggered IRQ for touchpad and touchscreen
* 49803f2130 mb/google/guybrush: Use GpioInt wake for touchpad and fingerprint reader
* 62abc7aca0 mb/google/guybrush: Switch touchpad IRQ to level triggering
* 65858ad5c9 mb/google/zork/var/vilboz: Guard GPIO for SAR sensor
* fd5b6323ea mb/google/zork: Use GpioInt wake for touchpad and fingerprint reader
* e2c419bc44 mb/google/zork: Use level-triggered IRQ for touchscreens
* 30b8524ff5 soc/qualcomm/calypso: Enable basic PCIe support
* ba3b83e51e mb/google/mensa: Implement SKU ID retrieval
* 888cc7f92a mb/google/mensa: Initialize FP GPIOs in bootblock
* a6921f7fb9 soc/qualcomm/calypso: Add placeholder for early clock initialization
* 421c21c6cf soc/qualcomm/calypso: Initialize QSPI and QUPv3 in bootblock
* 0fc956cd2d mb/google/mensa: Set correct Kconfig defaults for peripherals
* 8dbf88a300 soc/qualcomm/calypso: Add QUP Serial Engine (SE) entries
* 79b6dde1a5 soc/qualcomm/calypso: Set correct Kconfig defaults for peripherals
* dde131c555 mb/google/mensa: Add initial support for Mensa
* 38e8eadfa7 soc/qualcomm/calypso: Add initial SoC skeleton for Calypso
* c7a7fbbf2c soc/qualcomm: Add support for QUPV3 wrapper 3
* cb05d160d4 soc/qualcomm/x1p42100: Rename SOC_QUALCOMM_BASE to include SoC name
* b8ed516097 mb/google/bluey: Defer display initialization based on boot mode
* 9bfab15070 docs/mb/hp: fix link to Sure Start whitepaper, add another
* e839059435 mainboard/starlabs/common: enable OPAL S3 unlock
* 9fc27f4b15 soc/intel/common/pcie/rtd3: Add RTD3 support for OPAL S3 unlock
* 468f8131ec security/tcg/opal_s3: hook into default SMI/resume paths
* 36a4d92239 util/amdfwtool: Fix APOB_NV quirk
* e57478e238 treewide: Apply nonstring attribute to unterminated strings
* 492b7c7c09 soc/amd/common/block/psp: Add commands for A/B recovery
* cf541343a9 ec/lenovo/h8: Implement LOGO LED
* 7609822730 mb/starlabs/*: disable TCO Intruder SMI
* 26d005fb30 mb/starlabs/starfighter: use safe shared panel PWM frequency
* 25eee46bbc mb/starlabs/starbook/{adl,rpl,tgl}: raise panel PWM frequency
* bfaadde071 mb/starlabs/starbook/{adl_n,mtl}: raise panel PWM frequency
* d4bfac6564 mb/starlabs/adl/i5: use safe shared panel PWM frequency
* 1ca1c60019 mb/starlabs/adl/hz: raise panel PWM frequency to 10kHz
* e970b9b0df mb/starlabs/adl/hz: restore panel minimum brightness
* 9f6ae2b5a2 mb/starlabs/starbook/{adl,rpl,tgl}: fix panel timings
* f13a9cb910 mb/starlabs/adl/i5: fix panel timing values against datasheet
* d0e2b5df61 mb/starlabs/starbook/{adl_n,mtl}: fix panel timings
* f1bc59e66e mb/starlabs/starfighter: fix panel timing values against datasheet
* 040ff1ff39 mb/starlabs/adl/hz: fix panel timing values against datasheet
* ed261d5447 mainboard/starlabs/common: include acpi_gnvs.h in gnvs.c
* f1505f5e46 mb/google/zork: Add MKBP support
* a5b5591d31 mb/google/reef: Add MKBP support
* 134b3e050a mb/google/octopus: Add MKBP support
* caf980b3fa mb/google/hatch: Add MKBP support
* 1a75cd1da2 mb/google/glados: Add MKBP support
* f1e95c5536 mb/qemu/riscv: Intialize PCI root bus
* c5e905fa21 util/mec152x/Makefile: Include commonlib/bsd/compiler.h
* 576515394c util/amdfwtool: Use uint8_t for bitfields
* 800d3dbef4 soc/qualcomm/x1p42100: Support separate RO/RW CPUCP binaries
* c0e82f6963 3rdparty/amd_blobs: advance submodule pointer
* 82de37d171 libpayload: Makefile.mk: Fix unrecognized option '--no-weak'
* e021937f35 soc/amd/glinda: Add RAS Kconfig options
* e232934f6f mb/google/nissa: Create dirkson variant
* 79c98cca80 mb/google/volteer: Add non-ChromeOS TBMC support for 360/flip variants
* f867d8f76b mb/google/dedede: Add non-ChromeOS TBMC support for 360/flip variants
* 25ad0950a8 mb/google/brya: Add non-ChromeOS TBMC support for 360/flip variants
* a8615bed6b mb/google/cyan: Add support for EC mode change event
* 8f5477d92d mb/google/volteer: Set correct SYSTEM_TYPE for all variants
* 7b87cda615 mb/google/reef: Set correct SYSTEM_TYPE for all variants
* 7995a1d3ea mb/google/octopus: Set correct SYSTEM_TYPE for all variants
* 14ef332242 mb/google/hatch: Set correct SYSTEM_TYPE for all variants
* 3f10068936 mb/google/glados/var/caroline: Mark board as convertible
* 025c0edeb2 mb/google/dedede: Set correct SYSTEM_TYPE for all variants
* c049dcc271 mb/google/brya: Set correct SYSTEM_TYPE for all variants
* ecab793650 ec/chromeec: Add Kconfig and asl for vendor tablet ACPI
* 1769b10be0 mb/google/bluey: Lower CPU frequency to 710.4MHz for low-power boot
* 710df33471 mb/google/bluey: Signal ADSP to skip Type-C port resets during boot
* 521e7949c1 mb/google/bluey: Add support to reduce CPU clock to minimum frequency during OFF‑mode charging
* 9a86b9f729 mb/google/bluey: Integrate ADSP load and LPASS bring-up into charging flow
* 8beca96470 soc/qualcomm/x1p42100: Add LPASS bring-up sequence for ADSP cold boot
* a58f752d0f soc/qualcomm/common: add CBCR disable and config helpers
* 2e3e690023 soc/qualcomm/x1p42100: Support to load ADSP Lite firmware
* 1c6f4618b6 mb/google/bluey: Allow charger behind DAM
* 94dd3f3bba soc/qualcomm/x1p42100: Increase boot CPU frequency to 3.0GHz
* da36276955 smbios: Add smbios_cache_speed() implementation
* 6f7f27e6c1 soc/qualcomm: Relocate translation tables to DRAM
* 4320fe713a mb/google/brask/var/constitution: Generate RAM ID for Samsung K4UBE3D4AA-MGCR
* d43421da65 mb/google/nissa/var/quandiso: Generate RAM ID for SL5D32G32C2A-HC0
* 28fbd247f6 spd/lp5x: Generate initial SPD for SL5D32G32C2A-HC0
* d72d7d1ba0 soc/amd/common/block/spi: Check if ROM Armor is enforced
* cd8072191d soc/amd/common/block/psp: Get ROM Armor state from HSTI
* b42d148171 soc/qualcomm/x1p42100: Define CPUCP region and map in MMU
* 92fa2bbd09 soc/qualcomm/x1p42100: Disable compression for CPUCP payload
* 6c8a2a6ea1 soc/amd/glinda: Use VBIOS from amd_blobs
* ff7bc7d2d1 drivers/amd/ftpm: Fix compilation
* ab63331423 mainboard/starlabs/lite: Remove unused header
* a19b5b4b17 mainboard/starlabs/starfighter: Remove unused header
* c4e44caef8 mainboard/starlabs/starbook: Remove unused headers
* b0ff1cdd28 mainboard/starlabs/adl: Remove unused headers
* d319b33114 mainboard/starlabs/common: Remove unused headers
* b137044a39 ec/starlabs/merlin: Remove unused halt.h
* 7bc3561803 ec/starlabs/merlin: Include stdint
* e657f5da15 mainboard/starlabs: drop redundant vbt.bin overrides
* b7faa4c51a amdfwtool: Allow to set bios entry 0x6d (AMD_BIOS_NV_ST)
* 8e04206f28 amdfwtool: mark AMD_BIOS_APOB_NV BIOS directory entry as writable
* 8549c6894a amdfwtool: Make NVRAM regions writeable
* 1928db74a1 Documentation: Finalize 26.03 release notes
* aa27204240 mb/google/fatcat/variants/moonstone: Implement BOE touchscreen power timing
* dc41e46b7f google/fatcat: Move mainboard_pre_dev_init_chips hook to BS_ON_EXIT
* 3f46d6fd93 mb/google/bluey: Use safe SPMI reads for battery current telemetry
* 2f93e4331e soc/qualcomm/common: Add spmi_read8_safe helper with retry logic
* 444691603d mb/google/bluey: Support RTC wake-up boot mode
* 941597e52f {commonlib, libpayload}: Add RTC_WAKE to boot_mode_t
* 34f67580b5 ec/google/chromeec: Add API to check for RTC host event
* b00bfdd1e0 mb/google/bluey: Refactor SE firmware loading into early/late stages
* 1f2ea3c13e mb/google/bluey: Initiate PCIe link training in romstage
* f56a936c54 soc/qualcomm/x1p42100: Allow asynchronous PCIe initialization
* f1baed6f79 soc/qualcomm/common: Implement asynchronous PCIe initialization
* 8a90e46346 soc/qualcomm/x1p42100: Increase CBFS_MCACHE size to 22K
* 4b227a4aa6 arch/arm64: Add debug API to dump MMU page table configuration
* 99d409d3ba arch/arm64: Add support for TTB relocation to DRAM
* 493770d730 mb/starlabs/starfighter/mtl: add speaker idle CFR option
* f3c656b76a soc/intel/common/block/smm: drain sync smi around smmstore
* a215e07533 mb/google/nissa/var/craask: Add H58G56CK8BX146 to RAM ID table
* a7773d3ab3 mb/google/fatcat: Modifying parameters for AC only
* 05246a5934 mb/asus: Add Maximus VII Impact (Haswell/Broadwell)
* 0f30eed3e8 Doc/nb/intel/haswell: Fix typo
* 5e146277ae Doc/nb/intel/haswell: Drop outdated section about SPD addresses
* 86b3901ba5 mb/google/bluey: Monitor thermal sensors during charging
* 657bd42548 soc/qualcomm/x1p42100: Define TSENS controllers and thermal zones
* 53529b1d93 soc/qualcomm/common: Add Qualcomm TSENS support
* 9e7c787f6d soc/qualcomm/x1p42100: Add 806 MHz CPU clock definition
* e5c99fe9e0 Documentation: Add coreboot release 26.06 template
* 8791c5292d Documentation/releases: Update release notes for 26.03 release
* 1063e564e7 Documentation/vboot: Update list of vboot-enabled devices
* 8ff1a9a08c vc/tcg/opal: add OPAL packet builder for S3 unlock
* 30cd6efc29 util/amdfwtool: rename Faegan SoC to Krackan2e
* 1555a1a235 util/amdfwtool: rename Glinda SoC to Strix
* dc315c8f51 soc/amd/common/block/psp: Drop send_psp_command_smm
* 49f53bbb38 include/acpi/acpi_pld.h: Fix order of colour components
* e0bc32ce61 mb/google/brya: Add CFR-based storage selection for taeko/taniks
* db3e23d505 lib/fw_config: Add mainboard hook for selective probe override
* 225fd5e448 3rdparty/intel-microcode: Update to upstream main
* ac5722a66f 3rdparty/fsp: Update to upstream master
* 7bfad23a15 mb/google/bluey: Enable GBB_FLAG_ENABLE_ADB for development
* a649c82f7a security/vboot: Add option for enabling ADB via GBB flag
* 4943cfe4d0 soc/intel/pantherlake: Remove unsupported WCL CPU ID mappings
* 9a40f080ac security/tcg/opal_s3: add OPAL NVMe Security Send/Receive helpers
* 537f2acc67 vc/intel: add TCG storage core subset for OPAL S3
* fbd755341a security/tcg: add OPAL S3 unlock Kconfig
* 42a114e23f mb/google/nissa/var/teliks: Generate RAM ID for BWMYAX32P8A-32G
* a6b7fa5474 mb/google/brask/var/moxoe: Disable SAGV
* d74cf143fe mb/google/brask/var/kulnex: Disable SAGV
* 09d689561a soc/mediatek/common: dsi: Fix CPHY hfp_byte error check
* 674000732d drivers/intel/dtbt: Skip mailbox commands on downstream bridges
* b03b42285e soc/intel/{mtl,ptl}/fsp_params: Program PcieRpSlotImplemented
* e17cc395af soc/intel/alderlake/fsp_params: Drop !! in builtin root port check
* 11e9550e0c soc/intel/common/smm: Use cpu/x86 save_state ops
* ce1db1f54a cpu/x86/smm: reserve SMRAM for OPAL S3 state
* 9422dacdb8 mb/google/brask/var/moxoe: Remove weak symbols for memory config
* 53222f1ccb mb/google/brask/var/kulnex: Remove weak symbols for memory config
* 5bb8b30c03 nb/intel/haswell: Enable SA clock gating later
* a0be26ef5f nb/intel/haswell: Fix IOMMU early init
* 60994cf395 nb/intel/haswell/early_peg.c: Simplify implementation
* fed6f9494d nb/intel/haswell: Move early PEG stuff to separate file
* 76290e8cdc nb/intel/haswell: Move PEG device macros to header
* e7cfcec7a7 nb/intel/haswell: Use `report_cpu_info()` from CPU code
* f730ec6992 cpu/intel/haswell/report_cpu_info.c: Update CPUID info
* f249991e9d cpu/intel/haswell: Fix CPUID macros
* 96ab0c9942 nb/intel/broadwell: Move `report_cpu_info()` to CPU code
* 7c35218c88 nb/intel/broadwell/report_platform.c: Constify string array
* 4ea3450e45 nb/intel/broadwell: Use registers from Haswell
* 342d77a0dd nb/intel/broadwell: Rename `MCH_PAIR` to `INTRDIRCTL`
* 31f4c30a08 nb/intel/broadwell: Clean up cosmetics
* 53bc76856c nb/intel/broadwell/gma.c: Retype some variables
* 1172a4e6ee mb/google/brya/var/yavilla: Set LGD touchscreen HID address to 0x01
* 5c20d9ce76 3rdparty/amd_blobs: advance submodule pointer
* 817394f12c Makefile.mk: generate EDK2 update capsule
* bf037f3961 mb/emu/qemu-sbsa: Add GIC ITS and IORT for PCI MSI support
* e69bfef7c0 mb/emu/qemu-sbsa: Set io_port_mmio_base for PCI I/O port support
* dc7bf7e3f9 mb/google/bluey: Enable source mode on debug access port
* e9e4f7609c mb/google/bluey: Move QUP-GSI init/load to normal boot path
* 19e1b5c44b soc/mediatek/mt8196: Change dsi-phy1 & dsi-phy2 control method
* e6fb0faf7b soc/qualcomm/x1p42100: Skip redundant MMU toggling for QCLib
* deb510afeb cpu/x86/smm: add OPAL S3 CBMEM scratch
* 513899c3c8 vc/amd/opensil/phoenix_poc: Adjust headers from Genoa to Phoenix
* a616a589a2 vc/amd/opensil: Add Phoenix OpenSIL POC directory as a copy of Genoa
* 71effade58 mb/google/eve: Work around CLKREQ# timing erratum
* faf12bcacd soc/intel/skl: Allow disabling CLKREQ# independently of SrcClk
* 07e4cc0cc3 mb/google/fatcat: Set CPU ratio override in devicetree
* 94168f10bc Reland "mb/google/bluey: Configure GPIOs for USB camera"
* 975613717a mainboard/starlabs/starfighter: Convert SPD sources to JSON
* dda351b895 mainboard/starlabs/adl: Convert SPD sources to JSON
* 5202b1371d mainboard/starlabs/adl: Convert i5 SPD sources to JSON
* 2c9f1600e0 src/lib: Generate spd.hex from JSON at build time
* 9a8d22dcaa util/spd_tools: Improve spd_gen CLI for Make
* 3249ad1d7f mb/google/rex: Add SOF chip driver to screebo, kanix, karis
* 88eea9da6d vendorcode/amd/opensil/turin_poc: Pass microcode pointer to OpenSIL
* 39017d2257 amd/microcode: Add API to obtain address on microcode update block
* 6ce607eee4 mb/emu/qemu-sbsa: Add missing PCIe ACPI methods
* 5458b34de6 soc/intel/meteorlake: Use Arrow Lake FSP
* bd2c7443f3 soc/intel/ptl: Add ISCLK for controlling PCIe clock source
* 5e8cf41845 mb/google/bluey/mica: Add MAINBOARD_NO_USB_A_PORT configuration
* 2107e48c09 mb/google/nissa/var/telith: Generate RAM ID for BWMYAX32P8A-32G
* 1d17c9522f mb/google/trulo/var/kaladin: Add LGD touchscreen
* 4d9cb5336f mainboard/starlabs: drop display_native_res VBT toggle
* 9bb822dbf8 Update vboot submodule from 2024 to upstream main 2026
* 0be563503a mb/google/rauru: Support new bias IC TPS65130RGER
* 5d6061d0ba util/amdfwtool: add support for Strix Halo SoC
* 391d5f3cb4 mb/google/ocelot/var/ojal: Enable dtt and ish based on FW config
* df470521a7 mb/asus/p8x7x-series: Enable single PS/2 port role control
* a402a87405 mb/asus/p8z77-v_le_plus/cmos.layout: Extend checksummed area
* bbbc655b15 Revert "mb/google/bluey: Configure GPIOs for USB camera"
* fc312590d1 drivers/efi: Derive ESRT version from LOCALVERSION
* baae037f25 mb/google/bluey/mica: Add PS8820 re-timer configuration
* 40abf7946c mb/starlabs/adl/hz: Add missing cnvi_bt_core parameter
* 35dbfac13a mb/google/rex/var/karis: Add H58G56CK8BX146 to RAM ID table
* 4734da172b memlayout: Introduce PRERAM and POSTRAM TTB regions
* 0be9f20be4 soc/intel/pantherlake: Add icc_max settings for WCL SKU
* bf5aa04d8b soc/qc/common: Configure framebuffer as uncacheable
* ee3aef1c72 mb/google/bluey: Add AC unplug detection and charging status indication
* 0449fb45a6 mb/google/bluey: Refactor and secure low-power charging boot path
* b7ca29ba92 mb/google/bluey: Power off if charger applet fails to enable charging
* ddac3082ea mb/google/fatcat: Enable ChromeOS EC LED control for variants
* a1173d9bc1 mb/google/bluey: Enable ChromeEC LED control for Quartz and Mica
* eb5bdf06b9 soc/intel/pantherlake: Add power state thresholds for WCL
* bf6b14e4f7 mb/google/ocelot: Add VR_DOMAIN_IA for fast_vmode_i_trip
* 026bac6de7 arch/x86/ioapic: Add Kconfig option to keep pre-allocated IOAPIC ID
* d251282f2d Kconfig: move IOAPIC option to x86 Kconfig
* 1bdfc97c54 lib/cbfs: Enable LZ4 decompression in pre-RAM stages
* 1965a8740d mb/google/brox/var/caboc: Set LGD touchscreen HID address to 0x01
* 50ce94d715 Revert "soc/intel/pantherlake: Fix DDR5 channel mapping"
* ea58a467f1 Revert "soc/intel/pantherlake: Fill in SPD data on both channels of DDR5 memory"
* 92a430baee mb/google/fatcat/var/lapis: Modify parameters to reduce acoustic noise
* 4caf5ab903 soc/qualcomm/sc7280: Fix extended EDID read over I2C-over-AUX
* fd5f062446 mb/asus/p8x7x-series/*tree.cb: Consolidate gen1_dec into baseboard
* 6200d53e31 mb/google/bluey: Use LPASS GPIO configure API for Soundwire GPIOs
* 1d8c536d79 soc/qualcomm/x1p42100: Add API to configure LPASS GPIO
* 1e1b63c23b commonlib/device_tree: Utilize list_move() in dt_copy_subtree()
* 89048780c0 commonlib/list: Add list_move()
* 00e3b9989c lib: Rename devtree_update to mb_devtree_update
* b1194a838b mb/starlabs: Use common devtree_update mechanism
* 346a4ccaef mb/google/fatcat/moonstone: Add Samsung LPDDR5 memory parts
* fd6c0aa55b util/scripts: Add spd-decode for LPDDR5 SPD hex
* 2ac2df0eda sb/intel/wildcatpoint/pcie.c: Reorder some steps
* 59ac2cb2c0 sb/intel/wildcatpoint/pcie.c: Drop redundant write
* 44901340bf sb/intel/wildcatpoint/pcie.c: Ensure OBFF is disabled
* d74570b01e sb/intel/wildcatpoint/acpi: Use Lynx Point files
* 9541171de4 sb/intel/wildcatpoint/acpi: Move platform.asl to mainboards
* 762b564f3b mb/google/bluey: Add timeout for charging rail stabilization
* 61657cff8f spd/lp5: Add SPD for SK hynix H58G56DK9BX068
* 8aa0ea4062 soc/intel/pantherlake: Keep default values for TdcTimeWindow
* c97e740981 mb/google/ocelot: Fix fast_vmode_i_trip indexing in devicetree
* aaddb83491 soc/intel/pantherlake: Configure TDC IRMS mode for WCL IA domain
* f12d2997fc lib/cbfs: Don't include unused LZ4 code to shrink postcar stage
* c772a88b1d configs: Remove starbook/adl option table config
* dfc2c45ff4 util/inteltool: Add support for Wellsburg
* 23db1b3686 mb/google/bluey/mica: Add mainboard part number
* b5a703e5a0 mb/google/skywalker: Add mainboard_prepare_cr50_reset()
* 8a4937bf8f soc/mediatek: Add mtk_mipi_panel_poweroff()
* a300b135c3 soc/mediatek/mt8196: Call mtk_mmu_disable_l2c_sram via boot state
* 510e43d8bd soc/mediatek/mt8196: Move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C
* 2f88fec014 mb/google/bluey/mica: Add TPM I2C and EC SPI configuration
* 1b5df51c51 soc/intel: Fix Kconfig select order
* b52236fe9e soc/intel/pantherlake: Switch to common finalize implementation
* 5c56b9ff72 soc/intel/meteorlake: Switch to common finalize implementation
* ae932349bf soc/intel/common/block: Add common finalize implementation
* c9ba628d51 soc/intel/elkhartlake: Switch to common global reset implementation
* 73e89322ce soc/intel/jasperlake: Switch to common global reset implementation
* 0277c75bdd soc/intel/cannonlake: Switch to common global reset implementation
* 2ff987f906 soc/intel/tigerlake: Switch to common global reset implementation
* 0d4b934726 soc/intel/pantherlake: Switch to common global reset implementation
* 5c85dcda7f soc/intel/meteorlake: Switch to common global reset implementation
* b2a533c918 soc/intel/alderlake: Switch to common global reset implementation
* e4ea840114 soc/intel/common: Add common global reset implementation
* 7d8acb88c5 soc/intel/pantherlake: Switch to common PMC lockdown driver
* 4da2622964 soc/intel/meteorlake: Switch to common PMC lockdown driver
* 19fe81f08f soc/intel/alderlake: Switch to common PMC lockdown driver
* e160f3c506 soc/intel/common/feature: Add common PMC lockdown driver
* fec793e01d sb/intel/wildcatpoint/acpi: Add CID for GPIO device
* bacb55e348 nb/intel/broadwell/acpi.c: Use Haswell's file
* 3e89a234ef nb/intel/broadwell/acpi.c: Align with Haswell
* 958bc5cdff nb/intel/broadwell: Move `size_of_dnvs()` to southbridge
* 35694d2ea4 nb/intel/broadwell: Move device NVS to southbridge
* 3d4f2efcf7 nb/intel/broadwell/bootblock.c: Use Haswell's file
* 7240bbabe9 nb/intel/broadwell/acpi.c: Drop unneeded includes
* 4eb0fd7bea nb/intel/broadwell: Move PCH headers to wildcatpoint
* 0bc5746188 soc/intel/broadwell: Move to nb/intel/broadwell
* d740cee2d9 soc/intel/broadwell/pch: Move to sb/intel/wildcatpoint
* 0d2a0512fd sb/intel/lynxpoint: Configure IOSF Port and Grant Count
* 8b69dcccb2 sb/intel/lynxpoint/pcie.c: Add additional disable steps
* 381ce51ec4 sb/intel/lynxpoint/acpi: Add HIDs for Wildcat Point
* 6953c591ba sb/intel/lynxpoint/acpi/serialio.asl: Add more _PS0/_PS3 methods
* 0e9c2f53b0 haswell/broadwell: Move CPU bus ops to CPU code
* e0715bc0f9 soc/intel/pantherlake: Disable PCIe PM in compliance test mode
* bce8d28a59 MAINTAINERS: Add Nicholas Chin for autoport
* b6ebb24a48 util/spd_tools/src/spd_gen/lp5.go: Support LP5X 9600Mbps
* 13bf2d9566 mb/google/fatcat: Enable C1 and package C-state auto-demotion
* 56e645d942 mb/google/fatcat: Change Gen4 and Gen5 NVMe power sequence
* 8998999eb3 Haswell NRI: Add dumping of CAPID registers
* 343f439801 util/inteltool: set amb registers dumping error print to stdout
* 26006cc217 util/ifdtool: show overlapping region name and range details
* 93444a0ce0 mb/emul/qemu-[q35,i440fx]: Create ICQR interrupt resource locally and use defined offset
* 036af49b1d mb/emul/qemu-q35: Add a _DIS method for gsi_link devices
* f5c9c1c166 mb/google/bluey: Move ADSP QUP-I2C init to normal boot path
* 61c69ebfa8 mb/starlabs: Drop PCIe detect-timeout/hotplug workarounds
* baadfed999 mb/starlabs/adl: Add NVMe power sequencing
* 49a5b949ca mb/starlabs/starbook: Add NVMe/WiFi power sequencing
* 279406cd14 mb/starlabs/starfighter: Add NVMe port power sequence
* 0306eb0723 mb/starlabs/common: add NVMe power sequencing helper
* cfbf8f3953 starlabs: drop CMOS option tables
* 9dac2b9e53 ec/starlabs/merlin: persist settings via EFI options
* 3fa3818e41 starlabs: add ACPI SMI bridge for EFI options
* 484e39c068 mp_init: Pass microcode size to MPinit
* ea1a722d2b soc/intel/xeon_sp: Move microcode loading
* 08e3ad9e03 mb/google/brox/var/juchi: Add 2 memory parts and generate DRAM IDs
* ba6de6c866 mb/google/fatcat/var/ruby: Set ISH GP1 gpio pin to NC
* fb2e8b5e1e mainboard/google/bluey: Enable charging debug access in common path
* ca9b46d341 soc/mediatek: Add common low battery poweroff handling
* c222118cbf soc/qualcomm/x1p42100: Remove redundant VBUS enablement logic
* 2c58402339 soc/qualcomm/x1p42100: Configure OTG buck for USB host
* 10f0a87824 soc/qualcomm/sc7280: Update console message type non-fatal
* 270e84e59f vc/chromeos: Provide inline fallbacks for Chromebook Plus branding
* fe506bfe84 ec/google/chromeec: Add Kconfig for AP-controlled LED sync
* 12710eafff mb/google/bluey: Implement off-mode charging applet
* a1dd5f05b0 ec/google/chromeec: Add interface for offmode heartbeat command
* 125d9c8643 soc/qualcomm/x1p42100: Add logic for secure boot blob paths
* 6de3d04c4e Kconfig: Add Kconfig for signed secure blobs
* 0a6142dfbe soc/amd/turin_poc: Add SPI TPM SoC-specific initialization
* dde872911a mainboard/starlabs: drop unused TJ_MAX option
* 724176a218 mainboard/starlabs: namespace PL4 powercap setting
* 5156ec4533 mainboard/starlabs/adl: move SSDT hook to variant
* ffad2454c4 mainboard/starlabs/adl: drop redundant ASPM CFR guard
* 14fcb3baf8 mainboard/starlabs/adl: move CFR callbacks to variant
* 7f02993393 mainboard/starlabs: move starlite under adl/
* e02dc13b87 mainboard/starlabs: move Byte under adl/
* 3ea94fb2dc mb/starlabs/starfighter: Enable the card reader
* 56f588eec6 mb/starlabs/*: Don't consider fan presence for default power profile
* 19df8826d7 mb/starlabs/starlite_adl: Disable the card reader by default
* c940d20696 soc/intel: Consolidate common code macro definitions in pci_devs.h
* d03957e10f soc/intel/tigerlake: Use common PCH client SMI handler
* 402da237bc soc/intel/pantherlake: Use common PCH client SMI handler
* eb205e379a soc/intel/meteorlake: Use common PCH client SMI handler
* f0021f84ec soc/intel/alderlake: Use common PCH client SMI handler
* 4b73479c38 soc/intel/common/feature/smihandler: Add common PCH client SMI handler
* 2eb37453e5 soc/intel/meteorlake: Use common pmutil driver
* f0be882d9f soc/intel/pantherlake: Use common pmutil driver
* 2b70ce3fbf soc/intel/alderlake: Use common pmutil driver
* cc31cc0ab2 soc/intel/common/feature/pmutil: Add common pmutil driver
* 189f8d1a86 soc/intel/elkhartlake: Switch to common eSPI/LPC initialization
* aeb9db4467 soc/intel/jasperlake: Switch to common eSPI/LPC initialization
* 05006995b6 soc/intel/tigerlake: Switch to common eSPI/LPC initialization
* 7278030fa6 soc/intel/pantherlake: Switch to common eSPI/LPC initialization
* 4fe7e7fa36 soc/intel/meteorlake: Switch to common eSPI/LPC initialization
* 34be3842a1 soc/intel/alderlake: Switch to common eSPI/LPC initialization
* 0464f1032a soc/intel/common/feature/espi: Add common eSPI/LPC initialization
* f780b7c576 soc/intel/tigerlake: Use common SoundWire driver
* 620a33f1c8 soc/intel/pantherlake: Use common SoundWire driver
* ffc67b2938 soc/intel/meteorlake: Use common SoundWire driver
* ef364d623d soc/intel/alderlake: Use common SoundWire driver
* 74d4fac210 soc/intel/common/feature/soundwire: Add common SoundWire driver
* 7bee4f5efb mb/starlabs: Drop explicit devtree_update calls
* f8494fbeae lib: Add devtree_update bootstate hook
* 69242d5bb1 drivers/usb/acpi: Add DSM function 3 support for Intel Bluetooth
* 50e92c9cf1 mb/lenovo/m920q: Rename to reflect use for m720q variant as well
* e0c26a05d4 ec/starlabs/merlin: fix OSFG suspend comment
* ce5c915344 drivers/spi/flashconsole.c: Fix flashconsole
* c2eea0c96c mainboard/starlabs/adl: add Bluetooth RTD3 CFR option
* 7847a54eed mb/lenovo: Convert PNP device to generic device
* 091ae533b9 mb/lenovo/t430: Merge into t430 into t530
* 3a5e4660bb mb/lenovo/t530: Unify GEN_DEC entries
* 416875e93e mb/lenovo/t430|t530: Reduces differences in code
* 57f96b83fe mb/google/link/hda_verb: Remove presence detect flag from internal sources
* 6be9ee7ce4 mb/google/link: Use AZALIA_PIN_DESC macros for pin widgets
* 8718db133a mb/google/fatcat/var/lapis: Add 2 Micron modules to RAM id table
* f9f43d862d spd/lp5: Add Micron memory part
* c57b88d74d mb/google/brox/var/lotso: delete mb_get_channel_disable_mask
* 8ba58ef800 mb/samsung/lumpy: Correct NID 0x08 HDA pin config macro usage
* 38988a727e util/mediatek: Reduce non-boot related BROM settings
* e84415b8f8 mb/google/nissa/var/yaviks: Add micron memory to RAM ID table
* 08dcaf404c mb/google/nissa/var/yavilla: Add micron memory to RAM ID table
* 523242b2b9 google/bluey: Add RW_CDT region to flash map
* 5e46ac1364 mb/google/bluey: Resize WP_RO and add RW_UNUSED region
* 08f2f3a21b Haswell NRI: Implement 1D margin training
* 098a5cf16e mb/google/ocelot: Configure CDCLK frequency for display
* 7b205808e4 mb/google/rauru: Disable CHROMEOS_USE_EC_WATCHDOG_FLAG
* b1e8f87b30 mb/google/rauru: Enable MEDIATEK_WDT_RESET_BY_SW
* f4825e5c12 soc/amd/common: Add I3C driver
* cf5d6f1c88 soc/intel/common/block/gspi: Simplify Makefile using all-$()
* 56ede20f10 soc/intel/pantherlake: Use common SPI device function driver
* 4bdeb73635 soc/intel/meteorlake: Use common SPI device function driver
* 8ecff12528 soc/intel/alderlake: Use common SPI device function driver
* 0aea05411d soc/intel/tigerlake: Use common SPI device function driver
* 47f3e7e3cc soc/intel/jasperlake: Use common SPI device function driver
* 91520ab096 soc/intel/common/feature/spi: Add common SPI device function driver
* 0668959a92 soc/intel/skylake: Use common GSPI devfn mapping
* 45d3ab84a8 soc/intel/cannonlake: Use common GSPI devfn mapping
* 4aae5fb66d soc/intel/elkhartlake: Use common GSPI devfn mapping
* 78ef2d0433 soc/intel/jasperlake: Use common GSPI devfn mapping
* 66a6c25ef8 soc/intel/tigerlake: Use common GSPI devfn mapping
* 3c92c8402a soc/intel/pantherlake: Use common GSPI devfn mapping
* 6459039b76 soc/intel/meteorlake: Use common GSPI devfn mapping
* 039f21b5e3 soc/intel/alderlake: Use common GSPI devfn mapping
* a4bc3131a5 soc/intel/common/feature/gspi: Add common devfn mapping
* 253689aebb sb/intel/lynxpoint/acpi/xhci.asl: Guard PCH-LP methods
* 72ecebf0c3 soc/intel/broadwell/acpi/xhci.asl: Use macros for constants
* 813edbbde8 sb/intel/lynxpoint/acpi/xhci.asl: Use macros for constants
* 3cde265c28 sb/intel/lynxpoint/acpi/xhci.asl: Drop redundant writes
* a59ddda11e Doc/mb/protectli/fw6: describe revisions and more variants
* d5161611a4 soc/intel/pantherlake: Use common I2C devfn mapping
* 78e36f8c78 soc/intel/meteorlake: Use common I2C devfn mapping
* f703f2800c soc/intel/skylake: Use common I2C devfn mapping
* 7f922438be soc/intel/cannonlake: Use common I2C devfn mapping
* a0ba812a09 soc/intel/jasperlake: Use common I2C devfn mapping
* 83325f354b soc/intel/tigerlake: Use common I2C devfn mapping
* fe728d62c9 soc/intel/elkhartlake: Use common I2C devfn mapping
* 749bae2f94 soc/intel/alderlake: Use common I2C devfn mapping
* b21e861ab5 soc/intel/common/feature/i2c: Add common devfn mapping
* 34c156427d soc/intel/common/block/lpc: Fix AMASK decoding in window detection
* b50c219557 soc/intel: Use centralized emergency battery shutdown hook
* a96f1a464b mb/google/bluey: Use common platform hook for emergency shutdown
* 5c44e689ee vc/google/chromeos: Add platform hook for emergency battery shutdown
* 086d3a3232 mb/google/fatcat: Enable ChromeOS EC LEDs in romstage
* 2a821d8db6 mb/google/bluey: Early enablement of lightbar
* d39f406f55 mb/google/bluey: Disable lightbar during low-power charging boot
* b68ba24244 ec/google/chromeec: Add API to turn on lightbar
* 5f9a1ad962 ec/google/chromeec: Add API to turn off lightbar
* 4028996c9d mb/google/nissa/var/pujjoquince: Add support for Micron MT62F1G32D2DS-031RF
* 800db242bd {soc,sb}/intel: Drop named object from ASL `GPLD` method
* 57e30e6b9d mb/google/brask/var/moxoe: Switch memory to DDR5
* c069dc3eb1 mb/google/fatcat/var/ruby: Add settings for resolving EE noise
* 5ac3e40282 mb/google/brox/var/caboc: Probe LGD touchscreen by fw_config
* 61ce86ea3e mb/siemens/mc_ehl6: Reduce clock rate for I2C1
* acd8f42410 soc/intel/skylake: Use common UART device list driver
* a69d537e61 soc/intel/cannonlake: Use common UART device list driver
* e31d32443e Revert "mb/google/fatcat: Fix Gen4 SSD power sequencing"
* 7b4fb78e34 soc/intel/elkhartlake: Use common UART device list driver
* bb95093b8f soc/intel/jasperlake: Use common UART device list driver
* 61dc1e04e0 soc/intel/tigerlake: Use common UART device list driver
* 38baf0c5f6 soc/intel/meteorlake: Use common UART device list driver
* 44fcbf84b3 soc/intel/snowridge: Move defines to soc/pci_devs.h
* dfcd63370d cpu/intel: Use existing defines for MTRR_CAP_MSR
* fd2cdf206d cpu/intel/smm/gen1: Optimize cpu_has_alternative_smrr
* f96644e774 nb/intel/haswell: Do not print ME status twice
* d9bc4740da nb/intel/haswell: Fix DDR frequency reporting
* 6a1b016184 nb/intel/haswell: Tidy up memory info prints
* f89ac4e6ce soc/mediatek/common: Adjust splash logo bottom margin
* f01e11ac5c vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP headers to version WCL.3515.03
* 326e33b82d soc/intel/pantherlake: Use common UART device list driver
* 3337e56b50 soc/intel/alderlake: Use common UART device list driver
* bb941824ca soc/intel/common/feature/uart: Add common UART device list driver
* 78295974f8 soc/intel/common: Add feature directory for SoC-specific common code
* f691421daf soc/intel/common: Replace CFR enums with booleans
* 24870f54e0 soc/intel/skylake: Replace CFR enums with booleans
* 666e66800c soc/intel/tigerlake: Replace CFR enums with booleans
* 12f99ab067 soc/intel/alderlake: Replace CFR enums with booleans
* 47bc0a727c soc/intel/jasperlake: Replace CFR enums with booleans
* 1b0147f05b soc/intel/meteorlake: Replace CFR enums with booleans
* b935d5b058 soc/intel/cannonlake: Replace CFR enums with booleans
* daa32be457 soc/intel/apollolake: Replace CFR enums with booleans
* 90f9d9e7c6 mb/google/poppy: Replace CFR enums with booleans
* 6b481c73dd mb/google/hatch: Replace CFR enums with booleans
* 9a58dc7fee mb/google/auron: Replace CFR enums with booleans
* e7c05d666c mb/google/volteer: Replace CFR enums with booleans
* 71b7167396 mb/lenovo/sklkbl_thinkpad: Replace CFR enums with booleans
* ed10b36edf ec/google/chromeec: Replace CFR enums with booleans
* d19e5d2550 ec/lenovo/pmh7: Replace CFR enums with booleans
* 0ff3c3d2ec ec/lenovo/h8: Replace CFR enums with booleans
* f9f81e4839 mb/lenovo/x220: Replace CFR enums with booleans
* 7e8850a862 mb/google/*/cfr.c: Drop initial empty line
* 220669643b soc/qualcomm: Add Kconfig to skip redundant MMU toggling
* c9578eac24 mb/google/ocelot: Add THC-SPI Touchscreen support in fw_config
* d88e98cf49 mb/google/fatcat/lapis: Remove RTD3 config for SSD
* 24866fefef mb/google/fatcat/var/lapis: Add UFSC bit of new FP MCU
* 33d873324e mb/lenovo/*: Drop unused ACPI code
* 571dbbe345 mb/lenovo/t430: Move TPM in devicetree.cb
* 06446dd0ac dram/ddr3: Add speed in MT/s
* bf148cae0a lib/dimm_info_util.c: Handle 16-bit memory bus extension for ECC
* a3923d678f ec/starlabs/merlin: fix ITE CMOS index mapping
* e47952c3a7 mb/asus/p8x7x-series: Enable common SIO ASL code
* e82ecc739d sio/nuvoton/nct6776: Switch to common init code
* e72a325c40 sio/nuvoton/nct{5535,6779}d: Use new common init code
* 65c4ea0bfb superio/acpi/pnp_kbc.asl: Allow changing device and PNP IDs
* 2de0c9575d sio/nuvoton/nct6776: Switch to common Nuvoton ASL code
* 94a356e0c8 sio/nuvoton/nct5535d: Use common ASL code
* 4cee52e457 sio/nuvoton/nct6791d: Enable common ASL code
* c30802d6fb sio/nuvoton/nct6779d: Enable common ASL code
* 7876bcaa86 sio/nuvoton: Implement common ramstage keyboard/ACPI init routines
* afeca9f422 mb/starlabs: disable TCO INTRUDER# SMI by default
* c996684f40 intel/smm: make TCO INTRUDER# SMI optional
* 339ef9b5c9 soc/intel/common/block/lpc: Improve automatic window opening
* f1e4de7fbf mb/google/dedede/var/galtic: Add fw_config option for touchpad type
* 08b05f56a6 Revert "mb/google/dedede/galtic: Add CFR option for touchpad type"
* ed5a993f0f mb/google/fatcat/lapis: Enable eSOL feature

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-23 21:33:31 +01:00
Leah Rowe 9b01115c5a dell-flash-unlock: fix errno handling
and remove pedantic flags in makefile

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-22 03:38:30 +01:00
Leah Rowe a64cdaa300 nvmutil: remove pedantic flag
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-22 03:33:33 +01:00
Leah Rowe c4e8c4fa25 spkmodem-recv: remove pedantic flag
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-22 03:33:03 +01:00
Leah Rowe 46574146f5 spkmodem-recv: remove buggy errno usage
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-22 03:32:46 +01:00
Leah Rowe 3b7ac395f4 nvmutil: fix cast
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-22 03:17:14 +01:00
Leah Rowe d6658eb062 util/nvmutil: fix errno zero on exit return
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-22 03:15:41 +01:00
Leah Rowe 40cb95b15e nvmutil: fix bad return status on error
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-22 02:54:00 +01:00
Leah Rowe 4bf88a8081 nvmutil: use uintptr for gbe. check regular file.
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-22 02:53:15 +01:00
Leah Rowe 48e949263b switch spkmodem_decode back to spkmodem_recv
this version is more tested. i'll merge _decode back
once it's better tested. it contains a lot of invasive
changes, whereas recv is much closer to the original GNU
code that i inherited, that i also know works quite well.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 19:11:45 +01:00
Leah Rowe 7b5349e85d disable lbutils on non-linux systems
i should probably test musl as well, on linux

libreboot-utils is stable on the glibc systems i tested
with linux. it is quite buggy on bsd systems.

it's irresponsible to let users compile this until i've
properly tested the code. putting this error in for now.

i made lbmk use the old nvmutil version for now, and retro
fitted several improvements to i/o there from lbutils,
changes that i know are stable on bsd.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 19:05:26 +01:00
Leah Rowe b947150f8a nvmutil: don't rely on errno for errors
adapted from the changes made in lbutils

i'm just patching this crappy code. lbutils doesn't
work properly on openbsd yet, and i just want nvmutil
to work properly there, so i'm using the old code for
now, on openbsd.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 19:02:29 +01:00
Leah Rowe 4bf96fbc1e nvmutil-standalone: add eintr safety
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 17:38:31 +01:00
Leah Rowe dec63fc274 add gitignore
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 17:03:18 +01:00
Leah Rowe 2d33754a5c fix make file
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 13:54:01 +01:00
Leah Rowe 6d3341c637 nope. use nvmutil from libreboot 26.01
guaranteed not to break on openbsd (tm)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 13:50:54 +01:00
Leah Rowe b1b1d2cf0c remove pledge in nvmutil
don't fix it for now. this version was buggy.

i'm only using nvmutil for now, until i properly
fix all the memory issues in lbutils on openbsd.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 13:48:27 +01:00
Leah Rowe 6f9f0f7321 fix nvmutil Makefile for openbsd
same fix i did for lbutils

the nvmutil version is the same one used before
lbutils was introduced. just before.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 13:44:36 +01:00
Leah Rowe 7f4f07fc40 use old nvmutil for now, in lbmk
i'm trying to make nvmutil work on openbsd. the new code
in lbutils is a bit buggy, likely somewhere in mkhtemp.
i'm still debugging it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 13:39:29 +01:00
Leah Rowe 4b5aca8ff8 now mkhtemp works on openbsd!
yay

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 06:42:08 +01:00
Leah Rowe e097eb5483 lbutils: don't use stack memory for path strings
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 06:39:50 +01:00
Leah Rowe 7faf014a84 further makefile cleanup in lbutils
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 06:09:08 +01:00
Leah Rowe 0205c0e6b0 lbutils: remove xpledge/xunveil, just call them direct
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 05:54:50 +01:00
Leah Rowe 7ff5d925bf fix bsd
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 05:49:32 +01:00
Leah Rowe 59fefd9c57 tidy up lbutils makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-21 05:47:25 +01:00
Leah Rowe 7619bfed65 lbutils/mkhtemp: correct return value check
check if above or equal to zero, except where
counterindicated. this is the usual way on unix,
where a command returns -1 on error, or above/equal
to zero on success.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-10 22:59:08 +01:00
Leah Rowe 9dab2ffa29 lbutils/mkhtemp: use openat_on_eintr
missing EINTR handling fixed

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-10 22:59:08 +01:00
Leah Rowe f055809c17 lbutils/file: only override EEXIST if not set
in the linux fast path, we are universally overriding
errno with EEXIST, which pollutes errno in case of
debugging under fault condition. this is inconsistent
with posix and also leah.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-10 22:59:08 +01:00
Leah Rowe fc3c7b9c3e lbutils/file: tidy up mkhtemp_tmpfile_linux
make failure more obvious. no behavioural change.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-10 22:59:08 +01:00
Leah Rowe 7eecc42b92 Merge pull request 'supermicro x11ssh_f: Enable SATA hotplug' (#419) from noisytoot/supermicro-x11ssh-f-sata-hotplug into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/419
2026-04-10 23:57:20 +02:00
Ron Nazarov 4a7feba7cd supermicro x11ssh_f: Enable SATA hotplug
See the commit message in the patch:

Before this patch, hotplugging only worked to replace drives (if you
tried to plug a drive into a SATA port that no drive was plugged in to
at boot, it wouldn't be detected) and you'd have to manually rescan
the bus (echo "- - -" > /sys/class/scsi_host/host*/scan) to make
plugs/unplugs get detected by the operating system.

Now, hotplugging works for all ports (tested and working on Supermicro
X11SSH-LN4F) and there's no need to manually rescan (it sometimes
takes a few seconds for unplugs to be detected, but plugs are detected
instantly).

Also submitted upstream as https://review.coreboot.org/c/coreboot/+/91824
2026-04-10 20:21:53 +01:00
Leah Rowe 63ec707698 lbutils/file: ignore close err if errno is EINTR
but DONT LOOP IT. see comment.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 21:05:08 +01:00
Leah Rowe 2d69d45e26 remove dead code
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 20:36:05 +01:00
Leah Rowe 6b67e12428 lbutils/file: don't eintr loop fcntl
not indicated. the way we use it is basically like
stat, to check that a file exists / is a file.

just err the fuck out

nuance: SETLK is non-blocking (no wait).
we should loop on SETLKW, but we don't use that.
in this codebase, we use SETLK for locking a
tmpfile, but because of race conditions and
wanting to make another file quickly, we just
try again with a newly generated name, with a
certain number of retries, so we justt use SETLK

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 20:17:26 +01:00
Leah Rowe a6d2de4e88 libreboot-utils: don't loop lseek on EINTR
not necessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 19:17:32 +01:00
Leah Rowe d12ca7fd8e lbutils/file: don't use undefined USE_OPENAT
clang -Weverything told me to

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 19:09:26 +01:00
Leah Rowe 736a2504bb lbutils/file: don't loop EINTR on close()
state is undefined after EINTR. just abort universally.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 17:43:43 +01:00
Leah Rowe 249ae57c29 lbutils/file: fix implicit conversion on openat2
as dictated by clang -Weverything

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 17:33:01 +01:00
Leah Rowe c48a962eaf lbutils/file: fix overflow check
clang -Weverything:

lib/file.c:165:49: warning: implicit conversion changes signedness: 'ssize_t' (aka 'long') to 'size_t' (aka 'unsigned long') [-Wsign-conversion]
  165 |                 if (if_err(rval >= 0 && (size_t)rval > (nrw - rc), EOVERFLOW))

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 17:29:28 +01:00
Leah Rowe 3d24aa98f9 lbutils: remove more unused macros
detected via clang -Weverything

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 16:50:50 +01:00
Leah Rowe ae5e74554a lbutils/file: remove unused macro
not needed here (detected with clang -Weverything)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 16:49:19 +01:00
Leah Rowe fb81b7b736 lbutils/file: rename rw_file_exact
call it rw_exact, so that it's closer to
the name rw. it matches naming more closely;
the alternative was to call rw rw_file

but read/write can handle more than just files!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 16:20:12 +01:00
Leah Rowe f68cedf202 libreboot-utils/file: never retry file rw on zero
even with a timer, it's possible that on a buggy system,
we may keep writing even though the outcome is zero. if
a system comes back with zero bytes written, that is a
fatal bug and we should stop.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 16:19:46 +01:00
Leah Rowe 5b465d3af6 lbutils: remove -Werror
the actual warn flags are still there.

leaving Werror in production is ill advised.

i can (and will) still fix build errors as
i see them.

as a result of this, i now also see more info
when i type:

make strict

(this uses clang with -Weverything)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 15:02:52 +01:00
Leah Rowe 9dc141bafa lbutils/rand: close fd on urandom error
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 14:35:24 +01:00
Leah Rowe a879114734 lbutils: remove rw on_eintr functions. just use rw
rw is enough. i unified everything there.

next commit will remove rw_type and instead
run positional i/o depending on whether the
offset is zero. i'm simplifying the API a lot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 14:29:39 +01:00
Leah Rowe 229a283604 lbutils: portable options in Makefile
add options for building with urandom+openat and
arc4+openat. useful for emulating a bsd / old linux
environment in modern linux distros, for portability
testing.

these options are not recommended for everyday use.
just use make without any special options, and the
code has build-time OS detection for features like
randomisation/openat2.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 13:03:30 +01:00
Leah Rowe 4e72555ac7 lbutils: support using arc4random on linux
-DUSE_ARC4=1

use that

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 12:44:38 +01:00
Leah Rowe 44004191cb lbutils: don't set USE_OPENAT and USE_URANDOM
these can be set explicitly in the compiler flags,
e.g.

make CC="cc -DUSE_OPENAT=1 -DUSE_URANDOM=1"

these options, if set to 1, will cause you to use
the code as if it were running on non-linux systems
such as openbsd. of course, some differences will
still exist, but this is useful for portability
testing when compiling on linux.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 12:30:55 +01:00
Leah Rowe 2c40ad7816 lbutils: only use GNU SOURCE for syscall
and remove manual prototypes; fchmod, realpath
and so on rely on the _XOPEN_SOURCE macro.

the POSIX macro wasn't needed: _XOPEN_SOURCE
is sufficient.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 11:52:53 +01:00
Leah Rowe 716140b80f libreboot-utils: don't use the GNU SOURCE macro
use the POSIX one

declare prototypes where necessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 11:00:58 +01:00
Leah Rowe b7b34413e7 libreboot-utils: fix clang hell mode
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 10:23:48 +01:00
Leah Rowe d100ea1d2f libreboot-utils: always use strict cc flags
otherwise, i will end up with a mess like the
one i recently fixed.

we always want to use correct C. the current
spec is set to c99, with -pedantic turned on.

flags now:

-Os -Wall -Wextra -std=c99 -pedantic -Werror

if you do: make hell, you get (uses clang):
-Os -Wall -Wextra -std=c99 -pedantic -Werror -Weverything

i initially loosened up the Makefile rules, so
that the code would be more "portable", but
every compiler worth caring about has these
flags, and turning them on is advisable,
especially pedantic and -std, because you want
to have some guarantee that the compiler is
generating correct code; if the standard is
left ambiguous, you could be introducing subtle
bugs when people compile it, because who knows
what spec the compiler is using?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 10:11:30 +01:00
Leah Rowe 861f56375a libreboot-utils: fix ALL compiler warnings
i wasn't using strict mode enough in make:

make strict

now it compiles cleanly. mostly removing
unused variables, fixing implicit conversions,
etc.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 10:03:41 +01:00
Leah Rowe d91dd0ad81 fix coreboot/fam15h build error on arch
In file included from /home/user/lbmk/src/coreboot/fam15h/util/cbfstool/partitioned_file.h:19,
                 from /home/user/lbmk/src/coreboot/fam15h/util/cbfstool/partitioned_file.c:16:
/home/user/lbmk/src/coreboot/fam15h/util/cbfstool/common.h:34:16: error: expected ‘)’ before ‘__attribute__’
   34 | #define unused __attribute__((unused))
      |                ^~~~~~~~~~~~~
In file included from /home/user/lbmk/src/coreboot/fam15h/util/cbfstool/common.h:25:
/home/user/lbmk/src/coreboot/fam15h/src/commonlib/include/commonlib/helpers.h:137:40: error: expected identifier or ‘(’ before ‘)’ token
  137 | #define __unused __attribute__((unused))

^ this removes that error

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 08:25:54 +01:00
Leah Rowe 9cd86eb584 coreboot/default: fix vboot build error on arch
or any newer linux really.

new gcc is much stricter about const chars.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 08:13:56 +01:00
Leah Rowe e9a975b1f7 fix u-boot builds on arch linux
gnu changed a flag for like, no fucking reason

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 07:42:32 +01:00
Leah Rowe df5bb1c894 libreboot-utils: loop fcntl on eintr
but i can't write a generic function for this,
because fcntl is a variadic function, so wrapping
cannot be done cleanly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 06:17:25 +01:00
Leah Rowe f90af15502 safer macro
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-04-01 06:10:57 +01:00
Leah Rowe e731893208 util/nvmutil: call usage if argc below 3
otherwise, we invoke the state machine in weird
conditions, where some pointers may not be initialised.

we could handle this properly, but why?

therefore, the errhook is called after the argc
check.

this patch fixes a Speicherzugriffsfehler that
i got while running nvmutil with below 3 arguments

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-31 17:54:48 +01:00
Leah Rowe d2abde5303 libreboot-utils: stricter errno handling
where possible, try not to clobber sys errno. override
it only when relatively safe.

also: when a syscall succeeds, it may set errno. this
is rare, but permitted (nothing specified against it
in specs, and the specs say that errno is undefined
on success).

i'm not libc, but i'm wrapping around it, so i need
to be careful in how i handle the errno value.

also:

i removed the requirement for directories to be
executable, in mkhtemp.c, because this isn't required
and will only break certain setups.

in world_writeable and sticky, i made the checks stricter:
the faccessat check was being skipped on some paths, so
i've closed that loophole now.

i also generally cleaned up some code, as part of the errno
handling refactoring, where it made sense to do so, plus a
few other bits of code cleanup.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-31 17:49:23 +01:00
Leah Rowe c0fd88155a lbutils/rand: add missing error handle
accidentally removed in previous refactor

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-31 14:14:44 +01:00
Leah Rowe 6d9f162f5b lbutils/file: only support real pread/pwrite
the portable version was written for fun, but
it's bloat, and makes the code hard to read.

every unix since about 2005 has these functions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-31 12:22:42 +01:00
Leah Rowe a769537554 lbutils/file: don't alllow EAGAIN/EWOULDBLOCK
a non-blocking file descriptor could be used while
errno is set to these. this would create an infinite
loop. it's better that we only allow EINTR.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-31 12:06:33 +01:00
Leah Rowe bca09eebf3 lbutils/file: remove ETXTBSY from exemption on io
obsolete. ripe for abuse. do not permit this error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-31 12:04:37 +01:00
Leah Rowe 277c0c8e87 lbutils/file: don't reset errno on successful io
some io syscalls may set errno on success. this patch
honours that. we try to preserve caller errno, but it
is important for debugging not to clobber it.

if fs_err_retry errs, then we don't reset errno.
if fs_err is successful but errno wasn't set, we
restore caller errno. this is done by setting errno
to zero in callers, which also restore caller errno.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-31 12:03:46 +01:00
Leah Rowe aacf9fb6c9 libreboot-utils: unified EINTR loop handling
absolutely unified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-31 11:45:21 +01:00
Leah Rowe f2dd830c7b TODO
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-31 07:47:15 +01:00
Leah Rowe 2f7623ff06 libreboot-utils: unified max path lengths
just use PATH_MAX like a normal person

with additional safety

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-31 07:42:40 +01:00
Leah Rowe fb5f1b4ed1 correct exit status
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-30 07:12:25 +01:00
Leah Rowe 9400f4ea0b be reasonable
8GB of entropy is a tad extreme

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-30 07:04:26 +01:00
Leah Rowe da20b75bea libreboot-utils: more flexible string usage
i previously used error status and set return values
indirectly. i still do that, but where possible, i
also now return the real value.

this is because these string functions can no longer
return with error status; on error, they all abort.
this forces the program maintainer to keep their code
reliable, and removes the need to check the error status
after using syscalls, because these libc wrappers mitigate
that and make use of libc for you, including errors.

this is part of a general effort to promote safe use
of the C programming language, especially in libreboot!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-30 06:25:52 +01:00
Leah Rowe b96708bd3a lbutils: strict string functions - abort on err
on the conditions where these functions encounter
an unexpected error, we currently return -1

this means that the caller must check. which means
the caller won't check. nobody does. i often forget.

force the caller (me) to be correct, instead.

the current calling convention is that the real
return value is stored in a pointer, provided inside
the function signature, on a given string function,
and the function's return value is merely an indicator.

this calling convention is retained for now; the next
patch will change it, such that the real value is also
the function's return value. this is more flexible.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-30 03:03:14 +01:00
Leah Rowe 9d4302deb2 libreboot-utils: optimised string functions
operate per word, not per byte

this is also done on sdup, which uses a slightly
inefficient method: the new string allocation is
that of the maximum size, rather than what we
need. for example, if you wanted a 20 character
string (21 including null), you would still allocate
4096 bytes if that was the maximum length.

it's a bit naughty, and i have half a mind to
keep sdup on the old implementation, but i'll leave
it be for now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-30 01:53:17 +01:00
Leah Rowe 7fb0b2f692 libreboot-utils: safe memcmp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 23:55:38 +01:00
Leah Rowe 01aa95ec15 Revert "lbmk: use mkhtemp in libreboot's build system"
This reverts commit e54862fccc.

nope. not ready yet. will fix it later.
2026-03-29 16:25:41 +01:00
Leah Rowe e54862fccc lbmk: use mkhtemp in libreboot's build system
i added a fake -t option, which doesn't actually
read optarg, so that -t usage can just override
the normal template. mkhtemp isn't ready for
distros yet, but it's ready for lbmk.

i hacked the makefile to also copy the binary to
mktemp, and i set PATH in lbmk so that this binary
is used insttead of the one on your system.

that way, upstream projects use it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 16:08:00 +01:00
Leah Rowe 8657d084d2 util/nvmutil: re-add cleanup
delete tmpfiles after operation. fixes a bug where
tmpfiles are left behind after running the dump
command.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 14:37:51 +01:00
Leah Rowe e4016eb32c lbutils hexdump: reduce width on smaller integers
showing the size for 64-bit high integers seems silly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 14:26:56 +01:00
Leah Rowe ac04a5f50a libreboot-utils/lib: loop eintr on [p]read/[p]write
i forgot to do this!

with this, I/O should be bullet proof now.
i already loop this on other I/O commands.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 14:15:34 +01:00
Leah Rowe a56903a7b0 mkhtemp: rename variable for clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 13:53:55 +01:00
Leah Rowe b70ee41c5c hexdump performance test, part 1
spoiler alert: it's slow as molasses

part 2 will be presented at a later date

(yes, please don't fill 8GB of memory with
random data and hexdump it)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 13:42:37 +01:00
Leah Rowe cec3de5c9e mkhtemp: generalised string concatenation
scatn in strings.c was buggy, so i replaced it; it
concatenates any number of things.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 10:35:33 +01:00
Leah Rowe 1539aff302 lbutils: simplify getprogname usage
the functions no longer return errors, so i don't
need to handle them.

furthermore, the handling in state.c is redundant,
so i've removed that too.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 09:30:10 +01:00
Leah Rowe c2a70b7de0 libreboot-utils: simplify random tmpdir namegen
generalise it in rand.c because this logic will
be useful for other programs in the future.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 09:18:36 +01:00
Leah Rowe 45edcf33f7 lbutils: rename mkrbuf to rmalloc
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 08:37:32 +01:00
Leah Rowe 6e4839d356 libreboot-utils: simplify lbgetprogname
make it more reliable; it can't segfault
now, under any circumstance. not even
once.

the problem arised when lbsetname was not
called in a program, before calling the
function: lbgetprogname. a segfault would
occur, due to it being NULL.

not every os/libc has getprogname, so i have
my own implementation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 08:20:09 +01:00
Leah Rowe 909b321f3a lbutils makefile: use c99 in strict mode
not c90

i use stdint now on a few files. i had this
idea in my head to use C89 for some reason,
but this is pointless.

c99 however is worthy as a minimum, because
for example, compilers like tcc will adhere
to its spec (for the most part), so this is
the minimum reasonable requirement on modern
unix systems.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 07:30:29 +01:00
Leah Rowe afe2e71c01 util/nvmutil: better hexdump
this is a more generic one that i implemented
for "lottery.c" (which is really just a tester
of my rset function in lib/rand.c)

i could probably actually write a full hexdump
program in libreboot-utils to be honest.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 07:22:34 +01:00
Leah Rowe 546565f321 cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-29 07:09:06 +01:00
Leah Rowe ab79f2b113 TODO
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 09:27:55 +00:00
Leah Rowe 5b26343e24 TODO
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 09:17:44 +00:00
Leah Rowe 16bc9feda8 mkhtemp: use O_NOFOLLOW in same_dir
we have a policy:
symlinks do not exist.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 09:16:05 +00:00
Leah Rowe 93ecd26306 TODO
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 09:12:15 +00:00
Leah Rowe c4ff9e5763 lbutils env_tmpdir: use static strings for fallback
i currently return pointers to these, without copying.

they can fade because of this. make them static, since that
is what they should be anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 09:07:40 +00:00
Leah Rowe 6643d9c1fa lbutils: unify xopen and open_on_eintr
use open_on_eintr for gbe files

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 09:03:18 +00:00
Leah Rowe 4ecdadb7a6 libreboot-utils: unified errno handling on returns
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 08:32:27 +00:00
Leah Rowe 49cac232d8 libreboot-utils: much stricter open() handling
abort on error, and do EINTR looping

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 08:09:14 +00:00
Leah Rowe 03dd3c2894 lbutils/file ffree_and_set_null: err if null
free can take a null, that's fine, but my pointer
to the pointer being freed should not be null. that
is a bug.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 07:47:31 +00:00
Leah Rowe 63984a4a6a libreboot-utils: much stricter close() handling
remove close_warn and close_no_err

make close_on_eintr a void, and abort
on error instead of returning -1.

a failed file closure is a world-ending
event. burn accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 07:30:55 +00:00
Leah Rowe fd26c6e631 util/mkhtemp: fix wrongful errno reset
on error state, i was resetting errno
unconditionally, which would then mask
the real error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 07:06:22 +00:00
Leah Rowe 0f1a22174f libreboot-utils: unified error handling
i now use a singleton hook function per program:
nvmutil, mkhtemp and lottery

call this at the startup of your program:

(void) errhook(exit_cleanup);

then provide that function. make it static,
so that each program has its own version.

if you're writing a program that handles lots
of files for example, and you want to do certain
cleanup on exit (including error exit), this can
be quite useful.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 06:53:37 +00:00
Leah Rowe 55f0e6ac8e libreboot-utils: simplified pledge/unveil usage
i no longer care about openbsd 5.9. we assume unveil
is available, as has been the case for the past 12
years.

i use wrappers for unveil and pledge, which means that
i call them on every os. on OSes that don't have these,
i just return. it's somewhat inelegant, but also means
that i see errors more easily, e.g. misnamed variables
inside previous ifdef OpenBSD blocks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 05:49:41 +00:00
Leah Rowe 7f39ce5f9b libreboot-utils: extremely safe(ish) malloc usage
yes, a common thing in C programs is one or all
of the following:

* use after frees
* double free (on non-NULL pointer)
* over-writing currently used pointer (mem leak)

i try to reduce the chance of this in my software,
by running free() through a filter function,
free_if_not_null, that returns if a function
is being freed twice - because it sets NULL
after freeing, but will only free if it's not
null already.

this patch adds two functions: smalloc and vmalloc,
for strings and voids. using these makes the program
abort if:

* non-null pointer given for initialisation
* pointer to pointer is null (of course)
* size of zero given, for malloc (zero bytes)

i myself was caught out by this change, prompting
me to make the following fix in fs_dirname_basename()
inside lib/file.c:

-       char *buf;
+       char *buf = NULL;

Yes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 04:25:14 +00:00
Leah Rowe cec9a25c2a nvmutil: clamp rand (rejection sampling)
clamp rand to eliminate modulo sampling; high
values on the randomisation will bias the result.

not really critical for mac addresses, but there's
no reason not to have this. this patches reduces
the chance that two libreboot users will generate
the same mac addresses!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 03:10:46 +00:00
Leah Rowe f4f1670909 util/nvmutil: tidy up hextonum
i had a bunch of hacks in here because i was
previously using very buggy rand. now it's ok.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 03:08:52 +00:00
Leah Rowe 998528c404 rand.c: fix initialisation bug in mrkbuf
should be null on bad return

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-28 02:27:00 +00:00
Leah Rowe 29296fc513 cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-27 22:58:12 +00:00
Leah Rowe 1e23ee26b1 header
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-27 21:41:12 +00:00
Leah Rowe 0cc4ff7b3b util/libreboot-utils: fix div by zero in rsize
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-27 17:14:10 +00:00
Leah Rowe db6e817ded util/libreboot-utils: finish implementing hell
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-27 16:56:40 +00:00
Leah Rowe 5d6344292a challenge
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-27 02:28:27 +00:00
Leah Rowe a29a3ac6f6 cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 23:02:00 +00:00
Leah Rowe 1a09efbbbe cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 19:44:23 +00:00
Leah Rowe d1ba9bae03 further cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 13:09:43 +00:00
Leah Rowe 10ecf32e33 libreboot-utils: improved randomness test
and the module bias handling is fully correct

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 10:52:11 +00:00
Leah Rowe 8e8f7bced4 mkhtemp rand: fix theoretical integer overflow
extremely theoretical, with a T. T for theoretical.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 09:04:30 +00:00
Leah Rowe d6087901c1 rand/libreboot/utils: prevent div by zero
not really a thing. bufsiz would never be zero,
unless the demon takes over linux

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 08:59:03 +00:00
Leah Rowe cf16d07df9 rand: fix modulo bias in rmalloc
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 08:56:15 +00:00
Leah Rowe dbc99be9a0 cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 07:04:23 +00:00
Leah Rowe b211706559 improve 3
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 4d4285e63c improve 2
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe fe259bd042 improve
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 1900e18dae phrasing
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe f7bd4b9472 nvmutil: remove errno handle in hextonum
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 5e049df024 REAL_POS_IO enable by default in nvmutil
(for real pwrite/pread. don't use the compatibility
one - it works perfectly, but using it is pointless
and may have unknown bugs, even though i know it's
probably perfect)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 5ea7fe22b2 cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe c2c24b7a24 nvmutil: fix lseek call when read pos i/o enabled
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 3d3193bb80 mkhtemp readme
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 8522b5c391 more cleanup on rand.c
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe e151179d14 cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe c4ff47a8ed fix makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe f4f3fe3e0a libreboot-utils: tidy up rand.c
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 58ce1d74c0 libreboot-utils: new function, scatn()
concatenate an arbitrary number of strings,
pointed to by char **

i'll use this and the next function, dcatn,
in an upcoming feature planned for mkhtemp.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe b84c929e64 rmalloc
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe e0319f0116 util/libreboot-utils: randomisation test
to test the effectiveness of the rand function

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe dc7a02da2d cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe c66f381e90 mkrstr
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 1e79219bea lbutils: new function, mkrbuf (random malloc)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe ee4f765719 lbutils: close fd on rset failure
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe e8c4bccd86 further clarify intentt
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 4034b211ce lbutils, rset: err if zero bytes requested
similar to the logic about other failure states

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe b26837c4dc dot
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe e44ea5d794 lbutils: also check null!
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 7b3c8cf7ec lbutils: clarify design regarding urandom/getrandom
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 34f26319d7 lbutils, rand: err on zero return (fatal)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe bce1099509 cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 0626bf48f4 lbutils: cast to prevent ub in rset()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 50e3b1f45d cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 0d86fd38df fix offset on urandom falback
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe a6f76ac4ee libreboot-utils: tidy up rand
make it more efficient. much lower rejection
rate now, about 2-5%. deal with bias, but also
get numbers in bulk. not too many.

i'd say this is about right in terms of performance
balance. 64 bytes == 8 large integers.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe cbe48caf1b cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe a70ede850d libreboot-utils: replace rlong() with rset()
now you can send an arbitrary number of bytes
with random numbers

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 00b56c0278 libreboot-utils: tidy up rand
also re-add /dev/urandom support, as a config option

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 6c8cf9a9e0 util/mkhtemp: use /dev/urandom *if enabled*
build-time option. do not allow fallback; on
a system where getrandom is used, it should
be used exclusively.

on some systems, getrandom may not be available,
even if they have a newer kernel.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 718095b0fe util/mkhtemp: extremely hardened mkhtemp
This will also be used in lbmk itself at some point,
which currently just uses regular mktemp, for tmpdir
handling during the build process.

Renamed util/nvmutil to util/libreboot-utils, which
now contains two tools. The new tool, mkhtemp, is a
hardened implementation of mktemp, which nvmutil
also uses now. Still experimental, but good enough
for nvmutil.

Mkhtemp attempts to provide TOCTOU resistance on
Linux, by using modern features in Linux such as
Openat2 (syscall) with O_EXCL and O_TMPFILE,
and many various security checks e.g.
inode/dev during creation. Checks are done constantly,
to try to detect race conditions. The code is very
strict about things like sticky bits in world writeable
directories, also ownership (it can be made to bar even
root access on files and directories it doesn't own).

It's a security-first implementation of mktemp, likely
even more secure than the OpenBSD mkstemp, but more
auditing and testing is needed - more features are
also planned, including a compatibility mode to make
it also work like traditional mktemp/mkstemp. The
intention, once this becomes stable, is that it will
become a modern drop-in replacement for mkstemp on
Linux and BSD systems.

Some legacy code has been removed, and in general
cleaned up. I wrote mkhtemp for nvmutil, as part of
its atomic write behaviour, but mktemp was the last
remaining liability, so I rewrote that too!

Docs/manpage/website will be made for mkhtemp once
the code is mature.

Other changes have also been made. This is from another
experimental branch of Libreboot, that I'm pushing
early. For example, nvmutil's state machine has been
tidied up, moving more logic back into main.

Mktemp is historically prone to race conditions,
e.g. symlink attacks, directory replacement, remounting
during operation, all sorts of things. Mkhtemp has
been written to solve, or otherwise mitigate, that
problem. Mkhtemp is currently experimental and will
require a major cleanup at some point, but it
already works well enough, and you can in fact use
it; at this time, the -d, -p and -q flags are
supported, and you can add a custom template at
the end, e.g.

mkhtemp -p test -d

Eventually, I will make this have complete parity
with the GNU and BSD implementations, so that it is
fully useable on existing setups, while optionally
providing the hardening as well.

A lot of code has also been tidied up. I didn't
track the changes I made with this one, because
it was a major re-write of nvmutil; it is now
libreboot-utils, and I will continue to write
more programs in here over time. It's basically
now a bunch of hardened wrappers around various
libc functions, e.g. there is also a secure I/O
wrapper for read/write.

There is a custom randomisation function, rlong,
which simply uses arc4random or getrandom, on
BSD and Linux respectively. Efforts are made to
make it as reliable as possible, to the extent
that it never returns with failure; in the unlikely
event that it fails, it aborts. It also sleeps
between failure, to mitigate certain DoS attacks.

You can just go in util/libreboot-utils and
type make, then you will have the nvmutil and
mkhtemp binaries, which you can just use. It
all works. Everything was massively rewritten.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Todd Baker c2ad2f9b40 Add Dell OptiPlex 3040 Micro support
Adds libreboot support for the Dell OptiPlex 3040 Micro based on the
OptiPlex 3050 Micro (same Skylake H110 PCH-H platform). Key differences:
DDR3L SODIMMs, Pentium G4400T-class CPUs (Skylake only), Realtek ALC3234
HDA, and Boot Guard neutralization via deguard.

Tested and booted on hardware.

Signed-off-by: Todd Baker <todd_baker@student.uml.edu>
2026-03-26 06:59:42 +00:00
AlguienSasaki 417b85b464 Added full support for the X280 2026-03-26 06:59:42 +00:00
duchy 1586482c15 Added missing dependency 2026-03-26 06:59:42 +00:00
duchy 0c2de61a7e Added missing dependency 2026-03-26 06:59:42 +00:00
Ron Nazarov 92610cc92b Enable CBFS file option backend on T480s
It was already enabled on the other sky/kabylake thinkpads.
2026-03-26 06:59:42 +00:00
Leah Rowe 6d70a0dc56 nvmutil: fix unveil call
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe f7072fc4c0 util/nvmutil: better getrandom safety
err if buf NULL, len -1

also getrandom may return fewer bytes, so
loop that too.

why can't linux be like bsd? bsd is:

arc4random_buf(buf, len);

no checks needed. it never errs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 49413b7d6b fix variable name
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe bd5fc60dd9 util/nvmutil: re-add fallback timer rand
for 1989

enabled via ifdef. not enabled by default.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 59b9215a97 util/nvmutil: remove arandom fallback on rand
openbsd 2.1 has arc4random, which we detect here.

arandom was apparently added much later, so this
is dead code. remove it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe a3e3cdc057 util/nvmutil: rand: use getrandom on newer linux
we still fall back to the old /dev/urandom read
on older linux, via runtime detection (ENOSYS).

getrandom is better, because it guarantees entropy
via blocking, and works even when /dev/urandom
is unavailable.

it has the same practical benefit as arc4random,
which i use on bsd. linux can have arc4random,
but not every linux libc has it, so it's better
to use getrandom on linux.

older linux will fall back to /dev/urandom

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe bad5688ae9 util/nvmutil: buffered urandom reads
also generally tidied the code and made
it more robust e.g. retries

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 0e105e8135 tidy some comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 1c210e3857 nvmutil: make tmpdir string much more random
more random characters

i added support for higher than the standard 6
characters so i can go nuts

XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 113f2db37c util/nvmutil: hardened mkstemp
200 retries, not 100.

and open with O_NOFOLLOW and O_CLOEXEC

check X on mkstemp

support more than 6 X in mkstemp

make PATH_LEN 4096

1024 is a bit low

make default mkstemp length 4096

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 7cc584fe0e nvmutil: rename lseek_loop to lseek_on_eintr
that's what it does!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe f4ea610014 nvmutil: rename x_i_close to close_on_eintr
that's what it does. waits for eintr to stop firing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe d9f2aff95c nvmutil: don't have finite eintr wait
this is technically incorrect. we don't control
faults in the hardware.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 81ac8eead9 nvmutil: rename x_i_fsync to fsync_on_eintr
that's what it does. waits on eintr.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 2ddb9019c8 util/rename: rename x_i_fsync
rename to fsync_on_eintr, because that's what it does

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 861cc85580 nvmutil: remove memcmp/memcpy/strrchr/rename
i had this idea in my head of later porting this
to k&r c for fun. but screw it.

compiling on everything since 1989 is enough

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 1b82927843 util/nvmutil: tidy up includes
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe aff629f571 util/nvmutil: major cleanup
handle init in xstatus()

it's now a singleton design

also tidied up some other code

also removed todo.c. bloat.
will do all those anyway.

too much change. i just kept
touching the code until it
looked good

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 3010781df6 now remove the .empty files
but git still has these directories
in history now, so people should have
it now when cloning.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe c189c9c483 util/nvmutil: add obj dir to git
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 331a1af6df util/nvmutil: add rule to create lib objdir
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe a5a4e3d215 nvmutil: move lib files to lib/
only keep nvmutil.c in main

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 275f8e6f05 util/nvmutil: put objects in obj/
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 98aa88ad44 nvmutil makefile: use portable assignments
question mark respects environmental variables

but isn't portable

you can just pass as argument on the command line

question mark is more useful for build systems,
but i'm not really bothered. the old way works.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 0fea4f69e0 nvmutil: split nvmutil.c into multiple files
this is a big program now. act like it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe a7fa5c3bf4 util/nvmutil: remove global variable x
make a singleton function instead

now there are technically no global variables,
so i can more easily start splitting this up
into multiple linked programs

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 411076b499 nvmutil: disable arc4random on obsd below 2.1
arc4random added in openbsd 2,1

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe b60a243a87 util/nvmutil: initialise st in tmpdir
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 321b0ac07c util/nvmutil: use strlen for tmpdir length
sizeof includes the null

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 3256c3fcb8 nvmutil tmpdir: check world-writeable / sticky bits
must be world writeable and not have sticky bits

a bit theoretical, but we're also reading TMPDIR,
which could be anything

due to how this is called, it defaults back to /tmp
if null is returned, so itt's safe

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 21cd0b7a91 nvmutil: fix modulo bias in mkstemp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 65ed83d2e7 util/nvmutil: limit EAGAIN/EINTR retries
set it really high though, so it's still
basically reliably

an EINTR/EAGAIN storm could cause problems
in prw()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 232b069492 util/nvmutil: use real fsync
that function i added was a load of crap. it
worked, but it was a bit dumb, and crap.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 1197d43923 nvmutil: don't disable blocking on random
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 7fd8869c20 re-add arc4random in nvmutil
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe a3b8f1e8eb util/nvmutil: remove randomness fallback
not secure. i'll just re-add arc4random

and use urandom as the fallback

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe e3a007a8ae nvmutil: don't read urandom fd if fd not open
yeah. obvious bug

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe cdce83d19e nvmutil: new urandom fd every time (rlong)
otherwise, a stale descriptor could be manipulated
easily by an attacker over time

very theoretical to be honest

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe a400409517 util/nvmutil: fix typo in unveil call
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 4260327edc util/nvmutil: fix rlong static variables
whoops

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 5a9e5017ea nvmutil: remove redundant srand call
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe e57dc2efcb nvmutil: remove redundant check
the actual cat function just writes to stdout

we need only check that the input is null, which
i've now done.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe a3eeedf2d8 util/nvmutil: obsessively check null cmd
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 5b808d4f26 util/nvmutil: tidy up variables
where feasible, don't assign them at declaration

this is especially important for the next change
i'm working on

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe f63837888c stricter S_ISREG check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe e087d2cf77 nvmutil: even stronger double-run protection
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 562dc92325 util/nvmutil: guard against running twice
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe bb6acae8f4 nvmutil: make commands check themselves
check yourself before you execute yourself

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 1057bebce5 util/nvmutil: check file flags properly
masking O_ACCMODE tells you which flag it is

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 72dab46dbc util/nvmutil: tighter pledge and unveil
call it sooner. set new_state afterward.

i had to uncouple nv from some functions
for this, and i also added some extra
checks especially at exit, about whether
to touch nv (whether it is initialised)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 6e6b1dd366 util/nvmutil: stricter work buf check
check it right after initialisation

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe f5104c5893 79-character rule must be obeyed
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 182ea65774 util/nvmutil: fix comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 3871b60124 util/nvmutil: default to clang on make-hell
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 5d7e516e33 util/nvmutil: tidy up memcmp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 2fe71dfb90 nvmutil: add suffixes to makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 2457944d75 nvmutil: tidy up the makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 92580f0659 util/nvmutil: portable default make rules
older compilers might not have -std for example.

the code is portable, but old compilers can't
compile with just "make", you have to add lots
of flags

i will now use "make strict" and "make hell"
in testing, but otherwise make without flags
are fine.

move the current strictness to command:

make strict

added an extra command:

make hell

hell uses -Weverything, and is useful with
clang's strict testing, on which i only got
a very small number of errors (it's way less
than a lot of programs would get with this
flag, because -Weverything is REALLY STRICT):

ja, mich nvmutil$ make hell CC=clang
clang -I.   -Wall -Wextra -pedantic -std=c90 -Os -Werror -Weverything nvmutil.c -o nvmutil
In file included from nvmutil.c:35:
./nvmutil.h:225:16: error: padding struct 'struct commands' with 1 byte to align 'rw_size' [-Werror,-Wpadded]
  225 |         unsigned long rw_size; /* within the 4KB GbE part */
      |                       ^
./nvmutil.h:217:8: error: padding size of 'struct commands' with 4 bytes to alignment boundary [-Werror,-Wpadded]
  217 | struct commands {
      |        ^
./nvmutil.h:235:8: error: padding size of 'struct xfile' with 4 bytes to alignment boundary [-Werror,-Wpadded]
  235 | struct xfile {
      |        ^
./nvmutil.h:288:16: error: padding struct 'struct xstate' with 4 bytes to align 'xsize' [-Werror,-Wpadded]
  288 |         unsigned long xsize;
      |                       ^
nvmutil.c:617:43: error: implicit conversion changes signedness: 'off_t' (aka 'long') to 'unsigned long' [-Werror,-Wsign-conversion]
  617 |         _r = rw_file_exact(f->gbe_fd, f->buf, f->gbe_file_size,
      |              ~~~~~~~~~~~~~                    ~~~^~~~~~~~~~~~~
nvmutil.c:626:43: error: implicit conversion changes signedness: 'off_t' (aka 'long') to 'unsigned long' [-Werror,-Wsign-conversion]
  626 |         _r = rw_file_exact(f->tmp_fd, f->buf, f->gbe_file_size,
      |              ~~~~~~~~~~~~~                    ~~~^~~~~~~~~~~~~
nvmutil.c:654:46: error: implicit conversion changes signedness: 'off_t' (aka 'long') to 'unsigned long' [-Werror,-Wsign-conversion]
  654 |         _r = rw_file_exact(f->tmp_fd, f->bufcmp, f->gbe_file_size,
      |              ~~~~~~~~~~~~~                       ~~~^~~~~~~~~~~~~
nvmutil.c:661:39: error: implicit conversion changes signedness: 'off_t' (aka 'long') to 'unsigned long' [-Werror,-Wsign-conversion]
  661 |         if (x_i_memcmp(f->buf, f->bufcmp, f->gbe_file_size) != 0)
      |             ~~~~~~~~~~                    ~~~^~~~~~~~~~~~~
nvmutil.c:702:23: error: implicit conversion loses integer precision: 'int' to 'unsigned char' [-Werror,-Wimplicit-int-conversion]
  702 |                 f->part_valid[_p] = good_checksum(_p);
      |                                   ~ ^~~~~~~~~~~~~~~~~
nvmutil.c:1045:21: error: implicit conversion loses integer precision: 'int' to 'unsigned char' [-Werror,-Wimplicit-int-conversion]
 1045 |         f->part_valid[0] = good_checksum(0);
      |                          ~ ^~~~~~~~~~~~~~~~
nvmutil.c:1046:21: error: implicit conversion loses integer precision: 'int' to 'unsigned char' [-Werror,-Wimplicit-int-conversion]
 1046 |         f->part_valid[1] = good_checksum(1);
      |                          ~ ^~~~~~~~~~~~~~~~
nvmutil.c:1170:45: error: implicit conversion changes signedness: 'off_t' (aka 'long') to 'unsigned long' [-Werror,-Wsign-conversion]
 1170 |                     (unsigned long)(p * (f->gbe_file_size >> 1)));
      |                                       ~  ~~~~~~~~~~~~~~~~~^~~~
nvmutil.c:1269:37: error: implicit conversion loses integer precision: 'int' to 'unsigned short' [-Werror,-Wimplicit-int-conversion]
 1269 |         return (unsigned short)f->buf[pos] |
      |         ~~~~~~ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~^
 1270 |             ((unsigned short)f->buf[pos + 1] << 8);
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
nvmutil.c:1610:9: error: implicit conversion changes signedness: 'off_t' (aka 'long') to 'unsigned long' [-Werror,-Wsign-conversion]
 1609 |         r = rw_file_exact(f->tmp_fd, f->bufcmp,
      |             ~~~~~~~~~~~~~
 1610 |             f->gbe_file_size, 0, IO_PREAD,
      |             ~~~^~~~~~~~~~~~~
nvmutil.c:1618:9: error: implicit conversion changes signedness: 'off_t' (aka 'long') to 'unsigned long' [-Werror,-Wsign-conversion]
 1617 |         r = rw_file_exact(dest_fd, f->bufcmp,
      |             ~~~~~~~~~~~~~
 1618 |             f->gbe_file_size, 0, IO_PWRITE,
      |             ~~~^~~~~~~~~~~~~
nvmutil.c:1609:6: error: implicit conversion loses integer precision: 'long' to 'int' [-Werror,-Wshorten-64-to-32]
 1609 |         r = rw_file_exact(f->tmp_fd, f->bufcmp,
      |           ~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 1610 |             f->gbe_file_size, 0, IO_PREAD,
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 1611 |             NO_LOOP_EAGAIN, LOOP_EINTR,
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 1612 |             MAX_ZERO_RW_RETRY, OFF_ERR);
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~
nvmutil.c:1617:6: error: implicit conversion loses integer precision: 'long' to 'int' [-Werror,-Wshorten-64-to-32]
 1617 |         r = rw_file_exact(dest_fd, f->bufcmp,
      |           ~ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 1618 |             f->gbe_file_size, 0, IO_PWRITE,
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 1619 |             NO_LOOP_EAGAIN, LOOP_EINTR,
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~
 1620 |             MAX_ZERO_RW_RETRY, OFF_ERR);
      |             ~~~~~~~~~~~~~~~~~~~~~~~~~~~
nvmutil.c:1936:45: error: implicit conversion changes signedness: 'long' to 'unsigned long' [-Werror,-Wsign-conversion]
 1936 |                 if (rv >= 0 && (unsigned long)rv > (nrw - rc))
      |                                                         ~ ^~
nvmutil.c:2193:27: error: signed shift result (0x8000000000000000) sets the sign bit of the shift expression's type ('long') and becomes negative [-Werror,-Wshift-sign-overflow]
 2193 |         if (nrw > (unsigned long)X_LONG_MAX)
      |                                  ^~~~~~~~~~
./nvmutil.h:147:38: note: expanded from macro 'X_LONG_MAX'
  147 | #define X_LONG_MAX ((long)(~((long)1 << (sizeof(long)*CHAR_BIT-1))))
      |                              ~~~~~~~ ^  ~~~~~~~~~~~~~~~~~~~~~~~~~
fatal error: too many errors emitted, stopping now [-ferror-limit=]
20 errors generated.
make: *** [Makefile:42: hell] Fehler 1

in a future commit, i intend to fix all of these issues,
so that the code reliably compiles in hell-mode.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe ac0451c0b8 util/nvmutil: move asserts to header
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 611217e57e nvmutil: extremely defensive CHAR_BIT test
this program needs bits to be 8

some obscure systems set it to something else

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 38022c5d47 util/nvmutil: add defensive buffer check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 400369b361 util/nvmutil: remove stale comment
and add another

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe b6d176189e util/nvmutil: fix randomness in mkstemp
i need to re-initialise r each time.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 4688dee7cb util/nvmutil: split up copy_gbe
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 60a6d3861c util/nvmuti: make fsync_dir() generic
yes, this begins the next phase of nvmutil:

remove global status in functions that should be
generic, and make functions that are not generic,
generic. make everything as re-useable in a library
as possible.

most of the program is error control, as it should
be, but much of it is mixed in with functions
that really should just be split up for libraries.

so that is what i'm now beginning.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe c1c49c3945 prototype for new_state() in nvmutil
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 50695c9fbd util/nvmutil: split up nvmutil.c
i still use a global variable, but now only
one, which is a structure containing the
state of the entire program

now i can easily start modifying it to make
functions generic, and then i can start
making parts of it into easy libraries

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe b1a51d7e5c cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 2703c9c938 util/nvmutil: start removing global state
for now still actually global, but i'm gradually
putting variables into a single global stucture
which will then allow me to make everything
local, which would then allow me to start
splitting up the program and modularising it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 292f504524 nvmutil: stronger entropy_jitter()
run it for a bit longer

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 464fb5c0d8 util/nvmutil: don't use strcpy
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe cf8cb4bdcc util/nvmutil: check fd path in try_fdpath
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe ab8929808f util/nvmutil: add bound check to x_try_fdpath
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 8911d2c1dd another comment
it's a pretty insane hack. i should probably
just use normal fchmod

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe c6ae1d5ea2 comment
also improved the macro, making it stricter

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 6e6ab09cb0 cleanup (fix potential overflow in mkstemp)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 47a654a870 fsync_dir: abort if path length is empty
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe d0a125c16d nvmutil: prevent theoretical overflow on time()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 28820d169c also O_NOFOLLOW
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 1207b1bb72 util/nvmutil: dir fsync with O_DIRECTORY
guards against replacement attacks, on systems
that support this flag

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe ddb0bc314d util/nvmutil: fix mkstemp randomness
i made the string longer, but forgot
to adjust it. the new random function
is also better

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe b951ef2433 cast
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 251ba82ccb util/nvmutil: more reliable fallback crypto
we assume the fallback will be rare, so now we
make the mix static and keep xoring it, on the
theory that the number of failures on urandom
will be random, and tthat the fallback may only
apply once or twice in thousands of calls.

the time jitter is adjusted; rather than judge
the difference between two points close to each
other in time, we judge tthe randomness in
difference of time elapsed. this mitigates fast
CPUs being very fast and introducing rounding
errors, and also improves performonce on much
slower CPUs

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe a575a47733 util/nvmutil: use real rename() syscall
i was being cute earlier, but the rewrite
defeats the purpose of atomic file handling
in nvmutil, by not actually renaming! it was
more like, doing an actual copy, which meant
that corruption is likely during power loss

i've commented the code because i may
use it in a library in the future.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 8e2921f1ce nvmutil: harden against hardlink attacks
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 4871f4fda7 redundancy
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:42 +00:00
Leah Rowe 0237c9c9c6 util/nvmutil: loop EINTR on fsync
this improves reliability, making it more
likely that data actually gets synced,
since fsync can return -1 with EINTR,
indicating that a re-try should be
attempted.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 5ce5ac2994 pointer safety
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 7b62a1653b don't use PATH_MAX
unreliable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 1883325cd0 macro safety
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 2b3966feba util/nvmutil: portable S_IFMT
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 7650ab051f util/nvmutil: remove integer typedefs
better to just use standard names

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 445e96aefc util/nvmutil: remove global statics
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 28a499e556 util/nvmutil: fix unveil usage
arandom probably isn't available on super old obsd right??????

rather, unveil isn't. on systems that have arandom

yet we should not unveil something that may not
exist on modern systems

just don't unveil arandom, and don't check arandom
if unveil is enabled

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 96dde65d16 util/nvmutil: proper /dev/fd search in fchmod
some systems may not even have it

works with /dev/fd (bsd/mac etc)

works with linux (/proc/self/fd)

and falls back on super old systems
that have neither

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 120241f1cf util/nvmutil: tidy up makefile options
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe c46a634288 nope. put -Werror in the makefile
not compiling without it is a bug

don't let the default exclude it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 71ce22a938 nvmutil makefile: define WERROR but blank it
settting it to -Werror is wrong, should set
it not -Werror.

however, put the WERROR variable in the make
command. that way, i could test with

make WERROR=-Werror

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe af40114be7 util/nvmutil: portable fchmod
and with that, now the code compiles on gcc
with -std=c90 -pedantic

with -Werror and -Wall -Wextra

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe a0fd201b31 Revert "util/nvmutil: don't use fsync()"
This reverts commit bdb43afac6edef21a15f99b8c3beac01be8b86f7.
2026-03-26 06:59:41 +00:00
Leah Rowe e6b53e8aed util/nvmutil: longer string in mkstemp
have A-Z too, for more randomness

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe ad5a4771bf util/nvmutil: don't use mktemp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe f365969d34 util/nvmutil: don't declare libc prototypes
i no longer use -Werror

these can actually conflict on some weird
systems, so better just remove them

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 5927c175df util/nvmutil: portable memcpy/memcmp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 612783bc24 util/nvmutil: more portable close()
close may set errno to EINTR, which could
cause weird edge case behaviour in our
prw() functtion

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 26d8807b79 util/nvmutil: more secure tmpdir()
use stat instead of access (race conditions)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 1ce06b01e0 util/nvmutil: fix O_NONBLOCK fallback
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 15cbafe20b util/nvmutil: more secure mkstemp
try a few more times until success

explicitly return EEXIST when needed

we try multiple times and check more
thoroughly if a file exists, thus
reducing the risk of race conditions

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 24c4e715e6 util/nvmutil: more reliable TMPDIR handling
more portable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 0e0fcd5a81 util/nvmutil: don't use fsync()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 4233f76fee util/nvmutil: more portable functtions
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 64835e67fd util/nvmutil: add portable malloc extern
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 0043446f60 util/nvmutil: don't use size_t/ssize_t
not portable. some old systems don't have it,
or handle it very poorly

unsigned long is a reasonable way to refer
to indexes inside pointters

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe a8fe2c79db util/nvmutil: don't use SSIZE_MAX (not portable)
some old systems don't have ssize_t or size_t

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 6c37d2aa4b util/nvmutil: typeset size_t explicitly
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe ae43dc391f util/nvmutil: run-time CHAR_BIT test
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe ab806d2546 util/nvmutil: lower default PATH_LEN
older unix needed lower

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 9bdd91131d util/nvmutil: portable struct timeval
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe ea71010f85 util/nvmutil: portable S_ISREG
very old libc doesn't have it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 6a898dff72 mktemp prototype
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe ff458943c3 util/nvmutil: portable gettimeofday
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe e9d90e8aca util/nvmutil: use portable mkstemp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 2a6a63fef3 util/nvmutil: better urandom portability
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 609076d98b util/nvmutil: use local tmpfile on openbsd
if the global file is created on a different file
system than the gbe file, unveil would trigger an
abort trap, since we rely on created a second
temporary file, whose path we can't know ahead
of time.

i could get rid of unveil, or unveil a directory,
but neither is acceptable. just use localtmp on
openbsd. a temporary file is created next to
the gbe file, in the same directory.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 381b7e3abb util/nvmutil: /dev/random fallback
now the custom fallback code is very unlikely
to ever actually be used, on any system,
except really old systems.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe d7dea02fba add -I. to nvmutil makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 5b8ea71bbd re-add strict flags
i need these. can always turn them off
when running make if you need to

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe e795e42f66 also remove -Wextra
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 7f14693e6c util/nvmutil: more portable Makefile
-Werror removed, for older compilers

actual warnings still there

-std is configurable now

e.g.

make CSTD=-c90
make CSTD=-c99

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 824fade5e9 util/nvmuttil: don't use arc4random
i have urandom again. it's enough

the fallback rand implementation
is used if needed

now i don't have to worry about any
weird version of unix from 1992 and
deal with weird hacks. in fact, with
this change, my code will probably
compile on irix now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 04b215dd6d util/nvmutil: re-enable urandom reads
i had to loosen the pledges for the new i/o
framework, which needs more permissions

as a result, i can now open urandom in
this function statically, rather than
in nvmutil's control logic

and because of that, it's less buggy now

arc4random is disabled on linux by default,
because it's not universally available
on all libc, and only since about 2022
in some glibc versions

better for portability to let linux users
justt use urandom

the new logic is different. now it falls
back to rand per-byte, but in practise
it almost never will.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe b4b194f94c util/nvmutil: remove arc4random on linux
linux only had it since 2022.

lots of people will complain if i leave this enabled.

not all libc have it either

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 5d8b19fb75 util/nvmutil: fix cat
i simplified it in the last commits, but i sttill
need this loop to properly handle parts

otherwise yeah, all it's doing is copying a file
verbatim. duh.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe af7ab6f786 util/nvmutil: double-verify r/w using tmp files
we now read twice, verify the two, to make sure
one read isn't faulty

we operate on a tmp file, then rename back. this
reduces the risk of power cuts corrupting data

we properly verify the contents that we wrote
back

inspired largely by flashprog. i wanted to have
an insanely over-engineered and extremely safe
tool that edits intel gbe nvm files

and now i have one. the only one in existence.

i'm basically writing my own libc code at this
point, to be honest. i'll probably start puttting
these functions in libraries

e.g. that tmpfile generator

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 1556ca7173 nvmutil: use O_CLOEXEC on gbe files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 0d6bb8d747 util/nvmutil: fix verified first, in prw loop
yes, because otherwise if the offset is still
wrong, we allow junk to be written. bad!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 31835eb8e3 set errno
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 4b667f0d19 util/nvmutil: stricter return in pread
we were returning if verified is not off, but we
were not doing the check soon enough.

now it's clearer: just after either a reset,
or we found out offset doesn't match, we
return sooner.

otherwise, we read, and we verify again right
after. in the old code, we verified twice in
a row.

this is just more optimal, for error handling.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 572f00e7b7 no, break instead
in the last patch, i return, which then avoids
resetting the offset.

prw is very careful not to return early.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe d890a6b138 util/nvmutil pread: rw_over_nrw exit, not set
otherwise, if it's -1 and errno happens to be
EINTR or EAGAIN, we might loop on what is a
real error. this bug fixes that edge case.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 7f192b4344 nvmutil: stronger race-condition check on prw
do it per read, in the fallback pread/pwrite

per read/write that is

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe a050e5a563 util/nvmutil: fix theoretical buffer overflow
i already guard offsets in io_args, but it's best
to be thorough here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 8d81e8f68b util/nvmutil: prevent underflow in comparison
we already check before that rv is not negative,
and it starts at zero, but it's good to guard
it here just in case (for future re-factoring).

if rv is negative, it could convert (casted to
size_t) to a huge number (we don't want that).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe d148985e61 comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe b09f52547f util/nvmutil: extra race-condition check in prw
even with OFF_RESET, we still want some error checking.
if the check fails again immediately after, then it
suggests that another program really is modifying the
file, so we should stop.

the first check is done on the theory that another
program *was* working on it, but now isn't.

once again, this isn't perfect. use read pread/pwrite
if you need thread safety (and even then, you still
need to actually check your code)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 8c0946e9ba util/nvmutil: safer xstrxcmp() - overflow fix
if a points to a buffer shorter than maxlen,
and the string is not null-terminated early,
the loop may read may overflow

e.g.

char buf[3] = {'a', 'b', 'c'};
xstrxcmp(buf, "abc", 50);

this is undefined behaviour, and a bug. C allows
reading past arrays only if the memory exists,
but we can't guarantee that

to fix it, we check the condition for return,
namely NULL character, before using the character
again. This avoids reading further from a multiple
times so we exit as soon as we encounter NULL

this also avoids multiple reads from memory, though
a compiler would optimise that anyway

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 02dcee0bf7 phrasing
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 66a9166004 util/nvmutil: stricter rw_gbe_file_exact
we repeat these stteps later, but it's still good
to be exact here. these lower functions can
change.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 210f17b9d7 cast
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 7530881adc comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 2c66b813ef util/nvmutil: stricter lseep_loop return offset
we currently reset just fine, but a partial success
where the previous offset is not the same as the
original should also be considered failure.

this patch therefore makes the return much stricter,
making the code return an error if this occurs,
which in nvmutil would then cause a program exit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 00f92b33e1 util/nvmutil: only use srand on fallback rand
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 0ff1cac40c nvmutil: add missing check to io_args
accidentally removed this in a rebase

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 4b69645c88 util/nvmutil: add flock to pledge promises
otherwise, gbe.bin locking won't work!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 46bbb4d8e4 util/nvmutil: tidy up io_args
i don't like it grouped together. do it
all separate, for clarity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 402f5cacbd util/nvmutil: tidy up err()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 2d46837475 util/nvmutil: re-add io_args()
unified arg check for prw and rw_file_exact

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 7263125d60 util/nvmutil: rw_file_exact: check inputs also
we check them in prw, but we used to rely
on prw because we called that first. no more.

it's correct to also check them here anyway,
in case i ever call another function here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe a89747a5c8 util/nvmutil: rw_over_nrw: err if nrw is zero
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 13006f2516 util/nvmutil: rw: safer bound check
avoid pointer-range overflow arithmetic. this
patch doesn't change behaviour, but makes an
overflow impossible.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe f0f2e03476 util/nvmutil rw: make off_reset a toggle
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe d62780948f util/nvmutil: rw_file_exact: explicit casts
don't do it inside functions. some compilers may
be inconsistent, ditto several auditing tools.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 1583947625 util/nvmutil: fix potential overflow in rw
off is signed, so converting that to unsigned
is better than converting rc (unsigned)
to signed. i had the right idea, but got
it wrong in the earlier version. this
should fix potential overflow issues.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe e4802d4013 util/nvmutil: rw file: guard rc before addition
otherwise, it could still overflow

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 37526fc1c1 nvmutil: toggle for fd thread-safety err state
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 1d4a57ab26 util/nvmutil: clean up pwrite/pread case
some unused variables if enabled. hide them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 6d338e1fa4 util/nvmutil: partially mitigate fd offset race
our fallback pwrite/pread behaviour still does not
properly replicate the safety of real pwrite/pread

i intend to put this i/o code into a library for use
in other programs; nvmutil is single-threaded so
this change is largely redundant (but can't hurt)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 291c8a9a8b util/nvmutil: tidy up rw_file_exact
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe fe9900e7a1 comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe a78e156346 util/nvmutil: cleanup
remove ptr casts to ulong. size_t is better.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 4558993df4 nope, use size_t
despite my cast, size_t is better for mem index

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe ddd300493b util/nvmutil: use ulong on ptr casts
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 2de5c6332e util/nvmutil: remove rw_file_once
we don't need it anymore.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 3b9761fbed util/nvmutil: move looping logic to rw_file_exact
rw_file_once was doing what rw_file_exact should be
doing

_once does what it says: once

we were passing an offset (rc) to it that it was not
meaningfully using.

this makes the code now more robust, especially if
we later swap out or break _once - then we don't
get weird behaviour (if there is a regression).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe c825d80198 nvmutil: move increment logic to rw_file_exact
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 4a3951a4d9 nvmutil: fix redundant check
we already check not-zero in the next if

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe a3354d2598 util/nvmutil: cast gbe file size on ptr cmp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 1606f79c74 util/nvmutil: even safer pointer comparison
we assert now that ulong is the size of a pointer,
therefore we know that it can fit a pointer reliably.

this code is written for c90 spec so lacks uintptr

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe b88c81869b util/nvmutil: safer pointer comparison
technically we're never supposed to do arithmetic on
pointers (there's uintptr for that)

very anal fix

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 5b4168c763 util/nvmutil: enable arc4random on linux
not available on older systems. can just pass
the relevant flag in the compiler:

HAVE_ARC4RANDOM_BUF=0 at build time if you need
the fallback.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 8ccdde57e1 util/nvmutil: re-add arc4random
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 94632f3394 util/nvmutil: 5 retries, not 10
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 3c42608d6d util/nvmutil: check if gbe.bin is seekable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 5f6038af5d util/nvmutil: check inode during post-verify
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 30e953dc8f util/nvmutil: warn about gbe.bin hard links
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe b8246acf19 util/nvmutil: guard file replacement attacks
i already also guard other toctuo attacks :)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe e162d63ae6 util/nvmutil: guard against unlinking file
if someone deletes gbe.bin while operating, nvmutil
will now abort

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 7eadaf2894 util/nvmutil: don't use /dev/urandom
too over engineered and cumbersome.

the new security in prw() makes it brittle,
and i'd rather not move checks outside of it.

the fallback rand is random enough.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 64389b696b util/nvmutil: fix file check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe c5c629d776 util/nvmutil: fix cast check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe ec98e3143c util/nvmutil: more aggressive file checking
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe b231e28c93 util/nvmutil: prevent overflow in rw_file_exact
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 9ca9b54828 util/nvmutil: verify final offset in pwrite/pread
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe b86f415a3e util/nvmutil: check regular file in rw_file_exact
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe d34552b400 util/nvmutil: fix if (PWRITE)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 0612798ecf util/nvmutil: don't check o_append in prw
slow, per call. prw should be generic.

do it just for gbe files, once

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 026cbacbe2 util/nvmutil: configurable eintr/eagain
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 2eb045927b util/nvmutil: configurable retries/pread
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 72365f6447 util/nvmutil: support real pwrite/pread
build flag

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe c27dedfeea util/nvmutil: better commented I/O functions
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 33fa991141 util/nvmutil: make eintr/eagain setup clearer
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe caebecf6c6 nvmutil: fix rval in close_files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 0867507fc8 util/nvmutil: don't check write checksums on partial
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 3fba84ad95 util/nvmutil: don't recurse err/close_files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 897c7490b5 util/nvmutil: restore pad before reading to it
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe bae8999b80 util/nvmutil: don't show checksum on bad pwrite
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 6c29a07ca0 util/nvmutil: always restore saved errno
the last lseek there is only there to reset
state, so its errors are irrelevant.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe a12f502af8 util/nvmutil: post-write verification report
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 2f80ac76ae util/nvmutil: optimise fsync / write check
write all at once, then sync all at once,
then verify all at once.

this increases the chancce that all data
gets written first, in the case of power
less, because fsync may take a while on
some systems.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 7c73218438 util/nvmutil: set EIO on bad memcmp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 3f17cd3ebc util/nvmutil: split up rw_gbe_file_part
the post-verification stage deserves a function

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe df18e65835 util/nvmutil: detect partial gbe rw
we already covered this in prw() which is
what ultimately gets called, but still.

it's logically correct not to check it here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe fe16b79537 util/nvmutil: verify gbe contents after writing
read it back and check. sync to disk first.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe ce13599b99 util/nvmutil: consistent types
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 637d9a09c0 util/nvmutil: handle zero return in rw_file_exact
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 0cceb58867 util/nvmutil: rename lseek_eintr
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 8a7d73c223 util/nvmutil: fix lseek eintr err check
it should be is equal, not not equal

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 100cb2014e util/nvmutil: rename err_eagain() to try_err()
makes more sense in code

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe b345caa25c util/nvmutil: make EINTR configurable in prw()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 4a5a3bae45 util/nvmutil: tidy up prw()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe fe959f9fb8 util/nvmutil: extra overflow check in prw
compliant posix systems should never meet this
check, but i put it here.

spec != implementation

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe b60c42dcd0 util/nvmutil: extra overflow check in prw
do it at the very end

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 742b39be8c util/nvmutil: handle EAGAIN in prw()
the cat function can be greatly simplified

handle it conditionally, because not all
functions should use it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 7e8f375d9a util/nvmutil: split up rw_file_exact
move the gbe-specific parts out of it

what remains is a relatively generic
function; a very conservative implementation,
wrapping around libc functions but with
a few additional safety checks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe e71f977468 util/nvmutil: add negative off check to prw
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe fb57cedded util/nvmutil: also do libc check on normal io
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 2a83a8ec43 util/nvmutil: properly reset lseek on error
don't return. set r instead. this will fall through
and return the same way, but with proper reset.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 935d082a51 util/nvmutil: move libc check to prw()
this still gets done from rw_once, but
it's generic enough that we want it in
our prw() wrapper function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 07fa9bbc1f util/nvmutil: remove io_args()
most of it can be done in rw_file_once

truly general checks have been moved to prw(),
so that the function is more general purpose.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 4bb64c8d37 util/nvmutil: move EINTR handle to prw()
this way, we now have a universal function
that is reusable elsewhere, with the same
redundancy. the rw_once and rw_exact functions
still get this redundancy, through prw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 223932c5f8 util/nvmutil: simplify i/o
we can just fall through to nrw and decide
what function ta call there - either read/write
immediately and return, or fall back to the
portable positional implementation.

this also means we don't have to call io_args
in every function, since everything now runs
through prw()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 8071d7eaa8 util/nvmutil: cast rnum pointer check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 74077f9903 util/nvmutil: allow ushort to be 32-bit
no need to limit it here

rename ux to uint. no number specified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 4c0ec27b4e util/nvmutil: fix int assert
it can be higher than 32-bit, it's fine

the current check breaks some newer systems

accordingly, u32 becomes ux, x meaning x bits

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe dc6df36fe5 util/nvmutil: more asserts
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 23fee345fd util/nvmutil: nicer typedefs
now that i'm not using stdint, i can use sane
typedef names

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 9cfae27bf4 util/nvmutil: remove stdint feature macro
and remove stdint

i don't need it. i typedef these ints myself
and i assert their size

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 888107764d util/nvmutil: safer offset check (use subtraction)
don't allow overflows

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe abc484713a util/nvmutil: check null pointer in io_args
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe e1cd978f01 util/nvmutil: check overflow in io_args
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 5f8593b581 util/nvmutil: fix offset validation
i didn't take into account partial writes, in io_args

this fixes it

unfortunately, this means i have to loosen the offset
check a bit, but it's fine

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 6ad09f55e0 util/nvmutil: restrict pointers in io_args
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 8e555f444c util/nvmutil: check gbe file type before write
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 47936f52e9 util/nvmutil: check gbe file size before write
re-check. very unlikely since the program doesn't run
for very long, but we have to check if the file has
changed. this is a basic check of file size.

we could probably check the contents too, but that
would be overkill.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 551470cf6f util/nvmutil: lock gbe file
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe afcdae1350 util/nvmutil: don't allow symlinks
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 98466398f9 nvmutil: fix bound check in last commit
i was fixing the size, but it should be calculated
properly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe e44b297db5 util/nvmutul: remove unused arg in io_args
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 83f67bf02a util/nvmutil: block bad offset in io_args
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 14ab4c1b25 util/nvmutil: stricter i/o arg checks
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 386f715a29 util/nvmutil: stricter i/o length check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe d8be79432c util/nvmutil: rename len to nrw in i/o
consistent with prw()

i prefer nrw (number of rw operations)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 5ece694e67 util/nvmutil: tidy up prw()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 3e08c0724b util/nvmutil: block O_APPEND in prw()
O_APPEND allows writes at EOF, thus breaking
positional read/write

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 7836a2bbc6 util/nvmutil: stricter i/o errors
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 0c9bcaaba8 util/nvmutil: fix entropy issue
the time difference used here could go negative, which
would overflow in the xor op on mix, leading to a biased
entropy pool. we want to ensure that they numbers do
not overflow, because here they are cast to unsigned
which would then produce very large numbers.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 475c50932e nvmutil: cast integer in printf
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 6f26bd5db7 TODO
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 1abc40997f util/nvmutil: check defines/enum via assert
not at runtime

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 435b67327e util/nvmutil: r_type check in rw_gbe_file_part
i already send the right arg anyway. this is a
preventative bug fix against future maintenance.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 54536b0454 util/nvmutil: remove pointless check
already checked below, then err()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe f99921d717 util/nvmutil: add missing cast
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe ddf13a7e74 util/nvmutil: err in rw_file_exact on zero return
zero never occurs, because rw_file_once never returns zero,
but only rw_file_once determines that. rw_file_exact must
handle every possible error.

right now, if that call returns zero, rw_file_exact would
have an infinite loop.

this doesn't actually happen at the moment, so this is a
preventative bug fix.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe a0ca693d42 util/nvmutil: increment rc at end of rw_file_exact
for fussy static analysers and/or compilers

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 1dbd679c0c util/nvmutil: further tidy up prw()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe e239a3107f util/nvmutil: clean up i/o functions
properly verify the value of the arguments, with
asserts.

add simpler runtime checks in-function, on prw,
rw_file_once and rw_file_exact.

variable names in english now, and the code is
cleaner, while being functionally equivalent.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 347e39bab7 util/nvmutil: further tidy up rw_file_once
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe b4154dd29b util/nvmutil: minor cleanup: rw_file_once
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe a85f2898e2 util/nvmutil: remove dead code
useless check. will never be true.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe fdd99a9a45 util/nvmutil: remove pointless comment
itt's totally obvious

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 5f6a721fa0 util/nvmutil: reduced indentation in rw_file_once
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 172cbd4497 util/spkmodem-decode: add CHAR_BIT define
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 273bd992dd spkmodem-decode: edge detection *and* amplitude
for pulses, we currently use amplitude detection.

edge detection is better, because weak / low gain
signals will be more reliable. if audio is coming
in on/from a system that does automatic gain
adjustment, this once again is more robust too.

microphones and speakers (which people often use
with spkmodem if nothing else available) often
clamp amplitude, to an extent that this software
may not detect those pulses reliably that way.

so we detect slope edges instead. this causes
very little performance penalty (use of abs(),
that's about it)

however, edge detection is inherently vulnerable
to noise, so we will also detect amplitude. this
acts as an effective noise filter, while still
improving pulse detection.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 2aa1ccfd8a spkmodem-decode: reset calibration accumulators
in select_separator_tone, i never reset these
after computing their average.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe fd94bff968 util/spkmodem-decode: remove dead code
this check no longer applies (never triggers)

is_signal_valid already guarantees that the separator
tone is valid.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 1b73308c51 spkmodem-decode: small cleanup in decode_pulse
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe cad667faee spkmodem-decode: don't select sep tone on bad signal
otherwise, calibration could collect garbage data.
this improves noise mitigation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 15079d02bd spkmodem-decode: ignore invalid frames when setting bits
bits are currently assembled even on invalid frames. this
patch fixes that - the bug is also in the GNU version.

this reduces the chance of noise/calibration from creating
corrupt character output during operation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe 3245333c53 spkmodem-decode: reset char if separator disappears
improves reliability in the case when audio cuts out,
mic glitches, laptop audio power saving, etc.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:41 +00:00
Leah Rowe fe6da7a238 spkmodem-decode: fix single-tone learning bug
enforce at least two tones. this mitigates the
chance of random noise being treated as a real
tone, and reduces the chance of broken
thresholds versus freq min/max e.g.
freq min 31, max 32 and threshold 31

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 9e94cc017a spkmodem-decode: enforce calibrated seperator range
we weren't actually using what we calculated. this patch
fixes that, thus preventing random noise / microphone
clicks, random artifacts and such from being treated
as real frames (the purpose of is_valid_signal is
partly noise suppression).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 9d24b78340 spkmodem-decode: fix wrong sample count
in handle audio, i do the number of samples
per frame, and one more. e.g. 241 instead of
240. this bug is in the original GNU version
too. this patch fixes it.

this means that the output could slowly go
out of sync with calculated timings. the
patch fixes that. in practise, the decoder
is not that sensitive, and the code would
adjust anyway (automatic timing adjustment),
but ideally we want to not *cause* such
issues even if we mitigate them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 8085de594b Revert "util/spkmodem-decode: fix 3-frame timeout"
This reverts commit dbf0c3ccc2.
2026-03-26 06:59:40 +00:00
Leah Rowe 1d0e44c23a util/spkmodem-decode: clarify frame count on check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe a049f2df39 util/spkmodem-decode: static asserts
assert integer sizes, important in this program because
we make several implicit assumptions about word sizes,
and integers need to be of a certain size.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 681f580053 util/spkmodem-decode: annotate prototypes
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 7c88154cd2 util/spkmodem-decode: rename function for clarity
collect_separator should be select_separator, to bring
it in line with select_low_tone

this just makes the code a bit easier to read

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe fff2447606 util/spkmodem-decode: tidy up indentation
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 6ed722b73b fix typo in comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 4fff5121e8 util/spkmodem-decode: fix 3-frame timeout
i accidentally left this reset here during a
previous refactor.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe feb69bd946 util/spkmodem-decode: rename auto_detect_tone
auto seems redundant. detect implies auto.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 402e0ca7cc spkmodem-decode: learn tone per frame, not sample
the fir filter produces stable frequencies per frame,
but learning per sample (within a frame) means we
record the same value roughly 240 times.

here, we are syncing up at just the right moment
instead, and only at that moment, this increasing
both performance and reliability.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 84b0b8a543 spkmodem-decode: fix learn_samples increment
oops!!!

another mistake during refactoring. right now it
doesn't increment before being checked, so learning
can go forever in an infinite loop

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 011c65ddf4 spkmodem-decode: don't dump learn_samples in silence check
oops

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe a5d40166ce util/spkmodem-decode: split up auto_detect_tone
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 68fb740da2 util/spkmodem-decode: separate silence check
i conflated two separate tests in a previous change.

the silence check was defeated by still checking f
alongside it, which would be set, thus satisfying
the condition, and proceeding, which defeats the
purpose of the silence check (ignore false signal
that is actually noise) - so in the original patch
that i wrote, the extra checks actually do nothing.

this patch fixes that, and makes the logic a bit
clearer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:40 +00:00
Leah Rowe 4dc39990e1 util/spkmodem-decode: don't run decode in col_sep_tone
otherwise, it runs twice

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:39 +00:00
Leah Rowe 7e29d53667 util/spkmodem-decode: guard against silence in tone-detect
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:04 +00:00
Leah Rowe a81dde3d08 util/spkmodem-decode: split up handle_audio()
this enables the separated code to have reduced
indentation

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:59:02 +00:00
Leah Rowe e8d46de0e1 util/spkmodem-decode: also auto-detect separator
the tone detection currently only tracks data, not
the separator. track both instead, for improved
detection reliability.

e.g.

separator tone e.g: 9
data low tone e.g: 18
data high tone e.g: 24

two fir windows produce e.g.
freq data 9 sep 0
then 18, 9
then 24, 9
18, 9

so we take min(data, separator)

that gives 9,9,9,9

now we have the separator cluster

however, if both windows are active during transitions,
you can also capture the higher clusters, which would
allow freq_max to grow

so when you learn e.g.:

freq min = 9
freq max 24

then the learned threshold would be:

(9 + 24) / 2 = 16

and now you know how to separate the tones

fir already suppresses noise so the pulse should
be reliable. so freq/sep only go non-zero when an
actual tone exists

this should now result in being able to sync with
spkmodem encoders with no prior knowledge of the
correct tone frequences. we just use maths.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:58:19 +00:00
Leah Rowe 745e888edf util/spkmodem-decode: simplify valid_signal
since we have auto-detection now, we only need to know
that two signals exist, not that they are valid, since
the auto-detection now handles validation and fallback.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:58:19 +00:00
Leah Rowe 5b4c3c537e util/spkmodem-decode: automatic tone detection
a continuation of the previous patch. this waits for
currently one second, before defaulting to the hardcoded
value. otherwise, it tries to use whatever timing it
gets automatically.

this way, the program should now reconfigure its own
timing, without intervention by the user, if the timing
differs from sensible defaults.

this is because spkmodem is implementation-defined;
it's just however coreboot and/or GRUB happen to set
it up, and on the hardware in question.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:58:19 +00:00
Leah Rowe 78b71f867f util/spkmodem-decode: automatic tone calibration
current logic is hardcoded, as in the original spkmodem-recv.

with this change, small differences are observed and averaged,
then the detection thresholds are adjusted accordingly.

the existing macros serve as a baseline, but real signals
differ. with this change, we therefore account for possible
drift in timings, which can change in real-time; the old
code could possibly get out of sync beccause of that, which
may have resulted in corrupt characters on the screen. this
change therefore should make the output a bit more stable.

the detection window is continually adjusted, so that the
output timings don't drift.

the tolerances are automatically adjusted based on base
timings (see new define in patch)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:58:16 +00:00
Leah Rowe d03f80b893 util-spkmodem-decode: tidy up print_stats
make the frequencies clearer in printf

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:49:05 +00:00
Leah Rowe 4f26620e88 util/spkmodem-decode: do getopt first
much cleaner. do it right after zero-init memset.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:49:05 +00:00
Leah Rowe a0c8fd519e util/spkmodem-decode: init argv0 before pledge
otherwise, it'll be empty/undefined

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:49:05 +00:00
Leah Rowe a60be4028a util/spkmodem-decode: frequency meter in debug
useful timing now displayed

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:49:05 +00:00
Leah Rowe 6eff58aa7d util/spkmodem-recv: reset char precisely on timeout
instead of when it goes above, do it precisely on the
timeout. otherwise, if by sheer chance the signal
pauses and we reset the byte - sure, ok, but it's a
bit tight and we run the risk of advancing another
frame, depending on the timing.

this is a minor edge case, probably rarely ever
triggered in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:49:05 +00:00
Leah Rowe 30d5ca5146 rename util/spkmodem-recv to spkmodem-decode
it's no longer resembling the original util at all,
so a rename seems indicated. yes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:49:05 +00:00
Leah Rowe a31cfa4592 add missing star
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:49:05 +00:00
Leah Rowe cefae03502 util/spkmodem-recv: extensive commenting
and with this, i'm now pretty much done modifying grub's
crappy code. this experiment started in 2023 has now
pretty much concluded.

the original GNU code was poorly written, hardcoded
everywhere, and not documented or commented at all.

i had to learn what the code is doing through inference
instead, and i'm pretty sure that these explanations
cover everything. i hope?

maybe the frenchman can explain anything i missed. haha.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:49:01 +00:00
Leah Rowe 78d583e5ec util/spkmodem: explain what the defines are
and calculate some of them instead of hard coding

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-26 06:47:55 +00:00
Leah Rowe 2a32e498c8 useful comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 20:06:23 +00:00
Leah Rowe 8ccaff0d8e util/spkmodem-recv: also cache sep_pos in decode
yet another optimisation for weaker compilers - but
some modern compilers may not optimise well for this
code either.

this reduces the amount of references to the struct,
which is very expensive (48000 times per second) on
very old CPUs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 19:57:24 +00:00
Leah Rowe 9f41591a46 util/spkmodem-recv: optimise decode_pulse
the frame[] array is never actually used meaningfully.

that setting of frame[ringpos] on the decode_state is
only set here, but then the value isn't really used at
all. the entire size of the annay is used for sizeof
in print_stats, but then we can just declare that
manually. since we also know that this value never
changes, we can use a global define for the sizeof entry
in print_stats, thereby simplifying operation further

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 19:54:52 +00:00
Leah Rowe a7c69c3233 util/spkmodem-recv: clean up decode_pulse
make it easier to read by clearer variable naming.

this change also reduces memory accesses (fewer struct
dereferences - see: struct decoder_state), when using
much weaker/older compilers that don't optimise
properly. this, in the most active part of the code,
which is called.... 48000 times a second. peanuts on
modern CPUs, but on old (early 90s) CPUs it makes a
big difference.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 19:34:44 +00:00
Leah Rowe 3633878e1f util/spkmodem-recv: byte swap on big endian CPU
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 19:09:58 +00:00
Leah Rowe 594a5a02cd util/spkmodem-recv: remove errno define
may break on modern systems (macro)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 18:45:32 +00:00
Leah Rowe 9375ecc6a4 add endianness check to spkmodem-recv
a bit dirty. should handle this at runtime.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 18:37:11 +00:00
Leah Rowe f7fc5b1651 util/spkmodem-recv: properly handle stdin err
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 18:34:43 +00:00
Leah Rowe 22af92b473 another correction
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 18:25:34 +00:00
Leah Rowe 5b92b00bad util/nvmutil: fix regression on openbsd
when i removed arc4random integration, i forgot
to change this line back. oops!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 18:23:17 +00:00
Leah Rowe 1cce4871e2 TODO
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 17:55:54 +00:00
Leah Rowe cde28a8fbb TODO
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 17:52:05 +00:00
Leah Rowe 08b9595bc5 TODO
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 17:31:25 +00:00
Leah Rowe ab9ee73350 util/nvmutil: mitigate buggy libc i/o
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 16:34:33 +00:00
Leah Rowe 303c382eae util/nvmutil: implement zero-byte r/w timeout
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 16:24:36 +00:00
Leah Rowe 9656e78c3a TODO
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 16:16:09 +00:00
Leah Rowe 571c474866 util/nvmutil: add some useful comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 16:10:28 +00:00
Leah Rowe 1fb720e1e6 util/nvmutil: split up rw_file_exact
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 16:03:17 +00:00
Leah Rowe 48f124a2e8 fix indentation
i was editting this in another editor

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 15:34:10 +00:00
Leah Rowe f04b796dcc util/nvmutil: add jitter to fallback_rand entropy
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 14:36:01 +00:00
Leah Rowe 38c3889f67 util/nvmutil: improved entropy in fallback_rand
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 14:32:46 +00:00
Leah Rowe 1cee54ee2b util/nvmutil: remove /dev/random fallback
only use the old fallback, or /dev/urandom

/dev/random blocks on some older unix machines,
or in embedded environments that may never
have enough entropy, causing the code to hang.

urandom is most certainly expected to exist on
pretty much anything since the mid 90s.

i could probably re-add the arc4random setup
for BSDs. i'll think about it. gotta do that
portably too.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 14:26:54 +00:00
Leah Rowe 1ad9ffb482 util/nvmutil: include time.h after types.h
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 14:16:11 +00:00
Leah Rowe 922344e81e util/nvmutil: mitigate fast calls to rand
if someone calls rhex fast enough, the timestamp
may not change. this mitigates that by adding
a counter value to the mix

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 14:13:55 +00:00
Leah Rowe 53c5a40007 util/nvmutil: fallback randomiser
used when a random device isn't available, on old
unix, or on certain chroot environments.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 14:10:29 +00:00
Leah Rowe 5ba0b98fbc util/nvmutil: correct install usage
one for directory, then copy the binary

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 14:01:24 +00:00
Leah Rowe 35ba3aef91 util/nvmutil: fix makefile
forgot to include the binary in the path

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:56:47 +00:00
Leah Rowe af1a219e40 util/nvmutil: remove errno extern
may break modern systems. and all old systems that
i care about will handle errno just fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:54:04 +00:00
Leah Rowe 8269b05a63 util/nvmutil: use install -d instead of mkdir -p
-p isn't portable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:53:02 +00:00
Leah Rowe e931f66b99 util/nvmutil: fix comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:48:53 +00:00
Leah Rowe fe630cba5e util/nvmutil: use chmod instead, in Makefile
yeah, why not use a tool that's been around since the
80s?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:43:20 +00:00
Leah Rowe 478c994f34 util/nvmutil: add -m to install on Makefile
also support LDFLAGS

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:42:12 +00:00
Leah Rowe ea4deb98b5 util/nvmutil: simplify flags on urandom
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:31:35 +00:00
Leah Rowe 55e071c381 util/nvmutil: fix mistake in random check
forgot this. oops

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:28:18 +00:00
Leah Rowe a9e5f9ef4f util/nvmutil: portable errno
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:25:35 +00:00
Leah Rowe 87b74aadbc util/nvmutil: fix non-portable variable declaration
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:22:30 +00:00
Leah Rowe 1184dcb05c util/nvmutil: disable urandom if not found
disable random mac address generation on really old
operating systems.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:21:03 +00:00
Leah Rowe 74f2d9a1f3 util/nvmutil: use ECANCELED on checksum err
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 13:10:10 +00:00
Leah Rowe a40d14fcd6 util/nvmutil: don't use errno for program state
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 12:52:22 +00:00
Leah Rowe a4f5061297 util/spkmodem-recv: code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 07:13:42 +00:00
Leah Rowe 2479633368 util/spkmodem-recv: optimise pulse check
the last change was good, but this code, again,
has to do these calculations 48,000 times a second.

trivial on new computers. but now try it on a
computer from 1992.

we should try to make this as fast as possible :)

older compilers especially don't optimise these
checks. this patch shifts it to one subtraction and
one unsigned comparison, rather than checking less
than or greater than both. often used in... literally
exactly this type of program.

on a good compiler this will compile to an add, cmp
and conditional jump.

less readable, but the results (set 1 or 0) make it
pretty obvious what it does, after a few seconds.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 05:31:44 +00:00
Leah Rowe e23cecb496 util/spkmodem-recv: clearer pulse decoding
i turned this into abs() call earlier, but this isn't
obviously readable by some people.

make it absolutely clear what this does. also reduces
use of syscalls.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 05:28:34 +00:00
Leah Rowe 1d2ee1cabc util/spkmodem-recv: say what freq_sep/data are
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 05:25:24 +00:00
Leah Rowe fcecb1229e util/spkmodem-recv: add a usage function
replace the err call in getopt

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 05:22:25 +00:00
Leah Rowe 69fb0618cc util/spkmodem-recv: tidy up the getopt loop
more knf-compliant

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 05:20:09 +00:00
Leah Rowe 65a6205dab util/spkmodem-recv: allow short sample reads
fread() may return short reads, whereas the current
code assumes either EOF or a full read.

change if to a while. really, it's that simple.
just loop until it's done. i probably b0rked this
myself when refactoring the GNU code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 05:17:09 +00:00
Leah Rowe 59f04eba9e util/spkmodem-recv: don't exit in print_stats
i treated ftell errors as fatal, but if fttell fails
with ESPIPE, and someone's using -d, the program may
exit immediately, even though there's no problem.

instead, skip printing the offset (basically no debug).

this fixes a bug that i introduced myself, when i forked
this code, because i added that error check; the GNU
code didn't have any check whatsoever.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 05:13:44 +00:00
Leah Rowe 9ac0331595 util/spkmodem-recv: buffer calls to fread()
we currently read small amounts of data with fread,
repeatedly, which is quite taxing on the CPU, on
very old systems.

48khz audio. 48000 calls to fread() per second?

yeah. let's optimise this.

performance now should be roughly O(1) in practise.
this and the other recent changes means no modulo
or division, reduced branching, memory memory roads,
and lots of buffering.

the buffering here is quite conservative, so the human
won't notice any difference. we're cutting the number
of times we call fread by a factor of several thousand,
but you'll still see text scrolling down pretty quick,
with minimal lag.

the old GNU code i forked was terrible at this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 05:08:44 +00:00
Leah Rowe 2c3d0b5a3e util/spkmodem-recv: make new pulse calculation clearer
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 04:59:42 +00:00
Leah Rowe 62a496ec9e util/spkmodem-recv: tidy up pulse decoding
make it clearer about next/old, in the loop. this also
improves performance on older systems (cache the values
first, don't re-calculate)

again, this is GNU code. but you wouldn't know it, in my
current version. i forked this from GRUB several years
ago and started cleaning it for fun.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 04:55:18 +00:00
Leah Rowe 1953812efd util/spkmodem-recv: split up handle_audio()
the signal check should be its own function,
for clearer understanding

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 04:53:05 +00:00
Leah Rowe a31ccd8c3d util/spkmodem-recv: tidy up handle_audio
frame handling, error checks, pulse decoding and
character decoding are all jumbled up. this patch
separates them a bit, making it clearer.

should also help codegen. this tool is dealing with
high bandwidth text, which on slower computers may
be cumbersome. every optimisation counts.

not really relevant on newer systems.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 04:49:03 +00:00
Leah Rowe 44c6b453bc util/spkmodem-recv: optimise ring buffer pos calc
instead of computing next every time, just advance
two indexes. another performance optimisation on
older machines, especially old compilers, because
it reduces the amount of logical branching.

the old code was pretty much just advancing two
indexes in lockstep, when getting the next pulse,
but recalculating one of them based on the other,
each time.

this is yet another hangover from the old GNU code
that i forked three years ago.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 04:44:44 +00:00
Leah Rowe 54936a45a5 util/spkmodem-recv: don't use modulus on decode
it's slow on older compilers/systems that don't optimise.

instead, we branch (cheaper) and just do an above or
equal comparison), resetting appropriately or subtracting.

should yield an actually useful performance gain, on older
systems. a bit theoretical on modern systems, which optimise
well (modern compilers will produce assembly code much like
what the new C code is doing)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 04:39:00 +00:00
Leah Rowe 19e0249a8a spkmodemrecv makefile: add -c to install
a bit pedantic. but that's my intention.

for backwards compatibility with older systems.

this flag means: create the directory. on modern
versions on all systems, it's the default behaviour.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 04:36:29 +00:00
Leah Rowe 72eed0b12c util/spkmodem-recv: further portability / cleanup
i used a bunch of global variables. that's gone.

added proper externs, including for errno. lots of
old unix systems require this. this version should
be perfectly polished and portable now.

all status is now handled in a struct, making the
code a bit easier to understand, because the variables
now are clearly pertinent to the state of the decoder,
rather than being seemingly random.

some indentation reduced.

also cleaned up ftell/feof usage again. the new code
is a bit more robust when dealing with piped input(which
is literally what this program takes, exclusively)

i started my cleanup of this tool from GNU GRUB in 2023.

i finished it today.

also the Openbsd pledge is more portable now (code made
to compile on pre-pledge openbsd as well)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-12 04:30:40 +00:00
Leah Rowe bbb8825553 util/nvmutil: further clean up decode_pulse()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-11 23:40:34 +00:00
Leah Rowe 42cad20ffd util/spkmodem-recv: tidy up frame decoding
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-11 23:34:43 +00:00
Leah Rowe bf9c4a67f8 util/spkmodem-recv: handle fread errors
also handle EOF condition and exit cleanly.

don't use dirty feof.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-11 23:30:22 +00:00
Leah Rowe 9195ff97b7 util/spkmodem-recv: fix getopt prototype
i use -pedantic and std=c90

also add the define

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-11 23:25:50 +00:00
Leah Rowe 62c0cc68c5 removed some unnecessary things
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-11 23:14:51 +00:00
Leah Rowe 361dbef41c another fix
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-11 23:13:33 +00:00
Leah Rowe 7af3015a89 tiny fix
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-11 23:12:27 +00:00
Leah Rowe 6962404ce5 util/spkmodem-recv: portability and code cleanup
borrowing recent improvements from nvmutil

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-11 22:39:16 +00:00
Leah Rowe 977c83873e util/nvmutil: re-use do_rw() from prw()
using a special leah-only technique

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 18:20:47 +00:00
Leah Rowe 5f8fe4fdc3 util/nvmutil: add missing sanitization tests
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 17:17:39 +00:00
Leah Rowe 48f65abb01 util/nvmutil: properly use rc in rw_File_exact
subtract and add iteratively

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 16:57:46 +00:00
Leah Rowe 9eb3895f4e util/nvmutil: tidy up gbe_cat_buf()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 16:52:38 +00:00
Leah Rowe 69cf4fe6ed util/nvmutil: split up rw_file_exact()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 16:43:47 +00:00
Leah Rowe 454af12153 util/nvmutil: update some comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 16:25:43 +00:00
Leah Rowe 1403bdf1cc util/nvmutil: re-add EINTR loop check on rw
accidentally removed it during re-factor

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 16:17:33 +00:00
Leah Rowe f0240df229 util/nvmutil: rename set_err for code clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 16:14:43 +00:00
Leah Rowe c41483916a util/nvmutil: skip errno check in main
skip it if there is a valid checksum, to mitigate
erroneous errno state upon exit from run_cmd(),
because we can assume by this point that we
are in fact ready to write at this point.

the check at the end still exists, which will catch
any error set by write, and any error set before
that. this fixes a weird warning on cmd_dump.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 16:06:13 +00:00
Leah Rowe 13c759bf3a util/nvmutil: don't reset errno in rw_file_exact
reset it in callers instead.

this means that the main function is more generalised.

we know by the time we exit that there is no error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 16:02:57 +00:00
Leah Rowe 82dbeb9736 util/nvmutil: reset errno in gbe_cat
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 16:00:16 +00:00
Leah Rowe 9ba84d1117 util/nvmutil: reset errno in gbe_cat_buf
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:58:57 +00:00
Leah Rowe ca37bef34f util/nvmutil: fix bad loop in command sanitizer
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:55:05 +00:00
Leah Rowe 9691e7e7db util/nvmutil: use set_err where appropriate
in the new file i/o functions, my own setting
of errno should be done with set_err. this
avoids clobbering what the real libc set.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:50:45 +00:00
Leah Rowe 59eac512eb util/nvmutil: properly set errno everywhere
i set it to ecanceled before. now i set it more
appropriately, for each type of error.

where a real syscall was called, or my file i/o
functions are used, err() is called with errno
itself as input, to avoid clobbering real errno.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:46:30 +00:00
Leah Rowe 3174806b3f util/nvmutil: fix /dev/random fallback
i forgot to set urandom_fd

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:38:30 +00:00
Leah Rowe 318c0eb95b Revert "util/nvmutil: fix check in command sanitizer"
This reverts commit b28076557b.

nope. the check was already correct before.
2026-03-10 15:36:43 +00:00
Leah Rowe 9b6b89250d util/nvmutil: don't use bad pointer cast in prw
in practise it's ok, but some compilers might complain.

all this change costs is a bit of branching inside a
loop, but compilers will sort that out.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:33:50 +00:00
Leah Rowe b28076557b util/nvmutil: fix check in command sanitizer
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:30:10 +00:00
Leah Rowe 0b4e298cb1 util/nvmutil: use EINVAL in command sanitizen
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:29:23 +00:00
Leah Rowe 4819dcbc75 util/nvmutil: don't use xopen() for urandom
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:27:24 +00:00
Leah Rowe 9427285dce util/nvmutil: conservative use of errno
only use errno itself as the value

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:19:09 +00:00
Leah Rowe 1f953359cb util/nvmutil: re-try /dev/[u]random on EAGAIN
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:12:12 +00:00
Leah Rowe b291bbf2e5 util/nvmutil: Make rw_file_exact an ssize_t
Use its return value. Don't exit from the function,
but actually treat it like a real syscall.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 15:03:16 +00:00
Leah Rowe 4bc7ba1e4b util/nvmutil: use O_NONBLOCK on /dev/[u]random
on some systems, it is otherwise blocking, but blocking
can be disabled, making access more reliable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 14:25:43 +00:00
Leah Rowe c953228bb0 util/nvmutil: fix possible overflow: gbe_x_offset
preventative fix, since the values are currently
quite tiny. this new check is the same, but goes
the other way to eliminate overflow.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 14:18:19 +00:00
Leah Rowe 883860d687 util/nvmutil: reset rw_file_exact errno on EINTR
this is essentially what it already did, but it
wasn't explicitly stated. now it's clearer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 14:12:45 +00:00
Leah Rowe 6eefd80efe util/nvmutil: comment prw()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 14:07:35 +00:00
Leah Rowe 06cb129530 util/nvmutil: better SSIZE_MAX define
the old one assumes that ssize_t is signed size_t,
which let's face it, is always true in practise,
but not actually guaranteed!

so now i'm using one that's even more pedantic.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 13:42:43 +00:00
Leah Rowe 79106c5b3d util/nvmutil: define EXIT_FAILURE/SUCCESS
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 13:34:40 +00:00
Leah Rowe adfe865afc util/nvmutil: more sensible errno init
just use errno itself as input to err

if unset, it's set to ECANCELED anyway

i really should rewrite the error handling
to not use errno at some point. it's a bit
unreliable, on some unix systems.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 13:32:29 +00:00
Leah Rowe 4202ded96c util/nvmutil: proper errno status on prw()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 13:21:34 +00:00
Leah Rowe ee751c27ed util/nvmutil: reset errno if EINTR on lseek
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 12:32:42 +00:00
Leah Rowe bbe6de44e8 util/nvmutil: stricter errno on prw()
we want the first error to be the one shown,
when returning negative

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 11:25:27 +00:00
Leah Rowe 5603fa51d2 util/nvmutil: fix printf c89/c90 specifiers
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 11:15:43 +00:00
Leah Rowe 7431046ea6 util/nvmutil: reset part_valid
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 11:08:42 +00:00
Leah Rowe 632c85ce1c util/nvmutil: restore errno if lseek resets it
if it resets it on success, that is!

theoretically possible. we must preserve errno.

normally i'm a bit more casual about it, but this
function is replicating libc, so i must be strict

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 11:06:31 +00:00
Leah Rowe 8d156bcf35 util/nvmutil: fix another printf specifier
ditto to last commit

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 11:02:39 +00:00
Leah Rowe fa859d80d5 util/nvmutil: fix bad print specifier (c90)
size_t may be unsigned long long, but lu
is for unsigned long. the integer is small
enough that we don't need to worry, so let's
just cast it accordingly (inside err)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:58:41 +00:00
Leah Rowe 6778a4ed98 util/nvmutil: only inc num_invalid on bad checksum
this fixes a regression that i introduced

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:56:56 +00:00
Leah Rowe e3e02fa657 util/nvmutil: restore errno on failed offset restore
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:53:11 +00:00
Leah Rowe 6408570fa1 util/nvmutil: don't leave part_valid untouched
always set it. the current logic only sets it if
valid, but invalid doesn't, relying on global
initialisation. this check sets it explicitly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:48:16 +00:00
Leah Rowe 090a702b74 util/nvmutil: remove unused st variable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:44:27 +00:00
Leah Rowe cbd7ad13a3 util/nvmutil: check whether a file is a file
and not, say, a socket or a directory, or
a character device, or something else.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:35:51 +00:00
Leah Rowe 91a6395e5c util/nvmutil: preserve errno during i/o
do not clobber errno

yeah we're basically being libc now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:26:12 +00:00
Leah Rowe 5a005eff9e util/nvmutil prw: always restore original offset
it currently only does so on success, but errors will
leave the file descriptor corrupted.

reset it accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:24:16 +00:00
Leah Rowe 890d1a2ff6 util/nvmutil: err if file offset fails
currently it returns success, if restoring a
previous offset failed. this leaves descriptor
corrupted when the caller thinks otherwise

return -1 instead, so that the caller can treat
it as an error, relying on whatever lseek had
set for errno

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:18:25 +00:00
Leah Rowe b56cfbcc54 util/nvmutil: fix buffer overread in prw()
edge case scenario, unlikely to actually trigger.

now impossible to trigger.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:14:25 +00:00
Leah Rowe 19ee28161e util/nvmutil: fix rc overflow bug in rw_file_exact
check that it's below len, not above it. that way, it
will now exit if it goes above (which it shouldn't,
but it theoretically could if the code was changed
and there was a regression or subtle edge case)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 10:00:20 +00:00
Leah Rowe 6d27853f56 util/nvmutil: use C90 instead of C99
with the other changes made recently, super old
compilers now work.

yes, i needed to change some specifiers in printf.

typedefs provided for uint, and a define included
X OPEN SOURCE 500. and asserts for integers.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 09:25:27 +00:00
Leah Rowe f2d982e9b3 util/nvmutil: define O_BINARY flag
use it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 09:17:45 +00:00
Leah Rowe 630852b7be util/nvmutil: fix indent on ifdefs
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 09:15:55 +00:00
Leah Rowe e9a593b2c0 util/nvmutil: define SIZE_MAX if not defined
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 09:10:43 +00:00
Leah Rowe 7620d1d126 util/nvmutil: remove arc4random for portability
just use /dev/urandom and fall back to /dev/random

this is what i was doing for years. this combined
with other changes, and the new prw() function
for i/o, means portability should be pretty high
now. i will actually start testing nvmutil on old
bsd systems from the 90s later.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 09:07:15 +00:00
Leah Rowe 21f8d323f4 util/nvmutil: portable pread/pwrite
not thread-safe

lucky we're single-threaded!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 09:04:20 +00:00
Leah Rowe 5ae5d53751 wip
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 08:44:56 +00:00
Leah Rowe edb1508a59 util/nvmutil: more reliable stdint.h check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 08:26:20 +00:00
Leah Rowe 2a20251ad6 util/nvmutil: reset errno before run_cmd
in case any stale errors are present.

at this point, we know that the code is likely
safe and that nothing happened, because we quite
obsessively call err() before that point.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 07:12:55 +00:00
Leah Rowe d2cd126775 util/nvmutil: explicitly check cmd nullptr
null isn't guaranteed to be zero

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 07:05:34 +00:00
Leah Rowe 978c30a961 util/nvmutil: safer SSIZE_MAX define
the current one assumes two's compliment and no
padding bits. i assert two's compliment earlier
in code, but it doesn't guarantee:

sizeof(ssize_t) == sizeof(size_t)

it's theoretically possible that size_t=64
and ssize_t=32, and then the macro would break.

this new version uses SIZE_MAX instead, without
subtraction, but halves it using a bit shift.

this may still break, but it should work nicely.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:56:02 +00:00
Leah Rowe a6d0146a3b util/nvmutil: fix a bad cast (or lack thereof)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:53:39 +00:00
Leah Rowe e26511c8b8 util/nvmutil: err if unsupported rw_type on i/o
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:51:47 +00:00
Leah Rowe 0a55f286c1 util/nvmutil: rename badly named off_t assert
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:43:13 +00:00
Leah Rowe 0f035e208e util/nvmutil: assert two's compliment integers
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:35:17 +00:00
Leah Rowe 6392eb18b6 util/nvmutil: add assert for int
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:31:04 +00:00
Leah Rowe 83f3a059b9 util/nvmutil: add assert for off_t
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:30:52 +00:00
Leah Rowe 6ad7eaef32 Revert "util/nvmutil: don't use zx printf specifier"
This reverts commit ba3cf14faa.
2026-03-10 06:18:29 +00:00
Leah Rowe 90fada0a23 util/nvmutil: explain errval handling in err()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:17:04 +00:00
Leah Rowe 2fda988da6 util/nvmutil: make rc size_t (not ssize_t)
i overlooked this when writing. it's comparing
to a length which is size_t, so let's avoid
an unnecessary cast.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:11:31 +00:00
Leah Rowe ba3cf14faa util/nvmutil: don't use zx printf specifier
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:10:20 +00:00
Leah Rowe 2f1f129753 util/nvmutil: add portable asserts for integers
we need this to be the case for our code, that char
and uint8_t are 8 bits, and that uint16_t and uint32_t
are 16- and 32-bit.

these asserts protect us in case it's not (it will cause
a compile time error).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 06:07:21 +00:00
Leah Rowe 9747ca4151 util/nvmutil: abort if I/O len exceeds SSIZE_MAX
in rw_file_exact

otherwise, if length exceeds SSIZE_MAX, we could
hit an overflow

the buffers and lengths we deal with are relatively
small anyway, so this fix is preventative

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 05:33:12 +00:00
Leah Rowe 93a4ec3497 util/nvmutil: annotate the prototypes
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 05:11:32 +00:00
Leah Rowe f53a8d4f18 util/nvmutil: unified gbe file part I/O
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 04:58:24 +00:00
Leah Rowe baca2d8883 util/nvmutil: remove stale define
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 04:20:55 +00:00
Leah Rowe 80f3aac62d util/nvmutil: unified I/O: stdout, urandom and gbe
everything is a file

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 04:13:02 +00:00
Leah Rowe 6402a0fbe9 util/nvmutil: unified urandom/gbe file reading
like before, but with the newly correct logic

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 03:08:09 +00:00
Leah Rowe 4131402589 util/nvmutil: safer read_gbe_file_exact
it now retries infinitely on EINTR, except when the return
of pread is precisely zero, at which point it errs.

this is better than having an arbitrary maximum like before,
and increases robustness on unreliable file systems, e.g.
NFS shares.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 02:48:34 +00:00
Leah Rowe 0c23474322 util/nvmutil: report checksum in cmd_dump
as it should be!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 01:51:18 +00:00
Leah Rowe 84a9e8f89b util/nvmutil: reduce checksum report verbosity
only print a message what arg_part is set. this
means that a checksum error message won't be printed
on cat commands.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 01:38:22 +00:00
Leah Rowe 007dece09e util/nvmutil: unified io flags
don't hardcode it per command logically. do it in
the command table instead.

this also fixes a bug where the cat commands did
not set the permissions read-only.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 01:29:12 +00:00
Leah Rowe bb9010fdc1 util/nvmutil: require good checksum on cat
since the cat command can be used to create bad
gbe files, if the checksums don't match. my rule
is that nvmutil must never be used to destroy
data, only correct it (e.g. a file with just one
valid part can have it copied to the other part,
but you can't copy a bad part - and i removed
the "brick" command).

i *did* disable checksum requirements on the
dump command. with this, you can check the nvm
area and it tells you what the correct checksum
could be. then you could just correct it in a
hex editor if you wanted to, quite easily.

the idea is to slow down the act of destroying
or corrupting data as much as possible. someone
wily enough can use a hex editor to patch up some
files just fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 01:04:28 +00:00
Leah Rowe 08b1d95874 util/nvmutil: initialise w in gbe_cat_buf
no build error at the moment, nor would there be if
using clang or gcc, but i imagine some buggy compilers
might complain.

remember: portability. i also want this code to compile
on old, buggy compilers.

logically, this initialisation is redundant.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 00:53:53 +00:00
Leah Rowe 8f3bc13ac5 util/nvmutil: simplify the cat command
the current test is a bit over-engineered, so
i simplified it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-10 00:46:18 +00:00
Leah Rowe aa67cf087d util/nvmutil: add cat16 and cat128 commands
these take any file size of gbe file: 8KB, 16KB
or 128KB. so does the normal cat.

then you can use cat, cat16 or cat128. these
output to stdout, the corresponding size in KB.

0xFF padding used on the larger files. on the
larger files, the first 4KB of each half is the
GbE parts, and everything else is 0xFF padding.

now you can resize gbe files easily, example:

./nvmutil gbe128.bin > gbe8.bin

yes

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 23:47:22 +00:00
Leah Rowe 66f1640552 util/nvmutil: nope. rename out back to cat.
it *is* cat. it's catting two GbE parts. so its cat.

(two 4KB areas, plus padding when i add cat16/cat128)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 22:54:38 +00:00
Leah Rowe 724c9bb36c util/nvmutil: rename cat to out
it doesn't cat. it outputs one file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 22:34:28 +00:00
Leah Rowe 3d6e2637d6 util/nvmutil: remove stale comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 22:25:39 +00:00
Leah Rowe 1e45d19f5d util/nvmutil: added a "cat" command
with this, you can read 16KB and 128KB files, and output
them to stdout, but it outputs 8KB

for example:

./nvmutil gbe128.bin > gbe8.bin

now you have a 8KB file

i could probably easily add cat16 and cat128 too.

nvmutil reads two 4KB parts regardless of GbE file
size (one from the first 4KB of each half of the
file), so this was easy to implement.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 22:18:51 +00:00
Leah Rowe 7d64b8ea8d util/nvmutil: allow dump without good checksums
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 21:49:07 +00:00
Leah Rowe 45ea92a077 util/nvmutil: fix bad cast conversion
don't cast unsigned to signed.

no behaviour is changed, but this will prevent some
silly compilers complaining about -Wsign-conversion

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 21:12:59 +00:00
Leah Rowe b5af1bf3ac util/nvmutil: add guard in rhex()
i removed this before, but it's good to put it
here defensively, in case i ever mess up
the urandom read function again.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 21:08:36 +00:00
Leah Rowe f8ddb6ef84 util/nvmutil: fix EINTR detection on urandom read
i forgot to handle it in the previous refactor

not really a problem in practise, since the first
read probably succeeds anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 21:06:18 +00:00
Leah Rowe c59b3b7638 util/nvmutil: reorder some functions linearly
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 20:47:45 +00:00
Leah Rowe 0f9ce929b4 util/nvmutil: tidy up gbe/urandom reading
split them up into their own functions, since they
no longer operate according to the same policy.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 20:41:12 +00:00
Leah Rowe 1f4ab21403 util/nvmutil: fix a bad comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 18:11:34 +00:00
Leah Rowe 61968ec2b9 util/nvmutil: explicitly reset file descriptors
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 17:53:56 +00:00
Leah Rowe b69863e51f util/nvmutil: fix indentation in rhex()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 17:46:46 +00:00
Leah Rowe cd63f1a7f3 util/nvmutil: remove unused variable in rhex
on bsd

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 17:45:50 +00:00
Leah Rowe 646e349893 util/nvmutil: fix bsd build issue
urandom_fd is unavailable on bsd

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 17:44:48 +00:00
Leah Rowe 85cc3071bb util/nvmutil: even safer rhex()
also handles possible overflows in read_gbe_file_exact

it removes dead code on both paths: arc4random and
urandom

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 17:41:29 +00:00
Leah Rowe b2a3edd170 util/nvmutil: only check n in rhex on linux
not bsd

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 17:33:23 +00:00
Leah Rowe 8f719f80b8 util/nvmutil: safer calculated_checksum
we rely on uint16_t wrapping, but some platforms may
behave weirdly.

cast as uint32_t and then cast back, on return, with
an explicit mask beforehand.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 17:08:54 +00:00
Leah Rowe 61015dbc6c util/nvmutil: much safer rhex()
n could be zero under weird regression cases

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 17:02:14 +00:00
Leah Rowe f34d020a20 util/nvmutil: tidy up hexdump()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 16:54:42 +00:00
Leah Rowe d3b567edcf util/nvmutil: assert uint16_t as 16-bits
some platforms might get this wrong. define it
explicitly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 16:52:42 +00:00
Leah Rowe afebfe7389 util/nvmutil: safer cast in nvm_word
cast buf[x] directly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 16:41:40 +00:00
Leah Rowe 2d4567238a util/nvmutil: define _FILE_OFFSET_BITS
some older systems have 32-bit off_t. this makes them
have 64-bit off_t

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 16:34:59 +00:00
Leah Rowe 48b8be7a24 util/nvmutil: include sys/types.h
some older systems need it for pread/pwrite

it must come before stat.h

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 16:33:30 +00:00
Leah Rowe 31bd21a466 util/nvmutil: use even older define for pread
with this new define, we can target even older systems
from the late 90s.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 16:29:05 +00:00
Leah Rowe 8fc0f4fa07 util/nvmutil: tidied up a comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 15:32:26 +00:00
Leah Rowe 681967c386 util/nvmutil: don't include not-needed inttypes.h
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 15:30:03 +00:00
Leah Rowe 2773736dfc util/nvmutil: reset errno on urandom partial read
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 15:00:52 +00:00
Leah Rowe 62964b42ed util/nvmutil: consistent file location on err()
put it at the start of the message

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 14:47:33 +00:00
Leah Rowe f2a5f2de45 move nvmutil .gitignore rules to util/nvmutil/
i plan to release this as a standalone utility at
some point, once it's perfect (on its current
feature set)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 14:38:21 +00:00
Leah Rowe 7e0b052412 util/nvmutil: remove empty ChangeLog/README
i will write a *manpage* at some point. for now, the
documentation on libreboot.org shall suffice.

i'm nearly ready to submit this code to coreboot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 14:35:44 +00:00
Leah Rowe f05a273cb4 util/nvmutil: clean up the Makefile
that option there is already defined in the code

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 14:33:21 +00:00
Leah Rowe 3f566d3250 util/nvmutil: tidy up the main comment header
merge it into one

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 14:32:15 +00:00
Leah Rowe 4fd6bdc4ef util/nvmutil: say what the program does!
and with this, i'm probably done for a while

i've obsessively audited this code for a week

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 07:03:55 +00:00
Leah Rowe f266e2a16c util/nvmutil: standardised Makefile (add all)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 06:46:12 +00:00
Leah Rowe c96254be8b util/nvmutil: Makefile cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 06:38:18 +00:00
Leah Rowe 6a4ad68273 util/nvmutil: add phone section to Makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 06:33:52 +00:00
Leah Rowe ec1e6bd7e8 util/nvmutil: safer / more portable install
explicitly declare the directory path for the given
file (nvmutil), otherwise it's implementation-defined;
on some systems, /bin/nvmutil means a directory named
nvmutil could then contain nvmutil.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 06:31:52 +00:00
Leah Rowe 1446df01f2 util/nvmutil: create install dir in Makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 06:30:14 +00:00
Leah Rowe 9f75a23a84 util/nvmutil: fix target in Makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 06:28:50 +00:00
Leah Rowe d0bf316edf util/nvmutil: directly compare fd/urandom_fd
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 06:24:22 +00:00
Leah Rowe dbc7fadcbc util/nvmutil: allow partial reads of /dev/urandom
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 06:09:34 +00:00
Leah Rowe e092b2ce0b util/nvmutil: explicit cast in nvm_word
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 05:31:51 +00:00
Leah Rowe 3b73ea4288 util/nvmutil: clarify CFLAGS in code
makefile is correct, but lots of people don't read it.

putting it iin code helps people avoid confusion.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 05:25:58 +00:00
Leah Rowe 3b188b4d2b util/nvmutil: specifically enable -std=c99
I also needed: #define _POSIX_C_SOURCE 200809L

I use -pedantic with -Wall -Wextra -Werror, which
forces very strict error handling and ISO C; this
means pread and pwrite aren't available.

The define fixes this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 05:18:53 +00:00
Leah Rowe 532d723ccd util/nvmutil: fix indentation in setmac
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 04:37:48 +00:00
Leah Rowe 14c2588772 util/nvmutil: err sooner, on bad command
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 04:04:12 +00:00
Leah Rowe 1a60eabcfe util/nvmutil: print expected checksums
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 03:56:50 +00:00
Leah Rowe c27f8b709a util/nvmutil: rename cmd helper functions
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 03:29:08 +00:00
Leah Rowe 2cf1d1bed8 util/nvmutil: remove MAC address short-commands
only allow the long form: setmac [MAC]

specifying gbe.bin just shows the help/usage now.
this is a safety feature, so that someone doesn't
accidentally write the gbe file. we want it to be
that the user specifically requested setmac.

setmac with mac address as the 3rd argument is
also disabled. this is done as part of a general
simplification and safety improvement to nvmutil.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 03:25:33 +00:00
Leah Rowe aeb076b30e util/nvmutil: remove cmd_brick
this is an extremely dangerous feature, and serves
no purpose to the user.

this change is part of a series of extreme safety
improvements, part of a larger nvmutil audit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 02:23:22 +00:00
Leah Rowe 0c64907a9e util/nvmutil: remove the setchecksum command
This feature is extremely dangerous, and we should
discourage against its use.

This is part of a series of changes that I've made
to make the code safer. You should only ever run
this on a valid GbE file, and nothing else.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 02:19:24 +00:00
Leah Rowe f7dfb0d265 util/nvmutil: re-order functions by execution
linear, top-down order. re-order the prototypes

also some general cleanup:

argc enums now validated. ifdefs for pledge
and arc4random now use a consistent naming
scheme.

feature change:

the "dump" command now fails if both checksums
are invalid, and won't show anything.

my next commit will disable setchecksum when
both checksums are invalid. this and the other
insane auditing i've done over the last few
days has been part of a major effort to make
nvmutil extremely safe, and robust.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 02:12:28 +00:00
Leah Rowe a6e271c86d util/nvmutil: unified checksum update
setchecksum and setmac update the checksum.

other commands don't.

this patch unified the logic, handling it
in write_gbe based on command[].chksum_write

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 01:20:59 +00:00
Leah Rowe 39cdd562d8 util/nvmutil: don't pledge on OLD openbsd
only pledge/unveil where available, on versions
that have it. this patch disables it on older
versions, allowing nvmutil to compile.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-09 00:20:30 +00:00
Leah Rowe db440bd71d util/nvmutil: make write_mac_part() a void
its return value is never used, in the current code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 23:42:11 +00:00
Leah Rowe 5dc3f323c3 util/nvmutil: fix typo in message
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 23:40:12 +00:00
Leah Rowe 07f9f607ab util/nvmutil: don't re-calculate skip_part
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 23:39:13 +00:00
Leah Rowe dbd4d6d84a util/nvmutil: limit rw size on specific commands
i previously had this as a speed optimisation, but
removed it because it wouldn't make any real speed
difference, on most modern file systems / kernels.

however, this also has the dual purpose of ensuring
only what was verified gets written, on operations
that only touch the NVM area, since this relies on
checksum verification.

therefore, i have re-added this feature, but under
the new design of nvmutil. it is done policy-based,
instead of having if/else for specific commands.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 23:32:08 +00:00
Leah Rowe 70da9c3940 util/nvmutil: better error message for bin check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 23:06:01 +00:00
Leah Rowe 4d6732dade util/nvmutil: EINTR looping on write_gbe_file
up to a maximum number of retries

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 23:03:42 +00:00
Leah Rowe 163bf8beac util/nvmutil: clean up obsessive comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 22:41:03 +00:00
Leah Rowe 848d575cea util/nvmutil: policy-only cmd_swap and cmd_copy
their functions now only return. not needed anymore.

these commands are still available, but they no longer
need helper functions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 22:17:25 +00:00
Leah Rowe 61188ee9dc util/nvmutil: remove redundant checksum checks
we centralise this now. better not to over-engineer
our over-engineering.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 22:11:39 +00:00
Leah Rowe c012d4ea5b util/nvmutil: clean up a few binary checks
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 22:06:09 +00:00
Leah Rowe bd64d118f5 util/nvmutil: fix check in set_err()
errno must never be negative

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 21:37:53 +00:00
Leah Rowe 61e7147505 util/nvmutil: fix bad arc4random check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 21:16:18 +00:00
Leah Rowe c425c74c54 util/nvmutil: improved clarity on checksum check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 21:03:06 +00:00
Leah Rowe 6abc150e89 util/nvmutil: close files in err()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 20:57:30 +00:00
Leah Rowe 840f79fd82 util/nvmutil: only close gbe fd if opened
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 20:50:44 +00:00
Leah Rowe 1400508400 util/nvmutil: generalised checksum verification
the existing verification is retained, an a few commands.

this is an additional security mechanism. redundancy is
best.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 20:43:57 +00:00
Leah Rowe 3330f005fd util/nvmutil: validate ARG_PART and ARG_NOPART
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 17:57:28 +00:00
Leah Rowe 5532a721f5 util/nvmutil: clean up some code
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 17:54:26 +00:00
Leah Rowe 35ffe64765 util/nvmutil: fix 3-arg setmac
3-arg arguments were broken, by recent generalisations.

this should fix it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 17:48:22 +00:00
Leah Rowe a0829f7a27 util/nvmutil: simplified exit error
no more command-specific logic here. this should be the
same in the rest of the code now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 17:24:25 +00:00
Leah Rowe 624ecc4ce1 util/nvmutil: generalise skip-read on copy/brick
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 17:20:36 +00:00
Leah Rowe dd320601c2 util/nvmutil: remove redundant code
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 17:06:41 +00:00
Leah Rowe 3c55808e27 util/nvmutil: call usage() on cmd validation err
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 16:53:24 +00:00
Leah Rowe 37c04ac218 util/nvmutil: generalised cmd copy/swap
now they only set checksums.

and generalised checksumming is next!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 16:06:33 +00:00
Leah Rowe 74224e3dc6 util/nvmutil: print rmac method in setmac
get it out of main(), it's bloat there

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 15:20:26 +00:00
Leah Rowe 08de8d98e9 util/nvmutil: additional flag check on write
gbe_write already checks this, but we should
also check inside the caller.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 15:10:38 +00:00
Leah Rowe b5054f68ba util/nvmutil: don't write gbe file if errno set
nice bit of defense here

we absolutely need this code to be bullet proof

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 15:07:29 +00:00
Leah Rowe 1d630f8e36 util/nvmutil: set errno in xstrxcmp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 15:06:01 +00:00
Leah Rowe 502aeb8653 util/nvmutil: rename word/set_word
they should only access the nvm area, so rename
them accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 14:55:53 +00:00
Leah Rowe e6767d6e47 util/nvmutil: make xstrxcmp() easier to read
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 14:49:57 +00:00
Leah Rowe 6f2e5149f2 util/nvmutil: use N_COMMAND for items(command)
make the code slightly easier to read

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 14:37:25 +00:00
Leah Rowe 10507e1436 util/nvmutil: portable, secure strlen function
xstrxlen ftw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 14:30:36 +00:00
Leah Rowe 9be83fa034 util/nvmutil: use xstrxlen for mac length
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 14:16:32 +00:00
Leah Rowe 4a9aea629b util/nvmutil: use own strnlen function: xstrxlen
strnlen is not available on some older systems,
so now we provide our own portable version.

this version also aborts on NULL input, unlike
the standard function.

this version also does not permit empty strings.

this version also does not permit unterminated
strings.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 14:15:12 +00:00
Leah Rowe 0881b584f4 add util/nvmutil/nvmutil to .gitignore
oops

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 13:32:14 +00:00
Leah Rowe 92bd44676a util/nvmutil: err if arc4random disused on bsd
arc4random is superior, so using /dev/urandom
would be a mistake. we only use that on linux,
or old/weird unix.

we would also use it on linux, but GNU prohibits
nice things (its implementations are spotty, and
old glibc doesn't have it - before 2022 there is
libbsd, but i'm not importing that).

not that it matters. we're not doing encryption.
i'm just a stickler for technical correctness.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 13:32:14 +00:00
Leah Rowe e5d0dee668 util/nvmutil: unified cmd_index reset
use the macro, introduced in the previous commit

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 13:32:14 +00:00
Leah Rowe 1ff1dca661 util/nvmutil: unified cmd validity check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 13:32:14 +00:00
Leah Rowe 5517f81cbe util/nvmutil: commented some defines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 13:32:13 +00:00
Leah Rowe be7c965845 util/nvmutil: rename cmd to cmd_index
to make it clearer what this variable does

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 13:32:13 +00:00
Leah Rowe a7f97f385c util/nvmutil: sanitize the command list
this is a guard against mistakes by future maintainers

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 13:32:11 +00:00
Leah Rowe 8ce1cbe7f4 util/nvmutil: never allow cmd to be negative
make cmd a size_t and make the equivalent to NULL
be the number of items in command[]

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 13:32:09 +00:00
Leah Rowe 0160b26aee util/nvmutil: tidy up set_cmd()
don't set args here

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 13:32:06 +00:00
Leah Rowe de1963fdee util/nvmutil: do cmd bound check
instead of simply checking null, just do a bound check.

this would also cover NULL (-1)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 13:31:59 +00:00
Leah Rowe ccc58cefbb util/nvmutil: rename check_cmd_args
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 03:26:43 +00:00
Leah Rowe ec3ab4059c util/nvmutil: close random_fd only if used
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 03:22:50 +00:00
Leah Rowe 63fcc0891f util/nvmutil: Do not allow /dev/urandom on OBSD
There, we use arc4random_buf which does not directly
access /dev/urandom on BSD; it uses a userspace method
instead, which bypasses this.

This is therefore much more restrictive, which is
exactly the point of unveil(2) and pledge(2); restrict
your program's operation while ensuring that it has what
it needs, to help with debugging and prevent common bugs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 02:47:08 +00:00
Leah Rowe b1866312bd util/nvmutil: rename print_mac_address
the current name is misleading. this function
specifically converts what's stored in memory,
in the nvm.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 02:41:46 +00:00
Leah Rowe 1bbc6ac890 util/nvmutil: only open /dev/urandom on setmac
otherwise, it's a pointless computation

i also added a guard to mitigate this, in the
read file function. this should have been there
anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 02:39:53 +00:00
Leah Rowe 9bd7d04b49 util/nvmutil: say what randomiser is used
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 02:34:26 +00:00
Leah Rowe c1bfe6a438 util/nvmutil: rename command.args to argc
that way, it makes more sense sementantically

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 02:20:13 +00:00
Leah Rowe bf30cdd021 util/nvmutil: fix mistake in command
accidentally specified invert, for the brick
and setchecksum commands. oops!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 02:18:34 +00:00
Leah Rowe 4cdf22cf8f util/nvmutil: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 02:16:30 +00:00
Leah Rowe 7c3a4e253f util/nvmutil: remove stale comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 02:08:40 +00:00
Leah Rowe 26a69321ac util/nvmutil: use enum for command index
if the enum is messed up, this patch also prevents
that. this is not to catch a runtime error, but
to intentionally trip up a maintainer that screws
up, prompting them to fix their future mistake.

we previously used a pointer directly, without
even checking index/NULL - that too is now covered,
except that we now use an indice for command[] and
execute the command from that, rather than directly
declaring a pointer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 02:04:10 +00:00
Leah Rowe 1d17a8ffcf util/nvmutil: call it nvmutil in makefile
a package manager by the name "nvm" exists, as
i discovered.

this is a courtesy to them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 01:11:52 +00:00
Leah Rowe 6203f3ae61 util/nvmutil: print mac before setting
this way, if a user does e.g.

./nvm gbe.bin bullshit

It will say: bullshit

Right now, it just says invalid length. This
means if the user wanted to type e.g.

./nvm gbe.bin copy 0

but they typed:

./nvm gbe.bin coyp 0

Now it will tell them that it's trying
to set the MAC address "coyp".

This is because if an invalid command is given,
it's treated as a MAC address instead. This is
by design, to allow e.g.

./nvm gbe.bin xx:1x:1x:xx:xx:xx

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 01:11:52 +00:00
Leah Rowe 698d39dd06 util/nvmutil: store invert in command struct
handle inversion directly there

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 00:21:58 +00:00
Leah Rowe 50e20fb8bf util/nvmutil: make cmd an integer
point directly to the command table.

run through an intermediary function to check
bounds, for safety.

this will allow me to then set things like
the invert config directly in that struct.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-08 00:16:45 +00:00
Leah Rowe 3148d31798 util/clarity: name the gbe file half size
we need only declare it in the centralised gbe_file_offset
function, which determines whether a write to the gbe file
falls specifically within the 4KB range that is the gbe
part.

it is always half of the gbe file size, and then the first
4KB of each half stores the gbe part.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 13:36:46 +00:00
Leah Rowe 96cb52f21a util/nvmutil: only have newrandom on linux/oldunix
these variables newrandom and oldrandom are unused on
BSD systems, and their unused status may trigger
warnings on some compilers.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 13:18:54 +00:00
Leah Rowe c195e8cc2b util/nvmutil: tidy up open_dev_urandom
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 10:07:05 +00:00
Leah Rowe 6a505c9162 util/nvmutil: correct type on hextonum()
use uint16_t instead

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 03:28:15 +00:00
Leah Rowe 50ce806dfa util/nvmutil: fix a comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 03:16:20 +00:00
Leah Rowe a0da88d361 util/nvmutil: fix a comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 03:08:31 +00:00
Leah Rowe ea1046dc46 util/nvmutil: unambiguous sign conv_argv_part_num
yeah, do the verification manually, don't convert
to size_t. this avoids a bunch of theoretical
bugs that i can't be bothered to explain at 3AM

just trust me bro

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 03:00:35 +00:00
Leah Rowe b98f89c272 util/nvmutil: clean up hextonum()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 02:50:30 +00:00
Leah Rowe b8bd1ca65a util/nvmutil: tidy up some comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 02:44:11 +00:00
Leah Rowe 49eca198da util/nvmutil: make mac_updated a uint8_t
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 02:38:36 +00:00
Leah Rowe ef2937edbd util/nvmutil: fix prototype indentation
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 02:37:46 +00:00
Leah Rowe 7bfe134a19 util/nvmutil: reset mac_buf for mac parsing
preventative fix for later, if the tool is ever expanded
to have a better command syntax, for supporting more than
one file at a time.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 02:35:03 +00:00
Leah Rowe 14ad5a9818 util/nvmutil: comment the unhandled errno exit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 02:09:56 +00:00
Leah Rowe 90bd395cb1 util/nvmutil: tidy up set_mac_byte
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 02:05:57 +00:00
Leah Rowe 4619dad0b7 util/nvmutil: further mac address parsing cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 02:00:14 +00:00
Leah Rowe 921144856c util/nvmutil: tidy up mac parsing code
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 01:39:57 +00:00
Leah Rowe 86357dbe52 util/nvmutil: fix a bad comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 01:28:50 +00:00
Leah Rowe 7e88f53e99 util/nvmutil: tidy up set_mac_byte
send the mac address byte directly to check_mac_separator

functionally identicaly, but cleaner, and uses
multiplication instead of division (faster).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 01:21:29 +00:00
Leah Rowe c02f3166bb util/nvmutil: make do_read a uint8_t
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 01:11:07 +00:00
Leah Rowe a9f5cbb542 util/nvmutil: clearer commenting about commands
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 01:09:52 +00:00
Leah Rowe 0084452c4a util/nvmutil: comment regarding buf
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 01:01:44 +00:00
Leah Rowe 364abddeab util/nvmutil: minor code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 00:52:57 +00:00
Leah Rowe 68d689336b util/nvmutil: fix an err string
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 00:10:36 +00:00
Leah Rowe 658ed55bc1 util/nvmutil: tidy up conv_argv_part_num
no need for strlen here (1-character string).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 00:08:17 +00:00
Leah Rowe 330b2da20c util/nvmutil: Shorten a comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 00:04:57 +00:00
Leah Rowe 58182b48c3 util/nvmutil: fix a bad comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 00:03:10 +00:00
Leah Rowe 884a6779f9 util/nvmutil: make gbe_st local, not static/global
forgot to remove static when making it local

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-07 00:01:27 +00:00
Leah Rowe 44e6b00626 util/nvmutil: rename rfd to urandom_fd
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 23:58:04 +00:00
Leah Rowe 9e5736baa9 util/nvmutil: remove reset_global_state
it was put there for another change i haven't done yet,
and probably won't. the program currently just runs once
with one operation, on a given file.

the current defaults are initialised just fine without
this function, so let's remove this bloat for now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 23:56:19 +00:00
Leah Rowe 13b35ed1fc util/nvmutil: rename arc4random define
specifically refer to the actual function i use.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 23:51:57 +00:00
Leah Rowe 79c972367e util/nvmutil: reset errno on /dev/random fallback
i didn't catch this before. stale error state would
have passed through, even on ultimate success.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 23:50:06 +00:00
Leah Rowe 6e47315192 util/nvmutil: remove rval from conv_argv_part_num
relic from an earlier uncommitted version

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 23:42:33 +00:00
Leah Rowe 85b09c4275 util/nvmutil: set part_modified to a uint8_t
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 23:15:50 +00:00
Leah Rowe e5b108a764 util/nvmutil: make invert a uint8_t
cleaner intention, and shorter

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 23:14:26 +00:00
Leah Rowe 69c4d70650 util/nvmutil: safer argv part number parsing
we now handle signedness properly, which is implementation
defined, on char integers where signed/unsigned is not
specified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 23:07:29 +00:00
Leah Rowe 9b6f2a2f7e util/nvmutil: rename check_bound check_nvm_bound
this makes the intent clearer, because we only want to
access the 128-byte nvm area here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 22:39:43 +00:00
Leah Rowe a7d7f68a5c util/nvmutil: be clearer about GbE file sizes
the partsize variable is also misleading, because it
refers to the full half of a file, which might be
bigger than 4KB. this variable name is a hangover
from when nvmutil only supported 8KB files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 22:36:08 +00:00
Leah Rowe e273391792 util/nvmutil: rename fd to fd_ptr in xopen()
clearer intent

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 22:26:22 +00:00
Leah Rowe 4635a0eae9 util/nvmutil: cleaned up a few prototypes
make them match how they're declared

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 22:20:15 +00:00
Leah Rowe 0f5fcbd883 util/nvmutil: more readable xopen
match the argument names of openbsd open(2)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 22:18:26 +00:00
Leah Rowe 2c2bda31ea util/nvmutil: use unsigned char in hextonum
char can be signed or unsigned, and this is often
implementation-defined. this could result in bad
comparisons, so we should specifically cast it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 22:09:56 +00:00
Leah Rowe f57358ac1e util/nvmutil: remove redundant break
err takes care of it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 21:43:11 +00:00
Leah Rowe f59f45893b util/nvmutil: rename write_gbe to write_gbe_file
for clarity

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 21:39:58 +00:00
Leah Rowe 85877a93bb util/nvmutil: rename read_gbe to read_gbe_file
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 21:39:21 +00:00
Leah Rowe dad1f613fc util/nvmutil: unified partnum validation
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 21:35:49 +00:00
Leah Rowe ed32108613 util/nvmutil: rename global st variable
rename it to gbe_st, for clarity

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 21:22:50 +00:00
Leah Rowe b65c988007 util/nvmutil: full prototypes
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 21:21:40 +00:00
Leah Rowe 3aa30c5039 util/nvmutil: tidy up read_gbe
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 21:08:47 +00:00
Leah Rowe 040eee4607 util/nvmutil: tidy up set_mac_nib
simplify it again

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 21:06:58 +00:00
Leah Rowe 6b924787be util/nvmutil: remove unnecessary checck
the for loop exits when setting cmd

checking for NULL is pointless

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 20:59:50 +00:00
Leah Rowe af55dd8959 Revert "util/nvmutil: make invert an unsigned char"
This reverts commit 5b120d71e7.

the others are unsigned char. other variables like this one.

better be consistent.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 20:58:04 +00:00
Leah Rowe 10c8be92aa util/nvmutil: general code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 20:52:13 +00:00
Leah Rowe a34d430754 util/nvmutil: cleaner mac address variable names
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 20:34:20 +00:00
Leah Rowe 00e0197cfe util/nvmutil: general code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 20:11:30 +00:00
Leah Rowe 5b120d71e7 util/nvmutil: make invert an unsigned char
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:59:51 +00:00
Leah Rowe 4bf190a5f5 util/nvmutil: make mac_updated unsigned
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:58:37 +00:00
Leah Rowe 5c90b2453b util/nvmutil: use size_t in setmac functions
not int

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:57:39 +00:00
Leah Rowe fb805caf6a util/nvmutil: extra part check in set_checksum
it calls word() anyway, but we should still check it here,
since this is quite a critical function.

the other bound checks are done by word(), which this
function uses to add everything up.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:40:28 +00:00
Leah Rowe f316701d74 util/nvmutil: don't set part in write_mac_part
make a helper for cmd_setchecksum with size_t arg,
and use it in write_mac_part.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:35:54 +00:00
Leah Rowe c6c4e5303e util/nvmutil: fix duplicated word in comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:30:55 +00:00
Leah Rowe 5d05921875 util/nvmutil: make part_modified an unsigned char
better reflects intent

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:28:32 +00:00
Leah Rowe 1aa8f33d50 util/nvmutil: fix bad string in gbe_read_part()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:25:54 +00:00
Leah Rowe 9095722079 util/nvmutil: calculate off AFTER part validation
because we check the part first, so we need to know it's
valid before proceeding.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:23:56 +00:00
Leah Rowe 1131240d02 util/nvmutil: made a comment a bit clearer
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:21:02 +00:00
Leah Rowe 72caa5f892 util/nvmutil: fix another printf specifier
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:17:01 +00:00
Leah Rowe efdf110317 util/nvmutil: remove unnecessary casts
now that part numbers are size_t, i don't need them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:08:55 +00:00
Leah Rowe d94fbba779 util/nvmutil: fix more bad printf statements
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:04:38 +00:00
Leah Rowe 6d2a1afbd4 util/nvmutil: fix a few bad printf statements
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 19:03:06 +00:00
Leah Rowe 0698c6ada4 util/nvmutil: warn about partial gbe file writes
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 18:55:31 +00:00
Leah Rowe 397fc78e58 util/nvmutil: use size_t for part numbers
not int

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 18:45:26 +00:00
Leah Rowe 82fdee91fa util/nvmutil: clean up file handling
inline check_read_or_die

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 18:36:29 +00:00
Leah Rowe 58b17c98fd util/nvmutil: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 18:25:24 +00:00
Leah Rowe c8bd98c8a6 util/nvmutil: mem bound check on file read/write
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 18:17:07 +00:00
Leah Rowe 41f7f6352d util/nvmutil: rename gbe_bound for clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 17:47:49 +00:00
Leah Rowe b1abef8881 util/nvmutil: make defines easier to understand
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 17:44:07 +00:00
Leah Rowe edca6c2cd3 util/nvmutil: tidy up set_mac_nib
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 17:35:00 +00:00
Leah Rowe 123e77d07f util/nvmutil: use portable printf on hexdump
lx means unsigned long, and row is size_t which often
is, but this is not guaranteed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 17:31:04 +00:00
Leah Rowe c0a77a7301 util/nvmutil: make the MAC shifting easier to read
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 17:22:31 +00:00
Leah Rowe 596643a0d5 util/nvmutil: optimise hextonum
there is 0x20 of different between a and A

so we can just or 0x20 and compare only lowercase.

we can also cast char (which may me signed on some
systems) to unsigned, and then only check whether
it's lower than 10.

this code results in far less branching (in C),
but a good optimising compiler probably wouldn't
have cared about the old version anyway.

it's just nicer C code.

this also means we no longer need to check for
X, only x.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 17:07:12 +00:00
Leah Rowe 6023d17b6e util/nvmutil: fix parenthesis warning in GCC
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 17:01:48 +00:00
Leah Rowe 199dbad96d util/nvmutil: tidy up set_mac_nib
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 16:55:23 +00:00
Leah Rowe 9e32456c8c util/nvmutil: clearer intent on struct data
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 16:52:02 +00:00
Leah Rowe 7ae2288c10 util/nvmutil: more readable NVM defines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 16:49:41 +00:00
Leah Rowe 2f0c189da9 util/nvmutil: more readable SIZE_nKB defines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 16:46:01 +00:00
Leah Rowe 7f6d7526cc util/nvmutil: use arc4random on DragonFly BSD
it has arc4random, so we will use it there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 16:43:18 +00:00
Leah Rowe a358a6fe09 util/nvmutil: use strlen instead of strnlen
strnlen isn't available on some older unices.

we already know the string will be null-terminated,
because it comes from argv, so runaway reads are
extremely unlikely (read: impossible).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 16:41:59 +00:00
Leah Rowe a82c766b8c util/nvmutil: add bound checks for gbe read/write
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 16:29:45 +00:00
Leah Rowe 94f5e70366 util/nvmutil: minor code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 16:05:21 +00:00
Leah Rowe 0d4cc9e324 util/nvmutil: clearer macbuff init in set_mac_nib
and 1 does the same thing as mod 2, but it's cleaner.

i also now bitshift 3 times instead of times by 8,
which again is clearer in purpose.

i line breaked after h, to make it clear that all of
the next part is being shifted in

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 15:51:46 +00:00
Leah Rowe 7950a31c79 util/nvmutil: don't reset rfd on openbsd
it isn't defined there

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 15:02:46 +00:00
Leah Rowe 99543bc632 util/nvmutil: tidy up rhex()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 14:59:35 +00:00
Leah Rowe a4b9a333a9 util/nvmutil: properly handle sizeof in rhex()
sizeof is size_t, so we must act accordingly.

casting it to an int is unacceptable.

this version is also branchless.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 14:53:36 +00:00
Leah Rowe cc47a756f2 util/nvmutil: make rmac an array, not a literal.
this prevents reassignment.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 14:42:57 +00:00
Leah Rowe e7cbd9441c util/nvmutil: use arc4random when available
fall back to urandom.

also add a /dev/random fallback, for older unices.

with the posix compatibility changes, combined with
this change as above, the code should be portable
now. i expect it to compile on *many* unix systems!

pretty much everything from the last 30 years.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 14:42:29 +00:00
Leah Rowe 95b294db05 util/nvmutil: inline pos calculation on word()
we don't need a whole function. i previously did it
for clarity, but simply setting a variable all in
one line is totally fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 13:49:33 +00:00
Leah Rowe d89d14e911 util/nvmutil: remove pointless check
the input is already size_t, which is unsigned

there's no point in checking for negative

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 13:37:38 +00:00
Leah Rowe f96a119523 util/nvmutil: cast inside check_bound, not callers
the purpose of the cast is to check whether a given
integer would underflow under any circumstance.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 13:33:42 +00:00
Leah Rowe a31236b1f8 util/nvmutil: comment regarding endianness
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 13:30:14 +00:00
Leah Rowe c7409cce03 util/nvmutil: clean up set_word
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 13:28:51 +00:00
Leah Rowe feee6a728f util/nvmutil: use size_t for offsets in words
size_t is generally the size of the address space, so
this is more reliable for our purposes; we're only
working on small buffers, but even so, it's a good
thing to do.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 13:28:04 +00:00
Leah Rowe 32429f2c37 util/nvmutil: remove the swap() function
directly handle swapping in word and set_word

in my testing, x86_64 and arm64 compilers actually produce
more efficient code this way. i previously only did a big
swap on the whole buffer on big-endian CPUs, and directly
accessed without swaps on little-endian, as an optimisation.

however, the old code is actually slower than what the
compiler produces, with the new code!

portability is retained with big-endian host CPUs and
little-endian host CPUs.

this also avoids the complication of memcpy and is just
generally extremely reliable by comparison.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-06 13:02:24 +00:00
Leah Rowe b3516e8c16 update nvmutil COPYING file (2026 copyright year)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 11:25:07 +00:00
Leah Rowe 2f2295fc37 util/nvmutil: rhex: don't read twice!
we currently never read the 0th byte, so if we need
all 12, and we do when every byte is random, we
read again just to get one byte.

not really a bug, but it is a performance penalty,
so let's fix it!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 10:45:00 +00:00
Leah Rowe aceafd684a util/nvmutil: unified file read error handling
it must be read perfectly, or else

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 02:34:44 +00:00
Leah Rowe 947211fc3c util/nvmutil: tidy up cmd_brick
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 02:06:33 +00:00
Leah Rowe 2f782b8a01 util/nvmutil: minor code cleanup
mostly style changes

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:59:21 +00:00
Leah Rowe f727675f6d util/nvmutil: provide comment about global state
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:48:41 +00:00
Leah Rowe d6601059fb util/nvmutil: reset errno on *successful* read
otherwise, stale errno from an earlier syscall might
cause a valid read to still fail.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:43:39 +00:00
Leah Rowe 84b4ba48b4 util/nvmutil: don't reset errno in check_read_or_die
we want to debug it after the fact; this is now handled,
in the calling functions (unhandled error exceptions).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:39:34 +00:00
Leah Rowe 94415ca73d util/nvmutil: minor code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:39:11 +00:00
Leah Rowe 75ea8ab175 util/nvmutil: comment regarding memcpy endianness
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:32:34 +00:00
Leah Rowe ca98d418d5 util/nvmutil: don't usleep on file reads
i don't care. it's only 30 tries.

usleep can fail, setting errno, and it can actually
take longer, depending on the environment. it poisons
errno, and makes debugging harder.

just remove it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:29:30 +00:00
Leah Rowe e28409d80b util/nvmutil: handle error after check_read_or_die
we already exit reliably in that function. the current code
is logically correct, but very weak against future changes.

this extra check is essentially redundant, but prevantative
against future changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:27:13 +00:00
Leah Rowe 7d6f1a6b30 util/nvmutil: handle errno after file read
errno shouldn't be set, after reading a file successfully.

if it is, that's a bug. handle it accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:23:19 +00:00
Leah Rowe 12778a0ffd util/nvmutil: simplified zero-mac-address check
it's just three words. access them directly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:12:11 +00:00
Leah Rowe 84376fa308 util/nvmutil: don't pass h as param in cmd_setmac
it's only needed in one function (tmp variable).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:09:56 +00:00
Leah Rowe 0d4822e700 util/nvmutil: cast SIZE_4KB on the pwrite check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 01:02:42 +00:00
Leah Rowe 0d3a8749fe util/nvmutil: usleep 1 on check_read_or_die
This prevents hogging the CPU in a tight loop,
while waiting for access.

I've also reduced the number of tries to 30, rather
than 200. This is more conservative, while still
being somewhat permissive.

The addition of the usleep delay probably makes
this more reliable than the previous behaviour of
quickly spinning through 200 tries, but without
hogging CPU resources.

I *could* allow this loop to be infinite, but
I regard infinite spin-lock as an error state.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 00:57:48 +00:00
Leah Rowe 3d27c77a63 util/nvmutil: reset errno on successful file reads
a non-fatal error could have set errno. when we return
from check_read_or_die(), it should be assumed that
all is well.

i don't think this would mask anything important, but
it may be regarded as a preventative bug fix, since
it most likely only prevents false-positives.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 00:52:40 +00:00
Leah Rowe 6e08614e69 util/nvmutil: reset fd/rfd to negative one
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 00:51:24 +00:00
Leah Rowe 8143f95b41 util/nvmutil: reset buf in reset_global_state()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 00:47:45 +00:00
Leah Rowe 3e7148a9b7 util/nvmutil: reset macbuf in reset_global_state
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 00:46:42 +00:00
Leah Rowe 53a680c063 util/nvmutil: reset errno in reset_global_state
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 00:44:47 +00:00
Leah Rowe 46a0fe6b8a util/nvmutil: Comments relating to NVM size limit
Part of the code currently assumes we only work on
the smaller NVM area.

I'm adding some comments to make this clear, for
when and if the code is ever expanded to support
operating on the Extended NVM area (just part the
main 128-byte NVM area).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 00:41:08 +00:00
Leah Rowe 4b42419122 util/nvmutil: remove err_if()
use of it was preventing more verbose error messages
on exit.

the code is actually cleaner without it, and easier
to read, because of those verbose error messages.

i also added some comments to cmd_swap/copy and did
some other minor/related cleanup elsewhere.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 00:30:28 +00:00
Leah Rowe 6efd0429e2 util/nvmutil: improved some error messages
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 00:07:14 +00:00
Leah Rowe 6035a1bb6a util/nvmutil: rename valid_read
it doesn't just validate, but also exits.

rename it accordingly, to: check_read_or_die

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-04 00:01:28 +00:00
Leah Rowe be28140741 util/nvmutil: remove redundant casts
these just bloat the code

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:55:46 +00:00
Leah Rowe 3b8de31f37 util/nvmutil: more thorough global_state_reset
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:46:01 +00:00
Leah Rowe 704a7beeb4 util/nvmutil: reset fname properly
do it after resetting global state.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:42:15 +00:00
Leah Rowe 489f632cab util/nvmutil: simpler mac address totalling
i know it's always going to be 3

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:40:28 +00:00
Leah Rowe 76d6900d69 util/nvmutil: less obscure mac address zero check
make it totally clear what's going on.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:37:59 +00:00
Leah Rowe 8c5c4e1b93 util/nvmutil: reset global state in one function
split it out of main. this is good hygiene and it's preparation
for a planned expansion in the future, that allows operation
on multiple files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:29:45 +00:00
Leah Rowe 213626d898 util/nvmutil: reset cmd in main
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:24:46 +00:00
Leah Rowe 306f9087d9 util/nvmutil: reset fname in main
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:23:54 +00:00
Leah Rowe d0141ca2e4 util/nvmutil: reset part_modified in main
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:23:28 +00:00
Leah Rowe 1e407a2a65 util/nvmutil: reset invert in main
currently redundant, but again i might expand this
in the future to allow multiple runs. putting this
here as good practise (currently redundant).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:22:14 +00:00
Leah Rowe dd109ccf07 util/nvmutil: reset mac in main
we currently only run the logic once, but i might
expand nvmutil in the future, so that it can
operate on multiple files. this would require
using a different command syntax, e.g. getop-style
syntax.

this is a preventative bug fix, resetting global
state.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:19:33 +00:00
Leah Rowe 790009f58e util/nvmutil: reset macbuf in parse_mac_string
we only ever use it once, so it's fine, but future
expansion of this code might trip us up.

this is therefore a preventative bug fix.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:17:02 +00:00
Leah Rowe 7b15b020b5 util/nvmutil: use off_t for partsize (pread/pwrite)
size_t can truncate on some platforms. it's best to use
the proper variable type (a cast is insufficient).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:12:15 +00:00
Leah Rowe ae080c35e4 util/nvmutil: clearer error messages on valid_read
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:09:54 +00:00
Leah Rowe 75bcc46de4 util/nvmutil: comment valid_read for clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 23:00:17 +00:00
Leah Rowe 7a62ad3f62 util/nvmutil: clearer errno reset in valid_read
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 22:57:45 +00:00
Leah Rowe 3268c225d6 util/nvmutil: pass size_t to read, not ssize_t
ssize_t is signed, which could be negative.

in practise, we control the value that's going in anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 22:57:18 +00:00
Leah Rowe 3077f51c67 util/nvmutil: use zd for printf in valid_read
more portable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 22:51:50 +00:00
Leah Rowe cc51ac32d0 util/nvmutil: minor cleanup in usage()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 22:32:24 +00:00
Leah Rowe ae6db44543 util/nvmutil: minor cleanup in cmd_setmac
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 22:29:21 +00:00
Leah Rowe 8f81ed314a util/nvmutil: don't use err_if in usage
fname isn't set here, and fname is used in err_if

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 22:27:51 +00:00
Leah Rowe f93a40ecb6 util/nvmutil: rename errval to nvm_errval
strtonum implementations in bsd sometimes have this
variable name. rename it to avoid conflict.

also removed the commentt errno values, since i'm
only ever setting it to valid values, as are the
syscalls that i'm using, so it should be ok.

i'm not writing a stub to check errno. that would
be far beyond the scope of nvmutil.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 21:51:13 +00:00
Leah Rowe 21b8de87ff util/nvmutil: re-try reads if errno is EINTR
this is a bit of fault tolerance. a bit bloated too,
but it should make the code more resilient.

we limited the number of retries to 200 retries.

EINTR is when the syscall (read/pread) is interrupted.

we still error out on other conditions; we also still
error out on EINTR if the number of re-tries surpasses
200.

during this re-try loop, if *another* error occurs, we
exit as normal. this is done for both files: the gbe
file, and /dev/urandom.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 21:43:32 +00:00
Leah Rowe 493e3cf069 util/nvmutil: explicitly cast on read/pread/pwrite
these functions return ssize_t, so compare explicitly
to that, when using the SIZE_4KB define for example.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 20:38:36 +00:00
Leah Rowe af5d876bf0 util/nvmutil: remove unnecessary check
we can just use errval as argument to set_err,
because set_err itself now properly handles
errno, ensuring that is is never set to zero.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 20:30:52 +00:00
Leah Rowe 418015c232 util/nvmutil: stricter check_bound
word/set_word are only meant to operate on the nvm
area (128 bytes), but the current check is against
the entire 4KB block.

swap() only handles the nvm area, as per the design
of nvmutil.

this patch makes the boundary check truer to my real
intent, guarding against future logical errors.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 20:24:26 +00:00
Leah Rowe 80a5b08090 util/nvmutil: set errno only if x is not 0
otherwise, some minor edge cases may result in err
printing "success", when we want to signal an error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 20:15:39 +00:00
Leah Rowe 3f7d89c401 util/nvmutil: consistent errors on close()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 19:59:35 +00:00
Leah Rowe fd515e4c28 util/nvmutil: print correct file name for urandom
err_if reports fname, not /dev/urandom

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 19:53:09 +00:00
Leah Rowe f4e477b549 util/nvmutil: don't bother with strncmp
these are strings provided from the shell, which are
guaranteed to always be null-terminated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 19:51:25 +00:00
Leah Rowe 687e64a359 util/nvmutil: get rid of arg_cmd
it's pointless.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 19:48:48 +00:00
Leah Rowe 776eee721d util/nvmutil: use memcpy in word/set_word
alignment isn't an issue, but aliasing between uintX_t
types in C means that this code may fail on some weird
systems.

using memcpy here is advisable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 19:41:21 +00:00
Leah Rowe d88991f6bc util/nvmutil: use strncmp instead of strcmp
set a constant maximum length. this seems reasonable,
and it's even quite generous.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 19:18:47 +00:00
Leah Rowe bf081914a3 util/nvmutil: remove checkdir()
we don't need it. what follows is a call to open(), which
would fail anyway if the path is a directory; further, this
removes a theoretical race condition in the program, and
makes open() happen sooner, making it more likely that we
get the file first, before another program can take it.

checking whether /dev/urandom is a directory is the height
of absurdity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 19:11:20 +00:00
Leah Rowe 4325214d82 util/nvmutil: make rhex err_if consistent
n + 1 is the same as saying sizeof(rnum) in this case.
we should be clear about that, in code. n is irrelevant
here, since it is only an index for the return value.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 19:03:58 +00:00
Leah Rowe 668dec36e9 util/nvmutil rhex: check against sizeof(rnum)
checking against -1 is incorrect, because we specifically want
to ensure that it always read the number of bytes defined by
the size of rnum.

this still covers the case where the return value is -1, and
therefore makes the error handling much stricter.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 19:00:14 +00:00
Leah Rowe 4775bb2348 util/nvmutil err: filter errval when zero
default to ECANCELED if zero

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 18:54:58 +00:00
Leah Rowe 634f4a685d util/nvmutil: always exit non-zero on err
the way err works here now is very different than
the bsd one. here, we ALWAYS exit with EXIT_FAILURE,
and we call set_err with, as argument, the first
argument given to err.

this then sets errno, but the exit value is always
consistent.

that's what happens when i control err(). i make it
even better. the original bsd one is too conservative.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 18:47:14 +00:00
Leah Rowe 3af94efc16 util/nvmutil: more consistent output in usage()
and use getnvmprogname

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 18:03:27 +00:00
Leah Rowe 2faea7d890 util/nvmutil: use getnvmprogname in usage
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 18:00:19 +00:00
Leah Rowe 9b18d11878 util/nvmutil: use own implementation of err
and getprogname, written as getnvmprogname

this removes a dependency on err.h, which is non-standard.

the remaining code is posix-compliant, or ifdef'd where
use of openbsd pledge is concerned - someone could theoretically
define __OpenBSD__ that isn't and OpenBSD base maintainer, and
then use nvmutil in it, but i so don't care about that evermore
hypothetical individual.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 17:57:27 +00:00
Leah Rowe 0a08045f92 util/nvmutil: close rfd on exit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 17:30:55 +00:00
Leah Rowe 7c0eb780a9 util/nvmutil: remove unnecessary include
dirent.h is no longer needed, because i'm no longer
making use of opendir()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 17:13:03 +00:00
Leah Rowe 8faa36eb64 util/nvmutil: tidy up write_gbe
by handling close() in main, we can reduce the
indendation in write_gbe and generally make it
much easier to read.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 17:09:33 +00:00
Leah Rowe 86665c9d22 util/nvmutil: make the part check easier to read
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:53:01 +00:00
Leah Rowe 531f0c9d38 util/nvmutil: fix style inconsistency
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:45:54 +00:00
Leah Rowe b03a532c7d util/nvmutil: use braces on nested ifs
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:43:48 +00:00
Leah Rowe 5bae73c319 util/nvmutil: remove unnecessary global assignment
these integers are already initialised to zero.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:39:19 +00:00
Leah Rowe faf28691b8 util/nvmutil: make swap() easier to understand
the swap function reverses the byte order in memory, of
a loaded GbE after after reading it, or before writing
it. this is required (as detected) on big-endian CPUs,
because GbE files store bytes in little-endian order.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:37:55 +00:00
Leah Rowe 624589fcb1 util/nvmutil: declare arg_cmd earlier
set it after the argc check

i don't like initialising a const after
declaration, but it compiles, and it keeps
with the style used in the rest of the code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:29:40 +00:00
Leah Rowe 3983dc44f4 util/nvmutil: don't make op a typedef
it's not required

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:26:58 +00:00
Leah Rowe 49c2940421 util/nvmutil: fix arg_cmd initialisation
i declare it, using the 3rd argument, which might
not be available if only the file name is declared.

this fixes that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:20:51 +00:00
Leah Rowe 61fa94d0d2 util/nvmutil: remove COMMAND, MAC_ADDRESS, PARTN
these macros serve no purpose except to obfuscate the
code. it's actually cleaner just to refer directly to
argv, and it reduces the chance of contamination later
upon re-factoring.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:15:33 +00:00
Leah Rowe b3119c8b4d util/nvmutil: rename op_t to op
and op to ops

typedefs not part of any base system e.g. openbsd
base system, or e.g. the libc, should not have _t
in them.

this is a stylistic change, and does not alter any
actual program behaviour.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:06:02 +00:00
Leah Rowe f03570b674 util/nvmutil: make op a const
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:04:43 +00:00
Leah Rowe d267cd36cc util/nvmutil: remove redundant comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 16:03:23 +00:00
Leah Rowe 7fefeba076 util/nvmutil: use const char in usage
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:58:46 +00:00
Leah Rowe f1ee2ff630 util/nvmutil: tidy up set_cmd
reduced indentation

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:56:06 +00:00
Leah Rowe 6d8cf8909f util/nvmutil: split up set_cmd
the second half of the function is mostly checking
arguments, and has the hack to set cmd to cmd_setmac
if cmd is unset (no command specified) but argc is
above two.

stylistically, this is more consistent.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:50:20 +00:00
Leah Rowe 9f12aa3b91 util/nvmutil: tidy up final cmd check in set_cmd
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:47:01 +00:00
Leah Rowe 572b7758cf util/nvmutil: tidy up rhex
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:43:11 +00:00
Leah Rowe 403fd260b5 util/nvmutil: reduce the size of rnum to 12
we only need 12 bytes at a maximum

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:41:21 +00:00
Leah Rowe d9d628e146 util/nvmutil: tidy up check_mac_separator
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:40:33 +00:00
Leah Rowe 036ac6dc39 util/nvmutil: rename openFiles to open_files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:31:31 +00:00
Leah Rowe 48638e9a22 util/nvm: make variables and functions static
i don't intend for this to be used in a library

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:20:20 +00:00
Leah Rowe dbfd77b388 util/nvmutil: don't use spaces on err_if
this is inconsistent with the style in the rest of
the code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:08:57 +00:00
Leah Rowe bfb77077b3 util/nvmutil: use const for string literal in op
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:06:39 +00:00
Leah Rowe a8a9ce32f1 util/nvmutil: no designated initialisers in op
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:04:39 +00:00
Leah Rowe 5517cf923b util/nvmutil: declare one prototype per line
in the same order that functions are declared

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 15:02:15 +00:00
Leah Rowe e4e5022ab3 util/nvmutil: don't declare variables in for loops
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 14:50:33 +00:00
Leah Rowe 198843c2e3 util/nvmutil: use size_t on op for loop
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 14:43:16 +00:00
Leah Rowe 4edcc26849 util/nvmutil: make global variable names clearer
each variable is declared on its own line.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 14:37:10 +00:00
Leah Rowe 91879b7606 util/nvmutil: count the number of items in op
don't hardcode it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 14:33:46 +00:00
Leah Rowe d37726c353 util/nvmutil: set fname earlier
this fixes the bug where if you specify an invalid command
such as:

./nvm gbe brick 9

part 9 doesn't exist, but fname isn't yet set, here.

same thing applys when running those pledge commands on
openbsd.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 14:24:19 +00:00
Leah Rowe 65a2f352ee util/nvmutil: obey the 79-character rule
only 79 characters or less, per line.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 14:15:36 +00:00
Leah Rowe b8091c7bdc util/nvmutil: use spaces when calling err_if
this is separate from other function calls. err_if
is used as though it was an if, where we always add
a space. it's just a quirk of my coding style.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 14:14:06 +00:00
Leah Rowe 23cdfdd00a util/nvmutil: consistent variable/function naming
use the same naming scheme throughout

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 14:12:52 +00:00
Leah Rowe 8812a17683 util/nvmutil: use the invert in goodChecksum
this way, the correct part number is printed when an invalid
part is being operated on, in cmd copy or swap.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 13:38:39 +00:00
Leah Rowe 3bdefad097 util/nvmutil: readGbe: use inverted part in swap
i overlooked this in a previous modification

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 13:23:20 +00:00
Leah Rowe 50942a7a15 util/nvmutil: clean up write_mac_part
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 13:19:22 +00:00
Leah Rowe d4231e27fa util/nvmutil: clean up cmd_dump
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 13:17:21 +00:00
Leah Rowe 9044b55c48 util/nvmutil: don't copy data in copy/swap
instead, use a single integer, set to 1 if using
these commands (otherwise set to 0) used as an XOR
mask.

use this to invert where data gets read. one quirk
with this is that if a copy operation is performed
from a part with a bad checksum, it's already done
in advance, in memory, but then the check on the
checksum in cmd_copy is now checking the other part,
which will be all zeroes, so i invert that too; this
means now when running cmd_copy, it'll complain about
an invalid part, but the part number is inverted.

it's a small price to pay, because this restores the
previous performance optimisations but without being
as unsafe.

this is also true when doing the swap.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 13:07:39 +00:00
Leah Rowe 98bc523274 util/nvmutil: re-introduce do_read in readGbe
lots of block devices use 4KB block size. it makes
sense to have this optimisation here.

i previously removed it, along with the one that
only reads the NVM area - that one is still gone,
because it was largely pointless.

because of this modification returning, i also
re-introduced the check in setWord against
nvmPartModified - otherwise, for example, running
cmd brick 0 would brick part 0 but then write
all zeroes to part 1.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 12:40:50 +00:00
Leah Rowe 6770fa8ef2 util/nvmutil: use read, not pread, on /dev/urandom
we always read from offset zero, so use read

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 12:31:53 +00:00
Leah Rowe 188a3d012b util/nvmutil: clean up checkdir
those lines at the end are a hangover from the old opendir-
based implementation.

i also made the output more verbose in that first error
check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 04:17:25 +00:00
Leah Rowe c64324467f util/nvmutil: use separate st variable for urandom
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 04:13:21 +00:00
Leah Rowe 1c10eb524f util/nvmutil: cleaner directory checking
opendir allocates resources and causes a bunch of other
error conditions which we need to catch.

use of stat is more efficient here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 04:11:29 +00:00
Leah Rowe b8e0513123 util/nvmutil: initialise fname to empty string
otherwise, early calls to err_if make use of a NULL string
inside err()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 03:57:39 +00:00
Leah Rowe de5087bbd5 util/nvmutil: fix code formatting on xopen
it still had some leftovers from the old macro-style
implementation. it still compiled, but this patch
fixes the function properly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 03:55:12 +00:00
Leah Rowe efe2635c12 nvmutil: fix the swap function
irrelevant for most users, who are on little endian
anyway, but i broke the swap function on big endian
systems. this fixes it.

the new function uses an intermediate variable instead
of xor swapping, but i accidentally left some relics of
of the old xor swaps in place. this fixes that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 03:50:22 +00:00
Leah Rowe c721d6f4f4 util/nvmutil: use EXIT_FAILURE/SUCCESS for exits
this, in conjunction with the centralised exit scheme now
used by nvmutil, means that we have portable exit status.

notwithstanding the use of non-portable unix functions, and
especially the use of non-standard err.c (which GNU and BSD
libc implementations all have anyway, as does musl).

this code should now run on essentially any computer with
Linux or BSD on it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 03:43:06 +00:00
Leah Rowe e4b8bb4875 util/nvmutil: make err_if a function, not a macro
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 03:38:45 +00:00
Leah Rowe c98d5c743f util/nvmutil: properly cast void use of set_err
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 03:35:37 +00:00
Leah Rowe 7213bba0c5 util/nvmutil: don't exit with errno as status
exit with 0 or 1, as is proper.

errno is an int, but the return value on a shell
can be e.g. byte, and depending how that number (errno)
is valued, could overflow and cause a zero exit, where
you want a non-zero exit.

the code has been changed, in such a way to maintain
current behaviour (don't change errno), except that when
errno is set upon exit, the exit value is now one.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 03:31:09 +00:00
Leah Rowe 490f311d05 util/nvmutil: split up cmd_setmac
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 02:50:03 +00:00
Leah Rowe 3cbaa7ead8 util/nvmutil: rename some functions for clarity
also re-order the prototypes

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 02:32:42 +00:00
Leah Rowe 707fabab38 util/nvmutil: split up parseMacString
split it into smaller, more readable functions

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 02:25:11 +00:00
Leah Rowe d9c307d5a3 util/nvmutil: remove useless gbe variable
use buf directly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 01:50:21 +00:00
Leah Rowe a7cc8143a7 util/nvmutil: cmd copy/swap: use word/setWord
this means that we make use of the boundary checks. it's just
a safer way of handling these functions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 01:18:23 +00:00
Leah Rowe 566ae72ca3 util/nvmutil: remove variable nvmPartChanged
pointless optimisation. we know that when a user requests an
operation that would write, it will probably result in a change.

therefore, this change is the real optimisation. to avoid
writing the same half of a file twice, when using cmd_copy,
we check (in writeGbe) whether gbe part 0 and 1 are the same;
if they are, then we only loop once. this is important, because
otherwise we would call swap() twice.

this means that the optimisations in cmd_copy and cmd_swap must
be removed. the point of this and other changes is to improve
memory safety in nvmutil, so frivolous use of pointers has to go.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 01:07:59 +00:00
Leah Rowe dfbb3c5d9e util/nvmutil: merge nvmalloc with readGbe
it's so simply now, all it does is set the gbe pointers

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 00:41:05 +00:00
Leah Rowe 2b01e023ab util/nvmutil: remove do_read
pointless code complication, that doesn't yield a noticeable
performance increase.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 00:40:07 +00:00
Leah Rowe 1bfc89e3ad util/nvmutil: read in fixed 4KB blocks
modern file systems work in 4KB blocks. reading only
a small part of it doesn't really make much difference
in terms of performance.

simplify the code instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 00:34:31 +00:00
Leah Rowe 1d078c9daf util/nvmutil: use fixed buffer
modern malloc implementations make the optimisation here
pretty pointless.

modern computers make this modification pointless.

i'm not planning to run nvmutil on a VAX. openbsd removed
support for it ages ago. 8KB fixed buffer is fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 00:20:16 +00:00
Leah Rowe 0ccb790fc0 util/nvmutil: remove pointless arg in openFiles
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-03 00:11:49 +00:00
Leah Rowe 6dd91134bd util/nvmutil: don't use xor swap
it doesn't save any time on modern systems, and it's just
confusing for some people to read. i mean, i understand it
instinctively, but normal people do it with a swap variable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 23:29:00 +00:00
Leah Rowe 53e386d2b5 util/nvmutil: don't use size_t as pointer
the only reason i did this was for that xor swap, but we
can just use an intermediary value

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 23:26:02 +00:00
Leah Rowe 3248b8f651 util/nvmutil: don't capitalise set_err
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 23:04:03 +00:00
Leah Rowe d3ca9946a9 util/nvmutil: make xopen a function, not a macro
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 23:02:53 +00:00
Leah Rowe 761968e3c4 util/nvmutil: merge block_unveil back with main
we always want unveil/pledge calls to be in main, when
possible, so that they are more transparent and easier
to understand when re-factoring, because it's extremely
important that these syscalls be done correctly.

main is small enough now, from other re-factoring changes,
that i'm happy to have this back in main now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 22:30:19 +00:00
Leah Rowe 589ac92781 util/nvmutil: fix bad bound check
the current check is too liberal. make it sticter.

the issue is that the previous check did not take
into account that it's a check on a uint16_t array,
against nf which refers to a number of bytes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 17:47:58 +00:00
Leah Rowe 51e4e43c94 util/nvmutil: tidy up the xopen macro
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 17:41:10 +00:00
Leah Rowe a34e79f501 util/nvmutil: add boundary checks on word/setWord
this was the other complication with doing it as a macro.

for something this fundamental, we really want to ensure
that every access is safe.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 17:35:00 +00:00
Leah Rowe 4e7d48b5c5 util/nvmutil: make word/setWord a function
having this as a macro makes the code quite brittle.

better to have it as a function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 17:34:37 +00:00
Leah Rowe 8707695184 util/nvmutil: rename openGbeFile to openFiles
merge the urandom handling back into this function.

it's called immediately after in main anyway, so we
may as well. this reduces the size of main.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 17:06:57 +00:00
Leah Rowe c4138752c3 util/nvmutil: remove redundant unveil call
in the given call, we then do an equivalent call
immediately after that is the same, but without
unveil, so we'll just defer to that.

this changes no behaviour.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 17:03:00 +00:00
Leah Rowe a4fe1bfa4d util/nvmutil: call block_unveil earlier
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 17:01:41 +00:00
Leah Rowe ea1a9bc786 util/nvmutil: bring pledge in set_io_flag to main
in general, we should ensure that the pledge calls only happen
inside main. this means we can more easily see them, in future
re-factoring.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 16:57:50 +00:00
Leah Rowe 46b6b1feb3 util/nvmutil: call set_cmd much earlier
this will enable hardening of the pledge syscalls.

it also means that the program will error out much
earlier, when an invalid command is given, rather
than opening a bunch of files first, and it will
do so under reduced privilege already, notwithstanding
the further pledge/unveil hardening that is planned.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 16:46:20 +00:00
Leah Rowe 0106c38217 util/nvmutil: unveil /dev/urandom much earlier
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 16:41:06 +00:00
Leah Rowe 58cf5a1579 util/nvmutil: split xopen handling
same as the previous change. i'm going to harden the unveil
and pledge calls next.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 16:38:09 +00:00
Leah Rowe e5d7c3e3a2 util/nvmutil: split unveil handling
urandom in main. this is because i'm going to further
harden the use of pledge and unveil in a future patch,
and this is a prerequisite.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 16:34:59 +00:00
Leah Rowe 896f0ea1df util/nvmutil: split cmd init to new function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 16:34:18 +00:00
Leah Rowe 697eda800a util/nvmutil: split flags init to new function
main is getting much smaller now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 12:55:57 +00:00
Leah Rowe ab057e006c util/nvmutil: tidy up main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 12:50:18 +00:00
Leah Rowe 6de3968f2b util/nvmutil: split unveil code to new function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 12:18:23 +00:00
Leah Rowe 9c23eac148 util/nvmutil: separate usage function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-03-02 12:17:07 +00:00
Leah Rowe 7e81c5c630 Re-add x230_12mb corebootfb config
also for other variants

i removed it because it was reported broken. it's not.

the removal was always temporary, pending further testing.
next time, i will be more sceptical.

everything works fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-26 00:58:06 +00:00
Leah Rowe 1d20042f9a nvmutil: simplify readGbe and writeGbe
the for loop only contains one line

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 14:22:35 +00:00
Leah Rowe 5a414ea4d6 nvmutil: centralise all errno handling
do it in the macro. this way, if a given error is
present, it's not overridden. this enables easier
debugging.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 14:01:11 +00:00
Leah Rowe c64a2655e9 nvmutil: rename ERR to SET_ERR, for clarity
i renamed filename to fname, so that certain lines would
still fit within 80 characters without introducing a new
line break.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 13:49:16 +00:00
Leah Rowe 678b9d859b nvmutil: split pread from readGbe
split it into readGbe_part, for code clarity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 13:45:28 +00:00
Leah Rowe e1d8773c54 nvmutil: split pwrite handling from writeGbe
handle it in a separate function, for clarity.

the main function just checks each part whether it
changed, and then passes control to writeGbe_part.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 13:42:27 +00:00
Leah Rowe 261c41a3c3 nvmutil: simplify a few else statements
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 13:34:35 +00:00
Leah Rowe 8cf2558a6f nvmutil: don't hardcode errno to ECANCELED
use the ERR macro instead, so that an existing value
will not be overridden. this is useful for debugging.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 13:30:15 +00:00
Leah Rowe 50de561ac4 nvmutil: explain a few parts in nvmalloc
the current code is optimised for speed, but it's a bit
esoteric, so make it easier to understand.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 11:13:09 +00:00
Leah Rowe 061e6048a8 nvmutil: split malloc handling out of readGbe
this has to do with memory allocation, not actual reading
of the gbe file into memory. split it up, for clarity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 11:10:12 +00:00
Leah Rowe 3d408317b1 nvmutil: further simplify nr/nw error handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 11:01:52 +00:00
Leah Rowe 35d8d0993f util/nvmutil: simplify nr/nw error handling
when nf and nr/nw are not the same, we know there
is an error condition, so defer to the following err()
call, but use ERR() there instead of hardcoding use
of ECANCELED.

this actually improves the error handling, by being
more verbose, while reducing the amount of logic.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 09:50:26 +00:00
Leah Rowe 4473179300 util/nvmutil: remove pointless diagnostics
we only need to know the number of bytes written or
read under error conditions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 09:47:36 +00:00
Leah Rowe 45413f1209 util/nvmutil: say part number on read/write report
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-23 09:34:51 +00:00
Leah Rowe a55af90b6c vendor.sh: handle mfs in find_me
This makes the argument handling easier to understand,
since other arguments are also handled in find_me

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-22 17:18:51 +00:00
Leah Rowe a938309d35 vendor.sh: handle me_cleaner -p separately
this is a special mode that skips FPTR checks, which is
needed on the topton x2e_n150

we currently set this, when MEclean="n", but we may want to
skip cleaning while still checking FPTR on some boards (in
a future lbmk revision)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-22 17:15:24 +00:00
Leah Rowe 177f45355f vendor.sh: tidied up mecleaner argument handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-22 17:06:12 +00:00
Leah Rowe 182c1cd699 Merge pull request 'Provide x270 patch for correct VBT and HDA verb' (#405) from kittywitch/lbmk:x270-patch into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/405
2026-02-22 09:10:47 +01:00
Kat Inskip 913efaebe6 Provide x270 patch for correct VBT and HDA verb 2026-02-21 19:58:12 +00:00
Leah Rowe 0f93368ea0 get.sh: properly initialise _ua
it is currently only initialised inside case
conditions. this is fine on most shells, but
some of them can be a bit buggy here.

initialise it empty and then override.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-21 17:44:01 +00:00
Leah Rowe 4021617430 g43t_am3: make it 2mb, not 4mb
idk why i made it 4

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-21 16:28:17 +00:00
Leah Rowe 006571187b remove release=n on x270 port
this is a hangover from an earlier work, where we
had some issues prior to merging.

as it is, the port is ready for a future release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-21 08:33:08 +00:00
Leah Rowe 2edd583aee Add ThinkPad X270 coreboot port from Kat Inskip
Courtesy of Kat Inskip who ported this board.

Headphone output doesn't work at the moment, due to incorrect verb.
Intel VBT is also wrong. Both are taken from another board.

This will be amended later with the correct verb and VBT.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-21 08:26:44 +00:00
Leah Rowe 1068acd2c0 coreboot/default: new rev ed5a993f
latest coreboot rev as of literally today

this is in preparation for a thinkpad x270 port
using a WIP patch that was contributed

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-19 15:36:22 +00:00
Leah Rowe e6d9b82c62 Merge pull request 'supermicro x11ssh_f: Use deguard-configured ME image instead of SPS and disable ME HECI in devicetree' (#404) from noisytoot/supermicro-x11ssh-f into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/404
2026-02-19 15:35:59 +01:00
Leah Rowe a2c5715589 util/grubpo: new util, for grub PO files
this is the program I recently wrote, that generated
the submodule entries for the GRUB PO file fix

this utility is for reference only. i'll probably do
away with the fix at some point, replacing it with
my own git-based submodule repository, containing the
PO files. this would make things easier, and then
that repository would contain the utility instead.

i'm just putting this in lbmk for now, so that we
have it somewhere.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-19 12:24:47 +00:00
Leah Rowe 5a8ad2d311 util/nvmutil: general code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-19 12:23:57 +00:00
Leah Rowe a95cf1feeb util/spkmodem_recv: general code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-19 12:21:35 +00:00
Ron Nazarov 47bf8e69e8 supermicro x11ssh_f: Remove release="n"
Since we have redundant downloads for the ME image now, it's no longer
required.
2026-02-14 20:59:14 +00:00
Ron Nazarov 1017f16c3e supermicro x11ssh_f: Disable ME HECI in devicetree
Since we always use me_cleaner, this speeds up boot time by preventing
coreboot from wasting a few seconds waiting for HECI.
2026-02-14 20:17:41 +00:00
Ron Nazarov 80be5ce87e supermicro x11ssh_f: Use deguard-configured ME image instead of SPS
Using the same ME image as the 3050 Micro.  This fixes the lack of a
backup download URL for the ME and speeds up boot time, since MRC
caching is working with ME (unlike SPS).

Unfortunately, since the MFS partition must be preserved, this does
mean we need a larger ME region than with me_cleaned SPS.
2026-02-14 20:00:14 +00:00
Ron Nazarov 3c416c6396 Delete unused config/ifd/supermicro-x11-lga1151-series directory
Left over from the hyphen -> underscore renaming commit.
2026-02-14 19:46:04 +00:00
Leah Rowe d5a1de820b supermicro x11ssh_f: set release="n"
the lack of redundancy in Intel ME downloading is a current
release blocker with this board, so set it to release=n for
now.

it is quite possible to use deguard on this board, which does
have redundant downloading when used with lbmk.

although the board doesn't have bootguard, it is still possible
to use deguard. you can configure the generic ME image that it
fetches, and reconfigure it for each machine.

i've asked ron to look into this, on their test board.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-14 12:58:06 +00:00
Leah Rowe c0399adab3 supermicro x11ssh_f: use underscores in dir names
i don't like hyphens in file names, because of how lbmk
has historically handled directories and files in the past;
i've removed a lot of eval statements, to the extent that
it's no longer likely to be a problem (it's barely used now),
but i previously had a problem with using hyphens in config
names.

this design flaw (in lbmk) was fixed ages ago, but i still
maintain this policy. since that time, i use hyphens only.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-14 12:58:01 +00:00
Leah Rowe a14fbfd23a Merge pull request 'Added Danish Keymap dkqwerty.gkb' (#402) from nieldk/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/402
2026-02-14 12:15:57 +01:00
Leah Rowe fb754a187c Merge pull request 'Add Supermicro X11SSH-F/LN4F port' (#403) from noisytoot/supermicro-x11ssh-f into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/403
2026-02-14 12:15:06 +01:00
Ron Nazarov 2e98da9688 Add Supermicro X11SSH-F/LN4F port
Surprisingly, SeaBIOS VGA output works (coreboot documentation says it
doesn't).

I'm using a static CMOS option table currently (like most other boards
supported in libreboot), but maybe it would be better to switch to the
CBFS file option table.  The default option table enables
hyperthreading, overriding the compile-time setting.

I'm also using a ME/SPS image extracted from the official BIOS update
for this board.  Unfortunately, https://www.supermicro.com/Bios/* is
excluded from crawlers in robots.txt so it's not in archive.org, so I
haven't been able to find a backup download URL.  I also needed to set
the user-agent for fetching the update to "curl/8.6.0" because the
default user-agent override used by lbmk resulted in a 403 error.
deguard is not required (there's no bootguard on this board).

SPS does not implement CPU replacement detection which means that the
MRC cache does not work and RAM training needs to happen on every
boot.  To avoid this it may be possible to run ME instead of SPS on
this board, but I tried both the ME image used on the OptiPlex 3050
Micro in libreboot and one from the ASRock C236 WSI and they both hung
at "[INFO ] POST: 0x92" (POSTCODE_FSP_MEMORY_INIT).

The memtest86+ build included with libreboot doesn't work with USB
keyboards and this board doesn't have a PS/2 port, which is annoying.
2026-02-14 02:50:42 +00:00
Niel Nielsen 1099d30f7b Added Danish Keymap dkqwerty.gkb 2026-02-08 15:46:35 +01:00
Leah Rowe 8f128e6728 GRUB: don't download po files in bootstrap
The files it downloads are not versioned, and they could
change any time. GRUB has no way to deterministically grab
these.

I've removed GRUB's local for grabbing these, instead
mirroring them myself and checking hashes; no hashes seem
to have been provided by the upstream at Translation Project,
so I just used the hashes I had on the files it had, when
I downloaded them.

From now on, I can just re-download these and re-calculate
the hashes as desired, over time, when updating GRUB revisions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-01 22:09:33 +01:00
Leah Rowe 1cf3181537 Libreboot 26.01 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-30 07:14:30 +00:00
Leah Rowe e42eef2d2a Merge pull request 'Update config/dependencies/void' (#400) from lucius1664/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/400
2026-01-30 08:11:39 +01:00
lucius1664 466b01b17e Update config/dependencies/void 2026-01-27 13:14:22 +01:00
Leah Rowe bc5e0bbbbb fix config/submodule/
I accidentally removed a bunch of links in a previous change,
that isn't pushed yet.

due to gitignore rules, files in config/submodule/ have to be
added manually using -f with the git add command. as a result,
i need to be very careful when making changes, especially
temporary changes.

lbmk wasn't downloading files properly, because upstreams weren't
defined. this patch fixes that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-26 06:27:58 +00:00
Leah Rowe a808333c04 Libreboot 26.01 RC4 Magnanimous Max
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-21 01:20:43 +00:00
Leah Rowe baeec45f50 use newer ME on e7240
i accidentally picked an older version from Dell update
A16. this update uses A29.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-21 01:18:06 +00:00
Leah Rowe fc2a521446 Libreboot 26.01 RC3 Magnanimous Max
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-21 00:01:38 +00:00
Leah Rowe e91377b509 cb/default: new rev fcd716d9a2, 14 January 2026
This brings the following changes from upstream:

* fcd716d9a2 mb/google/ocelot: Limit Power Limit when battery is missing
* d246e2ca7e tests/Makefile.common: Fix inverted USE_SYSTEM_CMOCKA condition
* e64507638e tests/lib/ux_locales-test: Avoid double quotes in CMUnitTest.name
* 4427a34b6b drivers/intel/fsp2_0: Fix string length handling in timestamp printing
* 40dbe0807d Documentation/mb: Add missing entry for starfighter_mtl
* f070e0add8 mb/starlabs/byte_adl: Fix WOL
* fc20f238f6 mb/starlabs/*: Select DRIVERS_EFI_FW_INFO
* 225e635ea1 soc/amd/common/block/spi: Operate on multiple SPI flashes
* b9bd924847 soc/amd/common/block/spi: Implement boot_device_spi_cs()
* d7d4b67c6a commonlib/mipi/cmd: Remove unnecessary 'const void *' cast
* 5af56ddf92 mb/google/skywalker: Implement lb_board() to pass LB_TAG_PANEL_POWEROFF
* d110cf4669 commonlib/mipi/cmd: Add mipi_panel_get_commands_len()
* 0ee48a475c drivers/mipi: Add power-off commands for TM_TL121BVMS07_00C
* a974b7668e soc/intel/*: Disable InternalGfx w/o iGPU to prevent FSP-M/S crash
* 18ffcafa61 mb/google/bluey/quartz: Adjust PS8820 init sequence
* 532543027a mb/siemens/{mc_ehl6,mc_ehl7}: Configure GPIO GPP_G5 (SD CD) pull-up
* d420e1fb87 mb/siemens/mc_ehl8: Switch from LPSS UART to legacy 8250 I/O UART
* 483c3e51ae mb/siemens/mc_ehl8: Configure I2C and SMB devices
* d810257008 mb/siemens/mc_ehl8: Configure PCIe root ports
* cf2c2555f4 mb/siemens/mc_ehl8: Add new board variant based on mc_ehl1
* a12663fd88 drivers/spi: Allow SoC to provide the SPI flash CS index
* cacc11de4f include/cpu/x86/msr.h: Update return types from int -> bool
* d5fb4becd5 mb/google/nissa/var/yavilla: Update DTT parameters
* 3b18467e8a payloads/ipxe: Unconditionally restore config files post-build
* 4374bbd37b payloads/ipxe: Update and use the stable version
* c0998983d0 ec/google/chromeec: Fix uninitialized buffer in cbi_get_uint32()
* 03b47f947f soc/mediatek: Add mtk_get_mipi_panel_data() API
* 8cfc71d9e0 libpayload: Pass panel power-off commands to payloads
* d94d4b8a25 mb/starlabs/starlite_adl: Add trace length for the card reader
* 0f450a8d9c mb/starlabs/starlite: Set card_reader fallback value to 0
* 94672e2b45 sb/intel/ibexpeak: Remove 6/7 series chipset PCI IDs
* 2fc8051679 util/autoport: Factor out getting sorted Kconfig option names
* 01d82febb2 util/autoport: Separate handling of Kconfig selects
* b7763a5973 mb/google/fatcat: Implement Google Rex touchscreen integration
* 3f5807ce10 mb/siemens/mc_ehl7: Deactivate SATA interface
* 5f76f78383 mb/siemens/mc_ehl7: Deactivate GbE and PSE GbE 0
* b5ad97a268 mb/google/nissa/var/gothrax: Add wifi sar table
* 7351e663d2 mb/google/nissa: Enable early EC SW sync & eSOL for gothrax/epic
* f9b917d391 soc/qualcomm/x1p42100: Relocate CBMEM top below XBL log
* a306987ae4 util/superiotool: Add experimental Nuvoton NPCD378 support
* 139f6c3e64 mb/google/brya/var/redrix: Configure cameras for Windows/Linux ACPI mode
* 3883118ed9 mb/google/brya/var/kano: Configure cameras for Windows/Linux ACPI mode
* ae7b75fb0d mb/lenovo/sklkbl_thinkpad/cfr.c: Fix X280 build error
* 7639118729 drivers/amd/opensil: Add hooks to populate CBMEM_ID_MEMINFO
* 23f0b0b313 util/xcompile/xcompile: Fix clang target parameter
* f712c965e4 payloads/edk2: Update default MrChromebox branch from 2508 to 2511
* b4917ed44d payloads/edk2: rework serial output configuration
* 282c27c95c arch/x86/acpi_bert_storage.c: Allow vendor specific BERT entries
* 00fbc08b76 Reapply "soc/mediatek/mt8196: Call fsp_init via boot state"
* e6c5ee6450 mb/google/hatch/var/kohaku: Add Samsung S-pen driver support
* b890ca0648 mb/google/brya/var/yaviks: select USE_MTCL only if CHROMEOS
* a8737c5f86 mb/google/cyan: Set CBFS_SIZE default to match IFD BIOS size
* 72af15f1de mb/google/zork: Fix missing comma in CFR object list
* 5db16ea6fc soc/intel/pantherlake: Fix incorrect use of logical OR for TDP selection
* 2c58e525e8 soc/intel/ptl: Add ACPI IOST support
* 52aeb078ce soc/intel/common/acpi: Add IOST device
* d62764df87 soc/intel/common/block/p2sb: Add SSDT function for SoC-specific features
* 96b4754c35 soc/intel: Add CPU ID support for Nova Lake
* b741e2274e acpi: Add enums for TPM2 start method
* 6fd865f409 drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs
* c09352d58d soc/intel/pantherlake: Update PS1 threshold to the latest recommendations
* 093ae8eeaa mb/siemens/mc_ehl7: Enable reboot after HW Watchdog expiry
* ddf4748c22 mb/siemens/mc_ehl7: Deactivate RTC
* e8ac9ffcd9 mb/siemens/mc_ehl7: Add new board variant based on mc_ehl6
* 94e6e5cd0d mb/google/ocelot: Add option to enable VGA mode 12
* fbf0087918 mb/google/ocelot/var/ocicat: Use GPP_F10 for ISH
* f2788e963f device: Rename PCI_EXP_SEC_CAP_ID -> PCI_CAP_ID_SEC_PCIE
* e01baafbe2 include/cper.h: Add check information structures
* a6407000f1 mipi/panel: Add 'poweroff' field to panel_serializable_data
* b4fbc59c6f treewide: Move mipi_panel_parse_commands() to commonlib
* 1d2b399fd7 lib: Rename `fill_lb_framebuffer` to `get_lb_framebuffer`
* 5f86aba4b3 soc/intel/common: Enable high address support for MCHBAR in ACPI
* f00a2ff7b8 arch/x86/ioapic.c: Support 8-bit IOAPIC IDs
* 3c3fbbaabf arch/x86/acpi_bert_storage.c: Remove unused variable
* 9f4132712f soc/intel/alderlake: add chipsetinit support
* a5c0307e9c commonlib/device_tree: Add dt_add_reserved_memory_region helper
* a3a556f05d mb/google/fatcat/var/ruby: Add wifi SAR table
* 8bc1372f72 sb/intel/common/spi: Prevent transfers across 4KiB boundaries
* 95ad028274 drivers/smmstore: Use lookup_store() for memory-mapped reads
* c421847fe2 util/crossgcc: Fix GNAT detection for gnat-15
* 292d7b9d3d Revert "soc/mediatek/mt8196: Call fsp_init via boot state"
* e705c39009 libpayload/arch/arm64/mmu: Add CB_MEM_TAG to usedmem_ranges
* 18a986c5fe soc/amd/cmn/block/cpu/mca: Support MCA_SYND1 and MCA_SYND2
* c45e153dfb mb/google/bluey/var/quartz: Enable PS8820 support
* e303357cb9 soc/qualcomm/x1p42100: Call mainboard Type-C config hook
* f9efe53cb0 mb/google/bluey: Implement PS8820 retimer configuration
* 657bcd32d9 mb/google/bluey: Add Kconfig for PS8820 retimer support
* 17a52ce94e soc/qualcomm/x1p42100: Add mainboard USB Type-C config hook
* 16cb8d0d0c mb/google/bluey: Add power sequencing for USB-C1 retimer
* 5034f8629f soc/intel/common: Add spinlock protection to fast SPI flash operations
* ceaa41c9e4 drv/intel/mipi_camera: Verify SSDB only for camera sensors
* ede97ef9da mb/google/volteer: Add IPUA device and sensor names
* 65cbf312af mb/google/volteer: Convert MIPI camera cfg from static ASL to devicetree
* 2aca802e85 mb/google/brya/acpi/cnvi_bt_reset: Fix BT re-enumeration under Windows
* 524ad684af mb/google/brya/var/taeko: Fix SOF speaker topology selection
* 829b8be432 libpayload: Add bulk with timeout callback to USB
* f4fe5514fe mb/google/ocelot/var/kodkod: Update gpio settings for NC pins
* c7f0697867 coreboot_tables: Add new CBMEM ID to hold the PCI RB aperture info
* 3ded43722a soc/amd/cmn/block/acpi/ivrs: Use less PCI accesses
* 1da7c31810 include/cpu/x86/msr.h: Add MCA related MSRs
* 7deb82d744 mb/google/bluey: Configure QUPV3_0_SE3 and QUPV3_0_SE7 for USB-C0 and USB-C1 Retimer I2C access
* b00d2ad5c2 vc/intel/fsp/fsp2_0/pantherlake: Update PTL FSP headers to FSP 3442.07
* b7ad850fd6 mb/google/bluey: Add percentage symbol to battery level log
* ae48ff8c0b drivers/wwan/fm: Use _EVT method to enhance GPIO event handling
* 7ed7abbd92 acpigen_ps2_keybd: map screenlock
* 6b52f82df2 util/amdfwtool: Remove AMD_FW_GFXIMU_2 entry
* b9145e1588 util/amdfwtool: Remove duplicated AMD_TA_IKEK
* e393fd00a4 include/cper.h: Update cper_ia32x64_context_t
* 14a7a2315e soc/mediatek/mt8196: Call fsp_init via boot state
* 82f9c593ab payloads/libpayload: Add support for RISC-V 64-bit architecture
* 4decc72c23 drivers/intel/touch: Change ELAN device name for Google's Rex touch device
* 17b36286c8 mb/google/hatch/var/kindred: Drop VBT for KLED variant
* cf280eaa7f amdblocks/root_complex.h: Add new IOHC base addresses
* ba0483c94a soc/amd/common/Makefile.mk: Strip quotes from AMDFW_CONFIG_FILE
* b2b1eb3c5a soc/amd/common/block/smn: Add simple SMN I/O accessors
* f8c10eda36 mb/google/nissa/var/gothrax: Add Rayson parts to RAM ID table
* 0c26c4494d mainboard/google/bluey: Enable display clocks and MMCX power rail
* e1e7b9b203 soc/qualcomm/x1p42100: Add API to enable display clocks
* 02e6f2a214 soc/qualcomm/x1p42100: Add API to intialize RPMh resources for display
* dc162f84be soc/qualcomm/common: Add RPMh driver support
* 999dd8905a lib/bootmem: Replace conditional return with assert in bootmem_add_range_from
* eb814f3b12 lib/bootmem: Remove forward declaration of bootmem_range_string
* 6f394ce50d coreboot_tables: Update CB_MEM_TAG and LB_MEM_TAG values to 17
* 6966885290 mb/google/skywalker: Extend MIPI panel delay to meet T3 timing
* 273e84976b mb/asus/p8z77-v: Apply vendor PCH interrupt mapping
* 573c37a518 sio/nuvoton/common: Refactor nuvoton_pnp_*_config_state()
* 0c2a3002d9 mb/asrock/z87_extreme4: Temporarily refactor nuvoton_pnp_*_conf_state()
* 19deb55f02 mb/asrock/fatal1ty_z87_professional: Temporarily refactor nuvoton_pnp_*()
* 3d980dae22 mb/google/nissa/var/rull: Add 3 DDR modules to RAM id table
* 4030fc5f91 device/Kconfig: Gate early libgfxinit default on ChromeOS
* b8402a8dfc src/qualcomm/common: Remove display buffer region declarations
* 7896d94c76 soc/qualcomm/x1p42100: Avoid reserving display buffer region
* fe0e14d716 soc/qualcomm/x1p42100: Skip SHRM meta firmware load in ramdump mode
* 56013ce0ff mainboard/google/bluey: Skip SHRM firmware load/reset in ramdump mode
* b8680d53ac mb/google/ocelot/var/ocicat: Add fw_config definitions with UFSC
* c3ff1addde mb/google/ocelot/var/ocicat: Add WIFI SAR table
* 9b5d985838 mb/google/ocelot/var/ocicat: Update audio settings
* 091e8140ea spd/lp5: Add SPD for RS1G32LO5D2FDB-23BT
* bc240baba5 Documentation: Add method for GRUB2 to load seabios from drive
* 02c57577f3 superio/nuvoton: Add common ACPI ASL code
* 7273a5b932 mb/asus/p8x7x-series: Move CONFIG_SUPERIO_PNP_BASE to sio/nuvoton
* 40eca2934f soc/mediatek/common: Track firmware splash screen rendering completion
* 49d34a6f6c mb/google/skywalker: Add MIPI panel GPIOs via lb_gpio
* b354b49d58 libpayload: Increase SYSINFO_MAX_GPIOS to 10
* 25d159a7ec mb/google/skywalker: Use FW_CONFIG for storage and dual init support
* 4063a4c3f1 mb/google/skywalker: Create variant Mace
* a1e9cd3669 mb/google/bluey: Configure QUPV3_2_SE4 for ADSP I2C access
* 2b9653cf34 arch/x86/acpi_bert_storage.c: rename check -> proc_err_info
* a3236ef110 arch/x86/acpi_bert_storage.c: Fix array size calculation
* e3fc4a1f69 ec/starlabs/merlin: Reorganize Kconfig and guard options properly
* 4a07174d0e util/cbfstool: Fix RISC-V relocations
* d912ae91b0 mb/google/bluey: Configure GPIOs for USB camera
* a27a7f0c11 mb/google/trulo/var/kaladin: Decrease G2 touch stop delay time to 150 ms
* 3bebadd347 mb/google/bluey: Enable dynamic SoC calculation and log battery level
* bab8ca2bd0 ec/google/chromeec: Refactor Battery SoC calculation
* 02b3674198 ec/google/chromeec: Add SoC calculation from battery dynamic info
* 06c83d473b ec/google/chromeec: Add function to read battery state of charge
* 7c3d45d94f drivers/usb/intel_bluetooth: Correct S-state level for power resource
* 091ac10059 soc/intel/cnvi: Correct S-state level for CNVP
* 4631f94e51 drivers/usb/intel_bluetooth: Advertise D2 for S0W
* ea045bd322 soc/intel/cnvi: Re-enable Bluetooth on reset timeout
* ffac7d90da soc/intel/cnvi: Correct error values for _RST
* f24a2f35bf mb/asrock: Correct vendor name ASROCK to ASRock
* aeb9dcf2fa libpayload: Add new memory type CB_MEM_TAG
* c093b52c20 soc/mediatek: Correct BIAS_ON value to get bias ready
* 531c24cd0a Documentation: Fix typo in 'particularly'
* 331e93cbd2 libpayload/tests: Disable generation of lcov HTML
* 7d38a96c44 mb/google/skywalker: Create variant Vader
* 75333ea7c8 mb/google/bluey: Refactor is_pd_sync_required function
* 3f00ecb05c soc/intel/pantherlake: Add ChromeOS board-specific TDP setting
* 1dfa80f02c soc/intel/pantherlake: Add configurable TDP support
* dc68f5b265 soc/intel/pantherlake: Let common code set PL1 to TDP
* bb3f40627d util/autoport: Fix style issue in generated code
* 94b326469b mb/google/bluey: Increase FW_MAIN_A/B slot size to 8.5MB
* e6c3250912 mipi/panel: Remove pic_width and pic_height from dsc_config
* 456403d9ba soc/mediatek/mt8196: Stop using dsc_config.pic_width
* 7d50f63213 soc/mediatek: Drop mtk_ddp_soc_mode_set()
* 61c9450d62 soc/mediatek/common: Pass dsi_regs to mtk_dsi_cphy_timing()
* ba5b5ea406 soc/mediatek/mt8196: Move DPM and SPM initialization
* 206025754f libpayload/tests: Remove unrecognized flag --ignore-errors inconsistent
* 82c06da584 3rdparty/fsp: Update to upstream master
* c5eecee5e9 mb/google/rex: Add IPUA device and sensor names
* bceb2c83ad mb/{google/intel}: Fix/add missing MIPI camera SSDB lanes_used/link_used
* de4148888c tests: Disable generation of lcov HTML
* 188cd88ac7 soc/mediatek/mt8196: Correct MIPI register control
* 080ca011fe Documentation: Finalize 25.12 release notes
* 695041a9bf mb/starlabs/*: Increase size of SMMSTORE region to 512KB
* 975e48faaf mb/starlabs/starlite_adl: Add CFR option for charge LED brightness
* 951c28c1bf mb/starlabs/starfighter: Add CFR options for power/charge LED brightness
* ab2c69c4f3 mb/starlabs/starbook: Add CFR options for power/charge LED brightness
* 84ff3d3d12 ec/starlabs/merlin: Add charge LED brightness control
* ac170631d5 mb/starlabs/starlite: Fix ddr5 entry
* 0e217cf1d3 soc/mediatek/mt8196: Increase FRAMEBUFFER to 32MiB
* 003ea85115 soc/mediatek/mt8196: Support logo display on DISP_PATH_DUAL_MIPI path
* 7e7ba6fb11 security/lockdown/lockdown.c: option to lock COREBOOT and BOOTBLOCK
* 56a7ae4389 soc/mediatek/mt8196: Notify MCUPM to support MTE
* 7c7feca258 CBFS verification: support Top Swap redundancy
* 739808011a Makefile.mk: don't add bootblock after other files
* cbac0d7a25 Makefile.mk,cpu/intel/fit/Makefile.mk: introduce CBFS_REGIONS
* f773a0faac cpu/intel/fit/Makefile.mk: make FIT in TOPSWAP point at MCU in COREBOOT_TS
* fa80ab0146 src/Kconfig: add MAINBOARD_NEEDS_CMOS_OPTIONS
* 59d438f5c7 mb/google/bluey: Remove GSCVD region from Bluey and BlueyH variants
* 7c4d9e0862 mb/google/*: Update Kconfig names with all known board names
* 35be1ab679 configs: Build test ramstage zstd compressed
* 2d99da12a9 commonlib/bsd: Add zstd support
* 4ca5e9c8c6 rules.h: Add ENV_RAMSTAGE_LOADER
* 0421ef2cd8 util/cbfstool: Add zstd support
* 0302b2ee07 lib/xxhash: Move to commonlib/bsd
* 76e9635346 amdfwread: Parse and print directory sizes
* a3adf4898b mb/google/brya/var/pujjocento: Add 2 Micron modules to RAM id table
* d1e1003217 spd/lp5: Add SPD for MT62F2G32D4DS-031RFWT:C
* d528561130 mb/google/bluey: Use PMIC for off-mode detection
* 65833355ca tests: Disable gcov warnings
* 060d18f070 soc/mediatek/mt8196: Add DSI dual channel

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 23:53:12 +00:00
Leah Rowe 86cbf66b78 NEW MAINBOARD: Dell Latitude E7240 from Iru Cai
Thank you Iru Cai for this coreboot port.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 22:23:10 +00:00
Leah Rowe a494c3c2e2 Revert "coreboot/default: don't remove fsp files"
This reverts commit 2e6f6e2579.

This was a stupid revert. I don't remember why I even did it.

Better to make the releases *not* take up an extra 100MB per
source file, until I actually need these extra files.
2026-01-20 12:15:45 +00:00
Leah Rowe f22d4b1c49 u-boot: update configs
i did: ./mk -u u-boot

otherwise, building u-boot asks for user input

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 12:06:15 +00:00
Leah Rowe 778ae1653a fix grub version name in xhci_nvme
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 12:03:01 +00:00
Leah Rowe 9ea35f3866 Libreboot 26.01 RC2, or: Magnanimous Max
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 04:32:50 +00:00
Leah Rowe b538749c83 remove T480/T580 thunderbolt driver
it causes s3 resume to break on t480s

more testing needed across the board(s)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 04:32:34 +00:00
Leah Rowe 4e33b40655 re-add deleted grub border patch
accidentally deleted it during rebase

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-19 16:33:13 +00:00
Leah Rowe d22f7f9633 update grub to 2.14
This brings these extra changes:

* eaa3b8f0f Bump version to 2.15
* d38d6a1a9 Release 2.14
* 35bfd6c47 build: Add grub-core/tests/crypto_cipher_mode_vectors.h file to EXTRA_DIST
* ac042f3f5 configure: Print a more helpful error if autoconf-archive is not installed
* e37d02158 kern/ieee1275/openfw: Add a check for invalid partition number
* f94eae0f8 grub-mkimage: Do not generate empty SBAT metadata
* 1aa0dd0c0 configure: Defer check for -mcmodel=large until PIC/PIE checks are done
* ff1edd975 util/grub-mkimagexx: Stop generating unaligned appended signatures
* 51ebc6f67 tests: Add functional tests for ecb/cbc helpers
* caaf50b9a osdep/aros/hostdisk: Fix use-after-free bug during MsgPort deletion
* 18f08826f kern/efi/sb: Enable loading GRUB_FILE_TYPE_CRYPTODISK_ENCRYPTION_KEY and GRUB_FILE_TYPE_CRYPTODISK_DETACHED_HEADER

NOTE: This patch was reversed:

* ac042f3f5 configure: Print a more helpful error if autoconf-archive is not installed

Because it quite unhelpfully broke the build.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-19 16:03:51 +00:00
Leah Rowe 21d5050fb4 delete x230* corebootfb configs for now
a user reported that there is just a black screen at bootup
in 26.01 rc1 on these, but txtmode works.

only their x230 broke in corebootfb. their t430 and x200 they
tested worked fine.

txtmode works. this bug didn't affect 25.06, according to this
user.

no harm deleting these for now. i'll test it myself later (the
user isn't being very helpful with reporting) and fix whatever
the problem is.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-19 13:47:44 +00:00
Leah Rowe 2e6f6e2579 coreboot/default: don't remove fsp files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-06 22:18:54 +00:00
Leah Rowe bbfee155ba fix fsp extraction for topton x2e n150
coreboot updated the fsp file. we know the old one worked,
so no point testing the new one so close to a stable lbmk
release.

i've modified 3rdparty/fsp/ to re-add the old one as another
file, so that other boards are unaffected, and updated the
Kconfig so that the special file is used for x2e n150 only.

more specifically, added a second fsp submodule.

it's a bit dirty, but avoids bloating lbmk.git

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-06 22:17:05 +00:00
Leah Rowe d5351aee37 inject: fix mac address insertion
during previous re-factoring, i sorted variable initialisations.

that was all well and good, but prior to that, i initialised
the new_mac string to empty at first, and then to
the "xx" letters; the latter made the first initialisation
redundant, but in the re-factoring, I put the blanking of
the string afterward.

this disabled mac address insertion, because the way the script
works is precisely to avoid mac address insertion when the mac
string is empty. this is used when running the "nuke" command.

silly me.

yes, i'm very silly. very very silly. so silly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-25 13:41:37 +01:00
Leah Rowe a59fc6a353 Libreboot 26.01 RC1 Tenacious Tomato
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-25 01:11:59 +01:00
Leah Rowe b259f3493d update pcsx-redux openbios
use revision:
b745534eb231d3699ec57949f16a9a7bd5b79385

This brings the following upstream changes:

*   b745534e Merge pull request #1957 from wheremyfoodat/splash
|\
| *   33adecd6 Merge branch 'main' into splash
| |\
| |/
|/|
* |   d01e438e Merge pull request #1979 from nicolasnoble/upgrade-fmt
|\ \
| * | ae8c5cb8 Updating fmt to 12.1.0
|/ /
* |   fd9959a8 Merge pull request #1978 from malucard/all
|\ \
| * | 3ecd98e6 change deprecated fmt::localtime to std::localtime
|/ /
| * eec812e3 Nix: Stop using the outdated version of stb from nixpkgs (#7)
| *   836a0e10 Merge branch 'main' into splash
| |\
| |/
|/|
* |   e90d74d6 Merge pull request #1968 from wheremyfoodat/fix-coroutine
|\ \
| * | 62a23f8f Fix coroutine build on AppleClang 17
* | |   a56a96be Merge pull request #1974 from njfox/aur-ci-dependencies
|\ \ \
| * | | 98d10525 add --syncdeps to install missing PKGBUILD dependencies
| |/ /
* | |   3c155400 Merge pull request #1977 from aybe/fix-icon-overlay
|\ \ \
| * | | 79de997d Fix spurious folder icon overlay
* | | |   1d573efa Merge pull request #1976 from aybe/fix-missing-directory-extension
|\ \ \ \
| * | | | b13b80c7 Render directory node fully (including extension)
| |/ / /
* | | |   1a678f42 Merge pull request #1975 from aybe/fix-wrong-c-drive
|\ \ \ \
| |/ / /
|/| | |
| * | | c37d0597 Fix C:\ showing current directory
|/ / /
* / / 47d83a2b Padding isos to 2 minutes instead of 2 seconds.
|/ /
* |   718f0912 Merge pull request #1962 from njfox/aur-ci
|\ \
| * \   c70d85e4 Merge branch 'main' into aur-ci
| |\ \
| |/ /
|/| |
* | |   87f8e861 Merge pull request #1964 from nicolasnoble/tpageloc-fix
|\ \ \
| * \ \   acdc7e50 Merge branch 'main' into tpageloc-fix
| |\ \ \
| |/ / /
|/| | |
* | | |   a11e5ed6 Merge pull request #1965 from nicolasnoble/brew-hotfix
|\ \ \ \
| * | | | d6e15260 Now fixing psyqo...
| * | | | a7035f32 Fixing OpenBIOS build under 15.2...
| * | | | 909eb220 Also patching gcc now.
| * | | | c319254e Adding zlib patch for binutils on macos...
| * | | | d56b30e3 Derp.
| * | | | 00bd1db0 Upgrading gcc and gdb as well...
| * | | | 27e6fab9 Adding verbose mode.
| * | | | 5cb9084d Restoring readme properly.
| * | | | d911c2b1 Updating to binutils 2.45.
| * | | | a759cb84 Fixing https://github.com/orgs/Homebrew/discussions/6351
|/ / / /
| * / / 6de0f096 Properly returning a TPageLoc on TPageAttr::getPageLoc
|/ / /
| * |   98c53855 Merge branch 'main' into aur-ci
| |\ \
| |/ /
|/| |
* | |   a285e14e Merge pull request #1955 from wheremyfoodat/mac-bundle
|\ \ \
| * | | 97b9651b MacOS bundle script: Enable game mode support, list app as game
| * | | 0e0fabf2 MacOS bundle script: Clean up temporary image files
* | | |   1d54cbe6 Merge pull request #1958 from wheremyfoodat/aa64-flush-cache
|\ \ \ \
| * | | | 053eb573 arm64 JIT: Fix broken cache invalidation
| |/ / /
* | | |   52d9ddc5 Merge pull request #1956 from wheremyfoodat/jit-fixes
|\ \ \ \
| * | | | 4dd04425 a64 JIT: Fix setRWX function returning nothing on Apple
| |/ / /
* | | |   4e846d89 Merge pull request #1959 from wheremyfoodat/no-portable
|\ \ \ \
| * | | | 169788fb Add --no-portable flag
| |/ / /
* | | |   7bce4ecd Merge pull request #1960 from wheremyfoodat/remove-dynarec-dump
|\ \ \ \
| * | | | 8c995593 arm64 JIT: Don't unconditionally dump a JIT dump in the user's files
| |/ / /
* | | |   3a8ddc79 Merge pull request #1963 from njfox/openbios-fix-function-signatures
|\ \ \ \
| |/ / /
|/| | |
| * | | 98d9684b move pointer asterisk to be consistent
| * | | e7ad2b1e fix function definitions to include correct argument types
|/ / /
| * | bdaa1fe9 remove duplicate git dependency
| * | 53326672 combine dependency updates/installation and fix indentation
| * | f4d1f073 build against PR and push instead of master
|/ /
| * cdec82a4 Fix VS project files
| * 587ce8e9 GUI: Better splash image, bug fixes
| * 0b73a07a Add splash screen generation script
| * 3c4afbb6 Initial splash image draft
|/
*   4f4a00fe Merge pull request #1953 from cleverca22/fix-submodules
|\
| * 2bc000e8 fix submodules
* |   a4d6bcc4 Merge pull request #1954 from yaz0r/gdb_sharedmem
|\ \
| |/
|/|
| * 390ccf63 Address comments
| * 07e9b472 Add monitor command to retrieve the shared memory name. Only for wram so far.
|/
*   1b0cbe5e Merge pull request #1952 from yaz0r/gdbfix
|\
| * b4e77deb Fix GDB packet p (readRegister)
|/
*   a2a6d77c Merge pull request #1951 from nicolasnoble/linuxdeploy
|\
| * 2388bcb1 Switching to linuxdeploy.
|/
*   ec1154ad Merge pull request #1950 from grumpycoders/revert-1947-appimage-bullshit
|\
| * 5a66d37f Revert "Sorting out yet another AppImage breakage."
|/
*   a1f02931 Merge pull request #1940 from Forceh91/patch-1
|\
| * e23f9d01 Re-adding all examples.
| * f1b8694b Fixing test suite.
| *   78b4e9f1 Merge branch 'main' into patch-1
| |\
| |/
|/|
* |   b62b506f Merge pull request #1944 from eliasdaler/authoring_quiet
|\ \
| * \   572e18ba Merge branch 'main' into authoring_quiet
| |\ \
| |/ /
|/| |
* | |   cb651973 Merge pull request #1946 from nicolasnoble/pcsx-io-fixes
|\ \ \
| * \ \   fca66d17 Merge branch 'main' into pcsx-io-fixes
| |\ \ \
| |/ / /
|/| | |
* | | | b2066c72 Merge pull request #1947 from nicolasnoble/appimage-bullshit
* | | | e5244aea Sorting out yet another AppImage breakage.
 / / /
* / / e1be0936 Fixing accesses to the pcsx IO system.
 / /
* / 0fbc4206 autoring: add -q option
 /
* eaff5ed2 Merge branch 'main' into patch-1
* c0fa3b2f chore: nitpick changes from coderabbit
* 3b3e7986 chore: create readme with community examples

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 19:14:43 +01:00
Leah Rowe a4ad3afdbb bump flashprog rev: ffcf92fb, December 2025
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 19:02:08 +01:00
Leah Rowe 68e0b5dddc init.sh: Explicitly export UTF-8 locale
C.UTF-8, instead of just C.

This fixes a build issue in GRUB on my Arch Linux test bench.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 17:16:10 +01:00
Leah Rowe b990d54cff grub modules: add more gcry_ ciphers
Since the libgcrypt update in GRUB, which imported
GNU's own Argon2 implementation, other ciphers have
also been introduced.

This patch adds them to lbmk's GRUB build.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 02:35:30 +01:00
Leah Rowe 5df6b924d7 bump seabios revision
by the time i'd done this, i'd realised that seabios only
modified some documentation upstream. the code has not
changed since last update, upstream.

no point scrapping the update now. now we have slightly
better documentation for seabios!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 01:58:24 +01:00
Leah Rowe 9228a0c02c update grub again, to 25b7f6b93
i had a build error before, when trying this absolute
most up to dave revision.

i found that it was this patch:

commit 1a5417f39a0ccefcdd5440f2a67f84d2d2e26960
Author: Nicholas Vinson <nvinson234@gmail.com>
Date:   Tue Nov 18 19:38:07 2025 -0500

For now, I just revert it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 01:47:28 +01:00
Leah Rowe 512cce0770 GRUB: update to rev 2.14-rc1 December 2025
The argon2 patches were dropped (PHC implementation),
because GRUB has now its own Argon2 KDF implementation
as part of its recent libgcrypt update.

Argon2 support is therefore retained, but GNU's implementation
has replaced the one that Libreboot previously used.

This brings in the following upstream changes:

* 280715ec6 Release 2.14~rc1
* e549317e1 windows: Fix symbol table generation during module conversion from PE to ELF
* a340750f9 windows: Fix relocation sections generation during module conversion from PE to ELF
* c602035a9 loader/efi/linux: Fix compile error with Clang
* f62269767 build: Add tpm2key.asn file for reference to dist archive
* 46be4488f build: Include new zstd test support files in dist archive
* fa79d5ea9 build: Include MAINTAINERS and SECURITY files in dist archive
* 8271bcc13 build: Add appended signatures header file to EXTRA_DIST
* 11845da2b lib/xzembed/xz_dec_stream: Replace grub_memcpy() call with memcpy()
* 7ded35fea bootstrap: Fix patching warnings
* 4129e9ad6 tss2: Always init out buffer before calling tpm2_submit_command_real()
* 000e48b42 fs/ntfs: Correct next_attribute validation
* 5ff9c43cf kern/ieee1275/init: Use net config for boot location instead of firmware bootpath
* c2cae77ab net/tftp: Fix NULL pointer dereference in grub_net_udp_close()
* fadc94b91 net/dns: Prevent UAF and double free
* cd24e2591 net/bootp: Prevent a UAF in network interface unregister
* fca6c0afd docs: Document lsmemregions and memtools commands
* 42c099786 commands/memtools: Add lsmemregions command
* 20211246a tests/file_filter: Add zstd tests
* 092449f63 tests/file_filter: Add zstd test file
* 356dcac9a tests/file_filter: Regenerate gpg keys
* 8ea83c3ee io/zstdio: Implement zstdio decompression
* 7c22c1000 fs/btrfs: Update doc link for bootloader support
* 6435551a6 docs: Add Btrfs env block and special env vars
* b63447748 util/grub.d/00_header.in: Wire grub.cfg to use env_block when present
* e4e177661 fs/btrfs: Add environment block to reserved header area
* d6525f0e6 util/grub-editenv: Add probe call for external envblk
* 4b5ea8dca util/grub-editenv: Wire list_variables() to optional fs_envblk
* 84e2bc2f1 util/grub-editenv: Wire unset_variables() to optional fs_envblk
* c7c901916 util/grub-editenv: Wire set_variables() to optional fs_envblk
* 2abdd8cd2 util/grub-editenv: Add fs_envblk write helper
* e4d684cc4 util/grub-editenv: Add fs_envblk open helper
* 512e33ec7 tests: Add "z" length modifier printf tests
* 3c9762b12 kern/misc: Add the "z" length modifier support
* 91ddada64 disk/cryptodisk: Add --hw-accel to enable hardware acceleration
* f8f68f14a libgcrypt: Add hardware acceleration for gcry_sha512
* 70b2f5f08 libgcrypt: Add hardware acceleration for gcry_sha256
* 2158d8e8a libgcrypt: Declare the sha256 shaext function
* 0ff5faf8c libgcrypt: Implement _gcry_get_hw_features()
* 812356191 libgcrypt: Copy sha512 x86_64 assembly files
* 7f9c590af libgcrypt: Copy sha256 x86_64 assembly files
* 8423176f1 lib/hwfeatures-gcry: Enable SSE and AVX for x86_64 EFI
* 06a5b88ba lib/hwfeatures-gcry: Introduce functions to manage hardware features
* d01abd713 configure: Tweak autoconf/automake files to detect x86_64 features
* a122e0262 lib/pbkdf2: Optimize PBKDF2 by reusing HMAC handle
* 961e38b2b lib/crypto: Introduce new HMAC functions to reuse buffers
* 59304a7b5 docs: Document argon2 and argon2_test modules
* 28dbe8a3b kern/misc: Implement faster grub_memcpy() for aligned buffers
* da01eb0c5 tests/util/grub-fs-tester: Use Argon2id for LUKS2 test
* c1bd9fc82 tests: Integrate Argon2 tests into functional_test
* 6a525ee64 tests: Import Argon2 tests from libgcrypt
* 6052fc2cf disk/luks2: Add Argon2 support
* 66b8718f9 argon2: Introduce grub_crypto_argon2()
* de201105d libgcrypt/kdf: Fix 64-bit modulus on 32-bit platforms
* 93544861b libgcrypt/kdf: Remove unsupported KDFs
* 1ff720641 libgcrypt/kdf: Get rid of gpg_err_code_from_errno()
* 0c06a454f libgcrypt/kdf: Implement hash_buffers() for BLAKE2b-512
* bc94dfd54 crypto: Update crypto.h for libgcrypt KDF functions
* 5b81f490c util/import_gcry: Import kdf.c for Argon2
* 6b5c671d3 commands/menuentry: Fix for out of bound access
* 21cdcb125 tests/tpm2_key_protector_test: Add a test for PCR Capping
* afddba012 tpm2_key_protector: Support PCR capping
* ae7a39900 tss2: Implement grub_tcg2_cap_pcr() for emu
* 7b39970e9 tss2: Implement grub_tcg2_cap_pcr() for ieee1275
* 39f98e471 tss2: Implement grub_tcg2_cap_pcr() for EFI
* d47d261ec tss2: Introduce grub_tcg2_cap_pcr()
* b2549b4d3 tss2: Add TPM2_PCR_Event command
* e1b9d92a8 loader/i386/linux: Transfer EDID information to kernel
* a8379e693 fs/hfsplus: Allow reading files created by Mac OS 9
* c5ff0d616 docs: Fix build warnings in libgcrypt and blsuki doc
* fa93f2412 kern/command,commands/extcmd: Perform explicit NULL check in both the unregister helpers
* 9a725391f commands/efi/tpm: Call get_active_pcr_banks() only with TCG2 1.1 or newer
* 894241c85 kern: Include function name on debug and error print functions
* 75a20cc14 kern: Make grub_error() more verbose
* 8abbafa49 net/tcp: Fix TCP port number reused on reboot
* 3dff10a97 docs/grub: Document appended signature
* 0f2dda8cf docs/grub: Document signing GRUB with an appended signature
* 0b59d379f docs/grub: Document signing GRUB under UEFI
* dbfa3d7d7 appended signatures: Verification tests
* 7f68c7195 appended signatures: GRUB commands to manage the hashes
* 6cb58b1c9 appended signatures: GRUB commands to manage the certificates
* ab7b17717 appended signatures: Using db and dbx lists for signature verification
* 97f7001e1 appended signatures: Create db and dbx lists
* b5e872417 appended signatures: Introducing key management environment variable
* 76158ed1a powerpc/ieee1275: Read the db and dbx secure boot variables
* 069f3614e appended signatures: Support verifying appended signatures
* f8e8779d8 powerpc/ieee1275: Enter lockdown based on /ibm, secure-boot
* e95c52f1f appended signatures: Parse X.509 certificates
* a33754979 appended signatures: Parse PKCS#7 signed data
* 3e4ff6ffb appended signatures: Parse ASN1 node
* 7d28bdb0b appended signatures: Import GNUTLS's ASN.1 description files
* 1fca5f397 grub-install: Support embedding x509 certificates
* aefe0de22 pgp: Rename OBJ_TYPE_PUBKEY to OBJ_TYPE_GPG_PUBKEY
* f826cc8b0 crypto: Move storage for grub_crypto_pk_* to crypto.c
* 31cc7dfe5 powerpc/ieee1275: Add support for signing GRUB with an appended signature
* ee789e1a6 lib/b64dec: Use grub_size_t instead of size_t for _gpgrt_b64dec_proc() function definition
* abb8fb6d1 util/grub-mkimagexx: Fix riscv32 relocation offset
* 1f9092bfd libgcrypt: Allow GRUB to build with Clang
* 1d2ee8f8b tests: Add test ISO files to dist package
* dfa3dbf61 tests: Test dates outside of 32-bit Unix range
* 6837293b8 lib/datetime: Support dates outside of 1901..2038 range
* 02788bfdf bootstrap: Ensure shallow gnulib clone works on newer git
* 4e42199f3 docs: Correct some URLs
* 733cc28eb docs: Update Future section to reflect current release
* 54c8573ef docs: Document new libgrypt modules
* 1562dee69 docs: Clarify section heading and fix wording
* cf1b75a14 BUGS: Update to point to bug tracking system
* 236663dfb INSTALL: Document libtasn1 needed for grub-protect
* 7bfb38627 po: Update translations to build with gettext 0.26
* 49e76ad16 term/efi/console: Treat key.scan_code 0x0102 (suspend) as Enter
* de72f3998 util/bash-completion.d/Makefile.am: s/mkrescure/mkrescue/g
* 14c2966c7 blsuki: Add uki command to load Unified Kernel Image entries
* 5190df851 blsuki: Check for mounted /boot in emu
* 51b960132 util/misc.c: Change offset type for grub_util_write_image_at()
* 8cee1c284 blsuki: Add blscfg command to parse Boot Loader Specification snippets
* e016d6d60 kern/misc: Implement grub_strtok()
* 587db89af kern/xen: Add Xen command line parsing
* b2a975bc5 include/xen/xen.h: Add warning comment for cmd_line
* 19c698d12 zfs: Fix LINUX_ROOT_DEVICE when grub-probe fails
* 6898fcf74 relocator: Switch to own page table while moving chunks
* 67a95527b configure: Generate tar-ustar tarball instead of tar-v7
* 29d515b4c build: Add new libgcrypt and libtasn1 related files to EXTRA_DISTS
* eb76b064d build: Add util/import_gcrypt_inth.sed to EXTRA_DISTS
* eb56a6af9 include/xen/xen.h: Rename MAX_GUEST_CMDLINE to GRUB_XEN_MAX_GUEST_CMDLINE
* 80df5e132 loader/arm64/xen_boot: Set correctly bootargs property for modules
* 6831d242a loader/efi/linux: Return correct size from LoadFile2
* f326c5c47 commands/bli: Set LoaderTpm2ActivePcrBanks runtime variable
* 0e367796c docs: Write how to import new libgcrypt
* b930bfa37 libgcrypt: Fix a memory leak
* d48c277c4 libgcrypt: Don't use 64-bit division on platforms where it's slow
* de49514c9 util/import_gcry: Fix pylint warnings
* 334353a97 util/import_gcry: Make compatible with Python 3.4
* 2a6de4209 libgcrypt: Import blake family of hashes
* e54187912 libgcrypt: Ignore sign-compare warnings
* e3b78e49c libgcrypt: Remove now unneeded compilation flag
* e23704ad4 libgcrypt: Fix Coverity warnings
* d65810b01 keccak: Disable acceleration with SSE asm
* f808ef0d2 tests: Add DSA and RSA SEXP tests
* 0739d24cd libgcrypt: Adjust import script, definitions and API users for libgcrypt 1.11
* 3e1c2890b b64dec: Add harness for compilation in GRUB environment
* 5ca0d5e41 b64dec: Import b64dec from gpg-error
* 3312af6e0 libgcrypt: Import libgcrypt 1.11
* a0d4c94ef loader/efi/linux: Use shim loader image handle where available
* 1b9a84e63 loader/efi/chainloader: Use shim loader image handle where available
* e31d0cd7f efi/sb: Add API for retrieving shim loader image handles
* ed7e053a3 efi/sb: Add support for the shim loader protocol
* 70897d3d3 efi: Provide wrappers for load_image, start_image and unload_image
* 030a70fca loader/arm64/xen_boot: Consider alignment calling grub_arch_efi_linux_boot_image()
* e82609a47 loader/arm64/xen_boot: Use bool instead of int
* d1a470b69 loader/arm64/xen_boot: Remove correctly all modules loaded by xen_module command
* cf5e52fa8 dl: Fix grub_dl_is_persistent() for emu
2025-12-23 22:04:30 +01:00
Leah Rowe 8b338404e8 hp8300cmt and dell 780: use legacy verbs
see patches. coreboot making changes upstream. these
are used in the meantime.

this prevents build errors. (again, see patches, specifically
the 780 one explains rationale)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-23 18:49:47 +01:00
Leah Rowe 0ff8110a55 fix 3050micro vbt path again
i got the variable wrong, putting the dollar sign inside
the brackets, rather than outside.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-23 12:15:06 +00:00
Leah Rowe ce302356fc coreboot/dell3050: fix VBT-related build error
During routine build testing, I noticed that the VBT path was
wrong, because this port had been converted into a variant.

This is because of the OptiPlex 5040 port that is under
review on the coreboot Gerrit website.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-23 11:15:43 +00:00
Leah Rowe 2fe3b6ee66 actually enable TBT on T580
lbmk uses make-oldconfig before running a build anyway,
so it would have been fine. however, it's best to just
enable it outright.

this change was generated by doing:

./mk -u coreboot t580_vfsp_16mb

which runs make-oldconfig on the configs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-22 11:58:38 +00:00
Leah Rowe 6e253b3e73 thunderbolt support for thinkpad t580
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-22 11:10:05 +00:00
Leah Rowe 9142c8b419 ThinkPad T580 support.
Yes.

Thank you Johann C. Rode for this excellent coreboot port.

You're a star.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-21 14:49:53 +00:00
Leah Rowe 992b03a383 coreboot/default: use 3rdparty/cmocka by default
this is used by the coreboot build system, for tests.

upstream tries system cmocka by default, but we want the
one in 3rdparty to be used.

i've changed the default to 0 (try 3rdparty cmocka). you
can still override this at runtime.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-21 14:48:30 +00:00
Leah Rowe e7628421d7 coreboot/default: add cmocka submodule
otherwise, we get the following from coreboot's build
system, when performin operations in it:

tests/Makefile.mk:31: No system cmocka, build from 3rdparty instead...

However, *we* (Libreboot project) patch coreboot's build system,
so as to not download submodules itself, because lbmk handles
them manually. This is because lbmk's submodule handling has some
extra redundancy features.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-21 14:48:30 +00:00
Leah Rowe 946ede9e7d fix ifdtool build on coreboot/default
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-21 14:48:30 +00:00
Leah Rowe 24f25bf7bc update deguard
this adds the recent kaby thinkpads

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-19 08:17:44 +00:00
Leah Rowe 63b527e8ff cb/default: bump to rev def7aa7094, December 2025
latest coreboot revision of of today / right now at the
time of this commit

this brings the following upstream changes:

* def7aa7094 arch/riscv/smp: Fix race condition
* fc37085ddb Documentation/vboot: Update vboot supported boards list
* 5bb7a83a7a acpi/acpi_apic.c: Generate MADT LAPIC entries based on current mode
* 077191641b vendorcode/amd/opensil/Makefile.mk: Add 0x prefix for BIOS address
* 4b353affd4 soc/amd/common/acpi/lpc.asl: Add HPET device
* 0a867b3971 acpi/ivrs: Fill second EFR image value
* 92f03c0c28 mb/google/ocelot/var/kodkod: Config touchpad I2C frequency
* a923470688 drv/intel/mipi_camera: Remove duplicate comments for DSM methods
* 896984e800 mb/google/bluey/quartz: Enable parallel charging support
* de87ea0efa mb/google/bluey: Add parallel charging infrastructure
* cfb0d8a144 mb/google/bluey: Enable PD negotiation when battery is missing
* ddc1b51b43 mb/google/bluey: Enable PD negotiation in charging modes
* c4ee22e267 Reapply "mb/google/bluey: Implement EC-based off-mode detection"
* a225eefd4c drivers/spi: Add Macronix MX77U51250F chip id
* 793c15a866 mb/google/ocelot: Fix Gen4 SSD power sequencing
* b689671e79 include/acpi/acpi_apei.h: Add MCE APEI structs
* 7a41dc416b include/acpi/acpi_apei.h: Add NMI APEI struct
* 5251284e39 include/acpi/acpi_apei.h: Add PCIe APEI structs
* 53350d5c8d include/acpi/acpi_apei.h: Add internal acpi_head_t struct
* 5001b07f9c drivers/intel/mipi_camera: Add validation and remove unused defaults
* 0f1ae4ae5f drivers/gfx/generic: Add support for non-VGA devices
* ae0d232402 drivers/intel/mipi_camera: Add ACPI device type selection
* 1532eb60ee drv/intel/mipi_camera: Add CVF Support DSM function
* a64b93562d drv/intel/mipi_camera: Add I2C V2 DSM function
* c8f89e00e4 drv/intel/mipi_camera: Refactor DSM generator functions
* ea099e8b8c drivers/intel/mipi_camera: Split DSM generation into per-UUID functions
* 6459a2007a mb/{google,intel}: Add ROM type and address for MIPI camera sensors
* 11ea868b02 mb/google/volteer/var/drobit: Update pl2 minimum value
* 8ed87f71ec mb/google/volteer: Make touchpad wake user-selectable via CFR
* 7e1962a3cc mb/google/hatch: Make touchpad wake user-selectable via CFR
* 152914272c device/azalia: Drop spurious read-back of STATESTS
* 6e074550a5 device/azalia: Repurpose azalia_set_bits() for link-reset only
* ecf202b8e4 device/azalia: Add missing 521us delay after RESET# de-assertion
* d5d27badd4 Documentation: Add coreboot release 26.03 template
* 8e23c46beb Docs/releases: Update release notes for 25.12 release
* 01bc527afa soc/qualcomm/common: Add CMD-DB driver support
* 2277edff88 soc/qualcomm/x1p42100: Split dram_aop region to map dram_aop_cmd_db as non-cacheable
* a4cc178486 soc/qualcomm/common: Map AOP CMD-DB region as uncached region in MMU
* 1b5f105595 mb/google/ocelot/var/ocelot: disable ISH UART0 RX pin
* b67725d3f5 Revert "mb/google/bluey: Implement EC-based off-mode detection"
* 1dc3e45f7c mipi: Support passing user data to mipi_cmd_func_t
* 42c1947d99 mb/google/bluey: Implement EC-based off-mode detection
* e54b82b85b mb/google/ocelot/var/kodkod: Enable pcie_rp5 to allow proper enumeration of pcie_rp6
* 4cc830349c mb/google/rex/var/karis: Add fw_config probe to enable all wifi
* 173a32aa55 MAINTAINERS: Add Jayvik Desai to Google Bluey & Qualcomm SoCs
* f28997dcdd soc/qualcomm/common: Add PD negotiation attribute macro
* b70309350f arch/x86/acpi_bert_storage.c: Fix Error Section GUID compare
* 847d91b82e include/acpi/acpi_apei.h: Update APEI structs for better readability
* 679ea61d4d include/acpi/acpi_apei.h: Add APEI definitions
* eb79807bec soc/qualcomm/x1p42100: Add mainboard hook for QcLib override
* 8ece648c30 soc/qualcomm/common: Use bitwise OR for global_attributes
* 22e54a701d soc/qualcomm/x1p42100: Add AOP, QDSS, and QSEE regions to SSRAM layout
* 4d53aa7704 soc/qualcomm/x1p42100: Relocate PRERAM stack to BSRAM memory
* a26b718d5a soc/qc/x1p42100: Define pre- & post-RAM stack regions in linker script
* 1b599a8844 arch/arm64: Add an alternative entry point for ramstage code
* 641f7ac677 arch/arm64: Introduce distinct PRERAM and POSTRAM stack regions
* 2183326306 soc/qualcomm/x1p42100: Rename qcsdi region to aop_sdi in memlayout
* fad9878a3e vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP headers to FSP WCL.3393.02
* 71b79018da util/release/genrelnotes: Restore to saved HEAD instead of origin/main
* 9f6e297399 vc/intel/fsp/mtl: Fix license header in MemInfoHob.h
* 2171af0f5f mb/lenovo/sklkbl_x280: Fix build failure
* a5d3c4c119 mb/lenovo/sklkbl: Fix headphone jack
* 0b4d41004d mb/lenovo/sklkbl: Add Lenovo Thinkpad X280 as a variant
* 9a3818f9b6 soc/mediatek/common: Print DRAM calibration status as string
* 1e8cea55a0 soc/mediatek/common/emi: Cache SDRAM size
* 9203cc827f soc/mediatek/mt8196: Add MTE tag memory to bootmem
* 3d5135fdd0 lib/bootmem: Add memory type for Armv9 MTE tag storage
* 2d45723d87 lib/bootmem: Add bootmem_add_range_from function
* 4f78a40f53 mb/google/ocelot/var/ocicat: Update Touchscreen settings
* 510f1950b4 mb/google/ocelot/var/ocicat: Update devicetree
* 35cb6aea50 mb/google/hatch: Fix CFR pointer
* 8f34fdfab3 Remove <swab.h> and swabXX() functions
* d556bc65c2 mb/google/fatcat/var/ruby: Change GPIO pins to fix audio function
* 6b5a872ce8 soc/mediatek: Pass dsi_regs/mipi_tx_regs to DSI API
* 74c13eead4 soc/mediatek/mt8196: Define dsi_regs/mipi_tx_regs structs
* a3317182ff soc/mediatek/common: Move dsi0 definition to dsi_register_v*.h
* 3607024944 soc/mediatek: Move mtk_dsi_init declaration to display_dsi.h
* 7ef424c75e soc/mediatek/common: Rename mipi_tx to mipi_tx0
* cf0b91d774 soc/mediatek: Move dsi_regs/mipi_tx_regs definitions to soc/dsi_reg.h
* 403a42f1f0 soc/mediatek/mt8173: Fix mipi_tx1 address
* 72010408b5 mb/google/eve: Add CFR option menu support
* c36b149392 mb/google/eve/Makefile: Organize and group entries by stage
* f61ecfa154 mb/google/link: Add CFR option menu support
* 75460f531c mb/google/poppy: Add CFR option to enable/disable IPU cameras
* ae8f2d8cee mb/google/poppy: Add CFR option menu support
* 99d67bae63 mb/google/glados: Add CFR option menu support
* 0d81d38a31 mb/google/skyrim: Add CFR option menu support
* c397821cb6 mb/google/guybrush: Add CFR option menu support
* c1f0be39da mb/google/zork: Add CFR option menu support
* d105934073 mb/google/kahlee: Add CFR option menu support
* 46a32a2b56 mb/google/sarien: Add CFR option menu support
* e3bee6397d mb/google/rex: Add CFR option menu support
* d0345005ad mb/google/brox: Add CFR option menu support
* ee599486ac mb/google/dedede/galtic: Add CFR option for touchpad type
* 7a78543eca mb/google/dedede/drawcia: Add CFR option for touchscreen selection
* 1890c6d165 mb/google/dedede: Add CFR option menu support
* bd89858f09 mb/google/brya: Add CFR option menu support
* a58e0704c7 mb/google/volteer: Add CFR option menu support
* 8b34490137 mb/google/drallion: Add CFR option menu support
* 0762c7d6ee mb/google/drallion/Makefile: Organize and group entries by stage
* 89902e8c80 mb/google/hatch: Add CFR option menu support
* 0f93d154b2 mb/google/octopus: Add CFR option menu support
* f0346845cd mb/google/reef: Add CFR option menu support
* 2b959f4560 mb/google/puff: Add CFR option for automatic fan control
* a8a77f9da2 mb/google/fizz: Add CFR option for automatic fan control
* cde4280796 soc/intel/apollolake: Add CFR objects for existing options
* 2e10f75751 mb/google/sarien: Increase size of SMMSTORE to 512KB
* 91c6a0b5e6 mb/google/reef: Increase size of SMMSTORE to 512KB
* 36a345f99e mb/google/octopus: Increase size of SMMSTORE to 512KB
* d7cb2d2bc5 mb/google/drallion: Increase size of SMMSTORE to 512KB
* d32a372846 drivers/smmstore: Increase default size of store to 512KB
* c109fc92ff libpayload: Add API to get physical memory size
* 519332de10 mb/google/fatcat/var/ruby: Modify VCCCORE VR Fast Vmode ICC limit
* 7f93e2fe29 soc/intel/*: Add CFR option to enable/disable the Intel iGPU
* d5ea359347 soc/intel/**/cfr.h: Fix typo of "ACPI" in UI help text
* 02a2fe7907 Merge coreboot and libpayload <endian.h> into commonlib
* 5eb7b8bd34 payloads/external/edk2/Makefile: Set SMBIOS to 3.0.0
* c3afc13a0a soc/qualcomm/x1p42100: Update memlayout for BL31 region and realign TA region
* 04f83ff7dc cpu/x86/mtrr: Simplify MTRR solution calculation on AMD systems
* 6957f84aa7 soc/qualcomm/x1p42100: Define MDSS domain registers for display clock enablement
* 9a95aef482 soc/qualcomm/common: Add API to enable Lucidole PLL for X1P42100
* 5eaf85d19b soc/intel/skylake: Use CSE reset status for reset
* 84a4cdc6a5 soc/intel/*: Only skip PMC fallback on successful CSE reset
* 4f52ca6ba6 soc/intel/common/cse: Return usable error codes
* 8795680828 cpu/x86/lapic/lapic.c: Set spurious interrupt vector to 0xF
* 41348477e3 sb/intel/common/firmware/Makefile.mk: fix INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE
* c11faad2bf mb/google/skywalker: Correct MIPI panel power sequence
* 459cdd09f4 mb/google/rauru: Add variant-specific firmware config
* fee2befc82 3rdparty/blobs: Update to upstream main
* 626789b40a mb/siemens/mc_ehl{1..5}: Unify devicetrees SerialIoI2cPadsTermination
* 0513c45a38 mb/google/nissa/var/pujjoga: Generate RAM ID for MT62F1G32D2DS-031RF WT:C
* 4a5d0dee4a soc/mediatek/mt8189: Correct AUX LDO mask bit definition
* db01aa6cb2 commonlib/device_tree.c: Fix skipping NOP tokens
* 29bec62a22 cpu/x86/Kconfig: Remove SOC_SETS_MSRS option
* f4aeac4276 soc/amd/glinda: Set FSP UPDs from devicetree for USB4
* f68450e39b vendorcode/amd/fsp/glinda: Update FSP UPDs
* 244e8edf18 soc/amd/glinda/Kconfig: Add Faegan SoC as Glinda variant
* 9e5c7eb3f8 soc/amd/glinda: Add XGBE devices
* 87475d693a soc/amd/glinda: Remove set_resets_to_cold
* dcd4f07188 soc/amd/common/fsp: Fill in DIMM voltages
* 8929659d93 soc/amd/common/acpi/lpc.asl: Report ESPI1 fixed resource
* 3053cd2dad soc/amd/common/acpi/lpc.asl: Report fixed base addresses
* 7e1aa974bf soc/mediatek/common: Refactor mtk_ddp_mode_set to support dual DSI and DSC for MIPI
* 3aaeca8378 soc/mediatek/common: Refactor mtk_dsi_dphy_timing
* aeee9450a2 mb/google/ocelot/var/matsu: Add fw_config definitions with UFSC
* 67a7e06c38 drivers/tpm: Remove duplicated op
* ac5c57d24a drivers/tpm/ppi: Fix generated ACPI
* d922ad79c6 mb/google/fatcat/var/ruby: Add firmware configuration fields with UFSC
* 980c269643 mb/google/ocelot/var/ojal: Enable Audio Codec and update FW config
* 8e7975edfd mb/google/ocelot/var/ojal: enable CS42L43 driver options
* 9a6d1d4d69 mb/ocelot/var/ocicat: Modify ocicat Kconfig for bring up
* 94fe4c6926 mb/google/ocelot/var/kodkod: Add wake configuration to cnvi_bluetooth
* e3588d82bc mb/google/ocelot/var/kodkod: Enable CNVi Wi-Fi and BT cores
* 36edc2e371 soc/qualcomm/x1p42100: Add Dload mode detection and ramdump packing
* 26a18c674d acpi: Clear whole FACS table before filling it
* 5a6addca4b mb/google/fatcat/var/ruby: Change GPIO pins to fix audio function
* e6a8143d8b drivers/intel/touch: Add support for new Intel touch I2C _DSD entries
* 25c4501223 device/dram/ddr3: Fill in voltage fields for SMBIOS type 17
* 273a41c4d9 commonlib/memory_info: Introduce new fields to memory_info structure
* abe1ac0744 mb/google/brya/var/uldrenite: Add memory MT62F1G32D2DS-031RF WT:C
* 0599f3e1bd mb/google/bluey: Condition slow charging enablement on charger presence
* 8b3ceacd93 ec/google: Check AC charger presence by reading host event register
* 5b544c67eb mb/google/rauru: Add MIPI panel support with BOE NS130069-M00
* ed9239cd85 mb/google/nissa/var/gothrax: Add Samsung parts to RAM ID table
* 445961c604 soc/qualcomm/common: Add support for loading ramdump image
* 3c563669b5 soc/qualcomm/x1p42100: Add support for APDP image packing in CBFS
* 1d70286d4e soc/qualcomm/common: Add support for loading APDP image
* fc9f828ac0 mainboard/google/bluey: Select VBOOT_ALWAYS_ENABLE_DISPLAY
* c77d256886 {mb, security}: Use EC_REBOOT_FLAG_IMMEDIATE for cold reboots
* 1a0d123ec1 ec/google/chromeec: Update EC headers
* 3bd554feb2 soc/mediatek/mt8196: Align the struct for storing DRAM calibration data
* 33fc33c132 soc/amd/common/block/cpu/noncar: Add support for bootblock CRTM init
* 8b97968e53 soc/amd/common/block/pci/amd_pci_mmconf.c: Support 64bit ECAM MMCONF
* 7a98a62f7b drivers/intel/gma: Unify coding style
* 23b00a06da drivers/intel/gma: Fix brightness handling with valid-cache logic
* 4068ba39f8 soc/intel/common/block/rtc/rtc.c: Top Swap: add Slot B selection mechanism
* a65b874472 mb/dell: Convert OptiPlex 3050 into variant
* 2ce1068542 mb/google/ocelot/var/ojal: Decrease display count from 5 to 4
* b31e62ae5c mb/intel/ptlrvp: Add LPCAMM T3 RVP board support
* 58cdf9e668 soc/intel/pantherlake: Add LPCAMM memory support
* 67777b7671 soc/intel/common: Add LPCAMM memory topology support
* bb18e0b91d mb/google/skyrim: Increase size of SMMSTORE to 512KB
* dd1e54efc0 mb/google/zork: Increase size of SMMSTORE to 512KB
* 60e375fae4 mb/google/guybrush: Increase size of SMMSTORE to 512KB
* eb52862132 mb/google/brox/var/caboc: Update SSD port and FPMCU setting
* 85101704ae mb/ocelot/var/ocicat: Create ocicat variant
* 2975d7220a mb/google/ocelot/var/matsu: Update devicetree
* 0e9d85425e mb/google/ocelot/var/matsu: Fix GPP_V3 internal pull-up configuration
* 4f257a28f8 mb/google/ocelot: Add EC_GOOGLE_CHROMEEC_SKUID config
* db2ac42405 soc/mediatek/common: Refactor DDP mode setting
* d51f780515 mb/siemens/mc_rpl: Correct SMBIOS socket type to BGA1744
* 2f95552802 mb/siemens/mc_ehl: Move Kconfig switch to variants
* 3c49c13995 util/ifdtool: fix typo PSL->MSL
* a87e699f04 mb/lenovo/m900_tiny: Enable Vboot
* afc191357f 3rdparty/intel-microcode: Update to upstream main
* cbfa28b06e mb/google/fatcat/var/ruby: Modify power limit configuration
* f13e800a71 mb/amd/crater/Kconfig: Use A/B recovery scheme for renoir
* 416f67f670 vendorcode/amd/fsp/.../fsp_h_c99.h: Use fsp2_0 structs
* b94a84a792 drivers/efi: Exclude verstage from EFI variable store files
* bae5262c69 include/option: Add verstage stub for UEFI variable store backend
* 2d78478345 drivers/intel/gma: Reapply cached brightness once BCLM is valid
* 2ad08f9d72 drivers/intel/gma: Expose full brightness ladder
* 2e96a71e6f drivers/intel/gma: Cache brightness level
* 36632a08a8 soc/qualcomm/x1p42100: Reserve 33 MB DRAM memory for Display requirement
* 5807b59fc5 mb/google/rauru: Report panel ID for sapphire
* 49da58dccf drivers/mipi: Add support for BOE NS130069-M00 panel
* e9ebcb2918 mb/{google,intel}: Fix MIPI camera VCM type and address configuration
* 30b4383944 mb/{google,intel}: Set SSDB platform field for MIPI camera sensors
* 4c025191c7 drivers/intel/mipi_camera: Remove disable_ssdb_defaults option
* c75236d436 drivers/intel/mipi_camera: Set additional SSDB defaults
* 866b79c9fe drivers/intel/mipi_camera: Always generate PLD for camera sensors
* c6ed8c91fb drivers/intel/mipi_camera: Document more SSDB fields
* 423fbcd06b drivers/intel/mipi_camera: Adopt SSDB sensor SKU bitfield
* aa18a6fe8d drivers/intel/mipi_camera: Codify SSDB field enums
* f8d12a0bdb drivers/intel/mipi_camera: Add SSDB platform subtype enum
* 99cb6415ba drivers/intel/mipi_camera: Rename flash enum to match SSDB field
* c91ea7c582 drivers/intel/mipi_camera: Flesh out SSDB platform enum
* 0361e1a865 drivers/intel/mipi_camera: Verify SSDB struct size at build time
* b5d68e41a2 drivers/intel/mipi_camera: Tidy SSDB comment wrapping
* ab4c2fd0e8 drivers/intel/mipi_camera: Extract SSDB definitions into separate header
* d09ea1c351 cpu/intel: Add SMBIOS Socket BGA1744 type
* d97cb61b50 ec/google/chromeec: Add CFR option for RGB keyboard boot color
* e695731399 ec/google/chromeec: Add RGB keyboard helper functions and enum
* 4eb524ee9d spd/ddr4: Add three more parts
* e4a809d441 spd/ddr4: Double packageBusWidth of dual die package parts to 16
* 8753155f71 mb/google/slippy/var/peppy: Add CFR menu option for touchpad type
* 6f6a10df88 mb/google/slippy: Add CFR option menu support
* e366e0ba7d mb/google/slippy/Makefile: Organize and group entries by stage
* 6be83443e5 mb/google/auron/var/lulu: Add CFR option to enable/disable touchscreen
* 88d3f563b3 mb/google/auron: Add CFR option menu support
* 7ed515d1c3 mb/google/auron/Makefile: Organize and group entries by stage
* e15895b5c4 mb/google/poppy/var/nautilus/acpi: Fix CI02 comment
* 4dc03c54fc mb/google/poppy/var/nocturne: Hide FPR device in ACPI
* e85a0b7ff1 mb/google/puff: Remove unsupported EC features
* 3459502e0c mb/starlabs/starfighter: Enable pmc_shared_sram device
* 9b0af48604 mb/starlabs/starbook/mtl: Update GPIO config
* d3d4571411 soc/intel/common/block/graphics: Use Xeon W-11865MRE IGD PCI ID
* 1cfe413f95 soc/intel/common/block/lpc: Support RM590E eSPI
* c195859748 soc/amd: add ACPI code for I3C controller
* 02342b31df soc/amd/*/memmap.c: Report FCH MMIO regions as reserved
* 5078d32ccc mb/google/brya: Enable ACPI S3 sleep state support
* eb504eb49a mb/samsung/lumpy: Fix HDA pin configuration issues
* afd5e5d444 mb/samsung/lumpy: Convert HDA verbs to use AZALIA_PIN_DESC macros
* 109672a9a9 drivers/intel/gma: Guard legacy brightness fallback
* 908c2b54c6 mb/starlabs/starbook/mtl: Fix Card Reader USB Port
* 796d3b37aa mb/google/fatcat/var/moonstone: Update fw_config definitions with UFSC
* 2ce4e09469 drivers/intel/fsp2_0: Add typedef FSP_UPD_HEADER
* 7afe1e9f9d mb/google/fatcat/var/lapis: Adjust touchpanel power on timing
* 36f4341533 mb/starlabs/starfighter: Add Arrow Lake (285H) variant
* 80cf2008a9 spd/lp5: Add SPD for MT62F1G32D2DS-031RF WT:C
* f1d1c825dc mb/siemens/mc_rpl1: Enable IBECC
* 866a0591f7 mb/siemens/mc_rpl1: Set coreboot ready LED
* 801795d4dd mb/siemens/mc_ehl6: Alphabetize Kconfig options
* 1a11dca12d mb/siemens/mc_ehl6: Send POST codes to NC FPGA via PCI
* fceb033372 mb/siemens/mc_ehl6: Limit PCIe RP7 speed to Gen2
* 760c3f6abc mb/siemens/mc_ehl6: Activate SATA interface port 1
* 54f2652bde mb/siemens/mc_ehl6: Enable auto impedance calibration on GbE 0
* b6e7f3e005 mb/siemens/mc_ehl6: Change GbE LED settings
* aad2b715ea mb/siemens/mc_ehl6: Remove PSE GbE 1
* e19f2b313e mb/siemens/mc_ehl6: Enable PCHHOT_N via GPIO
* 43d5f70576 mb/siemens/mc_ehl6: Enable PTM for all enabled PCIe RPs
* 864e3ca661 mb/siemens/mc_ehl6: Adjust I2C setup
* 31f44f5521 mipi: Add DSC configuration and rate control parameters to panel header
* 743e31939c drivers/intel/fsp2_0/.../fsp/upd.h: Fix excess endif
* 2aadfc2b5e soc/amd/common/block/acpi: Add ACPI HEST table
* cc542c15f4 include/acpi: Move Error definitions/declarations into acpi_apei.h
* 2462e3a027 soc/mediatek/mt8188: Adjust memlayout for bootblock
* 804aab3abb mb/google/fatcat/var/ruby: Modify usb3 port setting
* fecf05c4f2 mb/google/trulo/var/kaladin: Mute speaker amp to prevent pop noise on reboot
* f35cb39de5 soc/amd/cezanne: Increase APOB DRAM size for Renoir
* 384e6e1c37 soc/amd/cezanne: Remove set_resets_to_cold
* 97291b5838 soc/amd/cezanne: Optionally propagate UART0 through ACPI
* 149d11d1d8 soc/amd/cezanne/Kconfig: Select Kconfig to program the PSP_ADDR MSR
* 520bc70b57 mb/amd/crater: Configure UART1 GPIOs
* 0ed1529ce3 src/vc/amd/fsp: fix type 17 DMI info
* e8599956dc mb/amd/crater: Make NVMe reset GPIO configurable
* 67bf203e52 mb/google/nissa/var/guren: Add missing settings for WWAN
* 3dabe4f857 mb/google/brox/var/caboc: Increase I2C0 touchpad tHD to 0.53 us
* 12e763eece device/pci_ids: Add DIDs for TGL-H (GT1 and RM590E)
* 01540f036e mb/google/fatcat/var/ruby: Use spd-11 for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV
* 14e96b4ef1 mb/google/brox/caboc: Mute speaker amp to prevent pop noise on reboot
* 567186a000 mb/google/bluey: Add support for off-mode charging
* 27fcb8617d commonlib: Add CBMEM ID to store boot mode
* d6132c4c03 mb/google/bluey: Use SOC PMIC API to detect off-mode charging event
* 201ebd48ee soc/qc/x1p42100: Add APIs to read PON reason from PMIC
* 293f3a7f5c soc/qc/spmi: Add API to read byte array
* 9f675eb96b soc/qc/common: Update SPMI_ADDR macro for better type safety
* cb1045a8b8 soc/intel/pantherlake: Update GT domain TDC value for PTL_TDC_1 SKU
* b0ee0c4620 soc/intel/pantherlake: Fix IA domain TDC value for PTL_TDC_2 SKU
* 6dbcf903a5 soc/intel/pantherlake: Add ICC Max and TDC settings for SKU_7
* 2148143ae9 soc/intel/pantherlake: Separate TDC configuration for different TDPs
* c7273c8ddc mb/google/fatcat/var/ruby: Add proto touch panel address
* 8575232317 mb/google/ruby: Migrate to UFSC
* 47101fc224 soc/amd/cezanne/Kconfig: Make AMDFW_CONFIG_FILE configurable
* c9f124a8fb mb/amd/crater/ec: Make macro ENABLE_M2_SSD1 a Kconfig option
* 430e34cd0f mb/amd/crater: Move gpio configuration to early_gpio
* 14b5c004f5 mb/amd/crater/ec: Create function to get board revision
* bd858faee8 mb/amd/crater: Add XGBE support
* f61553c9fa vc/amd/fsp/cezanne: Add Renoir FSP
* 87f8d15c87 ec/google/chromeec/cfr: Fix CFR callback signatures
* 7fb0f14ebe libpayload: arm64: Fix asynchronous exception routing in payload
* b584967d04 mb/google/ocelot: Add wake configuration to cnvi_bluetooth
* fc88b62174 mb/siemens/mc_ehl6: Enable PCIe root ports and clocks
* 5a4c749520 mb/siemens/mc_ehl6: Add new board variant based on mc_ehl2
* f5f304a5f3 mb/google/skywalker: Disable CHROMEOS_USE_EC_WATCHDOG_FLAG
* e4b0410946 soc/mediatek/mt8189: Enable MEDIATEK_WDT_RESET_BY_SW
* 1ae0cebff3 soc/mediatek: Add Kconfig option MEDIATEK_WDT_RESET_BY_SW
* 7d3bf767cc soc/mediatek/mt8189: Move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C
* a64dd410d8 mb/google/fatcat/var/ruby: Update EN_SPK_PA GPIO pin configuration
* 2f9b4ad6a5 soc/qualcomm/x1p42100: Add DFSR table configuration support
* 51e99de558 soc/intel/common/block/rtc/rtc.c: control Top Swap via CMOS option
* 56be23114e mb/google/rauru: Use chromeos-legacy.fmd for Hylia and Navi
* 10802bac16 spd/lp5: Modify SPD for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV
* e5d10e5d23 mb/lenovo/t480: Fix headphone jack
* 40b2a2b03c soc/mediatek/mt8196/booker: Refactor CMO property clearing with loop
* 1b0f9c5458 mb/google/nissa/var/telith: Add parade touchscreen support
* ddb3f0b17f drivers/hwid_dmi: Populate SMBIOS product name from CBFS hwid file
* 7a1e63308a acpigen_ps2_keybd: map insert
* 607740999d acpigen_ps2_keybd: map capslock
* a7efa40e39 acpigen_ps2_keybd: map KEY_HOMEPAGE to 0xaa scancode and TK_HOME
* fd603e5102 libpayload: Add CBMEM_ID_MEMINFO to sysinfo
* bae3e02662 include: commonlib: Move memory_info and dimm_info to commonlib
* d03799ec3c soc/mediatek/mt8196: Configure registers and parameters required for MTE
* 7521f3ea83 soc/qualcomm/x1p42100: Define pre and post-RAM DMA coherent regions
* d277b35307 soc/qualcomm/x1p42100: Relocate ddr_information and watchdog tombstone
* 958099b114 soc/qualcomm: Map the post-RAM DMA coherent buffer
* 931fa9c01d memlayout: Introduce PRERAM and POSTRAM DMA coherent regions
* af9d809823 soc/qualcomm/x1p42100: Move coreboot stack to SSRAM
* fec1032ee8 arch/arm64: Add timestamps for Secure OS (BL32) loading
* d0177bd102 soc/qualcomm: Add QCLib execution timestamps
* 0145ebe847 commonlib: Add timestamps for Qualcomm QCLib and ARM TFA
* cf2978f4b6 drivers/vpd: Search VPD info at 0x0 first
* a56a97d167 mb/starlabs/common/cfr: Adjust help text for S0IX
* 541fd14fd9 mb/google/nissa/var/uldren: Increase Touch IC enable delay time
* 0c18e7680a mb/google/fatcat/var/ruby: Remove GPP_D16 and GPP_D17 in fw_config.c
* 237944186e mb/google/nissa/pujjolo: update verb table
* cae53bea52 ec/google/chromeec: Add CFR options for keyboard backlight and fan control
* 1ca1dc6c31 ec/google/chromeec: Add ability to enable auto fan control via setup option
* 450389be05 ec/google/chromeec: Add fan presence helper function
* 9d355a39aa mb/amd/crater/ec.c: Enable power/reset for PCIe lanes
* 141fd11d79 mb/amd/crater: Rename ETH_AIC_SLOT_ONLY -> PCIE_DT_SLOT
* 1e28ff6955 src/mb/amd/crater/port_descriptors_renoir.c: Prettify code
* a48fd9ed7f soc/amd/cezanne: Add SOC_AMD_RENOIR as a Cezanne variant
* 760e19e18f mb/lenovo/sklkbl: Use spd_tools infrastructure for SPD binaries
* 8a83b86254 spd/ddr4: add parts
* 0ef4bd807c mb/google/ocelot/var/ocelot: Update DDR5 memory configs
* 7b11254d58 mb/google/ocelot/var/kodkod: Add overridetree
* aa1d44b644 mb/google/ocelot/var/kodkod: Update gpio settings
* a363007c3b ec/dell/mec5035: Route power button event to host
* 18dbeca5f4 util/autoport/azalia.go: Select CONFIG_AZALIA_USE_LEGACY_VERB_TABLE
* e9c47bf99e drivers/intel/fsp2_0: Add 1-bpp monochrome option for VGA mode 12
* f643141728 mb/google/fatcat: Option to enable monochrome VGA mode 12
* e05492cfb4 soc/intel/pantherlake/romstage: Configure VGA mode 12 monochrome buffer
* d3760cdfdf mb/google/bluey: Configure QUP0 SE5 as I2C
* abc87d533d mb/google/bluey: Introduce config to specify absence of USB-A port
* 872e06d60c mb/samsung/stumpy: inline fan thresholds and drop GNVS programming
* 8401bbd2ff mb/google/fatcat/var/ruby: Change touch panel address
* a4242e5c38 ec/starlabs/merlin: Fix get_ec_value_from_option() value validation
* 567470cbb3 payloads/edk2: Add iPXE EFI support for EDK2 payload
* f40de4e162 payloads/ipxe: Default enable serial output only if CONSOLE_SERIAL
* 962edb7e6d payloads/ipxe: Guard PXE_ROM_ID for non-EFI builds
* a907c6fb8d payloads/ipxe: Default to building from master branch
* 4081793ff2 payloads/external/edk2: Replace dependencies on EDK2_REPO_MRCHROMEBOX
* 10d606bfca soc/intel/common/acpi: Add P2SB write functions
* 7436c59875 util/amdtool: Add support for Phoenix AM5 CPUs
* 8f3626c4b5 util/amdtool: Add utility to dump useful information on AMD CPUs
* 3cf976e51a soc/mediatek/mt8196: Add dual display pipe path
* 14595d64de lib/edid_fill_fb: Add dual pipe flag to lb_framebuffer_flags
* 486b1b51af mb/google/bluey: Cache low battery mode check
* 33418b7e68 soc/qc/x1p42100: Disable compression for peripheral firmware binaries
* 5bfc2d23bb soc/qc/x1p42100:: Select Secure OS options in SoC Kconfig
* f5f943c1c3 bluey/kconfig: Consolidate SPI flash driver selection
* ee59936e83 commonlib/device_tree: Add an API to check if a DT is an overlay
* 0416ac9829 mb/google/var/fatcat/lapis: Modify type-A USB3 port0/1 tx_de_emp
* dfe553aebb util/intelvbttool/Makefile: Add install target
* 493e3d182e payloads/external/iPXE: Allow building EFI target
* 62fc93de90 soc/qualcomm/x1p42100: Add NVMe Power Loss Notification GPIO configuration
* 2b7b89ae31 soc/qualcomm/x1p42100: Update PCIE PHY init sequence
* 91594f4894 drivers/option/cfr.c: Replace memcpy() to avoid uninitialized object
* 04ea4724e2 Makefile.mk: separate bootblocks into BOOTBLOCK and TOPSWAP
* f164feba3e ifittool: allow adding files from a separate region
* 91073f37d7 mb/google/brya: Increase RW_SECTION_* by 256KB for 16MiB boards
* a43498e193 util/inteltool: Enable dumping GPIOs from Tiger Lake IoT PCH
* 04778ddd38 drivers/option/cfr: Remove old sm_object from constructor
* b535db8f1e soc/intel/cmn/usb: Add helper macro for USB 3.0 port TX configuration
* c197643d44 drivers/intel/gma/acpi: Add power management methods for GFX0
* 773997c92d drivers/intel/touch: Avoid returning undefined pointer
* 9dc35142ac soc/amd/stoneyridge: Generate SATA ACPI registers at runtime
* d62653749c payloads/libpayload: Support legacy LZ4 compression format
* 29faf77d4a mb/siemens/mc_rpl1: Limit CPU RP1 to PCIe Gen2 speed
* fad0908c5b soc/intel/alderlake: Make CPU RP PCIe speed configurable
* 04d5201426 treewide: Fix include guards
* 971f10d1d7 mb/google/var/fatcat/lapis: set custom SVID/SSID to load fw for CS35L56
* ace2e540d0 soc/intel/pantherlake: Update CONSOLE_UART_BASE_ADDRESS Kconfig value
* a65d9fe589 mb/google/fatcat: Remove FSP_UGOP_EARLY_SIGN_OF_LIFE from Lapis
* 729918628d 3rdparty/blobs: Update to upstream main
* d4bee96484 mb/lenovo/sklkbl: refactor memory_init_params to use gpio_base2_value()
* 2a9deabc35 commonlib/coreboot_tables.h: Fix lb_smmstorev2 alignment
* 0ba4505024 payloads/external/edk2/Makefile: Configure AP wakeup in UEFI payload
* 87c3373925 mb/google/fatcat: Add FW_CONFIG Support for TAS2563
* e08a35f806 drivers/sof: Add support for tas2563 speaker topology
* a3ea128ecf drivers/i2c/tas2563: Add driver for generating device in SSDT
* 240e17025c src/soc/intel/ptl: Add LPSS UART DMA control
* afa6c31ef5 soc/intel/alderlake/romstage/fsp_params.c: Refactor `pcie_rp_init()`
* ec5b5386d4 soc/intel/mtl/romstage/fsp_params.c: Refactor `pcie_rp_init()`
* 4c5c62bc8d mb/google/fatcat/var/ruby: Modify gpio pin for enabling audio function
* 2804a0d771 mb/google/fatcat/var/lapis: Update fw_config definitions with UFSC
* 0e1742a7e2 mb/google/bluey: Control slow battery charging via boot mode
* 113cef70fd soc/intel: Move USB port macros (2.0/3.0/TCSS) to IA common header
* 3c69295ce4 mb/google/fatcat/var/ruby: Add new supported memory part
* d18cc50e6a soc/intel/xeon_sp: Use common smm_relocate
* d0c936eea1 mb/google/nissa/var/guren: Tune SX9324 register for 5G LTE module
* 8851b5b0e7 soc/intel/pantherlake: Program HDA SVID/SSID
* c917ecf21e soc/intel/{adl,mtl}: Fix CLKSRC handling for compliance mode
* 312d455a93 soc/intel/{adl,mtl}/romstage/fsp_params.c: Fix printf specifier
* 786ac14d48 drivers/option/cfr: Add optional override table for default values
* ea84a29a27 mb/google/trulo/var/pujjoquince: Enable Bayhub LV2 driver
* 84e000b88e libpayload: arm64: Fix alignment for exception_state
* 9210f2fd1c mb/google/fatcat/var/lapis: add ILITEK touchscreen support
* b933a554ba mb/google/var/fatcat/lapis: Modify fw_config for audio and touch
* b3b7b7a027 mb/emulation/qemu-q35/Makefile.mk: Use all-y for memmap.c
* bb3e59051a mb/google/brya: Check power state before process _ON method for BT
* 0f7c54d7d1 mb/google/fatcat/var/felino: Disable card reader in coreboot
* 7946d2d65d mb/google/fatcat/var/felino: Add reset_gpio for SSD RTD3 configuration
* 8e2567c7a9 mb/google/fatcat/var/lapis: Adjust touchpad I2C frequency
* f8da2bf9b2 mb/google/fatcat/var/ruby: Modify camera enable gpio pin.
* 45163509cf util/cbfstool/cbfs-payload-linux.c: Remove TODO
* bdcd65bd7f ec/starlabs/merlin: Add battery capacity offsets
* 224ddb85e3 ec/starlabs/merlin: Choose a better default for GPE SCI
* 696344ac01 ec/starlabs/merlin: Optimise Kconfig defaults
* 649a6a591b ec/starlabs/merlin: Correct Kconfig dependancies
* 0d35c3fcc3 mb/starlabs/starbook: Fix inclusion of CPU RP ASPM option
* 87475ef37f mb/starlabs/common: Move power profile enum to common code
* 98e0ff1e4b mb/starlabs/*: Move DMIC disabling code to common dir
* 082ad480d9 mb/starlabs/*: Separate WiFi and Bluetooth controls
* abf630c96b mb/starlabs/byte_adl: Add wireless CFR object
* a58d99575e mb/starlabs/*: Move CFR object defs to common directory
* 74dcb4c679 mb/starlabs/common: Adjust the includes inline with coreboot
* 6b30e1f46b mb/google/dedede/var/pirika: Add support memory for CXMT CXDB5CBAM-MA-B
* d4e8af407c spd/lp4x: Add CXMT CXDB5CBAM-MA-B memory
* 8d7183a904 ec/google/chromeec: Add option to set keyboard backlight level at boot
* 973d0faf65 util/amdfwtool: Move needs_ish and combo_new_rab to data_parse.c
* 8449a15aed soc/qualcomm/x1p42100: Reduce USB OTG state enable timeout to 20ms
* f4af55a008 spd/lp5: Add SPD for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV
* 9bea3130b5 mb/google/skywalker: Add AW88081 support for beep sound
* d8bcf242c6 Revert "commonlib/endian: Silence GCC -Warray-bounds false positives"
* 66039a61f1 Revert "commonlib/endian: Restore -Warray-bounds at the end of file"
* c27c9db51b mb/samsung/stumpy: Fix thermal configuration issues
* 288889cd98 mb/google/jecht: Fix thermal configuration issues
* 9fa2d55987 mb/google/beltino: Fix thermal configuration issues
* 76a48b5158 mb/google/beltino: Remove unused GNVS fan configuration
* 8cc8f219bf Documentation/drivers: Add ACPI five-level fan control documentation
* 47c4da36c4 util/amdfwtool/data_parse.c: Remove duplicate MP2_CFG_FILE
* fa23504c59 mb/siemens/mc_rpl: Alphabetize Kconfig options
* 8411fef90f mb/siemens/mc_rpl1: Switch from LPSS UART to legacy 8250 I/O UART
* 534fceb36a mb/siemens/mc_rpl1: Set PCI bridge function for NC_FPGA
* 8ce9255f82 mb/samsung/stumpy: Fix ACPI fan control FNP4 power resource
* f12f292d91 mb/google/intel/*: Fix ACPI fan control FNP4 power resource
* b9b95c917a mb/google/guado: Fix ACPI fan control FNP4 power resource
* 8a518b2134 mb/google/beltino: Fix ACPI fan control FNP4 power resource
* 6d751ef987 payloads/edk2: Drop EDK2_PCO_MMIO_EMMC Kconfig option
* 4423a0b390 payloads/edk2: Drop EDK2_UFS_ENABLE Kconfig option
* a86a5ebf7c payloads/edk2: Update default MrChromebox branch from 2502 to 2508
* 40a8466655 mb/google/fatcat: Add option to enable VGA mode 12
* 824992ddef soc/intel/pantherlake/romstage: Configure VGA mode 12 planar buffer
* 74113f5d5e drivers/intel/fsp2_0: Add options to config VGA mode 12
* 75318743c3 commonlib: Add pKVM DRNG related timestamps
* 2646eeffb2 mb/google/skywalker: Create variant Dooku
* 1b2675e4f2 soc/mediatek/mt8189: Require libbl31.a to exist
* 9c0a914192 libpayload: Fix printf edge cases for precision
* ebc2030ff7 soc/intel/pantherlake: Enable HW managed microphone privacy
* 4d9dacae16 mb/google/fatcat/var/ruby: Modify touchpad device setting to enable function
* 2821e8e2ae soc/intel/ptl: Remove redundant HAVE_BMP_LOGO_COMPRESS_LZMA Kconfig
* eadf2ee4a3 ec/starlabs/merlin/cfr: Replace integer literals with named constants
* 2bbc0f1ad3 mb/starlabs/starbook/{kbl,cml,tgl}: Control USB Bluetooth with wireless
* 2c9596555b mb/google/skyrim: Use edge (vs level) triggering for PS2K
* 0c3f304d5a mb/starlabs/byte_adl: Enable Wake On Lan
* ca5b51ef9c mb/google/bluey: Select QTEE firmware dependent Kconfig
* fe7b75d792 mb/google/fatcat/var/moonstone: Add fw_config touchscreen setting
* cfdaff3f70 commonlib/endian: Restore -Warray-bounds at the end of file
* 32ec29a51e mb/google/fatcat/var/kinmen: Disable RT721 clock stop support
* 4b50bc9e5f payloads/external/U-Boot/Makefile: Add custom repo and tag
* 3d41ac370d payloads/external/U-Boot/Makefile: Remove conditional
* c3b5c8723e ec/google/chromeec: Add function to determine keyboard backlight presence
* 7afd731849 ec/google/chromeec/acpi: Fix long battery string reporting for Windows
* bc475414c7 MAINTAINERS: Add Chen-Tsung Hsieh for MediaTek platforms
* 65dc0bdd7e mainboard/fatcat/lapis: Override PMC GPE configuration
* 4ea33e5ffa mb/google/fatcat/var/lapis: Enable THC HID over I2C mode
* 111da2557a mb/google/fatcat: Preserve VGPIO GPE for THC wake on touch
* e167e56883 mb/google/nissa/var/yavilla: Add stop pin for G2 touchscreen
* 1fa24898e2 soc/intel/common/block/pcie: Move speed helper to pcie_helpers.c
* 66f40a86de ec/starlabs/merlin: Move version offsets to ECDEFs
* 82367b8205 mb/google/ocelot/var/matsu: Add overridetree
* 05c0e16593 mb/google/ocelot/var/matsu: Update GPIO table
* 98c7be30ad mb/google/fatcat/var/moonstone: Support new schematic changes
* 5eafe672e3 vc/intel/fsp: Update WCL FSP headers to 3344_03
* 641eeca835 lib/vga_gfx: Fix left-up and right-up orientations
* a4f067c058 Makefile.mk: Align FMAP COREBOOT region to 4k boundary
* 410506b47c Makefile.mk: Print all FMAP region sizes in hexadecimal format
* c189604f43 mb/goog/ocelot/var/ocelot: Enable rp5 if PCIE WiFi detected
* 4a806a6865 ec/starlabs/merlin: Only show EC FW options for ITE EC
* 04d9a0d0f0 ec/starlabs/merlin/Kconfig: Fix typo in description/help text
* 1eda98a16e mb/siemens/mc_rpl1: Document CLKSRC 2 usage for PCIe RP5
* 1815a204b4 src/mainboard/lenovo: Add smbios_slot_desc, fix register types
* da204a92c1 vc/intel/fsp/wildcatlake: Expose PchHdaMicPrivacyMode
* 105598545e soc/intel/pantherlake: Update thermal design current parameters
* a5b51ab285 mb/google/rex/var/kanix: Add H58G66CK8BX147 to RAM ID table
* d7f427a7d2 util/xcompile: Fix compiler detection on newer Linux distros
* 82d90b1f21 Revert "mb/starlabs/*/rpl: Re-enable GpioOverride"
* 784d8f25f9 mb/google/fatcat/var/ruby: Enable panel touch function
* 56a8c40efa mb/starlabs/starlite_adl: Add missing ACPI entry for USB card reader
* 4047a44b68 sio/nuvoton/common/nuvoton.h: Add common Nuvoton SIO LDNs
* 3a1d6d5ded mb/google/brox/var/caboc: Adjust WWAN power off sequence
* b42f74122c Documentation/mb/lenovo: Adjust docs for Thinkpad T470s/T580
* 70e79f43b1 Haswell NRI: Print and fill in memory-related info
* 1730d05ec3 nb/intel/haswell: Factor out `report_memory_config()`
* 3bbfbd37e1 nb/intel/haswell: Factor out `setup_sdram_meminfo()`
* 3ffb01e9cb mb/siemens/mc_rpl1: Disable I2C1 and enable I2C6
* 4563db2807 mb/google/nissa/var/riven: Add H58G66CK8BX147 to RAM ID table
* a748e8b82b mb/google/fatcat/var/ruby: Enable touchpad function using I2C interface
* a92a2ee5d6 mb/starlabs/byte_adl: Expose fan control option in CFR
* bbb895436f mb/nissa/var/pujjoga: Add single ram configuration
* e2cf7f7dc7 soc/mediatek/common: Fix MMU assertion for framebuffer region
* a5ddfa963f mb/starlabs/starlite_adl: Increase ME region size to match IFD
* 7484a887b8 mb/google/ocelot: Fix EC sync IRQ configuration for board variants
* b1ed60b910 mb/google/fatcat/var/ruby: Disable FSP_UGOP_EARLY_SIGN_OF_LIFE temporarily
* fea1b2abbe mb/google/nissa/var/pujjocento: Adjust touch panel timing for stability
* 8f1c54685a drivers/mipi: Fix pixel clock and enable C-PHY for TM_TL121BVMS07_00C
* 979fdee1d9 soc/mediatek/mt8189: Support MIPI C-PHY interface
* 44635f328c soc/mediatek/common: Add C-PHY support for MIPI DSI
* c63e901b99 mipi: Add panel flags to support C-PHY interface
* 385ae6669b mb/gigabyte/ga-h77m-d3h/devicetree.cb: Re-enable IGD and PCIe VGA
* 2c6cf2c2a8 include/cper.h: Update CPER structures with __packed attribute
* d97644dd3f mb/asrock: Add Z77 Extreme4
* a73db6d451 mb/intel/ptlrvp: Add fw_config support for SPD selection
* 3ef1cf9f84 soc/amd/turin_poc: Add Turin SoC structure as a copy of genoa_poc
* 668d643e5c mb/lenovo/sklkbl_thinkpad: Add Lenovo Thinkpad T470s as a variant
* 8a6f9bf731 ec/google/chromeec: Update EC headers
* 745f1312aa include/cper.h: Update comments to UEFI spec version 2.10
* aab8ad98b6 mb/google/ocelot: Create kodkod variant
* 2279ba80e1 .gitignore: Add .clangd as a "Development friendly file"
* cd4af952e7 mb/google/ocelot/var/ocelot: Update DDR5 memory configs
* 1af54d9784 drivers/intel/touch: Change I2C speed type to i2c_speed enum
* 84a348f4bf ec/starlabs/merlin: Remove the fast charge option
* 1699d455e7 vc/intel/fsp: Update PTL FSP headers to FSP 3373_03
* b87a9795de tree: Use boolean for s3resume
* ec1068883f mb/google/nissa/var/guren: Add initial WWAN related settings
* 752d49a4ff mb/google/fatcat/var/moonstone: Disable RT721 clock stop support
* 155041ad4c soc/qualcomm/x1p42100: Add EUSB2 HS repeater support for USB Type-C
* 6e45016610 intel soc,southbridge: Add Kconfig to set TSBS in IFD during build
* f4271cad0a ifdtool: Add set top swap size PCH strap subcommand
* ab4b82fb3c util/lint: Add a license check exception for .gitkeep files
* 03524780ff soc/qualcomm/x1p42100: Support loading QTEE FW config files
* 50adb3f23c mb/google/bluey: Increase FW_MAIN_A/B slot size to 4.5MB
* bbdf2eab6a soc/mediatek: Rename DSI common files for improved readability
* 8a2c04e04d mb/starlabs/*/rpl: Re-enable GpioOverride
* 9ff9f2904b mb/google/bluey/var/quartz: Enable all spi flash drivers
* f6743fba29 mb/google/fatcat/var/moonstone: Enable Intel DPTF support
* fc736de10e ec/starlabs/merlin: Remove the EC_STARLABS_NEED_ITE_BIN option
* 3dee4cd0c0 soc/intel/pantherlake: Correct Touch Controller Speed Configuration
* 7376761bdf mb/nissa/var/pujjoquince: Modify fingerprint configuration
* 6ffbc9a929 soc/mediatek: Move mtk_dsi_reset() to mtk_dsi_common.c for reuse
* 668ea97075 commonlib/endian: Silence GCC -Warray-bounds false positives
* 4a3cc37cbd crossgcc: Upgrade binutils from version 2.44 to 2.45
* 35d4b3f2f4 arch/arm64: Support to load QTEE firmware in x1P42100
* e38056bef8 amdfwtool: Move ISH before PSP L2
* c1c83df3b5 mb/emulation/qemu-riscv: Enable ACPI by default
* 5daf497df4 arch/riscv: Add ACPI support for riscv
* 5c85793d26 mb/google/fatcat/var/lapis: Add cs42l43 and cs35l56 Soundwire links
* 14fc6c3469 crossgcc: Drop nds32le-elf toolchain from default builds
* fce489e9e5 drivers/intel/touch: Check SoC I2C speed function exists before calling
* 249883d5bf mb/starlabs/starlite_adl: Squash SB and non-SB board variants
* 80861a9f69 mb/starlabs/starlite_adl: Add CFR option for USB card reader
* 5c1a9fa809 mb/google/fatcat: Create ruby variant
* 43df7b14ae mb/var/uldrenite: Fix ISH UART port and VR configuration mismatch
* 1a0b7195f9 mb/google/nissa/var/glassway: Removed the flag of DB_1A for pmc_mux
* 9f0f373ff9 mainboard/amd/crater: Select the option to keep the AMD ACP active in S3
* f04c45acee mb/google/fatcat/var/lapis: enable CS35L56_FAMILY and CS42L43 driver options
* 78e7dcb152 drivers/soundwire/cs42l43: Add optional properties for controlling jack and accessory detect
* f1c973bbff drivers/soundwire/cs42l43: Support Cirrus Logic CS42L43 codec
* 35970abcdf mb/google/nissa/var/dirks: Add H58G56CK8BX146 to RAM ID table
* 402ac7cd81 crossgcc: Upgrade acpica from 20250404 to 20250807
* 3aa312e4c9 soc/mediatek/mt8189: Add DSI path support and update mutex
* 6b93516e02 soc/intel/baytrail/acpi: Add missing MMIO window below 4GB
* 321d8c5b21 soc/intel/braswell/acpi: Add missing MMIO window below 4GB
* 74d7a21382 nb/intel/haswell/acpi: Add missing MMIO window below 4GB
* 07f25bef86 mb/google/ocelot/var/ocelot: fix gpio settings
* 10b0697dc3 soc/intel/pantherlake: Update power limits and voltage regulator parameters
* 163e6a502c mb/starlabs/common: Deduplicate Pin Mix
* 7622a57771 mb/starlabs/common: Move the SMBIOS code to common directory
* e7dd184e5f Makefile.mk: Add support for mainboard vendor common code
* dd3d7dcdfa mb/purism/librem_skl: Add CFR option menu support
* 0d50fdf035 mb/purism/librem_l1um_v2: Add CFR option menu support
* e9a01dea32 mb/purism/librem_jsl: Add CFR option menu support
* 08efea5141 mb/purism/librem_cnl: Add CFR option menu support
* 1d02f139d3 mb/google/fatcat: Add wake configuration to cnvi_bluetooth
* cf97e1bc25 mb/intel/ptlrvp: Add power meter acpi changes
* 7e3883633a mb/google/brox/var/jubilant: Apply fw_config to enable/disable I2C1
* 114d24cd7a lib: Generalize BMP_LOGO help text
* e468e32dfb mb/google/*: Update Kconfig.name with actual device names
* 85d7a1c85f drivers/ipmi: add Block Transfer (BT) interface
* fe26234cf2 mb/google/trulo/var/uldrenite: Update DPTF parameters
* 660f71e704 mb/google/trulo/var/uldrenite: Set GPP_E16 to NC for non-WWAN SKU
* 3747b47df1 mb/lenovo/sklkbl_thinkpad: Add Lenovo Thinkpad T580 as a variant
* d23eaa356f util/lint: maintainers-syntax: Add a check to ensure paths exist
* 079c9c47aa soc/amd/cezanne: Add config option to keep ACP running in ACPI S3 state
* f665e189da mb/starlabs/{starbook/mtl,byte_adl}: Select USB4_PCIE_RESOURCES
* a7a49e5f74 mb/starlabs/starfighter: Correct reference for second TBT port
* f22bcc1d42 mb/starlabs/starbook/rpl: Disconnect unused GPIOs
* a8c70f7578 mb/starlabs/starbook/rpl: Reconfigure TBT GPIOs
* 83aa4417cb mb/starlabs/starbook/rpl: Tidy up GPIO config straps
* 7ad632cbc7 mb/starlabs/starbook/adl: Disconnect unused GPIOs
* d7627a39e8 mb/starlabs/starbook/adl: Tidy up GPIO config straps
* 711d49d4ec mb/starlabs/starbook/adl: Configure additional SSD GPIOs
* 90d87c5941 mb/starlabs/starbook/*: Remove comments for unused GPIOs
* f6b5e26fe7 soc/mediatek/mt8196: Add 24MB framebuffer region
* 815f3f7df2 mb/google/rauru: Increase RW firmware sections size to 1756KB
* 193420fe0b soc/mediatek/common: Add bootsplash support
* bdd4561536 soc/mediatek/mt8196: Add mtk_ddp_ovlsys_start for rendering framebuffer
* 0ff213d711 soc/mediatek/common: Conditionally set up framebuffer
* 5271ac7ac5 soc/qualcomm/x1p42100: Reserve DDR carveout region
* 19feafc018 drivers/intel/fsp2_0/ppi/mp_service_ppi: Support CPU_V2_EXTENDED_TOPOLOGY
* 16feb1bb28 mb/google/brya/var/nissa: Add missing device type to gfx device
* f4ecb69314 util/inteltool: Add Twin Lake UHD Graphics PCI IDs
* ed736a47d8 mb/starlabs/byte_adl: Configure additional SSD GPIOs
* 38525716d8 mb/starlabs/starbook/adl: Re-order the config strap GPIOs
* 2c465c0e21 mb/starlabs/starbook/adl: Re-order GPIOs to match other boards
* 115a6ce36a mb/starlabs/starbook/adl: Correct clock request number in comment
* 1b5aaaefd9 soc/intel/meteorlake: Fix IGD IRQ
* 06de11693f mb/starlabs/starfighter: Fix Thunderbolt disabling code
* 5e36d9ba04 mb/starlabs/starbook/mtl: Update the VBT from 256 to 261
* fba8c14c27 mb/google/brya: add cnvi BT recovery mechanism
* 1fb4a7409b soc/intel/pantherlake: Add VR power state current thresholds
* 59ede353c5 soc/intel/pantherlake: Add Thermal Design Current (TDC) configuration
* c54658d200 soc/intel/pantherlake: Add ICC Max configuration support
* 0d1545ffac soc/intel/pantherlake: Add hysteresis window UPDs support
* 8f24546fc4 vc/intel/fsp/fsp2_0/wildcatlake: Expose Thermal current thresholds and mode
* 04affc3354 mb/google/ocelot: Update gpio's for ALC721 sndw
* 3ac1a2b124 MAINTAINERS: Drop non-existant TPM files from VBOOT
* af8b15ae04 Revert "libpayload: Define UCHAR_MAX/CHAR_MIN/CHAR_MAX"
* 5e64ae2554 mb/starlabs/starbook/mtl: Enable PCH Energy
* 375847acfe soc/intel/meteorlake: Configure PmcPchLpmS0ixSubStateEnableMask
* db0faffdb8 mb/starlabs/*: Add comment about not configuring eSPI GPIOs
* 990ad929a0 mb/starlabs/starbook/tgl: Don't configure eSPI GPIOs
* 7ebcd6763f soc/qualcomm/x1p42100: Handle Type-C polarity for USB4/DP PHY init
* f1708cf21a drivers/intel/touch: Enhance Intel touch driver for new devices
* 55bf4ea07e cpu/x86/topology: Add tile and die ID CPU topology fields
* 0c97aed8ac mb/google/fatcat/var/lapis: Modify touchpad and touchpanel configuration
* 9e4a0a6026 mb/starlabs/starbook/mtl: Don't configure eSPI GPIOs
* 3e0457e087 security/vboot/Makefile.mk: Fix building vboot lib with OpenSIL
* 60ef877d93 mb/google/skywalker: Modify the RST pin naming
* d5a8cec748 soc/intel/meteorlake: Rely on FSP_DIMM_INFO
* e168a516e4 soc/intel/pantherlake: Rely on FSP_DIMM_INFO
* 23419df34c drivers/intel/fsp2_0: Implement API to retrieve DIMM info
* 1f328351e6 mb/starlabs/*: Select SPD_READ_BY_WORD
* 88439b4cd3 mb/starlabs/starbook/mtl: Set the VPU default to disabled
* 8ffa58723a soc/qualcomm/x1p42100: Add USB Type-C support
* 45cedbb992 soc/qualcomm/x1p42100: Add HS/SS PHY support for USB Type-C ports
* b18dfde22a soc/qualcomm/x1p42100: Add Clock support for USB Type-C ports
* c7e4ef822d mb/starlabs/{starbook,starfighter}: Remove DRIVER_TPM_SPI_CHIP
* 0c73e45493 ec/starlabs/merlin: Add disabled option for lid switch
* ac7bb7694d mb/starlabs/starbook/mtl: Configure eSPI GPIO Mux
* b37821ac25 mb/starlabs/*: Unify settings across device VBTs
* ac8765c88a mb/starlabs/*: Correct USB Type-C Port Configuration
* f7512c8647 mb/starlabs/starbook/{adl,rpl}: Remove USB OverCurrent Configuration
* bf67771656 mb/google/fatcat/var/lapis: Update gpio GPP_E07 configuration
* ff5daa0581 MAINTAINERS: Remove '/' from the beginning of paths
* 6bfa257eef MAINTAINERS: Correct the path of cbmem_id.h
* d7ae81132b MAINTAINERS: Correct asus/p8z77-series to asus/p8x7x-series
* ef8eb79636 MAINTAINERS: Rename util/ipqheader to util/qualcomm
* 0965bb9f68 MAINTAINERS: Remove non-existant mainboards
* f5d1505c6b mb/google/fatcat/var/moonstone: Add Elan touchpad support
* 24bfeb154e mb/google/fatcat/var/moonstone: Add focaltech touchscreen support
* 1580346fa7 mb/google/fatcat/var/moonstone: correct the Kconfig settting
* 150647a2fb ec/google/chromeec: Fix ACPI _CRS method generation for LPC memory range
* ffa262db59 Documentation/FIT: reference archived copy of Intel TXT lab handout
* f47e6c3905 MAINTAINERS: Fix typo "copperlake_sp" to "cooperlake_sp"
* 1af0497c12 mb/google/dedede: Fix MAINBOARD_FAMILY conditional
* b4b6c3aa55 mb/google/brya/var/{marasov,mithrax,omnigul}: Add SOF chip driver entries
* 738fd2efc9 util/chromeos/extract_blobs: Add support for command line params
* e59c5abd13 ec/google/chromeec: Add EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
* 341b108a71 mb/starlabs/starfighter: Add missing GPP_A5 definition
* 414f1a61dd vc/intel/fsp/fsp2_0/pantherlake: Expose Thermal current thresholds and mode
* 2e92833172 soc/qualcomm/common/usb/qmpv4_usb_phy: Fix delay value in comment to 10 ms
* b48532c694 soc/mediatek: Refactor MMU configuration for DMA region
* 28a8eaa57b soc/mediatek/mt8192: Clean up memlayout.ld
* bca876849a soc/mediatek/common: Add enable parameter for configure_backlight
* 46ce812c1b mb/google/skywalker: Create variant Grogu
* 98a5445328 MAINTAINERS: Correct paths for Dell Latitude mainboards
* 984ee53de8 mb/asus/p8x7x-series: Introduce CFR setup menu
* 830ec89bca mb/google/bluey: Update mainboard part number for QuenbiH
* c2fcf69e41 arch/x86: Use boolean for flag_is_changeable_p()
* 2a791fcd66 mb/imb-1222/hda: Use AZALIA_PIN_CFG_NC() for disabled SPDIF_OUT2 pin
* 217a7962d0 ec/google/chromeec: Update EC headers
* 59cbb073c2 util/chromeos/crosfirmware.sh: Fix download of ninja (baytrail) recovery
* fba92daed3 soc/qualcomm/x1p42100: Clean up DDR and IMEM memory layout
* 5609174786 mb/google/rauru: Create variant Sapphire
* 386feb720e soc/mediatek/mt8196: Add DVFS support for the second SoC SKU
* 4b93b36170 mb/purism: add missing terminators to azalia codec tables
* a927d124be mb/asus: Replace verb tables with reworked implementation
* 9c0c925fe6 mb/siemens/mc_rpl1: Send POST codes to NC FPGA via PCI
* 10361583b3 mb/siemens/mc_rpl: Add code to wait for legacy devices before PCI scan
* d9979ba6a3 mb/siemens/mc_rpl: Sort includes alphabetically
* d9b609b139 nb/intel/haswell: Use boolean for cbmem_was_initted
* 1f2408f573 console: Fix flushing for slow consoles
* 6a016a784b Documentation: Finalize 25.09 release notes
* a0c5669c1b mb/asrock/imb-1222: Use macros for HDA verb table
* c94ca87d40 mb/google/fatcat/var/kinmen: Enable Intel DPTF support
* fe5f8494f6 docs/releases: Remove outdated "Upcoming release" in titles
* aef86a7e89 mb/google/ocelot/var/ocelot: disable HDA GPIOs by default
* 21f6ccf3a4 soc/intel/pantherlake: Use CPU ID mask for all stepping
* 8bc41fc937 mb/google/trulo/var/pujjocento: Update DTT settings for thermal control
* d5f1ecedf7 {device/azalia_codec,mainboard}: Use node ID enums for Realtek ALC887
* 02059c2250 mb/google/trulo/var/pujjoquince: Disable ISH gpio setting by fw_config
* 58459b8210 mb/var/uldrenite,orisa: Include the variant GPIO header
* 88ad238eca mb/google/skywalker: Fix incorrect GPIO_USB3_HUB_RST_L pull-down
* b8a8800152 mb/google/fatcat/var/lapis: Configure gpio of fingerprint sensor
* 4431848ee6 acpi: Move most of HEST ACPI table to common code
* ce1ced7f6a mb/intel/ptlrvp: Fix WIFI driver device settings under root port 4
* 691a23a272 mb/google/fatcat: Fix WIFI driver device settings under root port 4
* 16bf80b9b1 tests/imd: Fix invalid NULL comparison on uintptr_t
* 6d816b3b43 mb/asus/h610i-plus-d4: Add missing AZALIA_USE_LEGACY_VERB_TABLE
* 6f042c6ae4 lib: coreboot_tables: Fix grammar of *These information* in comment
* bcc7fce590 mb/topton/adl: Add TWL variant (X2E_N150)
* f634121fa4 mb/purism: Replace verb tables with reworked implementation
* 20d4042458 mb/asrock: Replace verb tables with reworked implementation
* 2b7dbf80c9 mb/apple: Replace verb tables with reworked implementation
* 970249694f mb/amd: Replace verb tables with reworked implementation
* 94beaa7ab3 mb/acer: Replace verb tables with reworked implementation
* f3db3a19d5 mb/51nb: Replace verb tables with reworked implementation
* bc92d9a666 nb/intel/haswell/minihd.c: Add reworked verb table implementation
* 69781b9806 soc/intel/broadwell/minihd.c: Add reworked verb table implementation
* 31fc5b06a6 device: Introduce reworked azalia verb table
* 50a59d4464 device: Add Kconfig to prepare for reworked verb table implementation
* a3e2073591 lib/vga_gfx: Add API to render text on a bitmap buffer
* ec2875e38f mb/google/ocelot/var/ojal: Enable FPS and update FW config
* beb0951c1c mb/google/ocelot/var/ojal: Update touchpad config
* bd933b641e mb/google/ocelot/var/ojal: Add overridetree
* 82a9e601bd mb/google/ocelot/var/ojal: Add initial GPIOs config
* 622c504a71 mb/emulation/qemu-riscv: Select DRIVERS_EMULATION_QEMU_FW_CFG
* ba3f529681 drivers/emulation/qemu: Adjust fw_cfg driver for Arm and RISCV
* c1e0384367 arch/riscv/include: Cast 'id' to int in OTHER_HLS()
* 67a3fb6abe mb/asus: Add PRIME H610i-PLUS D4 (Alderlake/LGA1700)
* 4f13f72dbc libpayload: Define UCHAR_MAX/CHAR_MIN/CHAR_MAX
* 7f8c442a09 soc/intel/meteorlake: Correct function naming
* 6d265ca31d device/pci_device: Fix typo in comments
* d4b6b55977 payloads/Kconfig: default to Skiboot payload on PPC64
* cb899b0c4d mb/google/brox/var/caboc: Update HDA verb table
* 15b903e1fd soc/intel/pantherlake: Add DDR5 memory type debug message
* a5252bd5b9 drivers/soundwire/cs35l56: Support Cirrus Logic CS35L56 Smart Amplifier Family
* 7d44128b2f mb/asus/p8z77-m_pro: Enable serial port A instead
* 894c8069fc superio/nuvoton: Add NCT5535D
* 69b0541375 sio/nuvoton/nct6779d: Add power loss resume support
* f61ffb68c9 soc/intel/pantherlake: Remove unused TxDqDqs retraining parameter
* 3a84c93b5b soc/intel/pantherlake: Correct function naming and code style
* 3b34079b19 mb/google/trulo/var/kaladin: Enable External bypass config2 settings
* 61488ffd57 mb/google/skywalker: Add CS35L51 support for beep sound for Padme
* 4a7d779ed0 soc/mediatek/mt8196: Set RTC EOSC calibration to 8 seconds
* 07df08836e Docs/releases: Update release notes for 25.09 release
* 8f52c0774e docs/security/vboot: Update supported board list
* 1f08b36f84 Documentation: Add coreboot release 25.12 template
* 02980f0ea6 soc/amd/common/block/psp: Add comments
* a17a41559a soc/amd/common/block/psp: Add BIOS SPI flash semaphore
* 038262155e soc/amd/common/block/psp/psp_smi_flash: Fix flash busy check
* 67e3579d61 sb/intel/lynxpoint: Enable PCIe Relaxed Order
* 865649edc0 util/docker/jenkins-node: Use the correct branch for encapsulate
* 6af7d299b2 mb/google/skywalker: Add MIPI panel support with TM_TL121BVMS07_00C
* 4fc5f7a843 mb/google/fatcat/var/lapis: Modify the gpio order of mem_id
* 2764a508ad mb/google/fatcat/var/lapis: Add 4 DDR modules to RAM id table
* 886bd1d186 spd/lp5: Add Samsung K3KLALA0EM-MGCU memory part
* 0a6f3e3868 mb/google/brox/var/caboc: Add PDC FW hash to hint romstage init
* cbd1529126 mb/google/brox: Update Auxiliary Firmware Version check
* 0d4c0ee7fc ec/google/chromeec: Add API for AP shutdown command
* bbd72abae5 ec/google/chromeec: Update EC headers
* 21ca3c5f3d mb/intel/ptlrvp: Update CKD/QCK mapping parameters
* 3d7b898ff4 mb/google/ocelot/var/ocelot: Disable ALC721 clock stop support
* c822148f2b mb/google/fatcat/var/lapis: Modify dq/dqs setting
* 78fb910fe2 mb/google/fatcat/var/lapis: Update the configuration of fw_config
* eb3497fae4 mb/google/fatcat/var/lapis: Update tpm i2c configuration
* 3a33217349 mb/google/fatcat/var/lapis: Update thermal strategy
* 36d2dc7cb9 mb/google/ocelot: Update wake event mapping for gspi0
* 59bd0e3206 mb/google/ocelot/var/ocelot: Update USB and TCSS port configuration
* c4627e0dda mb/google/ocelot: Remove FP_PRESENT probe from ISH device configuration
* 8e9ec16f45 mb/google/trulo/var/pujjolo: Add tablet mode fw config for ish fw
* e3a2d1cecf soc/qualcomm/qclib: Improve logging on invalid MRC cache data
* 289c01e6fb mb/google/ocelot: implement variant_memory_sku()
* fbb68982c9 mainboard/google/ocelot: Update PCIe root port for SD card interface
* c98155cbcd soc/intel/pantherlake: Generate TME keys only if TME is enabled
* d8ed977358 mb/google/skywalker: Remove space before tabs in gpio.h
* 1e7908fa9f mb/google/skywalker: Set up all output GPIOs
* 14e6c62c10 mb/google/skywalker: Define all GPIO pins
* 2859a5cba5 mb/{google,intel}/{fatcat,ptlrvp}: Prevent access to disconnected camera
* ffae0f7d73 security/vboot: Extend CROS_EC_HASH_TIMEOUT_MS
* d2345e0c60 mb/google/fatcat: Set `SkipExtGfxScan` FSP-M UPD
* 8953c772cf lib: Fix bad whitespace in add_bmp_logo_file_to_cbfs_call
* ef0c650edf soc/intel/cmn/blk/fast_spi: Cancel DMA transfer before locking
* b3ad2aa3e7 mb/google/ocelot: GPIO config for headphone jack detection
* 508c399bc1 mb/goog/ocelot/var/ocelot: add H58G66CK8BX147 memory option
* d8a3f2aedd mb/goog/ocelot/var/ocelot: add H58GE6AK8BX104 memory option
* f4110cebf6 spd/lp5: Add SPD for H58GE6AK8BX104
* 7acc99c3d2 acpi/acpi_pm: Fix compilation without SMBIOS
* c77d3d67cf mb/google/skywalker: Report panel ID and SKU ID for padme
* 6185983028 soc/intel/pantherlake: Standardize macros for core count and SKUs
* 9a8402adf9 mb/google/trulo/var/kaladin: Update HDA verb table
* 9af9e1d1f4 mb/google/trulo/var/kaladin: Add eMMC DLL settings
* 3b4c446fbb mb/google/bluey: Configure QUP0 SE1 as I2C
* ddf5987c1e drivers/mipi: Add support for TM_TL121BVMS07_00C panel
* 0fec287327 mb/google/nissa/var/dirks: Drive GPIO GPP_D2 high to fix noise issue
* 5a9ca2b040 mb/starlabs/starbook/mtl: Set SPD size to 512
* 79119456a2 soc/amd/common/block/iommu: Add missing newline to debug print
* 81bb2663b7 soc/qualcomm/x1p42100: Select HAVE_CBFS_FILE_OPTION_BACKEND
* bf83dd9927 soc/qualcomm/common/qclib: Introduce runtime debug log level control
* cf3af46e50 mb/google/skywalker: Create variant Padme
* 2b1809e026 mb/google/fatcat: Increase Fast VMode I_TRIP threshold to 63A
* 2a7a0e86cd mb/google/fatcat: Configure Acoustic noise mitigation
* 6c06602c75 mb/google/brya/var/uldrenite: Add fw_config probe for touchpad
* a3b73464b5 soc/qualcomm/x1p42100/usb: Fix code comments and debug messages
* e924021e69 mb/google/trulo/var/kaladin: Add GTH1563 and GTH7503
* d1967d927a spd/lp5: Add SPD for MT62F1G32D2DS-031 WT:C and MT62F2G32D4DS-031 WT:C
* 2e10ddb1ee mb/starlabs/starbook/mtl: Make TCSS notify the IGD of changes
* 47fb46e0e4 vc/intel/fsp/mtl: Update the headers to 5124_47 (13.0.228.64)
* bb760bc9f3 Kconfig: Introduce HAVE_CBFS_FILE_OPTION_BACKEND
* f1b83c8759 mb/google/rex/var/kanix: Add K3KL8L80EM-MGCU to RAM ID table
* bcb3263078 mb/goog/ocelot/var/ocelot: add H58G66BK8BX067 memory option
* 751afeb060 mb/google/brox/var/caboc: Update HDA verb table
* 56700713de mb/google/trulo/var/kaladin: Disable eMMC GPIOs via firmware config
* 93c147c5e6 commonlib/device_tree: Add dt_add_iommu_addr_prop function
* d3d2f0f1c8 mb/google/fatcat/var/moonstone: Add to support ALC1320 Smart Amp
* 1da045f6a5 mb/google/skywalker: Add API support for regulator VCN18
* fe70426dd7 soc/mediatek/common: Add support for regulator VCN18
* f4a123f055 tests: Allow specifying using system Cmocka or building from source
* e7d598ba2c Reland "tests: Allow specifying vboot source directory"
* a348ef46db mb/google/trulo/var/pujjolo: Change setting for lite ISH fw
* 16db59ccef mb/google/rex/var/karis: Add K3KL8L80EM-MGCU to RAM ID table
* 3639648f81 mb/google/fatcat/var/felino: Set GPP_A15 and GPP_B23 as not used
* 8585591596 mb/google/fatcat/var/lapis: Set GPP_A15 as not used
* b9af91dfe1 mb/starlabs/starlite_adl: Drop HDMI entries from verb table
* 461c6a7d31 mb/starlabs/starfighter/rpl: Drop HDMI entries from verb table
* fc3a647579 mb/starlabs/starbook/rpl: Drop HDMI entries from verb table
* a88d9e1033 mb/starlabs/starbook/mtl: Drop HDMI entries from verb table
* 90f94287fd mb/starlabs/starbook/adl_n: Drop HDMI entries from verb table
* 684530ebdc mb/starlabs/starbook/adl: Drop HDMI entries from verb table
* 258da6b1ef mb/goog/ocelot/var/ocelot: add H58G66BK7BX067 memory option
* 883103c77f mb/google/ocelot: Disable memory training progress bar
* f3a49c8b3d mb/google/ocelot/var/ocelot: Disable audio for invalid Audio FW_CONFIG
* be3148575e mainboard/google/ocelot: Set OEM footer logo bottom margin
* 092fca3210 mb/google/fatcat/var/kinmen: Add support ALC1320 Smart Amp
* 4ba1b615db mb/starlabs/starlite_adl: Use macros for HDA verb table
* ca8d6a7512 mb/starlabs/starfighter/rpl: Use macros for HDA verb table
* c30163dace mb/starlabs/starbook/tgl: Use macros for HDA verb table
* 15111ebb21 mb/starlabs/starbook/rpl: Use macros for HDA verb table
* 6d6a280ab2 mb/starlabs/starbook/mtl: Use macros for HDA verb table
* 543f6c2a52 mb/starlabs/starbook/kbl: Use macros for HDA verb table
* 6d7c8f5477 mb/starlabs/starbook/cml: Use macros for HDA verb table
* 515f566840 mb/starlabs/starbook/adl_n: Use macros for HDA verb table
* 4b61d4de5f mb/starlabs/starbook/adl: Use macros for HDA verb table
* 8bc0eddf15 soc/intel/pantherlake: Add support for a new Panther Lake B0 SKU
* 2b84d26f55 payloads/edk2: configure capsule updates
* f3211e9639 soc/intel/pantherlake: Add support for Acoustic Noise Mitigation UPDs
* 2c03fd06a9 mb/google/trulo/var/kaladin: Disable ISH via firmware config
* f8574f7145 soc/intel/ptl: Add Wildcat Lake SKU power map
* b1fe32dd9e mb/{intel,google}/{fatcat,ptlrvp}: Update GPP_A15 GPIO configuration
* 6074ca18d3 mb/google/ocelot: Create matsu variant
* 76e0f64035 mb/google/brya: Update GPIO_PCH_WP for trulo variants
* b69e66721d mb/google/brya: Update GPIO_PCH_WP configuration in trulo baseboard
* 17c623277b mb/google/trulo/var/pujjolo: Change stylus settings
* 7f74155aa4 mb/google/trulo/var/uldrenite: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
* f373faa9c8 mb/google/trulo/var/uldrenite: Add fw_config probe for storage
* a262cdbc27 mb/intel/ptlrvp: Add wake configuration to cnvi_bluetooth
* 1c0186f280 soc/intel/common/block/cnvi: Add CNVi chip configuration support
* bdbe8b9b6f util/kconfig: Fix xconfig
* 241b940ac7 mb/google/nissa/var/rull: add RAM ID H58G56CK8BX146
* 599d660c4b mb/google/fatcat: Enable support for Realtek EC
* 89a3ae3d80 mb/google/trulo/var/pujjolo: Update GPP_D15 setting
* b849c9daa1 3rdparty/qc_blobs: Update submodule to upstream main
* 8159b2e06c device/azalia_codec: Add header with enums for Realtek node IDs
* 18ae0c48e1 mb/google/fatcat/var/moonstone: Support new schematic changes
* c1f76dd87e mb/google/brya/var/dochi: Add H58G56CK8BX146 to RAM ID table
* 164b4a1d90 mb/google/nissa/var/craask: Add parade touchscreen support
* 492826771e mb/google/bluey: Enable USB support
* 96eb6a3ac1 soc/qualcomm/x1p42100: Add USB Type-A Host support
* 2908a955e5 mb/google/rex/var/kanix: Add H58G56CK8BX146 to RAM ID table
* 7fc414c886 mb/google/trulo/var/kaladin: Enable EC keyboard backlight
* 859cc31e3a mb/google/brox/jubilant: Generate RAM IDs
* a6c15129a7 mb/google/fatcat/var/moonstone: Generate SPD ID for memory module
* 1028f3e846 soc/intel/pantherlake: Add Bluetooth to PME wake source mapping
* 3f926bc110 commonlib/bsd: Add Bluetooth wake source in ELOG event data
* 84ec1493a3 drivers/wifi/generic: Fix typo in header guard comment
* 2e2490256f soc/qualcomm/x1p42100: Add USB clock support for X1P42100
* 159afbc5d5 lib/lzmadecode: Increase decoding speed by 30%
* 0b8ad35ac1 mb/starlabs/byte_adl: Adjust the VBT
* d3cea61907 mb/starlabs/starlite_adl: Adjust the VBT
* 3507992d1d mb/starlabs/starbook/adl_n: Adjust the VBT
* 05cd5a7ab9 mb/google/nissa/var/telith: Generate RAM IDs for telith
* a0bdf3961c soc/qualcomm/common: Add clock reset function support
* cf11722e68 soc/mediatek/mt8189: Enable tracker debug hardware
* 382a7caff3 soc/mediatek/mt8196: Refactor tracker driver to support new platform
* 97f9ebb5c2 mb/google/ocelot: Create ojal variant
* ef1d48ee1d util/lint: Don't check for Kconfig.name in common directory
* 5cb36eb16c util/lint: Don't check for board_info.txt in common directory
* 46b03e682c util/amdfwtool: Handle address mode properly for Turin
* 97cf4a1919 util/amdfwtool/amdfwread: fix offset decision for PSP/BIOS directory lookup
* 73dd7bb046 util/amdfwtool/amdfwread: add initial parsing for EFW structure
* d4da533473 smbios.h: Update smbios_memory_type
* 183589dcbd smbios.h: Update smbios_memory_form_factor
* 58726e58e4 mb/starlabs/starbook/mtl: Adjust the VBT to fix hot plug
* 80df8c336f mb/intel/ptlrvp: Update Kconfig for ptlrvp_chromeec4s and ptlrvp4es support
* ed59c1de34 soc/qualcomm/x1p42100: Update TF-A memory reservation
* 56dbafcff4 soc/intel/pantherlake: Remove UFS support
* 5b46caef93 mainboard/intel/ptlrvp: Remove UFS support
* 621633af9b mainboard/google/fatcat: Remove UFS support
* 5e2f5050ba mb/starlabs/starbook/kbl: Update HDA verb table
* 4626c053dd mb/starlabs/starbook/adl_n: Update HDA verb table
* 6f11c31354 mb/starlabs/starbook/mtl: Update HDA verb table
* b748a5e10b mb/starlabs/{starbook,starfighter}/rpl: Disable GPIO override
* 29ca9c8bfa mb/google/bluey: Disable charging during normal boot
* e82338b0a2 mb/google/bluey: Add boot mode to coreboot tables
* 893a2b008a libpayload: Add coreboot boot mode table
* a45c8441af lib: Add boot mode information to coreboot tables
* c73f30e74b mb/google/nissa/var/riven: Add H58G56CK8BX146 to RAM ID table
* 8c717df03a soc/intel/ptl: Update Wildcat Lake PCIe root port numbering
* afaef0b904 mainboard/google/ocelot: Update GPIO configuration for SLP_S0_GATE
* 97dbfd3098 cpu/intel/car/non-evict: Improve CAR setup
* cd48dc7d69 mb/google/rex/var/karis: Add H58G66CK8BX147 to RAM ID table
* ffbf40f6c0 ec/google/chromeec: Update EC headers
* 517185eca2 mb/google/bluey: Configure touchpad power GPIO
* baf159a1c8 mb/google/bluey: Configure GSC and EC for Quartz
* f8685bb2ee soc/mediatek/mt8189: Enable lastbus debug hardware
* 6e61ea65a8 mb/google/bluey: Add disable slow charging support
* 45d1f9cce4 mb/google/bluey: Move charging functions to dedicated file
* 9fb306f53c soc/qualcomm/x1p42100: Add SPMI driver to ramstage
* ac5bb861d8 mb/google/brya/var/uldrenite: Update HDA verb table
* f2d3051631 ec/lenovo/h8: Turn on PWR LED
* d8de1c4974 ec/lenovo/h8: Disable POST codes
* d5a92542aa mb/google/fatcat/var/fatcat: Disable ALC721 & ALC722 clock stop support
* 3b2962929b lib/timestamp: Init TSC frequency early on x86
* b0a63052b7 sb/intel/bd82x6x: Fix CPU replaced check
* 9ecf04c2bc mb/google/nissa/var/quandiso: Generate RAM ID for MT62F512M32D1DS-023 WT:E
* 16318a32ce spd/lp5x: Generate initial SPD for MT62F512M32D1DS-023 WT:E
* 283c25beec mb/google/trulo/var/kaladin: Select Strauss keyboard to show G icon
* 2709ae443b cpu/x86/entry16.S: Move reset vector to this file
* 53810448fc cpu/x86/reset16.S: Remove handcoded reset vector
* a1b7f5e1b8 mb/siemens/mc_rpl: Disable EIST to improve deterministic behavior
* e6f8900c2d mb/siemens/mc_rpl: Disable S0ix power states
* c71071397f soc/intel/common/fast_spi: Add static bus scanning
* e73b4579c6 mb/siemens/mc_rpl: Disable DPTF
* 77061d8427 mb/google/bluey: Add Quartz board (Qualcomm Hamoa)
* ee1446a791 mainboard/emulation/qemu-q35: Do not compile memmap into SMM
* a7b6590aca  mb/google/dedede/var/dexi: Add and use VBT
* 70ce81c86f mb/google/dedede/var/dita: Add and use VBT
* 87f5d4c54a tree: use boolean for PcieRpLtrEnable[]
* 725ab7b066 soc/mediatek/common: Increase WAIT_AUX_READY_TIME_MS
* f02e755364 config/builder/mitac: Hook up public FSP repo and microcode
* fc62ffab48 soc/amd/common/fsp/dmi: Skip parsing when memory type UNKNOWN
* c3071b7150 soc/amd/cezanne/fsp_m_params: add UPD pointer parameter to mb callback
* eb9a673a8e soc/amd/cezanne: Add a Kconfig option for SERIRQ_CONTINUOUS_MODE
* c590e8e75c mb/brya/var/uldrenite: Increase Touch IC enable delay time
* 9996fc58fd mb/siemens/mc_rpl: Disable C1E state via MSR_POWER_CTL
* c58c988b8e mb/siemens/mc_rpl: Remove unused code and power limit functionality
* 8e5e87a1cf mb/siemens/mc_rpl1: Configure CPU power limits to 28W TDP
* 4853f16a59 mb/google/fatcat/var/kinmen: Support new schematic changes
* 9d67120078 mb/google/moonstone: Create moonstone variant
* 00d954977c util/smmstoretool: Support other block sizes
* 4fd3cb35c2 util/cbmem: Change abort() to exit(1) in die()
* 62b6d1e336 mb/siemens/mc_rpl: Enable master bit in PCI config space if allowed
* a8bce33b82 mb/siemens/mc_rpl: Disable Intel Turbo Boost
* 1a9008b261 device/azalia: Use clrsetbits32() and friends
* cbf8527345 device/azalia: Amend the mistake of codec_is_operative()
* 0a328282ec device/azalia: Add enums for HDA verb and parameter IDs
* c15006eb0c soc/intel/alderlake: Add 28W TDP support for RPL-P ID 8 (0xa716)
* d7a996cf44 mb/siemens/mc_rpl1: Enable 4 P-Cores, disable E-Cores
* 2f9273f1f4 mb/siemens/mc_rpl: Select FSP_TYPE_IOT
* 1b14664311 mb/siemens/mc_rpl: Remove unused DPTF settings
* 66a3f2a1b1 mb/siemens/mc_rpl: Disable SaGv
* 993a9c9e14 mb/siemens/mc_rpl1: Configure SATA Ports
* e03f50bf5f mb/siemens/mc_rpl: Enable Siemens NC_FPGA driver
* 699c28c01d sb/intel/bd82x6x: Fix replay issues
* c2110e3161 tree: Use true, false for PcieRpClkReqSupport
* ebab858d92 soc/intel/pantherlake: Enable memory bandwidth compression for IGD
* ad10d4a977 soc/intel/cmn/blk/graphics: Reserve memory compression region
* 8a52418e9a commonlib/device_tree: Fix memory leak in fdt_unflatten()
* 7896f4950c mb/google/skywalker: Turn off UFS power for eMMC SKUs
* 22fe08c04b soc/mediatek/mt8189: Implement UFS power-off API for non-UFS SKUs
* 5f0225a7b5 drivers/intel/fsp2_0: Refactor for earlier graphics memory WC MTRR
* 1c571446ec soc/intel/common/block/systemagent: Increase MTRR region size to 32 MiB
* 67afbf5f96 soc/intel/pantherlake: Add TDP mappings for Panther Lake-U SKUs
* ec69479bdb mb/google/ocelot: Drop redundant SNDW GPIO mapping
* 5f168e9441 mb/google/ocelot/var/ocelot: Conditionally init ALC256 HDA using fw_config
* 152b584167 mb/goog/ocelot/var/ocelot: Add AUDIO_MAX98360_ALC5682I_I2S
* 8f2633cd60 soc/power9/rom_media.c: find CBFS in PNOR
* 44ec090551 ppc64: Kconfig switch for bootblock in SEEPROM, zero HRMOR
* 921027e09b src/lib/cbmem_common: Delete a space(' ') in the source code
* acb86babdf mb/protectli/vault_kbl/mainboard.c: bring back the beep
* 76d45a8219 soc/amd/genoa_poc/root_complex.c: Explain the order of IOHCs
* 8dcfa915f2 soc/amd/common/block/psp: Probe SPI flash early
* 00217275b2 soc/amd/common/block: Don't clobber SPI registers
* c13eadeadb soc/amd/common/block/psp/psp_smi_flash: Fix busy check
* fbcf031181 mb/qemu-riscv: set PCI_IOBASE
* bf0ee592f5 soc/intel/alderlake: Make SATA speed limit configurable
* 482a2d6548 nb/intel/sandybridge/northbridge.c: Disable non-active PEG devices
* 7e73d4ef30 Documentation: mb/erying/tgl: Update documentation
* 73cba1fdea mb/erying/tgl: Introduce CFR
* 23cf7c64f9 mb/erying/tgl: Use booleans in devicetree
* 261b6b4fd1 soc/intel/skylake: Allow generating USB ACPI code
* 23e92a5ac0 mb/erying/tgl: Map remaining USB ports
* 762a535551 mb/erying/tgl: Clean up the GPIO table
* 179b8444c3 soc/intel/xeon-sp/gnr: Hook up public FSP bin and headers
* 42ba7a9e48 soc/intel/xeon_sp/gnr: Add Kconfig symbols for SKUs GNR-AP and GNR-SP
* c732f406c7 mb/google/ocelot: ec.h: Disable sync IRQ, sync IRQ wake capable for OCELOT4ES
* 73961bf680 mb/google/ocelot: Use same mainboard part number for all ocelot variants
* 691d5e84cd mainboard/google/oceot: Drop redundant logo_valignment selection
* b67d88aecb mb/google/bluey: Enable PMIC based slow charging in romstage
* dcb7c317c2 mb/siemens/mc_rpl1: Enable Intel I210 MACPHY driver
* 2b26ea0eda mb/siemens/mc_rpl1: Configure SPI and implement TPM support
* 2bcd7f1522 mb/siemens/mc_rpl1: Adjust UART settings and enable LPSS UART
* 524fd18bd6 mb/siemens/mc_rpl1: Create variant specific Kconfig file
* c7cd4e3305 mb/siemens/mc_rpl: Move SOC selection to baseboard
* 6427e51c4f mb/siemens/mc_rpl1: Adjust USB port settings in devicetree
* 71c4619045 mb/siemens/mc_rpl: Remove unused devices from devicetree and Kconfig
* 296f5968d3 mb/siemens/mc_rpl1: Adjust I2C bus enablement in devicetree
* a1dd6bfc22 mb/siemens/mc_rpl1: Adjust PCIe settings in devicetree
* f94469c2a9 mb/google/nissa/var/pujjolo/pujjoquince: Add wifi sar table
* 6781f458ee mb/google/trulo/var/pujjolo: Enable fivr settings
* 17a88540fd soc/qualcomm/x1p42100: Use SPMI driver
* c1128ae649 soc/qualcomm/cmn: Add SPMI driver
* 0eebd5596b mb/google/fatcat: Create lapis variant
* 4931b978d9 soc/mediatek: Increase CBFS cache to 8MB in memlayout.ld
* 234eb53ed9 nb/intel/sandybridge/raminit: Speed up reading SPD EEPROMs
* 7d57333529 ec/starlabs/merlin: Add a "off" mode for the power LED
* 36624072a6 mb/google/trulo/var/pujjolo: Update wlan rtd3 settings
* 42a5c189b2 mb/lenovo/X220: Add CFR support
* 8509798006 sb/intel/common/smbus: Use proper delay instruction
* 5f7b5fcb19 mb/starlabs/byte: Lower the PL4 value to 65W
* 4a6a0de029 3rdparty/fsp: Update to upstream master
* de98da43fa 3rdparty/intel-microcode: Update to upstream main
* bdee19ba87 soc/qualcomm/x1p42100: Add ASCII memory map diagram to memlayout.ld
* 51a8e238b0 lib: Correct logo bottom margin handling for all panel orientations
* 9999a4aebb mb/google/nissa/var/pujjocento: Change touchscreen properties
* 8d2df573a8 soc/qualcomm/x1p42100/qclib: Support to pack and load CPR binary in CBFS
* a484a6529c soc/qualcomm/common/qclib: Support to declare cpr_settings region
* dc04ee827b mb/google/fatcat/var/kinmen: Generate SPD ID for memory modules
* e7cdf035fb mb/google/brox/var/caboc: Enable RTD3 for SSD to resolve S0ix issue
* cec34128d0 soc/qualcomm/x1p42100: Support to load CPUCP firmware in x1p42100
* a2b6e20509 soc/mediatek/common: Increase per-channel SPMI max byte count to 2
* 6ba2df9be5 soc/mediatek/common: Use polling to reduce eDP HPD wait time
* ee347d8812 soc/qualcomm/common/qclib: Support to load AOP config and meta in CBFS
* 3f4c84513d soc/qualcomm/x1p42100/qclib: Support to pack AOP config and meta in CBFS
* 5de5b519ca mb/prodrive/atlas/vpd.c: Replace union {0} initializers with {} for C23 compliance
* 48207895af lint: Warn about using change IDs for merged changes
* 6acf07022d Doc/contributing: Add clarification on how to reference other commits
* 40d0ec0fa4 Revert "soc/mediatek/common: Remove 200 ms delay from eDP init path"
* 244a34b3d0 cpu/x86/mp_init: Refactor ICR wait logic
* eee5be070a cpu/intel: Use mtrr_use_temp_range()
* e37a53a2fc arch/x86/memcpy: Fix undefined behaviour
* 7c0f7e0b3f vc/intel/fsp: Update PTL FSP headers to FSP 3272_04
* d315f26217 payload/seabios: Update from 1.16.3 to 1.17.0
* c61a762a47 mb/google/bluey: Add QuenbiH board
* 9edf49b008 mb/google/bluey: Add BlueyH board
* 9868417d5e mb/google/bluey: Refactor Kconfig for Hamoa SoC
* 74d91d0b76 mb/google/nissa/var/glassway: Support Memory MICRON MT62F512M32D2DR-031WT:B
* 7eb832b1dc mb/google/skywalker: Configure GPIO GPIO_AP_EDP_BKLTEN as output
* cdd42ccde8 soc/qualcomm/x1p42100: Use 4K for memory region alignment
* 2146ecc8e1 mb/google/brox/caboc: Enable PEG60 with PEG62
* 6925fd69f8 soc/qualcomm: Move common region macros to `soc/memlayout.h`
* d220b65b8f soc/qualcomm/qcs405: Add common include path
* b25939786d soc/qualcomm/x1p42100: Refactor CBMEM top address to use linker symbols
* d6ec4f108d soc/qualcomm/x1p42100: Mark additional reserved memory ranges
* 1b760645b9 soc/qc/x1p42100: Dynamically configure DRAM resources in ramstage
* 276432faf7 soc/qualcomm/common: Add MMU configuration for fragmented DRAM regions
* b4347f11d9 include: Make DRAM an explicit region
* 11c8d423d1 soc/qc/common: Remove ddr_base from qc_mmu_dram_config_post_dram_init
* 73de3f95ac mb/google/bluey: Support hardware watchdog logging
* 25e0a4642c mb/google/brox/var/caboc: Update LAN LED behavior
* e5ff7cb186 mb/google/ocelot/var/ocelot: Update DDI port Configuration
* 8df079c609 mb/lattepanda/mu: Enable CRB TPM (Intel fTPM)
* 6e9c0a26e3 device/device_util: Fix format specifier for DEVICE_PATH_GICC_V3
* 4a82f37525 mb/google/nissa/var/quandiso: Generate new RAM ID
* 17a7c351b8 mb/google/brya/var/kaladin/hda_verb.c: Correct number of entries to 21
* b65b98ace6 mb/goog/ocelot/var/ocelot: switch to H58G56BK8BX068 memory part
* 8097809c8a libpayload: Fix strsep() edge cases
* e38a216368 soc/intel/pantherlake: Rearm and clear only for valid crashlog in PMC
* 510686add4 soc/intel/pantherlake: Rearm crashlog using watcher
* 609eb4c5f1 mb/google/ocelot/var/ocelot:  Remove unused I2C controllers
* df7bf9404d soc/mediatek/common: Remove 200 ms delay from eDP init path
* a70bf82036 soc/mediatek/common: Measure eDP initialization time
* 6bb1ba95e1 soc/mediatek/common/dp: Move mtk_edp_init to dptx_common.c
* e49e8c6355 soc/qc/x1p42100: Add memory layouts for CPUCP and TZ regions
* c418a3b843 mb/google/brox/var/caboc: Update WWAN gpio
* 77b52ed3cc mb/google/brox/var/caboc: HDA: Correct number of jacks to 35
* e31fbc493d soc/qualcomm/cmn/qclib: Support reuse of existing DDR training data
* bdcf19f404 mb/google/trulo/var/pujjolo: Add fw config for PDC
* 13897bde9a mb/google/trulo/var/pujjolo: Add wlan rtd3 setting
* 90589d44d2 soc/qualcomm/x1p42100: Reserve DDR memory regions for AOP and BL31
* 2e61995b2f soc/qualcomm/x1p42100: Add support for Hamoa SoC
* 281b01ce5e soc/qualcomm/x1p42100: Remove unused PMIC file from CBFS
* ecbca16bf4 tree: Replace union {0} initializers with {} for C23 compliance
* b74d2b77d2 mb/google/trulo/var/kaladin: Add WIFI SAR table
* 4b46a0690e mb/hp: Add HP ProDesk 600 G1 SFF Business PC (Haswell / NPCD379 SIO)
* 2339508b6c mb/google/trulo/var/pujjolo: Update P-sensor parameters
* cd2a969c82 soc/intel/pantherlake: Remove storage-off related code
* fe6fa36504 mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM
* b486c84b23 mb/google/trulo/var/pujjolo: Update DTT settings for thermal control
* ece0072d1c mb/google/trulo/var/pujjolo: Update verb table to fix pop noise
* 795157a606 mb/google/bluey: Increase MRC cache size
* 34d9305dcc soc/qc/x1p42100: Pack QcLib DTB into CBFS
* 8f09629fb1 spi_flash: Fix initialization of `flags` field in lb_spi_flash
* ab2ef8878c mb/google/trulo/var/pujjocento: Update touchscreen information
* 0bedce05d8 mb/google/nissa/var/pujjocento: Change touchpanel sequence to meet spec
* 543fb60ec4 mb/google/brox/var/lotso: Set slew rate to 1/8
* c114906239 mb/google/trulo/var/pujjocento: Update DTT settings for thermal control
* b603f23088 mb/google/bluey: Avoid using function call table
* dc64b9659d soc/qc/cmn: Refactor qclib_load_and_run function
* e290bb6750 mb/baseboard/ptlrvp: Disable memory training progress bar
* 05a38e2af3 mb/google/fatcat: Disable memory training progress bar
* f789899dac sb/intel/common/gpio: Move register defines
* d6ceaf72da mb/samsung/lumpy: Use gpio_base2_value
* 21639c3771 mb/getac/p470: Use common gpio functions
* 8d4bb94663 sb/intel/common/gpio: Add and use gpio_invert()
* 85306062d8 mb/google/skywalker: Create variant Tarkin
* 1da2f46db8 soc/intel/alderlake: Restore mem_init_override_channel_mask()
* f0d5b25e02 mb/google/trulo/var/kaladin: Add firmware name and gpio for ISH
* 0b3fc8ce2d mb/google/nissa/var/pujjoniru: Decrease cpu power limits
* f01cc9258b mb/google/rex/var/screebo: Use ACPI for touchscreen power sequencing
* ef11f95125 soc/qualcomm/x1p42100: Set 1ms TX delay
* 2c8d157ea4 {drivers, soc/qualcomm/common}: Add configurable delay for UART bitbang
* b0d2d522ea soc/qualcomm/x1p42100: Enable bootblock compression
* 1e11bda5d0 soc/intel/cmn/smbus: Drop use of update_spd_len()
* 910f111891 soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory
* 0da943ed99 soc/intel/meteorlake: Fix DDR5 channel mapping
* 87c9bb3994 soc/intel/adl: Fill in SPD data on both channels of DDR5 memory
* a23be7a6fe mb/google/fatcat/var/francka: Disable ALC721 & ALC722 clock stop support
* 227d434e2d drivers/soundwire/alc711: Support clock stop flag from devicetree
* 49219f1ce1 Docs: Use markdown autolinks instead of Sphinx doc directive
* 6afc1ff9ac soc/mediatek/mt8189: Disable 8189G APU power to reduce power consumption
* 965131e40f soc/mediatek/common: Fix build error by including stdint.h in cpu_id.h
* e49743755d mb/google/ocelot: Select EC_GOOGLE_CHROMEEC_MEC for MCHP variants
* 32b944b77a mb/google/brox/var/caboc: Update hda_verb table
* ba228d160f mb/google/fatcat: Create new kinmen4es variant
* 6a42eb9134 soc/intel/pantherlake: Disable memory training progress bar
* e9cb352706 soc/common/smbus: Support reading SPD5 hubs for DDR5
* cba46a41b7 mainboard/{hardkernel,protectli}: Drop use of DRAM_SUPPORT_DDR5
* a79f341d29 mb/google/trulo/var/pujjolo: Disable mipi camera dmic LED
* 9411c6e7c7 util/amdfwtool: Fix NULL pointer dereference in fill_dir_header
* 280d3a25e8 util/lint/kconfig_lint: Fix operator precedence issue
* fbc2d76ab3 soc/intel/*: Select 'DRAM_SUPPORT_DDRx' as appropriate
* 008f0ec078 util/smmstoretool: Alias EfiImageSecurityDatabaseGuid to "secureboot"
* 88aeb8b7cd util/smmstoretool: Allow setting authenticated variable
* e977560e72 payloads/edk2: Increase non-full-screen menu size
* ac7487d766 mb/google/fatcat: Use same MAINBOARD_PART_NUMBER for felino variants
* 0f84878c89 mb/google/brox: Handle NULL return value in variant_get_auxfw_version_file
* 749fd1a8d8 soc/intel/pantherlake: Use macro for VGA Init Control
* 3c4fb7b729 mb/google/trulo/var/pujjolo: Update verb table
* 2ae0f6cdb9 mb/google/trulo/var/kaladin: Add fw config for ELAN touchscreen
* 53dd93ff14 libpayload/drivers/pci_qcom: Fix address during ATU config
* 54016e273e util/cbmem/sysfs_drv: Fix incompatible pointer type for 'size'
* a9997f2d7f soc/intel/cmn/block: Request bus master in final op for DSP and HDA
* fea789ed63 mb/google/fatcat/var/francka: Use ACPI for touchscreen power sequencing
* 211526ff38 Revert "mb/google/brya: Fix mux_conn index used by ec/google/chromeec"
* 7b91339e55 Revert "mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinter"
* 8a45e505b9 soc/mediatek/common/dp: Change dptx_hal_phy_wait_aux_ldo_ready to static
* 350c977fef soc/intel/pantherlake: Clear crashlog record using watcher
* ae942a70b8 mb/google/trulo/var/kaladin: Update GPIOs table
* 0a4bc79685 mb/google/trulo/var/kaladin: Update USB2 driving settings
* f34bc61ca7 mb/google/trulo/var/pujjolo: Correct the Goodix touchpad description
* d4b735f9f1 mb/google/ocelot: Turn off unused I2C ports
* 190c27d08b mb/google/brya/var/marasov: Add SPD ID for K3KL6L60GM-MGCT and K3KL8L80EM-MGCU
* d79febf356 soc/qc/x1p42100: Enable QcLib, SHRM and AOP firmware load
* db10b681b4 soc/qc/x1p42100: Load and populate QcLib interface table entries
* eee3ea0346 mb/google/bluey: Enable PCIE Feature for bluey
* 6f115f7bf0 soc/qualcomm/x1p42100: Configure Gen4 PHY link for x1p42100
* 823fa6b8f6 soc/qualcomm/common: Integrate QMP PCIe 4.0 PHY 2x2/1x4
* 6bb199d258 mb/google/fatcat/var/fatcat: Move `ISH_GP_x` pads to fw_config.c
* a5212f15ce mb/google/fatcat/var/fatcat: Remove unused GPP_B06 GPIO configuration
* d7415f5d9a mb/google/trulo/var/kaladin: Remove external bypass settings
* 479b39c3e9 mb/google/ocelot: Update wake on touch GPIO
* 7095c99a87 util/cbmem: Add support for CBMEM in sysfs
* eeb15e83cb mb/gigabyte: Add ga-h81m-d2w (ITE8620E superio)
* 5537ce7c2f mb/google/fatcat: Fix GPIO config for headphone jack detection
* 953957e961 mb/google/trulo/var/pujjolo: Change ICCmax at VCCIN_AUX from 25A to 27A
* 87d5c7224b mb/google/trulo/var/pujjolo: Select Strauss keyboard to show G icon
* eb005f5f5c mb/google/brya/var: Clarify comment for 'tcss_aux_ori'
* 85b26f75d2 soc/intel/xeon_sp: Remove fast_spi_cache_bios_region
* fc4911ec35 soc/qualcomm/x1p42100: Add CPU Clock boost support for X1P42100
* 1a9fb29a53 soc/qualcomm/common: Add API to enable Zondaole PLL for X1P42100
* e272b20c85 sb/intel/common: Remove unused function prototype
* c54fde5040 sb/inte/common/gpio: Implement gpio_input() and gpio_output()
* 55bed620a4 mb/dell: Use gpio_base2_value
* 84899e6fb7 sb/intel: Convert set_gpio to gpio_set
* 0c79443ca9 sb/intel/*/gpio: Convert get_gpios to gpio_base2_value
* 69364fc9e0 sb/intel: Convert get_gpio() to gpio_get()
* 2d7891abe2 sb/intel: Add soc/gpio.h
* 6a20caea01 drivers/lenovo/hybrid_graphics: Add missing header
* 04cc15feb4 sb/intel/common/pmutil: Drop unused header
* b44c0ab25b ec/lenovo/pmh7: Include stdbool.h
* b20f6d27e2 device/dram: Rename 'USE_DDRx' config options
* 1ade8247ce mb/google/trulo/var/pujjocento: update hda_verb table for ALC257
* 28848dc4fb mb/google/trulo/var/kaladin: Add elan touchscreen support
* 9a89e3b4c6 mb/google/trulo/var/kaladin: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
* f84934a203 mb/google/trulo/var/kaladin: Add DRAM part H58G56CK8BX146
* dd76bcc4c3 soc/qc/sc7280: Relocate SHRM firmware load to common Qualcomm path
* 88b10e09b6 mb/google/ocelot: Set TPM_TIS_ACPI_INTERRUPT for all ocelot variants
* c2dfe61016 mb/google/ocelot: Disable CNVi bluetooth core in the baseboard code
* 69e6d96aad mb/google/fatcat: Configure host command ranges for FATCAT4ES variant
* 8bdc170901 mb/google/brox/var/lotso: Update VR domain config
* a6842184ab mb/google/fatcat/var/kinmen: Use ACPI for touchscreen power sequencing
* 712aac780f mb/google/rex/kanix: Use ACPI for touchscreen power sequencing
* 26e6d0be00 mb/google/rex/var/karis: Use ACPI for touchscreen power sequencing
* 00d99a6e9b mb/google/brox/var/lotso: Configure Acoustic noise mitigation
* 4b6ebbdd94 mb/google/skywalker: Initialize clkbuf and srclken in romstage
* f131f0e336 soc/mediatek/mt8189: Add clk_buf and srclken_rc drivers
* 2de0158eec soc/intel/pantherlake: Add asynchronous CBFS file loading support
* eb1b5ee116 soc/intel/cmn/block/fast_spi: Introduce a DMA transfer queue
* 182ba52792 soc/intel/pantherlake: Remove mailbox interface offset
* 2ee78458be soc/intel/pantherlake: Use CONSUMED_BIOS bit
* 9a8ba5b39a {lib, drivers/intel}: Move BMP rendering logic out of SoC code
* a617317775 mb/google/fatcat/var/kinmen: Support SAR table selection via FW_CONFIG
* 92dd8cea59 mb/google/nissa/var/riven: Add parade touchscreen support
* b98f786375 mb/google/fatcat/var/francka: Increase reset delay to 100ms for ILTK0001
* 5f0177ac5d mb/google/trulo/var/pujjolo: Update Stylus IRQ wakeup group
* 5b1a8b53b6 soc/amd/common/i23c_pad_ctrl: add I3C pad config options
* 4b58ec5ac2 soc/amd/common/block/psp: Add fTPM specific bits
* 15bf25de78 Documentation/soc/intel: Update the referenced linuxboot_defconfig
* debfac6352 mb/google/ocelot/var/ocelot: Add wake support for touchpad
* b6425a9a78 soc/amd/common: Add comments about bootblock
* 69888bc7fc util/cbfstool/amdcompress: Bail out on invalid ELF
* 3b008bde8c soc/mediatek/mt8196: Fix intermittent black screen issue
* da33feeb51 soc/mediatek/mt8189: Correct thermal SRAM base address and length

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-19 07:47:18 +00:00
Leah Rowe aa0e4205d6 re-base the T480 thunderbolt patch
i noticed that the enablement patch came first,
before the actual driver. while this functioned
overall, it was obviously flawed in terms of
the resulting git history. the person who sent
the patch previously had 0046- on both patch
names, which meant that alphabetical sorting
caused the enablement patch to be applied
before the driver patch.

furthermore:

it seems that the submitted had manually re-applied
the same Kconfig changes in the enablement patch,
adding their own name - since Kconfig is not
copyrightable anyway, in this specific example, or
otherwise trivial, it's probably fine, but the
original author on the gerrit patch is actually
Matt DeVillier:

https://review.coreboot.org/c/coreboot/+/88490

I have therefore simply re-based by checking out
Matt's patch, on patchset 1.

However, patchset 1 of Matt's patch uses patch
set 16 of:

https://review.coreboot.org/c/coreboot/+/75286

HustlerOne's lbmk merge uses patchset 18:

https://review.coreboot.org/c/coreboot/+/75286/18

The differences between the two can be observed, thus:

https://review.coreboot.org/c/coreboot/+/75286/16..18

It should be clarified that these patches are not
upstreamed yet, but under heavy review on gerrit.
However, testing has revealed that the patch is
mostly stable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-15 14:06:12 +00:00
Leah Rowe f3dc54432e Merge pull request 'T480: Add Thunderbolt support' (#387) from hustlerone/lbmk-alpine_ridge:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/387
2025-12-15 14:57:52 +01:00
Hustler One 809e5d29a4 T480(s): Add Thunderbolt support 2025-12-11 14:58:33 +01:00
Leah Rowe ec8617f27a coreboot/t480s: fix headphone jack detection
this is merged from a patch sent to coreboot by
Matt DeVillier, based upon the work done by
Arthur Heymans for the regular T480

https://review.coreboot.org/c/coreboot/+/90450/2

yes

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-10 22:30:09 +00:00
Leah Rowe 724f905aaf Merge pull request 'T480: Fix headphone jack detection' (#385) from Riku_V/lbmk:t480verbfix into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/385
2025-12-02 22:17:21 +01:00
Riku Viitanen 2dea4b79b2 T480: Fix headphone jack detection
Recently, a HDA verb bugfix was merged to coreboot:
https://review.coreboot.org/c/coreboot/+/90023

Tested on a T480. Before the fix, detection *never* worked.
After fix, it seems to reliably work.

TODO: update docs to reflect this.

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2025-12-02 21:58:53 +02:00
Leah Rowe 9d740e9512 grub: add a keyboard layout for norway
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-22 21:26:40 +00:00
Leah Rowe 7a9977af72 rebase recent dell thermal safety patch
it didn't apply. i will soon update the coreboot revisions
ready for Libreboot 25.12

just rebase this patch for now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-18 18:47:23 +00:00
Leah Rowe efd17fde19 Merge pull request 'removed duplicate "payload_uboot" for e6230_12mb' (#374) from honzo/lbmk:e6230_12mb_deduplicated into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/374
2025-11-18 15:13:22 +01:00
Leah Rowe d1606ef11f Merge pull request 'fixed typo in "grub_scan_disk" for macbook11_16mb' (#375) from honzo/lbmk:macbook11_16mb_fixed_typo into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/375
2025-11-18 15:12:48 +01:00
Leah Rowe 48b00ce3c8 Merge pull request 'config/coreboot/default: Disable Latitude early thermal shutdown' (#376) from nic3-14159/lbmk:mec5035-updates into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/376
2025-11-18 15:12:28 +01:00
Nicholas Chin c0dab33972 config/coreboot/default: Disable Latitude early thermal shutdown
Disable the sudden EC initiated shutdown on the Sandy Bridge/Ivy Bridge
Dell Latitude laptops as soon as the reaches 87 degrees, allowing the
standard CPU thermal throttling mechanisms to work.

Fixes: https://codeberg.org/libreboot/lbmk/issues/202

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2025-11-18 06:48:38 -07:00
libreboot Contributor fda3ac975a removed duplicate "payload_uboot" for e6230_12mb 2025-11-16 00:19:36 +00:00
libreboot Contributor 831fa657de fixed typo in "grub_scan_disk" for macbook11_16mb 2025-11-16 00:18:31 +00:00
Leah Rowe 1b10c072d3 tree.sh: tidy up check_gnu_path
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-15 16:57:48 +00:00
Leah Rowe 7ef7e02f73 lib.sh: reduce indentation in setvars
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-15 16:55:27 +00:00
Leah Rowe 214ed3efd2 get.sh: reduce indendation in fetch_targets
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-15 16:51:59 +00:00
Leah Rowe 9d6af0063b get.sh: reduce indentation in clone_project
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-15 16:51:10 +00:00
Leah Rowe d7869a56f5 WIP: chromebook integration script
I intend to merge every Chromebook that Mrchromebox supports,
into Libreboot, ready for the Libreboot 25.12 release. Work
is still ongoing, and several changes need to happen in lbmk.

I started working on it a few weeks ago (today is
14 November 2025 as I push this).

Still TODO:

* Automatically create lbmk coreboot targets, based
  on the configs present in MrChromebox git
* Re-work git repository management in lbmk, such that
  a list of upstreams is used, instead of a hardcoded
  list per configuration; this will allow us to use
  different remotes across the same project, even where
  they diverge. This would then allow us to use the
  MrChromebook repository directly, instead of cherry-picking
  patches into upstream coreboot
* The note above about remotes would also mean that we can
  use MrChromebox's own edk2 repository directly. All of this
  would reduce the burden on lbmk.git
* Support building edk2 payloads, exactly mirroring the
  setups used on MrChromebox builds

There are some things that need to be checked first, for
boards that use MMC-based or eMMC-based storage, for the
GRUB and SeaBIOS payloads, also U-Boot, because I will
also be using these.

As such, this current script shall sit in lbmk master, but
it is not yet finished.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-14 18:22:51 +00:00
Leah Rowe 25f523bbac get.sh: return clone_project if multi-tree
this is the true fix, replacing the fixes previously
reverted.

the problem with the old fix was that it was a hack,
and could result in the archived backup of a code repo
being the wrong one; the destination was the one for
the main repo, but what if we were cloning the backup?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 22:40:29 +01:00
Leah Rowe bec7e6d4cb Revert "get.sh: don't frivolously copy tmp git clones"
This reverts commit b840cf3a83.
2025-10-17 22:32:43 +01:00
Leah Rowe f632b8aed7 Revert "get.sh: remove a redundant check"
This reverts commit e2a97455cc.
2025-10-17 22:32:35 +01:00
Leah Rowe e2a97455cc get.sh: remove a redundant check
loc is never empty.

if it is, it's a bug. don't hide bugs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 21:01:31 +01:00
Leah Rowe b840cf3a83 get.sh: don't frivolously copy tmp git clones
this fixes a regression in a previous patch, this time
also taking account for the different cache locations.

all of get.sh needs to be purged, and re-written clean.
it looks clean. but it's years of hacks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 20:57:18 +01:00
Leah Rowe 2aea7f6229 Revert "get.sh: make forcepull a macro"
This reverts commit b3232a7c4a.
2025-10-17 16:07:16 +01:00
Leah Rowe b3232a7c4a get.sh: make forcepull a macro
:

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 14:02:55 +01:00
Leah Rowe 54aa5b7d32 tree.sh: unify -f/-F in case/switch handling
they're the same commands, but -F does forcepull

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 13:57:14 +01:00
Leah Rowe 96f786b962 tree.sh: convert do_make into a macro
use it similarly to if_dry_build/if_not_dry_build

there is nothing cooler than an sh macro

:

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 13:29:56 +01:00
Leah Rowe 47f08e2e6d git: don't use review.coreboot.org as main
where backup links are available, use those as main instead.

this is because of the new XBMK_CACHE_MIRROR variable, which
makes --mirror be used

when performed on review.coreboot.org, this also pulls down
all changes from gerrit code review; the github backups for
example only contain the official branches, but gerrit creates
a new ref per merge request.

a user can still run ./mk -F to force pulling all repos,
including the coreboot.org ones, but use of -f will skip the
coreboot.org ones if the backup links worked and contain the
local commit needed, by a given project used in xbmk.

this patch won't change any real-world behaviour for xbmk
users, but it is done as a courtesy to the coreboot project,
in that it largely avoids a sudden surge in coreboot.org's
traffic if lots of users start doing XBMK_CACHE_MIRROR=y

if XBMK_CACHE_MIRROR is not set, or set to anything other
than y, a regular clone is performed, saving cached sources
to cache/clone/ - otherwise, cache/mirror/ is used.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-16 15:57:31 +01:00
Leah Rowe e1b6ccf69e xbmk: sort global variables alphabetically
also separate some of the special ones.

this makes the variables easier to read/find.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-16 15:46:44 +01:00
Leah Rowe d84a556bf0 get.sh: use the same directory map as --mirror
Don't hardcode the cache directory, and don't store
remotes anymore. This change retains compatibility
in practice, with the older directory location, because
it's extremely unlikely that newly generated locations
would conflict with old ones.

With this new change, non-mirror git clone caches are
now done twice; one directory per remote, rather than
one directory with two remotes.

This is just inherently much more reliable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-16 14:22:06 +01:00
Leah Rowe b333ddfe73 get.sh: use --keep-cr on git-am
Some repositories might use CR-LF line endings. This option
keeps Git from mangling patches when merging.

Repositories that don't do this, such as ALL repositories
currently used by xbmk, will be unaffected by this change.

This is being done in preparation for importing MrChromebox
edk2, as Intel's own edk2 repository on GitHub uses these.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-16 13:30:55 +01:00
Leah Rowe d83dd506c2 get.sh: More reliable git remote caching
Don't do one repository for all remotes. Do one *clone* per
remote.

This also means that users no longer download information twice,
in practice, because the backup repository will only be downloaded
if the main one didn't work.

Theoretically, this change is makes the process less efficient, but
in practise it's more reliable now.

We do now use --mirror on the git clone command for caches, but we
already did git pull --all before.

This just ensures that we absolutely have all local code.

NOTE:

The new code isn't used by default. To use it, you must do:

export XBMK_CACHE_MIRROR="y"

Otherwise, the old behaviour will continue to be used. This is
because the new code, while correct, puts more strain on upstream
servers (more code being downloaded), and can result in higher amounts
of disk space being used. The old behaviour wasn't broken, so we'll
also support that method.

TODO: perhaps also have a check in place to re-use both caches,
where available, regardless of XBMK_CACHE_MIRROR?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-16 13:29:59 +01:00
Leah Rowe 18c63682e7 Merge pull request 'Add Fedora 43 to dependencies' (#364) from bauduser/lbmk:fedora43dependency into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/364
2025-10-09 12:07:15 +02:00
bauduser 7b42779912 Add Fedora 43 to dependencies 2025-10-09 02:56:09 -07:00
Leah Rowe 11a3e9d887 xbmk: minor code cleanup (79 character rule)
recent re-factoring lead to certain code lines that
exceeded 79 characters in length.

we like to avoid this, whenever possible.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-07 05:52:36 +01:00
Leah Rowe fb95e4ad68 tree.sh: add missing -F flag
i support -F, but didn't include it in the
actual getopt string.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-07 03:02:01 +01:00
Leah Rowe ca5f0a5edd get.sh: use git-show instead, for rev checks
whatchanged is deprecated, and results in an error
on modern git versions, prompting you to include
the --i-still-use-this argument

what absolute, utter fucking arrogance. i use the
whatchanged feature every fucking day.

i will be complaining to git-scm.com about this.

but that's what we do in libreboot. we adapt.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-07 01:25:19 +01:00
Leah Rowe 8636d7497c rom.sh/tree.sh: clean up if_not_dry_build
the way it was used is messy, and a relic of the
old chained command coding style, from before when
i recently loosened that requirement.

the new focus is simple, readable code, regardless
of size.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 13:28:34 +01:00
Leah Rowe 1b54c7a744 rom.sh: use if_dry_build macro
instead of checking if_not_dry_build.

use it here the same way.

yes. shell script macros. it's how i roll.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 12:43:04 +01:00
Leah Rowe afccecbde0 rom.sh: don't run add_cbfs_option on dry builds
i added this in an earlier version of the patch, but
for some reason removed it.

this is necessary, or the build system will fail.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 07:44:38 +01:00
Leah Rowe 7d597bc4a1 disable stack overflow debug on alderlake
see patch

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 04:48:48 +01:00
Leah Rowe c716341c13 cb/kabylake: don't hardcode power_on_after_fail
I realised that the Dell OptiPlex 3050 Micro has NVRAM available.
Use that backend, and hardcode power_on_after_fail to Disable,
which is already done in cmos.default.

The Lenovo ThinkPad T480 currently has no option table in coreboot,
besides the CBFS one. For this, the CBFS option table has been
enabled, and the build system has been modified to insert
a relevant config for power_on_after_fail.

Nicholas Chin informs me that Kabylake generally has legacy NVRAM,
so enabling it for the T480/T480s should work, but we'll need
to use it in the future anyway; better to just use CBFS now.

I *could* use the CBFS backend on 3050micro as well.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 04:03:36 +01:00
Leah Rowe b5ad829ffe Merge pull request 'config/coreboot/default: Add Haswell NRI SMBIOS type 16/17 patch' (#363) from noisytoot/haswell-nri-smbios-memory into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/363
2025-10-06 03:22:07 +02:00
Ron Nazarov e82e2a1332 config/coreboot/default: Add Haswell NRI SMBIOS type 16/17 patch
This patch implements SMBIOS type 16 and 17 for Haswell NRI, making
`dmidecode -t memory` work.

From https://review.coreboot.org/c/coreboot/+/89385
2025-10-06 01:12:25 +01:00
Leah Rowe 9b104fca44 init.sh: only create cache/ here
also, the check is -e, not -d, because we
might be operating on a symlink.

it's a bit hacky but this should work.

the previous change (now reverted) broke
re-use of the main cache/ in release work
directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-05 01:23:32 +01:00
Leah Rowe ee2bca65f6 Revert "init.sh: explicitly create cache/"
This reverts commit 23f98c2958.
2025-10-05 01:21:26 +01:00
Leah Rowe 23f98c2958 init.sh: explicitly create cache/
otherwise, an error occurs when doing ./mk release

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-05 01:04:25 +01:00
Leah Rowe 1e488aae78 Revert "remove unar from dependencies"
This reverts commit e8a3cd8cd0.

We still need this for extracting the CAB files containing
KBC1126 EC firmware.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 23:57:08 +01:00
Leah Rowe c1d6cd22c2 xbmk: don't call mkdir. use xbmkdir (new function)
xbmkdir checks if a directory exists, before running
mkdir, and then still uses -p

i was testing xbmk on arch linux today, and noticed
that it errored out when a directory already exists.

i'm mitigating against buggy or differently behaving
mkdir implementations this way, by wrapping around
it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 22:42:42 +01:00
Leah Rowe f358cfaa55 coreboot/x2e_n150: fix the alderlake n fsp link
this fixes ./mk inject

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 22:23:52 +01:00
Leah Rowe 6a00b7a584 coreboot/default: don't require alderlake fsp repo
we need the full fd path to be automatically set. this
patch prevents it from being removed by ./mk -u coreboot

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 22:21:23 +01:00
Leah Rowe 247cb85489 don't compress alderlake fsp
for reproducibility, we must not compress it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 22:02:03 +01:00
Leah Rowe 183f378150 coreboot/x2e_n150: unset CONFIG_FSP_FULL_FD
otherwise, ./mk -u screws up the FSP path

we were still using the correct path for downloading
in ./mk inject, and in practise, the file used by
coreboot would have been the same, but without our
hash verification after splitting up the FSP.

that's the main reason we split FSP in lbmk, rather
than relying on coreboot's logic for this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 20:11:17 +01:00
Leah Rowe 31fa7ea591 vendor.sh: re-do the previously reverted change
but do it better. this time, the change won't cause any
behavioural differences.

the reason for the change is we don't want "$@" inside
an eval statement, if such calamity can be avoided.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 16:57:36 +01:00
Leah Rowe 2956fcc051 vendor.sh: fix setvfile
this reverts change made to this function in:

commit 4f01dc704a
Author: Leah Rowe <leah@libreboot.org>
Date:   Sat Oct 4 06:13:15 2025 +0100

    xbmk: remove even more eval statements

for some reason, the new code caused sch5545 ec firmware
to never download.

the old code wasn't horribly broken, so just use that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 16:14:36 +01:00
Leah Rowe 8334c93dac release.sh: preserve clean sbase before building
this way, the clean version can be placed inside the
release tarball.

there is a make clean option in sbase, but we should
not really on this.

the design of xbmk is that a clean src tarball is
created. there must not be build artifications in it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 10:09:24 +01:00
Leah Rowe 8969cc734f xbmk: use sbase sha512sum, not host sha512sum
the --status flag seems to be a GNUism

as stated in the previous commit, i import sbase
suckless now, so as to have a consistent implementation
of sha512sum.

this ensures that its output is reliable, when i'm using
the output of this command within backticks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 09:58:24 +01:00
Leah Rowe e9a910b33c config/git: import suckless sbase
i currently use the output of sha512sum in several
places of xbmk, which is a bit unreliable in case
output changes.

other cases where i use util outputs in variables
are probably reliable, because i'm using mostly
posix utilities in those.

to mitigate this, i now import suckless sbase, which
has a reasonable sha512sum implementation.

*every* binary it builds is being placed in build.list,
because i'll probably start using more of them.

for example, i may start modifying the "date"
implementation, adding the GNU-specific options that
i need as mentioned on init.sh

i'm importing it in util/ because the sha512sum
util is needed for verifying project sources, so
if sbase itself is a "project source", that means
we can into a chicken and egg bootstrapping problem.

this is sbase at revision:
055cc1ae1b3a13c3d8f25af0a4a3316590efcd48

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 09:20:12 +01:00
Leah Rowe 2cfaba181b xbmk: rename cv variables, for clarity
the new names are still a bit crap, but a bit better.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:41:25 +01:00
Leah Rowe 1943dba608 tree.sh: rename xtree to xgcctree, for clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:37:41 +01:00
Leah Rowe 51e424c7d1 tree.sh: rename btype to buildtype, for clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:36:18 +01:00
Leah Rowe d95af9ba44 vendor.sh: rename _t to blobtype, for code clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:33:26 +01:00
Leah Rowe 63002732f5 tree.sh: rename _f to flag, for code clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:29:33 +01:00
Leah Rowe b7a9aad9fc get.sh: delete tmp patch list when done
yet another oversight

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:20:27 +01:00
Leah Rowe a115679c57 get.sh: sort patches when applying
this was an oversight in my recent patch unrolling
the condensed code lines, to remove eval statements.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:17:53 +01:00
Leah Rowe 0776eb414c vendor.sh: make the fsp hack a bit cleaner
it's still a dirty hack. i really should make
a better check here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:12:24 +01:00
Leah Rowe 70cdb03f7f vendor.sh: correction to fsp hack
i unrolled these lines earlier, but this line was
incorrect; dl was already handled. it's dl_bkup
that we have to handle here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:08:34 +01:00
Leah Rowe 1eafcf9029 vendor.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:07:07 +01:00
Leah Rowe efd1db1ca3 release.sh: remove eval statement in nuke()
the symlink check is what made me use eval, but the
symlink check is not required, since i check every
entry that goes in nuke.list anyway.

not having that symlink check is safer than having
an eval statement on that line.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:03:12 +01:00
Leah Rowe b4c7cac8a2 xbmk: rename the "dry" variable to if_not_dry_run
and add a line break where it is used

now it is essentially a macro of sorts, used in
terms of syntax, to mean the same as:

if [ "$dry" != ":" ]; do
	thing
fi

in this case, we say:

$if_not_dry_build \
	thing

yes. macros in sh are a thing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 07:50:34 +01:00
Leah Rowe 9f84bd4f34 coreboot/mkhelper: don't use eval
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 07:36:19 +01:00
Leah Rowe 4f01dc704a xbmk: remove even more eval statements
in one or two cases, the use of eval is retained, but
modified so as to be safer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 07:17:42 +01:00
Leah Rowe 7f8d85140f xbmk: remove the setcfg function
this allows me to remove several eval calls, and the
errors relating to configs can now show exactly which
function they occured in, allowing for easier debugging.

once again, eval should be used sparingly if at all.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 05:23:47 +01:00
Leah Rowe 0a74cc8ec6 xbmk: clean up a few err calls
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 03:05:23 +01:00
Leah Rowe a09ec1d02b xbmk: remove more eval statements
i will eventually find a way to remove them all,
while still leaving the code completely clean.

in practise, i never use the contents of a file
for eval and the inputs are carefully checked.

however, over-use of eval is always a bad idea
in shell scripting.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 02:55:52 +01:00
Leah Rowe 0605fbe720 xbmk: general cleanup: unroll condensed code lines
i overlooked a number of lines, during previous cleanup

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 02:43:24 +01:00
Leah Rowe e1c70f4319 vendor.sh: remove superfluous AND
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-03 22:43:06 +01:00
Leah Rowe e1c580f6bc grub/xhci_nvme: fix target.cfg
it still said tree="xhci"

it should say  xhci_nvme

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-03 00:04:23 +01:00
Leah Rowe 093606784a add fedora42 dependencies from bauduser
this was sent by bauduser, who messed up the pull
request (number 362). i'm simply merging the
change manually.

once again, i instructed this contributor to
properly learn git vcs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 23:59:57 +01:00
Leah Rowe 5e35b0684d dependency/debian: libstdc++-arm-none-eabi-newlib
this is needed to make pico-serprog compile.

this change is submitted by "bauduser" in lbmk pull
request #362, but the PR was messed up. for such
a trivial change, I simply  merged this change
manually, instructing the contributor to properly
learn git vcs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 23:57:49 +01:00
Leah Rowe af88a066d0 grub/xhci: rename to grub/xhci_nvme
we have the "default" tree, then the "nvme" tree which adds
nvme support.

the "xhci" tree adds xhci patches, *and* nvme patches.

riku suggested that i rename it accordingly, and his advice
was quite correct, indeed wise.

this will reduce confusion for contributors, including *myself*.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 23:48:48 +01:00
Leah Rowe d90defeae3 mrc.sh: remove superfluous eval statement
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 07:09:37 +01:00
Leah Rowe a74af6aa05 tree.sh: remove superfluous eval statements
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 06:55:29 +01:00
Leah Rowe 15cefca84b rom.sh: remove superfluous eval statement
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 06:53:36 +01:00
Leah Rowe 2b4b5bf82e inject: remove superfluous use of eval
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 06:52:10 +01:00
Leah Rowe 85b10a674b init.sh: reduce the use of eval statements
also remove the unused _nogit variable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 06:51:03 +01:00
Leah Rowe 99f2c0fcf9 get.sh: reduce the number of eval statements
also split up try_fetch()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 06:27:39 +01:00
Leah Rowe be1f4ebb9c get.sh: allow force-pull via -F instead of -f
use of ./mk -F behaves the same as -f before the
previous commit.

this can be useful, during development when we want
to update revisions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 16:51:00 +01:00
Leah Rowe 24f120d1b8 get.sh: only pull if the local revision is missing
we pull from upstream in cached git repos, before performing
an operation, and we run from the cache, but we do this every
time, even if a local revision exists, defeating the purpose
of the caching; on unreliable/intermittent internet connections,
this can cause a problem.

this also causes us problems with gnulib.git and grub.cfg, which
for *some reason* are really slow, even when doing a pull.

this change improves the efficiency of the build system, during
release builds, on a development repository where we already
have lots of caches.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 16:28:04 +01:00
Leah Rowe 084b8b65c6 u-boot: make the libreboot logo rainbow again
i like the rainbow

removing it was a mistake

this patch brings it back

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 09:26:46 +01:00
Leah Rowe 2ac51f442b init.sh: break up xbmk_set_env
what this function does will differ wildly,
depending on whether it's a child instance
or a parent instance of xbmk.

break up this function accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 07:57:39 +01:00
Leah Rowe 8b351e51aa tree.sh: break up check_gnu_path to subfunctions
this whole check could probably be removed, honestly.

it was only put in place during the debian trixie testing
release cycle, before they finally updated gnat just before
the stable release of trixie came out.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 07:43:12 +01:00
Leah Rowe 3b6d2b799c vendor.sh: break up the extract_kbc1126 subshell
stick it in a new function, for easier reading.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 07:19:04 +01:00
Leah Rowe 347330a611 coreboot/x2e_n150: rename config to fspgop
because it's using fspgop init code, not libgfxinit

this is enabled by the previous patch, which now properly
handles seabios payloads when dealing with this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 23:20:25 +01:00
Leah Rowe f272c4d1c4 rom.sh: support "fspgop" init mode
for all intents and purposes, this functions like libgfxinit
corebootfb, but uses intel fsp's video initialisation instead
of coreboot's native initialisation code

this is currently in use on the x2e n150 mainboard, whose
config is dubiously named "libgfxinit_corebootfb"

now the config can be renamed, and will be, in the next commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 23:18:50 +01:00
Leah Rowe aa3ccf0433 fix up old comment in vendor/x2e_n150
theu current comment is for an old version of the n150
patch, before it was actually merged. the comment has
been adjusted, to match the actual implementation that
was merged.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 22:09:58 +01:00
Leah Rowe b786918b2b vendor.sh: use bsdunzip, not unzip
most implementations of unzip are info-zip

we already compile libarchive for bsdtar, to extract
rar archives in vendor.sh

now we also use bsdunzip

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 11:27:16 +01:00
Leah Rowe c6939cf390 libarchive: also copy bsdunzip and bsdcpio
bsdunzip in particular, can be used instead of relying
on the host to provide unzip.

most linux hosts use info-zip as the implementation,
which bsdzip is compatible with.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 11:23:52 +01:00
Leah Rowe 06c1ed009d add -p flag to old me_cleaner too
this lets you skip fptr checks

not currently used on this version, but i want this
patch here so that it can be in the future

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 03:20:07 +01:00
Leah Rowe e8a3cd8cd0 remove unar from dependencies
we use bsdtar now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 02:31:43 +01:00
Leah Rowe 8e8f29c2e5 vendor.sh: remove false error message
mkdst cycles through a bunch of outputted files
when running an extract function, to find the
right file as per defined checksums; if one is
found, it can still show errors for the others,
leading the user to think something is wrong.

remove their fear by removing this benign error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 02:29:04 +01:00
Leah Rowe 4075c8be38 vendor.sh: use bsdtar, not unar
unar is buggy and crap

and bsdtar has superior licensing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 01:56:05 +01:00
Leah Rowe e527820ceb vendor.sh: don't use unrar
the only practical way to use it is to to use
the non-free version; currently used as a
fallback if unar fails.

however, i'm also going to scrap unar and
use bsdtar instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 01:45:36 +01:00
Leah Rowe 7b297a44ce config/git: Support building libarchive
This is for bsdtar, which we will use in place
of unar, because unar is not available on all
of the distros, and we had some recent problems
with it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 01:45:36 +01:00
Leah Rowe d4f5fdec06 Merge pull request 'New mainboard: X2E_N150' (#361) from Riku_V/lbmk:x2en150 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/361
2025-09-28 01:25:27 +02:00
Riku Viitanen b4c3bafb0e New mainboard: X2E_N150
Patch in Gerrit: https://review.coreboot.org/c/coreboot/+/89281
Not working: USB3 ports only work at USB2 speeds.

IFD:
Modified the original by:
- Removing Device Exp2 region (empty anyway)
- Enlarging the BIOS region to use this freed space
- Setting the HAP bit in PCHSTRP55 using a fork of
  me_cleaner: https://github.com/XutaxKamay/me_cleaner

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 02:21:15 +03:00
Leah Rowe 9da4fa64a6 coreboot/default: allow alderlake fsp in releases
i delete unneeded fsp modules in releases, to cut down
on the tarball size. so, currently, only kabylake fsp
is distributed.

i'm now also allowing alderlake fsp, because riku has
sent a patch adding an alderlake machine to libreboot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-27 15:56:39 +01:00
Leah Rowe c9d6143e20 gru bob/kevin: make u-boot bootflow timeout 8secs
not 30secs

it's 8 seconds on x86

8 is more reasonable. 30 feels too long.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 13:33:36 +01:00
Leah Rowe fa6c3512d6 rom.sh: remove TODO note
the return is necessary when release=n while doing
release builds, because it prevents a build error
since the given images don't exist in that scenario.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:25:13 +01:00
Leah Rowe 574fd30cde inject.sh: don't exit from patch_release
return instead. xbmk's coding style specifically
prohibits anything other than x_ or err from
running "exit".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:21:40 +01:00
Leah Rowe 4fbafaaa46 init.sh: remove comment in pybin
the following checks on the path mitigates the
lack of error handling in the findpath command
that sets pypath.

this was all thought of when i initially wrote
this code. it's perfectly fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:14:45 +01:00
Leah Rowe 204e310f5a get.sh: remove unnecessary check in try_copy
the check for whether a file is present is unnecessary,
because the following cp command would also print the
file name if it doesn't exist, and exit with the same
non-zero status.

let cp do the work.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:13:17 +01:00
Leah Rowe b4fbdb448d get.sh: rename try_file to try_fetch
the previous function name was misleading, because
this tries multiple methods including git and curl.

therefore, this was renamed to match what it dose.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:12:21 +01:00
Leah Rowe e42cb4f4cd xbmk: tidy up some if statements
this is an extension of the previous work to unroll
most of the condensed code lines.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:09:46 +01:00
Leah Rowe f5060232e1 init.sh: remove TODO note
on further inspection, the following check ensures that the
python version number is 3.

if anything went wrong, the possibility alluded to in the
comment wouldn't actually matter in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-25 23:54:16 +01:00
Leah Rowe 0303167e25 init.sh: create TMPDIR *after* suid check
otherwise, it may get created as the root user, disabling
further use of lbmk until manual user intervention.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-25 02:26:48 +01:00
Leah Rowe 1a74172a17 release.sh: use cache src on release builds
use what's in cache/clone/ from the main directory

this speeds up the build process

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-25 02:25:59 +01:00
Leah Rowe 6bb4e2c72a init.sh: remove symlink check on XBMK_CACHE
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 23:34:12 +01:00
Leah Rowe dc722b5bb8 init.sh: switch back to old TMPDIR checks
the new check is still retained, to the extent that
the lock file still contains the TMPDIR string, and
it's checked whether this changed during execution.

however, the current TMPDIR handling is over-engineered
and prevents the re-use of project source caches when
doing release builds; this means that the release builds
happen much more slowly, especially for slow internet
connections.

this change *fixes* that bug. now release builds once
again re-use the main cache/ directory.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 23:26:11 +01:00
Leah Rowe 4686ba8a4a make notices a bit more readable
add line breaks, so that the license and author are
visually separated. this makes it easier to read.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 20:14:51 +01:00
Leah Rowe 5a8f350bc7 release.sh: fix typo in script: ./mk, not ./mx
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 18:19:48 +01:00
Leah Rowe 8347e2c85d xbmk: cleanup of recent code refactoring
be a bit less pedantic about if else clauses. leave the
big ones still with then on separate lines, where else
is specified.

also unroll a few condensed code lines where i missed
a few.

sloccount 2303 in lbmk. that's still only slightly bigger
than libreboot 20260907 which was 2180, and still much
smaller than libreboot 20230625 which was 3322.

this is *without* the condensed codelines, so now the only
thing that's reduced is the overall amount of logic present
in the build system.

and i should clarify that lbmk is presently much more powerful
than both of those two versions (20160907/20230625).

the 2016 one is useful for comparison historically, since that
was the last major version of libreboot prior to the great
second coming of leah in 2021; and the 2023 june release was
basically the last one before the great audits of 2023 to
2025 began.

not to brag (not much anyway), but all of this means that lbmk
is an insanely efficient build system, considering all the
features it has and what it does.

i unrolled the condensed code style in lbmk, making the scripts
a lot easier to read, because i received complainst about the
condensed style previously used; nicholas chin and alper nebi
yasak both told me that it sucked, and riku viitanen had hinted
at that same fact several months prior.

so hopefully now, lbmk is a bit nicer. those and other people
often find it challenging to challenge me because for reason
they assume i'll get upset and fly off the handle, but it's the
opposite. i want constant criticism, so that i know to improve!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 13:19:23 +01:00
Leah Rowe 03bf6c185b mk: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 08:53:24 +01:00
Leah Rowe 0275c60111 get.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 08:40:45 +01:00
Leah Rowe 193001bc71 init.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 06:54:36 +01:00
Leah Rowe ace167445f inject.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 03:13:42 +01:00
Leah Rowe 94ab695457 lib.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 02:15:41 +01:00
Leah Rowe 8d5d6a3e2a mrc.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-23 12:19:47 +01:00
Leah Rowe 45c4d4045c release.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-23 12:18:15 +01:00
Leah Rowe f5c91ff0ee rom.sh: unroll condensed code lines
ditto to last commit

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-23 11:47:25 +01:00
Leah Rowe e282586427 tree.sh: unroll condensed commands
i went further than in the previosu commit. in this
commit, i also provide indentation inside subshells,
to make it clearer that soomething is being done
inside a subshell.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-23 05:55:18 +01:00
Leah Rowe 8b3f476b57 vendor.sh: unroll condensed code lines
this is part of a general effort to make lbmk
easier for novices to understand.

more commits to follow (one for every script).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-23 02:34:00 +01:00
Leah Rowe 6b796e2b4c init.sh: make TMPDIR *after* calling xbmkpkg
otherwise, running ./mk dependencies as root will
create xbmkwd/ (temporary directories) as root,
which will then prevent non-root instances of lbmk
from being able to make temporary files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-21 19:52:14 +01:00
Leah Rowe 2c02b17810 lenovo/t440p: add a target with 4mb cbfs
this is exactly the same as the normal t440p config,
except that cbfs is 4mb instead of 8mb.

this is useful when externally updating libreboot,
or unbricking; it could also be used for lazier
installation, where you only flash the 2nd chip
without doing a disassembly to get at the other one,
if the user didn't care about neutering the ME.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-19 16:48:05 +01:00
Leah Rowe c11c5a7a14 Revert "xbmk: don't use backticks for command substitution"
This reverts commit 4999a49de3.
2025-09-18 23:35:12 +01:00
Leah Rowe 14bcb3a6fa config/dependencies: cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-18 14:55:52 +01:00
Leah Rowe fe301a019b vendor.sh: add missing error handle on sha512sum
it's still outputting to a file, with an error handle
there, but use of x_ on the sha512sum command itself
adds further assurance of reliability.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-17 17:27:39 +01:00
Leah Rowe c734a6e757 tree.sh: fix bad variable reference
we didn't want to say a variable name here.
we only wanted to say "trees".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-14 19:23:40 +01:00
Leah Rowe 995963baf4 xbmk: much more verbose error messages
use the new functionality in err(), whereby a given
function name and arguments can be provided, for
debugging purposes.

something similar was already done in a few places,
and replaced with this unified functionality.

this patch will make xbmk much easier to debug, under
fault conditions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-13 13:27:47 +01:00
Leah Rowe 7bed68f5b7 lib.sh: use xprintf in err()
if more than one argument is provided, it is interpreted
as a command, and the command is outputted.

this means that now for example, where you have:

ls -l foo | err "could not list directory"

you could do:

ls -l foo | err "could not list directory" "$@"

this would show all the arguments given to the calling
function that tried to run "ls"

let's say that function was called bar, you might do:

ls -l foo | err "could not list directory" bar "$@"

right now, it's not easy to provide good debug info
where err is used, unless it was called with x_, which
provides the command/arguments that was bugging out.

with this, we now have an easy and readable/maintainable
way to do the same thing everywhere in xbmk.

this will now be done, in a follow-up commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-13 12:09:55 +01:00
Leah Rowe edcf8cead8 lib.sh: use xprintf in x_
don't echo the arguments

this new logic shows quotes, in error outputs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-13 11:50:44 +01:00
Leah Rowe 333739961a lib.sh: check args for errors in fx_ and dx_
check that there are at least two arguments, and ensure that
they are not empty.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-13 11:47:10 +01:00
Leah Rowe ce5127e46b inject.sh: add missing semicolon in case
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 12:16:33 +01:00
Leah Rowe 0deac58e41 vendor.sh: tidy up apply_deguard_hack()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 11:26:19 +01:00
Leah Rowe c738698cca vendor.sh: tidy up extract_intel_me()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 11:20:35 +01:00
Leah Rowe e9c7338cda vendor.sh: clean out 7ztest on startup
otherwise, some files from a previous me.bin scan
might still be there, which could lead to the wrong
me.bin being found.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 10:55:18 +01:00
Leah Rowe 07cda7fa12 vendor.sh: remove unnecessary rm -Rf command
this file being deleted was never created.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 10:53:38 +01:00
Leah Rowe 4999a49de3 xbmk: don't use backticks for command substitution
the newer way handles escaped characters better, and it
can be nested more easily. it's also more readable.

personally, i prefer the old way, because it's more
minimalist, but it occurs to me that a lot of people
nowadays don't know about backticks, but they do know
of the modern way.

to make the code more readable, i have modernised it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 10:29:59 +01:00
Leah Rowe 5cfe54b06d Revert "inject.sh: put tmpromdel in xbtmp, not cache/"
This reverts commit a444910bf2.
2025-09-09 19:59:46 +01:00
Polarian 9d32af58eb Update arch dependencies
* unifont was split into pcf-unifont and psf-unifont
* mipsel packages have dropped the cross prefix

Signed-off-by: Polarian <polarian@polarian.dev>
2025-09-09 14:01:52 +01:00
Leah Rowe 269fa65b93 init.sh: write-protect the lock file on startup
you can still remove it with the -f flag on rm, but
xbmk only does that on exit from the main parent
instance, or after each build stage in release.sh

because of this, the user could still manually override
the lock file; this would cause running instances of lbmk
to restart wrongly as parent instances.

there's no way to fix any of this, but users don't normally
put -f in their rm commands.

however, this is also a preventative bug fix. if a bug
is ever caused in the future, where the lock file is
created erroneously, the write protection will prevent that,
so long as *it* is still done.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-09 11:56:36 +01:00
Leah Rowe dea587a16f Revert "git/grub: use codeberg as the main mirror"
This reverts commit d06d6a1905.
2025-09-07 19:43:08 +01:00
Leah Rowe c3e52bc2ee Revert "change grub git again"
This reverts commit 1e07c4eb02.
2025-09-07 19:37:23 +01:00
Leah Rowe a00f4153c6 Revert "vendor.sh: put _pre_dest in xbtmp, not cache/"
This reverts commit 69934d18cc.
2025-09-07 19:13:50 +01:00
Leah Rowe 2873ed5e7e Revert "vendor.sh: put appdir in xbtmp"
This reverts commit 4c74311eae.
2025-09-07 19:13:36 +01:00
Leah Rowe 1e07c4eb02 change grub git again
this time to source hut.

for some reason, *grub* is slow no matter what repo
provider i host it on??

i tested srht just now, and it seems ok. let's use that.

i'm *paying* for this sourcehut account, so it better be
good!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 18:33:21 +01:00
Leah Rowe 53491bdca2 tree.sh: don't combine remkdir/cd gnupath
it's stupid. separate them, to make the code readable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 17:49:12 +01:00
Leah Rowe c4cd9c08df release.sh: delete xbmkwd on src tarballs
the previously deleted tmp/ directory was a relic
from prior to recent tmpdir changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 17:45:36 +01:00
Leah Rowe 4c74311eae vendor.sh: put appdir in xbtmp
do away with redundant variable "vendir"

the "appdir" directory is for files extracted from
vendor updates, which are then further processed to
create the real files that we need, such as me.bin
images processed via me_cleaner.

thus, appdir should go in xbtmp.

the appdir currently clutters vendorfiles/, which is
not ideal.

we want it to be that the vendorfiles/ directory only
contains the final firmwares.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 17:34:24 +01:00
Leah Rowe a444910bf2 inject.sh: put tmpromdel in xbtmp, not cache/
cache/ is meant for permanent cached files, not for
temporary files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 17:28:19 +01:00
Leah Rowe 23fb10c3f5 mk: include mrc.sh before inject.sh
and vendor.sh before mrc.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 17:04:58 +01:00
Leah Rowe 69934d18cc vendor.sh: put _pre_dest in xbtmp, not cache/
XBMK_CACHE (cache/) is meant for permanently cached
files, not temporary files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 15:26:35 +01:00
Leah Rowe 4475b4db4b init.sh/tree.sh: put PATH dirs in xbtmp
e.g. gnupath, xbmkpath

these currently go in XBMK_CACHE/, which is bad
because they're meant to be temporary.

XBMK_CACHE is for permanent files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 15:24:02 +01:00
Leah Rowe f5e8483f41 init.sh: bail if date is non-GNU (for now)
We currently use GNU-only options in the date command,
when initialising a Git repository.

This isn't a problem in practise, on non-GNU implementations
if not initialising a Git repository, because it's only
used in that situation.

In practise, only those systems with GNU coreutils and libc
are used to compile releases, so this is OK for me at least.

Future portability improvements will correct the issue, and
then this error check can be removed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 14:20:21 +01:00
Leah Rowe 882a6917bc lib/init.sh: sanitize the version string
the release functions in release.sh rely on the
version string *not* being a path containing slashes.
just a single string e.g. "foo", not e.g. "foo/bar"

this is because several checks there make that
assumption. in practise, we always ensure that tags
and such do not contain these characters.

however, someone else working on their own version
of xbmk might not know of this design flaw, so let's
try to correct it in code.

we can add more filtering as designed, in the relevant
function (xbmk_sanitize_version).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 14:06:57 +01:00
Leah Rowe 1c02f2a770 release.sh: put vdir in xmtmp, not XBMK_CACHE
XBMK_CACHE is meant for permanent cached files, not
temporarily files.

the temporary release files are copied upon successful
return, to their rightful place under release/

this new change also reduces the chance of race
conditions, if multiple xbmk instances are used; while
not yet supported as a use-case, this is a goal for a
future design change.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 13:37:02 +01:00
Leah Rowe 5096e0040f mk: hardened PWD check (deny symlinks)
we check if the first argument is "./mk" and bail if not,
which forces you to be in the xbmk work directory.

however, this check is flawed because symlinks were still
possible.

this patch prevents a same-named symlink "mk" pointing to
the real mk from being used.

this hardening is necessary, due to several built-in
assumptions inherent within the design of xbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-05 11:46:16 +01:00
Leah Rowe d06d6a1905 git/grub: use codeberg as the main mirror
the gnu one is often really slow, for some reason.

use the official gnu mirror only as a backup.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-05 11:16:51 +01:00
Leah Rowe 92ecf145fa get.sh: put tmpgit in xbtmp
similar to the previous failed patch, which tried to
also generate it each time, but that led to issues.

this version of the same change merely maintains the
current hardcoding logic, while putting it in xbtmp.

that way, it's more robustly cleared upon exit from
the parent instance of xbmk.

this also reduces the chance of race conditions,
since it's in a unique place each time, rather than
going in XBMK_CACHE.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-05 03:59:50 +01:00
Leah Rowe ddbefea475 Revert "get.sh: put tmpclone dirs in xbtmp"
This reverts commit 01a779d4eb.

This commit broke ./mk -d coreboot for vendor files in lbmk.
2025-09-04 15:27:20 +01:00
Leah Rowe aa38608bff Revert "tree.sh: add missing colon at the end of trees()"
This reverts commit 568887cd5e.

This commit broke ./mk -d coreboot for vendor files in lbmk.
2025-09-04 15:27:07 +01:00
Leah Rowe f6d5b44757 Revert "vendor.sh: looser error handling on find_me"
This reverts commit c9a81292e5.

This never caused actual issues. Keep it strict.
2025-09-04 15:26:56 +01:00
Leah Rowe c9a81292e5 vendor.sh: looser error handling on find_me
i added a stricter check recently, but this broke
extraction on fresh lbmk clones, tested when doing
a release-build test.

loosen it up again, but only for find_me

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 07:37:32 +01:00
Leah Rowe 769d645c2a init.sh: create separate lock in release dirs
this removes the current hackiness, preventing
build errors since xbtmp is now based on xbmkpwd,
which changes when we're in the release dir.

XBMK_RELEASE is still set accordingly, so this
will still work the same way.

this is also cleaner in general.

XBMK_CACHE is still the same, so the release work
directory still re-uses files from the main work
directory, rather than re-creating them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 07:01:24 +01:00
Leah Rowe 568887cd5e tree.sh: add missing colon at the end of trees()
this is because when using chained commands at the end
of functions, sometimes you have to explicitly terminate
the line.

the way i do it in this patch is common across the
build system, to mitigate this sh quirk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 06:49:38 +01:00
Leah Rowe 01a779d4eb get.sh: put tmpclone dirs in xbtmp
and generate them, don't hardcode them - this reduces
the chance of race conditions, which we have seen in
the past and which current execution flow in xbmk even
mitigates in a few places, by doing things in a certain
order.

this change makes the code more robust and easier to
maintain.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 06:33:31 +01:00
Leah Rowe 0d107ad872 xbmk: remove xbloc, re-use xbtmp instead
we no longer separate them. xbloc was the on-disk
tmp directory, whereas xbtmp used to be in /tmp
which we assumed to be tmpfs (it may not be, but
often is on many workstation setups - and our
documentation recommended doing this).

as mentioned in the previous commit, benchmarking
shows little speed difference using tmpfs /tmp
versus on-disk /tmp, for our purposes at least.
therefore, the handling of tmp files is being
greatly simplified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 06:29:20 +01:00
Leah Rowe 64b69907ab init.sh: put TMPDIR inside xbmkpwd, not /tmp
This way, all operations will be done inside the xbmk
work directory. This is being done, so that I can then
reliably sandybox certain commands in future commits,
for example the "rm" command.

This will also allow me to unify the location of all
temporary files, in future commits. I previously used
the /tmp directory because it's tmpfs-based on many
setups, and this is great for performance. However, in
practise, I never noticed any difference in performance
when benchmarking it (testing /tmp on-disk versus tmpfs).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 06:02:57 +01:00
Leah Rowe 8a8be1dec9 get.sh: remove unnecessary variable, repofail
it is entirely unused

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 04:02:49 +01:00
Leah Rowe 3af4c7bcb1 rom.sh: simplify rmodtool copy handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 03:35:48 +01:00
Leah Rowe bec4c63b25 release.sh: remove support for the -d flag
this lets you change the directory for outputted
release files, versus the default "release" directory.

this code is buggy, because it could let you overwrite
a part of xbmk or worse - and checking for such bad
usage would require a lot more code.

knobs are for nobs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 03:31:34 +01:00
Leah Rowe e059614589 get.sh xbget: don't use eval for file/dir checks
the actual code works fine, but it's quite hacky.

there are times when use of eval is acceptable; this
is not one of those times, but i'd used it in this
instance when i was being a bit crazy about code size
reductions during my audits.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 03:26:26 +01:00
Leah Rowe 934e89510e vendor.sh: remove unnecessary error check
setting a variable in this way will never result in
an error. this is a relic from a prior re-factoring
versus older versions of the code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 00:19:37 +01:00
Leah Rowe b1f485d0f2 release.sh: fix broken release lock file handling
we need to copy the main lock file, rather than creating
a new, empty one. this is because the new lock file
handling requires it, and the release lock file will
be used during release builds.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-01 08:46:20 +01:00
Leah Rowe ed84d33e59 lib.sh and rom.sh: stricter mktemp usage
error out under fault condition

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-01 08:14:49 +01:00
Leah Rowe 40f064ae33 inject/vendor.sh: stricter set + usage
set - as soon as possible, for example in the extract_me
function.

we only turn off error handling when certain error-prone
tasks are performed, and mitigations are in place after
these commands run to make sure that the result was valid.

this is because in some cases, we want certain buggy behaviours
to be permitted, with errors handled in a more fine-tuned way,
because sh can sometimes be much stricter depending on the
implementation; otherwise, we almost always rely on -e -u in
most of the build system.

this mainly affects the vendorfile insertion logic.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-01 07:08:47 +01:00
Leah Rowe 24a8226fee init.sh: tidy up xbmk_set_env
this is a general function that sets variables,
but there are many types of variables to be set.

rather than have all the logic inside this function,
handle it in subfunctions called by xbmk_set_env.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 21:37:30 +01:00
Leah Rowe 7c04cd37b5 init.sh: tidy up xbmk_child_set_tmp
the checks of xbmk cache/threads is unrelated.

this has been moved back to the calling function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 21:33:00 +01:00
Leah Rowe 2d20be3d99 init.sh: remove unnecessary lockfile checks
we don't need these anymore, because we now know
whether or not the lock file exists in these cases.

this is because child/parent instance determination
is now done based on the presence of that file, rather
than how TMPDIR is set; and TMPDIR is now set accordingly,
via more robust logic as in previous patching.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 21:30:29 +01:00
Leah Rowe c148b220d8 init.sh: move TMPDIR handling to own functions
this makes xbmk_set_env easier to read

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 21:28:12 +01:00
Leah Rowe f96bf2b2cd init.sh: prevent race condition with TMPDIR
it is extremely unlikely to occur, but this patch reduces
the likelihood even further. that unlikely occurance is:

when creating a TMPDIR, it's possible that it was already
created before. this is OK on child instances, where that
is the intended behaviour (unified TMPDIR), but not for
parent instances.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 20:39:07 +01:00
Leah Rowe bbce74d78a init.sh: MUCH safer TMPDIR handling
we previously checked whether xbmk was running a child
instance, based on the initialisation of TMPDIR, but
this relied on unreliable string substitutions, which
could not be made inherently reliable. there were also
no checks on whether the given TMPDIR, even if correct,
was a directory or whether it was a symlink; there were
also no checks on whether it changed.

now with this change, child instances are detected by
the presence of the lock file. the parent instance
writes the generated TMPDIR location in that file, and
this is checked again in the child instance, to ensure
that the TMPDIR didn't change; it also errors out if
the TMPDIR doesn't exist or if it is a symlink.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 20:25:00 +01:00
Leah Rowe ad58364e18 mk: simplify the main script check
it's still not perfect, but now it's unambiguous.

the previous generic check was written based on the
fact that xbmk's main script used to also be called
via several symlinks, which is no longer the case.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 18:27:09 +01:00
Leah Rowe 09646783a5 config/dependencies: add --no-install-recommends
use this on the debian dependencies, otherwise it installs
a bunch of extra crap e.g. xorg crap, in some circumstances,
which someone probably won't want when they're in a minimal
chroot or something.

reported by ron nazarov. thank you ron!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-30 07:22:38 +01:00
Leah Rowe d9011da0eb inject.sh: redirect stderer to /dev/null FIRST
for the grep command, we must ensure that errors are
suppressed *BEFORE* outputting to a file. depending
on the sh implementation, the previous code might
have begun outputting to a file before suppressing
errors.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-29 04:44:52 +01:00
Leah Rowe 50a0bac01c vendor.sh: tidy up extract_intel_me
too many chained commands. break it out a bit.

this makes it more readable, without changing behaviour.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-26 07:01:35 +01:00
Leah Rowe 9fb707b49b rom.sh: safer use of cat in copyps1bios
the output to a file also has its own error handling,
but x_ can be used safely to provide additional assurance
that the script will break if an error occurs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 18:31:33 +01:00
Leah Rowe 89238c0579 tree.sh: tidy up check_cross_compiler
group related operations together, without whitespace.

declare all variables at the start of the function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 17:38:29 +01:00
Leah Rowe 07562e3f28 tree.sh: don't re-check xgcc needlessly
instead, create a file indicating that a given xgcc
target had already been built successfully, within a
given coreboot tree.

this will considerably speed up the building of release
archives, especially when there are a lot of boards.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 16:02:40 +01:00
Leah Rowe 66f1be1ba7 tree.sh: check xgcc AFTER checking elfdir
if e.g. elf/coreboot/default/w500_16mb contains readied
images from before, crossgcc is still being checked.

if you already built all the coreboot images, and wanted
to just modify all the payloads for example, this would
result in a much slower re-build process, because it is
needlessly re-checking crossgcc every time.

by doing it this way, we need up the testing of payloads
quite considerably, during xbmk development.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 15:49:10 +01:00
Leah Rowe c12965f8e4 lib.sh: safer pad_one_byte function
instead of copying to a temp file and then
concatenating with padding back to the main
file, we concatenate and create the temp file,
then move the temp file back to the main file.

this is because cat can be quite error prone,
more so than mv, so this will reduce the chance
of corrupt files being left behind depending
on the context (of course, the latter is often
avoided due to xbmk's design, which emphasises
use of temporary files first).

this matches the same design used in the function
unpad_one_byte, which creates the deconcatenated
output in a temporary file first, moving it back.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 15:38:29 +01:00
Leah Rowe 7e6f52ec0a vendor.sh: use pad/unpad functions
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 03:59:35 +01:00
Leah Rowe 616ef52a6f lib.sh: additional error handling on cat
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 03:48:27 +01:00
Leah Rowe 41945a2220 tree.sh: Delete files *before* updating hashes
The current logic deletes old project files e.g. sources,
but *after* updating the project hash.

This means that if a deletion fails, and the directory
is still there (e.g. src/coreboot/default/) afterward, it's
now a tainted archive, yet the hash has been updated, so
subsequent runs of the build system will cause unknown
errors.

This patch fixes that, by first copying the new hash to
a temporary file. *Then*, deletions are handled, and the
final hash file is updated afterward.

The code is now a bit more bloated as a result, but this will
reduce the risk of tainted sources being handled under fault
conditions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-10 14:50:32 +01:00
Leah Rowe d44c143846 tree.sh: rename hashtype to hashname
since it's the name, e.g. "default", referring to a
project tree (in this example, coreboot/default).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-10 14:17:57 +01:00
Leah Rowe 289c4e1c2f tree.sh: rename hashname to hashdir
since it's only ever used as a directory name

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-10 14:15:55 +01:00
Leah Rowe b31f2387ee tree.sh: rename hashvar to badhashvar
now the code that uses it makes a bit more sense
to the casual reader.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-10 14:13:47 +01:00
Leah Rowe 2c24b94d80 tree.sh: rename function and remove comments
the new function names make the comments redundant. the
code is now self-explanatory.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-10 14:12:48 +01:00
Leah Rowe ef79b11082 tree.sh: don't delete builds if tree==target
in that case, the previous tree-wide check will cover
it, so the current logic wastes computational time.

this patch therefore somewhat optimises the code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-04 09:33:33 +01:00
Leah Rowe 1c5c28f2cb tree.sh: re-add comments to check_hashes
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-04 09:16:58 +01:00
Leah Rowe 3d5a6bccae tree.sh: unified project hash handling
the target/project hash checks are basically identical,
so let's unify them under a single function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-02 11:31:28 +01:00
Leah Rowe a499d5bba2 rom.sh: Don't run mkhelpers if release=n
This fixes the following error on ./mk release:

cp: cannot stat 'elf/coreboot/default/d510mo/libgfxinit_txtmode/coreboot.rom': No such file or directory

I recently re-wrote the handling of coreboot images, and
I overlooked this entirely. When a given target specifies
release=n, it has to be skipped, so builds are not done.

The "release" variable is already checked, in mkcoreboottar.

Let's also put it in the other mkhelper functions, to make sure
there are no errors.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-01 05:32:25 +01:00
Leah Rowe 84a1ff85b0 coreboot/default: rev 9e41c7cec7, 18 July 2025
T480/T480s patches were dropped since they're included as
part of the upstream code now.

This update brings the following upstream changes:

* 9e41c7cec7 soc/intel/cmn/block/fast_spi: Lock DMA before exiting coreboot
* c1d45ef93b mb/google/trulo/var/kaladin: Update touchpad settings
* f13f980e03 mb/google/trulo/var/kaladin: Add fw_config probe for storage
* 50c39b3a22 mb/google/trulo/var/kaladin: Fix Type C function
* f0d50aa404 commonlib/include/commonlib: Add volatile qualifier
* 3828153ea5 soc/intel/xeon_sp/gnr: Use official microcodes
* a87cbcd3c9 soc/intel/xeon_sp/ibl: Config ACPI base using PMC device
* 480ac15044 util/cbfstool: Prevent overflow when sorting fit table entries
* bf4f08f3b6 mb/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff: early VGA output
* dd19f6bc5a util/cbmem: Extract devmem and common code to separate files
* def945f3ba soc/intel/apollolake: Measure the IBBL, IBB and OBB from the bootblock
* fbb0738272 mb/google/brox/var/lotso: Decrease cpu power limits
* ce88b12420 mb/google/ocelot: Set correct TPM I2C bus for all ocelot model variants
* e050e2fbfc mb/google/ocelot/var/ocelot: Remove irrelevant comment
* b66c8ea3d3 mb/google/ocelot/var/ocelot: Remove Bluetooth Audio offload
* d5d633f607 mb/google/ocelot/var/ocelot: Update variant.c
* 3b069d320c cbfs: Add a function to wait for all CBFS preload operations to complete
* a7710ed8fd Documentation: coding_style: Add *long* to long multi-line comment example
* 19d7104d85 drivers/intel/touch: Use recommended short multi-line comment style
* 451988d015 mb/google/trulo/var/pujjolo: Fix Goodix touchscreen function
* 542e52c126 soc/qualcomm/x1p42100: Optimize memory layout for X1P42100
* 2e47bd50f2 mb/google/trulo/var/pujjocento: Add 6W and 15W DPTF parameters
* 6e4f4538bb soc/intel/{tgl,adl,mtl,ptl}: Default to Software Connection Manager
* 1b8dd662a9 soc/qualcomm/x1p42100: Add PCIE Clock support for x1p42100
* 4d3def7514 soc/mediatek/mt8189: Fix timer reset in BL31 by using time_prepare_v2
* d898653b0e soc/meidatek/mt8196: Extract common timer code for reuse
* d1c096a5b9 src/soc/mt8196: Correct systimer register offset
* edaa67d0c9 mb/google/skywalker: Add thermal init flow in romstage
* 6aec09875b soc/mediatek/mt8189: Add thermal driver
* 5cc4b9e6ce soc/amd/common/cpu/noncar: Add bootblock overlap detection
* 67cd138df9 soc/intel/apollolake: Add missing header in measured_boot.h
* a428481574 mb/google/nissa/var/dirks: Update power limits
* 55ae0d8a37 mb/google/nissa/var/baseboard/nissa: Add power limits functions
* 82163aedc6 soc/amd/common/block/cpu/noncar: Move BSS and DATA out of PT_LOAD
* 6405641647 mb/google/fatcat: Use same mainboard part number for all fatcat variants
* c5613469ae device: Make a note that SeaBIOS doesn't support above 4G MMIO
* ced4c09359 soc/intel/xeon_sp/gnr: Implement get_mmio_high_base_size
* 7100f226ca vc/intel/fsp/fsp2_0/wcl: Add FSP headers for WCL FSP
* 5171098814 drivers/qemu/bochs: Allow building for non-x86 architectures
* d233b6c903 payloads/external/LinuxBoot/Makefile: Fix build prerequisite
* 502d19be89 payloads/external/LinuxBoot/targets/u-root.mk: Add missing prerequisite
* cba0f0b8b9 payloads/external/LinuxBoot: Rename build target
* 43a54e3b1b util/amdfwtool: Add binary parsing
* 85da3954d0 .gitmodules: Ignore changes make by what-jenkins-does
* 397c5fe420 Documentation: Add a mainboard entry for the Lenovo T480/T480s
* 6768586353 Documentation: Add information about the deguard utility
* ad8b738af0 mb/lenovo: Add ThinkPad T480 and ThinkPad T480s
* 96e381766e ec/lenovo: Add support for MEC1653 EC
* 2181b02765 util/smmstoretool: Properly initialise the authenticated variable header
* 3058464263 util/smmstoretool: Add support for creating variable from file contents
* b49f567e45 util/smmstoretool: Ensure that the FVB header isn't too large
* a6fbaa47ea util/smmstoretool: Clarify the `auth_vars` field
* 3698517d82 mb/amd: Use mec152x tool
* 5a0953614b util/amdtools: Add ec_usb_pd_fw
* e63620012c util: Add Microchip EC FW tool
* 0b5ce9d9f0 soc/intel/apollolake: Add support for IFWI Measured Boot
* 289cff3423 soc/intel/apollolake: Load the IBB into CAR
* 2408695dd3 soc/intel/apollolake: Add a loader for the IBB
* 61b66e9a81 soc/intel/apollolake: Add function to clear MCA in Bank 4
* 138402e7ff soc/intel/apollolake: Create IBB, IBBL and OBB
* 61b4e1983c mb/google/fatcat: Update PCH reset power cycle duration to 1 second
* e9af95d5ab soc/intel/pantherlake: Configure FSP UPDs for minimum assertion widths
* 79bd154b49 drivers/genesyslogic/gl9763e: Mask replay timer timeout of AER
* a775bfc2b2 soc/mediatek/mt8189: Specify MTKLIB_PATH for building BL31
* e583b2ffb7 soc/meidatek/mt8196: Extract common thermal code for reuse
* f62734976c mb/dell: Convert E6400 into a variant
* 8d60bf9975 mb/google/fatcat: select MIPI pre-prod if PTL pre-prod SoC is set
* 2f978ecab3 mb/google/fatcat: Choose platforms with pre-prod Panther Lake SoC
* eb1483ba17 soc/mediatek/mt8189: Increase SCP clock frequency from 26MHz to 416MHz
* 9c5557f982 util/abuild: Add --sequential-boards option
* 9e5234feee payloads/external/edk2: Drop our toolchain override
* 8d9e18a122 payloads/edk2: Indicate whether edk2-platforms is available
* 626fd50a94 mb/google/fatcat/var/kinmen: Enable ISH
* e7cefe4f41 soc/mediatek/mt8196: Move srclken_rc related code to common
* e9731f8925 soc/intel/pantherlake: Add configs for pre-production silicon
* 8687b3d108 mb/google/trulo/var/pujjolo: Add ISH firmware config
* 722c9314c7 mb/google/dedede/var/awasuki: Add 2 HYNIX modules to RAM id table
* 6082bd7711 ec/lenovo/h8: Rework invalid temperature reporting
* 621b1061d0 ec/lenovo/h8: Add Kconfig to select use of Thermal Zone 1
* bc116b8797 ec/lenovo/h8: Replace chip regs for BT/WWAN detect with Kconfig options
* d9169ef617 ec/lenovo/pmh7: Add CFR objects for existing options
* 45d9973a6d ec/lenovo/h8: Add CFR objects for existing options
* ce5a1e8a51 mb/google/brox: Create caboc variant
* d745d38393 soc/intel/cmn/block/fast_spi: Add DMA support
* 8e666c367d soc/qualcomm/x1p42100: Update boot critical firmware memory layout
* e35c784847 Doc/gfx/libgfxinit.md: Fix file names in source code references
* 0e682859e7 payloads/external/U-Boot: Upgrade from 2024.07 to v2025.07
* 8b52167a9f arch/x86: Add support for cooperative multitasking on x86_64
* 569b7a8861 Docs/releases: Finalize 25.06 release notes
* 5db8bf0cfa mb/trulo/var/pujjolo: Enable USB3 WWAN device
* e013c9586c mb/trulo/var/pujjolo: Modify mipi camera parameters
* 7b8520ab69 mb/trulo/var/pujjolo: Update fingerprint enable pin status
* f74027d5ae mb/google/nissa/var/craask: Add elan touchscreen support
* 396a883a0c mb/hp/snb_ivb_desktops: Include PS/2 controller ASL code for MS Windows
* 18c067d392 mb/google/fatcat/var/kinmen: Add Synaptics touchpad
* 2f5b384ba5 soc/mediatek/mt8189: Enable EARLY_MMU_INIT to improve boot time
* d5bce8c420 mb/hp: Add HP 260 G1 DM Business PC (Haswell)
* 48c6f66fa4 mb/google/ocelot: Update TPM_TIS_ACPI_INTERRUPT value in Kconfig
* 0660fe50de mb/google/ocelot: Update GPE configuration
* 5b3063802e mb/google/fatcat/var/kinmen: Fix touchscreen IRQ setting
* 6c4e502fdd mb/google/nissa/var/pujjocento: Reduce PL4 to 38W with no battery
* 6e92554ab6 mb/trulo/var/pujjolo: Modify FW_CONFIG for mipi camera
* 4f5f75da34 mb/trulo/var/pujjolo: Correct USB3 Type-A OC pins
* a1dfd39e04 mb/google/fatcat/var/kinmen: Add AUDIO_UNKNOWN and probe for ALC721
* 306544b427 mb/google/fatcat/var/francka: Add AUDIO_UNKNOWN and audio probes
* edf47d44cd mb/google/fatcat/var/fatcat: Disable Audio for invalid Audio FW_CONFIG
* 454079c3bc lib/cbfs: Ensure cache buffer alignment in ramstage
* 0ef670a66a mb/google/ocelot/var/ocelot: Configure FPS related changes
* 6ab37f0e0e mb/google/ocelot/var/ocelot: Add FW_CONFIG for Finger Print
* 3f61df24d5 mb/google/ocelot/var/ocelot: Add FW_CONFIG for Storage
* bb95a26cda mb/google/ocelot/var/ocelot: Add FW_CONFIG for WiFi
* 410b3c697f mb/google/ocelot/var/ocelot: Add FW_CONIG for ISH
* afaf4c3d7b mb/google/brya/variants/pujjolo: Update ISH GPIOs and add ISH firmware name
* f6de6f8933 mb/google/fatcat: Drop redundant SNDW GPIO mapping
* 584fdd6572 soc/mediatek/mt8196: Remove redundant bootblock.c from Makefile.mk
* 24ea6937f2 soc/intel/apollolake: Add the Kconfig options for IFWI Boot Profile
* c68645cd88 util/supermicro: Fix mem leak in get_line_as_int error conditions
* 05396238da libpayload/drivers: Fix mem-leak in cbmem_console error condition
* 1219981177 drivers/emu/qemu: Add a comment about fw_cfg assumptions
* d866e72b3a mb/google/fatcat/var/kinmen: Set CRFP to use GPIO for status
* 4367daae20 drivers/spi: Add option to generate proper PowerResource _STA
* 03c331399c mb/google/nissa/var/craask: Add focaltech touchscreen support
* b3d7c40fb5 mb/siemens/mc_rpl: Remove code for board_id
* 5de16ed1b8 mb/siemens/mc_rpl: Remove unused embedded controller code
* a1067ec6de mb/siemens/mc_rpl: Remove unneeded code to select a VBT name in CBFS
* 463cda84d2 mb/siemens/mc_rpl: Remove unused Type-C data definition
* dcbe591201 mb/siemens/mc_rpl: Use SPD data from HWInfo instead of from CBFS
* 6c059f8af3 IVB mainboards: Drop 1024M option for gfx_uma_size
* 3b61dbaa06 mb/asus/p8z77-m_pro: Remove incorrect gfx_uma_size options
* 2b7115b139 mb/hp/snb_ivb_desktops: Add gfx_uma_size options up to 512MB
* d99769bbde mb/hp/snb_ivb_desktops/variants: enable 4th sata port on tested models
* 95784dbafb mb/google/ocelot/var/ocelot: Add FW_CONFIG for Audio
* f323adb19f soc/mediatek/mt8189: Increase SPI NOR clock rate from 26MHz to 52MHz
* 689af47b52 commonlib: Add pvmfw related timestamps
* f1d06a5ad4 soc/intel/common/block/memory: Provide a way to use SPD data from memory
* 11b1dc0a97 Reapply "util/cbmem: Consolidate CBMEM and coreboot table access"
* 13f1c6118e Documentation: Update cbmem.md with more information
* 07267d19ce arch/x86/postcar_loader: Add comment line for reloc_params assignment
* e94ac6e655 mb/google/nissa/var/pujjocento: Reduce PL4 to 38 W with no battery
* 2eaec1b53a sbom: Fix build with merged bootblock and romstage
* 267f08dafd MAINTAINERS: Add KunYi Chen as maintainer for LattePanda Mu

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-23 04:09:47 +01:00
Leah Rowe cc2f08e7bb Revert "coreboot: rev 8b52167a9f 13 July 2025, rebase t480"
This reverts commit 32dfdfbb01.

The update caused an issue on T480:

Backlight comes on, then off, then on, then off, repeatedly, and
never gets to the payload. Will have to investigate further.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-14 11:26:58 +01:00
Leah Rowe 32dfdfbb01 coreboot: rev 8b52167a9f 13 July 2025, rebase t480
coreboot/default: update t480 patches to set 38

see: https://review.coreboot.org/c/coreboot/+/83274/38

I was previously using:
https://review.coreboot.org/c/coreboot/+/83274/25

Matt DeViller aka MrChromeBox, recently took over the
patch set, tidying up and re-factoring the code so that
it's more suitable for upstream. Several hacky behaviours
were removed, for example the MEC1663 code is now its own
code in coreboot, rather than being bolted onto the H8s code.

Certain T480-specific changes made to global parts of the
coreboot code are now done only on the tree itself.

Mate Kukri has also tested Matt's recent updates. More
testing still needed on Nvidia dGPU models, which never
worked before anyway; Intel GPU models should still work.

Thermas zone handling is also improved. See patch:
https://review.coreboot.org/c/coreboot/+/88415/1
https://review.coreboot.org/c/coreboot/+/88416/2

Functionally, this is mostly the same as before. As I said,
Matt has focused on code cleanup, so that the board can be
properly upstreamed. Hopefully this will be merged soon,
in coreboot-main.

Besides this, the following upstream changes were imported:

* 8b52167a9f arch/x86: Add support for cooperative multitasking on x86_64
* 569b7a8861 Docs/releases: Finalize 25.06 release notes
* 5db8bf0cfa mb/trulo/var/pujjolo: Enable USB3 WWAN device
* e013c9586c mb/trulo/var/pujjolo: Modify mipi camera parameters
* 7b8520ab69 mb/trulo/var/pujjolo: Update fingerprint enable pin status
* f74027d5ae mb/google/nissa/var/craask: Add elan touchscreen support
* 396a883a0c mb/hp/snb_ivb_desktops: Include PS/2 controller ASL code for MS Windows
* 18c067d392 mb/google/fatcat/var/kinmen: Add Synaptics touchpad
* 2f5b384ba5 soc/mediatek/mt8189: Enable EARLY_MMU_INIT to improve boot time
* d5bce8c420 mb/hp: Add HP 260 G1 DM Business PC (Haswell)
* 48c6f66fa4 mb/google/ocelot: Update TPM_TIS_ACPI_INTERRUPT value in Kconfig
* 0660fe50de mb/google/ocelot: Update GPE configuration
* 5b3063802e mb/google/fatcat/var/kinmen: Fix touchscreen IRQ setting
* 6c4e502fdd mb/google/nissa/var/pujjocento: Reduce PL4 to 38W with no battery
* 6e92554ab6 mb/trulo/var/pujjolo: Modify FW_CONFIG for mipi camera
* 4f5f75da34 mb/trulo/var/pujjolo: Correct USB3 Type-A OC pins
* a1dfd39e04 mb/google/fatcat/var/kinmen: Add AUDIO_UNKNOWN and probe for ALC721
* 306544b427 mb/google/fatcat/var/francka: Add AUDIO_UNKNOWN and audio probes
* edf47d44cd mb/google/fatcat/var/fatcat: Disable Audio for invalid Audio FW_CONFIG
* 454079c3bc lib/cbfs: Ensure cache buffer alignment in ramstage
* 0ef670a66a mb/google/ocelot/var/ocelot: Configure FPS related changes
* 6ab37f0e0e mb/google/ocelot/var/ocelot: Add FW_CONFIG for Finger Print
* 3f61df24d5 mb/google/ocelot/var/ocelot: Add FW_CONFIG for Storage
* bb95a26cda mb/google/ocelot/var/ocelot: Add FW_CONFIG for WiFi
* 410b3c697f mb/google/ocelot/var/ocelot: Add FW_CONIG for ISH
* afaf4c3d7b mb/google/brya/variants/pujjolo: Update ISH GPIOs and add ISH firmware name
* f6de6f8933 mb/google/fatcat: Drop redundant SNDW GPIO mapping
* 584fdd6572 soc/mediatek/mt8196: Remove redundant bootblock.c from Makefile.mk
* 24ea6937f2 soc/intel/apollolake: Add the Kconfig options for IFWI Boot Profile
* c68645cd88 util/supermicro: Fix mem leak in get_line_as_int error conditions
* 05396238da libpayload/drivers: Fix mem-leak in cbmem_console error condition
* 1219981177 drivers/emu/qemu: Add a comment about fw_cfg assumptions
* d866e72b3a mb/google/fatcat/var/kinmen: Set CRFP to use GPIO for status
* 4367daae20 drivers/spi: Add option to generate proper PowerResource _STA
* 03c331399c mb/google/nissa/var/craask: Add focaltech touchscreen support
* b3d7c40fb5 mb/siemens/mc_rpl: Remove code for board_id
* 5de16ed1b8 mb/siemens/mc_rpl: Remove unused embedded controller code
* a1067ec6de mb/siemens/mc_rpl: Remove unneeded code to select a VBT name in CBFS
* 463cda84d2 mb/siemens/mc_rpl: Remove unused Type-C data definition
* dcbe591201 mb/siemens/mc_rpl: Use SPD data from HWInfo instead of from CBFS
* 6c059f8af3 IVB mainboards: Drop 1024M option for gfx_uma_size
* 3b61dbaa06 mb/asus/p8z77-m_pro: Remove incorrect gfx_uma_size options
* 2b7115b139 mb/hp/snb_ivb_desktops: Add gfx_uma_size options up to 512MB
* d99769bbde mb/hp/snb_ivb_desktops/variants: enable 4th sata port on tested models
* 95784dbafb mb/google/ocelot/var/ocelot: Add FW_CONFIG for Audio
* f323adb19f soc/mediatek/mt8189: Increase SPI NOR clock rate from 26MHz to 52MHz
* 689af47b52 commonlib: Add pvmfw related timestamps
* f1d06a5ad4 soc/intel/common/block/memory: Provide a way to use SPD data from memory
* 11b1dc0a97 Reapply "util/cbmem: Consolidate CBMEM and coreboot table access"
* 13f1c6118e Documentation: Update cbmem.md with more information
* 07267d19ce arch/x86/postcar_loader: Add comment line for reloc_params assignment
* e94ac6e655 mb/google/nissa/var/pujjocento: Reduce PL4 to 38 W with no battery
* 2eaec1b53a sbom: Fix build with merged bootblock and romstage
* 267f08dafd MAINTAINERS: Add KunYi Chen as maintainer for LattePanda Mu

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-14 03:19:31 +01:00
Leah Rowe 122d009af1 coreboot/default: probe EDID twice in libgfxinit
this mitigates buggy video converters e.g. displayport
to hdmi, where sometimes the display doesn't come up.

sometimes you have to probe them twice. this is apparently
what linux does, according to nicholas chin's interpretation.

this is a really quick and dirty patch that worked for
Noisytoot on IRC, tested on their Dell OptiPlex 5050 SFF
which they are porting; the port otherwise works, and this
patch enables them to use their displayport adapter.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-13 15:21:46 +01:00
Leah Rowe dac3d6d06a rom.sh: Don't build coreboot utils if dry=":"
This fixes a build error when doing ./mk release, after
a regression caused by the last few commits.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-10 10:43:53 +01:00
Leah Rowe 6f7525a5b3 cache coreboot builds in elf/ again
This was a problem when I did it before, because individual
target builds weren't automatically re-compiled when needed.

The recent design improvements in lbmk enable this to be
done again.

Cached images in elf/ have no payloads, so they are a liability,
therefore they are padded by one byte to prevent flashing. This
solves the problem that the previous caching had.

With this change, modifying payloads can be tested without
needing to re-build coreboot each time.

The cached coreboot builds are also automatically re-built when
needed, which is another improvement this time, compared to
the last time coreboot builds were cached in this manner.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-10 04:26:31 +01:00
Leah Rowe 7c6c9ff547 tree.sh: delete individual target builds if needed
Detect when a config changes. This is done even if the
entire tree doesn't change.

This is already done per-tree if files change, but
individual project files don't change.

For example, if a grub.cfg changes, the given cached
build for that GRUB tree isn't deleted. Same thing if
a given U-Boot config doesn't change.

This patch fixes a longstanding design flaw of lbmk,
making auto-re-builds more reliable. This complements
another recent change, that deletes all target builds
of a given tree when the tree changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-10 02:00:13 +01:00
Leah Rowe fb95230a4c tree.sh: Remove redundant deletion
Target builds go inside a common directory for
the given tree now, which gets deleted, thus
deleting all target builds of that given tree.

Therefore, the deletion being removed is redundant.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-10 01:07:55 +01:00
Leah Rowe e25bca2ef7 T480/T480: Drop redundant PcieRpEnable from dt
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-08 17:57:53 +01:00
Leah Rowe cc82b733d3 tree.sh: Place target builds under tree/target/
as opposed to target/

for example:

image the command:

./mk -b u-boot amd64coreboot

This would put the U-Boot binaries here:
elf/u-boot/amd64coreboot/default/

With this change, they now go here:

elf/u-boot/x86_64/amd64coreboot/default/

This solves a problem that existed previously, where
you could modify a given tree in a multi-tree project,
but cached builds for targets branching separately off
of each tree would not be deleted, and thus not re-built.

This accomplishes such a result, without needing to
further check hashes of individual targets.

The latter will still be done, in a future change, because
this change doesn't fix another problem:

If you change a given config, e.g. targetname "foo" which
uses tree "bar", elf/foo/ would not be removed automatically
for re-build.

So this change only deletes individual target builds when
their master tree changes.

Where the target and tree are the same, this also means
elf/tree/target/

for example: seabios/default would create binaries in:

elf/seabios/default/default/

not:

elf/seabios/default/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-08 13:38:59 +01:00
Leah Rowe 9541dfcefa rom.sh: bump pcsx-redux copyright date to 2025
it's 2019-2025 now, not 2019-2024, because i recently imported
new pcsx-redux upstream changes that go up to June 2025.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-08 10:39:54 +01:00
Leah Rowe 91a63ccd1f hppro3500: enlarge CBFS to match the BIOS region
i enlarged the BIOS region in a previos commit, but I forgot
to enlarge CBFS. it's the policy of lbmk to enlarge CBFS when
possible, after applying a truncated ME configuration.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-08 01:59:13 +01:00
Leah Rowe ed839db0a0 pcsx-redux: bump rev 8f8cc3d5, 20 June 2025
Many other changes were imported into the wider pcsx-redux
tree, but we're mainly concerned with the OpenBIOS diffs.

This update brings in the following upstream changes, for
PCSX-Redux OpenBIOS:

* 35de25bb Fixing realloc's edge case.
* b8a9080d OpenBIOS: Annotate sio0/driver.c with enums
* c7cec91e OpenBIOS: Refactor card driver
* 4e42a6b6 Move OpenBIOS SIO to a seperate header and add enums
* a50434c5 Remove OpenBIOS dead sio1 code
* 9c3d3a1e Renaming readAligned to load32Aligned.
* 1b8312e5 [Chores] Format code
* 8b9df484 Simplifying openbios allocation scenario.
* a658a18d Brand new memory allocator.
* ba48f01b Bumped copyright date to 2025
* 64b63a13 Bumped copyright date to 2025
* 3ada28e3 [Chores] Format code
* d25af104 Fixing setjmp/longjmp attributes.
* e51ffafa Assign _bu_init alias to 0x55.
* ae1dd51e Split out the common thread structures to its own file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 21:07:19 +01:00
Leah Rowe dd65f55b29 coreboot/default: bump rev 812d0e2f62, 5 Apr 2025
There are *many* excellent changes. These changes are of note,
for Haswell mainboards (raminit improvements, courtesy Angel Pons):

* d5854e4139 Haswell NRI: Implement COMP offset optimisation
* f14880934b Haswell NRI: Use final timings after basic training
* ab29f52ee2 Haswell NRI: Measure per-task execution time
* 4ae9a79d8d Haswell NRI: Remove unused `SPD_LEN` define
* 0c5286ba34 Haswell NRI: Tidy up REUT subsequence programming
* 7766228798 Haswell NRI: Deduplicate PCODE mailbox functions

My GMP fixes have been removed, because upstream did
similar fixes which accomplish the same result.

This brings in the following upstream changes:

* 812d0e2f62 Documentation/lib: Update Timestamp documentation
* d461627668 payloads/Kconfig: Allow compression for Linux payloads
* f3ca3aa16b util/cbfstool/cbfs-payload-linux: Copy segments when compression fails
* 29440057b0 mb/starlabs/{adl_n,twl}: Don't use the IOT FSP
* eaf76d2dd1 vc/intel/fsp2_0/twinlake: Update FSP headers
* d5854e4139 Haswell NRI: Implement COMP offset optimisation
* 2739c4b773 SBOM: Change makefile to get versions from build.h
* a4156f99ff soc/intel/ptl: Add Wildcat Lake CPU ID to platform reporting
* 9f73b04074 soc/intel/pantherlake: Add new MCH ID for Wildcat Lake
* 167c771bc5 mb/google/fatcat/var/francka: Enable audio codec ALC722/ALC1320
* d8455dfbf6 mb/trulo/var/pujjolo: Change wifi SAR id fw config bits
* a9e97268fe crossgcc: Fix acpica base url version
* dabc200abb mb/lenovo/m900_tiny: enable power LED blink in S3 and S4
* cb86b9a089 mb/lenovo/m900_tiny: Put options in CFR cbtable
* 26d6da4533 mb/lattepanda/mu: Correct UART1 pinmux for native mode
* 2ec9a9f17d mb/lattepanda/mu: Update eDP/HDMI in devicetree
* 3cfa24c1bf mb/lattepanda/mu: Enable PMC drivers
* c3dba4da2b mb/lattepanda/mu: Add flashmap definition
* b5db9bcc9d soc/intel/alderlake: Enable USB3 HSIO related parameters for USB3 GEN2 support
* da49da6c82 soc/intel: Add Arrow Lake-S/HX IDs
* 8cec500968 mb/google/skywalker: Configure firmware display for eDP panel
* 78a89d4d70 soc/mediatek/mt8189: Extract code to disable secure mode from DDP driver
* 8d8d0f9746 soc/qualcomm/x1p42100: Add Clock support for x1p42100
* 20c2813891 soc/qualcomm/common: Update QUP register structure for QUP v3.2
* d24c4086e1 Documentation: Add Ramstage Bootstates
* 10d01fc2de Documentation: Add Threads
* faf0f29f8d mb/google/ocelot: Update EC host command range for variants
* ac4dfa5762 mb/hp/snb_ivb_desktops: Add Compaq Pro 6300 MT/SFF variant
* 984c64295b drivers/crb/tpm: Add new method to retrieve base address
* 1e8e5d902a mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer
* 5993dd6ef5 Documentation: Add Timers, Stopwatch, and Delays
* 4f1f502fd5 soc/mediatek/mt8189: Add PI image loader in ramstage
* e3ffa3c14f soc/meidatek/mt8196: Move PI image related code to common
* e96bf7e094 soc/qc/x1p42100: Support to generate Bootblock as multi ELF
* ae5810e358 util/qualcomm: Add MBN v7 format support
* 626c5364b8 tree: Use boolean for PcieRpSlotImplemented[]
* a90a7e0aed mb/google/bluey: Specify ROM size per board variant
* 0c9204046a mb/google/bluey: Update SPI flash vendor selection
* d636b38577 soc/qualcomm/x1p42100: Select ARM64_USE_ARM_TRUSTED_FIRMWARE
* 17abedaef6 include/smp/node: Drop unused is_smp_boot
* c0413336bc acpi/acpi.h: Use boolean
* 9be383b855 drivers/lenovo/hybrid_graphics/chip: Use boolean when appropriate
* f33507c1d8 mb/{google/zork,novacustom/mtl-h}: Use true/false for boolean
* ae282fe502 drivers/generic/bayhub: Use boolean for power_saving
* 0a94fcd2db crossgcc: upgrade binutils from version 2.43 to 2.44
* 316f76635f soc/mediatek/mt8189: Use pmif_spmi_v2 for MT8189
* f3bd8b7a07 soc/mediatek/pmif_spmi: Move pmif_spmi_force_normal_mode() to common
* ef10e93e0a tree: Replace scan-build by clang-tidy
* 6707e9281c mb/google/brox: Update cpu power limits
* f1aa0a175b util/crossgcc: Build compiler-rt using runtimes
* b0e0c688c8 buildgcc: Use -d to check libstdc++ include directory
* f2fed71533 crossgcc: Upgrade acpica from 20241212 to 20250404
* 07a8737cbd crossgcc:Initialize OPT_LDFLAGS to avoid unset variable in IASL build
* ad9bfd4243 crossgcc: Always update HOSTCFLAGS from GMP headers if already built
* c3f5d7c1ee crossgcc: Upgrade MPFR from 4.2.1 to 4.2.2
* a3ea1cb542 util/crossgcc: Upgrade CMake from 3.31.3 to 4.0.3
* f9cde87f5a crossgcc/buildgcc: Fix GMP-6.3.0 build with GCC 15 using proper prototypes
* 35d6ee9223 crossgcc/buildgcc: Remove invalid option for CMake
* bd36a4a465 util/lint: Remove missing dirs from checkpatch linter
* a0f2e42879 util/lint: Improve final newline check
* 6cb9efa19a util/lint: Ignore opensil for Kconfig linter
* 5228b3ef7b util/lint: Ignore binary files for cb lowercase linter
* 58d450d2dc util/crossgcc/buildgcc: Reorganize toolchain version variables
* baf28f8668 mb/trulo/var/pujjolo: Add GPE configuration
* eb749f2416 spd/lp5: Add SPD for MT62F2G32D4DS-023 WT:C
* 731bea2fc1 mb/lattepanda/mu: Make VBT compatible with ADL-N FSP IPU25.3
* 6b7f697309 util/amdfwtool/amdfwread.c: Properly error out in relative_offset()
* 4a99023e0f util/amdfwtool/amdfwread.c: Remove APOB_NV special case
* 000ac2cc38 util/amdfwtool/amdfwtool.c: Use physical address for APOB_NV
* d0355cb647 util/amdfwtool: Move APOB_NV quirk to amdfwtool.c
* 6fa44461e7 mb/google/fatcat/var/kinmen: Add Fn key scancode
* dd7956bfc5 mb/google/ocelot: Update GPIO table
* 1222c704b5 mb/google/fatcat/var/felino: Add pull high setting on GPP_V12 and NC_LOCK GPP_F09
* 61d74dc8f7 payloads: Propagate SPI flash address mode flag to libpayload
* 8dec5fcaf8 drivers/spi: Add 4-byte address mode flag to lb_spi_flash
* a01c368a8a drivers/spi: Refactor 4-byte addressing mode handling in SPI flash
* 30e7e604fb mb/google/fatcat/var/fatcat Align I2S and DMIC pad configuration
* 9fe1546ffe Docs/releases: Update 25.06 release notes
* 5c281529ea mb/trulo/var/pujjolo: Add FW_CONFIG for mipi camera
* e5e79de8cc mb/trulo/var/pujjoquince: Add Fingerprint function
* 0dcea61e7c cbfstool: Add multi ELF support
* 6a02f2d4a7 util/qualcomm: Add script to concatenate ELF images
* 3a0b6f625a mb/google/trulo/var/pujjocento: Enable WiFi SAR table
* 64a79d23e8 mb/trulo/var/pujjoquince: Add SD card function
* b726a9c7e9 mb/google/fatcat: Create new fatcatite4es variant
* e7984f39eb mb/google/fatcat: Create new fatcatnuvo4es variant
* cdf0c76dc8 mb/google/fatcat: Create new fatcat4es variant
* 8e5bdde028 mb/intel/ptlrvp: Add support for H58G66BK7BX067 memory
* 110aebb4d2 mb/google/nissa/var/riven: Add focaltech touchscreen support
* bc8876d56d Revert "soc/intel/xeon_sp/uncore.c: mark TSEG/SMM region as reserved"
* 64d4888349 mb/google/dedede/var/magolor: Generate SPD ID for CXMT CXDB4CBAM-ML-A
* cc116e08aa mb/google/nissa/var/quandiso: Add touchscreen FTSC1000 support
* 35648dc37b acpi: Add _func suffix for callback functions
* 03be570994 mb/google/rauru: Remove unused get_oled_description
* cc0a410ff5 soc/mediatek/dp: Correct eDP register settings for dptx_v2
* 056405a10d mb/google/ocelot: convert variants for use with ES silicon
* 4ef51ffbd7 mb/google/skywalker: Add panel driver in mainboard
* cdb49c4d2e soc/mediatek/mt8189: Add ddp driver to support eDP output
* d8fc5eba2d soc/mediatek/mt8189: Add eDP driver
* cfd0b4dd20 soc/mediatek/mt8189: Change msdcpll default freq to 384MHz
* a60c5d205b mb/google/nissa/var/meliks: Initialize display signals on user mode
* f846ec1e37 mainboard/google/fatcat: Set OEM footer logo bottom margin
* 97f92d5c69 drivers/intel: Add support for configurable footer logo bottom margin
* 3e0d8a2f2c mb/google/bluey: Enable 4-byte addressing mode
* 5568bee055 drivers/spi: Support forced 4-byte address mode via 0xB7 command
* a66d2d41f5 mb/lenovo/m900/devicetree.cb: Use OC6 enum
* f14880934b Haswell NRI: Use final timings after basic training
* 0e5d1d29bd soc/intel/skylake: Expand USB OC pins enum to OC7
* 1f28803dcd mb/trulo/var/kaladin: Create kaladin variant
* 1c2978dba6 mb/google/dedede/var/awasuki: Add ChangXin modules to RAM id table
* 912161e52d spd/lp4x: Modify parameters of SPD for NT6AP1024F32BL-J1
* 47f1b798e4 util/amdfwtool/amdfwtool.c: Remove APOB_NV src address check
* c7fe471482 mb/novacustom/mtl-h/var/dgpu: Add NVIDIA dGPU ASL code
* 24d8e6f35e Revert "mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE"
* cf7159af64 mb/siemens/mc_ehl3: Limit eMMC speed mode to DDR50
* 68ede7b860 mb/google/nissa/var/meliks: Configure Acoustic noise mitigation
* ea3cc3231c mb/intel/ptlrvp: Remove power limit constraints
* cae47dfd44 soc/intel/pantherlake: Correct DRHC and SATC in DMAR table
* e58883aace soc/intel/pantherlake: Refactor VR Fast Vmode I_TRIP threshold settings
* abbf549558 mb/google/fatcat: Add support for new Panther Lake IDs
* 57bffed893 soc/intel/pantherlake: Add new PCI and CPU IDs
* 59fce656b1 soc/intel/pantherlake: Enable Thermal Design Current for various SKUs
* 5a2de49baa soc/intel/cmn/blk/power_limit: Add helper functions to romstage
* 2207a4b59a vc/intel/fsp/fsp2_0/pantherlake: Add TDC current limit configuration
* efa24540b0 drivers/wifi/generic: Implement Bluetooth PRR DSM functions
* d92b6163e7 drivers/wifi/generic: Implement Wi-Fi PRR DSM functions
* 81d7bc386e soc/intel/cmn/blk/cnvi: Set WFDL default value to 50 ms
* 1be1ccb42e soc/intel/cmn/blk/cnvi: Use WFDL field for Wi-Fi PLDR reset delay
* ff46501d6d soc/intel/cmn/blk/cnvi: Correct generated ACPI code in comments
* 782ae11bc7 soc/intel/cmn/blk/cnvi: Add _PRR method for Bluetooth CNVi Reset
* 23f5df6eae mb/google/nissa/var/yavilla: Add H58G66CK8BX147 to RAM ID table
* 4a2c61a8a0 soc/qc/x1p42100: Allow building QC platform without upstream blobs
* 2a09db3c29 drivers/intel: Refactor logo rendering with helper functions
* 57d29ebd74 vc/google/chromeos: Don't pack `cb_plus_logo.bmp` if footer is present
* ef051256dc mainboard/google/fatcat: Drop logo_valignment selection
* dfeaead9f2 drivers/intel: Add horizontal logo alignment for splash screen
* ced9f91ae9 soc/intel/cmn: Improve comments for fw_splash_vertical_alignment enum
* d309a9dfa8 drivers/intel/fsp2_0: Suppress OEM footer in low-battery mode
* 4373eea5d8 {lib, drivers/intel}: Add splash screen footer
* be5609bdaf lib: Introduce a new function `bmp_load_logo_by_type()`
* a1dbb4076c lib: Add support for different bootsplash types
* f48865ab9a drivers/intel/fsp2_0: Refactor bitmap loading and GOP BLT conversion
* f3f9c0bd8e soc/intel/ptl: Add PCIe ACPI support for Wildcat Lake SoC
* ba715b3d25 mb/google/nissa/var/guren: Add SPD ID for MT62F512M32D2DR-031 WT:B
* 43b6f44e22 soc/mediatek/mt8189: Remove ulposc1 hardware calibration
* f63016c36f soc/mediatek: Unify DPTX swing/preemphasis API
* df91698b11 soc/mediatek/mt8196: Refactor mt8196 eDP driver for better code sharing
* 03fca0f0b4 mb/google/brox: Enable support for Realtek EC
* c8eb52c10c ec/google/chromeec: Modify Realtek EC initialization timing
* e2ac46bcc7 spd/lp5: Add SPD for hynix H58G66CK8BX147
* 812379f500 soc/mediatek/common: Move map_to_lpddr_dram_type() to common for reuse
* 7c19b1fa58 mb/google/skywalker: Run MTK FSP binary in ramstage
* 89e4fff2d3 crossgcc/buildgcc: introduce RISCV_ISA_SPEC for RISC-V ISA specification
* 620c8d9f71 mb/google/brask/var/constitution: Generate RAM ID for B3221XM3BDGVI
* 57b12d2171 spd/lp4x: Generate initial SPD for B3221XM3BDGVI
* 7c0da94aeb mb/google/brya/var/pujjoga: Add and select VBT
* bcd569faf1 mb/google/skywalker: Create variant Baze
* fb2c834f7c mb/trulo/var/pujjolo: Fix p-sensor function
* a7cd5c8c6b mb/trulo/var/pujjolo: Enable USB3 functions
* 2c53151c0c mb/trulo/var/pujjolo: Enable Ax211 wifi function
* ad78fc535a mb/trulo/var/pujjolo: Add single ram configuration
* f941b51e0e soc/mediatek/mt8189: Correct MFG MUX OPP init setting
* a1d9b69f47 soc/qc/x1p42100: Add metadata files for shrm and cpucp
* b369756680 util/qualcomm: Add script to extract a segment from ELF
* 19d1604fd7 mb/google/bluey: Update flash layout
* b9aae6180b mb/google/nissa/var/meliks: Link touchscreen device with display panel
* 6e58c0148b Reland "libpayload: arm64: Reduce DMA allocator space to 1MB"
* f18420b6a9 mb/google/fatcat: Create new felino4es variant
* 992ba78142 mb/google/fatcat: Create `felino` model for easier variant integration
* afbc9126f9 mb/trulo/var/pujjolo: Update GPIOs and probe SD card to fix S0ix suspend
* b3b1809764 mb/google/octopus: Correct channel count for DMIC
* 9accaa7238 mb/google/poppy: Correct channel count for DMIC
* 41e09a5c59 mb/google/fizz/var/karma: Correct channel count for DMIC
* fed7ad967a mb/google/reef: Correct channel count for DMIC
* 686dea9883 mb/google/glados: Correct channel count for DMIC
* ea6f150d9d soc/intel/cmd/blk/cnvi: Correct conditional logic for CNVI readiness
* 29dd511628 soc/intel: Move CNVI sideband definitions to SoC-specific files
* ea8a3e685f soc/intel/cmn/blk/cnvi: Add descriptive comments for PRRS and RSTT
* d17ace2c1b soc/intel/cmn/blk/cnvi: Remove hardcoded offset in OperationRegion
* bb3a484e36 soc/intel/*/acpi: Move the BASE ACPI method to northbridge
* 3c88e629d9 mb/google/brox/var/lotso: Generate RAM IDs for lotso
* 1bdf89d78c device/device_util.c: Complete function documentation
* bc84e1ba42 soc/intel/cmn/acpi: Refactor `SPCO` ASL method
* 4bf0f4fab3 mb/google/fatcat/var/felino: Add PIXART touchpad to devicetree
* 8269a89d32 mb/google/fatcat/var/felino: Add Synaptics touchpad to devicetree
* 4d9dfb63bd Documentation: fix broken flashrom.org link
* 3696fea4e0 mb/google/ocelot: add BOARD_GOOGLE_OCELOTMCHP
* 6ebd30bf7d mb/google/ocelot: add BOARD_GOOGLE_OCELOTITE
* da122fe8f5 mb/starlabs/*: Use PLTRST for PCH Strap GPIOs
* 7f03e3bd6c drivers/efi/efivars: Change printk level from ERROR to DEBUG
* c740786f12 drivers/gfx/generic: Use 'noop_read_resources'
* b1759c9bd6 mb/starlabs/starlite: Adjust the Flash Map to match the Twin Lake IFD
* cc1f0e5c90 mb/starlabs/starbook: Disable TME_KEY_REGENERATION_ON_WARM_BOOT
* 9381dd0cbf soc/intel/meteorlake: Make TME_KEY_REGENERATION_ON_WARM_BOOT selectable
* 9b91d50fc1 mb/siemens/mc_rpl1: Add GPIO configuration
* f44b19f2dc soc/intel/pantherlake: Fix ACPI can't tag data node error
* fad0064377 soc/intel/ptl: Add UFS support for Wildcat Lake SOC
* 3a065dbbfc mb/google/nissa/var/yavilla: Add H58G56CK8BX146 to RAM ID table
* 98f1886c89 mb/google/nissa/var/yaviks: Add H58G56CK8BX146 to RAM ID table
* 3711be4e18 soc/intel/xeon_sp: Use Kconfig to define SPI_BASE_ADDRESS
* ad05c65d72 soc/intel/xeon_sp: Initialize SPI before using it
* b4f2a51533 libpayload/arch/arm64/mmu: Fix missing CBMEM in used ranges
* 6da913bd46 docs/security/vboot: Update supported board list
* a0e6fd9a95 Documentation: Add coreboot release 25.09 template
* d4a33638f5 mb/trulo/var/pujjolo: Change dram id table
* 2ee72eaab1 soc/intel/pantherlake: Update CONSOLE_UART_BASE_ADDRESS Kconfig value
* 25385df017 vc/intel/fsp/ptl: Update PTL header files to FSP 3182_01
* 2286134002 mb/google/fatcat/var/felino: Configure CAM_VDD_EN_SOC GPIO to restore camera function
* 486604360c mb/google/ocelot: add BOARD_GOOGLE_MODEL_OCELOT
* f6926dc8a5 mb/google/nissa/var/pujjoniru: Update DTT settings for thermal control
* bb022f18d5 mb/google/dedede/var/awasuki: Add 2 NANYA modules to RAM id table
* 4ef1258436 spd/lp4x: Add Nanya memory part
* 99c138ec50 soc/mediatek: Don't attempt de-assert PERST# without pci_root_bus
* b9754131a6 mb/google/ocelot/var/ocelot: Update initial overridetree settings
* 4199351c1b Revert "libpayload: arm64: Reduce DMA allocator space to 1MB"
* a11eacc204 mb/msi/{ms7d25,ms7e06}/devicetree.cb: Add fan control config
* a069c920f5 mb/msi/{ms7d25,ms7e06}: Mimic the vendor BIOS early SIO init
* 3c23d7b3a9 src/superio/nuvoton: Add HWM initialization code
* ace18dea15 mainboard: Add 2S Intel Birch Stream MiTAC Computing R520G6SB
* 4569adeedc mainboard: Add 1S Intel Birch Stream MiTAC Computing SC513G6
* ab29f52ee2 Haswell NRI: Measure per-task execution time
* 925845c38c mb/google/ocelot: Update Kconfig
* c796c68dec mb/google/ocelot: Update MAINBOARD_PART_NUMBER
* b322d30944 mb/google/brya/var/moxie: Enable RTD3 for SSD to resolve S0ix issue
* f85f7d7aed mb/intel/beechnutcity_crb: Use host address for BiosRegionBase
* 4d3dc433f9 mb/intel/avenuecity_crb: Use host address for BiosRegionBase
* 881fe9cef6 soc/intel/alderlake: Add cpuid_to_adl mapping for Core 3 N350 SoC
* 08c8a74170 mb/trulo/var/pujjolo: Add MB usb-a port3 function.
* 317affb0ad mb/trulo/var/pujjolo: Enable Elan touchscreen function.
* de259ad970 mb/trulo/var/pujjolo: Enable s0ix function
* 712dfb3761 Revert "util/cbmem: Consolidate CBMEM and coreboot table access"
* 30865c2fb1 mb/amd/birman_plus: Skip i2c_early init
* f2e488cfbf mb/google/fatcat: Add power limit overrides for H204 and H404 SKUs
* 1537c89e8d soc/intel/cmn/block/power_limit: Enforce variant PL4 for Fast VMode
* d9c5cef7f0 soc/intel/pantherlake: Add Fast VMode PL4 Power Limit configuration
* b879342fe6 soc/intel/pantherlake: Add support for the H204 SKU
* b42842bbe5 mb/google/brox: Add brox_rtk_ec variant
* 73cc8a413a treewide: Work around GCC 15 Werror=unterminated-string-initialization
* d00f5c2d8c mb/google/skywalker: Reset xsphy0 in mainboard_init
* 40bf6c28f8 soc/mediatek/mt8189: Add support for USB port 0 reset
* 26fd33a92a mb/starlabs/starlite_adl/acpi: Fix _GPE callback type
* d14a3e23da mb/starlabs/starlite_adl: Clarify pmc_gpe0_dw0 mapping in devicetree
* 2c0417ea06 mb/starlabs/starlite_adl: Remove duplicate GPP_E12 entry
* 7e711a5bef Reland "soc/mediatek/mt8196: Specify MTKLIB_PATH for building BL31"
* 47f2c17961 mb/starlabs/*: Add CFR option to enable/disable S0ix
* dc3d524d19 mb/starlabs/starlite_adl: Use SoC common CFR forms
* 808c982104 mb/starlabs/starfighter: Use SoC common CFR forms
* 644fd7b7f5 mb/starlabs/starbook: Use SoC common CFR forms
* c7a1539d87 mb/starlabs/lite: Use SoC common CFR forms
* 3f16609ba2 mb/starlabs/byte: Use SoC common CFR forms
* c3be703b71 soc/intel/common/cfr: Add bool option for auto power on
* b3ac5ecdac soc/intel/cmn/block/cfr: Add CFR form for pciexp_aspm_cpu
* 9f8e5ab661 soc/intel/cmn/block/aspm: Use separate option variable for CPU RP
* 4247128e39 soc/intel/cmn/block/aspm: Fix ASPM control for CPU root ports
* b66b7f7860 commonlib/device_tree.c: Add a function that reads FDT ints
* c776d2dbd6 ec/google: Add support for Realtek EC in ChromeOS EC
* 8b54428200 mb/google/nissa: Override GPIO_PCH_WP for pujjocento variant
* 2060f24d60 mb/system76/mtl: Add Darter Pro 11 variants
* c2496bc62e drivers/analogix/anx7625: Add a retry mechanism to decode EDID
* 7b1eac4192 soc/mediatek/mt8189: Enable MUXes for improved peripheral stability
* da54093bb9 Update arm-trusted-firmware submodule to upstream master
* 40c84c2577 mb/starlabs/*: Tidy up the devicetree files
* cb7d2ebe5c mb/starlabs/starbook/{kbl,cml,tgl}: Remove generic.detect from the touchpad
* c4eb645a0b update_submodules: Fix submodule path handling
* 581af94115 ec/dasharo/ec: Add DTT power and battery participants
* f6dd8f534f MAINTAINERS: Add Dinesh as intel/pantherlake and google/fatcat maintainer
* f2310ab35e update_submodules: Prefix commit title with relative path
* 5fcbc709ec mb/google/fatcat/fmap: Add 1 MB from SI_BIOS to SI_All
* 24778a25de mb/trulo/var/pujjolo: Fix gtx functions.
* 619699648f soc/intel/pantherlake: Simplify P2SB and P2SB2 device operations
* beafbfd29a soc/intel/pantherlake: Remove IOE support and references
* 5277bc4efc soc/intel/pantherlake: Resolve memory corruption by using P2SB2 driver
* 61ac238bb5 soc/intel/common/block/p2sb: Add driver for second P2SB device
* 8961f6681f soc/intel/common/acpi/pcie_clk: Fix ACPI conditional compilation error
* 471df8ca5e util/crossgcc/buildgcc: Fix GMP build on GCC 15
* c24a12db86 util/cbmem: Consolidate CBMEM and coreboot table access
* 99e5a386c2 mb/amd/birman_plus/glinda: Add onboard devices
* 033810a7db payloads/libpayload/Makefile.mk: Replace nm with $(NM)
* a1738e87b5 soc/intel/panterlake: avoid SPI access delay
* 359ae67668 elog: Handle elog in later boot phase
* bf330f2dd0 security/vboot: Back up CMOS data later boot phase
* 45febdec26 mb/starlabs/starfighter: Add reset GPIO for the USB Bluetooth
* a9a51f9916 mb/starlabs/starfighter: Add missing ASPM config for the SSD
* 644ebf5ebc mb/starlabs/starbook/{adl,rpl}: Add generic Graphics driver config
* 902df45eab mb/starlabs/starfighter: Remove the overcurrent config
* b872c50f90 mb/starlabs/starfighter: Add generic Graphics driver config
* cfdf5906fd mb/starlabs/starfighter: Tidy comments for board ID GPIOs
* 9950825a2b mb/starlabs/starlite_adl: Remove extra lines
* 6d079d45d1 mb/starlabs/byte_adl: Remove comments for disconnected GPIOs
* f6a45f6856 mb/starlabs/byte_adl: Re-organise GPIOs
* 63f781b508 mb/starlabs/byte_adl: Disconnect unused GPIOs
* 6aeebc4b4b mb/starlabs/byte_adl: Reconfigure PCH Strap GPIOs
* 5f9046cbb4 mb/starlabs/byte_adl: Remove vGPIO configuration
* c589142c28 mb/starlabs/byte_adl: Add the Byte Mk III variant
* 2cb9c3ee46 mb/starlabs/byte_adl: Update the VBT to the Twin Lake version
* ad8ccf4822 Update arm-trusted-firmware submodule to upstream master
* c615de7248 soc/amd/glinda: Don't let OS put debug UART into D3
* 0251e98e9e util/amdfwtool: Do not attempt to continue processing `--help`
* 0af68855c0 mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port
* bba9d27145 mb/google/ocelot: Remove power limit override functionality
* b3776e23a7 ec/google/chromeec: Add SPI/I2C EC communication files to bootblock
* be6787a55e mb/google/skywalker: Add storage types to fw_config
* 0a41779e2e mb/google/skywalker: Add eMMC configuration
* 3e6b47980a mb/google/skywalker: Add support for getting storage id
* de251dd677 soc/mediatek/mt8189: Add support AUXADC
* a283246ef7 soc/mediatek/common: Refactor auxadc driver to support new platform
* 94686e581a mb/google/skywalker: Add DVFS support in romstage
* 8ede4bc67b soc/mediatek/mt8189: Add DVFS driver
* 096ce4b244 soc/mediatek/mt8196: Move dvfs_init() declaration to dvfs_common.h
* 0b1bc3df2c mb/trulo/var/pujjocento: Support x32 memory configuration
* 7690442d88 mb/starlabs/byte_adl: Tidy the Kconfig selections
* ab8339770e 3rdparty/fsp: Update submodule to upstream master
* 8e3adf778b soc/mediatek: Add data_version to ddr_base_info struct
* 0cdd4125be mb/trulo/var/pujjolo: Fix touchscreen function and boot up issue
* 99e0484000 mb/google/bluey: Increase bootblock size to 120KB
* 1840fb49e0 mb/google/trulo/var/pujjocento: Update gpio setting for DDI-B
* 69a067a9d6 mb/google/skywalker: Add RT1019 support for beep sound
* 4caf5131b9 mb/google/skywalker: Add ALC5645 support for beep sound
* 623caa537f mb/google/skywalker: Add RT9123 support for beep sound
* 16ff3b33ce mb/google/skywalker: Add SD card configurations
* 3b68408693 mb/google/trulo/var/pujjocento: Configure USB related settings
* 6c87853a83 mb/google/bluey: Implement board and SKU ID retrieval
* 830a887ecb mb/google/bluey: Add WLAN and SSD PCI devices to devicetree
* 891c208835 soc/qualcomm/x1p42100: Enable basic PCIe support
* a5d99a814a soc/qc/x1p42100: Perform `soc_mmu_init` inside early bootblock init
* 481001e13b soc/qualcomm/x1p42100: Add placeholder for early clock initialization
* 77c6104645 Revert "mb/google/rex: Enable use_gpio_for_status for touchscreen"
* 715e7e51c5 mb/google/fatcat/var/francka: Add support for DMIC0
* c16891ecbd soc/intel/meteorlake: Use CACHE_TMP_RAMTOP for TME exclusion range
* 394dfcaa7b mb/intel/ptlrvp: Handle GPIO support for DDR5 configuration
* 58165618da mb/google/byra/var/craask: Add VBT for HDMI variant
* ab160ca301 mb/google/byra/var/teliks: Add default VBT
* 4d5b32f7f7 mb/google/ocelot/var/ocelot: remove unused gpios
* 0e5757bfa7 mb/google/trulo/var/pujjocento: Update DTT settings for thermal control
* c34baacc72 soc/mediatek/common: Add UFS2.2 and eMMC definitions to storage.h
* f325409784 soc/mediatek/mt8189: Add SD card support
* ae435c014c soc/mediatek/mt8189: Configure and early initialize eMMC
* 91ebbb8d35 mb/trulo/var/pujjolo: Modify pujjolo variant
* aea05e51a7 mb/google/trulo/var/pujjocento: Enable WWAN function
* 47133a716d mb/google/trulo/var/pujjocento: Add P-sensor support
* 04c0527aba soc/mediatek/mt8189: Support different PMIC soluitons for MT8189(G/H)
* 80149f55f7 soc/mediatek/common: Convert spmi_dev_cnt to a function
* dcf403e43a mb/google/skywalker: Configure fingerprint pins
* 508d910ed4 libpayload/arch/mock: Select ARCH_HAS_NDELAY for ARCH_MOCK
* 96ac0224ab pci: Add support for assigning resources to SR-IOV VF BARs
* ba8be19122 mb/intel/ptlrvp: Update Kconfig for PTLRVP_CHROMEEC
* 7cbbf786cc update_submodules: Use relative paths to submodules
* dcc8400e27 mb/google/fatcat/var/felino: Modify GPIOs config
* 99af85ad36 mb/google/puff: Add VBTs for Moonbuggy and Scout variants
* 4ae9a79d8d Haswell NRI: Remove unused `SPD_LEN` define
* 0c5286ba34 Haswell NRI: Tidy up REUT subsequence programming
* 7766228798 Haswell NRI: Deduplicate PCODE mailbox functions
* ae68ef3684 cpu/intel/haswell: Export PCODE mailbox functions
* ddce240d34 cpu/intel/haswell: Clean up Makefile
* 2117ed850f mb/google/ocelot/var/ocelot: fix storage configs for ocelot
* c5488c0d6d mb/google/ocelot/var/ocelot: update gpios
* 6602a4462b mb/google/ocelot/var/ocelot: Enable hda device for AUDIO_ALC721_SNDW.
* 99b6ff25d4 soc/mediatek/mt8189: Add MTK FSP loader in ramstage
* c4fe5e2483 mb/google/skywalker: Pass reset GPIO parameter to BL31
* f59ced2c7c mb/google/fatcat/var/francka: boot up by pressing power button in S5
* df0221e62a libpayload: Protect against trying to use weak symbols in the wrong way
* d27e8ef460 update_submodules: Add an empty log line between each iteration
* d9bd7ce89f mb/google/fatcat/var/francka: Enable audio codec ALC721
* 48fbd99223 mb/google/fatcat/var/francka: Set the default HDA GPIO pin to an NC pin
* 3b975f92c7 soc/intel/pantherlake: Select TME support for the SoC
* 8408bd4863 soc/intel/pantherlake: Add TME configuration
* dc36a725d6 3rdparty/fsp: Update submodule to upstream master
* 1f47b0e018 3rdparty/intel-microcode: Update submodule to upstream main
* 4c446751c6 {commonlib, drivers}: Track firmware splash screen rendering completion
* ccb8b34194 Revert "mb/var/uldrenite: Use VBT with limited resolution for 4GBx32 memory"
* 1a00629ae2 mb/google/skywalker: Set up open-drain ChromeOS pins
* 0f2942b513 mb/google/skywalker: Raise little core CPU frequency to 2.0 GHz
* 0ba0d03140 mb/google/skywalker: Implement regulator interface
* 090bce1042 soc/mediatek/common: Add VMODEM and VSRAM_MD bucks support for MT6359
* c74610afae soc/mediatek/mt8189: Shut down PMIC on power key long press
* d1f7565403 mb/google/skywalker: Notify EC that AP is in S0
* da45a88dd3 util/abuild: Fix checking of missing_arches
* cdcbb71936 mb/google/link: Use chromeec_smi_sleep()
* 885aacf004 mb/google/byra/var/teliks: Add VBT for 11" panel option
* 2ce777f178 mb/google/byra/var/yaviks: Add VBT for yavilla
* 0db4444446 mb/google/byra/var/pujjo: Add VBT for pujjo1e
* 8c3e6ea319 mb/google/nissa/var/pujjocento: Enable touchpad
* 643bba345c mb/google/trulo/var/pujjocento: Enable touchscreen
* 3ecaf04dad mb/var/uldrenite: Use VBT with limited resolution for 4GBx32 memory
* 71ae2c7366 mb/google/octopus: Add VBTs for DOOD and FOOB variants
* 7a703fc1fb mb/google/rex: Select IOM_ACPI_DEVICE_VISIBLE
* 0121d0e3e0 ec/google/chromeec/smi: Clear events before enabling wake mask
* 5a947da94e mb/google/sarien: Update VBT from v221 to v228
* 0fba735482 soc/intel/cmn/blk: Refactor CSE status flag and optimize forced sync
* bb8d069dd3 vc/google/chromeos: Move pvmfw cbmem and enable
* f562992da1 mb/google/trulo/var/pujjocento: Enable EC keyboard backlight
* d281a3c559 mb/google/trulo/var/pujjocento: Configure tcss_aux_ori
* 7150c5e2fe mb/google/skywalker: Create variant Anakin
* aedc177f00 libpayload: arm64: Reduce DMA allocator space to 1MB
* 4ccb4a78c4 libpayload: Use Kconfig instead of weak symbol for arch_ndelay()
* 37513297d3 libpayload: Use Kconfig for architecture memcpy, not weak symbols
* bcbe17dea3 mb/google/skywalker: Configure TPM
* 3d40b7d018 soc/mediatek/mt8189: Increase bootblock size from 60KB to 70KB
* 8d25cf3ae7 soc/mediatek/mt8189: Add SSPM loader
* 8ab9f56470 mb/google/skywalker: Set up SPM in mainboard
* 368eeb7da4 soc/mediatek/mt8189: Add MCUPM loader
* bc3af56fdd soc/mediatek/mt8189: Add SPM loader
* 98782a59e9 mb/google/fatcat/var/kinmen: Add overridetree
* bbcb222f0b mb/google/fatcat/var/kinmen: Update GPIO table
* 743e3a07f5 mb/google/brya/var/nissa: Remove duplicate ACPI device GFX0
* 87110309d4 mt8196: Remove mcupm_plat.h header from mcupm_plat.h
* d6fe379e9c mb/google/ocelot: Enable LP5 and DDR5 memory configuration
* 2985af84c3 mb/google/trulo/var/pujjocento: Add Fn key scancode
* dafd7d6eb9 mb/google/nissa/var/dirks: Deassert RTL8111H's ISOLATE_ODL earlier
* c1df30db18 mb/siemens/mc_rpl: Delete fw_config since it is not used
* 7fbea3175d mb/siemens/mc_rpl: Remove unused gpio and devicetree files
* 8fdf8694e3 mb/siemens/mc_rpl: Remove Chrome OS and EC as they are not used
* e020979993 mb/siemens/mc_rpl: Adjust the flash map file
* 71fb8f63e0 mb/siemens/mc_rpl: Add new mainboard based on Intel's Alder Lake RVP
* 918f21b72d drivers/spi/winbond.c: Add W25Q64JV signature
* 278a6d2682 mb/google/trulo/var/pujjocento: update hda_verb table for ALC257
* 43f7c537f8 mb/google/trulo/var/pujjocento: update GPP_R4/GPP_R5 setting
* e4fc00adbe soc/amd/common/block: Enable MMCONF first
* cbbf380fa4 soc/amd/common/block/lpc: Use ROM3 window if possible
* 9d878fc6c0 soc/intel/xeon_sp: Add support for Emerald Rapids (5th Gen Xeon-SP) CPUs
* bd66b8cdd2 mb/google/nissa/var/rull: Enable VBOOT_EC_SYNC_ESOL for rull device
* 3155b2f64c mb/dell/haswell_latitude: Correct BOARD_ROMSIZE_KB_* for E7240
* 4d30d06637 mainboard/google/ocelot: Configure middle logo vertical alignment
* 583bf972c5 mb/google/ocelot: Remove NPK device
* 2bec5a9d9a soc/mediatek/mt8189: Check eFuse ECC in WDT init
* a89406790a mb/google/nissa/var/meliks: Set vccin_aux_imon_iccmax to 25A
* ccd4d1d1db mb/var/uldrenite: Make two pins NC to reduce S0ix power consumption
* e2baa9c7ed mb/google/bluey: Create Quenbi variant
* a98511fd23 mb/google/bluey: Only select EC_GOOGLE_CHROMEEC_SWITCHES with VBOOT
* 756d02f779 mb/google/fatcat: Remove extraneous space in Felino Kconfig name
* 8de02842d5 soc/intel/common/block/cpu: Execute post_cpus_init at BS_DEV_ENABLE
* 0baf47e03b vc/intel/fsp/ptl: Update header files from FSP 3071_00 to FSP 3144_01
* 61f043de4a mb/google/skywalker: Initialize DPM in ramstage
* 3f8702a0d6 soc/mediatek/mt8189: Add DPM v2 driver configuration
* d5bfa1c697 soc/mediatek/common: Add DPM V2 non-broadcast mode support
* 24ab31f477 mb/google/skywalker: Enable RTC boot init
* b288aaee85 soc/mediatek/mt8189: Use common RTC driver MT6359
* 12d6d0606c mb/google/skywalker: Initialize PMIC in romstage
* 2a3fd0659d soc/mediatek/mt8189: Add PMIC MT6315 driver
* 42ac3ccff4 soc/mediatek/mt8189: Add PMIC MT6359 driver
* a2010cf5ee mb/novacustom/mtl-h/Makefile.mk: include tas5825m.c in the build
* 2033075753 intel/alderlake/romstage: Implement eSOL during EC software sync
* e6a7666bcd cpu/intel/car: Skip EC software sync in common code
* ac4503d0dd security/vboot: Introduce VBOOT_EC_SYNC_ESOL Kconfig option
* 8a4b3e1346 cpu/intel/microcode: Add error handling if microcode directory is empty
* cb77cafbb4 soc/mediatek/mt8189: Add SPMI and PWRAP driver
* b9a4d6ede1 soc/mediatek/common: Correct MT6359 RTC EOSC setting
* ae2f3ab153 mb/system76: Add SMBIOS slot descriptions
* c0113106fa nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled
* 5e2aee4474 soc/mediatek/mt8196: Move sspm_enable_sram() to common code
* c81b08c4ba util/abuild: Fix building ChromeOS boards
* 62b823f69e mb/google/bluey: Increase flash size to 64MB for W25Q512NWEIM
* 276eb20b04 mb/google/bluey: Limit SPI flash support to Winbond
* 47c171a157 mb/google/bluey: Make Chrome EC optional
* 139a5b6fe0 mb/google/bluey: Select MISSING_BOARD_RESET due to lack of Chrome EC
* f9d933db36 mb/google/bluey: Introduce MAINBOARD_HAS_GOOGLE_TPM Kconfig
* e8450f78a0 mb/google/bluey: Make GPIO setups conditional on Kconfig options
* 4e8ea210bb mb/google/fatcat/var/felino: Add pull high setting on GPP_C03/GPP_C04 in gpio.c
* 65523e98a6 soc/mediatek: Extract DPM common code
* aaf373c253 mb/google/skywalker: Implement sku_id()
* be675e5369 mb/google/skywalker: Configure GPIO XHCI_INIT_DONE as output
* 9a60da5297 mb/google/skywalker: Enable ChromeOS EC
* c443478509 mb/trulo/var/pujjolo: Create pujjolo variant
* 24757047e5 util/abuild: Fix merge error
* d93f7f01a6 mb/topton/adl: Use CFR setup menu to manage options
* b59fef9678 soc/intel/cmn/cse: Add Kconfig to set ME default CFR option state
* 50a5fe77de soc/intel/meteorlake: Add CFR objects for existing options
* d53f00fbd9 soc/intel/meteorlake: Hook up the VT-d setting to option API
* e356483eb6 soc/intel/jasperlake: Add CFR objects for existing options
* 87663d1c0a soc/intel/jasperlake: Hook up the VT-d setting to option API
* 2c0c2f46d7 soc/intel/tigerlake: Add CFR objects for existing options
* d06c8dde58 soc/intel/tigerlake: Hook up the VT-d setting to option API
* 3cfb24a326 soc/intel/alderlake: Hook up the VT-d setting to option API
* 6f9df7ace4 soc/intel/cannonlake: Add/use enums for IGD config
* c8199f26e0 soc/intel/skylake: Add/use enums for IGD config
* 947dd07823 soc/intel/jasperlake: Hook up IGD config to option API
* 09adda95b9 soc/intel/meteorlake: Hook up IGD config to option API
* dcbb5771c9 soc/intel/tigerlake: Hook up IGD config to option API
* d930a3542c soc/intel/alderlake: Hook up IGD config to option API
* 9faf7ce4f4 soc/intel/alderlake: Add CFR objects for existing options
* 011baca89d cpu/x86/smm/smm_module_loader: Install bigger page tables
* aa121a9bbe payloads/external/edk2/Makefile: Set OemId Pcd
* ca9616b984 ec/system76/ec: Add config for 2nd fan without GPU
* f1f58b20b9 soc/mediatek/mt8189: Add SPI driver support
* d4a759a068 mb/system76/mtl: darp10: Add TCSS configs
* 85972101e6 commonlib/device_tree: Make *path const in dt_find_node()
* de9d76c761 mb/starlabs/starbook/tgl: Configure the eSPI GPIOs
* af7fb83ed0 soc/intel/apollolake: Hook up S0ix setting to option API
* 9979be7482 drivers/intel/fsp2_0: Remove redundant NULL checks and simplify code
* 6f9de346ae Revert "soc/amd/glinda/Makefile.mk: Use relative address for APOB_NV"
* d263e0bd92 soc/amd/glinda/Makefile.mk: Use relative address for APOB_NV
* 4f7ea3667c mb/google/rex/var/kanix: Tune camera I2C timing
* f0ad05b57e mb/google/brya/var/uldrenite: Fix USB_OC1 for USB3 A0 port
* 1140891211 mb/google/bluey: Initialize I2C, SPI, and GPIOs in bootblock
* ba8407f0c1 soc/intel: Add Arrow Lake-H/U IDs
* 3e1f96a0f4 mb/system76/mtl: Add Lemur Pro 13
* 3008b8de53 soc/intel/skylake: Show that SMRAM is unconditionally locked
* e6dc71fe9f util/superiotool: Dump one more NCT6779D register
* b50ceba64a mb/amd: Increase ROM size on boards, incorrectly limited to 16 MB
* 850703b32b mb/google/bluey: Configure FPMCU power, reset, and QUPv3 peripherals
* b4c6984a40 soc/qualcomm/x1p42100: Initialize QSPI and QUPv3 in bootblock
* fe34206442 soc/mediatek/mt8189: Add audio/display bus protection release functions
* c2b17a083d soc/mediatek/mt8189: Add PLL and clock init support
* e4cbd9ea9f soc/mediatek/mt8189: Add MTCMOS init support
* 5cf460dce9 soc/mediatek/mt8196: Fix RTC protection register unlock failure
* 2c986d016e MAINTAINERS: Add Google Bluey and Qualcomm SOC maintainers
* 64fe6fd94a util/abuild: fix TODO and update targets variable to an array
* 902288db22 util/abuild: Update version and date string
* 8504c796fc util/abuild: Remove obsolete FIXME
* a8e1113e3b util/abuild: Check functions directly instead of with $?
* b128abcdad util/abuild: Add quotes around variables
* 52b932df3b util/abuild: Group printfs to timestamps file together
* ad19c94d87 util/abuild: Fix shellcheck warnings about local vars
* d88ea14e8d util/abuild: Remove unused debug() function
* 82dea9d6d1 util/abuild: Disable shellcheck warning on interrupt()
* a2baaec067 util/abuild: Use ${} around variable names
* 9ddb54e6ad util/abuild: Update syntax from 'function func' to 'func()'
* f66c7c1037 util/abuild: Update echo to printf for consistency.
* 49ae935b37 util/abuild: Change [...] to [[...]] for consistency
* ea32e30a18 mb/starlabs/*/cfr: Remove `reboot_counter` CFR option
* d4cb553986 mb/starlabs/*/cfr: Remove `boot_option` CFR option
* 452e179727 mb/starlabs/*/cfr: Use global console CFR object
* aebef78622 xcompile: Use Walloc-size GCC option
* 074dd4f6f5 mb/google/fatcat: Set logo vertical alignment to middle for variants
* 02ca72b2d4 soc/intel/meteorlake: Hook up Pch Sleep Assertion widths
* 166f0ea146 util/abuild: Identify abuild builds with an env variable
* 511872dae3 mb/dell: Convert Latitude E7240 into a variant
* b5581d556b drivers/mrc_cache: Measure MRC cache as runtime data
* 05eb3e3716 mb/google/skywalker: Create variant Yoda
* c8ddae9ebe mb/google/puff: Use CFR setup menu to manage options
* dc19824e56 mb/google/fizz: Use CFR setup menu to manage options
* 1d62a1e857 mb/google/jecht: Clean up makefile
* 4112c77919 mb/google/jecht: Use CFR setup menu to manage options
* 6eddde31bb mb/google/beltino: Clean up makefile
* 445575525c mb/google/beltino: Use CFR setup menu to manage options
* 376a5acc24 util/lint: Add lint file for gofmt
* 4456c125f6 soc/mediatek/common: Move PMIF SPI macros to per-SoC's header
* 8efdbf0c34 mb/google/nissa/var/meliks: Use default domain_vr_config[] settings
* f07a1a76f3 mb/google/brya: Enable GNA scoring accelerator
* 6c830088da mb/google/rex/var/screebo: Generate RAM IDs
* ac2bd75817 spd/lp5: Add SPD for K3KL9L90EM-MGCU
* 66873a3812 vc/amd/fsp/glinda: Update SMBIOS Type 17 information
* b23db384a9 vc/amd/fsp: Update SMBIOS Type 17 PartNumber size
* 0b120de7c0 Documentation: Update documentation for Topton X2F-N100
* d50019d432 mb/starlabs/starbook_mtl: Select SKIP_SEND_CONNECT_TOPOLOGY_CMD
* 4aa1861fbb mb/starlabs/starbook/mtl: Configure sleep assertion times
* 183c414577 soc/intel/meteorlake: Add Kconfig to skip FSP TBT connect topology
* aa1eba2f25 drivers/intel/fsp2_0: Enable firmware splash using 24-bit BMP logo
* da29107572 mb/google/fatcat/var/francka: Reduce generic reset delay to 10ms
* 60916d0f10 mb/trulo/var/uldrenite: Support different ISH UART mappings
* 3fe4b00966 mb/trulo/var/uldrenite: Swap ISH UART from UART1 to UART0
* 407c7d0da3 Documentation: Add Device Operations
* 20d7eaeb0f Documentation: Add chip operations
* bf38f8eddc vc/intel/fsp2: Drop superfluous header for Raptor Lake S
* eec228987e mb/intel/coffelake_rvp: Make use of chipset devicetree
* c9f4cfa463 AUTHORS: Update list to 25.03
* da5101fde4 cpu/x86/smm: Drop unused label
* 9154070320 mb/asus/h61-series: Add H61M-A/USB3
* e8c724fe1a mb/lenovo/m900_tiny: Update VBT to build 1037 with Kaby Lake gfx support
* 21ca6701ff mb/google/{drallion,hatch,sarien}: Skip adding DTT/TCPU to SSDT
* 5bf88a44e9 drivers/smmstore: Support 64-bit MMIO addresses
* 2706ce0266 mb/intel/ptlrvp: Add GPIO support for T4 LP5 board
* 40b62ff6c4 mb/intel/ptlrvp: Add memory configuration support for T4 LP5 board
* 7f826fddc5 mb/intel/ptlrvp: Compile variant.c in ramstage for ptlrvp
* 0ca46ac0d2 soc/intel/pantherlake: Enable coreboot native logo rendering
* 210371e25b mainboard/google/fatcat: Configure middle logo vertical alignment
* e446c1f917 drivers/intel/fsp2_0: Introduce coreboot native logo rendering
* 2f23896299 soc/intel/intelblocks/cfg: Add splash screen vertical alignment options
* 78d15d9a12 drivers/intel/fsp2_0: Add Kconfig to select FSP for BMP rendering
* 5f941893ef cpu/x86/mtrr: Introduce mtrrlib with common MTRR helper functions
* e180971560 drivers/intel/fsp2_0: Move graphics info struct/GUID to FSP header
* 18b4349422 mb/var/uldrenite: Fix fw_config_gpio_padbased_override not being called
* a6be271e63 arch/x86: Unify GDT entries
* 1e7e4e943f soc/intel/tigerlake: Hook up S0ix setting to option API
* ba4b26c4fc soc/intel/meteorlake: Hook up S0ix setting to option API
* 514ad949e3 soc/intel/jasperlake: Hook up S0ix setting to option API
* 55afbe250d soc/intel/elkhartlake: Hook up S0ix setting to option API
* 3cc728110d soc/intel/alderlake: Hook up S0ix setting to option API
* 245cba6795 cpu/x86/smm: Add support for exception handling
* 2e27ceed67 mb/google/volteer/var/elemi: Check FP presence against SKU ID
* 663dbd462a soc/amd/phoenix: Remove outdated TODO comments
* b1b8b0e8e1 mb/starlabs/starbook/tgl: Reconfigure PCH Strap GPIOs
* 36ac6226ff util/autoport: Add function to create empty files
* f8071719e7 soc/intel/ptl: Add Wildcat Lake platform reporting
* db4162adce soc/intel/ptl: Add Wildcat Lake PCIe Device details
* 1baf0baf58 soc/intel/ptl: Add Wildcat Lake SoC device tree
* 2fc246cd2d mb/google/ocelot: Remove unused devices from devicetree
* 3278551f8c drivers/intel/fsp2_0: Include coreboot_tables.h in fsp_gop_blt.h
* 18172b6009 mb/google/bluey: Add SoundWire amp and SD card GPIOs to lb_gpios
* 80901a4494 mb/google/bluey: Add GPIOs for Soundwire, Display, and SD Card
* 1015d4332f mainboard/google/bluey: Add fingerprint sensor GPIO entries
* a85b9a21b2 mb/intel/ptlrvp: Add support for DDR5 configuration
* c1bcb43f7c cbgfx: Prevent divide-by-zero edge case in Lanczos kernel
* 565c768c20 soc/intel/alderlake: only add wifi Mitigation if DRIVERS_WIFI_GENERIC
* ac948173ad mb/starlabs/starfighter/rpl: Add ramstage.c to makefile
* f1509a467c mb/starlabs/starfighter: Add CFR option to use native panel resolution
* 3593314cf5 mb/starlabs/starlite_adl: Add CFR option to use native panel resolution
* d13afbbbca mb/starlabs/starbook: Add CFR option to use native panel resolution
* 8fa84d9111 mb/starlabs/*: Add CFR entry for Bluetooth RTD3
* d2b0220a38 allocator_v4: Re-enable top-down allocation for edk2
* 4d7b56cdaa soc/intel/cmn/cse_lite: Fix handling of soft disable state
* 33b3269d91 soc/intel/cmn/cse: Add function to check if ME state is M3_NO_UMA
* 30a4fec86e mb/google/fatcat/var/kinmen: Generate SPD ID for Micron modules
* cf5696834b soc/intel/ptl: Refactor Panther Lake SoC configuration
* e99532d99b soc/mediatek/common: Update SPMI calibration process
* f83fb11e5f soc/mediatek/mt8189: Add CPU segment ID support
* 7b27b1ca99 soc/mediatek/mt8189: Fix incorrect GPIO register address
* f2cf732997 libpayload: usbmsc: Correctly deal with disks larger than 2TB
* 173c5d0aad src/arch/x86/c_start: Delete duplicated code masking stack pointer
* 1166f9be0d include/console: Add CFR object for setting the logging level
* 0f0d5fc725 soc/intel/apollolake/acpi: Add function to get PCIe BAR
* 5d3664ce3b mb/starlabs/starbook/adl_n: Update VBT to fix HDMI output
* 4b765fdd98 mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC
* f63c3bb297 soc/intel/cannonlake: Hook up DPTF device to devicetree
* b7d59185ab soc/intel/common/dtt: Add Kconfig to skip SSDT generation
* 094f75162f cpu/x86/64bit/pt: Fix integer arithmethic in assembly
* bbd8f0aef8 soc/intel/ptl: Refactoring NUM_COMx_GRP_PADS calculation
* cf47edb173 ec/google/wilco/acpi: Add UCSI port data
* 89e915e981 ec/google/wilco/acpi: Fix S3/S4 support
* 4a89d1b77d soc/intel/ptl: Add GPIO ACPI support for Wildcat Lake SoC
* a4a2cdeb17 soc/intel/ptl: Add GPIOs for Wildcat Lake SoC
* 2ce567f1d0 soc/intel/common/block/cse: Prevent HECI commands when flash descriptor override is set
* 9660279966 drivers/usb/intel_bluetooth: Hook RTD3 up to the option API
* e2705d93d8 soc/intel/pantherlake: Reduce IGD stolen memory size from 128MB to 64MB
* 9f98a2a78a mb/asus/p8z77-v_le_plus: Use additional rt8168 MAC programming
* 2b598a9472 drivers/net/r8168.c: Add option to program MAC address to ERI registers
* 4b871c6314 ec/intel: read board ID one time from EC per stage
* 08722cd9f9 mb/google/dedede/var/beadrix: Add Ziliatech part to RAM ID table
* c0920396d0 mb/google/bluey: Make GSC_AP_INT GPIO configurable via Kconfig
* 2e387e13f5 mb/google/fatcat/var/francka: Conditionally init HDA
* e545494f6d mb/google/fatcat/var/fatcat: Conditionally init ALC256 HDA
* 03d2ef67d7 soc/intel/cmn/hda: Introduce mainboard hook for HDA initialization
* 85c65b0c20 mb/google/fatcat: Remove NPK device from fatcat and francka variants
* 92955fbfa6 mb/google/trulo/var/uldrenite: Configure GPP_E9 as NF2
* aafcb01ec4 mb/intel/ptlrvp: Synchronize codebase with fatcat
* effd1ffdad mb/google/ocelot: Update Ocelot board
* 1044f03878 payloads/external/edk2: Set StatusD register to work around failing AMD boot
* 2170ad0c60 Documentation/lib/timestamp.md: Reformat to 72 characters per line
* 22118a137b mb/google/fatcat/var/kinmen: Add memory settings
* 54c87dbed0 mb/google/trulo/var/uldrenite: Update DPTF parameters
* 9ef62ad64c mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations
* 7c965f9df0 MAINTAINERS: Add Nick, Avi, and Pranava for new google/ocelot entry
* d2e698056e mb/google/bluey: Set correct Kconfig defaults for peripherals
* 34d6bc8784 soc/qualcomm/x1p42100: Set correct Kconfig defaults for peripherals
* 2201f57493 soc/qualcomm/x1p42100: Add QUP Serial Engine (SE) entries
* 6a503fe5a4 mb/google/var/uldrenite: Configure GPP_A16 as NF4
* c2c95fbd24 sb/intel/lynxpoint: Add CFR objects for existing options
* 96fd20c5e0 soc/intel/broadwell: Add CFR objects for existing options
* ce6f7820f4 ec/google/chromeec: Increase EC status timeout to 30 seconds
* 17347eedc3 soc/intel/cannonlake: Add CFR objects for existing options
* ad704e0500 soc/intel/cannonlake: Hook up the VT-d setting to option API
* 7f8d1f2086 mb/google/nissa/var/pujjoniru: Support x32 memory configuration
* fe881c990c mb/google/brya: Create pujjocento variant
* 7da36ad79a mb/google/bluey: Add initial support for Bluey
* 57d7957e3c soc/qualcomm/x1p42100: Add initial SoC skeleton for X1P-42-100
* c82f5fe133 soc/amd/glinda: Select SOC_FILL_CPU_CACHE_INFO
* ee76692571 payload/external/edk2: Add Kconfig to support use of PCIe OpROMs
* fb3f025ea6 soc/amd/common/cpu/noncar: Add SMBIOS helper
* 36f01c3481 mb/google/fatcat/var/felino: Add Write Protect GPIO to cros_gpios
* 934fcfb6a0 soc/mediatek/mt8189: Add I2C driver support
* b3bdffa475 soc/mediatek/common: Move I2C functions to common code
* 1e0941c295 mb/google/ocelot: Select Wildcat Lake(WCL) SoC config
* b249275e3d mb/amd/crater: Fix some ec defines
* 443f514365 mb/amd/crater: Add touchscreen support
* 4e55225f2c mb/amd/crater: Add missing dxio descriptors
* 608db150f1 smmrelocate: Drop unused parameter
* 157b7ae778 payloads/edk2: Update default branch for MrChromebox repo to 2025-02
* 76a1e81b10 mb/starlabs/*: Unify Sleep S3 and S4 GPIO configurations
* fed584e100 soc/intel: Add Wildcat Lake CPU and PCIe device IDs
* 5d7e2b4c0c mb/google/fatcat: Disable VR settings on Panther Lake H SoC
* 8be95806a6 mb/google/ocelot/var/ocelot: update gpios
* 92f9c8a985 mb/google/ocelot: update FW_CONFIG
* 49bf8f94a0 soc/intel/common: Add CFR objects for existing options
* 509b01c3b6 soc/intel/cannonlake: Hook up S0ix setting to option API
* b830fdc2d7 soc/intel/cannonlake: Hook up IGD config to option API
* 5efb54d371 soc/intel/broadwell: Allow ME enable/disable to be set via option
* 42379e7f76 sb/intel/lynxpoint: Allow ME enable/disable via option
* 204aae207d mb/samsung/stumpy: Clean up makefile
* e3d3fc5b4a mb/samsung/stumpy: Use CFR setup menu to manage options
* 936ca8404a drivers/option/cfr: Select EFI variable store when edk2 payload used
* 20ceed1929 drivers/efi/fw_info: Select necessary UDK binding as needed
* c0e3f6d1d2 drivers/efi/variable_store: Select necessary UDK binding as needed
* a899359720 sb/intel/bd82x6x: Add CFR objects for existing options
* ada6b98766 nb/intel/sandybridge: Add CFR objects for existing options
* f14aa06606 soc/intel/skylake: Add CFR objects for existing options
* f51c0bb090 soc/intel/skylake: Hook up IGD config to option API
* 32c78b7e22 soc/intel/skylake: Hook up S0ix setting to option API
* 73b095d5ea mb/starlabs/*: Select DRIVERS_OPTION_CFR_ENABLED
* 4eba4e3f26 superio/ite/it8772f: Program power state after failure
* fbca3e6806 superio/ite/*: Move setting of power state to common code
* 60b414fc13 soc/intel/cannonlake: Drop redundant PcieRpEnable
* ee30558c49 soc/intel/skylake: Drop redundant PcieRpEnable
* 439d7fb7d0 mb/google/brya: Create epic variant
* c4e6050146 mb/google/skywalker: Create variant Obiwan
* 0cc0e6996c drivers/smmstore: allow full flash access for capsule updates
* 7814b8a6be Revert "soc/mediatek/mt8196: Specify MTKLIB_PATH for building BL31"
* 14b66cb01b soc/intel/pantherlake: Add new SoC config for Intel Wildcat Lake(WCL)
* d14ebe3957 mb/google/fatcat/var/felino: Use GPP_C08 for GPIO_PCH_WP
* 6322be7992 sb/intel/bd82x6x/me.h: Add missing definitions
* 2f62dd8a6b mb/google/brya/var/uldrenite: Configure ISH_GP5 GPIO
* 3ce612194c mb/google/rex: Generate RAM IDs
* 430ab9257b spd/lp5: Add SPD for K3KL8L80EM-MGCU
* c7a450ba7d Documentation/mainboard/asrock/imb-1222.md: Update information
* ac7717a7b0 mainboard/asrock/imb-1222: Enable USB3 port in WWAN slot
* eb68ff66eb mb/asrock/imb-1222: Update GPIO config using new intelp2m
* a1210875e9 mb/imb-1222: Update some GPIOs according to new vendor config
* fc8e88da9b drivers/intel/mipi_camera: Rework info print output
* d04d7d80b0 drivers/intel/mipi_camera: Only generate ADR if no HID supplied
* 36c89598a7 mb/erying/tgl: fsp_params: Replace half_populated with statement
* 0307f52cd9 soc/mediatek/mt8196: Move SPM loader functions to common part

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 19:18:50 +01:00
Leah Rowe f6da49b3a7 deguard: bump to rev 0ed3e4f
There really isn't anything functionally different. However,
this means one less patch is needed in lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 17:54:51 +01:00
Leah Rowe 81dc1a7f89 GRUB: Bump to rev a68a7dece, 23 June 2025
NOTE: gfxterm_menu module removed, because of this
change by upstream:

commit ca2a91f43bf6e1df23a07c295534f871ddf2d401
Author: Glenn Washburn <development@efficientek.com>
Date:   Mon May 5 16:11:36 2025 -0500

    tests: Disable gfxterm_menu and cmdline_cat tests

This brings in the following changes from upstream:

* a68a7dece loader/i386/pc/linux: Fix resource leak
* de80acf36 loader/efi/linux: Unload previous Linux kernel/initrd before updating kernel size
* 249db11d8 loader/efi/linux: Correctly terminate load_options member
* f3b339af1 loader/efi/linux: Use sizeof() instead of constant
* c2b2e0dcf loader/efi/linux: Use proper type for len variable
* de4e8e2aa loader/efi/linux: Do not pass excessive size for source string
* 8c8f96664 loader/efi/linux: Remove useless assignment
* 8ebf155af include/grub/charset.h: Update documentation
* 2f2ed28d5 Revert "lzma: Make sure we don't dereference past array"
* 2539ede82 tests/util/grub-shell: Correct netboot and file_filter test failure
* 8c2d4e64f normal/charset: Fix underflow and overflow in loop init
* ba8eadde6 dl: Provide a fake grub_dl_set_persistent() and grub_dl_is_persistent() for the emu target
* 409e72ced util/grub-protect: Correct uninit "err" variable
* 5eca564b1 gnulib: Bring back the fix for resolving unused variable issue
* ac1512b87 gnulib: Add patch to allow GRUB w/GCC-15 compile
* db506b3b8 gnulib/regexec: Fix resource leak
* bba7dd736 gnulib/regcomp: Fix resource leak
* 91cb7ff6b tests/tpm2_key_protector_test: Add tests for SHA-384 PCR bank
* 451e227e5 tpm2_key_protector: Dump the PCR bank for key unsealing
* 11caacdb2 util/grub-protect: Fix the hash algorithm of PCR digest
* ce23919ca build: Add new header files to dist to allow building from tar
* e3b15bafd build: Remove extra_deps.lst from EXTRA_DIST
* 40e261b89 lib/LzmaEnc: Validate "len" before subtracting
* 86e8f2c4b osdep/unix/hostdisk: Fix signed integer overflow
* 438f05581 disk/luks2: Add attempting to decrypt message to align with luks and geli modules
* 20e6d0c4a osdep/linux/getroot: Detect DDF container similar to IMSM
* b71bc0f8b fs/fshelp: Avoid possible NULL pointer deference
* 272ff81cb fs/ntfs: Correct possible infinite loops/hangs
* 8c95307a0 fs/ntfs: Correct possible access violations
* 06914b614 fs/ntfs: Correct attribute vs attribute list validation
* 0e1762c8a fs/ntfs: Correct regression with run list calculation
* be303f8c1 lib/envblk: Ignore empty new lines while parsing env files
* 34bd00ee2 fs/zfs: Fix another memory leak in ZFS code
* ca2a91f43 tests: Disable gfxterm_menu and cmdline_cat tests

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 16:26:49 +01:00
Leah Rowe 5b2661a485 SeaBIOS/default: Bump to rev b686f460, 28 Jun 2025
This brings in the following changes:

* b686f460 sercon: Fix keycodes for F11 and F12
* b52ca86e docs: Note v1.17.0 release
* a6c8e8bb ahci: Fix hangs due to controller reset

The serial console fix is useful to us, as is the AHCI
fix; the latter was previously mitigated by removing
SeaBIOS's AHCI reset patch.

Upstream realised that the AHCI controllers need to have
a timeout on them when resetting them, because they don't
always react immediately to commands.

This makes the AHCI behaviour more correct, in SeaBIOS.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 15:31:48 +01:00
Leah Rowe 248192ad9a ifd/hppro3500: use truncated ME, enlarge BIOS size
i did:

ifdtool -f layout.txt ifd.bin

changed layout.txt to say this:

00000000:00000fff fd
00019000:007fffff bios
00001000:00018fff me
00fff000:00000fff gbe
00fff000:00000fff pd

then i did:

ifdtool -n layout.txt ifd.bin -O ifd.bin

this was done to the ifd for hp 3500 pro, based on
the 96KB size of the truncated me.bin via me_cleaner,
when downloading vendor files in lbmk.

it's the policy of libreboot that me.bin should always
be shrunk, and the BIOS region enlarged.

in the original HP 3500 PRO patch submitted, the ME region
was larger, with region boundaries like this:

00000000:00000fff fd
00400000:007fffff bios
00001000:003fffff me
00fff000:00000fff gbe
00fff000:00000fff pd

In the above example, you see that the BIOS region is 4MB.

In the new setup, BIOS is about 7.9MB.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 04:34:14 +01:00
Leah Rowe 1cd8353082 ifd/hppro3500: unlock regions by default
coreboot already unlocks the regions during build, by default,
anyway, and this was present in the submitter's patch.

however, it's also good to unlock the IFD regions. like so:

ifdtool --unlock ifd.bin -O ifd.bin

this has been done, on the ifd for hp pro 3500

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 04:25:22 +01:00
Leah Rowe 67858207eb ifd/hppro3500: set HAP bit by default
ifdtool --altmedisable 1 ifd.bin -O ifd.bin

always remember to do this, when adding a new
ifd to lbmk. i merged the 3500 port anyway, since
the submitted already used me_cleaner anyway, but
setting the HAP bit is also useful. for example, if
someone was to only flash the BIOS region, which is
possible in this case since the submitter also
didn't truncate the ME region or enlarge the BIOS
region.

in that case, flashing IFD and BIOS is another valid
way to do it, where IFD's HAP bit is set

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 04:22:48 +01:00
Leah Rowe a13772bf31 cb/hppro3500: use seagrub, not grubsea
We want graphics cards to work out of the box. This is
why SeaGRUB is default, on desktops; SeaBIOS also has
better code quality and is less likely to break, so it
provides a nice fallback in case the GRUB payload is ever
buggy during development (this decision was made ever
since the botched May 2024 release)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 04:15:22 +01:00
Leah Rowe 047ddf40d8 Merge pull request 'Add HP Pro 3500 Series' (#350) from JoelLinn/lbmk:feature-port-hppro3500 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/350
2025-07-06 05:10:17 +02:00
Leah Rowe d25aaac9ad lib.sh: remove erroneous break from fx_
it means nothing here. in context, if a non-zero return
is observed, we should not do anything here, which is
already the behaviour anyway, except that "break" means
nothing since we're not in a loop here.

where an error exit should be observed, x_ is used inside
the command given for fx_

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 03:25:35 +01:00
Leah Rowe c46a71138c Libreboot 25.06 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-30 14:08:48 +01:00
Joel Linn 587af4a7b6 Add HP Pro 3500 Series
Everything should work except cpu fan control because ME cleaning breaks PECI.
2025-06-15 15:20:32 +02:00
Leah Rowe b1ef562b76 tree.sh: add sha512 error for check_project_hashes
handle errors on sha512sum - also handle awk errors inside
the mini subshell, and provide overall error handling.

we know that the project.hash file should always exist, and
always be read no matter what; technically, the find command
that proceeds it might not yield any results, but an empty
file would then be produced.

the edge case of an empty file would have lead to an error
beforehand, when configuring the project in function,
configure_project(), so we've already got that covered.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:41:09 +01:00
Leah Rowe 04bee3834d tree.sh: add error check in check_project_hashes()
when reading old_pjhash, we need to error out where a read
error occurs. such an error is unlikely, but could occur under
certain edge cases.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:41:03 +01:00
Leah Rowe 677dfc4d10 tree.sh: more reliable clean in run_make_command
Don't do no-op if it fails; fall back to "clean" instead,
and fail if that fails.

The no-op was there was not all projects have distclean,
but we do intend for them all to be cleaned.

We mitigate further error by only running make-clean if
a makefile exists.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:40:33 +01:00
Leah Rowe 267d4c9034 inject.sh: add missing semicolons
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:39:57 +01:00
Leah Rowe 974bdbb381 vendor.sh: fix bad cbfstool path
i overlooked this one in the previous commit

there is always one.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-27 11:18:18 +01:00
Leah Rowe dc6996252a put coreboot utils in elf/coreboot/TREE
not elf/UTIL/TREE

This way, they are automatically deleted when a tree
has to be re-built.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-27 10:11:42 +01:00
Leah Rowe b77154640d release.sh: use printf to create version files
Don't copy the files directly, because we might be doing
this from a work directory that has no files; in this case,
generic "unknown" variables are used, without generating
any files, so the current logic would produce an error.

However, we do need to create those dot files, because
we then rely on them for building release binaries.

The new logic maintains current behaviour, while fixing
this technical edge-case scenario via mitigation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 18:46:58 +01:00
Leah Rowe dee6997d0c lib.sh: simplify setvars()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:49:55 +01:00
Leah Rowe 79ded40f3d lib.sh: simplify chkvars()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:45:12 +01:00
Leah Rowe 5036a0bc50 mk: simplify main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:33:56 +01:00
Leah Rowe 41308ee924 get.sh: simplify fetch_project()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:26:34 +01:00
Leah Rowe b5867be214 get.sh: simplify try_copy()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:23:06 +01:00
Leah Rowe 495098d6a7 get.sh: tidy up bad_checksum()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:19:06 +01:00
Leah Rowe 671e3aa27b get.sh: simplify fetch_targets()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:11:20 +01:00
Leah Rowe 09b6e91803 general cleanup in get.sh and vendor.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 01:30:33 +01:00
Leah Rowe 18dacd4c22 xbmk: rename xbmklocal/xbmktmp variables
shorten them

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:57:50 +01:00
Leah Rowe e981132c82 get.sh: consolidate printf statements
stick it in git_prep, which both single- and multi-tree
projects will use, when downloading git repositories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:50:06 +01:00
Leah Rowe afc36754b1 get.sh: remove redundant printf in fetch_project
The following execution will result in another printf
that says exactly what is being downloaded.

There is no need to inform the user twice about
what is being downloaded.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:44:57 +01:00
Leah Rowe ffe387ac6b get.sh: remove superfluous command in try_git()
A git-pull is performed immediately after git-fetch.
Git-pull already performs git-fetch as a prerequisite.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:35:38 +01:00
Leah Rowe ba7c49c090 vendor.sh: simplify fetch()
the checks at the end of the function are mostly
superfluous, because bad_checksum() is immediately
called just beforehand, and performs the same checks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:33:36 +01:00
Leah Rowe 30bc3732c3 init.sh: error out if .git/ is a symlink
the current behaviour is a relic from the older lbmk
design, before recent auditing.

the current logic would cause xbmk to continue execution,
going into a child process with .git/ being a symlink.

The .git/ directory should never be a symlink, because
it is extremely error-prone.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 17:01:10 +01:00
Leah Rowe 2493203ee5 get.sh: Properly error out if tmpclone fails
We rely on a non-zero exit on other try_ commands, which
works fine there because we then check the file afterward
and error out accordingly.

For git repositories, we assume that both mirrors are
identical and therefore once we get to the first clone
attempt, we assume that it must succeed.

Therefore, if it does not succeed, we must fail. This fixes
a regression I found in testing, where sometimes a failed
patching attempt would not result in an error exit, and
would therefore result in broken sources being present.

In practise, I always very closely watch the terminal when
testing xbmk, especially when updating project patches, so
we probably didn't introduce any broken sources in practice.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 14:46:33 +01:00
Leah Rowe ad333ae248 tree.sh: Don't auto-run make-oldconfig
This code was introduced to provide fault tolerance,
so that if I forgot to manually update the configs
myself, builds would still succeed, e.g. coreboot
builds.

However, there have been cases in the past where this
introduces settings we don't want, and in general we
do want to know when there is an error in the configs.

The policy should always be: fail early, fail hard.

This also mitigates bugs in U-Boot's build system; for
example, when I last attempted to update the U-Boot
tree for x86, make-oldconfig introduced a lot of junk
settings unrelated, which then introduced code that
would brick the board if you tried it on one, e.g.
it broke booting most Linux kernels via bootflow.

With this change, U-Boot will be easier to handle,
which normally requires manual configuration; the
automated make-oldconfig reconfiguration feature
breaks U-Boot. This will no longer occur, since we
no longer run it manually.

On the other hand, this feature has also prevented
other disastrous bugs in the past, such as when I
forgot to properly set the SPD size on T480; it was
set to 256 bytes, not 512 as is correct. Therefore,
this new design change means I must also be more
vigilant about config changes in project trees.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 14:35:02 +01:00
Leah Rowe 97ce531c34 rom.sh: simplify mkcoreboottar()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 05:03:03 +01:00
Leah Rowe a47e981172 rom.sh: rename mkvendorfiles
it mainly does general tasks, like handling utils
and enabling ccache. the vfiles are a small part.

rename the function accordingly. it is called by
premake, so let's call it corebootpremake.

this change will also make sense when cherry-picked
into cbmk, which does not handle vfiles at all.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 04:46:08 +01:00
Leah Rowe d2e148fdd9 rom.sh: simplify ccache handling for coreboot
we simply do not need to run the make-oldconfig command
at all, and after removing it, the "cook" function seemed
quite redundant so i merged it with mkvendorfiles()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 04:40:30 +01:00
Leah Rowe 8c3f10ba40 rom.sh: simplify u-boot payload handling
define it with a single variable, rather than several.

this allows several checks to be greatly simplified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 03:09:29 +01:00
Leah Rowe 3e28873532 ifd/hp8300usdt: set the HAP bit by default
In practise, coreboot can set this bit at build time.
We also use ME Soft Temporary Disable by default, on
this platform.

We also use me_cleaner by default, so the me.bin file
added to flash only contains the code that would run
with HAP set anyway.

Therefore, this change is of little practical consequence,
but as a friend put it to me, this change is most technically
correct.

And I'm all about technical correctness.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-23 04:52:36 +01:00
Leah Rowe 452aeb6001 coreboot: Remove unused vboot tests
Futility tests enlarge the src tarballs, without much utility.

Uttterly futile.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 14:13:11 +01:00
Leah Rowe 64cc91bca3 coreboot/default: Remove unneeded FSP modules
We only need the Kabylake version. We can safely
remove the other ones, thereby significantly
reducing the size of the lbmk release archive.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 13:48:20 +01:00
Leah Rowe 0216a3104a get.sh: Always update git remotes
Right now, if cache/clone/PROJECT/ already exists,
the logic for pulling new changes doesn't execute,
and neither does the logic for updating remotes.

This is bad when updating revisions, because then
manual updating is required, defeating the purpose
of xbmk's own automation in this regard.

Fix it by only checking the cached download on files,
not Git repositories; the try_git function itself will
already perform this check, before updating remotes
and pulling in new commits from upstream.

The updating only happens when a given target directory
doesn't exist, e.g. src/flashprog/ or src/grub/default/,
so this won't slow down release builds for example.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 12:45:59 +01:00
Leah Rowe 419733d307 get.sh: re-generate remotes every time
that way, when a remote changes in config/, it
will be updated automatically, without user
intervention.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 12:22:07 +01:00
Leah Rowe 231b320e63 release.sh: copy version files to rsrc
Otherwise, an "unknown" version number is created.

This regression was caused by the recent optimisation
that reduces the amount of extra work done by init.sh
on child instances of xbmk.

As a result of those changes, now release.sh has to
do some minor initialisation of its own, such as this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 11:51:31 +01:00
Leah Rowe fc0720184d xbmk: add fake config makefile args to flashprog
also pcsx-redux

this way, commands like "./mk -u" without argument
will not fail. these fake makefile commands do nothing.

otherwise, an error errors because their makefiles
do not define these options.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 11:34:28 +01:00
Leah Rowe f9266601b8 vendor.sh: add colon at the end of a for loop
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 11:27:22 +01:00
Leah Rowe 8e0c6059d1 rom.sh: skip copyps1bios on dry builds
otherwise, ./mk -d (without arguments) will fail.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 01:47:02 +01:00
Leah Rowe a3250d1447 tree.sh: Don't run make-clean on dry runs
Otherwise, ./mk -d (without arguments) fails for GRUB,
which first requires running autoconf to get a Makefile.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 01:17:27 +01:00
Leah Rowe 24b8e633e0 GRUB: Update to revision 73d1c959e (14 March 2025)
This brings in several changes from upstream:

* 73d1c959e cryptocheck: Add --quiet option
* dbc0eb5bd disk/cryptodisk: Wipe the passphrase from memory
* 301b4ef25 disk/cryptodisk: Add the "erase secrets" function
* 23ec4535f docs: Document available crypto disks checks
* 10d778c4b commands/search: Add the diskfilter support
* 7a584fbde disk/diskfilter: Introduce the "cryptocheck" command
* ed691c0e0 commands/search: Introduce the --cryptodisk-only argument
* c448f511e kern/rescue_reader: Block the rescue mode until the CLI authentication
* 4abac0ad5 fs/xfs: Fix large extent counters incompat feature support

This commit is of particular interest:

* dbc0eb5bd disk/cryptodisk: Wipe the passphrase from memory

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-21 13:34:18 +01:00
Leah Rowe f6b7782283 Revert "vendor.sh: optimise find_me()"
This reverts commit fb7aaa78bb.

it caused a few issues. will re-do later

the old code isn't really broken, just inefficient, because
several files are scanned twice, but in practise the overhead
isn't that great

The error occurs sometimes, when bruteforcing me.bin:

ERROR ./mk: Unhandled error for: mv /home/user/lbmk/tmp/me.bin /home/user/lbmk/cache/tmpdl/check

This revert should fix the issue, for now.
2025-05-20 20:14:09 +01:00
Leah Rowe fb7aaa78bb vendor.sh: optimise find_me()
i'm adding characters to 7ztest, which isn't being passed
on through because everything runs in subshells; the next
pass would default back to the original string, so a given
file may be checked multiple times.

fix this by mitigation; use the random string from mktemp
as a suffix instead.

in practice, this has not affected performance much, but it
will nevertheless avoid unnecessary work by xbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-20 02:58:33 +01:00
Leah Rowe 903f78bf08 get.sh: add missing check in fetch_project()
we check the main url, but not backup urls.

this patch fixes that oversight.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 23:13:29 +01:00
Leah Rowe f15bb8153a get.sh: stricter URL check in xbmkget()
don't skip if the URL is empty. throw an error instead.

i decree that all links must be properly initialised, because
that is the design of lbmk. where only one link is provided,
such as in a local copy operation, the second would succeed no
better than the first so two identical paths are given.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 23:09:37 +01:00
Leah Rowe cdc0fb49e1 get.sh: make xbmkget() easier to understand
the intent once again is that this for loop shall
return, with zero status, if success is observed.

otherwise, the loop breaks and an error is thrown.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 23:07:01 +01:00
Leah Rowe 620c1dd6fa get.sh: Make xbmkget err on exiting the loop check
The idea in this function is that if a file or repo is
successfully handled, a return will be performed from the
loop.

If the loop exits for any reason, an error is thrown. The
current code is probably fine, but I can forsee future
modifications possibly causing bugs here.

Make it unambiguous, by always throwing an error if execution
reaches the end of the function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 22:59:20 +01:00
Leah Rowe 900da04efa tree.sh: fix up copy_elf(), bad for loop
Because of how sh works, having just the [] line causes
sh to exit, annoyingly without an error message, but it
does cause a non-zero exit.

This bug will have already been triggering, before I added
the recent error handling on files for this for loop.

also do it to the other loop in lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 19:58:55 +01:00
Leah Rowe 8aaf404dde lib.sh: Use while, not for, to process arguments
This is more reliable against globbing, in context of for.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 19:29:59 +01:00
Leah Rowe d9c64b2675 xbmk: stricter handling of files on while loops
i overlooked these!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 19:24:43 +01:00
Leah Rowe b25a487643 init.sh: looser XBMK_THREADS validation
on child processes, we can simply correct it.

we currently provide an error message, but this is silly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 18:53:22 +01:00
Leah Rowe 769a97aed5 init.sh: Hardcode XBMK_CACHE for integrity
I never really intended for this to be configurable,
but the cache directory is also used during release
builds.

There's too much that can go wrong, letting the user
decide where their cache is. Simplify it by hardcoding.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 18:50:06 +01:00
Leah Rowe 265ec0b767 dependencies/debian: add libx86
already present on a few other config files, e.g. arch

i noticed on debian-experimental that i needed to explicitly
install it, whereas it was implicitly installed on debian 12

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 17:40:44 +01:00
Leah Rowe 2702a43a86 init.sh: merge xbmk_lock() with xbmk_set_env()
it's just two lines, and we want much more granular
control of where the lock is enforced. it should be
JUST after confirming that the instance is a parent.

it is at this moment that we should bail if a lock
file exists, because this signals that another instance
of xbmk is running.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:32:24 +01:00
Leah Rowe fc4006ce87 init.sh: move xbmk_set_version
it's called before set_pyver, so move it above that

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:29:51 +01:00
Leah Rowe 962902a1c4 init.sh: set pyver from set_env
it's related to this function, no point calling from main

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:28:31 +01:00
Leah Rowe 158c56072c init.sh: merge xbmk_mkdirs with set_env
it's just two lines, and they relate.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:25:37 +01:00
Leah Rowe 5f022acbf4 init.sh: check version/versiondate once read
once again, we are being stricter in child instances.

we must ensure that these variables are set by xbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:10:22 +01:00
Leah Rowe 485a60e2f6 init.sh: error if version not read
we no longer rely on the .git version being
read by child instances, so we MUST ensure
that it is being read.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:08:49 +01:00
Leah Rowe 99f09f25ef init.sh: only update version files on parent
don't update them on child instances, since it's a waste
of time; the lock file prevents further execution, so we
are just wasting time writing to disk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:03:09 +01:00
Leah Rowe 94437278dc init.sh: simplify unknown version creation
we don't need to read or write a file at all, in that case.
we only then need to generate one if running ./mk release.

the scenario in which no .git and no version files exist
is when someone grabs the build system from a snapshot
generated by e.g. forgejo instances. it's ill advised, so
we advise against it, but it is mitigated in code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 12:54:31 +01:00
Leah Rowe 6b603b9fbf init.sh: only set xbmk version on parent instance
On child instances, we need only read.

Apply the principle of least privilege.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 12:07:10 +01:00
Leah Rowe ac36ea7f95 init.sh: initialise variables AFTER path
That way, unnecessary work is avoided on child instances.

Of course, the current check assumes that TMPDIR wasn't
already set by a wily user before running lbmk, but then
those sorts of users probably know what they're doing.

If they don't know, they will soon find out. Therefore, I
have added additional checks on child instances, preventing
the build system from running if XBMK_CACHE is not set; if
it isn't, then that could very easy lead to certain system
files being overwritten.

The user must never know what happens if XBMK_CACHE is unset.
We simply will not allow it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 12:02:51 +01:00
Leah Rowe 484afcb919 init.sh: merge create_pathdirs with set_pyver
all this function does now is create the python symlink,
based on work that was already performed in set_pyver

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:40:58 +01:00
Leah Rowe d0bee6b4eb init.sh: Set python version only on parent
Do it after the creation of xbmkpath.

This avoids performing an unnecessary check, since
PATH will have already been corrected for child
instances; Python will already be correct there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:38:11 +01:00
Leah Rowe 4aa69a7d1f init.sh: remove useless command
we mkdir -p xbmklocal, only to remkdir it immediately
afterward, which is the intended behaviour; on parent
instances, xbmklocal is to be re-created fresh.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:30:11 +01:00
Leah Rowe 36ffe6ef50 init.sh: remove useless comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:29:54 +01:00
Leah Rowe 0343081d90 init.sh: xbmk_create_tmpdir to xbmk_mkdirs
this function now simply creates directories that lbmk
will use, rather than creating specific directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:28:57 +01:00
Leah Rowe c75bc0449d init.sh: move gnupath creation to create_tmpdir
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:28:15 +01:00
Leah Rowe 253aa81a3f init.sh: move PATH init to set_env
we must only set this in the parent instance, not
child instances. this prevents the variable from
being over-populated with repeated entries.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:26:28 +01:00
Leah Rowe e05a18d351 init.sh: check the lock file BEFORE git init
this way, initialisation will not be performed erroneously
while another parent instance of lbmk is running.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:21:30 +01:00
Leah Rowe cde3b7051e init.sh: return from child in set_env instead
This is earlier than the current check, thus preventing
the initialisation of a git repository and/or the recreation
of xbmktmp and xbmklocal by erroneous parent executions of lbmk
while another parent is running - the latter of which could have
caused a massively unpredictable build failure, so this is also
a pre-emptive bug fix, fixing all kinds of weird bugs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:18:45 +01:00
Leah Rowe 7ec9ee4228 inject.sh: shorten the nukemode variable name
just call it "nuke". this is what tells whether to remove
vendor files from an archive.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:12:20 +01:00
Leah Rowe b48eb161e4 vendor.sh: simplify mksha512sum()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:10:57 +01:00
Leah Rowe ac609d5aae vendor.sh: Remove _dest if it's bad
Also, provide more ample warning to the user

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 10:59:16 +01:00
Leah Rowe a3e1ed9823 release.sh: rename relsrc to rsrc
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 10:51:03 +01:00
Leah Rowe 44df3b2bff release.sh: tidy up nuke()
i wasn't ok having that variable initialisation and
then the commands on the same line. it looks messy.

having the commands on a separate line makes the code nice
to read, so let's separate them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 10:33:23 +01:00
Leah Rowe 3c58181f69 get.sh: remove useless message
the user doesn't care where the temporary git repo is

git shows that information anyway, in the git clone command

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 16:53:23 +01:00
Leah Rowe 01a0217c1e get.sh: simplify bad_checksum()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 16:51:12 +01:00
Leah Rowe 4ca57943d7 release.sh: simplify nuke() EVEN MORE, yet again
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 16:03:08 +01:00
Leah Rowe 47a3982bbe release.sh: use x_ on find command for nuke()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 15:49:24 +01:00
Leah Rowe 6dc71cc024 release.sh: simplify nuke() EVEN MORE
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 15:38:20 +01:00
Leah Rowe 05c07f7401 get.sh: move nuke() to release.sh
we really only need it there, because the context is
for release archives. normal use of the git repository
doesn't matter in the context of deletions, because that
will not be distributed. only the result of ./mk release
will be distributed.

the builds produced will not change as a result of this,
for people using the normal git repository, because the
files in question are never used anyway, in our configs.

this is being done to make working on local repos easier.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 15:20:02 +01:00
Leah Rowe 587d245caf release.sh: simplify prep_release_bin()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 13:17:09 +01:00
Leah Rowe 136bd66c28 mrc.sh: merge extract_mrc with extract_shellball
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 13:00:17 +01:00
Leah Rowe dbe109d7b5 release.sh: don't move src/docs/
otherwise, ./mk -b (without argument) will fail, on release
archives. also, perhaps i should add an mkhelper to build it?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 12:43:25 +01:00
Leah Rowe 840d6a1d27 get.sh: FURTHER simplify nuke()
this is getting almost comical now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 12:17:36 +01:00
Leah Rowe d2564fd945 get.sh: simplify tmpclone()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 11:08:06 +01:00
Leah Rowe 6dea381614 get.sh: fix bad mkdir command
this is the mkdir call that createsn the directory where
a cached git repository is moved to, during creation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 09:46:54 +01:00
Leah Rowe 6a2ed9428b vendor.sh: Fix broken KBC1126 insertion
On release archives, I overlooked the previous change to
downloads, during the recent implementation of extra safety
checks. I previously checked there whether the variable named
CONFIG_KBC1126_FIRMWARE was defined, and grabbed both; now I
check CONFIG_KBC1126_FW1 and CONFIG_KBC1126_FW2 separately,
grabbing each file separately.

This patch replicates that change for insertions. Otherwise,
hash verification on ROM images will fail, when running the
inject script on release images.

Downloading was being done, reliably, and the extracted files
were correct, so there was no danger if the user was building
from source and flashing that way.

However, checksum verification on full images failed when
inserting into archives. This is not because the files were
wrong; they were *correct*. However, the EC firmware was not
being inserted *at all* on HP EliteBooks, because of this
oversight. The check is now based on whether the paths to
the files themselves are defined, not whether EC firmware
is enabled in the coreboot config; the latter is implied.

With this patch, vendor file insertion once again works
perfectly, without error, on every board. There was no real
danger for users, just a minor inconvenience. Sorry!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-16 09:44:34 +01:00
Leah Rowe 4313b474a5 vendor.sh: additional safety check
the exit from mkdst can also be non-zero if mv or cp
failed, but there's no way to handle that reliably.

therefore, the checksum verification should be done
one final time, to compensate.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-16 07:03:08 +01:00
Leah Rowe d668f3a352 vendor.sh: Properly verify SHA512SUM on extraction
I currently check the downloaded files e.g. .exe file, but
then I don't check - or even define - sha512sums for the
files extracted from them e.g. me.bin

This patch fixes that. It also caches the hashed files, so
that extraction is faster on a re-run - this makes release
builds go faster, when running ./mk release

If a checksum is not defined, i.e. blank, then a warning is
given, telling you to check a specific directory. This way,
when adding new vendor files, you can add it first without
specifying the checksum, e.g. me.bin checksum. Then you can
manually inspect the files that were extracted, and define it,
then test again.

In a given pkg.cfg for config/vendor, the following variables
are now available for use:

FSPM_bin_hash for fsp m module
FSPS_bin_hash for fsp s module
EC_FW1_hash for KBC1126 EC firmware (1st file)
EC_FW2_hash for KBC1126 EC firmware (2nd file)
ME_bin_hash for me.bin
MRC_bin_hash for mrc.bin (broadwell boards)
REF_bin_hash for refcode (broadwell boards)
SCH5545EC_bin_hash for sch5545 firmware (Dell Precision T1650)
TBFW_bin_hash for Lenovo ThunderBolt firmware (e.g. T480/T480s)
E6400_VGA_bin_hash for Dell E6400 Nvidia VGA ROM

In practise, most people use release archives, and the
inject script, so I knew those were reliable, because the ROM
images were hashed prior to removing files. This patch benefits
people using lbmk.git directly, without using release files,
because now they know they have a valid file e.g. me.bin

Previously, only the download was checked, not the extracted
files, which meant that the only thing preventing a brick was
the code not being buggy. Any number of bugs could pop up in
the future, so this new level of integrity will protect against
such a scenario, and provide early warning prompting bug fixes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-16 05:39:18 +01:00
Leah Rowe a191d22bd6 get.sh: add missing eval to dx_ in nuke()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-15 02:41:04 +01:00
Leah Rowe c8813c9a14 properly exit 1 when calling fx_
in a few places, we use the presence of a file found
by fx_ to cause an exit, but the command that runs
looks something like:

exit 1 "string"

this yields an error, and a non-zero exit, because of
too many arguments to "exit", but we wanted a non-zero
exit anyway.

nevertheless, this is incorrect.

to fix it, eval is used instead. if the never-going-to-exist
condition one day exists where exit 1 actually returns, not,
you know, exits, we will use err instead, with the string
as argument.

this should be fine. it's a bit hacky, but so is fx_, and
it works. fx_ is used in several places to keep the sloccount
down, providing a common way to perform while loops on the
output of a command; that is its only purpose..

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-15 02:25:02 +01:00
Leah Rowe 208dfc89bd get.sh: simplify nuke()
more specifically, re-write it so that it can be called with fx_

this means that the single-tree check for nuke.list can be made
much simpler

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-15 02:12:04 +01:00
Leah Rowe 46f42291d3 get.sh: fix broken printf statement
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 18:06:29 +01:00
Leah Rowe f29aa9c8d5 get.sh: use subshells on try_ functions
This way, we can use x_ which will then print the command
that failed, if we need to debug future errors.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 17:03:32 +01:00
Leah Rowe e62886deda get.sh: simplify try_copy()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:59:59 +01:00
Leah Rowe d9ed03f9ea get.sh submodules: Don't delete files recursively
I overlooked this in a previous patch. It doesn't really
matter, since we're operating on a file anyway, but it's
not correct.

Files should have rm -f on them, not rm -Rf, for deletion.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:52:33 +01:00
Leah Rowe 8d5475ed5b get.sh: simplify fetch_submodules() config check
We already do what the old code does in setcfg, by
virtue of the fact that the st variable is later
checked, after loading this config conditionally,
where the st variable is otherwise blank.

We can avoid the unnecessary work after loading
the config, by returning if the config is absent.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:48:25 +01:00
Leah Rowe 21867b7d80 get.sh: simplify fetch_submodules()
We are calling xbmkget in the same way, whether it's
a subfile or subrepo.

Rename these variables to subcurl and subgit, so that we
can call xbmkget unconditionally.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:39:51 +01:00
Leah Rowe e9fe5a74a2 get.sh: fix caching of crossgcc tarballs
they were always re-downloading every time.

i've basically re-written most of xbmkget.

there was some erroneous conditions under which
it wrongly deleted the cached file, resulting in
it being downloaded again.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:28:29 +01:00
Leah Rowe 6089716f07 release.sh: Don't run prep_release with fx_
The result of the printf statement is sorted, making
it do binaries first, which results in a lot of junk
files then being present inside the source archive.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 22:17:37 +01:00
Leah Rowe b04c86e574 git.sh: rename to get.sh
it now handles more than just git, and i forsee
it handling even more in the future, e.g. rsync,
ftp, bittorrent.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 22:00:28 +01:00
Leah Rowe 3c23ff4fa1 git.sh: Only create destination repo on success
Don't leave a broken cache laying around, which would
otherwise break lbmk for the user.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 21:57:34 +01:00
Leah Rowe ed8a33d6fb git.sh: cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 20:47:41 +01:00
Leah Rowe 1ca26c5d23 git.sh: Re-implement redundant git downloads
And this time it works.

I'm now calling xbmkget() which in turn calls tmpclone(),
instead of me calling tmpclone() directly.

The git-pull is done on both remotes, regardless of whether
the first succeeds. This way, if I forgot to update a mirror,
downloads would probably still work.

This also fixes an issue people were having, for example where
the gnulib repository of GRUB was always being downloaded
every time.

I'm using a new directory, XBMK_CACHE/clone, instead
of XBMK_CACHE/repo (which I used before), in case people
still have the old caches from before.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 20:25:37 +01:00
Leah Rowe e38805a944 rom.sh: reduce indendation in check_coreboot_utils
call it via fx_, instead of using a for loop

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 21:32:07 +01:00
Leah Rowe 6bf24221e6 release.sh: simplify release()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 21:11:34 +01:00
Leah Rowe 66f7ecdb2d release.sh: clean up the vdir after release
do this after moving the version directory within it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 21:04:48 +01:00
Leah Rowe d4c0479093 release.sh: remove src_dirname variable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 20:25:35 +01:00
Leah Rowe 6d3a6347c3 release.sh: build in tmp directory first
don't move to the real directory until the work
is done.

that way, a re-try can be done, while analysing
the old files. it is created based on the tmpdir,
under XBMK_CACHE/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 20:23:41 +01:00
Leah Rowe a0105e1ab4 release.sh: remove unnecessary mkdir command
the following git clone command creates that directory

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 20:07:50 +01:00
Leah Rowe f4871da9bc release.sh: split up build_release()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 19:49:50 +01:00
Leah Rowe c85aff5c54 release.sh: delete tmp/cache from the tarball
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 19:29:58 +01:00
Leah Rowe 92954eeb38 lib.sh: remove rmgit()
We don't need to call it from git.sh, because it's
only being done when building a release anyway,
and we already run rmgit when doing a release.

The function itself is only two simple fx_ calls,
so we can just do that from build_release().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 19:20:50 +01:00
Leah Rowe 05b5914b35 lib.sh: remove mk()
i don't need it. i can use fx_ instead, on functions
that previously called mk().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 18:05:32 +01:00
Leah Rowe c9696e2333 lib.sh: move xbmkget() to git.sh
in cbmk, it's only used from there.

in lbmk, it's also used from vendor.sh.

however, i plan to further expand git.sh at
some point, tidying it up so that git cloning
is also done from xbmkget, with dlop=git and
git.sh would then be renamed to get.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 16:30:05 +01:00
Leah Rowe 23913bb8d2 lib.sh: move mksha512sum() to vendor.sh
this is unused in cbmk.

it's only used from vendor.sh.

therefore, lbmk shall have it in vendor.sh.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 16:20:34 +01:00
Leah Rowe 80f0562e8d lib.sh: split up try_file()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:44:31 +01:00
Leah Rowe 89cd828e87 lib.sh: move _ua to try_file()
it's only used there

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:32:50 +01:00
Leah Rowe 308a9ab1e1 mrc.sh: minor cleanup
group the cbfs command to the extract command, since they
are related. this makes it clearer that the following
command to extract refcode is unrelated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:06:25 +01:00
Leah Rowe 40163dcfa4 mrc.sh: update copyright year to include 2025
I've made several modifications to the file, this year.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:05:21 +01:00
Leah Rowe ef800b652c inject.sh: remove the hashfiles variable
we only use it once, and it's a trivial string

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:52:27 +01:00
Leah Rowe 311ae2f8df inject.sh: define xchanged here instead
this is used here, and also needed in cbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:49:14 +01:00
Leah Rowe 76f81697e6 vendor.sh: remove check_vcfg()
We don't need it. The vfile variable is only used in
one place, and only once, for use with setcfg.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:47:43 +01:00
Leah Rowe 97d4d020d9 vendor.sh: simplify getvfile()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:30:27 +01:00
Leah Rowe 57f896ac01 vendor.sh: simplify setvfile()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:23:32 +01:00
Leah Rowe 3879f6c4d8 lib.sh: use fx_ in rmgit()
with fx_, i have more much granular control over
how errors are handled.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 13:21:59 +01:00
Leah Rowe 0911a5a5ae lib.sh: split up xbmkget()
it was too complicated. most of the logic has been moved
to a new function, try_file()

the for loop is handled by xbmkget(), whereas each try
is now handled in try_file()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 13:16:10 +01:00
Leah Rowe a449afb287 inject.sh: only compile nvmutil if needed
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:56:28 +01:00
Leah Rowe 2bbf2ae80b inject.sh: simplified serprog check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:52:47 +01:00
Leah Rowe 9c27b7437c vendor.sh: tidy up variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:43:34 +01:00
Leah Rowe 0cc816167b vendor.sh: split up setvfile()
split the actual bootstrapping to getvfile()

setvfile only sets the config, but then it will
call getvfile() to act on that config.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:39:01 +01:00
Leah Rowe 7d90d43425 remove another confusing message
the current message says the file name, and implies that
the given file has already been updated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:51:38 +01:00
Leah Rowe a0c436ad4b inject.sh: Remove confusing path on tar creation
The path is wrong. The correct path is printed afterward.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:48:38 +01:00
Leah Rowe dcfd3e632e inject.sh: re-add mac address confirmation
it just makes the script more user-friendly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:23:46 +01:00
Leah Rowe e5af201060 inject.sh: further cleanup for vendor.sh
i moved out more code to vendor.sh, to reduce the
amount of lbmk-only code on inject.sh

this should reduce the number of merge conflicts
even further, when cherry picking from lbmk to cbmk.

in particular, vendor file insertion is now handled
entirely through the "setvfile" function, instead
of from inject.sh, which seems counterintuitive,
but remember that inject.sh also does MAC addresses.

therefore, the inject.sh script is now primarily for
inserting MAC addresses, and handles vendor downloads
in a slightly more convoluted way, but still easy
enough to understand if you read it a bit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:06:41 +01:00
Leah Rowe 0aa99f4bf8 tree.sh: only create elfdir in copy_elf()
otherwise, we create empty directories where build.list
doesn't exist, like on coreboot.

we already create a directory when needed, when actually
copying elf files, so let's just leave it at that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 17:58:22 +01:00
Leah Rowe a8e374020c tree.sh: simplified srcdir check on make-clean
this is the check that ksips a given target if the tree
directory does not exist, on the clean command.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 17:19:00 +01:00
Leah Rowe 0f931b508a inject.sh: split to vendor.sh the download parts
to the extent feasible, keep lbmk-specific parts on
inject.sh to a minimum. this will later be used to
re-sync cbmk's inject.sh with lbmk's, because cbmk's
one doesn't handle vendor files.

the way this is designed now, with this patch, will
make cherry-picking lbmk to cbmk easier in the future,
when keeping this part of cbmk in sync with lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 13:03:16 +01:00
Leah Rowe 3554b5aad9 inject.sh: split up the inject functions
generally go for a more linear function order, and
split up any functions.

the objective is to have functions only suitable to
libreboot be separate. more splitting will be done,
and eventually the vendor-download functions will be
split into a new file, as will several other functions.

this is being done as part of an effort to bring the
libreboot and canoeboot versions of inject.sh in sync,
so that from now on, cherry picking between the two
projects will produce fewer merge conflicts and require
a lesser amount of post-merge maintenance.

some other minor cleanup has also been done; for example,
the "need_files" variable is redundant and was removed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 10:45:48 +01:00
Leah Rowe 81dbde7e09 lbmk: use x_ instead of err, where appropriate
many places in lbmk used err, because older versions
of x_ did not handle globbing properly.

however, use of x_ is preferable on trivial commands.

the only time err() should be called is what it has
to be, when x_ can't work, or when a more useful error
message is needed, for context.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 20:54:23 +01:00
Leah Rowe 14d46abced mrc.sh: operate on refcode in tmp area first
that way, the Intel GbE device can be enabled there,
and only then would the refcode file be copied.

otherwise, the current behaviour would leave buggy
refcode in place, if the dd command failed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 20:31:00 +01:00
Leah Rowe 6e521c2e1e mrc.sh: fix outdated info in the comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 20:21:58 +01:00
Leah Rowe 23486abef3 inject.sh: use direct comparison for metmp
use of the e function would slow down execution,
and it's mostly unnecessary in this case.

the e function is only needed if we want to confirm
via user message that a file exists. that is not
needed here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 00:26:33 +01:00
Leah Rowe 91220ce183 inject.sh: use subshell to speed up find_me()
the current test allows a further extraction after
running mecleaner, even if me.bin was found.

further, any recursive calls that exit non-ze
don't lot the loop acthually stop, unless we
subshell that too, otherwise fx_ is returned to
return 0 when a given command it runs returns 1,
or more specifically: the for loop in x_ breaks.

this is by design, and there's not much that can
be done, but this patch should pseed up extraction
a little bit, when dealing with intel me files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 00:20:33 +01:00
Leah Rowe ff33ec3352 mk: use zero exit instead, to run trees
that way, with set -u -e, we aren't risking some
buggy sh implementations from causing an error exit
where it shouldn't.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:41:24 +01:00
Leah Rowe c2b627dc6d remove useless comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:36:44 +01:00
Leah Rowe 066402b7e7 mk: remove unnecessary line break
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:35:40 +01:00
Leah Rowe 7012c00ed1 mk: re-split tree logic to include/tree.sh
I really think mk should just be a small stub.

Better to keep everything separate.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:33:49 +01:00
Leah Rowe 50ce1ac9b2 mk: move release functions to idnclude/release.sh
The idea with mk is that it's meant to basically be a
stub for running everything else, while mainly having
the trees logic within it (what was once script/trees).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:28:49 +01:00
Leah Rowe 1ce3e7a3d3 mk: add missing error handli for mk -f
on the release command, that is

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 22:17:35 +01:00
Leah Rowe 0d876622fc git.sh: re-write tmpclone without caching
remove caching for now. it's buggy as hell.

will re-write the caching feature next.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 22:14:43 +01:00
Leah Rowe 454f11bdd7 git.sh: use setvars for fail variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 21:50:17 +01:00
Leah Rowe 6bdb15fd32 git.sh: hard fail if git am fails
similar to the last patch, we must ensure that the
inability to patch will cause a hard exit, regardless
of any redundancy we have for cloning.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 21:36:37 +01:00
Leah Rowe 93d4eca04a git.sh: Hard fail if reset fails
We allow a re-try when cloning fails, to account
for redundancy, but resetfail currently doesn't
cause any error exit at all.

This patch mitigates that bug.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 21:33:17 +01:00
Leah Rowe a3ba8acfac init.sh: Only check XBMK_CACHE if it exists
Otherwise, if it doesn't exist, the current check will
wrongly exit with error status, preventing you from
running the build system at all!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 20:49:49 +01:00
Leah Rowe 021e7615c8 HP 820 G2: Use fam15h cbfstool tree for refcode
We used cbfstool from coreboot 4.13, because it was the
last version to work with the particular format used
for stage files, before the CBFS standard changed in newer
releases of cbfstool.

When I added this board to Libreboot, it was source-only at
first so it didn't matter. I didn't want to do a standalone
cbfstool binary, in case some people decided to use that one
on newer boards, which would cause all sorts of issues.

So I bodged it and just included an import of coreboot 4.13.

Well, the cbfstool from coreboot 4.11, as used for FAM15H
AMD boards, is compatible. I checked the code diff between
the two, and there is no meaningful difference.

I've tested this, and it works, since the last release or
two now includes 820 G2 images, so I  was able to use those
with ./mk inject, to verify whether the refcode file is
still grabbed properly. We need the refcode to handle MRC
on Broadwell platform, but we extract it from an old Google
Chromebook image, that uses the old CBFS stage file layout.

This change solves my problem: the problem was that releases
are bloated further, due to including this extra coreboot
version. This should reduce the size of the next release
considerably, especially after decompressing the tarball.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 20:46:05 +01:00
Leah Rowe fe92605244 also fix the other grub trees
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 11:12:34 +01:00
Leah Rowe a8594762d2 Merge pull request 'fix trying to boot all logical volumes after unlocking an encrypted volume' (#330) from cqst/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/330
2025-05-08 10:11:13 +00:00
cqst e084b06dc7 fix trying to boot all logical volumes after unlocking an encrypted volume 2025-05-08 02:28:58 -07:00
Leah Rowe 2cea8517f3 init.sh: remove useless export
we already reset to n if not y, afterward

just rely on that

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 21:16:50 +01:00
Leah Rowe 1b0afdcea2 init.sh: also allow XBMK_RELEASE=Y or N
as opposed to =n or =y

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:23:32 +01:00
Leah Rowe 570f1417a8 init.sh: Resolve XBMK_CACHE via readlink
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:14:36 +01:00
Leah Rowe e1af1055ed init.sh: check XBMK_CACHE is a directory instead
it doesn't matter if it's not a file. that's the wrong check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:09:29 +01:00
Leah Rowe e1628ad8f3 init.sh: export LOCALVERSION in set_env
Don't do it in set_version

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:04:52 +01:00
Leah Rowe 40a944118f init.sh: run set_version before set_env
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:03:51 +01:00
Leah Rowe cba04aa74b init.sh: Use readlink in pybin()
Use realpath only as a fallback.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:00:13 +01:00
Leah Rowe a94bd3c093 inject.sh: simplify extract_kbc1126ec()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 17:08:42 +01:00
Leah Rowe e3098c61f4 inject.sh: simplified MAC address handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 17:00:41 +01:00
Leah Rowe d530e68594 inject.sh: Simplify patch_release_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 16:53:57 +01:00
Leah Rowe 7f71328f0e lib.sh: Remove useless command in err()
We don't need this, since we're exiting anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 16:23:12 +01:00
Leah Rowe 394b4ea7a5 inject.sh: rename copytb and preprom functions
make them shorter so they go on one line again

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 15:17:45 +01:00
Leah Rowe ec5c954337 lib.sh: Simplified fx_() and removed fe_()
Instead of calling fe_, prefix x_ as indicated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 15:12:10 +01:00
Leah Rowe 1390f7f800 mk: Create serprog tarballs here instead
i simplified rom.sh to use mkhelper for actual image
building.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 14:21:28 +01:00
Leah Rowe 0ef77e6583 build serprog using fe_ *defined inside mkhelper*
sh macros ftw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 14:01:50 +01:00
Leah Rowe d2e6f989d7 rom.sh: build serprog images with fe_
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 13:44:05 +01:00
Leah Rowe 0faef89946 lib.sh: support any command on find_exec()
right now, we assume "find", but it adds any number of
arguments next to that.

change it instead to support any command, where the
assumption is that it would generate a list of files
and directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 13:28:55 +01:00
Leah Rowe 2b7f6b7d7c inject.sh: Simplify extract_intel_me_bruteforce()
This is probably about as small as it's going to get.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 10:20:59 +01:00
Leah Rowe 485d785d33 inject.sh: clean up tmp me file before extract
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 21:16:06 +01:00
Leah Rowe fac99aa2d4 lib.sh: re-add missing break in fe/fx_
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 20:24:32 +01:00
Leah Rowe 03300766d1 inject.sh: tidy up extract_intel_me_bruteforce
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:47:08 +01:00
Leah Rowe 4781dbd2a0 inject.sh: fix oversight in me bruteforce
i used i instead of 1, in the variable when running
the extract_archive function.

this didn't trigger since +u was set, and +e was set.

in practise, then, it seems that because of this, and
because my ME extract/insert test was a success, that
none of the archives we use actually have a ME inside
of a file inside of a given downloaded archive.

still, this is technically incorrect, so fix it!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:43:44 +01:00
Leah Rowe cf78583a6d inject.sh: remove unnecessary check
the call stack already falls through with  a bunch of return
1s after a successful run of me_cleaner, so it's really not
necessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:32:18 +01:00
Leah Rowe 5657cc1afb inject.sh: don't use subshell for me bruteforce
i needed it on the old version, which used cd

this one stays in the same directory at all times

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:30:55 +01:00
Leah Rowe 5686f35e0f inject.sh: insanely optimise the me bruteforce
use fe_

fe_ ftw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 18:59:32 +01:00
Leah Rowe e8be3fd1d4 git.sh: Simplify git am handling
fx_ and fe_ really are the best shell functions ever.

really. they're the best.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 11:09:39 +01:00
Leah Rowe 4c1de1ad12 inject.sh: remove unused function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 04:49:56 +01:00
Leah Rowe 282b939d9d init.sh: New function dx_ to execute path files
Generated by find, this is a wrapper in place of using
for loops everywhere. This simplification temporarily
increases the amount of code, because we don't do this
a lot, but this will reduce the growth of the build
system code size in future changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 21:37:16 +01:00
Leah Rowe 73074dedee inject.sh: Further simplified FSP extraction
We don't need the copy command at all, since the files
it copies are the only ones that the Python script does
anyway, so now we just make that script output to the
directory, directly, where these files must go.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 21:13:28 +01:00
Leah Rowe 7585336b91 inject.sh: simplify kconfig scanning
Use fe_ with a new function, scankconfig, to do the
same thing. Not only is this simpler, it now also
operates on all coreboot configs for a given target,
whereas it previously only operated on the first one.

This is useful for cases where one config might use a
file that the other one does not; in practise, we don't
do this yet, but it's a theoretical possibility

Also: don't use the function check_defconfig, which is
now redundant and has been removed.

That function also conflicted with another function by
the same name in mk, but fortunately didn't cause an
issue in practise, due to how sh works; when vendor.sh
was used, it was without running the tree commands,
except under a separate lbmk instance.

So this is a simplification, a feature enhancement and
even a bug fix, all wrapped into one!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 21:05:45 +01:00
Leah Rowe ef38333f8b lib.sh find_ex: Write sort errors to /dev/null
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:45:31 +01:00
Leah Rowe c275f35e7e lib.sh x_(): Remove warning of empty args
It's completely unnecessary, and I forsee this
check breaking the build system at some point,
since some commands rely on the output of other
commands. Therefore, I've removed this check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:41:48 +01:00
Leah Rowe 17d826d3a9 lbmk: Replace err with much simpler implementation
The current implementation is insanely over-engineered,
and completely unnecessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:38:19 +01:00
Leah Rowe f98e34a24d singletree/elfcheck: use fx_, not fe_
fe_ returns an error on the find command, but we rely
on the only error ever being our intentional exit, upon
discovering files.

in singletree, the directory being checked was already
checked first, so we know it's safe not to err on find;
and find not reporting an error if no files are found is
ok.

on elfcheck, it's very much the same thing. In fact, we
very much want it to return 0 if the directory doesn't
exist, or if files don't exist within it.

Therefore, use fx_ which is designed for this use-case.

Quick re-cap: fx and fe execute a given function name with
each line outputting by find as an argument, each time. It
is somewhat similar in scope to find's -exec command.

We use fe_ as shorthand in several places all over lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:33:02 +01:00
Leah Rowe 8ca06463eb rom.sh: Print the rom image path being generated
This message used to exist, and it's a nice feedback
for the user, to confirm that the build went OK.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 18:14:44 +01:00
Leah Rowe dc9fe517cb rom.sh: Safer cprom()
Don't insert special files like GRUB keymaps after
copying to the final destination.

Instead, copy the tmprom to /tmp and operate on that,
in these instances.

This is less efficient, depending on the user's
configuration; if /tmp is on the same file system as
the user's xbmkpwd, it should be fine. However, the
actual performance hit isn't that bad in practise,
on most setups.

If the user's /tmp is a tmpfs, then that means using
tmpfs, but it's one image at a time. It should be OK.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 18:08:55 +01:00
Leah Rowe 2be8d1c798 rom.sh: specifically check keymaps in cprom()
"not seauboot" is a valid check at present, but if
i start supporting other arguments in the future,
this code would have to change.

therefore, i change it in advance, on that theory.

this new check is more technically correct. these
lines are triggered when inserting grub keymaps.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 17:53:43 +01:00
Leah Rowe 89a8cd4936 rom.sh: simplify mkseagrub()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 17:48:57 +01:00
Leah Rowe c2182d8219 mk: simplify elfcheck()
fe_() called inside subshell, ftw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 15:51:04 +01:00
Leah Rowe 437ac2454c lib.sh: simplify singletree()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 15:40:08 +01:00
Leah Rowe 62ec3dac07 git.sh: move singletree() to lib.sh
it's also used by mk, to determine which build function
to use (build_project or build_targets).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 15:31:33 +01:00
Leah Rowe 6b247c93e2 mk: Fix bad error handling for gnu_setver
I mixed logical OR and AND by mistake. Oops!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe ee8bb28ba2 GRUB: Mark E820 reserved on coreboot memory
See, coreboot bug report:

https://ticket.coreboot.org/issues/590

We hadn't noticed this for quite a while, since we always
just booted with iomem=relaxed when needing to run cbmem,
since in practise it was always combined with other tasks
that require access to lower memory.

GRUB currently matches coreboot's own mmap for cbmem, but
for example SeaBIOS marks cbmem as E820 reserved. Therefore,
this change replicates the SeaBIOS behaviour.

Without this patch, Linux needs to boot with iomem=relaxed
for cbmem access, for example when running ./cbmem -1

With this patch, cbmem is now accessible regardless. This
patch also prevents Linux from overwriting parts of CBMEM.

Thanks go to Paul Menzel, who wrote this GRUB patch.

Thanks also go to Nicholas Chin, who provided testing, all
the way from Coreboot 25.03 back to Coreboot 4.20. It seems
that this is just something the payloads have to handle.

This means that both SeaBIOS and GRUB no longer have this
bug, in Libreboot; now what remains is to replicate the
test with our U-Boot payload.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe 61ec396ef6 inject.sh: simplify extract_intel_me_bruteforce()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe e4edc2194d inject.sh: Remove unnecessary check
_dest is already checked in the calling function fetch(),
after extract_tbfw() has been called.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe f4057d7daa inject.sh extract_intel_me(): reduce indentation
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe b7ca59debe inject.sh: Move FSP extraction only to extract_fsp
Don't do FSP-specific extraction in extract_archive, as
that is not what the latter is for.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:07 +01:00
Leah Rowe eb882de94c inject.sh: tidy up intel me handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 05:43:38 +01:00
Leah Rowe 153dd76a82 inject.sh: tidy up the deguard command
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 05:41:21 +01:00
Leah Rowe 428c46ca2b lib.sh: set -u -e in err()
Some parts of lbmk set +u +e, to be reset later on
under normal conditions upon exit. We must ensure
such level of integrity in err() as well.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 05:20:47 +01:00
Leah Rowe 20c8730858 lib.sh: Provide error message where none is given
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:53:02 +01:00
Leah Rowe 35265731c5 init.sh: Silence the output of git config --global
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:50:50 +01:00
Leah Rowe 5e3aaa1eb8 init.sh: Run git name/email check before init
Otherwise, it returns if init is already done, which
later leads to build errors in coreboot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:49:30 +01:00
Leah Rowe a3b5626f53 lib.sh: stricter xbmk_err check in err()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:35:31 +01:00
Leah Rowe 51b2a1159d lib.sh: simplify err-not-set handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:31:08 +01:00
Leah Rowe 61e5fd1a0b lib.sh: Add warning if x_ is called without args
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:28:22 +01:00
Leah Rowe 4020fb4328 lib.sh: simplify err()
Rely once again on err_, but still explicitly add an exit
just below, in case I made a mistake one day.

err() is essentially a trap that triggers in case I mess
up an error function, so that it doesn't reliably exit.

So, the idea is that everything calls err(), and err() is
almost never modified, or modified very carefully.

If error exits were ever broken, the result could be quite
unpredictable, so lbmk has very strict error handling, and
great care is taken to ensure that it does reliably exit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:23:11 +01:00
Leah Rowe b51846da6d init.sh: single-quote xbmklock in xbmk_lock()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:14:50 +01:00
Leah Rowe 8b7bd992f6 init.sh: define lock file in a variable instead
don't hardcode it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:12:23 +01:00
Leah Rowe 9611c19e7e init.sh: tidy up xbmk_child_exec()
make the command style more consistent, for example
relying on x_ inside a subshell to print the command
and arguments if a command failed.

this is a good style, and i'll probably use it in other
places on lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:03:34 +01:00
Leah Rowe 37ca0c90e1 lib.sh err: add missing redirect to stderr
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 10:18:33 +01:00
Leah Rowe 54291ebb72 lbmk: MUCH safer err function
Don't directly call a variable. Call a function that
checks the variable instead.

The new err function also checks whether an exit was
actually done, and exits 1 if not.

If an exit was done by the given function, but the exit
was zero, this is also corrected to perform an exit 1.

This fixes a longstanding design flaw of lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 10:13:42 +01:00
Leah Rowe 3f7dc2a55f lib.sh: rename errx to xmsg
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 09:17:23 +01:00
Leah Rowe 59c94664e3 lib.sh: Make x_ err if first arg is empty
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 09:14:09 +01:00
Leah Rowe 91bb6cbede lib.sh: Make err_ always exit no matter what
Always certainly redundant, since if -u -e isn't
set, it'll continue to exit anyway.

However, we want to be pedantic about this, since
the safety of lbmk relies entirely on this function
NOT misbehaving.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 09:10:24 +01:00
Leah Rowe b19c4f8f67 inject.sh: tidy up TBFW handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:50:23 +01:00
Leah Rowe 439020fbda inject.sh: remove useless comment block
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:47:56 +01:00
Leah Rowe 6e447876cc init.sh: tidy up the python version check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:47:12 +01:00
Leah Rowe 7392f6fc8e init.sh: move non-init functions to lib.sh
these were missed in a previous cleanup

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:33:17 +01:00
Leah Rowe 7acec7a3a1 init.sh: simplify dependencies handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:29:19 +01:00
Leah Rowe 93ba36ae45 rom.sh: tidy up copyps1bios()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:19:17 +01:00
Leah Rowe fc71e52fdf mk: tidy up xgccargs handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:15:00 +01:00
Leah Rowe 184871bc17 mk: remove useless code
this was added a few commits ago, but the previous commit
made me realise it's not needed at all.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:10:59 +01:00
Leah Rowe b6a2dc4ea3 init.sh: tidy up pathdir creation
we can use remkdir here. it does the same thing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:10:36 +01:00
Leah Rowe f5b2bdb886 mk: re-make gnupath/ after handling crossgcc
instead of deleting every file within

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:07:53 +01:00
Leah Rowe 1b7a9fd637 mk: tidy up check_cross_compiler
only initialise variables at the point they're needed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:07:06 +01:00
Leah Rowe 488d52e784 mk: re-make gnupath/ for each cross compiler
it could be that some were left over before, for some
reason. that isn't currently the case, but this will
avoid the possibility in future.

therefore, this is a preemptive bug fix.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:05:19 +01:00
Leah Rowe c33467df1e mk: reduce indentation in check_cross_compiler()
we only call it in one place. the resulting code is still
quite clear.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:02:14 +01:00
Leah Rowe aa4083443b mk: Allow use of x_ on prefix functions
Use this for the sha512sum command, on the main mk
script at the function check_project_hashes().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 18:30:37 +01:00
Leah Rowe 8f828e6cd3 mk: tidy up check_project_hashes() sha512sum check
the extra function isn't needed at all. awk can just
handle every line all at once.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 18:18:41 +01:00
Leah Rowe 7a2f33264d mk: simplify check_gnu_path()
the initial checks are unnecessary, since i always know
what arguments are being provided.

the -f check in the for loop is now an -x instead, more
efficient and complete.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 18:05:37 +01:00
Leah Rowe 46b968a6e8 inject.sh: minor code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 13:49:49 +01:00
Leah Rowe 5499ae66bd inject.sh: simplify extract_archive()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 13:35:28 +01:00
Leah Rowe 72f4412a52 inject.sh: simplified fsp extraction
we know that _dest is always what's set in the coreboot config,
without the ../../../ in it, so just copy both files in a single
function, and call the function twice.

if both files are done on the first call, the second call will
be skipped. if only the first file was done on the  first call,
running the download script again will skip the  first one, and
grab the second one.

this also avoids having to run the decat function twice, in most
cases, so it's a tiny optimisation.

this optimisation only works if both fsp files (s and m) are to
be extracted into the same directory, which is the case anyway,
and this will always be the case.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 13:28:47 +01:00
Leah Rowe bf569d2b4d inject.sh: Remove redundant code in copy_tbfw
We don't use the tbtmp variable anymore, in this function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:20:48 +01:00
Leah Rowe 8de0ed811f inject.sh: Stricter TBFW handling
Don't copy it until it has been padded properly.

Otherwise, erroneous padding would result in an error,
and who knows what would be left in vendorfiles/ ?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:17:21 +01:00
Leah Rowe 530e4109a2 init.sh: *Re-create* tmpdirs on parent instance
To make sure any old files are removed, always re-create.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:05:38 +01:00
Leah Rowe 498f5a26cc init.sh: Always create xbmklocal
If we're in a release work directory, TMPDIR is already
set, so the local ./tmp won't be created, which would
lead to an error.

Fix it by creating xbmklocal before checking TMPDIR.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:04:34 +01:00
Leah Rowe 00d22f2082 lbmk: Unified local ./tmp handling
Make it an absolute directory, relative to xbmktmp.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:01:19 +01:00
Leah Rowe 0f7b3691ab lib.sh: redirect find errors to /dev/null
this silences confusing error messages that the user
sees on the screen, that are actually benign, and it
will thus reduce the number of people who ask questions
on #libreboot irc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:41:20 +01:00
Leah Rowe 7fadb17fd9 lib.sh: Fix bad touch command
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:36:43 +01:00
Leah Rowe 0b09d97073 inject.sh: Only build nvmutil once
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:35:48 +01:00
Leah Rowe 308df9ca40 inject.sh: always re-build nvmutil
it's not a lot of code, and takes less than a second.

the previous change uses x instead of ?, but this would
cause an error if the nvmutil was already built, because
the makefile might cause a build to be skipped.

therefore, force a re-build to mitigate the error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:28:14 +01:00
Leah Rowe 44a1cc9ef8 util/nvmutil: use x, not ?, for random characters
A user reported that '?' causes an error on zsh. See:

https://codeberg.org/libreboot/lbmk/issues/261

For example:

./mk inject libreboot-XXXXXX.tar.xz setmac ??:??:??:??:??:??

The user got:

 zsh: no matches found: ??:??:??:??:??:??

The mitigation here is to double-quote, e.g.:

./mk inject libreboot-XXXXXX.tar.xz setmac "??:??:??:??:??:??"

However, a lot of people won't do that. Therefore, I will
retain the current behaviour but support x/X for randomness.

Now lbmk uses x by default, instead. I will now update the
documentation, accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:23:10 +01:00
Leah Rowe a17875c345 lib.sh find_ex: explicitly create the tmp file
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:57:39 +01:00
Leah Rowe 0ffaf5c733 init.sh: Explicitly create the xbmktmp directory
mktemp would normally do it, but we must not rely on that

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:33:02 +01:00
Leah Rowe fcc52b986e init.sh: unified handling of ./tmp
not to be confused with /tmp

we use ./tmp inside the lbmk work directory, for large files,
because /tmp might not be very big, or might be a tmpfs

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:32:01 +01:00
Leah Rowe 47762c84ad lib.sh: add fe_ which is fx_ but err on find
In the mk script, we need fx_ to not return errors on the
find command, since it's searching a bunch of directories
where some of them may not exist.

All other instances where fx_ is used, must return an error
if the directory being searched doesn't exist.

For this, fe_() is introduced, which does the same as fx_
but with this much stricter check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:25:11 +01:00
Leah Rowe d18d1c2cae lbmk: unified execution on find commands
We have a lot of places in lbmk where the output of find is
used, and then some function is executed on the result.

This is messy, and bloats several of these functions.

Now this is unified, into a new function: fx_

What fx_ does is execute a given function, for each result
found, with the arguments for a find command appended.

For example:

find -name ".git"

If you wanted to do: foo "$arg"

Where "arg" is a search result from find, and you wanted
to execute "foo" on each one, you would do:

fx_ foo -name ".git"

The find utility does have an -exec feature, but I've found
that it only works for executables, not functions.

fx_ does not return errors, so "foo" in this example
would have to do its own error handling.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:02:31 +01:00
Leah Rowe 773d2deaca NEW MAINBOARD: Dell Precision T1700 SFF and MT
This is similar to the 9020SFF, but this board has ECC support.
However, the native raminit isn't used here, even though it is
otherwise compatible, because the native init doesn't do ECC yet.

The broadwell mrc.bin has ECC support, which is also used on the
HP EliteBook 820 G2. The MRC for broadwell can be used on haswell
boards such as the T1700.

Add both the SFF and MT variants. Since these are identical to the
9020 variants, except for slightly different PCH enabling ECC, we
can just re-use the 9020 port without issue.

We *could* add a variant to coreboot, for T1700, but there is not
really any pressing need. It is simply the 9020sff/mt with mrc.bin

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 17:18:55 +01:00
Leah Rowe 9b11e93686 mk: include rom.sh directly
remove it from mkhelper files, because rom.sh doesn't
initialise any variables globally, except one that
never changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 11:20:55 +01:00
Leah Rowe 1f7e4b35cb mk: Download vendorfiles before building release
Do it just after creating the src archive. This way,
everything is downloaded all at once.

Otherwise, a momentary lapse of internet uptime will
cause a release build to fail later on, and one of
lbmk's flaws is that this would then mean you must
re-build from scratch.

If we assume that the internet is working within a
short period of time, then this change would mitigate
that possibility. If something did happen during tar
archive creation, that's a much shorter amount of time
that is "wasted".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 10:56:14 +01:00
Leah Rowe acb0ea202f lib.sh: Simplify rmgit()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 10:52:38 +01:00
Leah Rowe 15b76bc202 lib.sh: support multiple arguments in remkdir()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 07:26:39 +01:00
Leah Rowe f3ae3dbbbe lib.sh: simplify remkdir()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 07:26:17 +01:00
Leah Rowe 6c4d88f268 move x_() to lib.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 07:24:11 +01:00
Leah Rowe 2ae565ba93 init.sh: move setvars/err_ to lib.sh
these functions make more sense in lib.sh

i made mk link lib.sh first, so that the
functions on init.sh can still use them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 05:54:36 +01:00
Leah Rowe c073ee9d4f Restore SeaBIOS 9029a010 update, but with AHCI fix
I fixed the AHCI bug, with a patch that I wrote. It works by
restoring the old SeaBIOS AHCI initialisation behaviour, whereby
the AHCI controller is enabled from its current state; the patch
that broke AHCI in coreboot (tested on ThinkPad T420), changed
AHCI initialisation behaviour so that the controller's state is
first reset, prior to enablement.

However, my patch also retains the new AHCI initialisation
behaviour, when a CSM is in use. The AHCI reset patch was done,
by the author, specifically for SeaBIOS in CSM mode, so it makes
sense to only change the behaviour conditionally according to that.

This reverts commit 8245f0b321.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 02:24:07 +01:00
Leah Rowe 8245f0b321 Revert "seabios: bump to rev 9029a010, 4 March 2025"
This reverts commit a08b8d94fc.

From #libreboot IRC today:

07:02 <irys> ooh this is fun. seabios commit 8863cbbd15a73b03153553c562f5b1fb939ad4d7 (ahci: add controller reset) breaks ahci entirely on t420
07:05 <irys> cbmem console on that seabios commit has a timeout then "AHCI/0: device not ready"
07:07 <irys> AHCI works fine if i change config/seabios/default/target.cfg to use the immediate previous seabios commit (df9dd418b3b0e586cb208125094620fc7f90f23d)
07:07 <irys> works in grub payload either way though
07:31 <irys> here, `cbmem -c` after booting the broken rev: https://0x0.st/84oQ.log
07:31 <irys> compared to the working one https://0x0.st/84o1.log
07:33 <irys> i can't report to upstream myself *right now* but i figure you might want to know about this leah

I have downloaded those logs locally for reference, so that an upstream
report can be made to SeaBIOS. For the purposes of this Libreboot commit,
the diff of the logs is as follows (diff -u broken.log working.log):

Taking each diff line out of the log, the relevant entries
seem to be:

Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
+AHCI/0: Set transfer mode to UDMA-6
+Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0
+AHCI/0: registering: "AHCI/0: Netac SSD 128GB ATA-11 Hard-Disk (119 GiBytes)"

-WARNING - Timeout at ahci_port_setup:477!
-AHCI/0: device not ready (tf 0x80)
-All threads complete.

-2. Payload [memtest]
+2. AHCI/0: Netac SSD 128GB ATA-11 Hard-Disk (119 GiBytes)
+3. Payload [memtest]

-Space available for UMB: c7000-eb800, f5880-f5ff0
-Returned 16777216 bytes of ZoneHigh
+drive 0x000f5fa0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=250069680
+Space available for UMB: c7000-eb800, f5880-f5fa0
+Returned 16773120 bytes of ZoneHigh

Therefore, the revision will be reverted back for now. It was
only about 8 additional patches imported in the update anyway.
2025-05-01 14:30:14 +01:00
Leah Rowe 4c50157234 coreboot/t420_8mb: add missing txtmode config
Reported by irys on #libreboot irc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-01 14:29:22 +01:00
Leah Rowe f21749da8b Libreboot 25.04 Corny Calamity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 12:28:46 +01:00
Leah Rowe bb5f5cd576 add pico-sdk backport patch fixing gcc 14.x
src/rp2_common/boot_stage2/boot2_w25x10cl.S:142: Error: junk at end of line, first unrecognized character is `0'
src/rp2_common/boot_stage2/boot2_w25x10cl.S:145: Error: garbage following instruction -- `beq 00b'

This should also fix it on Debian sid Experimental, where I'm testing
with GCC 15 and other bleeding edge dependencies.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 11:11:03 +01:00
Leah Rowe 4f77125066 coreboot/fam15h: update submodule for nasm
i forgot to in the last commit, but it didn't matter because
it just meant that coreboot.git's own download logic kicked
in as a fallback. however, it's better to rely on libreboot's
build system for this, since it has redundancy.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 04:38:07 +01:00
Leah Rowe 0f2202554a coreboot/fam15h: update nasm to 2.16.03
this fixed kgpe-d16 build errors on gcc 15 when tested
on debian sid (with gcc-15 installed from experimental)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 04:32:49 +01:00
Leah Rowe 2009c26f0a serprog: Remove pico2 support for the time being
Many users report bugs, so I'm reverting lbmk back to only
supporting the rp2040 dongles for the time being. The
documentation will be updated to reflect this.

Pico2 support will be re-added at a later date, once more
testing has been done, and fixes made if necessary.
2025-04-30 02:35:34 +01:00
Leah Rowe a08b8d94fc seabios: bump to rev 9029a010, 4 March 2025
This brings in the following improvements from upstream:

* 9029a010 kconfig: fix the check-lxdialog.sh to work with gcc 14+
* 8863cbbd ahci: add controller reset
* df9dd418 update pci_pad_mem64 handling
* a4fc1845 add romfile_loadbool()
* a2725e28 drop acpi tables and hex includes
* 35aa9a72 drop obsolete acpi table code
* 1b598a1d usb-hid: Support multiple USB HID devices by storing them in a linked list

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 01:52:56 +01:00
Leah Rowe 342eca6f3d update untitled
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 01:26:34 +01:00
Leah Rowe b0a6d4711a coreboot413: add alper's fix to cbfstool for gcc15
otherwise, it won't compile on gcc 15 (pragma fix from
earlier on, used on the other coreboot trees)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 00:59:39 +01:00
Leah Rowe 628ae867c9 flashprog: bump to rev e060018 (1 March 2025)
This brings in the following upstream changes:

* e060018 flashchips: Explicitly zero-initialize in .qpi_read_params
* ff9526b dediprog: Use dual-i/o default only for SF600Plus-G2
* 5a72cfb flashchips: Fix block-protection bits for 4BA Puya chips
* 284d55b flashchips: Add WPS bit description for GD25Q128C
* 37e07a8 flashchips: Add missing QE bit descriptions
* 3646b18 flashchips: Add GigaDevice GD25LF128E 166MHz, 1.8V part
* d4eb532 flashchips: Add GigaDevice GD25LF80E..GD25LF64E 166MHz, 1.8V parts
* 38d037f flashchips: Add GigaDevice GD25LB512MF..GD55LB02GF 1.8V parts
* 1da0293 flashchips: Add GigaDevice GD25LB512ME..GD55LB02GE 1.8V parts
* 6d728e6 flashchips: Add GigaDevice GD25B512MF..GD55B02GF 3.3V parts
* 493a4e0 flashchips: Update and split GD25Q256D entry
* 648dfdc spi25: Fix cosmetic debug-print error due to unitialized buffer
* cfd607d layout: Show a warning if no region is included
* ec287e2 ich_descriptors_tool: Change region name EC/BMC -> EC_BMC
* 39a4f7d sb600spi: Request more `lspci` details
* 404529d memory_bus.c: Add missing copyright notice
* fbea0fe udev rules: Restore mode/group configuration
* c90d6c4 flashchips: Add some 25LC series EEPROMs
* ee8cf1c Provide no-op probe function, always returning 1
* 4e6155a spi25: Add SPI25_EEPROM enum and handle < 3-byte addresses
* 9512c9c Add missing copyright notices to recently created files
* 06fbccc flashchips: Add GigaDevice GD25LB256E 1.8V part
* bc001da flashchips: Add some GigaDevice GD25L*256 1.8V parts
* 7d0f556 flashchips: Update GigaDevice 1.8V family up to GD25LQ128
* 7f8c12d flashchips: Add GigaDevice GD25LQ20, update family up to GD25LQ16
* 565471c flashchips: Add GigaDevice GD25B512ME..GD55B02GE 3.3V parts
* 6ee2f89 flashchips: Update GigaDevice GD25Q/B/R 128Mbit, 3.3V parts
* c230c69 flashchips: Add remaining Puya PY25Q..H 3.3V parts
* 06e0264 flashchips: Add Puya PY25Q..H family up to PY25Q128H
* fe21b43 flashchips: Add remaining P25Q..H family 3.3V chips
* 1c5d829 flashchips: Add Puya P25Q40SH, P25Q80SH, P25Q16SH 3.3V parts
* b0cae5e flashchips: Add Puya P25Q06H, P25Q11H, P25Q21H 3.3V parts
* b09136b flashchips: Add Puya P25Q05..16H 3.3V parts
* ed8b82c flashchips: Add Fudan FM25Q128 3.3V part
* 4a35134 flashchips: Add Fudan FM25Q08A 3.3V part
* 7f7bffa flashchips: Add Fudan FM25Q64, update FM25Q08..Q32
* c591518 flashchips: Add Fudan FM25Q02/Q04 3.3V parts
* fea6e16 flashchips: Add Winbond W25Q16JV_M (DTR version)
* 56d727e flashchips: Add newer gen. XTX Tech. XT25F..F 3.3V parts
* c64a803 flashchips: Add XTX Tech. XT25F..B 3.3V family
* 46e4209 flashchips: Add XTX Tech. XT25F02E/04D/08B 3.3V parts
* 6bc88e7 flashchips: Add Boya/BoHong BY25Q32/64/128 3.3V variants
* 3cddff4 flashchips: Complete Boya/BoHong BY25D family
* 34e3de6 flashchips: Add Zetta Device ZD25LQ64/128 1.8V parts
* f050370 selfcheck: Check dummy-cycle settings when QPI is advertised
* d40037a selfcheck: Check for WP functions when BP bits are given
* 2a1036b flashchips: Fix up GD25Q128C write-protect support
* d4e41d3 flashchips: Add SST26VF080A
* 04c1cf7 Add .envrc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 00:43:45 +01:00
Leah Rowe 5e96db5a2b further gcc-15 fix for gmp on -std=23
the fix in the previous revision wasn't being applied
properly, because the build system of gmp generates
a conftest.c file, and the entry being made for it was
actually coming from this place in the configure file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 23:21:59 +01:00
Leah Rowe 9a9cd26b2d coreboot/default and fam15h: gmp fix, gcc15 hostcc
gcc 15 defaults to -std=c23, but the older gcc was
using -std=c17. The new c23 breaks GMP, so let's add
a patch from upstream (GMP project) to fix it.

this has been done to both coreboot trees.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 22:16:09 +01:00
Leah Rowe 80007223c8 lib.sh: Provide printf for mktarball
Just to let the user know lbmk hasn't died.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 19:51:15 +01:00
Leah Rowe a16c483e5f Merge pull request 'coreboot: fam15h: Add patches to fix build with GCC 15 as host compiler' (#318) from alpernebbi/lbmk:coreboot-fam15h-gcc15 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/318
2025-04-29 17:13:45 +00:00
Alper Nebi Yasak 685685ab0e coreboot: fam15h: Add patches to fix build with GCC 15 as host compiler
Building the fam15h tree results in one of the same nonstring errors
we also had when building the default tree. Copy the relevant patch from
the default tree, while dropping a hunk that we don't need in this old
version.

Another build error is about bool being a reserved keyword now:

  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7140:13: error: 'bool' cannot be used here
   7140 | static void bool(struct compile_state *state, struct triple *def)
        |             ^~~~
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7140:13: note: 'bool' is a keyword with '-std=c23' onwards
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7140:18: error: expected identifier or '(' before 'struct'
   7140 | static void bool(struct compile_state *state, struct triple *def)
        |                  ^~~~~~
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c: In function 'mkcond_expr':
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7708:19: error: expected ')' before ',' token
   7708 |         bool(state, test);
        |                   ^
        |                   )
  [...]

Fix that by adding a patch that renames the function to bool_().

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 19:54:12 +03:00
Leah Rowe 02110f2bc1 Merge pull request 'coreboot: Add patch to fix build with GCC 15 as host compiler' (#317) from alpernebbi/lbmk:coreboot-gcc15-nonstring into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/317
2025-04-29 16:31:07 +00:00
Alper Nebi Yasak 5ad1de3931 coreboot: Add patch to fix build with GCC 15 as host compiler
Building coreboot host tools with GCC 15 results in build errors:

  In file included from .../lbmk/src/coreboot/default/util/cbfstool/console/console.h:7,
                   from .../lbmk/src/coreboot/default/src/commonlib/fsp_relocate.c:3:
  .../lbmk/src/coreboot/default/src/commonlib/include/commonlib/loglevel.h:170:26: error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (6 chars into 5 available) [-Werror=unterminated-string-initialization]
    170 |         [BIOS_EMERG]   = "EMERG",
        |                          ^~~~~~~
  .../lbmk/src/coreboot/default/src/commonlib/include/commonlib/loglevel.h:171:26: error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (6 chars into 5 available) [-Werror=unterminated-string-initialization]
    171 |         [BIOS_ALERT]   = "ALERT",
        |                          ^~~~~~~
  [...]
  ../cbfstool/common.c: In function 'bintohex':
  ../cbfstool/common.c:195:43: error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (17 chars into 16 available) [-Werror=unterminated-string-initialization]
    195 |         static const char translate[16] = "0123456789abcdef";
        |                                           ^~~~~~~~~~~~~~~~~~

Add a patch that marks the latter with the "nonstring" attribute, and
disable the warning for the former because I couldn't figure out how to
add that attribute there.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 17:45:46 +03:00
Leah Rowe 9e7bceb7fa Merge pull request 'seabios: Fix malloc_fn function pointer in romfile patch' (#313) from alpernebbi/lbmk:seabios-romfile-malloc-fptr into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/313
2025-04-29 13:55:18 +00:00
Leah Rowe 686e136f15 Merge pull request 'dependencies/debian: Fix libusb package name' (#315) from alpernebbi/lbmk:debian-libusb-dependency into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/315
2025-04-29 13:55:06 +00:00
Alper Nebi Yasak 6f120f0158 dependencies/debian: Fix libusb package name
The Debian package for libusb is "libusb-1.0-0". Fix the typo in the
list which is missing the suffix. While we're here, also fix a line
continuation.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 16:46:24 +03:00
Alper Nebi Yasak 35c853f8b3 seabios: Fix malloc_fn function pointer in romfile patch
One of our SeaBIOS patches causes build errors with GCC 15:

  src/romfile.c: In function 'romfile_loadfile_g':
  src/romfile.c:65:18: error: too many arguments to function 'malloc_fn'; expected 0, have 1
     65 |     char *data = malloc_fn(filesize+add_len);
        |                  ^~~~~~~~~ ~~~~~~~~~~~~~~~~
  src/romfile.c: In function 'romfile_loadfile':
  src/romfile.c:88:50: error: passing argument 3 of 'romfile_loadfile_g' from incompatible pointer type [-Wincompatible-pointer-types]
     88 |     char *data = romfile_loadfile_g(name, psize, &malloc_tmphigh, 1);
        |                                                  ^~~~~~~~~~~~~~~
        |                                                  |
        |                                                  void * (*)(u32) {aka void * (*)(unsigned int)}
  src/romfile.c:55:28: note: expected 'void * (*)(void)' but argument is of type 'void * (*)(u32)' {aka 'void * (*)(unsigned int)'}
     55 |                    void *(*malloc_fn)(), int add_len)
        |                    ~~~~~~~~^~~~~~~~~~~~
  In file included from src/romfile.c:8:
  src/malloc.h:42:21: note: 'malloc_tmphigh' declared here
     42 | static inline void *malloc_tmphigh(u32 size) {
        |                     ^~~~~~~~~~~~~~
  make: *** [Makefile:142: out/src/romfile.o] Error 1
  make: *** Waiting for unfinished jobs....
  src/optionroms.c: In function 'vgarom_setup':
  src/optionroms.c:468:60: error: passing argument 3 of 'romfile_loadfile_g' from incompatible pointer type [-Wincompatible-pointer-types]
    468 |     void *mxm_sis = romfile_loadfile_g("mxm-30-sis", NULL, &malloc_low, 0);
        |                                                            ^~~~~~~~~~~
        |                                                            |
        |                                                            void * (*)(u32) {aka void * (*)(unsigned int)}
  In file included from src/optionroms.c:18:
  src/romfile.h:17:34: note: expected 'void * (*)(void)' but argument is of type 'void * (*)(u32)' {aka 'void * (*)(unsigned int)'}
     17 |                          void *(*malloc_fn)(), int add_len);
        |                          ~~~~~~~~^~~~~~~~~~~~
  In file included from src/optionroms.c:16:
  src/malloc.h:30:21: note: 'malloc_low' declared here
     30 | static inline void *malloc_low(u32 size) {
        |                     ^~~~~~~~~~
  make: *** [Makefile:141: out/src/optionroms.o] Error 1
  make: Leaving directory '/tmp/lbmk/src/seabios/default'

This is because the function pointer defined as `void *(*malloc_fn)()`
refers to a function that takes no arguments, unlike `malloc_tmphigh`
which takes an unsigned int. Add the missing argument type.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 16:37:14 +03:00
Leah Rowe d8b0e74998 init.sh: fix yet another double quote for dotfiles
i missed this one, in another recent revision

double-quote because of the dot, for bash users

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 14:11:56 +01:00
Leah Rowe 780844112a Merge pull request 'Update U-Boot to v2025.10' (#305) from alpernebbi/lbmk:uboot-v2025.04 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/305
2025-04-29 12:50:55 +00:00
Alper Nebi Yasak 1265927ca3 u-boot: gru: Disable INIT_SP_RELATIVE
Recently, gru boards were migrated to use common stack addresses with
U-Boot commit 5e7cd8a11995 ("rockchip: Use common bss and stack
addresses on RK3399") and commit 49f8131e5594 ("rockchip: rk3399-gru:
Use TPL with common bss and stack addresses"). This is done with the
ROCKCHIP_COMMON_STACK_ADDR config.

With POSITION_INDEPENDENT, INIT_SP_RELATIVE defaults to enabled as well.
However, ROCKCHIP_COMMON_STACK_ADDR selects HAS_CUSTOM_SYS_INIT_SP_ADDR,
which depends on INIT_SP_RELATIVE being disabled. So this results in a
configuration warning:

  WARNING: unmet direct dependencies detected for HAS_CUSTOM_SYS_INIT_SP_ADDR
    Depends on [n]: ARM [=y] && ARCH_KIRKWOOD [=n] || ARC [=n] || ARM [=y] && !INIT_SP_RELATIVE [=y] || MIPS [=n] || PPC [=n] || RISCV [=n]
    Selected by [y]:
    - ROCKCHIP_COMMON_STACK_ADDR [=y] && ARM [=y] && ARCH_ROCKCHIP [=y] && SPL_SHARES_INIT_SP_ADDR [=y]

I'm not sure if adhering to the Rockchip values means we can't be
position-independent. Disabling INIT_SP_RELATIVE still appears to keep
my kevin board working, so let's do that for now.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:31:11 +03:00
Alper Nebi Yasak 5bea1fade9 u-boot: arm64: Expand our modified defconfigs to full configs
Run `./mk -l u-boot` to regenerate full configs from our new defconfigs.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:31:01 +03:00
Alper Nebi Yasak fd56d8ada1 u-boot: arm64: Merge our modifications into new defconfigs
Apply our preserved changes to the new U-Boot defconfigs. Upstream
rearranged memory layouts for Rockchip boards to a unified layout, which
got rid of CUSTOM_SYS_INIT_SP_ADDR and HAS_CUSTOM_SYS_INIT_SP_ADDR, and
will need a change to a related INIT_SP_RELATIVE later.

Normalize the positions of each line in the config by regenerating the
defconfig by `./mk -l u-boot` and then `./mk -s u-boot`, so that the
diff looks all green when we actually expand it to the full config.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:28:08 +03:00
Alper Nebi Yasak ed9ddd7415 u-boot: arm64: Add new upstream defconfigs
Copy over the new upstream defconfigs from the refreshed U-Boot trees,
so we can fold our modifications into them. Manually done, but like:

    do_defconfig() {
        ours="$1"
        theirs="$2"
        tree="$3"

        cp src/u-boot/${tree}/configs/${theirs}_defconfig \
           config/u-boot/${ours}/config/default
    }

    do_defconfig  amd64coreboot   coreboot64        x86_64
    do_defconfig  i386coreboot    coreboot          x86
    do_defconfig  gru_bob         chromebook_bob    default
    do_defconfig  gru_kevin       chromebook_kevin  default
    do_defconfig  qemu_arm_12mb   qemu_arm64        default

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:27:32 +03:00
Alper Nebi Yasak b1fa44858c u-boot: arm64: Rebase to v2025.04
Set the U-Boot revision to the commit hash for v2025.04, and rebase the
patches for the default U-Boot tree to accommodate for upstream changes:

 - The SPL/TPL/VPL phases are being unified under the xPL name, so
   there's a config rename.
 - Some test macros were renamed, for the video-related patches.
 - Add some missing hunks for video damage series.
 - Upstream Makefile adds another argument to the binman call.
 - The SWIG related patch is merged upstream, drop it.

I'm not sure if src/u-boot/* directories are regenerated on new builds,
so it may be necessary to remove them manually after applying this.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:26:58 +03:00
Alper Nebi Yasak 976fc6890a u-boot: arm64: Save our modifications to the upstream defconfigs
Run diffconfig from Linux to track our modifications to the old upstream
defconfigs, so we can apply them to the new ones. Restore the original
defconfigs to highlight our changes here, and upstream changes in the
next commit. Done manually, but something like:

  do_diff() {
      ours="$1"
      theirs="$2"
      tree="$3"

      diffconfig \
          src/u-boot/${tree}/configs/${theirs}_defconfig \
          config/u-boot/${ours}/config/default \
          >config/u-boot/${ours}/config/diffconfig

      cp src/u-boot/${tree}/configs/${theirs}_defconfig \
          config/u-boot/${ours}/config/default
  }

  do_diff amd64coreboot    coreboot64        x86_64
  do_diff i386coreboot     coreboot          x86
  do_diff gru_bob          chromebook_bob    default
  do_diff gru_kevin        chromebook_kevin  default
  do_diff qemu_arm64_12mb  qemu_arm64        default

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:26:22 +03:00
Alper Nebi Yasak 418570a617 u-boot: arm64: Turn configs into defconfigs
Run `./mk -s u-boot` to convert our configs into defconfigs, so we can
keep our changes to the old upstream defconfigs and re-apply them to the
new upstream defconfigs.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:26:12 +03:00
Leah Rowe 093a86d9c0 init.sh: don't use eval to read version files
it's not necessary, and was the cause of a recent issue,
which i mitigated, but why mitigate it?

prevent bugs. don't use eval unless absolutely necessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 12:01:13 +01:00
Leah Rowe 3045079947 init.sh: use backslash for dotfiles in eval
see:

commit f0c629dcc6
Author: Leah Rowe <leah@libreboot.org>
Date:   Sat Apr 12 13:51:49 2025 +0100

    lib.sh: write version/versiondate to dotfiles

and this bug report:

https://codeberg.org/libreboot/lbmk/issues/284

The report indicates that the above commit broke bash,
when sh (on the user's system) is bash.

I know sometimes when using bash, I need to use the
back slash when dealing with dots, e.g. when grepping
something.

Also double quote references to dotfiles, e.g. when
directing the output of printf.

I never noticed the issue myself, since I use dash.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 11:53:32 +01:00
Leah Rowe da108d1c04 mk: Don't run mkhelpers if mode is set
If the mode string is empty, then it's a build command.

See commit:

commit b1ea416575
Author: Leah Rowe <leah@libreboot.org>
Date:   Wed Apr 23 03:54:08 2025 +0100

    mk: remove mkhelp() and use x_() instead

This commit removed the following check:

If mode isn't set, run an mkhelper, otherwise don't.

Because this simplification removed that behaviour,
running e.g. "./mk -m coreboot x200_8mb" would result
in the mkcorebootbin function being executed, which is
normally putting the coreboot rom together.

Since it wasn't built in this case, an error is thrown.
This change therefore restores the previous behaviour,
fixing the bug.

First reported in this error report:
https://codeberg.org/libreboot/lbmk/issues/306

This commit fixes the issue.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 11:25:39 +01:00
Leah Rowe 71a58a38ab mk: condense main() again
i prefer it this way. this reverses the change that
i made a few revisions ago

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 23:07:25 +01:00
Leah Rowe f3882b9bf2 init.sh: make git name/email error more useful
instruct the user what to do in these conditions

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 23:02:04 +01:00
Leah Rowe 9cebda333d init.sh: move git name/mail check to xbmk_git_init
the command -v check has been removed, since this function
already calls git immediately, which would accomplish the
same thing since that causes an error if git isn't there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:54:43 +01:00
Leah Rowe ea081adc4c init.sh: tidy up the git name/email check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:51:56 +01:00
Leah Rowe 3292bded69 mk: make main() more readable
now that main is so small, some of the condensed
lines can be loosened up.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:46:30 +01:00
Leah Rowe 97a5e3d15e mk: move git check to init.sh xbmk_set_version
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:44:11 +01:00
Leah Rowe 11cd952060 init.sh: tidy up xbmk_init()
more version-related code moved to xbmk_set_version

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:41:05 +01:00
Leah Rowe f6c5c8d396 mk: move git_init to init.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:35:45 +01:00
Leah Rowe ec1c92238c init.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:23:37 +01:00
Leah Rowe e009f09e7f init.sh: clean up setvars
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:11:52 +01:00
Leah Rowe 9ec7215340 init.sh setvars: make err a printf for eval
setvars is always invoked with eval, so make the error
condition a message for eval, to ensure that it is reliably
handled, in case of error condition.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:07:52 +01:00
Leah Rowe 18ad654a1f init.sh: merge xbmk_child_init with xbmk_init
the for loop at the end of xbmk_init does essentially
the same thing. adapt accordingly, and merge.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:02:26 +01:00
Leah Rowe 1526820247 init.sh: split xbmk_child_init into functions
one function, for one task. skeleton functions for
performing multiple tasks. that is the basic coding
style guideline for lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 21:47:28 +01:00
Leah Rowe 0280cd4c0e init.sh: move parent fork to new function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 21:28:13 +01:00
Leah Rowe a0e1d42ff7 init.sh: Provide more complete error info
On initialisation of the child instance, ./mk is
executed, but an error from it won't reveal what
command was actually executed.

This change makes that the case, since x_ does
print the command that caused an error.

This is useful for debugging. However, we don't
want x_ to cause a real exit, because we still
need to handle the lock file from the parent
instance.

Therefore, the first child instance is executed
inside a subshell, and xbmk_rval is set if that
subshell returns non-zero.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 21:18:59 +01:00
Leah Rowe a8f0623efb update uefitool to rev a072527, 26 Apr 2025
This fixes a problem, in that CMake 4.0 dropped compatibility
with CMake version 3.5; UEFIExtract/CMakeLists.txt had the line:

CMAKE_MINIMUM_REQUIRED(VERSION 3.1.0 FATAL_ERROR)

This is lower than 3.5.

The new version has this:

CMAKE_MINIMUM_REQUIRED(VERSION 3.22)

Which is higher than 3.5, in terms of version number.

This brings in the following upstream changes:

* a072527 Convert other uses of 0xABCD back to ABCDh
* a19aead Revert "Update hexadecimal numbers output format from ABCDh to 0xABCD" due to breaking downstream tools
* 7752279 Improve region access settings info for Intel v2 descriptor
* 6f6debb Add volume header info on NumBlocks and Length used to calcualte alternative size of it
* f64ba09 Minor fix for embedded QHexView on Windows
* 2b23bbd Implement Apple developer signing for macOS builds
* 9cc9518 Update hexadecimal numbers output format from ABCDh to 0xABCD
* 73d07cd Add Kaitai-based parser for Dell DVAR store
* c8b7151 Fix minor bug while presenting the EOF elemement of AppleSysF store
* 892111a Add new fields into Intel Microcode header
* 7cea8ee Remove outdated definition of FLASH_PARAMETERS
* c38ed92 Add missing header comments to goto*dialog.h
* 22bb757 Remove PATH_MAX from realpath
* d61d759 Make sure to wrap all uses of kaitai::kstream into try-catch blocks
* 7ef3719 Add initial support for Insyde H2O FlashDeviceMap rev4
* 97a85f9 Add Microsoft LZMA section GUID
* a077743 Bump version numbers
* 07742a5 Update GUID database
* a12be6b Address review comments
* 9719b0c Update copyright and authors in About UEFITool window
* fbf6afd Expand Type column of the report to fit new FlashDeviceMap store and entry types
* 3cb5dc0 Add SLIC pubkey and marker parsers
* fd0faea Add Phoenix CMDB parser
* 01e2e08 Add FFS volume parser for non-AMI NVRAM areas
* 4e2a8f6 Add Intel uCode parser
* 58366f4 Add Insyde Flash Device Map parser
* b98edf6 Add Phoenix EVSA parser
* f989fdf Add Phoenix FlashMap parser
* 4e600eb Add Apple SysF/Diag parser
* 2d6eaa9 Add EDK2 FTW parser
* ca7d4ca Add Insyde FDC parser
* 34904bd Add KaitaiStruct parsing of Phoenix VSS2
* 489b85f Rewrite VSS and VSS2 NVRAM variable parsers in KaitaiStruct
* 2661b8f Remove manual NVRAM parsing, add EDK2 VSS parser written in KaitaiStruct
* d91115f Also sign UEFIFind and UEFIExtract for macOS
* 0fae05c Add adhoc signature to UEFITool on macOS
* 5e6a1c7 Fix CFBundleIdentifier in UEFITool Info.plist
* 8d7e01c Make sure to initialize counterUncData
* b1ad055 Bump version numbers
* 7dd9014 Update GUID database
* 4e3fa58 Update QHexView, build it as a library for Qt6 builds
* 369f101 Enable building ffsparser_fuzzer during CI/CD, improve readUnaligned to silence Clang UBSAN
* ff42cec UEFIExtract: add support for extracting uncompressedData for tree items that have it
* c94f78a Add missing common/LZMA/SDK/C/7zWindows.h
* b5756f9 Revert old patch from common/LZMA/SDK/C/CpuArch.c
* 65fb4a8 Update LZMA SDK to 24.09
* e66bc7d Apply a small patch to common/zlib/gzguts.h to fix a build issue in macOS
* dcf21fa Update built-in zlib to 1.3.1
* 0af36bd Fix an issue with kaitai_regenerate.sh creating backup files on modern macOS
* fd76e89 Update README.md
* 427d8ec Update README.md
* a824260 Add MX77L12850F
* a777f1f Update main.yml
* 5f23377 Update main.yml
* 932120c Use x64 macos-13 runner for FreeBSD in main.yml
* a8c008c Update macos-12 to macos-latest in main.yml
* 6b853f8 Fix SonarCube Scan action version
* 66565a5 Try using new SonarCube scan action
* 371448d Enable long file paths for UEFIFind
* b0cd7fe Update upload-artifacts action to v4
* 4b868bb Remove CodeQL and PVS-Studio from main.yml
* 214b356 Add AMIC A25LQ64 to internal JEDEC ID database
* 0030ea9 Fix findPattern logic when pattern is at the end of the data
* 3441255 fix: add qt version limit to setDesktopFileName
* 941ee6c Set desktop file name to fix the missing icon when running under Wayland
* c550853 Defined ACCESSPERMS for musl
* bf93a5e Bump version numbers
* d03a8f2 Fixing FreeBSD action
* 0a88da1 Update guids.csv
* 6f9a4c0 Fix off-by-one error in parsing IFWI partition table
* e0b1e02 Update main.yml
* 161c697 Update main.yml
* 573452e Update main.yml
* 166c797 add Micron XM25RH128C
* 0e11189 fix a few misspellings
* daf5851 Update README.md
* 1cba371 Update guids.csv
* 4992474 Fix CPD Extension offset (reverts 29915ca)
* 29915ca Fix CPD Manifest's partition offset

The ACCESSPERMS patch has been removed, because upstream
already dealt with this. Libreboot had made the same fix
independently, without realising that upstream also did.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 20:33:12 +01:00
Leah Rowe c698972130 rename include/vendor.sh to inject.sh
this matches cbmk, where inject.sh is the file name

this will make future cherry-picks of lbmk->cbmk easier

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:58:29 +01:00
Leah Rowe 24e488aae5 lib.sh: move _ua to the xbmkget function
don't declare it globally, because it's only used here

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:30:38 +01:00
Leah Rowe 6779d3f991 move variables out of init.sh to others
move them where they are used, or if they are used
in many places, move them to lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:28:49 +01:00
Leah Rowe 848159fa0e lib.sh: rename vendor_checksum
rename it to bad_checksum, so that its use makes more sense

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:21:22 +01:00
Leah Rowe 1de77c6558 lib.sh: move singletree() to git.sh
it is primarily used there, and then in mk,
but only after git.sh is sourced.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:19:36 +01:00
Leah Rowe 703fe44431 lib.sh: move cbfs() to rom.sh
it is only ever used there, so move it there

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:16:40 +01:00
Leah Rowe b57952e90d re-split include/init.sh to lib.sh
move non-init functions to lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:10:01 +01:00
Leah Rowe 8ecb62c662 rename include/lib.sh to init.sh
this is in prep for the next change, where non-init
functions will be moved to another file, again named
include/lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:04:03 +01:00
Leah Rowe ce4381169f lib.sh: introduce more top-down function order
a lot of init code was handled outside of any function. the
coding style used in the rest of the build system has now
been introduced, with xbmk_init being the main function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 18:35:41 +01:00
Leah Rowe 15b64cfebe mk/git.sh: remove tree_depend variable
this was used alongside the xgcc linking, so that coreboot
trees could specify that another tree was to be downloaded.

since this variable will no longer be used, it should be
removed, to avoid dead code bloat.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 12:02:55 +01:00
Leah Rowe 9b8179c0e5 git.sh: remove unused xgcc linking feature
the "xtree" variable is used by projects such as u-boot,
to export a CROSS_COMPILE variable specifying prefix for
gnu compilers, and for building the named coreboot tree.
for example, xtree can be "default", which is then the
coreboot tree downloaded, for use of crossgcc.

however, it is also used to symlink identical versions
of crossgcc between coreboot trees. this latter feature
was only needed for fam15h boards which were previously
split between two mostly identical coreboot trees, that
were later merged into a single tree, and this feature
is therefore no longer used.

remove this dead code, to reduce bloat in the build system.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 11:55:51 +01:00
Leah Rowe 4624c6e536 mk: remove unused variables (ser/xp)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 11:44:33 +01:00
Leah Rowe aba5b3a353 mk: simplify main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 11:30:32 +01:00
Leah Rowe 0ab7c6ff9c lib.sh: use realpath to get sys python on venv
In the previous revision, I make hardcoded use of
/usr/local/bin and /usr/bin as search locations, instead
of relying on PATH, when the user has a python venv, because
in those cases, we cannot rely on PATH so we use a python
command to detect the venv and then force use of the
normal system path for python.

However, there's no guarantee that the real Python will
indeed live at these locations. For example, some distros
like Nix or Guix will use many locations for different
versions of a given package, and it's for the birds as to
what given package version the user might be running.

Therefore, this patch retains that current hardcoded
assumption of /usr/local/bin and /usr/bin but *only* as
a fallback solution, instead checking realpath first.

The "realpath" command isn't technically POSIX standard,
but in practise it is available on GNU coreutils, Busybox,
and the various BSD userlands.

I could perhaps *import* a realpath utility, and use that,
but this should be fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 06:43:49 +01:00
Leah Rowe 8edea026c5 lib.sh: Force use of System Python to prevent hang
If the user has a virtual environment, the current logic
will cause lbmk to hang. A useful workaround is to force
use of the direct path to the system binary of python.

This works by detecting a virtual environment first, and
deferring to the old behaviour if no venv is found. If one
is found, then it will not rely on PATH, but instead only
search the standard locations /usr/local/bin and /usr/bin.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 05:25:28 +01:00
Leah Rowe b1b964fa5c lib.sh: further condense the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:35:18 +01:00
Leah Rowe 9543a325ac lib.sh: further simplify the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:31:40 +01:00
Leah Rowe 9baabed718 lib.sh: condense the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:27:03 +01:00
Leah Rowe 0c5c5ffc87 lib.sh: simplify mk()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:12:53 +01:00
Leah Rowe 83022b6ba8 lib.sh: simplify cbfs()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:11:20 +01:00
Leah Rowe 13ad839691 lib.sh: simplify the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:04:03 +01:00
Leah Rowe b1ea416575 mk: remove mkhelp() and use x_() instead
x_ and mkhelp pretty much do the same thing

in fact, there is no functional difference

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 03:54:08 +01:00
Leah Rowe 4cf64e59ed mk: simplify handling of trees()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 03:49:22 +01:00
Leah Rowe d0581914c7 coreboot/hp8300cmt: purge xhci_overcurrent_mapping
This prevents a build error, as the variable is no longer
used at all by coreboot (EHCI mapping is used as reference
instead).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 10:25:08 +01:00
Leah Rowe cb52fc4ba8 Fix VBT path on HP Elite desktops
Also: hp8300cmt_16mb did not specify a data.vbt path, even
though it is indeed available in the coreboot tree. This
has been corrected.

The previous lack of VBT on hp8300cmt_16mb wasn't really a
big problem, since coreboot handles initialisation anyway,
and it's basically optional on Linux. Coreboot doesn't parse
VBT at all.

This patch should fix build errors, that were caused on the
recent revision update, where several of the HP desktops
have now been turned into variants.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 07:51:49 +01:00
Leah Rowe 2bee87cfc2 lib.sh: add missing copyright year
alper made a fix to this file a few hours ago, but
forgot to update the copyright header

i'm doing it for alper, as a courtesy

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 04:01:31 +01:00
Leah Rowe 4b7ab403c6 ifd/q45t_am: unlock regions by default
i used ifdtool --unlock to do this

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 03:25:51 +01:00
Leah Rowe 564155277e coreboot/g43t_am3: use ifd-based setup
no-ME setup. with a gbe file. we previously made this
a descriptorless setup.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 03:24:38 +01:00
Leah Rowe 0ddd196375 coreboot/q45t_am3: use ifd-based setup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 02:44:33 +01:00
Leah Rowe 3b2d933842 coreboot/default: add missing submodules
due to a rule in .gitignore, these were ignored, because it
ignores .tar.xz entries in git status

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 01:59:05 +01:00
Leah Rowe a10d81399c NEW MAINBOARD: Acer Q45T-AM (G43T-AM3 variant)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 00:16:08 +01:00
Leah Rowe d114e0a765 mk: don't print confirmation of git pkg.cfg
otherwise, the "list" commands include such text,
where they should not.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 00:09:27 +01:00
Leah Rowe f59c24f12a coreboot/g43t_am3: fix data.vbt path
this board became a variant, in the new coreboot revision that
lbmk recently updated to. fix the data.vbt path to prevent error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 00:06:29 +01:00
Leah Rowe 21020fa319 add missing config/data/coreboot/0
this is a file containing one byte, of value zero

i meant to add it in previous commits, for the resizing
and shrinking of tarballs when inserting or deleting
vendor files

used by include/vendor.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-21 21:24:53 +01:00
Leah Rowe 2b4629d790 Merge pull request 'lib.sh: Fix python3 detection when 'python' is python2' (#290) from alpernebbi/lbmk:python3-detection-fix into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/290
2025-04-21 14:52:28 +00:00
Alper Nebi Yasak a18d287a81 lib.sh: Fix python3 detection when 'python' is python2
Properly set $pyver to "3" when we detect we can use python3. In the
following version checks, use the $python we detected instead of a
'python' from PATH because the latter might be a python2 while still
co-existing with a python3.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-21 17:45:25 +03:00
Leah Rowe c7569a6714 coreboot/next: merge with coreboot/default
I also cherry-picked a patch from Heads, that fixes build
issues caused by the hacks in the T480 port; several changes
made by Mate are now ifdef'd based on whether a KabyLake
ThinkPad is specified in defconfig.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-21 06:38:30 +01:00
Leah Rowe 762c7ff43e coreboot/default: Update, c247f62749b (8 Feb 2025)
This is currently the latest revision of coreboot.

Other coreboot trees to follow. The "next" tree will
also be merged with coreboot/default, in a follow-up
commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-21 03:26:54 +01:00
Leah Rowe 86e7aa80c5 Update the GRUB revisions
A number of regressions were caused by the recent CVE fixes,
many of which have since been fixed upstream. This includes
several ext4 file system bugs, which caused some systems not
to boot properly, when dealing with very large initramfs files.

No additional patching has been made. This will be tested, and
then used to provide a revision update for Libreboot 20241206.

After this, there are several additional OOT patches that will
be merged, for the next *testing release* of Libreboot.

Update to this revision, for all GRUB trees:
a4da71dafeea519b034beb159dfe80c486c2107c

This brings in the following changes from upstream:
* a4da71daf util/grub-install: Include raid5rec module for RAID 4 as well
* 223fcf808 loader/ia64/efi/linux: Reset grub_errno on failure to allocate
* 6504a8d4b lib/datetime: Specify license in emu module
* 8fef533cf configure: Add -mno-relax on riscv*
* 1fe094855 docs: Document the long options of tpm2_key_protect_init
* 6252eb97c INSTALL: Document the packages needed for TPM2 key protector tests
* 9d4b382aa docs: Update NV index mode of TPM2 key protector
* 2043b6899 tests/tpm2_key_protector_test: Add more NV index mode tests
* 9f66a4719 tests/tpm2_key_protector_test: Reset "ret" on fail
* b7d89e667 tests/tpm2_key_protector_test: Simplify the NV index mode test
* 5934bf51c util/grub-protect: Support NV index mode
* cd9cb944d tpm2_key_protector: Support NV index handles
* fa69deac5 tpm2_key_protector: Unseal key from a buffer
* 75c480885 tss2: Add TPM 2.0 NV index commands
* 041164d00 tss2: Fix the missing authCommand
* 46c9f3a8d tpm2_key_protector: Add tpm2_dump_pcr command
* 617dab9e4 tpm2_key_protector: Dump PCRs on policy fail
* 204a6ddfb loader/i386/linux: Update linux_kernel_params to match upstream
* 6b64f297e loader/xnu: Fix memory leak
* f94d257e8 fs/btrfs: Fix memory leaks
* 81146fb62 loader/i386/linux: Fix resource leak
* 1d0059447 lib/reloacator: Fix memory leaks
* f3f1fcecd disk/ldm: Fix memory leaks
* aae2ea619 fs/ntfs: Fix NULL pointer dereference and possible infinite loop
* 3b25e494d net/drivers/ieee1275/ofnet: Add missing grub_malloc()
* fee6081ec kern/ieee1275/init: Increase MIN_RMA size for CAS negotiation on PowerPC machines
* b66c6f918 fs/zfs: Fix a number of memory leaks in ZFS code
* 1d59f39b5 tests/util/grub-shell: Remove the work directory on successful run and debug is not on
* e0116f3bd tests/grub_cmd_cryptomount: Remove temporary directories if successful and debug is not on
* e6e2b73db tests/grub_cmd_cryptomount: Default TMPDIR to /tmp
* 32b02bb92 tests/grub_cmd_cryptomount: Cleanup the cryptsetup script unless debug is enabled
* c188ca5d5 tests: Cleanup generated files on expected failure in grub_cmd_cryptomount
* 50320c093 tests/util/grub-shell-luks-tester: Add missing line to create RET variable in cleanup
* bb6d3199b tests/util/grub-shell-luks-tester: Find cryptodisk by UUID
* 3fd163e45 tests/util/grub-shell: Default qemuopts to envvar $GRUB_QEMU_OPTS
* ff7f55307 disk/lvm: Add informational messages in error cases of ignored features
* a16b4304a disk/lvm: Add support for cachevol LV
* 9a37d6114 disk/lvm: Add support for integrity LV
* 6c14b87d6 lvm: Match all LVM segments before validation
* d34b9120e disk/lvm: Remove unused cache_pool
* 90848a1f7 disk/lvm: Make cache_lv more generic as ignored_feature_lv
* 488ac8bda commands/ls: Add directory header for dir args
* 096bf59e4 commands/ls: Print full paths for file args
* 90288fc48 commands/ls: Output path for single file arguments given with path
* 6337d84af commands/ls: Show modification time for file paths
* cbfb031b1 commands/ls: Merge print_files_long() and print_files() into print_file()
* 112d2069c commands/ls: Return proper GRUB_ERR_* for functions returning type grub_err_t
* da9740cd5 commands/acpi: Use options enum to index command options
* 1acf11fe4 docs: Capture additional commands restricted by lockdown
* 6a168afd3 docs: Document restricted filesystems in lockdown
* be0ae9583 loader/i386/bsd: Fix type passed for the kernel
* ee27f07a6 kern/partition: Unbreak support for nested partitions
* cb639acea lib/tss2/tss2_structs.h: Fix clang build - remove duplicate typedef
* 696e35b7f include/grub/mm.h: Remove duplicate inclusion of grub/err.h
* 187338f1a script/execute: Don't let trailing blank lines determine the return code
* ff173a1c0 gitignore: Ignore generated files from libtasn
* fbcc38891 util/grub.d/30_os-prober.in: Conditionally show or hide chain and efi menu entries
* 56ccc5ed5 util/grub.d/30_os-prober.in: Fix GRUB_OS_PROBER_SKIP_LIST for non-EFI
* 01f064064 docs: Do not reference non-existent --dumb option
* 3f440b5a5 docs: Replace @lbracechar{} and @rbracechar{} with @{ and @}
* f20988738 fs/xfs: Fix grub_xfs_iterate_dir() return value in case of failure
* 1ed2628b5 fs/xfs: Add new superblock features added in Linux 6.12/6.13
* 348cd416a fs/ext2: Rework out-of-bounds read for inline and external extents
* c730eddd2 disk/ahci: Remove conditional operator for endtime
* f0a08324d term/ns8250-spcr: Return if redirection is disabled
* 7161e2437 commands/file: Fix NULL dereference in the knetbsd tests
* 11b9c2dd0 gdb_helper: Typo hueristic
* 224aefd05 kern/efi/mm: Reset grub_mm_add_region_fn after ExitBootServices() call
* 531750f7b i386/tsc: The GRUB menu gets stuck due to unserialized rdtsc
* f2a1f66e7 kern/i386/tsc_pmtimer: The GRUB menu gets stuck due to failed calibration
* 13f005ed8 loader/i386/linux: Fix cleanup if kernel doesn't support 64-bit addressing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-20 05:43:53 +01:00
Leah Rowe 8d57bf6009 Revert "git.sh: minor cleanup"
This reverts commit e63d8dd20d.
2025-04-18 02:25:16 +01:00
Leah Rowe a2898771f6 lib.sh: perform root check even earlier
initialising variables, setting PWD, setting version,
this is all unnecessary before the root check, because
the dependencies commands use none of these.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 02:17:53 +01:00
Leah Rowe 779f600342 lib.sh: tidy up opening logic (put it together)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 02:10:49 +01:00
Leah Rowe bac4be99c2 lib.sh: do root check before python check
we don't need python before the root check

principle of least privilege

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 02:02:10 +01:00
Leah Rowe e63d8dd20d git.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 01:52:44 +01:00
Leah Rowe 11078508a2 lib.sh: simplify mktarball()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 01:33:45 +01:00
Leah Rowe 087bbedc5f vendor.sh: tidy up vendor_download()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:35:48 +01:00
Leah Rowe e11fd52d95 mk: tidy up check_gnu_path()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:27:33 +01:00
Leah Rowe 3442f4278e mk: simplify check_project_hashes()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:23:32 +01:00
Leah Rowe 6b6a0fa607 lib.sh: fix missing s/TMPDIR/xbmktmp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:17:11 +01:00
Leah Rowe e07a2adb13 lbmk: don't handle TMPDIR directly
lbmk creates TMPDIR as /tmp/xbmk_*, but it's theoretically
possible that something could re-export it by mistake.

this change retains the same initialisation, but further
use is now via a new variable "xbmktmp", that stores the
value of TMPDIR upon lbmk's initialisation of it.

this reduces the chance of such a bug in the future, as
described above, so it is a preemptive/preventative fix.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 23:43:22 +01:00
Leah Rowe 9d3b52cd1d rom.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 23:31:26 +01:00
Leah Rowe b4402c5425 vendor.sh: yet even more code cleanup
code equals bugs. code that doesn't exist can't
have bugs, so it is superior by definition.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 23:04:14 +01:00
Leah Rowe fe5bdc7633 vendor.sh: even more cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 22:09:05 +01:00
Leah Rowe fcedb17a9a vendor.sh: more cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:38:20 +01:00
Leah Rowe 4e2b59ed3f vendor.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:20:14 +01:00
Leah Rowe a3acf4c3f9 vendor.sh: simplify process_release_roms
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:11:55 +01:00
Leah Rowe 30213a9688 vendor.sh: remove unnecessary check
the next part checks whether the file is below 512k,
so there's no point checking if it's below 2, because
the lowest a file size can be is zero, and expr will
produce a result of -1 if decrementing from zero.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:04:51 +01:00
Leah Rowe 38df7275f1 git.sh: remove unnecessary comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 17:14:11 +01:00
Leah Rowe f5891fb699 git.sh: remove link_crossgcc()
merge it with git_prep

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 17:10:19 +01:00
Leah Rowe a685654b90 git.sh: remove move_repo()
merge it with git_prep, since it's only a small
function and only called from there. the merged
code still makes sense and its purpose is still
quite clear on casual reading.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 16:54:59 +01:00
Leah Rowe e4aa62f79a git.sh: remove prep_submodule()
merge it with git_prep, since it's only a tiny
function and only called from there. the for
loop moved to the if block still makes sense
on casual reading.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 16:45:00 +01:00
Leah Rowe 2839feb9e4 git.sh: make git_prep command clearer
the "u" argument can actually be any thing. git_prep
handles git submodules only for single-tree projects,
under any candition, or on multi-tree projects if
the number of arguments to git_prep is above four.

"u" is the 5th argument, meant to enable submodule
downloads. it really doesn't matter what this string
says, so let's just make it as clear as possible.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 16:32:21 +01:00
Leah Rowe 410fa702c9 mrc.sh: Make proper use of variable inside printf
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 05:06:21 +01:00
Leah Rowe 075902c3ea simplify a few file checks
the combination of x_ with the "e" function enables
for much simpler file-check error handling, which is
a unique innovation of lbmk as it pertains to sh.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 04:49:17 +01:00
Leah Rowe b2255425eb rom.sh: remove unnecessary check
the cbfs function will call cbfstool, which will perform
the same check, and the same error condition would cause
the same exit behaviour in lbmk. the error message would
also provide output that is just as useful for debugging.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 04:22:25 +01:00
Leah Rowe 39640d76a7 lbmk: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 04:22:03 +01:00
Leah Rowe c8dc701f3e lib.sh mktarball: stricter tar error handling
There was no error handling, *at all*, on the actual tar
command, due to the lack of set -o pipefail, which we cannot
rely on in sh.

The x_ wrapper can be used in this case, as a mitigation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-16 00:57:54 +01:00
Leah Rowe 58a53d7046 vendor.sh: don't err on bruteforce me extract
it wouldn't exit with error status anyway, since i'm
setting +e here, but if that accidentally changed in
the future, i still wouldn't want this to exit.

the bruteforce me extraction naturally throws a lot of
errors, hence +e, because of how the extraction works,
but the result is checked at the end of the process,
to compensate. hence +e, because otherwise this brute
force extraction would never work.

therefore, this is an extremely theoretical bug fix, the
most quintessential of preemptive bug fixes, to the point
that it is actually rather pedantic.

The ":" in "|| :" will likely *never* be executed, but it
handles the theoretical case where the subshell exits with
non-zero status and +e is set; subshells aren't meant to
behave this way anyway, but who knows what cursed sh
implementation the user is on?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 17:58:59 +01:00
Leah Rowe 958fa34832 mk check_project_hashes: handle error on sha512sum
We can't do set -o pipefail in POSIX sh, which we're using,
but the build system has x_ which wraps around a command
and executes it, exiting with non-zero status if it does.

This fact enables lbmk to have functionality that is actually
superior to pipefail, since you can more easily control
specifically which parts error.

For example:

foo | bar | foo2 | bar2 | $err "error"

ERROR exits with non-zero status, but foo2, bar and foo
would not exit on error, only bar2 would. In *bash*, which
we avoid, set -o pipefail would make all of them exit on
error, but what if you wanted "bar" to not exit?

With lbmk, you could do, in the above example, and with the
above question asked ("what if you wanted bar not to exit"):

x_ foo | bar | x_ foo2 | bar2 > file | $err "error"

of course, you could also do, if not outputting to "file":

x_ foo | bar | x_ foo2 | x_ bar2

NOTE: in lbmk, $err is a variable containing the name of
a function that does something (whatever you want) and
then exits with non-zero status.

This entire explanation is beyond the scope of simply
providing (and explaining) this fix, but I also wanted to
use this commit as an example of the power of lbmk with
regards to POSIX shell scripting.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 17:08:25 +01:00
Leah Rowe 8b4b069e3f vendor.sh: remove unnecessary xchanged="y"
in these if clauses, what follows afterward is exactly
the same: set xchanged and return.

Therefore, these lines are redundant and they can be
removed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 15:53:36 +01:00
Leah Rowe 166dbb04c9 vendor.sh: set need_files="n" if skipping patch
This change finally ensures that no insertions will be
attempted, on the basis that readkconfig failed; this
covers the instance whereby vcfg was set, but no scanned
items were indicated e.g. Intel ME files not specified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 15:49:10 +01:00
Leah Rowe e90657cc73 vendor.sh: Don't handle vendor files if not needed
This should speed up automated tests. Otherwise, it goes
through all the extra checks that aren't needed, for each
individual type of vendor file, and also errors out when
handling pico serprog images; during automated testing,
on the bin directory, you might try on every tarball, one
of which is the pico tarball and this patch makes lbmk skip
that one too.

In general, we must not perform unnecessary tasks. Doing so
may even cause other bugs that we couldn't easily detect.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 14:09:31 +01:00
Leah Rowe 2e10a45fa3 Revert "lib.sh: use eval for the command in x_"
This reverts commit 3bfdecdc75.

The commit that this reverses, caused sch5545 ec firmware
downloads to fail, due to globbing.
2025-04-13 05:15:13 +01:00
Leah Rowe 738d4bb6b6 lib.sh: fix bad eval writing resized file
x_ cannot be used, where output is redirectod to a file;
only the conventional piping can be used.

same as the last change. this and the other fix were caught
during testing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 04:02:34 +01:00
Leah Rowe eb9e5d2d5d lib.sh: fix bad eval writing version/versiondate
x_ cannot be used, where output is redirected to a file;
only the convention piping can be used, for errors.

relying on x_ in these cases will cause unpredictable bugs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 03:57:04 +01:00
Leah Rowe 3bfdecdc75 lib.sh: use eval for the command in x_
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 02:31:25 +01:00
Leah Rowe 4fa3bb9e5b mk: use eval to run mkhelp commands
directly quoting it and running it quoted means
that the shell way try to execute it as a file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 02:25:01 +01:00
Leah Rowe 9b3635718a mk: tidy up the switch/case block in main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:43:28 +01:00
Leah Rowe 0c381028ab mk: tidier error handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 023f9cf049 lib.sh: tidy up the error handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe cb3253befb rom.sh: tidy up error handling
same as the last change

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 7af46721bc vendor.sh: tidy up error handling
x_ can be used nowadays on any function, because it
properly handles globbing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 04ebb3b91a vendor.sh: tidy up decat_fspfd()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 0c87fdf96a git.sh: clean up fetch_project()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 9eb8856b3c mk: Remove unnecessary argument checks on trees()
These checks are no longer necessary, because these
checks are already properly handled in main().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 52f3d54116 vendor.sh: properly call err_ in fail_inject
i can't call $err (variable), because it's set
to fail_inject. fix this infinite loop, which
was an oversight in the previous commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 20:19:48 +01:00
Leah Rowe c4c6692b76 remove xbmk_parent, handle forking in lib.sh
I was using a complicated method of knowing whether
the current instance was parent or a child, to know
whether the lock file and TMPDIR needed to be purged.

It was quite error-prone too. Instead, I'm now handling
it directly from within the if statement that previously
initialised xbmk_parent=y, forking ./mk from there.

The forked instance would not trigger that if clause
again, since then TMPDIR is created, thus avoiding
recursion.

This is an improvement because it doesn't rely on how
the parent handles exit statuses, and it ensures that
the lock/tmp files are never accidentally deleted.

Even if a given program/script that lbmk runs would
export TMPDIR, it doesn't matter because lbmk doesn't,
so it would be unaffected.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 20:03:40 +01:00
Leah Rowe fd5431db05 lib.sh: define x_ right after err_
because the top-down function order isn't as reliable
in lib.sh, since this is what first runs, included
in every other script

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:40:51 +01:00
Leah Rowe 972681a127 mk: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:38:14 +01:00
Leah Rowe b41cd39b68 lib.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:35:30 +01:00
Leah Rowe 4993950264 mrc.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:32:18 +01:00
Leah Rowe c158d82298 rom.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:29:35 +01:00
Leah Rowe cb36248c8c vendor.sh: tidy up check_release()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:10:49 +01:00
Leah Rowe 409cab39c5 vendor.sh: tidy up vendor_inject()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:08:30 +01:00
Leah Rowe 12b1623e47 vendor.sh: tidy up readcfg()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:05:12 +01:00
Leah Rowe 0d85f061e2 vendor.sh: tidy up patch_release_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:02:07 +01:00
Leah Rowe 61f2014102 vendor.sh: tidy up process_release_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:57:29 +01:00
Leah Rowe 5901f36e49 vendor.sh: tidy up patch_rom()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:53:34 +01:00
Leah Rowe 082930ce0e vendor.sh: tidy up inject()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:50:54 +01:00
Leah Rowe e1f91f3037 vendor.sh: tidy up modify_mac_addresses()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:43:59 +01:00
Leah Rowe 3181ac5012 script/trees: merge with mk and delete script/
script/ no longer exists. this means that the
only executable script in lbmk is now mk.

script/trees was never called directly; instead,
we used ./update trees in the past, then just ./mk.

this is part of a larger audit to simplify lbmk,
in preparation for the next Libreboot release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 14:46:09 +01:00
Leah Rowe 3d03dd1a50 mk: remove the legacy "roms" command
we don't need it. the documentation only tells you
now to run ./mk -b coreboot target1 target2 etc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 14:24:10 +01:00
Leah Rowe f0c629dcc6 lib.sh: write version/versiondate to dotfiles
write to .version and .versiondate, instead
of version and versiondate.

this will hide them to avoid visual clutter while
analysing files within lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:51:49 +01:00
Leah Rowe 23b942c83e lib.sh: hardcode projectname/projectsite
remove the corresponding files, containing these strings

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:44:05 +01:00
Leah Rowe a03bb793ae remove update/vendor symlinks
these are obsolete commands for backward compatibility,
but they are being removed before the next release.

the documentation has for some now only referenced use
of the ./mk commands, making lbmk live up to its name!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:37:21 +01:00
Leah Rowe d7f80ebe71 move build to mk
i'm removing all the backward-compatibility in the
build system, so that only the ./mk command is available

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:32:34 +01:00
Leah Rowe 57d58527fd trees: unify the execution of mkhelper commands
provide it in a new function: mkhelp()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:20:16 +01:00
Leah Rowe e5262da4be trees: tidy up configure_project()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:07:27 +01:00
Leah Rowe 5179827839 build: make coreboot building an else in "roms"
Otherwise, the current return prevents set -u -e
after the case/switch block, which is a problem if
set +u +e was done at any point before the return.

Remove the return in the roms) section of the case/switch
block, and make the building of coreboot images part of
an else clause.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 12:58:28 +01:00
Leah Rowe c189257888 trees: don't build dependencies if dry=":"
build_depend is already blanked anyway, but it can't
hurt to have an extra check here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:28:14 +01:00
Leah Rowe 115a66fddd trees: unified handling of flags
this way, the error message will never be incorrect,
which i had to fix in a recent patch.

now, the same string is used for error messages and getopt.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:18:15 +01:00
Leah Rowe 3ea633cc79 trees: simplified handling of badhash/do_make
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:15:53 +01:00
Leah Rowe 9be40e94a2 trees: don't set mode on ./mk -b
mode is already initialised as an empty string

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:15:53 +01:00
Leah Rowe 67ad7c2635 trees: don't set mod on ./mk -d
mode is already initialised as an empty string

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:15:53 +01:00
Leah Rowe 2444894841 trees: don't initialise mode to "all"
this is not necessary. the fetch mode is still handled,
as before, and no make commands will run in this case.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 01:45:36 +01:00
Leah Rowe 97c50a39a6 trees: clean up some comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 01:45:10 +01:00
Leah Rowe cfb14fd8dd vendor.sh: simplified readkconfig()
So much bloat

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 01:13:05 +01:00
Leah Rowe 5b697b93a2 lib.sh: double-quote pwd to prevent globbing
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 20:11:51 +01:00
Leah Rowe 5a0a24f555 lbmk: unified PWD handling (work directory)
instead of running pwd all the time, run it once in lib.sh,
and export PWD.

for lbmk-specific use of PWD, use xbmkpwd, which contains
the value of PWD as was set by the pwd utility in lib.sh.

many parts of lbmk rely on pwd, and it *must* be correct.
this change adds basic error handling, since pwd can in
fact return errors in some cases.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 20:04:53 +01:00
Leah Rowe a25a29cfbb lib.sh: initialise PATH if it's unset
it's incorrect for PATH not to be set, but some users
may foolishly blank it out before running lbmk.

prevent such issues, by initialising it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 19:31:26 +01:00
Leah Rowe 1022abf699 move XBMKPATH to include/lib.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 19:22:23 +01:00
Leah Rowe 0764c969a2 lbmk: use pwd util, not PWD environmental variable
PWD could be anything, if the user manually exported
it before running lbmk.

always run pwd instead, to get the real string.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 17:52:18 +01:00
Leah Rowe f98b9b0110 clean up a few semicolons in the build system
several code lines were condensed together, which
make them less readable. make the code more readable
by having separate commands on separate lines.

i previously did this during my manic build system
audits of 2023 and 2024; condensing lines like this
is overly pedantic and serves no real purpose.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 17:15:00 +01:00
Leah Rowe 8ccb61cc71 trees: err if first argument is not a flag
E.g. ./mk -f coreboot is valid

./mk coreboot -f is not valid

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:24:51 +01:00
Leah Rowe 947c3e1a17 trees: err if no argument given
We were already covering this from the main build
script, but it's good to also check it here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:24:19 +01:00
Leah Rowe edbbde0b12 trees: set dry=":" on ./mk -f
We don't want any build commands to run, when
the -f flag is used.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:11:24 +01:00
Leah Rowe 33bb0ecf76 trees: clean up initialisation of the dry variable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:10:42 +01:00
Leah Rowe c7636ff1df trees: initialise mode to "all", not ""
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 13:39:55 +01:00
Leah Rowe d0bd12631a trees: don't abuse the mode variable on -f
The "mode" variable is used as a suffix for make commands,
for example ./mk -m sets mode to "menuconfig", which means
you want to run "make menuconfig".

When fetching sources (./mk -f), I was setting mode to "fetch",
and putting checks in code to avoid use of make when mode was
set to "fetch".

The behaviour now is identical, except that a new variable
called "do_make" is set to "n" when doing ./mk -f, otherwise
set to "y", and this is checked instead. This should make
the meaning of the code somewhat clearer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 04:47:04 +01:00
Leah Rowe c4cd876c60 trees: Add missing flag to error output
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-09 09:38:59 +01:00
Leah Rowe 5ebcae5235 lbmk: minor code formatting cleanup
some lines were needlessly condensed, and less readable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-06 23:17:33 +01:00
Leah Rowe 70cef71dba grub/xhci: Remove unused patch
I was importing a patch for the z790 boards, but
Libreboot doesn't support this board yet, and the
patch was a hack that may affect other boards.

When I do later merge that board, and I find that the
hack is needed, I'll simply make another grub tree
within lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-04 13:57:09 +01:00
Leah Rowe 3f14a470a2 remove _fsp targets (keep _vfsp)
_fsp is obsolete. people should use _vfsp

_fsp was kept for a short while, for backward compatibility,
but nobody really uses it now and it just causes confusion

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-01 08:45:41 +01:00
Leah Rowe d7312260e7 util/nvmutil: remove excessive comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-25 13:29:16 +00:00
Leah Rowe e348ea0381 Bump GRUB revision to add 73 security patches
You can find information about these patches here:
https://lists.gnu.org/archive/html/grub-devel/2025-02/msg00024.html

GRUB has been on a crusade as of late, to proactively audit
and fix many security vulnerabilities. This lbmk change brings
in a comprehensive series of patches that fix bugs ranging from
possible buffer overflows, use-after frees, null derefs and so on.

These changes are critical, so a revision release *will* be issued,
for the Libreboot 20241206 release series.

This change imports the following 73 patches which
are present on the upstream GRUB repository (commit IDs
matched to upstream):

* 4dc616657 loader/i386/bsd: Use safe math to avoid underflow
* 490a6ab71 loader/i386/linux: Cast left shift to grub_uint32_t
* a8d6b0633 kern/misc: Add sanity check after grub_strtoul() call
* 8e6e87e79 kern/partition: Add sanity check after grub_strtoul() call
* 5b36a5210 normal/menu: Use safe math to avoid an integer overflow
* 9907d9c27 bus/usb/ehci: Define GRUB_EHCI_TOGGLE as grub_uint32_t
* f8795cde2 misc: Ensure consistent overflow error messages
* 66733f7c7 osdep/unix/getroot: Fix potential underflow
* d13b6e8eb script/execute: Fix potential underflow and NULL dereference
* e3c578a56 fs/sfs: Check if allocated memory is NULL
* 1c06ec900 net: Check if returned pointer for allocated memory is NULL
* dee2c14fd net: Prevent overflows when allocating memory for arrays
* 4beeff8a3 net: Use safe math macros to prevent overflows
* dd6a4c8d1 fs/zfs: Add missing NULL check after grub_strdup() call
* 13065f69d fs/zfs: Check if returned pointer for allocated memory is NULL
* 7f38e32c7 fs/zfs: Prevent overflows when allocating memory for arrays
* 88e491a0f fs/zfs: Use safe math macros to prevent overflows
* cde9f7f33 fs: Prevent overflows when assigning returned values from read_number()
* 84bc0a9a6 fs: Prevent overflows when allocating memory for arrays
* 6608163b0 fs: Use safe math macros to prevent overflows
* fbaddcca5 disk/ieee1275/ofdisk: Call grub_ieee1275_close() when grub_malloc() fails
* 33bd6b5ac disk: Check if returned pointer for allocated memory is NULL
* d8151f983 disk: Prevent overflows when allocating memory for arrays
* c407724da disk: Use safe math macros to prevent overflows
* c4bc55da2 fs: Disable many filesystems under lockdown
* 26db66050 fs/bfs: Disable under lockdown
* 5f31164ae commands/hexdump: Disable memory reading in lockdown mode
* 340e4d058 commands/memrw: Disable memory reading in lockdown mode
* 34824806a commands/minicmd: Block the dump command in lockdown mode
* c68b7d236 commands/test: Stack overflow due to unlimited recursion depth
* dad8f5029 commands/read: Fix an integer overflow when supplying more than 2^31 characters
* b970a5ed9 gettext: Integer overflow leads to heap OOB write
* 09bd6eb58 gettext: Integer overflow leads to heap OOB write or read
* 7580addfc gettext: Remove variables hooks on module unload
* 9c1619773 normal: Remove variables hooks on module unload
* 2123c5bca commands/pgp: Unregister the "check_signatures" hooks on module unload
* 0bf56bce4 commands/ls: Fix NULL dereference
* 05be856a8 commands/extcmd: Missing check for failed allocation
* 98ad84328 kern/dl: Check for the SHF_INFO_LINK flag in grub_dl_relocate_symbols()
* d72208423 kern/dl: Use correct segment in grub_dl_set_mem_attrs()
* 500e5fdd8 kern/dl: Fix for an integer overflow in grub_dl_ref()
* 2c34af908 video/readers/jpeg: Do not permit duplicate SOF0 markers in JPEG
* 0707accab net/tftp: Fix stack buffer overflow in tftp_open()
* 5eef88152 net: Fix OOB write in grub_net_search_config_file()
* aa8b4d7fa net: Remove variables hooks when interface is unregisted
* a1dd8e59d net: Unregister net_default_ip and net_default_mac variables hooks on unload
* d8a937cca script/execute: Limit the recursion depth
* 8a7103fdd kern/partition: Limit recursion in part_iterate()
* 18212f064 kern/disk: Limit recursion depth
* 67f70f70a disk/loopback: Reference tracking for the loopback
* 13febd78d disk/cryptodisk: Require authentication after TPM unlock for CLI access
* 16f196874 kern/file: Implement filesystem reference counting
* a79106872 kern/file: Ensure file->data is set
* d1d6b7ea5 fs/xfs: Ensuring failing to mount sets a grub_errno
* 6ccc77b59 fs/xfs: Fix out-of-bounds read
* 067b6d225 fs/ntfs: Implement attribute verification
* 048777bc2 fs/ntfs: Use a helper function to access attributes
* 237a71184 fs/ntfs: Track the end of the MFT attribute buffer
* aff263187 fs/ntfs: Fix out-of-bounds read
* 7e2f750f0 fs/ext2: Fix out-of-bounds read for inline extents
* edd995a26 fs/jfs: Inconsistent signed/unsigned types usage in return values
* bd999310f fs/jfs: Use full 40 bits offset and address for a data extent
* ab09fd053 fs/jfs: Fix OOB read caused by invalid dir slot index
* 66175696f fs/jfs: Fix OOB read in jfs_getent()
* 1443833a9 fs/iso9660: Fix invalid free
* 965db5970 fs/iso9660: Set a grub_errno if mount fails
* f7c070a2e fs/hfsplus: Set a grub_errno if mount fails
* 563436258 fs/f2fs: Set a grub_errno if mount fails
* 0087bc690 fs/tar: Integer overflow leads to heap OOB write
* 2c8ac08c9 fs/tar: Initialize name in grub_cpio_find_file()
* 417547c10 fs/hfs: Fix stack OOB write with grub_strcpy()
* c1a291b01 fs/ufs: Fix a heap OOB write
* ea703528a misc: Implement grub_strlcpy()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-19 21:26:23 +00:00
Leah Rowe 4b228c11f9 Merge pull request 'Update pico-serprog revision' (#271) from Riku_V/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/271
2025-02-12 21:20:17 +00:00
Riku Viitanen a8359e30b2 Update pico-serprog revision
Most importantly this should fix issues with rp2350 boards
not synchronizing properly.

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2025-02-12 22:19:11 +02:00
Leah Rowe d2cb954933 util/nvmutil: Fix bad error messages on R/W
The messages didn't really make sense.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-10 20:27:48 +00:00
Leah Rowe e1e515bd22 util/nvmutil: hardened pledge on help output
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-07 12:31:46 +00:00
Leah Rowe ada057a865 Merge pull request 'Simplify the README' (#269) from runxiyu/lbmk:readme-simplification into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/269
2025-02-02 10:32:39 +00:00
runxiyu 9ced146b47 README.md: Use newlines instead of bulleted list for docs/support links
I think newlines look better here. The indent that bullet-pointed lists
have, does not seem natural at the start of the document.

Signed-off-by: runxiyu <me@runxiyu.org>
2025-02-02 07:56:24 +00:00
Runxi Yu 266122592c README.md: Use the EFF's page on Right to Repair 2025-02-02 15:19:26 +08:00
Runxi Yu e36aa8c5a5 README.md: Vastly simplify it 2025-02-01 00:18:31 +08:00
Runxi Yu c17f4381ce README.md: Mention SeaBIOS and U-Boot instead of Tianocore as payloads
SeaBIOS has been supported for a long time and seems to be the
"recommended" payload nowadays (though usually with GRUB too). I haven't
seen Tianocore / EDK II been mentioned in a while. U-Boot support was
added as of Libreboot 20241206-rev8.

Signed-off-by: Runxi Yu <me@runxiyu.org>
2025-02-01 00:08:44 +08:00
Leah Rowe 47eb049cb4 Merge pull request 'deps/arch: genisoimage belongs to cdrtools' (#267) from runxiyu/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/267
2025-01-31 08:45:01 +00:00
Runxi Yu fa9a0df245 deps/arch: genisoimage belongs to cdrtools
genisoimage is not a an AUR package as suggested by aur_notice. It is
available in the "cdrtools" package in the repositories.

References: https://archlinux.org/packages/extra/x86_64/cdrtools/
Signed-off-by: Runxi Yu <me@runxiyu.org>
2025-01-31 16:38:20 +08:00
Leah Rowe a98490573b util/nvmutil: only set mac_updated at the end
after setting the checksum too

this is functionally no different, but setting it
at the start didn't sit right with me.

it's more logically correct to set it at the end,
in case any error did not result in an exit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:45:57 +00:00
Leah Rowe 6b9cf09ca2 restore old x230 gbe file
i accidentally committed one where i'd changed
the mac address, on a previous revision to nvmutil

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:17:07 +00:00
Leah Rowe 8a43535513 util/nvmutil: Fix bad comparison
We're checking if errno is ENOTDIR, not setting it;
the previous code would always return true, and then
set errno 0, which in the context of this code was
actually OK, so this patch makes no functional difference
in practise.

However, I'm a stickler for technical correctness. I caught
this when trying to compile with clang, because clang is
quite pedantic about checking for exactly this type of bug.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:10:52 +00:00
Leah Rowe a65a0c2f96 util/nvmutil: allow ./nvm gbe MAC
previously, if the user ran:

./nvm GBE [MAC address]

it would error, treating the MAC as a command

now if only 3 arguments are provided, and the
3rd argument ins't a valid command, it's treated
as a MAC address and validated accordingly.

this should make nvmutil easier to use, because
I imagine a lot of users forget to use setmac

there's no reason we should be so pedantic. we
should allow it to be used flexibly like this

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:07:54 +00:00
Leah Rowe 96356ce94f util/nvmutil: move "e" to swap()
we only use it there, so we should only define it
there. it's used to detect host CPU endianness.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 03:47:20 +00:00
Leah Rowe b1d8975959 util/nvmutil: Only read up to 4KB on larger gbe
On the 16KB and 128KB files, we still only need to
operate on 4KB at the start of each block, where the
block size is larger than 4KB.

The reason we deal with the entire 4KB block is because
the nvm words (in the 128 byte section) can define an
extended nvm area anywhere after 128 bytes, within the
128 byte block.

We could systematically read where that is being handled,
and handle it; we could then allocate less memory, and
read/write fewer bytes, but many block devices like SSDs
and flash drives have at least a 4KB erase block anyway,
so it's kinda pointless. saving memory would be nice, but
I don't really want to bloat the code.

This is a nice easy optimisation, to avoid wasting an
additional 8KB of memory when handling 16KB files, and
additional 120KB if handling 128KB files, since nf is
what determines how much memory will be allocated.

the alternative would be to use an mmap, and then we
could reasonably handle the idea above for only writing,
surgically, what we need: nvm words and extended nvm
words.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 03:41:55 +00:00
Leah Rowe 6821659bcb util/nvmutil: fix minor mistake (line break)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 18:46:36 +00:00
Leah Rowe 3bb7520f6d util/nvmutil: do setmac if only filename given
./nvm gbe.bin

with this patch, the above example does the same as:

./nvm gbe.bin setmac

now you can simply specify the gbe file, and it will
randomise the mac address within it, and update the
nvm checksum word.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 18:40:44 +00:00
Leah Rowe d94b274fd9 vendor.sh: don't error if grep -v fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 06:57:30 +00:00
Leah Rowe 6ebdd3c72b vendor.sh: Don't show gbe filename on inject
it's a temporary file, so printing it may confuse
the user. hide it from the output.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 06:49:45 +00:00
Leah Rowe a08748a9ed util/nvmutil: don't say write not needed if errno
otherwise, the output is confusing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:54:06 +00:00
Leah Rowe 6841a351eb util/nvmutil: print dump *after* modification
this way, we still get an error exit for example
when trying to invalidate an already invalid
checksum; this error exit was disabled by the
last revisions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:50:34 +00:00
Leah Rowe da0a6c216c util/nvmutil: verbosely print the written MAC
This is for user friendliness. Otherwise, many users
might try to dump afterward if they specified a random
MAC address.

This saves the user from having to re-run with the dump
command, thus saving time for the user.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:37:02 +00:00
Leah Rowe db5879c6b5 util/nvmutil: minor cleanup in cmd_dump
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:29:14 +00:00
Leah Rowe bd7215d1eb util/nvmutil: show nvm words written on writeGbe
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:26:59 +00:00
Leah Rowe c70117c79c util/nvmutil: clean up readonly check on writeGbe
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:18:38 +00:00
Leah Rowe cf5a63e65c util/nvmutil: Remove useless gbeFileChanged var
We don't need it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:13:20 +00:00
Leah Rowe 83601aa524 util/nvmutil: reset errno if any MAC updated
instead of setting errno in the for loop, set a variable
declaring that the mac was updated, and reset errno based
on that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:08:17 +00:00
Leah Rowe 3e86bf5ce2 util/nvmutil: reset errno when writing a MAC
if checksum verification passed, then we should reset
in case we're operating on a given part and the last
one checked was bad.

a catch-all reset is already performed in writeGbe,
but it's good to do it here too.

in practise, if the 2nd part (part 1) is what failed,
errno still wouldn't be reset.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:05:59 +00:00
Leah Rowe bcf53cc2cc util/nvmutil: show total number of bytes read
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:02:54 +00:00
Leah Rowe c91cc329cf util/nvmutil: rename tbw/bw to tnw/nw
to match nr in the readGbe function

number of bytes written, and total number
of bytes written.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:59:17 +00:00
Leah Rowe 9060710833 util/nvmutil: err if bytes read lower than nf
same as the last change. just covering edge cases.

we will likely never trigger this error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:57:32 +00:00
Leah Rowe c72f699d36 util/nvmutil: err if fewer bytes written
it will probably never happen, and this is technically
not an error condition of pread/pwrite, but we need it
to read and write that exact number of bytes, as per nf

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:55:05 +00:00
Leah Rowe d666f67ebe util/nvmutil: Show bytes written in writeGbe
This will be useful for future debugging, and future
work on optimisations.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:47:49 +00:00
Leah Rowe b2d6393ed5 util/nvmutil swap(): ensure that no overflow occurs
it wouldn't occur, on the current logic, but i wasn't
comfortable having the starting point (on little endian)
being higher than the checked endpoint, in case of
possible integer overflow as a result of future
modifications.

this is therefore a pre-emptive bug fix, because it doesn't
yet fix a bug, but it prevents a bug from being introduced.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:09:48 +00:00
Leah Rowe 063fef14d3 util/nvmutil: make swap() a bit clearer
don't sizecode. show the individual steps clearly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:09:09 +00:00
Leah Rowe fd1bbdc96c util/nvmutil: make 0x3f checksum position a define
for code clarity

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:06:12 +00:00
Leah Rowe 5ddf7f251d util/nvmutil: make 128 (nvm area) a define
for code clarity

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:03:34 +00:00
Leah Rowe 8850acc7da util/nvmutil swap(): Only handle the nvm area
The 128-byte nvm area is all that we need to handle,
since that is the only thing we actually work on in
nvmutil, based on checksum verification; the latter
implies that bytes must be in the correct order.

The swap() function previously worked on the entire
block, e.g. 4KB on 8KB files, 8KB on 16KB files and
64KB on 128KB files, and it did this twice, so it would
have operated on anywhere between 8KB to 128KB of data.

It now only operates on 256 bytes at a maximum, or 128
bytes if only handling one block. This is a significant
performance optimisation, on big endian host CPUs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 03:56:13 +00:00
Leah Rowe 49506a8832 util/nvmutil: move write checks to writeGbe
doing it in main() is messy. better do it from the
actual function. now the logic in main is clearer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 08:52:26 +00:00
Leah Rowe 948377b0e7 util/nvmutil: make cmd_swap its own function again
previous audits sizecoded nvmutil.c, reducing the sloccount,
but this resulted in unreadable code.

move the swap logic (swap parts) back to its own function,
for clarity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 08:48:51 +00:00
Leah Rowe 6e134c9f4b util/nvmutil: minor cleanup
SIZE_64KB no longer needed, and the malloc error
is needlessly verbose

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 08:03:27 +00:00
Leah Rowe 98e105ac4f util/nvmutil: allocate less memory for setchecksum
also cmd_brick

where the checksum is being corrected or bricked, we
only need to handle the 128-byte nvm area on one of
the parts

similarly, we only need to allocate half the gbe file
size when doing a copy command.

256 bytes still allocated for setmac (see previous
commit), because we verify both checksums and set both
parts if possible.

with this, nvmutil is now much more memory-efficient.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 07:25:26 +00:00
Leah Rowe 52e8ea57f7 util/nvmutil: Further reduce memory usage
Allocate memory based on nf instead of partsize.

nf is the number of bytes actually read from each
part of the file.

Now if the user is running setmac for example,
256 bytes of memory will be allocated regardless
of gbe file size, whereas it would have previously
allocated 8KB, 16KB or 128KB depending on the file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 07:05:06 +00:00
Leah Rowe 7a7d356824 util/nvmutil: Remove unnecessary buf16 variable
We can just point to gbe[] directly, in the word macro.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 06:26:53 +00:00
Leah Rowe cdf23975bc util/nvmutil: Only allocate needed memory for file
We were allocating 128KB even if we only needed 8KB, for
example. It's not a lot of memory, but the principle of
the matter is that we must respect the user by not wasting
their memory.

The design of nvmutil is that it will never overflow, because
operations are mapped in memory to the exact size of the gbe
file, which can be 8KB, 16KB or 128KB, and this is enforced.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 06:09:04 +00:00
Leah Rowe ed45da9cae util/nvmutil: Remove unnecessary buffer
The buf variable is only used once, and only so
that we can get a pointer. We can point to buf16
instead, for the same result.

The gbe pointer (size_t) is later converter to
a char * when writing back to the file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-25 06:23:22 +00:00
Leah Rowe ec3148dc3b util/nvmutil: Show specific error for bad cmd argc
For example, if the brick command is used without specifying
a part number. Instead of saying "Invalid argument", show a
much more useful error message to help the user adapt.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 18:14:25 +00:00
Leah Rowe 073420d305 util/nvmutil: cleaner argument handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 18:10:17 +00:00
Leah Rowe a6c18734e7 util/nvmutil: extreme pledge/unveil hardening
call pledge *much* earlier, and and lock everything down
much sooner. the point of pledge/unveil is precisely that
your program must operate under the most restrictive set
of conditions possible, and still function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 17:58:42 +00:00
Leah Rowe deb307eaf6 util/nvmutil: more minor cleanup
just some line breaks

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 17:03:31 +00:00
Leah Rowe c14eccaf15 util/nvmutil: more granular MAC parsing errors
tell the user exactly what they got wrong, instead
of simply printing "bad mac address", which is not
very helpful to the user

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 16:58:51 +00:00
Leah Rowe 88fb9cc90e util/nvmutil: more cleanup
spread out a few lines, so that they are more
readable, and more thoroughly comment some parts.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 16:45:08 +00:00
Leah Rowe 5aaf27f80c remove errant comment in nvmutil
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 13:34:07 +00:00
Leah Rowe c829b45c17 util/nvmutil: support 16kb and 128kb gbe files
See:
https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-mobile-p/intel-600-series-chipset-family-on-package-platform-controller-hub-pch-datash/spi0-for-flash/

The rules described there are universal, and replicated elsewhere
for many other platforms. The rules are simply:

* Flash descriptor is one block size, e.g. 4KB
* GbE is two block sizes, so if IfD is 4KB, GbE is 8KB

Intel defines 16KB and 128KB GbE files in specs, pertaining to
8KB and 64KB block sizes respectively.

The minimum size is 4KB blocksize, for 8KB GbE files which
we already supported. On larger block sizes, the same 4KB
parts are observed: a single 4KB IfD area at the start of
the block, and:

4KB GbE part at the start of the GbE region, and:
4KB GbE part at the start of GbE region plus block size

The empty space inbetween is padding, and we ignore it,
except when running swap/copy commands.

The nvmutil code has been modified, to create a 128KB buffer in
memory instead of 8KB, for loading GbE files.

Partsize is set to GbE file size divided by 2, and only the
area of memory we need to use is mapped; for example, if
we're loading a 8KB GbE file into memory, we only touch
the first 8KB part of the buffer, or first 16KB for 128KB
files.

In practise, we almost never see GbE files with sizes higher
than 8KB, but *we have seen it*, *AND NOW IT'S SUPPORTED!"

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 13:13:28 +00:00
Leah Rowe a98ca5bf65 util/nvmutil: Prevent unveil allowing dir access
We were checking directories *after* calling unveil, which
means that the sandboxing was incomplete; we only want files
to be accessed, not directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 12:18:45 +00:00
Leah Rowe 68c32034a0 typo: nvme should say nvm in nvmutil.c
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 11:37:26 +00:00
Leah Rowe c944c2bbac util/nvmutil: General code cleanup
A lot of size-coding was performed in prior audits, to
make the sloccount lower on nvmutil, but this resulted in
code that wasn't very human readable.

I've reversed some of it and added comments, for clarity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 11:33:30 +00:00
Leah Rowe 8c65e64e39 snip
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-18 05:06:34 +00:00
Leah Rowe f666652fe1 snip
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-18 01:43:02 +00:00
Leah Rowe 64d3c7b515 grub/xhci: Add xHCI non-root-hub fixes from Nitrokey
See:
https://github.com/Nitrokey/nethsm-grub/commits/nethsm-z790?since=2025-01-13&until=2025-01-13

And more generally, see branch:
https://github.com/Nitrokey/nethsm-grub/commits/nethsm-z790

This brings in a few minor fixes, and also a not-so-minor fix:
Add TT (transaction translation) handling for non-SuperSpeed
devices in xhci.c

More generally, this patchset will improve non-root hub support
in the xHCI code. There is also a patch to work around a quirk
on the MSI Z790-P mainboard, which I'm planning to add to Libreboot
at a later date.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-14 20:34:16 +00:00
Leah Rowe 7bf0d4c2ed add gnults-devel to fedora 41 dependencies
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-12 23:59:44 +00:00
Leah Rowe 66d084e7f7 grub.cfg: scan luks *inside lvm*
the user might have boot their kernel inside luks
inside lvm for some dumb reason

it's theoretically possible that the user would be
so silly indeed

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-12 13:45:00 +00:00
Leah Rowe 5a3b0dab96 grub.cfg: Scan *every* LVM device
We were scanning a hardcoded set up LVM volumes, so in practise,
LVM boot didn't really work. We did this because scanning for
asterisk is slow on some machines. However, since LVM is the last
one, and since most users don't boot directly from LVM, it wasn't
that much of an issue in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-12 13:19:48 +00:00
Leah Rowe 3c9f4be76f Libreboot 20241206, 8th revision
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 22:47:14 +00:00
Leah Rowe d4cc94d6b4 rom.sh: don't run mkpicotool on dry builds
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 18:15:22 +00:00
Leah Rowe de6d2f556f pico-sdk: Import picotool as a dependency
We were previously not handling picotool at all, and
pico-sdk would download picotool itself, at build time.

This means that the source archive, if created, would
not contain picotool. While not strictly required, for
complete corresponding source, since it's a toolchain
and not the actual pico-serprog firmware, it is my policy
that releases must include full corresponding source code,
when it is feasible to do so.

I must say, I intensely dislike cmake, with such burning
passion; I am thoroughly displeased by how hacky this is,
but it works and now nothing is in my way for a Libreboot
20241206 rev8 release!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 17:26:51 +00:00
Leah Rowe 4210ee68ea lib.sh: Much safer python version check
See:
https://docs.python.org/3/library/sys.html#sys.version_info

The sys.version_info tuple is a more reliable way to
get the version. Our previous logic assumed that Python
would always output "Python versionnumber", but this may
not always be how it works. We've seen this for example
where Debian modifies some GNU toolchains to include Debian
something in the output.

Python has a standard method built in for outputting exact
the information we need. In my system, what I got was this:

(3, 11, 2, 'final', 0)

That output was from running this command:

python -c 'import sys; print(sys.version_info[:])'

This is much more robust, so use this instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 03:54:38 +00:00
Leah Rowe 8c7ba6131c coreboot/next uprev: Fix T480 backlight keys
Backlight controls already worked on the T480/T480s, if you
used software-based controls e.g. set a hotkey for
xbacklight, but the actual Fn buttons on the keyboard did
not function at all; this patch fixes that issue

This also fixes LEDs on T480, on warm reboot, which are
otherwise off. It sets them back to the state they were
at on cold boot.

Both fixes are from Mate Kukri in the new T480 patchset.
In addition to these fixes, Mate made several code quality
improvements as part of efforts to upstream this code into
coreboot's main branch.

Updated coreboot T480 patchset to patchset 25. This change
will be reflected next in a modification to the Libreboot
documentation.

I had to make several other fixes on top of this; see diff.
A debug option was being enabled relating to stack overflow
detection, which we ought to avoid to mitigate over-zealous
build errors and stack corruption at boot; an errant option
for an EC we don't use was also being enabled, by some code
in coreboot relating to a Dasharo board; both issues have
been mitigated in this lbmk patch, by patching the upstream
coreboot build system in this patch.

As part of this change, the coreboot/next tree within lbmk
has been updated. Existing patches have been rebased.

This brings in the following changes from upstream, relative
to the previous revision used on coreboot/next:

* 2f1e4e5e85 mb/hp/snb_ivb_desktops/z220*: Remove leftover old usb configurations
* 9e859154ea mb/hp/snb_ivb_desktops: Remove unused includes
* 70b33cb38d ec/google/chromeec/acpi: Add support for generic LPC memory range
* f2ad73b5d1 mb/google/rauru: Raise little core CPU frequency from 700MHz to 2.4GHz
* 044017b4cd mb/google/rauru: Initialize PMICs in romstage
* 397c3e3c52 mb/google/fatcat/var/fatcat: Add touchpad wake source
* e18f0f53cb mb/google/fatcat/var/fatcat: Change touchpad interrupt to edge trigger
* a8b4ee246d mb/google/nissa/var/rull: Configure Acoustic noise mitigation
* c09fd09edf tree: Use "true", "false" for has_power_resource
* 1e64875265 mb/google/fatcat: Remove unused <stdio.h>
* f316ab6796 mb/google/fatcat/var/francka: Fix early pad configuration for TPM
* 6ca2c3c415 soc/mediatek/mt8196: Fix indentation in Makefile.mk
* 94c1307fdb soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks
* 67b140a949 tree: Use "true", "false" for fine_grained_control
* 97923aebe1 mb/prodrive/atlas: Add initial support for options
* 1a16146795 Fix up CFR's open issues
* 7e8d8cdea2 mb/google/rauru: Initialize SPM
* 3153432b83 soc/intel/alderlake: Add function to force disable memory channels
* 8ea2b0ab46 mb/google/fatcat/var/francka: Use RAM ID 2 for MT62F2G32D4DS-020 WT:F
* 5f600a8ee9 mb/google/fatcat: Limit Power Limit when battery is missing
* 5213646241 ec/google/chromeec: Add function to detect barrel charger
* 5ef70e5f22 ec/google/chromeec: Add API to check if battery is critically low
* 42fd35b486 ec/google/chromeec: Add API to check if charger is present
* 56370d0283 ec/google/chromeec: Add API to check if a USB PD charger is attached
* 001e7a0b45 soc/mediatek/mt8196: Add MT6685 Clock IC driver
* 5852841ca7 soc/intel/meteorlake: Use ASPM helpers from Alder Lake
* b04f057efd mb/google/rex/var/kanix: Add Synaptics touchpad
* af0c2e7a2e mb/prodrive/atlas: Remove the workaround for CLKREQ pins
* 13316c644b mb/google/fatcat/var/fatcat: Modify interrupt GPIO for LPSS I2C touchpad
* 825e9173b4 soc/mediatek: Distinguish pmic_init_setting function name
* d65ff8492c soc/intel/xeon_sp/spr/acpi: Fix regression
* 291778a1bd mb/google/corsola: Add new board variant Wyrdeer
* 745dcc861d mb/google/corsola: Refactor mipi_panel_power_on function
* 79f60c6b22 mb/google/nissa/var/telith: Disable stylus function
* d7934bdd53 Doc/soc/amd/family15h: Fix URLs to AMD documents
* 3cb7db4075 soc/mediatek/mt8196: Add PMIC MT6316 driver
* 60bce10750 drivers/mipi: Add support for KD_KD110N11_51IE panel
* d4c80054a4 soc/mediatek/mt8189: Enable timer compensation v2.5
* 403846f177 soc/mediatek/mt8196: Define MFGPLL_*_BASE using MFGSYS_BASE
* b3edaa7b10 mb/google/rauru: Implement SKU ID
* b470b48718 mb/google/rauru: Add support for getting storage id
* 24a5048948 mb/google/nissa/var/pujjo: Add new supported memory part
* c6e27c5fbf mb/google/nissa/var/rull: Add G2 touchscreen to devicetree
* 639def1d84 mb/google/fatcat/var/fatcat: Enable FPS
* acb8c870b2 mb/google/fatcat: Suppress unnecessary extra space in device trees
* d79ba5565d mb/google/nissa/var/telith: Modify PLD for typeC and typeA
* 620d2fab06 soc/mediatek/mt8189: Replace SPDX identifiers to GPL-2.0-only OR MIT
* d90b1322ab commonlib: Refactor CSE sync eventLog
* 4ef6c13b38 mb/google/brya: Adjust EC memory map range to support indexed IO
* 1e90bbadfa ec/google/chromeec: Add indexed IO support
* a8ab708584 mb/google/nissa/var/quandiso2: Create a quandiso2 variant
* 78f610a0ae util/docker/doc.coreboot.org: Allow git to work in envs owned by root
* 38ee22f6da util/docker/doc.coreboot.org: Use Alpine minor instead of point releases
* 0196c3b6a4 util/docker/doc.coreboot.org: Get rid of bash workarounds
* 897b46693b util/docker/doc.coreboot.org: Don't create volumes
* a0c45cbf1f 3rdparty/fsp: Update submodule to upstream master
* aa562d2881 soc/mediatek/mt8189: Add GPIO driver
* 40a863cd60 soc/mediatek/mt8189: Initialize watchdog
* 1380ed0cd2 soc/mediatek: Add support for MediaTek firmware support package
* 4f92943c89 soc/mediatek/common: Rename GPT_MHZ to TIMER_MHZ for readability
* 5a73692e0c soc/mediatek/mt8196: Add SPM loader
* 306660c2de util/crossgcc: Update CMake from 3.30.2 to 3.31.3
* f3adc74e44 mb/google/fatcat: Keep GSPIx interface default PCI
* 809e704101 soc/intel/pantherlake: Rename GSPI2 to GSPI0A
* 222ef676f9 soc/intel/pantherlake: Add ACPI name for GSPI2
* 1fda7027c0 util/crossgcc: Update ACPICA from 20230628 to 20241212
* e35175bb38 Update vboot submodule to upstream main
* 9eb4c5aff8 util/ifdtool: Fix memory leaks
* 87ae3573b5 mb/starlabs/starlite_adl: Configure GPIO interrupt for Virtual Button
* eaf87422b1 ec/starlabs/merlin: Add Intel Virtual Button Driver for Tablet Mode
* a1532790b9 docs: Add 24.12 release notes
* 8c0df740c7 mb/google/nissa/var/gothrax: Add probe and GPIO config for HDMI and  touchpanel
* f6fcff5511 docs/security/vboot: Update supported boards
* 0dba17da0c mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
* 2c4af7cd29 mb/topton/adl: Enable TPM2 (Intel fTPM/PTT)
* c11558d4c7 mb/asus/p8z77-m: Drop GPIO by I/O
* 4f1a1adef6 mb/topton/adl: Disable mapped SATA port
* 81cbe11361 mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM
* 9578c67c77 mb/google/brox: Include CSE reset in mainboard reset expectation
* 5af5e66686 util/cbfstool: eliminate late sign of life event
* 0797c40d52 src/soc/intel/cmn/blk/cse: Log cse sync information
* 9a15a1ed21 soc/intel: Log CSE Sync Early Sign of Life event from a better place
* c812c78618 mb/trulo/var/uldrenite: Support USB_OC on the A0 port
* ee1a766f05 mb/trulo/var/uldrenite: Set GPP_B5 and B6 to ISH function
* 87c9d93a62 mb/google/skywalker: Add MediaTek MT8189 reference board
* 6bd51ce42a soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC
* ea646c0514 mb/google/rauru: Add pwrsel init in romstage
* c3265da005 soc/mediatek/mt8196: Add pwrsel driver
* 30d8e1880a ec/google/chromeec: Publish LPC GMR address range via CREC _CRS
* bb85775d92 soc/intel/cmn/acpi: Add ACPI method to get LGMR address
* 84347d0b45 payloads/Linuxboot: Fix u-root build
* 7bcec7a2ef payloads/LinuxBoot: Build x86_64 with host toolchain
* e3150e819d util/crossgcc: Add libstdcxx target
* 61385c4976 soc/mediatek/common: Move SPM_SYSTEM_BASE_OFFSET to soc folders
* 6625dee027 soc/mediatek/common: Use array to represent spm_sw_rsv registers
* cd8d6861f6 soc/mediatek/common: Move some functions to spm_v1.c
* 91fe658714 drivers/option: Add forms in cbtables
* 4d4776f320 mb/emulation/qemu-sbsa: Configure flash region for MMU
* dfef1895f2 mainboard: Add MiTAC Computing Whitestone-2 (LGA-4677)
* caf8f9f60f mb/google/brya/var/uldrenite: Enable PMC, HECI and SRAM devices
* b668c756bf mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682)
* 941f994809 mb/trulo/var/uldrenite: Configure Network
* 600e7810fb mb/trulo/var/uldrenite: Configure USB ports and mapping
* 0261cbe8e9 mb/trulo/var/uldrenite: Configure serial_io and I2C
* 113205bcd1 mb/trulo/var/uldrenite: Enable eMMC and DLL tuning parameters
* 0dd227f9c1 mb/trulo/var/uldrenite: Enable DPTF, S0ix and configure FIVR setting
* 0ce153c8df mb/google/nissa/var/rull: For probe, change unprovisioned to unknown
* b57308f437 mb/google/rauru: Add SD card configurations
* e969a3df87 soc/mediatek/mt8196: Add SD card configurations
* 8be835ce3c soc/mediatek/mt8196: Add tracker driver
* 78560f9958 soc/mediatek/mt8196: Add MMinfra driver support
* 0b252ef8b4 util/mtkheader: Add GFH header for mt8189 bootblock code
* 540eb5ba73 cpu/qemu: Enable IDT_IN_EVERY_STAGE
* f9d6fd4e0f soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE
* c3dee9eaba cpu/intel/car/romstage: Fix false-positive stack corruption
* b659fb5cea mb/ocp/tiogapass: Wait for BMC
* 7c0556244d drivers/wifi: Update Drive Strength BRI Rsp Table revision
* 70bdd2e1fa cpu/x86/topology: Simplify CPU topology initialization
* 3a2ffba231 soc/intel/xeon_sp: Introduce early_pch_init
* 48ed4b0f85 soc/intel/xeon_sp/lbg: Add support to hide HDA
* a857c81122 arch/x86: Disable DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
* 45dabe846d mb/google/brox: Apply ISH_FW_VERSION in Kconfig
* e0b1a0dbec vc/intel/fsp/mtl: Update MTL fsp header files from 3471_91 to 4122_21
* c20fd2fc3f 3rdparty/fsp: Update submodule to upstream master
* e5b5fc345a soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
* 673075f102 util/cbfstool: Add eventLog support for ELOG_TYPE_FW_CSE_SYNC
* 3235b7c6d5 commonlib: Add ELOG_TYPE_FW_CSE_SYNC eventLog type
* 4a0c49e671 soc/intel/pantherlake: Keep image clock configuration enable
* 51cc2bacb6 soc/intel/pantherlake: Disable stack overflow debug options
* eeb6f67eec Docs: Convert bare URLs into hyperlinks
* 2609519704 mb/google/rauru: Implement regulator interface
* 8c6426c1b4 soc/mediatek/mt8196: Add PMIC MT6373 driver
* bda5b83661 mb/google/brya/var/uldrenite: update gpio settings
* afb11d05b9 mb/google/trulo/var/uldrenite: Add memory config
* 46df9e1d38 mb/google/brya/var/marasov: Enable GPP_F9 GPIO for early panel power-on
* 04d33b90ec mb/google/fatcat: config GPP_F23 as ISH gpio pin
* 16ab83b34a soc/mediatek/mt8196: Initialize SSPM
* b793209b80 mb/google/brox/var/jubilant: Disable Tccold Handshake
* 2f1e67bbc7 mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
* a1c50f233d soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
* 8910b6ba7d soc/mediatek/mt8196: Add PMIC MT6363 driver
* c215889442 soc/mediatek/mt8196: Add PMIF and PMIC driver support
* 27fa0595de soc/mediatek/mt8196: Add mtcmos init support
* 61a00269a2 mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1]
* 38b59164ca ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
* 50c9747d87 drivers/usb/intel_bluetooth: Add GBTR Method
* 0bb4a220a8 soc/intel/common/cnvi: Fix GBTE path in comment
* d33244c3af drivers/usb/intel_bluetooth: Relocate BTRK to \_SB.PCI0
* 04b9627e07 drivers/usb/intel_bluetooth: Fix GBTE to return Local0
* c3f9dd3af3 drivers/usb/intel_bluetooth: Change the Power Resource to S0
* 1cf8d84f3b mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
* 62a9d670bf mb/google/brya/var/uldrenite: Add HDA verb tables
* 56278eeed8 mb/google/rex/var/kanix: Enable/Disable PCIE WLAN based on fw_config
* 6d3346068b intel/common/block: Program the right power_limits_config entry
* 35bf4bc59c commonlib: Add generic word-at-a-time optimization to ipchksum()
* e987ba45d6 soc/mediatek/mt8196: Add booker driver
* aa3cfd5c69 haswell NRI: Post-process selected timings
* 4a4ad2b1e6 haswell NRI: Initialise MPLL
* 41c2e1685e soc/intel/xeon_sp: Add PCU PCI drivers
* 8721757aca soc/intel/xeon_sp/skx: Configure IOAPICs
* e9c546b153 arch/x86: Rename breakpoint removal function
* 0351872731 arch/x86: Add breakpoint to stack canary
* 572da7c524 acpi/acpigen: generate Create*Field() from name string directly
* 2e9aebf63f mb/google/fatcat: Enable Intel DPTF support and configure policies
* a8ff286185 mb/google/fatcat: Enable Bayhub Level 2 errata
* 230e646d98 mb/google/fatcat: Remove redundant GPIOs for x1 slot
* fbacae625a soc/intel/ptl: Enable UFS functionality by adding IRQ programming
* b67e001a85 soc/intel/pantherlake: Fix UFS ACPI _ADR calculation
* 2496943b5c mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
* dfdb210e26 soc/intel/common/block: Fixup itss_get_on_chip_dev_pirq
* 223dabef56 soc/intel/common/block: Add const qualifier for input of pirq ops
* afc49fa013 soc/intel/xeon_sp: Remove lpc_lockdown_config
* 1a4ab38035 soc/mediatek/mt8196: Rename SCP to SPM base variables
* 3189afbdee soc/intel/common: Drop locking function fast_spi_set_vcl
* 01bf34cb28 soc/intel/xeon_sp: Support _PRT reporting for domain
* 1399dd8086 soc/intel/xeon_sp: Skip not pre-routed devices in _PRT reporting
* a5362f6d73 soc/mediatek/mt8196: Enable ARM Trusted Firmware integration
* 42a696090f Update arm-trusted-firmware submodule to upstream master
* 861413b295 mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
* d5a11293ff soc/intel/alderlake: Add support for PCIe speed setting
* 5b447d00f5 soc/intel/pantherlake: Fix UFS ACPI inclusion in southbridge.asl
* 1c51c3e57f device/pci_ids: Add Pantherlake-H GT2 (DID2)
* 15109603c6 mainboard/ocp/tiogapass: Enable TPM
* 94d200c394 soc/intel/xeon_sp/cpx: Add missing FADT fields
* 534585d7bd soc/intel/xeon_sp/skx: Drop ACPI_FADT_8042
* 98ca450a53 soc/intel/xeon_sp: Use generate_p_state_entries
* 28c03b501e mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists
* 74ee80d207 soc/intel/xeon_sp/cpx: Fix register lock
* e1a0e6b738 soc/intel/xeon_sp/skx: Fix CPU init
* b04ecb2a5f arch/x86: Enable support for IOAPIC devices
* a7437ca340 soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU
* 0d284bfc36 soc/intel/mtl/acpi/gpio.asl: fix missing gpio.h include
* aeb5ccd129 ec/dasharo/ec: add Dasharo features
* 820c7e06d2 soc/mediatek/mt8196: Set DRAMC_PARAM_HEADER_VERSION to 4
* d8104af174 mb/google/rex/var/kanix: Disable FP_MCU based on fw_config
* 075a13b775 mb/google/fatcat: Update Soundwire codec address based on devicetree
* 2411942a05 drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs
* 534f81d165 mb/google/fatcat: Update flash layout
* 1b175a64e3 soc/intel/ptl: Populate SMBIOS Type 4 with unique serial number
* 4b574281f0 soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC
* 4ce5304879 soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well
* 5613f0e6be soc/intel/xeon_sp: Fix debug print
* 0d827a5810 soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
* d3aa108acf drivers/ipmi/ocp: Add missing include
* 37e9c22089 libpayload: configs: Add new config.featuretest to broaden CI
* bcced7caea commonlib/device_tree: Make END token part of struct_size
* 8ad1ee9b0a util/intelp2m: Print the current project version
* 1b9c312273 intelp2m/patform/sunrise: Add unit tests
* 2394795279 intelp2m/patform/lewisburg: Add unit tests
* bce3363412 intelp2m/patform/apollolake: Add unit tests
* 6abf66c8f3 util/intelp2m/parser/template: Add unit test
* 6b43e4ba33 MAINTAINERS: Add Yuchi and Vasiliy for Intel Atom Snow Ridge SoC
* 5cedebf874 soc/intel/xeon_xp: Remove 1 bytes losing in lower DRAM
* cd30d94ae5 mb/google/brya/var/uldrenite: Generate RAM ID and SPD file
* cda1e7e553 mb/google/nissa: Create pujjogatwin variant
* c0ccace4d5 .checkpatch.conf: Set max line length to 96
* 6f2a8ee8cc soc/mediatek/mt8196: Require DRAM blob to exist
* 850cf7d07a Update blobs submodule to upstream main
* 75424efdc4 soc/amd/common/psp/psp_def.h: increase P2C_BUFFER_MAXSIZE
* 179945291c soc/amd/common/psp/rpmc: fix printk format string
* 9b308f4d54 soc/amd/common/psp/psp_smi: report errors in 'handle_psp_command'
* 5613f209c7 soc/amd/common/psp_smi_flash: implement SPI flash RPMC command handling
* b1f954bc6c soc/amd/common/block/psp/psp_smi_flash.h: fix struct element types
* ce01117aa5 drivers/spi: add RPMC support
* 78270ef3f1 Documentation/tutorial/managing_local_additions.md: Add symlink info
* 0a7c3ed514 soc/mediatek/mt8195: Fix SCP register address
* 4c8547704f mb/google/rauru: Add 2nd source TAS2563 amps to support beep
* ac83b48cba soc/mediatek/mt8196: Add audio base address definition
* c661933a24 soc/mediatek/common: Add read16/write16 support for PMIF
* c107755701 vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00
* a417acdfbc mb/google/fatcat: Remove unnecessary prototype
* d095f1ea45 soc/amd/glinda: Update MCA banks
* 8df4eefd44 soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING
* 5c766bc150 mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
* 2007792b08 mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro
* 7f54139a81 Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax

Signed-off-by: Leah Rowe <leah@libreboot.org>

wip2

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 03:11:05 +00:00
Leah Rowe 411fb697df set up python in PATH, ensuring that it is python3
we already check the python version, and set a variable
for it, so that we can reliably use python3, even if
python in PATH doesn't correspond to python3. for
example if a system has python as python2 and python3
as python3

well, we use that when running deguard for example, but
various upstream projects that we use may need python,
and all of them use python3, not 2

so, re-use the python variable set up by lbmk, and
set it up in PATH accordingly. this now makes the note
about python3 obsolete, on docs/build.md in lbwww.git

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 21:48:45 +00:00
Leah Rowe e8336bcc3c vendor.sh: Proper semantics on prefix file names
They may not actually always be binary blobs, at least not
software. I started referring to these as "vendor files" some
time ago, for this reason.

With this terminology, it applies properly to any sort of file
from the vendor. For example, it may be that in the future, we
start inserting the MFS section of an an Intel ME image, into
the Intel ME.

We already do that with deguard for example (set MFS config),
on MEv11 based setup. That is a vendor *file*, and though it
may still actually be a binary blob, it's not software, but
configuration.

The term "blob" normally means compiled software, in most people's
minds, but the term blob is technically accurate for any blob,
not just software; however, we have to keep people's perception
in mind.

Whereas, "vendor file" is also understood by most people to
include code supplied by the vendor.

We haven't done any releases yet with this ROM image file name
prefix, so it's perfectly OK to handle it now, without handling
the old one for backwards compatibility.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 08:56:23 +00:00
Leah Rowe 63f4578263 vendor.sh: Confirm if need_files=n
Users running setmac on an X200 tarball for example, will
now see it being modified, if they didn't specify
setmac keep, so they might think vendor files are being
inserted, which they are not.

Therefore, a confirmation is provided at the end of the output.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 08:20:53 +00:00
Leah Rowe 13b06ae130 vendor.sh: Allow restoring the default GbE file
./mk inject libreboot-YYYYMMDD_board.tar.xz setmac restore

This does the same thing as a normal setmac command, except
that it does not alter the MAC address; it is also not the
same as "keep", which skips *writing* the GbE region in-ROM.

The *restore* argument writes the default, unmodified GbE file
kept by lbmk, unmodified because nvmutil is skipped when the
user specifies this argument.

This option is useful for debugging purposes, because it can
be used to verify whether anything else is being wrongly
modified by the script; the "nuke" command can be executed
afterward, and the hash file inspected versus release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 08:13:28 +00:00
Leah Rowe ab8feff92e vendor.sh: set random MAC address *by default*
MAC addresses are generic, inside Libreboot images where
an Intel GbE region is specified.

We commonly get users flashing multiple systems for their
own use, and sometimes they complain that they networking
broke, because they don't know that the MAC address is
identical on each machine.

This still doesn't work around the case where the same machine
is used, e.g. multiple T440p thinkpads, but if they have one
of each model, it can work nicely, because we do in fact
change it for various platforms.

This change will also reduce the number of people at conferences
in the future, where there are multiple Libreboot users, having
MAC address conflicts.

Changing the MAC address is a good practise, so we enforce good
practise. The user can still retain the old behaviour by
using this command:

./mk inject libreboot-YYYYMMDD_boardname.tar.xz setmac keep

The "keep" argument clears new_mac, which will then skip
changing the MAC address. They can also still set an arbitrary
MAC address as an argument for setmac, e.g.:

./mk inject libreboot-YYYYMMDD_boardname.tar.xz setmac 00:de:ad:c0:ff:ee

This change will be covered in the documentation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 07:48:50 +00:00
Leah Rowe 0ceaa01d45 vendor.sh: add clarification to nogbe warning
if the user ran this on an x60 tarball, the no-gbe
warning seems confusing since that one has intel gbe,
but pre-ifd, so no gbe region in the flash; on pre-ifd
systems e.g. ich7 southbridge, the mac address was baked
into a separate gbe nvm on mask rom, inaccessible to users

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 07:31:14 +00:00
Leah Rowe 4d5caf1dcf vendor.sh: check that the vcfg file exists
setcfg already checks it, but it's good to check anyway

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 19:32:39 +00:00
Leah Rowe fc4ee88e16 vendor.sh: error out if nuking failed
We already have code to handle this, but it's possible
that I might break it in the future, due to the complex
logic of this script.

So, I've implemented this catch-all check at the end of
the process. It still relies on the actual setting of
the variables, upon which this check is based, to be set
correctly.

This condition will most certainly never be met, unless
I break some other part of the code in the future. That
is precisely what this overly pedantic check is for.

Example scenarios:

I forget to set xchanged=y, on a new modification.

I set has_hashes erroneously.

The variables are re-used between runs, and not properly
reset; at present, a given run of ./mk inject only
operates on a single target, but this latter fact could
change in the future.

need_files is set erroneously; vendorfiles detected as
being required, when they aren't.

These are just a few examples. As such, this is a preventative
bug fix, because it's preventing a bug.

The main reason I want this i n here is because I need to ensure
that vendor files are properly deleted, for a given release.
If I accidentally includes ones that I'm not supposed to,
inside ROM images, that could be a big problem.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 19:24:53 +00:00
Leah Rowe 8819a93d89 add line break, part 3
forgot a line break, three times in a rowe

you got a problem with that?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:33:18 +00:00
Leah Rowe 8ce1a00f51 add line break, part 2
because printf

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:32:13 +00:00
Leah Rowe bc2c14e76a add line break
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:30:23 +00:00
Leah Rowe c762850311 vendor.sh: prevent double-nuke
where the nuke command is used, we need the files to be
there; if they're not, it will try to nuke them, which will result
in an error in most cases, but there may be some cases where that
isn't true, for instance if only the Intel ME is needed; it'll be
writing zeroes over zeroes.

we want to only allow technically correct behaviour, because
technically correct is the best kind of correct.

it is theoretically possible that a double-nuke might affect
certain behaviours unpredictably. for example, if vendor.sh
later integrates another tool that works whereby the same command
inserts or nukes depending on a certain condition, but with the
same command, and where that command would return zero in both
cases.

this is a preventative bug fix, because it fixes an issue that
does not yet actually occur in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:26:22 +00:00
Leah Rowe 68299ad05c vendor.sh: much more verbose errors/confirmation
the user must be well-informed as to the next step, which
this script directly influences

guide the user accordingly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:15:43 +00:00
Leah Rowe b8e6d12f3d add libx86 to arch dependencies
needed to compile the "int" tool defined
under config/git/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 14:21:24 +00:00
Leah Rowe cf8ad497b4 vendor.sh: Remove unnecessary return
The message at the end that states a file was
not modified, is not currently printed when vendor
files are not needed, and setmac is not used.

This patch fixes that, so the user now sees a
confirmation of such change, or lack thereof.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 02:36:50 +00:00
Leah Rowe c858099b35 vendor.sh: Download utils even if vcfg unset
This is because the user may have specified setmac.

I tried without this change, on a fresh lbmk, setting
the MAC address on an X200 tarball, and it produced an
error that ifdtool was unavailable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 02:33:32 +00:00
Leah Rowe ce16856a24 vendor.sh: Allow setmac if vendorfiles not needed
Observe the following prior patch:

commit 818f3d630c
Author: Leah Rowe <leah@libreboot.org>
Date:   Fri Jan 3 17:06:14 2025 +0000

    vendor.sh: Don't error if vcfg is unset

Now:

This patch made vendor inject more robust, and speeds
up the processing of images where no vendor files are
needed, but it broke setmac on such tar archives.

This new patch works around it. For example, I was
able to run ./mk inject on an X200 tarball to change
the MAC address; no vendorfiles are inserted, because
it's not needed.

The further check for whether a board uses Intel GbE
still protects against accidental modification.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 02:23:07 +00:00
Leah Rowe 4b51787d07 add less to arch dependencies
probably not actually needed, but it annoys me that it doesn't
come installed by default, and it's needed for certain git
operations

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 00:59:33 +00:00
Leah Rowe 8bd028ec15 lib.sh: Set python after dependencies
otherwise, the user can't install python, which is
in the dependencies. an irony!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 20:53:05 +00:00
Leah Rowe 44b6df7c24 update my copyright years on modified scripts
there are some lbmk scripts that i modified, starting
this year. update the headers.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 18:09:03 +00:00
Leah Rowe 818f3d630c vendor.sh: Don't error if vcfg is unset
It should return 1 instead, in readcfg(), because this
is not an error condition; vcfg not being set means
that the board doesn't use vendor files, which is
perfectly normal and should not yield an error.

This fixes a build error under certain conditions,
found during release-build testing.

This bug was exposed when I fixed double quoting issues
as per shellcheck tests.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 17:08:05 +00:00
Leah Rowe 432a1a5bca lib.sh: Fix unescaped quotes in chkvars()
This should be the proper fix now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 16:00:11 +00:00
Leah Rowe a73b0fd910 Revert "fix more unescaped quotes in eval"
This reverts commit ec6bcc1fba.
2025-01-03 15:56:41 +00:00
Leah Rowe ec6bcc1fba fix more unescaped quotes in eval
it should fix more build errors that might have appeared
in the aforementioned revision, mentioned in the previous
commit message

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 15:43:27 +00:00
Leah Rowe 5284f20b98 fix ./mk dependencies build issue
the bug was actually caused by chkvars

add an escape for the quotes and bam. fixed.

without this, i got the following e.g.

For command: ./mk dependencies debian

Output:

./mk: 1: [: apt-get: unexpected operator
ERROR ./mk: pkg_add unset

Someone reported a similar issue with the Arch one,
which is also now fixed. This regression was caused
by the previous commit:

commit 0cf58c2273
Author: Leah Rowe <leah@libreboot.org>
Date:   Thu Jan 2 23:52:45 2025 +0000

    fix lbmk shellcheck errors

I forgot to escape the double quotes in an eval.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 14:35:31 +00:00
Leah Rowe d825f9a968 rom.sh: Remove errant GRUB modules check
This check is a good idea, but not viable here,
because the modules naturally aren't set in all
circumstances, so it just causes a build error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 09:34:42 +00:00
Leah Rowe 4149f3dc81 submodule/grub: use codeberg for 1st gnulib mirror
the gnu.org mirror is always slow for some reason, but only
for gnulib. it may only be for me, because routing in other
countries/networks may differ.

when i'm freshly cloning lbmk modules, gnulib is always really
slow, like 300KB/s (bytes, not bits)

i have 1gbps internet and wish to not have 2005-era speeds,
thank you kindly!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 09:19:59 +00:00
Leah Rowe 0305975e70 util/nvmutil: Update AUTHORS and COPYING files
Mention Riku's copyright in the COPYING file, and update
my years in that file. Add Riku to the AUTHORS file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:24:09 +00:00
Leah Rowe 20b192e13b util/nvmutil: Describe nvmutil in help output
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:15:18 +00:00
Leah Rowe d1ca21628c util/nvmutil: Remove the correct binary on uninstall
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:13:01 +00:00
Leah Rowe e63fe256df util/spkmodem-recv: More correct Makefile
Set up the DESTDIR variable properly. Otherwise,
this is just style changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:09:55 +00:00
Leah Rowe efd50ee548 util/nvmutil: Honour the INSTALL variable
Don't assume "install" is the correct command.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:08:38 +00:00
Leah Rowe 8008838abb util/nvmutil: Don't clean when doing uninstall
The user might wish to uninstall, but not remove the
build that they just did.

The user can still do make clean if they wish.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:06:12 +00:00
Leah Rowe 982f257f58 util/nvmutil: Proper DESTDIR/PREFIX handling
DESTDIR is the root directory where it goes, which
is normally an empty string; PREFIX is where the
bin directory is located, relative to DESTDIR

Default to /usr/local for PREFIX, not /usr, because
/usr/bin is for system utilities.

nvmutil is a local utility.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:03:44 +00:00
Leah Rowe 3f85ae5f85 util/nvmutil: Set CC and CFLAGS only if unset
We don't want to clobber anything that the user set themselves.

Instead, we should respect the user's choice.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:48:52 +00:00
Leah Rowe 2c7b9fb941 util/nvmutil: Capitalise BABA
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:45:55 +00:00
Leah Rowe 57f9906f6d util/nvmutil: Add uninstall to Makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:41:46 +00:00
Leah Rowe 4defe2c608 util/nvmutil: Add distclean to Makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:39:46 +00:00
Leah Rowe 033e4cd9d5 util/nvmutil: Make the GbE checksum a define
This makes the code easier to understand.

All 2-byte words, stored in little endian order within
the 128-byte GbE NVM area, must add up to 0xBABA.

If it doesn't, then software is supposed to reject that
GbE config. The nvmutil software works on that basis.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:36:44 +00:00
Leah Rowe 874317c4e5 util/nvmutil: nicer hexdump display
make it look like hexdump -C, where individual bytes are
spaced, and there is an additional space after 8 bytes,
per row.

i won't bother with a character display, since that is
meaningless on gbe nvm words.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 00:36:17 +00:00
Leah Rowe a338e585ee util/nvmutil: show the correct hexdump order
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 00:26:32 +00:00
Leah Rowe b032e483ef lib.sh mktarball: cleaner if statement
i also removed that printf, because the path it prints is
actually wrong sometimes; in the recent re-write of vendor.sh,
it prints the correct path instead

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 23:58:37 +00:00
Leah Rowe 0cf58c2273 fix lbmk shellcheck errors
There was also a condition in run_make_command that is now
an OR, where it was an AND, on script/trees, to fix the use
of mixed (and erroneous) OR/AND operators.

I'm planning a much more invasive audit than this. These are
light fixes, intended for Libreboot 20241206 rev8.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 23:52:45 +00:00
Leah Rowe 8276560cc9 lib.sh and rom.sh: update my header
i made modifications to them in 2025, so
update them to 2025

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 18:33:55 +00:00
Leah Rowe 08e86d2218 vendor.sh inject: reset err upon return
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 10:17:39 +00:00
Leah Rowe 41275d699c vendor.sh: MUCH, MUCH, MUCH safer ./mk inject
Don't extract to bin/release/

Modify the tarball instead. Previously, the tarball would
not be modified, but a lot of users thought the tarball was
being modified and ignored bin/release/, where the injected
images were actually being saved to.

Don't copy the tarball either. Just modify it in-place.

Don't allow single-rom injection either; only allow the
tarball-based method.

The command syntax has changed, but:
./mk inject tarball.tar.xz

This is the same. What has changed is nuke, and MAC address
modification. Observe:

./mk inject tarball.tar.xz nuke
./mk inject tarball.tar.xz setmac
./mk inject tarball.tar.xz setmac ??:??:??:??:??:??
./mk inject tarball.tar.xz setmac 00:1f:16:??:22:aa

These are just a few examples. The MAC address syntax is
the same as used for nvmutil, which means you can set it
randomly. Also:

./mk inject tarball.tar.xz setmac

You can use the *setmac* command *repeatedly*, even if
you've already injected a given archive. It'll just
update the archive, but skip injecting other files
that were already injected.

If you use setmac without a MAC address, it will randomise
the MAC address. This is therefore very similar to the
command structure used in nvmutil.

The code for injection is generally more robust, with
stronger error checks. This design change was done, so
that the user doesn't accidentally brick their machine.

The non-injected images have a prefix in the file name
saying "DO_NOT_FLASH", and those non-injected images are
padded by 1 byte. That way, the user knows not to flash it
and if they try, flashprog will throw an error.

The prefix and padding is removed on injection. Old images
without the padding/prefix can still be injected, via
tarballs; this new code is backwards-compatible with tarballs
from older Libreboot releases.

A common thing I see sometimes is a user will say they have
a black screen or something, and I say: did you insert vendor
files? And they say yes. And they did. But they extracted and
flashed from the tarball, which wasn't injected, because
they didn't release about bin/release/

No amount of RTFM is justified. The previous design flaw
is a bug. We must always observe user safety first, no matter
what, so that has now been done.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 08:46:36 +00:00
Leah Rowe ed7293494e util/nvmutil: Obey the 79-character per line limit
Must not exceed 79 lines. Some variables and functions have
been renamed, and there has been some minor re-factoring.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 21:10:56 +00:00
Leah Rowe 637b5e36fd util/nvmutil: Tidy up copyright header
I don't like using SPDX for actual copyright declarations.

I only want it to be used for the license identifier.

Also:

I made a *single* change to nvmutil.c in 2024, which means
that I have copyright in all years since and including 2022;
the file said 2022, 2023, 2025, but it's actually 2022-2025.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 20:56:54 +00:00
Leah Rowe cd28db883e vendor.sh: fix comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 18:30:57 +00:00
Leah Rowe 57971ceb22 util/nvmutil: Fix another straggler
I don't like using strings this way, it looks unclean.

Once again, use good old fashioned if/else.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 14:49:24 +00:00
Leah Rowe 15b37b2a1a util/nvmutil: Tidy up pledge calls
I wasn't too happy using shorthand for strings like that.

Tidy it up and use good old fashioned if/else.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 21:14:24 +00:00
Leah Rowe e8799310db hp820g2: fix vendorfile inject and set release=y
I believed that the compressed nature of refcode was the only
non-reproducible thing, but turns out you also need to run
rmodtool on the refcode to make the binary relocatable in
cbfs. This is based on my reading of the coreboot Makefile.

With this change, I can now provide release binaries for
the HP EliteBook 820 G2.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 14:46:13 +00:00
Leah Rowe f9ab082ec1 fedora41/dependencies: add libuuid-devel
it seems to be required for uuid/uuid.h

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:57:00 +00:00
Leah Rowe 661591f9f0 add uuid-devel to fedora41 dependencies
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:27:11 +00:00
Leah Rowe 1a46c04738 support ./mk dependencies fedora reinstall
dnf reinstall package

or

dnf install package

for reinstall, do this:

./mk dependencies fedora41 re

this is an example command

the 4th argument prefixes "install" in dnf install

a bit hacky but it should work

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:25:27 +00:00
Leah Rowe d58d63569f fix missing semicolon in grub nvme patch
i  forgot this when rebasing on the recent uprev

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:22:11 +00:00
Leah Rowe 95ea3293df bump seabios to rev 1602647f1 (7 November 2024)
This brings in a *single* change from SeaBIOS, because there
has only been one change in the main branch, and it's a bug fix.

The change from upstream is as follows:

commit 1602647f1be24fe63d11138d802e735c8e674e63
Author: Daniel Khodabakhsh <d.khodabakhsh@gmail.com>
Date:   Thu Nov 7 18:46:16 2024 -0800

    boot: Force display of the boot menu when boot-menu-wait is a negative number

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 03:31:37 +00:00
Leah Rowe 6d7e6c361b Bump GRUB revision to 6811f6f09 (26 November 2024)
Although this is for a stable release revision, namely
Libreboot 20241206 revision 8, I've carefully audited the
upstream changes and they all seem fine.

Several important bug fixes have been imported with this change.
Most interestly, GRUB has also added support for TPM2 Key
Protectors; we don't use this feature yet, and probably won't
for the time being, since TPM is largely security threatre for
our purposes anyway. There's no harm including all upstream
revisions, up to those ones, since those modules are not yet
added in lbmk.

Most notably, there are several file system fixes, and minor fixes
to the graphics terminal of GRUB. Minor fixes only, in terms of
what Libreboot actually uses at present.

The full list of imported changes are as follows, relative to the
previous GRUB revision, which was b53ec06a1 from 17 June 2024:

* 6811f6f09 tpm2_key_protector: Enable build for powerpc_ieee1275
* ff14b89bd ieee1275/tcg2: Add TCG2 driver for ieee1275 PowerPC firmware
* 72092a864 ieee1275/tcg2: Refactor grub_ieee1275_tpm_init()
* 8c0b5f200 ieee1275/ibmvpm: Move TPM initialization functions to own file
* 7344b3c7c ieee1275: Consolidate repeated definitions of IEEE1275_IHANDLE_INVALID
* 29d1bd2a9 term/ieee1275/serial: Cast 0 to proper type
* 99ee68a01 tss2: Adjust bit fields for big endian targets
* 3770a6905 docs: Document TPM2 key protector
* f898440cc tests: Add tpm2_key_protector_test
* 76a2bcb99 tpm2_key_protector: Add grub-emu support
* 135e0bc88 diskfilter: Look up cryptodisk devices first
* b35480b48 cryptodisk: Wipe out the cached keys from protectors
* 6abf8af3c cryptodisk: Fallback to passphrase
* fba3a474e tpm2_key_protector: Implement NV index
* 550ada7d6 tpm2_key_protector: Support authorized policy
* 5f6a2fd51 util/grub-protect: Add new tool
* ad0c52784 cryptodisk: Support key protectors
* 48e230c31 key_protector: Add TPM2 Key Protector
* 35c9904df tss2: Add TPM2 Software Stack (TSS2) support
* 63a78f4b4 tss2: Add TPM2 types and Marshal/Unmarshal functions
* 2ad159d9b tss2: Add TPM2 buffer handling functions
* 5d260302d key_protector: Add key protectors framework
* 3d60732f9 libtasn1: Add the documentation
* 99cda6788 asn1_test: Test module for libtasn1
* 504058e82 libtasn1: Compile into asn1 module
* 8a0fedef2 asn1_test: Enable the testcase only when GRUB_LONG_MAX is larger than GRUB_INT_MAX
* 66cf4cb14 asn1_test: Use the grub-specific functions and types
* 0d0913fc6 asn1_test: Print the error messages with grub_printf()
* 2e93a8e4b asn1_test: Remove "verbose" and the unnecessary printf()
* b7568e335 asn1_test: Return either 0 or 1 to reflect the results
* d60a04bae asn1_test: Rename the main functions to the test names
* 54e0e19a2 asn1_test: Include asn1_test.h only
* 0ad1d4ba8 libtasn1: Fix the potential buffer overrun
* 4160ca983 libtasn1: Use grub_divmod64() for division
* 8f56e5e5c libtasn1: Adjust the header paths in libtasn1.h
* d86df91cb libtasn1: Replace strcat() with _asn1_str_cat()
* 32fdfe600 libtasn1: Replace strcat() with strcpy() in _asn1_str_cat()
* fa498af7b libtasn1: Disable code not needed in GRUB
* 9a26abbc3 libtasn1: Import libtasn1-4.19.0
* c85c2b9f5 posix_wrap: Tweaks in preparation for libtasn1
* 4f6c46091 kern/fs: Honour file->read_hook() in grub_fs_blocklist_read()
* 792132c72 docs: Fix incorrect and potentially confusing language and minor formatting
* 1763d83f5 docs: Correct GRUB config file name for network boot
* 097fd9d9a docs: Correct chainloader UEFI secure boot info
* f48e6af11 docs: Correct PXE environment variables descriptions
* dd743ba42 loader/multiboot: Do not add modules before successful download
* 9a9082b50 grub-mkimage: Add SBAT metadata into ELF note for PowerPC targets
* f97d4618a grub-mkimage: Create new ELF note for SBAT
* f26b39860 commands/legacycfg: Avoid closing file twice
* 337cb2486 nx: Rename GRUB_DL_ALIGN to DL_ALIGN
* 31de991de kern/acpi: Fix out of bounds access in grub_acpi_xsdt_find_table()
* f5bb766e6 nx: Set the NX compatible flag for the GRUB EFI images
* 94649c026 nx: Set page permissions for loaded modules
* 09ca66673 nx: Add memory attribute get/set API
* 9fb80dd57 modules: Load module sections at page-aligned addresses
* 6e2fe134e modules: Don't allocate space for non-allocable sections
* 2b79d550f modules: Strip .llvm_addrsig sections and similar
* 246c82cda modules: Make .module_license read-only
* 616adeb80 i386/memory: Rename PAGE_SIZE to GRUB_PAGE_SIZE and make it global
* 95a7bfef5 i386/memory: Rename PAGE_SHIFT to GRUB_PAGE_SHIFT
* 1b1061409 i386/msr: Extract and improve MSR support detection code
* 929fafdf5 i386/msr: Rename grub_msr_read() and grub_msr_write()
* d96cfd7bf i386/msr: Merge rdmsr.h and wrmsr.h into msr.h
* 86ec48882 commands/tpm: Skip loopback image measurement
* 3808b1a9b net/drivers/efi/efinet: Skip virtual VLAN devices during card enumeration
* e5f047be0 efi/console: Properly clear leftover artifacts from the screen
* c5ae124e1 kern/riscv/efi/init: Use time register in grub_efi_get_time_ms()
* 9c34d56c2 loader/efi/linux: Reset freed pointer
* 92bed41bf loader/efi/linux: Reuse len variable
* 33cb8aecd lib/x86_64/relocator_asm: Use .quad instead of .long
* 77cd623de lib/x86_64/relocator_asm: Fix comment in code
* 95145eea5 loader/efi/linux: Update comment
* d333e8bb3 util/grub-mkimagexx: Explicitly move modules to __bss_start for MIPS targets
* 34b7f3721 include/grub/offsets.h: Set mod_align to 4 on MIPS
* ed0651673 gentpl: Put boot/mips/startup_raw.S into beginning of the image
* 648f2d16c configure: Add -mno-gpopt option for mips and mipsel targets
* f0710d2d8 lib/xzembed/xz_dec_bcj: Silence warning when no BCJ is available
* e61157bbd fs/erofs: Replace 64-bit modulo with bitwise operations
* 5313fa839 configure: Look for .otf fonts
* 33b94f2a9 loader/efi/chainloader: Do not print device path of chainloaded file
* ab1e6fc04 docs: Document all GRUB modules
* 9537f4403 commands/bli: Fix crash in get_part_uuid()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 03:13:58 +00:00
Leah Rowe 09a01477df t480/3050micro: force power off post power failure
The T480 has no option table, because it lacks nvram, so the
default option applies, which seems to be power on after power
failure. This is undesirable on a laptop.

It's triggered simply when your laptop battery runs out, and
once triggered, it couldn't be configured at all.

Hard-code this. The documentation will be updated later on
after this patch is pushed, telling those users who want
to change this behaviour how to modify/remove the patch,
if they wish to to do so, because some people may actually
want to run a server on the OptiPlex 3050 Micro (or if they're
crazy like I am, they will host libreboot.org on a ThinkPad).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 01:54:02 +00:00
Leah Rowe d344cd95ea flashprog: Disable -Werror
We haven't seen any build errors, but it seems flashprog
sets -Werror on CFLAGS. If you provide WARNERROR=no as
a make argument, it avoids -Werror entirely.

This is a preventative fix, for over-zealous compilers.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 00:12:21 +00:00
Leah Rowe dc95e912bf bump flashprog to revision eb2c041 (14 Nov 2024)
This brings in several important bug fixes from upstream.

With this, the following upstream changes have been imported:

* eb2c041 cli_wp: Fix bail-out when multiple chips are detected
* e05e334 cli_common: Rename local `optarg' variable
* efad610 manibuilder: Include NetBSD (anita tags) in `native' target
* 09289fb manibuilder: Replace unmaintained DEFAULT_TAGS list
* 1457cc6 manibuilder: Stop build testing oldest, EOL targets
* 1faffa5 manibuilder: Fix Ubuntu Noble Numbat (24.04) for amd64
* 61dbe36 udev rules: Use `uaccess' tag instead of `plugdev' group
* 63d30a2 install: Install binary into bin/, not sbin/
* 6ce26a7 flashchips: add Winbond W25R512NW / W74M51NW
* 612519b ichspi: Add Intel Arrow Lake support
* d5a61ef ichspi: Add Intel Lunar Lake support
* 5e0d9b0 ichspi: Add Intel Meteor Lake SoC
* 0ef2eb8 ichspi: Add Intel Snow Ridge SoC
* 42daab1 ichspi: Properly add Emmitsburg PCH
* af26008 ich_descriptors_tool: Add missing options for EHL & C620
* 82fe123 ich_descriptors: Hard code number of masters for newer gens
* 157b818 ich_descriptors: Guard MCH strap handling by chipset version
* db878fb ich_descriptors: Drop chipset detection based on `freq_read`
* b3cc2c6 ich_descriptors: Unify pretty printing of PCH100+ masters
* 8e4151d chipset_enable: Remove hidden-spidev workaround for Elkhart Lake
* 6d72efa chipset_enable: Remove hidden-spidev workaround for all 14nm PCHs
* 092a699 chipset_enable: Remove hidden-spidev workaround for TGP+
* 5bbd324 chipset_enable: Add missing PCI ID for Intel PCH H410
* a088475 chipset_enable: Factor PCH100 hidden-spidev workaround out
* 5eb7a58 Drop 1s delay before automatic verification
* 7427569 libflashprog: Run programmer_shutdown() on failed setup
* 5a9d6ea chipset_enable: Fix memory leaks introduced with AMD SPI100
* e149fbe Only try to check erase opcodes for SPI25 chips
* 07ebc68 Avoid NULL deref in check_block_eraser()
* 2405310 chipset_enable: Mark Intel QM87 as DEP
* 9897063 flashchips: Allow volatile register writes for W25Q128.V
* c972aed flashchips: Configure WP for MX25L25635F/45G
* 8f7122c cli: Add new write-protect CLI
* eed122d layout: Implement flashprog_layout_get_region_range()
* 1f693db cli: Add new `config' CLI for status/config registers
* 85c2cf8 cli: Implement "command" option parser
* 24c0977 cli: Add print function for generic CLI options
* b82aadc cli: Move some declarations into `cli.h`
* a705043 cli: Add a new CLI wrapper
* d39c7d6 cli: Extract basic CLI init into cli_common
* df6ce9f cli: Extract log argument parsing into cli_common
* 0da839b cli: Extract layout argument processing
* d91822a cli: Extract layout argument parsing into cli_common
* e7899a9 cli: Move all long-option keys into cli.h
* 34e783a cli: Extract flash argument parsing into cli_common
* e68b08b cli_classic: Rewrite programmer argument parsing
* 6898f5b spi25_statusreg: Prefer volatile status register writes
* 55e7884 Introduce FLASHPROG_FLAG_NON_VOLATILE_WRSR
* fbba454 Install udev rules
* 768cfc4 flashchips: Add GigaDevice GD25LR512ME

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 00:03:12 +00:00
Leah Rowe 27c8c1c16b replace liblz4-tool with lz4 and liblz4-dev
In Debian dependencies files. These are available in
Debian Stable, but liblz4-tool is a transitional
package referring to lz4; liblz4-tool transition
package is unavailable in Debian sid, so remove it
from the dependencies files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 22:31:24 +00:00
Leah Rowe d3a732a64d lib.sh dependencies: support --reinstall argument
./mk dependencies debian --reinstall

Add --reinstall and it'll do:

apt-get install --reinstall

This can be useful when updating from a stable release
to a testing release. The variable, "reinstall" can be
configured for other distros, but it's currently only
configured for Debian-based distros.

Also, it can be anything. For example, you could add -y;
however, a 4th argument will not be accepted. For example,
you cannot do:

./mk dependencies debian --reinstall -y

If you do this, it'll only see --reinstall; similarly, if
you did this command:

./mk dependencies debian -y --reinstall

then -y would be passed, but not --reinstall. This is an
intentional design decision, in case you accidentally pasted
or subshelled something that outputted something undesirable,
to prevent possible abuse.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 21:53:55 +00:00
Leah Rowe 466ada423d move xbmkpath to XBMK_CACHE/
When doing ./mk release, the build system would create
symlinks inside xbmkpath/ relative to the current work tree,
which will differ from what's in PATH.

Since XBMK_CACHE is already set globally, from the main work
tree and the release-build work tree, that means we can know
reliably that PATH is always correct if we put xbmkpath/
inside XBMK_CACHE.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 21:25:55 +00:00
Leah Rowe b0a2384032 Revert "Remove legacy update/vendor commands"
This reverts commit 7813205146.

I'm doing changes for 20241206 rev8. It was a mistake to
remove these; they will be removed again, after rev8.

The documentation standardised on ./mk a while ago now, and
it's almost time to remove these commands. However, anyone
using the old commands ought to be able to, up to and including
any revision of the Libreboot 20241206 release.

It is my intention that these legacy commands finally be
removed for the next testing release, as part of a much wider
build system audit that I'm doing between now and then.

(Libreboot Build System Audit 7 is underway, and several of
these early audit7 changes are going on 20241206 rev8; after
that, I will create a branch named 20241206_branch off of rev8,
and anything in master from then on will contain much wilder
changes, with more conservative changes in 20241206_branch)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 21:06:05 +00:00
Leah Rowe 3d7dd4aa9f Fix U-Boot build issue with Swig 4.3.0
Tested on Debian Sid, as of 30 December 2024, which uses
Swig 4.3.0. Context here:

commit a63456b9191fae2fe49f4b121e025792022e3950
Author: Markus Volk <f_l_k@t-online.de>
Date:   Wed Oct 30 06:07:16 2024 +0100

    scripts/dtc/pylibfdt/libfdt.i_shipped: Use SWIG_AppendOutput

This patch from U-Boot upstream has been backported to the
release revision used by Libreboot. Swig has, since 4.3.0,
changed the language-specific AppendOutput functions, but
the helper macro SWIG_AppendOutput is identical; therefore,
upstream switched to this function.

The benefit of this fix is that since the newly used macro
is also the same on older Swig versions, and behaves the same,
this shouldn't fix building on older Swig versions. For reference,
the initial Libreboot 20241206 release, and revisions of it before
revision 8, was built on Debian 12 which uses Swig 4.1.0.

The rev8 release will still be compiled on Debian 12, but with
this change, it should also compile on Debian Sid, and bleeding
edge distros like Arch Linux.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 20:24:46 +00:00
Leah Rowe 0c81074746 use command -v instead of which
which is a non-standard command, whereas command is part of posix

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 19:23:27 +00:00
Leah Rowe 6c7e3ce2d6 trees: remove unnecessary subshell
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 18:38:42 +00:00
Leah Rowe ad137eae89 trees: only symlink host gcc/gnat to build xgcc
In general, we don't want to mess with the hostcc, unless
we have to. To avoid other breakage, clear what we did
after crossgcc has compiled.

This is a follow-up to the previous patches, matching gcc
to gnat versions and vice versa, when compiling crossgcc.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 18:36:46 +00:00
Leah Rowe cfb6de94c3 trees: correction on check_gnu_path
i intend for this function to work generically,
matching gnat to gcc or gcc to gnat, but there was
a hangover from the previous code where it specifically
assumed we were matching gnat

this bug manifested when i tested with gnat being v13
and gcc being v14 in path, where gcc-13 was also
available in path.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 17:59:19 +00:00
Leah Rowe ec2f071666 trees: match gcc/gnat versions both ways
on debian trixie/sid after updating from stable,
sometimes gcc 13 and gnat 13 are both available, but
gcc resolves to gcc-14 and gnat-14 isn't available.

even when gnat-14 and gcc-14 are available, gnat will
still either resolve to gnat-13, or nothing at all.

in cases where gnat-14 is unavailable, but gcc and gnat 13
are both available, we should match gcc to gnat.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 15:29:41 +00:00
Leah Rowe f64b599627 Merge path.sh into script/trees
The code is simple enough now that I'm happy for it
to just be part of the main script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 14:14:19 +00:00
Leah Rowe 295463d281 path.sh: Further cleanup
Remove all symlinks each time, to ensure that no
stragglers are left behind, since they are being
re-generated each time anyway.

The code for determining version numbers has now
been unified under gnu_setver()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 14:11:45 +00:00
Leah Rowe 5b24e0a5a9 path.sh: More thorough gcc/gnat version check
We were checking the shorthand version number, but
the precise version numbers need to match.

Also: when we searched $PATH/gnat-$gccver, we assumed
that the full version would then match, without checking
it, so now it is checked precisely.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 13:36:34 +00:00
Leah Rowe 7849a07588 path.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 13:18:57 +00:00
Leah Rowe 17168a87db path.sh: remove unnecessary shebang
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 02:24:23 +00:00
Leah Rowe e565df94fd Fix globbing issue in lbmk
When doing e.g. $@ we should use double quotes to prevent globbing.

Thanks go to XRevan86 for pointing this out.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 01:02:22 +00:00
Leah Rowe c80cc0a00b remove auto-confirm on distro dependencies
because if it says yes to everything, and the package
manager would otherwise ask whether you want to give
it your first born son, you are therefore agreeing to it.

so remove -y for safety

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 00:29:04 +00:00
Leah Rowe 01fc65a0a9 Mitigate Debian Trixie/Sid GCC/GNAT version mismatch
When I tested Debian Trixie, and Debian Sid, I saw that
GCC in PATH pointed to gcc-14, but gnat in path pointed
to GNAT-13, even if you manually install gnat-14.

GNAT 14 was marked experimental, but GCC 14 was marked
for use, in the apt repositories.

So this patch doesn't address the mismatch when doing e.g.
apt-get install gcc gnat

I will address the actual package dependency in a follow-up
patch, on the Debian dependencies config.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 00:21:02 +00:00
Leah Rowe 424b0c7103 t480/3050micro: disable hyperthreading
Hyperthreading is a risk factor for spectre/meltdown
and other attacks.

Disabling it is a best practise. Those who need it
can always turn this option back on. Otherwise, disabling
it by default is a simply courtesy to the average user,
in the interest of security.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-29 02:10:03 +00:00
Leah Rowe 603105f3b4 t480/t480s: Disable TPM2 to mitigate SeaBIOS lag
SeaBIOS was lagging a lot, on startup and when executing
almost any payload, especially when doing anything in the
ESC menu.

I set the debug level to *21*, and thoroughly analysed the
logs. I found entries such as this:

Checking for bootsplash
WARNING - Timeout at wait_reg8:81!
TCGBIOS: Return value from sending TPM2_CC_StirRandom = 0x00000000
WARNING - Timeout at wait_reg8:81!
TCGBIOS: Return value from sending TPM2_CC_GetRandom = 0x00000000
WARNING - Timeout at wait_reg8:81!
TCGBIOS: Return value from sending TPM2_CC_HierarchyChangeAuth = 0x00000000
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc16e
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc1c5
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc211
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc25d
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc2a9
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc2f5
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc341
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc38d
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc3d9
Searching bootorder for: HALT
Mapping hd drive 0x000f49e0 to 0

I'm not quite certain what the problem is, but disabling TPM2
made the problem go away; SeaBIOS is snappy again.

TPM is security threatre anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-29 01:20:33 +00:00
Leah Rowe 754bd1e6ca rom.sh: Name pico directory serprog_pico
Previously serprog_rp2040, but we now also support
the RP2530 boards.

Therefore, serprog_pico is a nice generic name. The
directory on release archives will now be serprog_pico
instead of serprog_rp2040; it will contain serprog images
for both RP2040 and RP2530 devices.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-28 16:46:59 +00:00
Leah Rowe db22308eba add 2024 to Riku's copyright header on rom.sh
he forgot to do this in the recently merged pico2
support. i'm doing it for him as a matter of courtesy.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-28 13:24:01 +00:00
Leah Rowe 4fa5f696db Merge pull request 'rp2530' (#258) from Riku_V/lbmk:rp2530 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/258
2024-12-28 12:26:39 +00:00
Riku Viitanen a5e0360992 pico-sdk: update to 2.1.0
this brings support for a new microcontroller platform rp2530.

total number of pico boards supported now: 97

TEST: built them all

Tested-by: Riku Viitanen <riku.viitanen@protonmail.com>
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2024-12-28 04:02:08 +02:00
Riku Viitanen e2f8cc7f3e pico-serprog: enable building for multiple pico chips
rp2040 and rp2530 platforms can't share a cmake build directory. we
could just delete the build directory after every compilation, but that
would be really wasteful (every tool would need to be recomiled every
time. instead create new build directories as new plaforms are found
and symlink them to the point where the build directory used to be.

to find out which platform we're compiling for, we crudely parse the
board headers file.

there surely would be better ways to do this, but this hack works
with all the boards in pico-sdk 2.1.0.

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2024-12-28 03:53:25 +02:00
Leah Rowe ccc2b4d589 add spdx headers to dependencies configs
these used to be separate scripts under gpl 3+, so it makes
sense to clarify the licensing situation

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-27 14:01:07 +00:00
Leah Rowe a3969701e6 dependencies/debian: fix debian sid
change python3-distutils to python3-distutils-extra

the latter is still available in debian sid, but not
the former. however, installing this should still
provide the additional files required.

with this, the debian script is now compatible with
both debian sid and debian stable(bookworm, presently).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-27 13:58:29 +00:00
Leah Rowe 8f370cb60d add spdx headers to various config files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-27 02:24:38 +00:00
Leah Rowe d591ea4c5d git.sh: don't initialise livepull globally
set this variable in the tmpclone function. otherwise,
certain submodules might always download every time,
when handling multiple projects.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-26 23:47:48 +00:00
Leah Rowe b5da9feba3 vendor.sh: Print useful message on ./mk inject
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-26 22:25:07 +00:00
Leah Rowe 12c6259cb2 vendor.sh: Handle FSP insertion post-release
The Libreboot 20241206 release provided FSP pre-assembled
and inserted into the ROM images; the only file inserted
by vendor.sh was the Intel ME.

Direct distribution of an unmodified FSP image is permitted
by Intel, provided that the license notice is given among
other requirements. Due to how coreboot works, it must split
up the FSP into subcomponents, and adjust certain pointers
within the -M component (for raminit).

Such build-time modifications are perfectly fine in a coreboot
context, where it is expected that you are building from source.
The end result is simply what you use.

In a distribution such as Libreboot, where we provide pre-built
images, this becomes problematic. It's a technicality of the
license, and it seems that Intel themselves probably intended
for Libreboot to use the FSP this way anyway, since it is they
who seem to be the author of SplitFspBin.py, which is the
utility that coreboot uses for splitting up the FSP image.

Due to the technicality of the licensing, the FSP shall now
be scrubbed from releases, and re-inserted.

Coreboot was inserting the -S component with LZ4 compression,
which is bad news for ./mk inject beacuse the act of compression
is currently not reproducible. Therefore, coreboot has been
modified not to compress this section, and the inject command
doesn't compress it either. This means that the S file is using
about 180KB in flash, instead of about 140KB. This is totally OK.

The _fsp targets are retained, but set to release=n, because these
targets *still* don't scrub fsp.bin; if released, they would
include fsp files, so they've been set to release=n. These can
be used on older Libreboot release archives, for compatibility.

The new ROM images released for the affected machines are:

t480_vfsp_16mb
t480s_vfsp_16mb
dell3050micro_vfsp_16mb

Note the use of _vfsp instead of _fsp. These images are released,
unlike _fsp, and they lack fspm/fsps in the image. FSP S/M must
be inserted using ./mk inject.

This has been tested and confirmed to boot just fine.
The 20241206 images will be re-compiled and re-uploaded with this
and other recent changes, to make Libreboot 20241206 rev8.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-26 22:05:16 +00:00
Leah Rowe 7813205146 Remove legacy update/vendor commands
We only use ./mk now.

./build still exists for now. This will be removed
in a future revision, when the trees script is removed
and merged with the main script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-25 09:10:57 +00:00
Leah Rowe 07037561bd lbmk: remove use of deprecated ./vendor command
use ./mk instead, because in a future change to lbmk,
only ./mk will be used and the other commands will
be removed.

with this change, the ./vendor, ./build and ./update
commands are no longer used. these commands still work,
for backwards compatibility, but they are deprecated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 16:58:23 +00:00
Leah Rowe 5d1f182306 vendor.sh: Safer exit when vendorfiles not needed
When vendor files were not needed on a given board,
the script would directly exit. This is bad, because
the inject functions are called directly from the main
script, which means the parent instance of lbmk.

This means that the lock file and temporary files were
not being removed on exit. On a subsequent run, this
would cause the error stating that a lock file is present,
which would cause further error, making the user believe
something is broken in lbmk.

Modify the behaviour accordingly; exits are now returns,
and these are handled in the calling functions, in such
a way that a proper exit occurs, whereby temporary files
and the lock file are deleted.

For context, please read the main "build" script where
it calls vendor_inject and vendor_download. At the end
of that script, it calls tmp_cleanup, which removes the
TMPDIR that was created, and the lock file. In lbmk,
the TMPDIR is not /tmp, but rather a subdirectory
under /tmp, so that further calls to mktemp create
everything under one single temporary directory, which
lbmk automatically removes on exit.

Therefore, this patch also avoids leaving temporary files
laying around on the disk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 14:09:29 +00:00
Leah Rowe a18175a5df data/deguard: Remove unused patch
The appdir.patch file was used on the older deguard
version, prior to Mate Kukri's rewrite. This patch is
no longer required, and no longer used, so it can be
removed safely from lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 12:40:53 +00:00
Leah Rowe ee8f53b96f lib.sh: Safer exit from ./mk dependencies
The exit was dependent upon install_packages returning
zero status, which it always would in practise, due to
its design, but this exit must always be observed, so
the code has been modified to honour this design.

A direct exit violates lbmk's design in most instances,
where a temporary directory and lock file has already
been created; at this stage, no such act was performed,
so a direct exit is perfectly acceptable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 12:39:05 +00:00
Leah Rowe a8b35c88cf remove geteltorito and mtools from lbmk
we needed these for extracting intel vga roms from
lenovoo updates, for t480, very briefly. about an hour
after i pushed that patch, mate kukri fixed libgfxinit
and then i removed the vgarom integration because it
wasn't needed anymore.

however, i forgot to remove geteltorito/mtools from
dependencies. some distros like fedora were problematic
about it.

the best thing about bugs is when you don't have to fix them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-22 23:13:43 +00:00
Leah Rowe 1dd32ea548 rom.sh: support grub-first setups
in this setup, seabios is never the default payload, grub is,
but only if grub is enabled.

set this in target.cfg:

payload_grubsea="y"

if payload_grub isn't enabled, this is auto-set to n

ditto if initmode=normal

NOTE: if flashing libgfx setups, you should make sure
that you're not booting with a graphics card, only intel
graphics. this setting will intentionally not be documented,
because it's not recommended, but is being implemented for
testing purposes (and i implemented it for some guy who i
think is cool). i'll probably also use this myself, since
i already do grub-only setups on all my own machines.

seagrub is the default on x86 because of past instabilities
with grub. to mitigate in case of future issues, since seabios
is always stable, we reduce the chance of bricks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-18 07:15:18 +00:00
1118 changed files with 77199 additions and 34269 deletions
+6 -1
View File
@@ -24,11 +24,12 @@
/push
/version
/versiondate
/.version
/.versiondate
/vendorfiles/
*me.bin
*sch5545ec.bin
/mrc/
/util/nvmutil/nvm
/src/
/CHANGELOG
/todo.txt
@@ -39,3 +40,7 @@
*.tar.*
/m
/f
/r
/e
/xbmkpath/
/xbmkwd/
+39 -105
View File
@@ -1,123 +1,57 @@
Libreboot
=========
Find libreboot documentation at <https://libreboot.org/>
Documentation: [libreboot.org](https://libreboot.org)\
Support: [\#libreboot](https://web.libera.chat/#libreboot) on
[Libera](https://libera.chat/) IRC
The `libreboot` project provides
[libre](https://libreboot.org/freedom-status.html) *boot
firmware* that initializes the hardware (e.g. memory controller, CPU,
peripherals) on specific Intel/AMD x86 and ARM targets, which
then starts a bootloader for your operating system. Linux/BSD are
well-supported. It replaces proprietary BIOS/UEFI firmware. Help is available
via [\#libreboot IRC](https://web.libera.chat/#libreboot)
on [Libera](https://libera.chat/) IRC.
Libreboot provides
[libre](https://libreboot.org/freedom-status.html)
boot firmware on
[supported motherboards](https://libreboot.org/docs/install/#which-systems-are-supported-by-libreboot). It replaces proprietary vendor BIOS/UEFI implementations, by
* Using coreboot to initialize the hardware (e.g. memory controller, CPU, etc.) while
minimizing unwanted functionality (e.g. backdoors such as the Intel Management Engine)
* ... which runs a payload such as SeaBIOS, GRUB, or U-Boot
* ... which loads your operating system's boot loader (BSD and Linux-based
[systems](systems) are supported).
Why use Libreboot?
==================
Why use Libreboot, and what is coreboot?
----------------------------------------
Why should you use *libreboot*?
----------------------------
A lot of users who use libre operating systems still use proprietary boot
firmware, which often contain backdoors and bugs, hampering
[user freedom](https://writefreesoftware.org) and
[right to repair](https://www.eff.org/issues/right-to-repair).
Libreboot gives you freedoms that you otherwise can't get with most other
boot firmware. It's extremely powerful and configurable for many use cases.
[coreboot](https://coreboot.org) provides libre boot firmware by initializing
the hardware then running a payload. However, coreboot is notoriously difficult
to configure and install for most non-technical users, requiring detailed
technical knowledge of hardware.
You have rights. The right to privacy, freedom of thought, freedom of speech
and the right to read. In this context, Libreboot gives you these rights.
Your freedom matters.
[Right to repair](https://vid.puffyan.us/watch?v=Npd_xDuNi9k) matters.
Many people use proprietary (non-libre)
boot firmware, even if they use [a libre OS](https://www.openbsd.org/).
Proprietary firmware often contains backdoors (more info on the FAQ), and it
and can be buggy. The libreboot project was founded in December 2013,
with the express purpose of making coreboot firmware accessible for
non-technical users.
Libreboot solves this by being **a coreboot distribution** (in the same way
that Alpine Linux is a Linux distribution). It provides a fully automated build
system that downloads and compiles pre-configured ROM images for supported
motherboards, so end-users could easily fetch images to flash onto their
devices.
The `libreboot` project uses [coreboot](https://www.coreboot.org/) for [hardware
initialisation](https://doc.coreboot.org/getting_started/architecture.html).
Coreboot is notoriously difficult to install for most non-technical users; it
handles only basic initialization and jumps to a separate
[payload](https://doc.coreboot.org/payloads.html) program (e.g.
[GRUB](https://www.gnu.org/software/grub/),
[Tianocore](https://www.tianocore.org/)), which must also be configured.
*The libreboot software solves this problem*; it is a *coreboot distribution* with
an automated build system (named *lbmk*) that builds complete *ROM images*, for
more robust installation. Documentation is provided.
Libreboot also produces documentation aimed at non-technical users and
excellent user support via IRC.
How does Libreboot differ from coreboot?
========================================
In the same way that *Debian* is a GNU+Linux distribution, `libreboot` is
a *coreboot distribution*. If you want to build a ROM image from scratch, you
otherwise have to perform expert-level configuration of coreboot, GRUB and
whatever other software you need, to prepare the ROM image. With *libreboot*,
you can literally download from Git or a source archive, and run `make`, and it
will build entire ROM images. An automated build system, named `lbmk`
(Libreboot MaKe), builds these ROM images automatically, without any user input
or intervention required. Configuration has already been performed in advance.
If you were to build regular coreboot, without using libreboot's automated
build system, it would require a lot more intervention and decent technical
knowledge to produce a working configuration.
Regular binary releases of `libreboot` provide these
ROM images pre-compiled, and you can simply install them, with no special
knowledge or skill except the ability to follow installation instructions
and run commands BSD/Linux.
Project goals
=============
- *Support as much hardware as possible!* Libreboot aims to eventually
have *maintainers* for every board supported by coreboot, at every
point in time.
- *Make coreboot easy to use*. Coreboot is notoriously difficult
to install, due to an overall lack of user-focused documentation
and support. Most people will simply give up before attempting to
install coreboot. Libreboot's automated build system and user-friendly
installation instructions solves this problem.
Libreboot attempts to bridge this divide by providing a build system
automating much of the coreboot image creation and customization.
Secondly, the project produces documentation aimed at non-technical users.
Thirdly, the project attempts to provide excellent user support via IRC.
Libreboot already comes with a payload (GRUB), flashprog and other
needed parts. Everything is fully integrated, in a way where most of
the complicated steps that are otherwise required, are instead done
for the user in advance.
You can download ROM images for your libreboot system and install
them without having to build anything from source. If, however, you are
interested in building your own image, the build system makes it relatively
easy to do so.
Not a coreboot fork!
--------------------
Libreboot is *not a fork of coreboot*. Every so often, the project
re-bases on the latest version of coreboot, with the number of custom
patches in use minimized. Tested, *stable* (static) releases are then provided
in Libreboot, based on specific coreboot revisions.
How to help
===========
Contribute
----------
You can check bugs listed on
the [bug tracker](https://codeberg.org/libreboot/lbmk/issues).
If you spot a bug and have a fix, the website has instructions for how to send
patches, and you can also report it. Also, this entire website is
written in Markdown and hosted in a [separate
repository](https://codeberg.org/libreboot/lbwww) where you can send patches.
You may use Codeberg pull requests to send patches with bug fixes or other
improvements. This repository hosts the code for the main build system.
The website lives in [a separate repository](https://codeberg.org/libreboot/lbwww).
Any and all development discussion and user support are all done on the IRC
channel. More information is on <https://libreboot.org/contact.html>.
Development is also done on the IRC channel.
LICENSE FOR THIS README
=======================
License for this README
-----------------------
It's just a README file. This README file is released under the terms of the
Creative Commons Zero license, version 1.0 of the license, which you can
read here:
It's just a README file. It is released under
[Creative Commons Zero, version 1.0](https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt).
<https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt>
-132
View File
@@ -1,132 +0,0 @@
#!/usr/bin/env sh
# SPDX-License-Identifier: GPL-3.0-or-later
# Copyright (c) 2014-2015,2020-2024 Leah Rowe <leah@libreboot.org>
# Copyright (c) 2015 Patrick "P. J." McDermott <pj@pehjota.net>
# Copyright (c) 2015-2016 Klemens Nanni <contact@autoboot.org>
# Copyright (c) 2022 Caleb La Grange <thonkpeasant@protonmail.com>
set -u -e
if [ "./${0##*/}" != "${0}" ] || [ ! -f "build" ] || [ -L "build" ]; then
printf "You must run this in the proper work directory.\n" 1>&2
exit 1
fi
. "include/lib.sh"
. "include/vendor.sh"
. "include/mrc.sh"
eval `setvars "" vdir src_dirname srcdir mode xp ser`
err="fail"
main()
{
[ $# -lt 1 ] && $err "bad command"
spath="script/$1"; shcmd="shift 1"
[ "${1#-*}" != "$1" ] && spath="script/trees" && shcmd=":"
for g in "which git" "git config --global user.name" \
"git config --global user.email" "git_init"; do
eval "$g 1>/dev/null 2>/dev/null || $err \"Unconfigured: $g\""
done
case "${spath#script/}" in
version) printf "%s\nWebsite: %s\n" "$relname" "$projectsite" ;;
release) shift 1; mkrelease $@ ;;
inject) shift 1; vendor_inject $@ ;;
download) shift 1; vendor_download $@ ;;
roms)
[ $# -gt 1 ] && [ "$2" = "serprog" ] && \
mk -b stm32-vserprog pico-serprog && return 0
shift 1; x_ ./mk -b coreboot $@ ;;
*)
[ -f "$spath" ] || $err "bad command"
$shcmd; "$spath" $@ || $err "excmd: $spath $(echo "$@")" ;;
esac
set -u -e # some commands disable them. turn them on!
}
git_init()
{
[ -L ".git" ] && return 1
[ -e ".git" ] && return 0
eval `setvars "$(date -Rud @$versiondate)" cdate _nogit`
git init || return 1
git add -A . || return 1
git commit -m "$projectname $version" --date "$cdate" \
--author="xbmk <xbmk@example.com>" || return 1
git tag -a "$version" -m "$projectname $version" || return 1
}
mkrelease()
{
export XBMK_RELEASE="y"
vdir="release"
while getopts d:m: option; do
[ -z "$OPTARG" ] && $err "empty argument not allowed"
case "$option" in
d) vdir="$OPTARG" ;;
m) mode="$OPTARG" ;;
*) $err "invalid option '-$option'" ;;
esac
done
vdir="$vdir/$version"
src_dirname="${relname}_src"
srcdir="$vdir/$src_dirname"
[ -e "$vdir" ] && $err "already exists: \"$vdir\""
mkdir -p "$vdir" || $err "mkvdir: !mkdir -p \"$vdir\""
git clone . "$srcdir" || $err "mkdir: !gitclone \"$srcdir\""
touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
build_release
printf "\n\nDONE! Check release files under %s\n" "$vdir"
}
build_release()
{
(
cd "$srcdir" || $err "$vdir: !cd \"$srcdir\""
./mk -f; x_ rm -Rf tmp; rmgit .
x_ mv src/docs docs
) || $err "can't create release files"
git log --graph --pretty=format:'%Cred%h%Creset %s %Creset' \
--abbrev-commit > "$srcdir/CHANGELOG" || $err "!gitlog $srcdir"
rm -f "$srcdir/lock" || $err "can't remove lock file in $srcdir"
(
cd "${srcdir%/*}" || $err "$vdir: mktarball \"$srcdir\""
mktarball "${srcdir##*/}" "${srcdir##*/}.tar.xz" || $err "$vdir: mksrc"
) || $err "can't create src tarball"
[ "$mode" = "src" ] && return 0
touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
(
cd "$srcdir" || $err "$vdir: 2 !cd \"$srcdir\""
mk -b coreboot pico-serprog stm32-vserprog pcsx-redux
x_ mv bin ../roms
) || $err "can't build rom images"
rm -Rf "$srcdir" || $err "!rm -Rf $srcdir"
}
fail()
{
tmp_cleanup || printf "WARNING: can't rm tmpfiles: %s\n" "$TMPDIR" 1>&2
err_ "${1}"
}
tmp_cleanup()
{
[ "$xbmk_parent" = "y" ] || return 0
[ "$TMPDIR" = "/tmp" ] || rm -Rf "$TMPDIR" || return 1
rm -f lock || return 1
}
main $@
tmp_cleanup || err_ "can't rm TMPDIR upon non-zero exit: $TMPDIR"
@@ -1,56 +0,0 @@
From f22f408956bf02609a96b7d72fb3321da159bfc6 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.huber@secunet.com>
Date: Tue, 22 Jun 2021 13:49:44 +0000
Subject: [PATCH 1/1] cbfstool: Make use of spurious null-termination
The null-termination of `filetypes` was added after the code was
written, obviously resulting in NULL dereferences. As some more
code has grown around the termination, it's hard to revert the
regression, so let's update the code that still used the array
length.
This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
which actually did fix something, but only one path while it broke
two others. We should be careful with fixes, they can always break
something else. Especially when a dumb tool triggered the patching
it seems likely that fewer people looked into related code.
Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
util/cbfstool/common.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index e2ed38ffc4..539d0baccf 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -168,10 +168,10 @@ void print_supported_architectures(void)
void print_supported_filetypes(void)
{
- int i, number = ARRAY_SIZE(filetypes);
+ int i;
- for (i=0; i<number; i++) {
- printf(" %s%c", filetypes[i].name, (i==(number-1))?'\n':',');
+ for (i=0; filetypes[i].name; i++) {
+ printf(" %s%c", filetypes[i].name, filetypes[i + 1].name ? ',' : '\n');
if ((i%8) == 7)
printf("\n");
}
@@ -180,7 +180,7 @@ void print_supported_filetypes(void)
uint64_t intfiletype(const char *name)
{
size_t i;
- for (i = 0; i < (sizeof(filetypes) / sizeof(struct typedesc_t)); i++)
+ for (i = 0; filetypes[i].name; i++)
if (strcmp(filetypes[i].name, name) == 0)
return filetypes[i].type;
return -1;
--
2.39.2
-2
View File
@@ -1,2 +0,0 @@
tree="coreboot413"
rev="5c186c6777c9438ff4681929c9c25c98dee28bef"
@@ -10,17 +10,19 @@ CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
@@ -57,6 +59,7 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@@ -68,6 +71,7 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
@@ -75,15 +79,19 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@@ -93,6 +101,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_QOTOM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
@@ -104,7 +113,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
CONFIG_MAINBOARD_VERSION="1.0"
@@ -120,24 +131,26 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
# CONFIG_CONSOLE_POST is not set
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -147,7 +160,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -182,6 +194,7 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -197,6 +210,15 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_PANTHERLAKE_CRB is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@@ -204,7 +226,6 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
@@ -214,10 +235,8 @@ CONFIG_D3COLD_SUPPORT=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -256,8 +275,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x80000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -272,11 +292,15 @@ CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# CONFIG_TOP_SWAP_REDUNDANCY is not set
#
# CPU
@@ -355,6 +379,7 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -367,7 +392,6 @@ CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -379,6 +403,9 @@ CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@@ -395,12 +422,14 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -419,15 +448,18 @@ CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
CONFIG_DRAM_SUPPORT_DDR3=y
CONFIG_DRAM_SUPPORT_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -445,6 +477,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -507,7 +540,6 @@ CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
@@ -594,7 +626,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@@ -608,9 +639,20 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
+2
View File
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
@@ -10,17 +10,19 @@ CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
@@ -57,6 +59,7 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@@ -68,6 +71,7 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
@@ -75,15 +79,19 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@@ -93,6 +101,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_QOTOM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
@@ -104,7 +113,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
CONFIG_MAINBOARD_VERSION="1.0"
@@ -120,24 +131,26 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
# CONFIG_CONSOLE_POST is not set
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -147,7 +160,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -182,6 +194,7 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -197,6 +210,15 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_PANTHERLAKE_CRB is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@@ -204,7 +226,6 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
@@ -214,10 +235,8 @@ CONFIG_D3COLD_SUPPORT=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -256,8 +275,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x80000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -272,11 +292,15 @@ CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# CONFIG_TOP_SWAP_REDUNDANCY is not set
#
# CPU
@@ -355,6 +379,7 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -367,7 +392,6 @@ CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -379,6 +403,9 @@ CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@@ -395,12 +422,14 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -419,15 +448,18 @@ CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
CONFIG_DRAM_SUPPORT_DDR3=y
CONFIG_DRAM_SUPPORT_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -445,6 +477,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -507,7 +540,6 @@ CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
@@ -594,7 +626,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@@ -608,9 +639,20 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
+2
View File
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
@@ -10,17 +10,19 @@ CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
@@ -57,6 +59,7 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@@ -68,6 +71,7 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
@@ -75,15 +79,19 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@@ -93,6 +101,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_QOTOM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
@@ -104,7 +113,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
CONFIG_MAINBOARD_VERSION="1.0"
@@ -120,25 +131,27 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
# CONFIG_CONSOLE_POST is not set
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -148,7 +161,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -183,6 +195,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -198,6 +211,15 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_PANTHERLAKE_CRB is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@@ -205,7 +227,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
@@ -213,10 +234,8 @@ CONFIG_D3COLD_SUPPORT=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
CONFIG_COREBOOT_ROMSIZE_KB_512=y
@@ -255,8 +274,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -271,11 +291,15 @@ CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# CONFIG_TOP_SWAP_REDUNDANCY is not set
#
# CPU
@@ -354,6 +378,7 @@ CONFIG_SUPERIO_SMSC_LPC47M15X=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -366,7 +391,6 @@ CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -378,6 +402,9 @@ CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@@ -394,12 +421,14 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -415,14 +444,17 @@ CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_USE_DDR2=y
CONFIG_DRAM_SUPPORT_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -440,6 +472,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -501,7 +534,6 @@ CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
@@ -592,7 +624,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@@ -607,9 +638,20 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
@@ -10,17 +10,19 @@ CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
@@ -57,6 +59,7 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@@ -68,6 +71,7 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
@@ -75,15 +79,19 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@@ -93,6 +101,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_QOTOM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
@@ -104,7 +113,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
CONFIG_MAINBOARD_VERSION="1.0"
@@ -120,25 +131,27 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
# CONFIG_CONSOLE_POST is not set
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -148,7 +161,6 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
@@ -183,6 +195,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -198,6 +211,15 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_PANTHERLAKE_CRB is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@@ -205,7 +227,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
@@ -213,10 +234,8 @@ CONFIG_D3COLD_SUPPORT=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -255,8 +274,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -271,11 +291,15 @@ CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# CONFIG_TOP_SWAP_REDUNDANCY is not set
#
# CPU
@@ -354,6 +378,7 @@ CONFIG_SUPERIO_SMSC_LPC47M15X=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -366,7 +391,6 @@ CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -378,6 +402,9 @@ CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@@ -394,12 +421,14 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -415,14 +444,17 @@ CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_USE_DDR2=y
CONFIG_DRAM_SUPPORT_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -440,6 +472,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -501,7 +534,6 @@ CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
@@ -592,7 +624,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@@ -607,9 +638,20 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
+2
View File
@@ -1,3 +1,5 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
+18
View File
@@ -0,0 +1,18 @@
3rdparty/fsp/EagleStreamFspBinPkg
3rdparty/fsp/MeteorLakeFspBinPkg
3rdparty/fsp/IceLakeFspBinPkg
3rdparty/fsp/AmberLakeFspBinPkg
3rdparty/fsp/DenvertonNSFspBinPkg
3rdparty/fsp/TigerLakeFspBinPkg
3rdparty/fsp/CedarIslandFspBinPkg
3rdparty/fsp/ElkhartLakeFspBinPkg
3rdparty/fsp/CometLakeFspBinPkg
3rdparty/fsp/WhitleyFspBinPkg
3rdparty/fsp/ArrowLakeFspBinPkg
3rdparty/fsp/IdavilleFspBinPkg
3rdparty/fsp/BraswellFspBinPkg
3rdparty/fsp/CoffeeLakeFspBinPkg
3rdparty/fsp/RaptorLakeFspBinPkg
3rdparty/fsp/ApolloLakeFspBinPkg
3rdparty/fsp/SkylakeFspBinPkg
3rdparty/vboot/tests
@@ -1,7 +1,7 @@
From f625e31ee3abb867e775ab0cb724550825699c36 Mon Sep 17 00:00:00 2001
From 03e8f5f33723fd291e30c5305fa2f5eb22bdf656 Mon Sep 17 00:00:00 2001
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
Date: Wed, 27 Oct 2021 13:36:01 +0200
Subject: [PATCH 01/51] add c3 and clockgen to apple/macbook21
Subject: [PATCH 01/48] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +
@@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644
end
end
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From 8821f229d4fe48153ec7a45e0e04c3b2a3cd8c7c Mon Sep 17 00:00:00 2001
From da742084f51bb7e97472605d6eff0726fd7a5863 Mon Sep 17 00:00:00 2001
From: persmule <persmule@gmail.com>
Date: Sun, 31 Oct 2021 23:33:26 +0000
Subject: [PATCH 02/51] lenovo/t400: Enable all SATA ports
Subject: [PATCH 02/48] lenovo/t400: Enable all SATA ports
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -15,7 +15,7 @@ This patch unmasked all SATA ports found within t400s with factory firmware.
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index 259c3e1b21..3d007533a4 100644
index 9e056772e9..9361f330d2 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
@@ -30,5 +30,5 @@ index 259c3e1b21..3d007533a4 100644
register "sata_traffic_monitor" = "0"
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From 0298639b6e80c8950fbb4484180b7195883ab8c1 Mon Sep 17 00:00:00 2001
From 278c2a989c025c1b3a097966968c8d253c973a3e Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 3 Jan 2022 19:06:22 +0000
Subject: [PATCH 03/51] lenovo/x230: set me_state=Disabled in cmos.default
Subject: [PATCH 03/48] lenovo/x230: set me_state=Disabled in cmos.default
I only recently found out about this. It's possible to use me_cleaner to
do the same thing, but some people might just flash coreboot and not do
@@ -33,5 +33,5 @@ index 732e214b32..8454f0eac0 100644
-me_state=Normal
+me_state=Disabled
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From c697c90ace86edfe724c86bd6a680cf0ae0e4b58 Mon Sep 17 00:00:00 2001
From 63357b7f8c9da3a8d644542c70f50fc9bc77a8fc Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 2 Mar 2022 21:50:01 +0000
Subject: [PATCH 04/51] set me_state=Disabled on all cmos.default files!
Subject: [PATCH 04/48] set me_state=Disabled on all cmos.default files!
yeah. why the hell isn't this the default
@@ -120,5 +120,5 @@ index d61046df6b..8c793fd1c3 100644
-me_state=Enable
+me_state=Disabled
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From d2f579b82921c2c35e4cf756db0ca476fbadfac1 Mon Sep 17 00:00:00 2001
From 434136e0aca4839e449e3841a5e993688b4586f0 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
Subject: [PATCH 05/51] util/ifdtool: add --nuke flag (all 0xFF on region)
Subject: [PATCH 05/48] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
@@ -16,22 +16,22 @@ Rebased since the last revision update in lbmk.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
1 file changed, 83 insertions(+), 31 deletions(-)
util/ifdtool/ifdtool.c | 116 +++++++++++++++++++++++++++++------------
1 file changed, 84 insertions(+), 32 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 32b2081d93..1473cf058b 100644
index 0592785bf6..cab934c3a5 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -2204,6 +2204,7 @@ static void print_usage(const char *name)
@@ -2240,6 +2240,7 @@ static void print_usage(const char *name)
" tgl - Tiger Lake\n"
" wbg - Wellsburg\n"
" -S | --setpchstrap Write a PCH strap\n"
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
@@ -2212,6 +2213,60 @@ static void print_usage(const char *name)
" -T | --topswapsize Set the Top Swap Block Size PCH strap value\n"
" Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n"
@@ -2251,6 +2252,60 @@ static void print_usage(const char *name)
"\n");
}
@@ -92,23 +92,23 @@ index 32b2081d93..1473cf058b 100644
int main(int argc, char *argv[])
{
int opt, option_index = 0;
@@ -2219,6 +2274,7 @@ int main(int argc, char *argv[])
@@ -2258,6 +2313,7 @@ int main(int argc, char *argv[])
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
+ int mode_nuke = 0;
int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
char *region_type_string = NULL, *region_fname = NULL;
const char *layout_fname = NULL;
@@ -2254,6 +2310,7 @@ int main(int argc, char *argv[])
{"validate", 0, NULL, 't'},
int mode_settopswapsize = 0;
char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL;
@@ -2294,6 +2350,7 @@ int main(int argc, char *argv[])
{"setpchstrap", 1, NULL, 'S'},
{"newvalue", 1, NULL, 'V'},
{"topswapsize", 1, NULL, 'T'},
+ {"nuke", 1, NULL, 'N'},
{0, 0, 0, 0}
};
@@ -2303,35 +2360,8 @@ int main(int argc, char *argv[])
@@ -2343,35 +2400,8 @@ int main(int argc, char *argv[])
region_fname++;
// Descriptor, BIOS, ME, GbE, Platform
// valid type?
@@ -146,10 +146,11 @@ index 32b2081d93..1473cf058b 100644
fprintf(stderr, "No such region type: '%s'\n\n",
region_type_string);
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
@@ -2508,6 +2538,22 @@ int main(int argc, char *argv[])
case 't':
mode_validate = 1;
@@ -2552,7 +2582,23 @@ int main(int argc, char *argv[])
mode_settopswapsize = 1;
top_swap_size_arg = optarg;
break;
- case 'v':
+ case 'N':
+ region_type_string = strdup(optarg);
+ if (!region_type_string) {
@@ -166,12 +167,13 @@ index 32b2081d93..1473cf058b 100644
+ }
+ mode_nuke = 1;
+ break;
case 'v':
+ Case 'v':
print_version();
exit(EXIT_SUCCESS);
@@ -2524,7 +2570,8 @@ int main(int argc, char *argv[])
break;
@@ -2571,7 +2617,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 |
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
+ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
@@ -179,9 +181,9 @@ index 32b2081d93..1473cf058b 100644
fprintf(stderr, "You may not specify more than one mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2533,7 +2580,8 @@ int main(int argc, char *argv[])
@@ -2580,7 +2627,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 +
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
@@ -189,7 +191,7 @@ index 32b2081d93..1473cf058b 100644
fprintf(stderr, "You need to specify a mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2646,6 +2694,10 @@ int main(int argc, char *argv[])
@@ -2746,6 +2794,10 @@ int main(int argc, char *argv[])
write_image(new_filename, image, size);
}
@@ -201,5 +203,5 @@ index 32b2081d93..1473cf058b 100644
struct fpsba *fpsba = find_fpsba(image, size);
struct fmsba *fmsba = find_fmsba(image, size);
--
2.39.5
2.47.3
@@ -1,20 +1,20 @@
From a5bc59037dabd95b6595c5aaf38b83da2a91de54 Mon Sep 17 00:00:00 2001
From 91e4334541da6522d5a0bf5277ac478c891e7117 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
Subject: [PATCH 06/51] mb/dell/e6400: Enable 01.0 device in devicetree for
Subject: [PATCH 06/48] mb/dell/e6400: Enable 01.0 device in devicetree for
dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6400/devicetree.cb | 2 +-
src/mainboard/dell/gm45_latitude/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
index bb954cbd7b..e9f3915d17 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
+++ b/src/mainboard/dell/e6400/devicetree.cb
@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
diff --git a/src/mainboard/dell/gm45_latitude/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
index 5919803be2..76dae87153 100644
--- a/src/mainboard/dell/gm45_latitude/devicetree.cb
+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
@@ -18,7 +18,7 @@ chip northbridge/intel/gm45
ops gm45_pci_domain_ops
device pci 00.0 on end # host bridge
@@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644
device pci 02.1 on end # Display
device pci 03.0 on end # ME
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From f883599a362f1383f3712b72516f76187d0a9cbe Mon Sep 17 00:00:00 2001
From 3ebe9e03ec563e5adb43337340fe973aa66a984a Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 07/51] Remove warning for coreboot images built without a
Subject: [PATCH 07/48] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
@@ -35,5 +35,5 @@ index 5f988dac1b..516133880f 100644
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From ec27f5414c78d493ec7be4cd055ac877ce9ea178 Mon Sep 17 00:00:00 2001
From 0e2fa472354b2e68ffbfc01d5bb225ca9d8973f0 Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Thu, 22 Jun 2023 16:44:27 +0300
Subject: [PATCH 18/51] HACK: Disable coreboot related BL31 features
Subject: [PATCH 08/48] HACK: Disable coreboot related BL31 features
I don't know why, but removing this BL31 make argument lets gru-kevin
power off properly when shut down from Linux. Needs investigation.
@@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation.
1 file changed, 3 deletions(-)
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
index cb43897efd..a9e5ff399a 100644
index efd628fee7..6c4f3d702e 100644
--- a/src/arch/arm64/Makefile.mk
+++ b/src/arch/arm64/Makefile.mk
@@ -173,9 +173,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
@@ -156,9 +156,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
# Always enable crash reporting, even on a release build
BL31_MAKEARGS += CRASH_REPORTING=1
@@ -24,5 +24,5 @@ index cb43897efd..a9e5ff399a 100644
BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
--
2.39.5
2.47.3
@@ -1,430 +0,0 @@
From 40545928c415c27d3a30748e4bfdee7f9d8f82f9 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 19 Aug 2023 16:19:10 -0600
Subject: [PATCH 08/51] mb/dell: Add Latitude E6530 (Ivy Bridge)
Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was
not tested. I do not physically have this system; someone with physical
access to one sent me the output of autoport which I then modified to
produce this port.
I was also sent the vbios obtained using intel_bios_dumper while running
version A22 of the vendor firmware, which I then processed using
`intelvbttool --inoprom vbios.bin --outvbt data.vbt` to obtain data.vbt.
This was originally tested and found to be working as a standalone board
port in Libreboot, though this variant based port in upstream coreboot
has not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/Kconfig | 8 +
.../dell/snb_ivb_latitude/Kconfig.name | 3 +
.../snb_ivb_latitude/variants/e6530/data.vbt | Bin 0 -> 4280 bytes
.../variants/e6530/early_init.c | 14 ++
.../snb_ivb_latitude/variants/e6530/gpio.c | 192 ++++++++++++++++++
.../variants/e6530/hda_verb.c | 32 +++
.../variants/e6530/overridetree.cb | 37 ++++
7 files changed, 286 insertions(+)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index be9ac37845..03377275f0 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -23,6 +23,12 @@ config BOARD_DELL_LATITUDE_E6430
select MAINBOARD_USES_IFD_GBE_REGION
select SOUTHBRIDGE_INTEL_C216
+config BOARD_DELL_LATITUDE_E6530
+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ select BOARD_ROMSIZE_KB_12288
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select SOUTHBRIDGE_INTEL_C216
+
if BOARD_DELL_SNB_IVB_LATITUDE_COMMON
config DRAM_RESET_GATE_GPIO
@@ -33,6 +39,7 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
+ default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@@ -42,6 +49,7 @@ config USBDEBUG_HCD_INDEX
config VARIANT_DIR
default "e6430" if BOARD_DELL_LATITUDE_E6430
+ default "e6530" if BOARD_DELL_LATITUDE_E6530
config VGA_BIOS_ID
default "8086,0166"
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
index 183252630a..d89185d670 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -2,3 +2,6 @@
config BOARD_DELL_LATITUDE_E6430
bool "Latitude E6430"
+
+config BOARD_DELL_LATITUDE_E6530
+ bool "Latitude E6530"
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
GIT binary patch
literal 4280
zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV
zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU
zIJ+cPr4+cc-@WIad+wQY&YW{+c1J!nPPgn&^^N3Hy*D37jg0=7CSl@*=mXr>x75gi
zTMlK0$A=H4Mh~QKqCa92jz_;d3rtFqp(o-4gCnzxrJ2}Rw@^!haWp<ahv&+aDb5_3
zE0-vq=pkms7Ves!pD#^PA#PF^_wjBTO=oC(ayR{asyKURiBdh3?x76Ll#Z5WXklvl
z@M5XFK#OxUXqrdzedca+l4WK~_tG8Hv&HgsX`$Za3pnYy`CpW$@0?nsSh|}MrfK#j
z%y^t^lPNt{p5INwGcz<MWEN<wv`{J^Eluv$Rb2&6%ZgV5Bp(6~Lz2Eoz~@C!!B)bs
z1x-OrK~}*8L07Po(5+xZL6I<}phTEf5QRsVJYHa{f^AXPFaoSsnJ0feXUdB=CJ>Fv
zr&_=Q6YubieL}zoiJ0a+c+(bGwFN5g1pz;^rGP1sM+lHB@UAPM2&F=RB&yv@$caXF
ze~Io&3CQe=cMHr!e{yiokd?~p&F&k`jg99Ex7}WO=$8*Kx8wXv4eSa_CJqKVkyRr&
zCdcqs*@M5!gD84e@fW{|5B#mDGTH;JFw`h^stQcTjf@V3pNe8&f$=NG?-+klRGea*
zX1vOHi}4@EM~qJyfuM>e#%9J&Mjzt`j5OnB#;uGZ<1WTMj3vgSj3*esXZY{I`KqUa
zfbB~~a>piTMAVDNyHR<{<v-=}gXhE(15|emxueb8Kv%5>0{F7}8pool{7_h6u?7yg
zlyNm>-Eq_&WjW{0$9ZHq6x?~W8l2#1g0CyrtN#R-nbWG(?>iNG1zRiZgj;Lm_%rVe
zwZ6i{g#sR5xudpbj~5H9TNIQ3gMikIG@l(Z4IR@^2|Vu|LZteLF5@$KH5`Pr&3_vn
z^!Fn27&z6hSPR+*;D*&lm-)OE=ZgjK*(X&XdBq7RDUd7>|Lou?UMNg6lVCB;TPz{Z
zN4-~p*Rr=uq8OYdlAy38{}dt5%2}aUax{}zWzDRgmsn2|!)=Bp)U35;Ld3H+Ye=*_
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eZvUbDHC^NLu5~gtzg|!EqSkX2ep9pg!tpEeo1jDh
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c
new file mode 100644
index 0000000000..ff83db095b
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c
new file mode 100644
index 0000000000..777570765a
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c
new file mode 100644
index 0000000000..3ebccff81d
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x10280535, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280535),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb
new file mode 100644
index 0000000000..8b9c82fba4
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb
@@ -0,0 +1,37 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1028 0x0535 inherit
+
+ device ref igd on
+ register "gpu_cpu_backlight" = "0x00000251"
+ register "gpu_pch_backlight" = "0x13121312"
+ end
+
+ chip southbridge/intel/bd82x6x
+ register "usb_port_config" = "{
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 0, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 2, 6 },
+ }"
+
+ device ref xhci on
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ end
+ end
+ end
+end
--
2.39.5
@@ -1,7 +1,7 @@
From a15b59616e00c43c05d7853080859d4aefe26c5d Mon Sep 17 00:00:00 2001
From f692cd96a4484b8e60bd112454d1bdbc3c689017 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 11:41:41 +0000
Subject: [PATCH 19/51] dell/e6430: use ME Soft Temporary Disable
Subject: [PATCH 09/48] dell/e6430: use ME Soft Temporary Disable
i overlooked this. it's set on other boards.
@@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644
-me_state=Normal
+me_state=Disabled
--
2.39.5
2.47.3
@@ -1,430 +0,0 @@
From 423e2e28618b08a4107aea0a2fbc1096f5a8be02 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 31 Jan 2024 22:57:07 -0700
Subject: [PATCH 09/51] mb/dell: Add Latitude E5530 (Ivy Bridge)
Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A21 of the vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/Kconfig | 7 +
.../dell/snb_ivb_latitude/Kconfig.name | 3 +
.../snb_ivb_latitude/variants/e5530/data.vbt | Bin 0 -> 6144 bytes
.../variants/e5530/early_init.c | 14 ++
.../snb_ivb_latitude/variants/e5530/gpio.c | 194 ++++++++++++++++++
.../variants/e5530/hda_verb.c | 32 +++
.../variants/e5530/overridetree.cb | 39 ++++
7 files changed, 289 insertions(+)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index 03377275f0..183a67bec3 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select SYSTEM_TYPE_LAPTOP
select USE_NATIVE_RAMINIT
+config BOARD_DELL_LATITUDE_E5530
+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ select BOARD_ROMSIZE_KB_12288
+ select SOUTHBRIDGE_INTEL_C216
+
config BOARD_DELL_LATITUDE_E6430
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_12288
@@ -38,6 +43,7 @@ config MAINBOARD_DIR
default "dell/snb_ivb_latitude"
config MAINBOARD_PART_NUMBER
+ default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
@@ -48,6 +54,7 @@ config USBDEBUG_HCD_INDEX
default 2
config VARIANT_DIR
+ default "e5530" if BOARD_DELL_LATITUDE_E5530
default "e6430" if BOARD_DELL_LATITUDE_E6430
default "e6530" if BOARD_DELL_LATITUDE_E6530
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
index d89185d670..c15ef4028f 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -1,5 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only
+config BOARD_DELL_LATITUDE_E5530
+ bool "Latitude E5530"
+
config BOARD_DELL_LATITUDE_E6430
bool "Latitude E6430"
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3
GIT binary patch
literal 6144
zcmeHKU2Gdg5dO}0w$JA~+qs02q)iz56C9e5vuQ#oL0l3O+%|395Q2peO{y4(2uX0t
zuMja1N)bPb1cE+5)fYsCK!89MFQAGChyWpk5PuR<K|G+sLmxmOR4}u5=Rg`mj70g7
zvgdDic6N4dW^QKhynd)>kS^cR)3#-(r*-?zo-O^C(kLvv8XM<+Y3tdt^YY!P?!oTe
zJ^ed-x6w0Lh5fN#jsv5TWE#mtd*_yky}9xDK(kOwLt+C7_AQAd#iwr=o0`gvQZ`{x
z6ZeT`x^^;8+a~jSa^o~PF@8J6N5;o#dhCwebaM;!_oisw1#O9K={qQM<@Oeu$lXeN
z#wJGcW4Y<2)-A{Bot(NoKX%>qdnw-AOi9bKT9Z~HL5|7PJDHz4kGlEx143q+26EH6
z{4KfB^9;?<fTOaiNPy%=@LovL&q<^d1Qdi+Xex9SvIM^ZLq%9cP{A1rE>#dw(WfA;
zBCR3@pCS1a;A|CZW1h7H*l#mW{%y{bf)9ofiz!EHzyiac@{RpMzz>O-<~{hx5tw%b
z3ZJWD4_g-`iF`tUJb}+Vfe;XI1T2Y4_Y!iVk<<T4ce(^PWKh<?N^a`t+}vgNr25iZ
z`!fTBL)ojYF5G?3y|eW=`9>MLB9et&!A7LDDE7&5ye#|hn%s#IWgagDEPNHHMUhb-
ztc9t?uz{bD#kh#kpsE;AO-wWHV?4olPStRPag^~k<737bjBgm<GlC%vRgBe)4U9I%
zg^XUtcE**A5ylOSn;A2V2N;hso?--U#>t|ufS}_`LGs2bcSKCVBh4s0>G7ZR_@NWx
zkph}GhP}~YR?roT!61GqzQ?gBsuv3jY}UXbmr|alv^VxUqbz5<`5=!hhpaa*7DK~4
zP4ad6dhH!>nYpc4{J&G-w{UiWo$zXnTz{tAq0|?c_`QJ7pKmCwIpe7Uix$P?9}v*1
z(aVR6OkMkQ6oM}*UC@j78!~>7=OZCVYXeu|u0SiI4}w$uw6&0P09LF%Hp}O&IA3gl
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z`yI_BR#`La=Oxxt#qgS`3pER^nh^CZ%*qlq2N9@uSAtz-C7AhduB_U|{>#oOrY`tq
z%|?L!zRd2-$V6^@$H<Mj3MXf#F<J+^8%<X2{tnmQTI*aK*ageBrm9^|<Ked3j_s;%
zva<(Dob)BOwdcj8Z67UhYUAjbk==Of9W#D7k!DJobLx$$fXD_wuZyD&Kk-$EIY~S`
zan1ANbFUW8hZ0pUw5)y??*}!;chdgq|0X5;s;m`@YdY{zs4z#z8e;13T6b4tC7gy$
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zB3a%B!?6K=TJ$W+SJv@*9Lms{mTvWmU4Zanj_Z*lSqOGISzYp?yawOqLhVhRt#-E6
zd)YW~h&meh-5prIE}Cr&7f?MMi&cqTt_^%Fa?>k(=`9jVoIf@}{g+WX#TpWuc+!2v
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z9rOI3;Mt}9)_G{zXTAPw`8T@6=Ut0r9R5;0#Zy|#8F;v4^UAmqft3iXL|`QXD-l?U
Jz~2*rUjdP?m;3+#
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c
new file mode 100644
index 0000000000..ff83db095b
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c
new file mode 100644
index 0000000000..0599f13921
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c
new file mode 100644
index 0000000000..3e89a6d75f
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x1028053d, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x1028053d),
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb
new file mode 100644
index 0000000000..85c448d010
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb
@@ -0,0 +1,39 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1028 0x053d inherit
+
+ device ref igd on
+ register "gpu_cpu_backlight" = "0x00000000"
+ register "gpu_pch_backlight" = "0x03d003d0"
+ end
+
+ chip southbridge/intel/bd82x6x
+ register "usb_port_config" = "{
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 0, 3 },
+ { 1, 2, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 0, 6 },
+ { 1, 1, 6 },
+ }"
+
+ device ref xhci on
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ end
+ device ref gbe off end
+ device ref pcie_rp7 on end # BCM5761 Ethernet
+ end
+ end
+end
--
2.39.5
@@ -1,435 +0,0 @@
From 200668a694f1c534a94a0bc8996416e246fe91b0 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 26 Nov 2023 17:08:52 -0700
Subject: [PATCH 10/51] mb/dell: Add Latitude E6420 (Sandy Bridge)
Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was
not tested. I do not physically have this system; someone with physical
access to one sent me the output of autoport which I then modified to
produce this port. I was also sent the VBT binary, which was obtained
from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the
vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/Kconfig | 13 +-
.../dell/snb_ivb_latitude/Kconfig.name | 3 +
.../snb_ivb_latitude/variants/e6420/data.vbt | Bin 0 -> 6144 bytes
.../variants/e6420/early_init.c | 14 ++
.../snb_ivb_latitude/variants/e6420/gpio.c | 191 ++++++++++++++++++
.../variants/e6420/hda_verb.c | 32 +++
.../variants/e6420/overridetree.cb | 35 ++++
7 files changed, 287 insertions(+), 1 deletion(-)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index 183a67bec3..d2786970ee 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -17,6 +17,12 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select SYSTEM_TYPE_LAPTOP
select USE_NATIVE_RAMINIT
+config BOARD_DELL_LATITUDE_E6420
+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ select BOARD_ROMSIZE_KB_10240
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select SOUTHBRIDGE_INTEL_BD82X6X
+
config BOARD_DELL_LATITUDE_E5530
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_12288
@@ -43,6 +49,7 @@ config MAINBOARD_DIR
default "dell/snb_ivb_latitude"
config MAINBOARD_PART_NUMBER
+ default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
@@ -54,11 +61,15 @@ config USBDEBUG_HCD_INDEX
default 2
config VARIANT_DIR
+ default "e6420" if BOARD_DELL_LATITUDE_E6420
default "e5530" if BOARD_DELL_LATITUDE_E5530
default "e6430" if BOARD_DELL_LATITUDE_E6430
default "e6530" if BOARD_DELL_LATITUDE_E6530
config VGA_BIOS_ID
- default "8086,0166"
+ default "8086,0166" if BOARD_DELL_LATITUDE_E5530
+ default "8086,0126" if BOARD_DELL_LATITUDE_E6420
+ default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
+ || BOARD_DELL_LATITUDE_E6530
endif
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
index c15ef4028f..257d428a70 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -1,5 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only
+config BOARD_DELL_LATITUDE_E6420
+ bool "Latitude E6420"
+
config BOARD_DELL_LATITUDE_E5530
bool "Latitude E5530"
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd
GIT binary patch
literal 6144
zcmeHKeQZ-z6hE);wSBvNZ|mO1=*HLC2BQN8uVX6{N9eY)75ORymb$R8!YYuAZEgeE
zKk|S@Fen*n41W-viAF;r%)~^EkpLz-B{2q##)LmGAtoY;7*Qhv_1yPbw$TC$2}G0K
z=6Ao&x#ym9?z!i_&TOh(kLzky2cN8MTpny#R<;VU4Rkn?rBIz(YL~BBw<%b&zGhSH
z$~AQ>@D0d=Xx6RE0BwSxspWdrW9y<FZGD@&x3_JL;p$p!;!BVdcKLkht0=-%(Jj&T
z_GkyztZ%>#t7^)^(T-R<7W?O6ZTI%A+j=`<Jw3Q%dk6N!da<_?7oyiU3)^<~_TiSk
zE$y+=RK3PGQ`gzmXYPRBx>C|f*UP9{h|4>ANrAe~?ymV*)83AaT#FuTjP=C2cg5P~
zt4w78r$t#300cWY_k)mevmAmFI3&oBfytoAAPQiYK$XEIgHwV@5-gJ-Q-*p8yfTDj
zaDz=1Y!X1B3`OpQ&Ik}bM|0xHn0gYNZw0rT=7AXS2in-q8K^?)0|el+Z6geW7i7MM
zv~!|>HqL-|Fk}EYOa@)R<X)VQ7c}d8R1b@RTn5rq(90|QRg0?wwZZz(6Dz}w>zg9Y
z8;!mD_V*XSjT33~$`o`s>zEGBq8AQ`HaH?y!Fh2QiX1v@aCo4LaENf&DZ_cE2A2qb
z5@cC}X)=S^1RvpXLWs~v*hqMau$!=t@B-mg!XV)|;eEm>!Z6`H;R4|&!d1d`f|S7^
zli+B98*!TfPE&6~NVM5j3v{N3OTjpnm_L@BPh(}esd(J!gj?~iJP?n|OZZOiTqlql
zg<NWR@g&-*W-E%A7|*1Z_`sVO$K&iAP+VIj9{<1hT%SXsK}IBk8!daftR`6-)EUiS
zvv*HR(#-ZwhA~7wcmxbe4%E?Y7P0y{1q|nqR1L29UR8v@#No^g5MH)7!>{%-$T|cR
zZx5|xm>Fl>;@$m};P{0WC>O~<Nl1`*PLgPN_hP2a^h+L$ls&SYrkDYr+&l*%%S?^Q
ziPSdtHE<LNEnr7cs=ihL-C>-p>*$9CpHRLgN|POkqD^UP4nw|4nf0bc8MOBk<;%js
zfpCAWNzqSPlz@X%j9CGrwZDKUl@K{g6pzqiIIARDQ)#@^RW&0pmNG;XZ?!SlHB?L#
zKRAMgq(R;aQd%@Gy38-LS@ix)fR**(P3B9wI=Uk^&cWmmwB<vf21<0#LBA!;qtAh(
zYe5g_T{+gw^mi8QzPPraBoH~8oCz%r=$nVi1A)`Y8IKqIdqm6MihqxtpFaTggaPxu
zQP07nf#&kPkPp}Cmk$F1g7q7QK;kz~80i&oDN}~wYbPUI6AtG5H+$T!@f5FzUhp21
z^XiPT3rb%B@sA9g!n88R7BOsLS|?+D3}0v3dyIX|@JFWo&e%<c#V)PV#g@7-=F*;V
zvAr&Q+ogTvVxPM3XP5Smi`f;Nt7uCU)}Y`HMcbpW=M_AuXlE35PQl+4O{7m66&I@7
zGL@}Sai^*sP}va`KTx$VRQ8REf2*1+lTFH0=UkNx+eN|1rVyipl)Du=h=@%w+iQZG
zT6@-PdW^oyFb44AG`HMZWEnP{&OQ+jC`N4emoS)x;EPN}uaSFOf-Mn8JRRO&LTWJc
zn6%=L94~PR)%Ua_HTZcfTXD<p{%8p|<N<;Efw$Zb4$}{m8@7c((~<7^thaau&@Wx#
zVGNL)lmH@{o=h*{muXGc!;nXrVgpp3;1V1stMj=4AtxyzX+?SoB~zN}!*r?9Qvs1P
zmV_(CTmt0sY&6=F=_M>E34GYvuh1uQF+BUdWyQC5SaEM1QvKlHBMs13C}n{0SwRxW
ziekMa&kvRFruRcKCevGy5)TxUBDlur@E{TtQ^NQ>nO+Cgl)&Ga(PxqVW?e3TLH-UY
zdL3T{z^xdd`$(STFUb8R*cKa}r>n{Wk+MXRH~o-hN}#9OF*>T#>rfhiRs(Wc-R^9@
z%F=<}dn(E}ADc03zJ>JvZe;_8f+WFLL4%qNYs`_aa`a$Pl5H;iO^Wt*cP3W(d=(g}
zZ%nKT1$|r-tAv8($u2-BI2Uiz#%OT&!Q3b~Ru2P2j;Gem!@wfPsTR%J>W{8z)oq^J
k^Qm&?O@bFkw4CTocwoW<6CRlGz=Q`TJTT#bN9KWl0rH4|j{pDw
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
new file mode 100644
index 0000000000..ff83db095b
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
new file mode 100644
index 0000000000..943c743f48
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
new file mode 100644
index 0000000000..ede8445aaf
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x10280493, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280493),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
new file mode 100644
index 0000000000..3012a3177f
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
@@ -0,0 +1,35 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1028 0x0493 inherit
+
+ device ref igd on
+ register "gpu_cpu_backlight" = "0x0000054f"
+ register "gpu_pch_backlight" = "0x13121312"
+ end
+
+ chip southbridge/intel/bd82x6x
+ register "usb_port_config" = "{
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 0, 6 },
+ { 1, 0, 7 },
+ }"
+
+ device ref sata1 on
+ register "sata_port_map" = "0x3b"
+ end
+ end
+ end
+end
--
2.39.5
@@ -1,7 +1,7 @@
From 440ebbe1e10911dc3d8c53cf9eecb5519c2ecd67 Mon Sep 17 00:00:00 2001
From 78db6c595ff816ad4344d541688605ae720a83c4 Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Sat, 23 Dec 2023 19:02:10 +0200
Subject: [PATCH 20/51] mb/hp: Add Compaq Elite 8300 CMT port
Subject: [PATCH 10/48] mb/hp: Add Compaq Elite 8300 CMT port
Based on autoport and Z220 SuperIO code.
@@ -868,5 +868,5 @@ index 0000000000..8dbd95ef96
+ .enable_dev = mainboard_enable,
+};
--
2.39.5
2.47.3
@@ -1,449 +0,0 @@
From 53abe363f2fa038080a976f2d3a2c63ee8da9022 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 31 Jan 2024 22:07:25 -0700
Subject: [PATCH 11/51] mb/dell: Add Latitude E6520 (Sandy Bridge)
Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was
not tested. I do not physically have this system; someone with physical
access to one sent me the output of autoport which I then modified to
produce this port. I was also sent the VBT binary, which was obtained
from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the
vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/Kconfig | 9 +
.../dell/snb_ivb_latitude/Kconfig.name | 3 +
.../snb_ivb_latitude/variants/e6520/data.vbt | Bin 0 -> 6144 bytes
.../variants/e6520/early_init.c | 31 +++
.../snb_ivb_latitude/variants/e6520/gpio.c | 190 ++++++++++++++++++
.../variants/e6520/hda_verb.c | 32 +++
.../variants/e6520/overridetree.cb | 35 ++++
7 files changed, 300 insertions(+)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index d2786970ee..72bdc96c0a 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -23,6 +23,12 @@ config BOARD_DELL_LATITUDE_E6420
select MAINBOARD_USES_IFD_GBE_REGION
select SOUTHBRIDGE_INTEL_BD82X6X
+config BOARD_DELL_LATITUDE_E6520
+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ select BOARD_ROMSIZE_KB_10240
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select SOUTHBRIDGE_INTEL_BD82X6X
+
config BOARD_DELL_LATITUDE_E5530
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_12288
@@ -50,6 +56,7 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
+ default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
@@ -62,11 +69,13 @@ config USBDEBUG_HCD_INDEX
config VARIANT_DIR
default "e6420" if BOARD_DELL_LATITUDE_E6420
+ default "e6520" if BOARD_DELL_LATITUDE_E6520
default "e5530" if BOARD_DELL_LATITUDE_E5530
default "e6430" if BOARD_DELL_LATITUDE_E6430
default "e6530" if BOARD_DELL_LATITUDE_E6530
config VGA_BIOS_ID
+ default "8086,0116" if BOARD_DELL_LATITUDE_E6520
default "8086,0166" if BOARD_DELL_LATITUDE_E5530
default "8086,0126" if BOARD_DELL_LATITUDE_E6420
default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
index 257d428a70..c7665ac263 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -3,6 +3,9 @@
config BOARD_DELL_LATITUDE_E6420
bool "Latitude E6420"
+config BOARD_DELL_LATITUDE_E6520
+ bool "Latitude E6520"
+
config BOARD_DELL_LATITUDE_E5530
bool "Latitude E5530"
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
GIT binary patch
literal 6144
zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN)
z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y
z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+
z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7
zcXx+--0R}IwzW3-+`f2k?^Av5V7MpRO-q(9rn_R1@Xlz2Ztdy`$Gf6^w6~|bKi!!7
z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ
z)4V8f0Gt`D`+>9Fr~tnJ76EJ`5D_F1cn-`0$RgN9unI6kfYkzIiO?W`ON4+34lv1_
zNdPDkq1cf$p8^EW;TS*O$CdzNo#1fbIG_Oi0T(ti0jwyt0le_p_HlvX^CFvr)>$b>
zO-z8^CSU`w=mIK7Q)@9fR;XUzrFu{T=rRyygIZBpU9+Or>+?4R9%~G?Y-|g)Z`Sti
z+do(U*Wb-xR~DzjS<75#=Us4sH^C9U2FCbND7L7u$>M|<;t=AnRfI9C0v8c~AVg7t
zIU<3D2oK^>L;%r(*o=4*u?Mja@dDyi#4zFn;(f#^#3*76aUSs#;tJv#La-6YLRdQB
zdcvfERkvH?k~GJlfM<HR476j(@nfm+47<!Ult@^ua5M3h6A}q=C0ognX9aX4mxq)U
zXOhm=DbLene?C%_16Q)2NRV@Yacz`D;{V>Ve-1?&ZXy}n)YwnVAgNlz#zX;=IX)-F
z)9LL3lbEdY5Co)LsK?vP)7s}G(5xduE!Y!#Wgh<IN3(3ey=-oWU(9aEJ_HzV53Jbq
zj5B5RjzLUt>_T&xi$uUA#0e}X3D~`J(bHz;DgTa@GrpW6=>eZwJeNYYo*GjF=``;(
zuoQ3|V5YoKd$j=KK{`uSX*DeU1oJg=+RT6)rLe6%2>Ci^!5ao=*gS}wFN=nUf`fTF
zM?Gb5ycWjM7I?MJ!2;w|LFg=UoLq-ytr2iemG)AsW}bI4X9PK}T5UKsQi7anu=tD6
zf|={kXkNeQBD>6bQ3taC8XJOJ^e40_ydyfr&a41L^1)jNrK<B_wV}+ZE`p;QK=rDz
zTw`SJ+e`Oc*icaF4INF51Xg*~ts@m)@9ETt(*@N7yy0)Ddce%i9{^k2kbd8=Wns~P
zWBD$~himxDharxF@f!ti^0$~9Zxt{tg`@Dbl_0Ki2Xp_MEw-<z6qgep;XYmR%Dl-F
z%3cBfcN;Avikpz-gmw_6mymu!Unk0YgnUfsk3{*6kQ;=S*p(_fS!JhDyYh^k?6uRk
z?8--W@~NHvY*+ra6SG9iC1s^V)<|@Rqzp*pd5NBslrs`JC(&Oeg~v}CnJ$x+)iP<8
z=`LA0Ad@39{XkZ}kjXbP{YzHtS!70*yy%LcnJ#cz4u%*Wq!^d*AVMZdr&l=#Qgik~
ze2l)cX+!kF9EaFhY;0^Uo_#VNC?7K2Tf=ZR1y5);b!mCGG?<cc#M0rtHKYeKi%BE?
z@Y6|P8fx#li}c`Uv24UGyZaM0To;Ep<_AWZA1t~bFgI)uf}&Eq=L_Cs89=>wnT0Vx
z-jp>o1ffJNommZ4?=TIPlePIw0hgQ706f*tBC`#pg>9&zRHe>J2%RxBTrOc6Adh9E
ziJr`?VQH!N!_GkoKaoq|+3$^Ae0#sUxXlmM1Huq~g<=Ls?ILv+nQcH%PQedGOlH=Q
z77rMcJlH4Mkc#U2(IDv>rsm1aHpsdL_RdT^i_ACcQUMIJcSus}*(?CIiy^#^=t=g1
z+*^Zbh30&^#_bKclSy9pL$<B~pK8m*sLpIdnHM@W$nA7Ea@Z`x27K?aNK<@lCW(2L
zb@kB3H8kKy4W3Hu)NN|kd!DL^o#iR9a{QYV-Wl&r&hmIFX{ezkIV<4zFiVUQ@K>ao
z00DnFy~Uek!JRwhVX!of0)$Sa*X^S~LMQH0<E(UUx}L=|;Kgw(r(4q=nD)T52c|tR
O?SW|zOncy=dEg(6JAK&z
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
new file mode 100644
index 0000000000..b6415a428b
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 0, 6 },
+ { 1, 0, 7 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
new file mode 100644
index 0000000000..61f01816c4
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
new file mode 100644
index 0000000000..ae376691e7
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x10280494, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280494),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
new file mode 100644
index 0000000000..f90f2dee1f
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
@@ -0,0 +1,35 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1028 0x0494 inherit
+
+ device ref igd on
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_pch_backlight" = "0x13121312"
+ end
+
+ chip southbridge/intel/bd82x6x
+ register "usb_port_config" = "{
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 0, 6 },
+ { 1, 0, 7 },
+ }"
+
+ device ref sata1 on
+ register "sata_port_map" = "0x3b"
+ end
+ end
+ end
+end
--
2.39.5
@@ -1,7 +1,7 @@
From 4c7577314f19e934d690c4cce3642fe693400c07 Mon Sep 17 00:00:00 2001
From beb9b1650fb3aec96544b683fbe53ee16584f3d8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 2 Mar 2024 22:51:09 +0000
Subject: [PATCH 21/51] nb/intel/haswell: make IOMMU a runtime option
Subject: [PATCH 11/48] nb/intel/haswell: make IOMMU a runtime option
When I tested graphics cards on a coreboot port for Dell
OptiPlex 9020 SFF, I could not use a graphics card unless
@@ -288,5 +288,5 @@ index e47deb5da6..1a7e0b1076 100644
if (capid0_a & VTD_DISABLE)
return;
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From b5695d0f0dc44ed1eb1feac008e601040feda55d Mon Sep 17 00:00:00 2001
From 0f76a919522c9624c2b5df2a9c17525ab21bd6b9 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 2 Mar 2024 23:00:09 +0000
Subject: [PATCH 22/51] dell/optiplex_9020: Disable IOMMU by default
Subject: [PATCH 12/48] dell/optiplex_9020: Disable IOMMU by default
Needed to make graphics cards work. Turning it on is
recommended if only using iGPU, otherwise leave it off
@@ -25,5 +25,5 @@ index 8000eea8c0..0700f971ee 100644
-iommu=Enable
+iommu=Disable
--
2.39.5
2.47.3
@@ -1,442 +0,0 @@
From 3f8eade6150f582129332f6347e9a685f8a7b500 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 7 Feb 2024 10:23:38 -0700
Subject: [PATCH 12/51] mb/dell: Add Latitude E5520 (Sandy Bridge)
Mainboard is Krug 15". I do not physically have this system; someone
with physical access to one sent me the output of autoport which I then
modified to produce this port. I was also sent the VBT binary, which was
obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
A14 of the vendor firmware.
This was originally tested and found to be working as a standalone
board port in Libreboot, but this variant based port in upstream
coreboot has not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/Kconfig | 10 +-
.../dell/snb_ivb_latitude/Kconfig.name | 3 +
.../snb_ivb_latitude/variants/e5520/data.vbt | Bin 0 -> 6144 bytes
.../variants/e5520/early_init.c | 14 ++
.../snb_ivb_latitude/variants/e5520/gpio.c | 195 ++++++++++++++++++
.../variants/e5520/hda_verb.c | 32 +++
.../variants/e5520/overridetree.cb | 39 ++++
7 files changed, 292 insertions(+), 1 deletion(-)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index 72bdc96c0a..4e94a7ef80 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select SYSTEM_TYPE_LAPTOP
select USE_NATIVE_RAMINIT
+config BOARD_DELL_LATITUDE_E5520
+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ select BOARD_ROMSIZE_KB_6144
+ select SOUTHBRIDGE_INTEL_BD82X6X
+
config BOARD_DELL_LATITUDE_E6420
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_10240
@@ -55,6 +60,7 @@ config MAINBOARD_DIR
default "dell/snb_ivb_latitude"
config MAINBOARD_PART_NUMBER
+ default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
@@ -68,6 +74,7 @@ config USBDEBUG_HCD_INDEX
default 2
config VARIANT_DIR
+ default "e5520" if BOARD_DELL_LATITUDE_E5520
default "e6420" if BOARD_DELL_LATITUDE_E6420
default "e6520" if BOARD_DELL_LATITUDE_E6520
default "e5530" if BOARD_DELL_LATITUDE_E5530
@@ -77,7 +84,8 @@ config VARIANT_DIR
config VGA_BIOS_ID
default "8086,0116" if BOARD_DELL_LATITUDE_E6520
default "8086,0166" if BOARD_DELL_LATITUDE_E5530
- default "8086,0126" if BOARD_DELL_LATITUDE_E6420
+ default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
+ || BOARD_DELL_LATITUDE_E5520
default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
|| BOARD_DELL_LATITUDE_E6530
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
index c7665ac263..7976691f21 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -1,5 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only
+config BOARD_DELL_LATITUDE_E5520
+ bool "Latitude E5520"
+
config BOARD_DELL_LATITUDE_E6420
bool "Latitude E6420"
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729
GIT binary patch
literal 6144
zcmeHKZ){Ul6hE);wSBvNZ|mL$bmQOM2BTvXUI!}^N9ejTij1vnu+)Wx6<c9(Y_%K6
zzOV-@f<ehpWB5RHBpMBgG7}RuMuM2=l*E{6G$wq&gqTQ3#E2RZsOP@dvW*rP7>Fjj
z&F`Lj?>YC}bI(2Z+}C+6zKyiGrosQXuW7A+&1%<rN+Y1ck(}dLrx)Ma#^x>lnvFGE
zeD#gB>*#Tq4&j^|7Xcz1r^pp*)g#T}u1Me3ct>Pgls5Qi3!6e2W0%`a-Ic|3efWuR
zXJ@#}wJyGMTXTcY<%@TBKh@(3hP$Gjv}E}rx-%9D_eLXhYe!c&-VyDg-Cdo1>Biji
zNNsnlFW#|jdoOj?mZ43m>cVO%UE9@*E7x|%V~c4`XD4l9GCi~@+7pfMibfX8L?!^I
zc~Rg1I5SxH1DAEZ0{jA41jrJBh#-l;b6^%g7QrThRe)&%tQH_!ggOD7A_PRRgGuI0
z0zi=n#rCB66d-sO$M~^6wgeb$2fH1|0R`v}xUiWCU`4SF;Dyh&j|mK&6WJWJ&Pq9I
zVgmFQfh+)vE}(KWwHA|Oh3fSkss|;2E(2i}s1?gRRV%8!K7U={vHD=s#+Fd)W^M1j
z{R4$??VSvEWpgT=vCM&1-U$bI6CB~IV3Z$$Vv7o!EDnev4j~R(MHsazZ~^fLLKGF4
zEfQFOa3dZ?1Q1P#&4?!vyAk^k&m&$z3?WV+-b0*1j37o4=MX<3E+eiYge(Ht2umAW
zOPDmU>UL{flI9u|@JtVvfp#o8ek?VfVV9YP5(%pnZX~{PKq4WoWGmV8t$=Ri@{zLQ
zNYYt4<$0Ry&qIoG;7s-t333)Nu8opN{NG!)&!I@eO(cVx8vBVEBvotJ7%yNl$7iQ_
zI=xk30+V$ff`F6<wRoF(TK%j9nsr#H23umU%)_7jNOl%*FPU567qbg;4gtp711nj2
z#+kHw`v4|5cA+`UMIvAl;slnH1nl0v=xH<al>1}ljxDE1dcda^&!do|r^eJkI?aC-
zEQMSfm?<w*Unzumkj_w5>VYL6W4=aCiy4rk%xq~5LV?bi|GL2$G7li<%c7yd;6T34
zQBN5huZ3~6`ChGkpb$Bg5ITb#2iK-qs|1`=sl6Dhn(Lj&8Agt?S{sTDmmtRj7Jm_1
zFnt{w&FdFkWS3bl>OeL?eO+*i{)9G!cSI-InGt|U0eEYmRCOHm7|I;#LO8ksRIeJ#
zGe+jTwPg4C4TYuN(9zULV3k+hI$YuPo=%N8oZ#u_4S!3Xelt6N0BmuC`hCNeg+&97
z6*!>)uHvr%2004GZv?!_-y&|TRmil=9D%Q`1aXBsnD^gov3*UZI34&1_vn(B=T4kZ
z_A>ClXVIBNaS^hd&^DrU6VgZMYeadMkdFxcktn|ra-Gl;n^I{bt86rCQ=YMry*B!$
zP5ID9KDE)GZOY#^VwPyRq^y+48j0?ZlzxdkC()CV@`*&wO7vGr;qjA3rb}gIwM-gi
zx>HsT$mEDj-<OpyWb%zn|B@A3Hkp<!FT5;hrt_SZiy?*wDaIu{h>%Ir=@rh7)SR;b
zAEWQGv_X1)wq0y5Ha0c~&psIsln<Hiu3;#Lf;%*eI<@?p8cfMJV(IYi8q$NA#iS8`
z_~|4t4b^wtMSAeFST^F8-Tm<zu8D&j^8=&I4;I}Im>aeSK~X8*^Z9SE44_`P#KIUL
zf6^N2f>5HCPWM3N+f0MyWOV^kz~!-wVc4MRXOY>4Jsxd1RyBKEMzNf{RKhesKFdbq
zJ(*d<l2Y#n?E?~iBA39P?~Pr2d#}5=#Sfl-VGzGUF$4U2KcqCIVlwkC(&7PQk_X!a
z8}3Jgq-&U*Co|h1>l)ZQGyW_x->i#;FvQ*=Nv&nG0N5@D@jjv_Q}K}6MP?1A6`JGe
zDwj9pN+x;T4>`I9e5x(uqdK#OGB31ikk@Xv=dxLb4fx(;ktX@rOb~M~?dYQQYiPia
z8r;jUQ?sd2@3||-cb2Eb%JFYfxHsONoaJ^eqoKN{<g9?-%`7oWz+aJS0tEc!^d@hD
z1-I{%hr!Y?0uVZpUbl__37xn@jkD6Z>3SATgBQlEoN7&ZV9Eni9+>jLln16fFy(=V
H=7E0zE^L4Z
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c
new file mode 100644
index 0000000000..ff83db095b
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c
new file mode 100644
index 0000000000..f76b93d9f0
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_NATIVE,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio46 = GPIO_LEVEL_HIGH,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_NATIVE,
+ .gpio69 = GPIO_MODE_NATIVE,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c
new file mode 100644
index 0000000000..1373975352
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x1028049a, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x1028049a),
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb
new file mode 100644
index 0000000000..479d1b696e
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb
@@ -0,0 +1,39 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1028 0x049a inherit
+
+ device ref igd on
+ register "gpu_cpu_backlight" = "0x00000218"
+ register "gpu_pch_backlight" = "0x13121312"
+ end
+
+ chip southbridge/intel/bd82x6x
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
+ register "usb_port_config" = "{
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 1, 6 },
+ { 1, 1, 7 },
+ }"
+
+ device ref gbe off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet
+ device ref sata1 on
+ register "sata_port_map" = "0x3b"
+ end
+ end
+ end
+end
--
2.39.5
@@ -1,442 +0,0 @@
From bbcd6a7f09ee99f3b26b0931f1dcd70970242ee8 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 4 Mar 2024 18:05:43 -0700
Subject: [PATCH 13/51] mb/dell: Add Latitude E5420 (Sandy Bridge)
Mainboard is Krug 14". I do not physically have this system; someone
with physical access to one sent me the output of autoport which I then
modified to produce this port. I was also sent the VBT binary, which was
obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
A02 of the vendor firmware.
This was originally tested and found to be working as a standalone board
port in Libreboot, but this variant based port in upstream coreboot has
not been tested.
This can be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I0283653156083768e1fd451bcf539b4e028589f4
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/Kconfig | 10 +-
.../dell/snb_ivb_latitude/Kconfig.name | 3 +
.../snb_ivb_latitude/variants/e5420/data.vbt | Bin 0 -> 6144 bytes
.../variants/e5420/early_init.c | 14 ++
.../snb_ivb_latitude/variants/e5420/gpio.c | 195 ++++++++++++++++++
.../variants/e5420/hda_verb.c | 32 +++
.../variants/e5420/overridetree.cb | 39 ++++
7 files changed, 292 insertions(+), 1 deletion(-)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index 4e94a7ef80..e6a21ffb99 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select SYSTEM_TYPE_LAPTOP
select USE_NATIVE_RAMINIT
+config BOARD_DELL_LATITUDE_E5420
+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ select BOARD_ROMSIZE_KB_6144
+ select SOUTHBRIDGE_INTEL_BD82X6X
+
config BOARD_DELL_LATITUDE_E5520
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_6144
@@ -60,6 +65,7 @@ config MAINBOARD_DIR
default "dell/snb_ivb_latitude"
config MAINBOARD_PART_NUMBER
+ default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
@@ -74,6 +80,7 @@ config USBDEBUG_HCD_INDEX
default 2
config VARIANT_DIR
+ default "e5420" if BOARD_DELL_LATITUDE_E5420
default "e5520" if BOARD_DELL_LATITUDE_E5520
default "e6420" if BOARD_DELL_LATITUDE_E6420
default "e6520" if BOARD_DELL_LATITUDE_E6520
@@ -82,7 +89,8 @@ config VARIANT_DIR
default "e6530" if BOARD_DELL_LATITUDE_E6530
config VGA_BIOS_ID
- default "8086,0116" if BOARD_DELL_LATITUDE_E6520
+ default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \
+ || BOARD_DELL_LATITUDE_E5420
default "8086,0166" if BOARD_DELL_LATITUDE_E5530
default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
|| BOARD_DELL_LATITUDE_E5520
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
index 7976691f21..a3fa2b1837 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -1,5 +1,8 @@
## SPDX-License-Identifier: GPL-2.0-only
+config BOARD_DELL_LATITUDE_E5420
+ bool "Latitude E5420"
+
config BOARD_DELL_LATITUDE_E5520
bool "Latitude E5520"
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57
GIT binary patch
literal 6144
zcmeHKeQZ-z6hE);wSBvNZ!2$ObQ^;MgV6zl*Rhp}BXnCCMZU^_r7jRwT!kfLo8?3H
zk9)u(7?cb(hChhTM57@QFfmbMB!G!dNsO6BW5OSp5EGF^jHnTTdhUBI+h`e+1ft1q
z^SfW?+;h)4_uO+|XEfEV$91)<gOArWE)OnSTD}Ug6?8a~vz+SmQn!4~y3N7b^|hPp
zR<5aEfv-b8M00Lk251!oO|8(YA6XaeXzkt-Z)@Ee!_{@z#Fro^?DqN4SGjRIu8KYp
zZEufuU@5MM@7jv%h;75FS}ezKv?JDzCH}d%tE)A-GuDb*+B%}~w%88r>}c;!*XQ5O
z)OU7u$J@4U+lk)#GSW%c%c)v`%R6?`w)LIyu6bD7-j0o&X9qUMcEsYlW3BU4rZRvt
zqAUpjf*qXuLCCsU0YM2I5@gB1WKd)f1+Yt?%HWd0DZxYumP(K<LxTif8A39+!KMl}
z31FHG)7?qk5g>e?=ER{f^&}W<0k@mxff(?6+Stw+s6y%k1mM$cLk#^FWWI*9bE1GY
z&VY9?WC1u#23^3^UYw5?H0x2S2gN`x18Fko6_x(#MKyuCU_<D!mEp$qO_An}#@>DV
zdkf*li41yW3p$*0Oo3+63kO6S91*KwP#l2i4jnc)JkUirL^$k}VbH0;CBh#BS=OLf
zW-yE3BRon75gG{_2~QIC5cUzCC%i)FCmbidM>tIwAPf>N5Pl?FC0r*+Sq!oXj!keQ
zVKcyK>TL+gc7oLco$28+FpeeXkEP}_Sea=mk#IWUR^m$!BogvszLPu83FJm0k6K<l
z$#$~YiXtY*GpHp#@FvHJ1UnBD*H%d+{_j24XE4nmBa*?5mOWiold28s3}>*}<HaeO
z+1|-8g2)FCfkDZIdb-Ub);z0#;XEbPfGe?A72!{DAUg|$m+Z~(i@h9j4gtm611ni(
z#u>ACcP}M4exU`*MKVwl5+t6JBpTkmm}xWflKUe~7}`!#%z#gAo{NxUrpDAndYktu
zI0}VLU`J7^xmF1AFiz5S^uzp*DPI$%$qq!(ikh0kP+(GKzF|@N?Y%_#Vp@M+xHr$F
z=%+18z`-fT%z)9-TS$~Dh@2yeN7!UIt0h`fWxUu`JvA_ra*8P48l%7KR0&c1;0R75
z4f0oz(xQ3MWqz5>qW5M4tZWExHs8<H(e1G@4km@5wEzOOP^x<l`YmA|eKs6j3wl8B
z%C%;uygh%<#kGZ{fymL+OlV0!-*T!V5IB>X@p!@CBU=7e{5^Jl{s7by`po-AJqM2l
znk(=^0bHkF0rUw7)^7j;$=_UIs8`6P6b-;vPDZ#U9L)W1_PAYRDP9k~;5$stt5ZiV
zD0>;i-?OlYY2}P9WVnfGos4xee2r=EGWHR}ADH$VV>cO=xU?!4TjIi)OMBYI_PX#b
zm-eBHed5BOT-x6*W>;{IqAga~G6lCQT93k>Q}CpsomJR*1%FjEkv?fuT%c-8RklXO
zU8;6KWk*zeU)4TW+1D!mrE0EhHZfbBeN{4S7X@Pig%};A99QTdA~wZruL*8y?K!jP
zG5R*k=);S}Zn<T;W!Mxt`(!+z7_r@3LVpf|FESauM&4}+wqzXfba-zG>A}on(uzNF
zyu>BcjA})C@bg%<;+Eh2;Sz4heFFCbZ@C{FrXMIbYzu>?Bi-|vZ}JSFU%JA>7$7et
z0Yo%CnOVZm#ZA}4kWZOn15};h5*#OM3b+6vHzgruMP>=5MNJK1y42{YgveP-!j%#(
z0rGe@8t%!=66Ti%K4|Gx=o7gFp83wQ;+s3H7+r^SKlpp3KKcr!3@|n;NCH_=qL=3T
zq3WH?en`b+W-HR-fnrhw*9aZ%M}lHX7@H?E>!6wv_&YQFEHdA$%Z1R--yub>=c@p?
z6@7Fc$&>sAxwiz{BE$1kb$K9Co=ozlA973y^i(^BM|EZ$$^y`0KyHiMJ%O*XbfEX1
ziZaH>W(1pWL0bo|T!x__N$^$DpmxI=bL6WUK3JGyn?rw-qC4ZA$yGjIB}N(=ldD2O
zAJ@bxp<qR-3lIv<!P~SE8r*#_Ckl?$0|1fZ>2>n}u*mUIYFd>}O_wuwBD^r9<#=!0
X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c
new file mode 100644
index 0000000000..ff83db095b
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c
new file mode 100644
index 0000000000..f76b93d9f0
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_NATIVE,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio46 = GPIO_LEVEL_HIGH,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_NATIVE,
+ .gpio69 = GPIO_MODE_NATIVE,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c
new file mode 100644
index 0000000000..0bc6c35a63
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x1028049b, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x1028049b),
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0xd5a30130),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb
new file mode 100644
index 0000000000..3f55bfd49d
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb
@@ -0,0 +1,39 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1028 0x049b inherit
+
+ device ref igd on
+ register "gpu_cpu_backlight" = "0x00000c31"
+ register "gpu_pch_backlight" = "0x13121312"
+ end
+
+ chip southbridge/intel/bd82x6x
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
+ register "usb_port_config" = "{
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 1, 6 },
+ { 1, 1, 7 },
+ }"
+
+ device ref gbe off end
+ device ref pcie_rp4 off end
+ device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet
+ device ref sata1 on
+ register "sata_port_map" = "0x3b"
+ end
+ end
+ end
+end
--
2.39.5
@@ -1,7 +1,7 @@
From d86824305f11bc684f1e91e3826158b8c7d7e0ee Mon Sep 17 00:00:00 2001
From df64f2825157226b98e002e746114e25b0047438 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 6 Apr 2024 01:22:47 +0100
Subject: [PATCH 23/51] nb/haswell: Fully disable iGPU when dGPU is used
Subject: [PATCH 13/48] nb/haswell: Fully disable iGPU when dGPU is used
My earlier patch disabled decode *and* disabled the iGPU itself, but
a subsequent revision disabled only VGA decode. Upon revisiting, I
@@ -47,5 +47,5 @@ index f7fad3183d..1b188e92e1 100644
static struct device_operations gma_func0_ops = {
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From 2fdd5bbb2bbec76c3c2238c4cd471b9b63073942 Mon Sep 17 00:00:00 2001
From fdf4774a6e80b1f94079abb346049113dfbf5241 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 11:03:32 -0600
Subject: [PATCH 25/51] ec/dell/mec5035: Add S3 suspend SMI handler
Subject: [PATCH 14/48] ec/dell/mec5035: Add S3 suspend SMI handler
This is necessary for S3 resume to work on SNB and newer Dell Latitude
laptops. If a command isn't sent, the EC cuts power to the DIMMs,
@@ -28,10 +28,10 @@ Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/Makefile.mk | 1 +
src/ec/dell/mec5035/mec5035.c | 14 ++++++++++++++
src/ec/dell/mec5035/mec5035.c | 13 +++++++++++++
src/ec/dell/mec5035/mec5035.h | 22 ++++++++++++++++++++++
src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++
4 files changed, 54 insertions(+)
4 files changed, 53 insertions(+)
create mode 100644 src/ec/dell/mec5035/smihandler.c
diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk
@@ -46,13 +46,13 @@ index 4ebdd811f9..be557e4599 100644
endif
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index dffbb7960c..85c2ab0140 100644
index 17ac2c1dab..c5067c16f6 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
ec_command(CMD_RADIO_CTRL);
@@ -100,6 +100,19 @@ static void mec5035_power_button_route(enum ec_power_button_route target)
write_mailbox_regs(&buf, 2, 1);
ec_command(CMD_POWER_BUTTON_TO_HOST);
}
+void mec5035_change_wake(u8 source, enum ec_wake_change change)
+{
+ u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
@@ -66,15 +66,14 @@ index dffbb7960c..85c2ab0140 100644
+ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
+ ec_command(CMD_SLEEP_ENABLE);
+}
+
void mec5035_early_init(void)
{
/* If this isn't sent the EC shuts down the system after about 15
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index 32f791cb01..8d4fded28b 100644
index 5fdf56631b..5cd907bf71 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -4,12 +4,15 @@
@@ -4,6 +4,7 @@
#define _EC_DELL_MEC5035_H_
#include <stdint.h>
@@ -82,16 +81,17 @@ index 32f791cb01..8d4fded28b 100644
#define NUM_REGISTERS 32
enum mec5035_cmd {
@@ -11,6 +12,8 @@ enum mec5035_cmd {
CMD_MOUSE_TP = 0x1a,
CMD_RADIO_CTRL = 0x2b,
CMD_POWER_BUTTON_TO_HOST = 0x3e,
+ CMD_ACPI_WAKEUP_CHANGE = 0x4a,
+ CMD_SLEEP_ENABLE = 0x64,
CMD_CPU_OK = 0xc2,
};
@@ -33,9 +36,28 @@ enum ec_radio_state {
RADIO_ON
@@ -39,9 +42,28 @@ enum ec_power_button_route {
HOST
};
+#define ACPI_WAKEUP_NUM_ARGS 4
@@ -143,5 +143,5 @@ index 0000000000..958733bf97
+ }
+}
--
2.39.5
2.47.3
@@ -1,435 +0,0 @@
From cd6e699649459fa5ff2623018ccf3585eb3d3821 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 7 Feb 2024 15:23:46 -0700
Subject: [PATCH 14/51] mb/dell: Add Latitude E6320 (Sandy Bridge)
Mainboard is PAL70/LA-6611P. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A22 of the vendor firmware. This port has not been tested.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/Kconfig | 11 +-
.../dell/snb_ivb_latitude/Kconfig.name | 3 +
.../snb_ivb_latitude/variants/e6320/data.vbt | Bin 0 -> 6144 bytes
.../variants/e6320/early_init.c | 17 ++
.../snb_ivb_latitude/variants/e6320/gpio.c | 190 ++++++++++++++++++
.../variants/e6320/hda_verb.c | 32 +++
.../variants/e6320/overridetree.cb | 35 ++++
7 files changed, 287 insertions(+), 1 deletion(-)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index e6a21ffb99..84ffe1d33a 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520
select BOARD_ROMSIZE_KB_6144
select SOUTHBRIDGE_INTEL_BD82X6X
+config BOARD_DELL_LATITUDE_E6320
+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ select BOARD_ROMSIZE_KB_10240
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select SOUTHBRIDGE_INTEL_BD82X6X
+
config BOARD_DELL_LATITUDE_E6420
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_10240
@@ -67,6 +73,7 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
+ default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320
default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
@@ -82,6 +89,7 @@ config USBDEBUG_HCD_INDEX
config VARIANT_DIR
default "e5420" if BOARD_DELL_LATITUDE_E5420
default "e5520" if BOARD_DELL_LATITUDE_E5520
+ default "e6320" if BOARD_DELL_LATITUDE_E6320
default "e6420" if BOARD_DELL_LATITUDE_E6420
default "e6520" if BOARD_DELL_LATITUDE_E6520
default "e5530" if BOARD_DELL_LATITUDE_E5530
@@ -93,7 +101,8 @@ config VGA_BIOS_ID
|| BOARD_DELL_LATITUDE_E5420
default "8086,0166" if BOARD_DELL_LATITUDE_E5530
default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
- || BOARD_DELL_LATITUDE_E5520
+ || BOARD_DELL_LATITUDE_E5520 \
+ || BOARD_DELL_LATITUDE_E6320
default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
|| BOARD_DELL_LATITUDE_E6530
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
index a3fa2b1837..ef6a1329a9 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420
config BOARD_DELL_LATITUDE_E5520
bool "Latitude E5520"
+config BOARD_DELL_LATITUDE_E6320
+ bool "Latitude E6320"
+
config BOARD_DELL_LATITUDE_E6420
bool "Latitude E6420"
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..471a9e29da639dd496f3ecebd5d0754a9045c00b
GIT binary patch
literal 6144
zcmeHKeP|p-6#wn*-rZ(yH@R-odPzTgZEU>S#_pv}j2iKhT+^%8_DtJw21|4GP8*0x
zyw;EYW49Xozz<Rt@ek1mic(N32r8oZ0U9lcR8a)~s33wLV8yCftLK~DJJWb)8w-j;
z=J?H<nfK<+n>TOX?48xuwV5_`Zb)3w)w?dSc1`nTL|NF_SMw&<<)v%g#!cH2otrzi
zb*<mneJMSLdC1iK_7#v-6w7R}+t1&W8P4wBo*&F!lcNn?)F-EqWZV#oQEb%`x-4^5
zW@sogOik1`n9Wc#r82|0A!=-0LD!FFGrMwG+CDg($q(js(#Y`8?s79ubEJD@ba#I6
znjO0++P#czvh8NBR?)iQUA%txNPhHO>Kq!PUMaJadUHE-`5SWCb4_6i;5Aj(6hQGK
zcq^2uUt5sS5YSMiL+CJcs0#cVOdTN|K@D>?tkF=dqenwjM^Z-^K2z~&z+xRs!o^Jx
zkUGd?>QtXw8V(I09OiMb0DZy>`=tO^#BCssw{}bkOnj=#Ic!~!6!J*{`jbEv5O4)-
zg-UBlIa$c9Pg4C;0_-wq3t+dbZfn1wBi@zhNnWx()w{Vb-G8OC_m*478gTrX3U*a1
zHr@y<Lcbct?Wzy^)OH+FC$S`8V@n`{QN~@2dxJU-1ucBe_>rOO78dFPXES1q3mHj9
zFXKwa)r^}Mw=nKzJjj?}>}NdBc$G29IK=pr@de`u;}}D$5~yYbw&Hlf=OF0X?I=Y$
z$D`mgy>}U$hl}G6m&PmXveHnY5DenC!g~=E3i?HIrEpyk>_(-IsVtEqUEoqxrDFdq
zrYwhOv0o^NgW$OKN}=$7Z-w5*Vuv?T3~uuFGwP92?Qr8n0iQp=u*7rep9Q8dW#?ZI
zFly1ww^^l*+YC6t16l_{g}tVVpVZ0fDk%5+`|+*688vr-<Lw_SRc^+avHI{BCpdYb
z70yLEI0-45%t;z||GKzov+|VFW6hab&NAG9FD+h6sBu$cX`r0eJ%T`kvK4+(wT`0=
z$fxKG+om?Ge1-EhbNc*Xjy1opKZSaiv-EL~GvOa&&bx~z##3W;F2{b=<HQ4!<1CFk
z17i)$X+`=C=0udOPOx3$IjzopqwQzLr*jT4C)(jmj2>uYP8$M=#caX6OWA1Ez395U
z%x<yAs)6-Ascr5<x*>CIZibyRlE~I0-ianVaz~q|EMlL7hc1U5w?}Kekws6fyy@`e
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zLYyaPtFT6d*e&Q$VLd0r%Yr@=*7rjEDyT7JwT8sSA<BiU8$)7mh@K2tFNMULA^I|8
z{Sp#>gO(fCMTS^w(6xrO#}IcK^sHgMZis^heP>uIf6|z=%Cy#)Vxvjdo7U~7*k{rU
zruB{~J}~KL(+X9Kxz*-5M>NNGSaIfXi19({d4mrk?K50@R0%Wn*PP9d(MMIzI2~RX
z)(4h&8(YL@UyKJ*)4o${n5ZGd(hDf+)cv8sSBxWen|f*u<-sgt(u+U-bkd}Tj+5@9
zJosfSdvPo8zGnluemJg=E7A{=N<Rc#KYYEg?^p`+_?~aU(kEmFus{DshA~iA(onLY
zvIfpBJt;KWP4n8&`n1##c($WnDo|=?rlHBz&}36&HPWwp8op_i8c-**(TSd{Y{SZ?
z_=^K$27e+q;^vRNU3~a=cd;V{%O=iuo*&xwXyg19${Ap0yO@a|N-<e^7iIClF{vUn
z&4$y_V7MA)=E=%7n63u!J9FY$RK8hXHDE%%Lx$ZgX902-<9r|4lkx>QwFch>PUO1w
z=6JffnB-kQ)VLb>sSZdDrI@U2!?HLA9Mlek!*k>;&jx<)xfnBiY^I6DRt*l*`n8ly
zu!h)b?sRV1==Nf*Cw9&&i7n^9Nts>wk>adaY&E5OdW*A?iI}v+E6GGlsR<+#%jpl^
zGz<Q^vpj>qhDjj3zr60Bgh=l{NzJp$x#fCR%*8!ZR?fC&JuvHmSr5#5VAcb(9+>sO
IzvhA80TAzedH?_b
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
new file mode 100644
index 0000000000..b0c4638858
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
new file mode 100644
index 0000000000..61f01816c4
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
new file mode 100644
index 0000000000..2e3f7fa697
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x10280492, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280492),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
new file mode 100644
index 0000000000..3bfe6b57ed
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
@@ -0,0 +1,35 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1028 0x0492 inherit
+
+ device ref igd on
+ register "gpu_cpu_backlight" = "0x00000622"
+ register "gpu_pch_backlight" = "0x13121312"
+ end
+
+ chip southbridge/intel/bd82x6x
+ register "usb_port_config" = "{
+ { 1, 1, 0 },
+ { 1, 0, 0 },
+ { 1, 1, 1 },
+ { 1, 0, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 0, 6 },
+ { 1, 0, 7 },
+ }"
+
+ device ref sata1 on
+ register "sata_port_map" = "0x3b"
+ end
+ end
+ end
+end
--
2.39.5
@@ -1,438 +0,0 @@
From a32431d5f7574ffa6391221c7740f1739203eaa7 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 8 Mar 2024 09:27:36 -0700
Subject: [PATCH 15/51] mb/dell: Add Latitude E6220 (Sandy Bridge)
Mainboard is codenamed Vida. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. The VBT was obtained using
intelvbttool while running version A14 (latest available version) of the
vendor firmware.
Tested and found to boot as part of a libreboot build based on upstream
coreboot commit b7341da191 with additional patches, though these do not
appear to affect SNB/IVB. The base E6430 patch was tested against
coreboot main.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/Kconfig | 9 +
.../dell/snb_ivb_latitude/Kconfig.name | 3 +
.../snb_ivb_latitude/variants/e6220/data.vbt | Bin 0 -> 3985 bytes
.../variants/e6220/early_init.c | 14 ++
.../snb_ivb_latitude/variants/e6220/gpio.c | 192 ++++++++++++++++++
.../variants/e6220/hda_verb.c | 32 +++
.../variants/e6220/overridetree.cb | 37 ++++
7 files changed, 287 insertions(+)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index 84ffe1d33a..baa83baa41 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520
select BOARD_ROMSIZE_KB_6144
select SOUTHBRIDGE_INTEL_BD82X6X
+config BOARD_DELL_LATITUDE_E6220
+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ select BOARD_ROMSIZE_KB_10240
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select SOUTHBRIDGE_INTEL_BD82X6X
+
config BOARD_DELL_LATITUDE_E6320
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_10240
@@ -73,6 +79,7 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
+ default "Latitude E6220" if BOARD_DELL_LATITUDE_E6220
default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320
default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
@@ -89,6 +96,7 @@ config USBDEBUG_HCD_INDEX
config VARIANT_DIR
default "e5420" if BOARD_DELL_LATITUDE_E5420
default "e5520" if BOARD_DELL_LATITUDE_E5520
+ default "e6220" if BOARD_DELL_LATITUDE_E6220
default "e6320" if BOARD_DELL_LATITUDE_E6320
default "e6420" if BOARD_DELL_LATITUDE_E6420
default "e6520" if BOARD_DELL_LATITUDE_E6520
@@ -102,6 +110,7 @@ config VGA_BIOS_ID
default "8086,0166" if BOARD_DELL_LATITUDE_E5530
default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
|| BOARD_DELL_LATITUDE_E5520 \
+ || BOARD_DELL_LATITUDE_E6220 \
|| BOARD_DELL_LATITUDE_E6320
default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
|| BOARD_DELL_LATITUDE_E6530
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
index ef6a1329a9..349ee7f79e 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420
config BOARD_DELL_LATITUDE_E5520
bool "Latitude E5520"
+config BOARD_DELL_LATITUDE_E6220
+ bool "Latitude E6220"
+
config BOARD_DELL_LATITUDE_E6320
bool "Latitude E6320"
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..548075a74500b5d159108089ee29cff802d07db7
GIT binary patch
literal 3985
zcmdT{eP|p-6#wn*-rZ(yH@R-odPzTgZQ6LXjonL|7&YQ0xu#d`$C=h}21|4GP8*0x
zyjE@hv0Dv(P?c0g{G(_DMJZ@22r8oZ0U9lcR8a)~s33wOSg|T<^?b8?XBzL?#)6`A
z{N~Nfd-LYan>TOv7WZ{+rcIq264!S1u1&02-MpSC3mf}u-r~BvbgkXEX=|c$bLZBs
zbsM{{q9-s1nVR3f2C|A`nJsqvC7UwC+1=angV`H%w4sao<P?&OTVpYbtz1OwGuLN^
zhBCv{M16zV3^h|KGn^Zu#@6L@%V;*UGnb`pgTtBpU~UJE3=i!tH{%>fx<^KL=Lc`x
zzLTQeOW7vdZsuwwtsUOU>vxajM=zqzp&{y(GCQa@w<DLoHJ81}6s7=PS9MJR6hDG@
zLaF+#1qlrS4OKdX4nv2kz^}p75z-OVFk8cF4b?h&G(>eIb%fzF6`uwy)UhaB+ynus
zBRr-~^|__t=m5fD9tR81r@XLV3UEc-2I6>o`;@@MXS$rj)&)r+pA?|K2vh+9SHM=N
zw3d{Uh1~iK)juV`E`v4?cFU@^_DehBU5TFLmFrTyoBPuJ*ExIdxO1!lC!eceSG8i}
z&A<Zmt5Mvo`mkSZ$5C|>ivl*T2}Cf;*vEJvsN-nR!WWDm8M<y^zAkV9BgVLlk!18T
zu4CN5*u}VmaUbIm#suRa;|0cRj7i2(#%GK#8OIsFFtjRxYDQoSP8NI)g09_;Qlzsy
z3O>^Zmcltu96wMRudvHXLxn;xh~EqEM^Gr}m&=vHbwRKjl{%)fM2d8tOI4MM{l!dK
z4$)%2P!LDJaqX2t;s4$Wy@Q1gZ=x97<n3qFBc<Bm#;F26e|~<6=hD9lOk>K<zaU`L
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zMLIYMDVoel8h1}$+_YJF%DJ&-O)X~`ZoroouO-yDsj)OrPU{{+ph4LJKdD;Bi3a3T
zbe?Tf8&<r^`I<R>elW+H+t;5$y~|nhq{o@?k1^-Hg%jhcu{xJyzvgk`0m*Te#GQe$
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z3BN(h4C``3tTE^&!`fqrdks2dSZ^5Oh(X^Omdc+rCapBB)uz~J(k-TSw<-3U^rC6K
zYl;s|`q{KX)nazFdEs%*@f}l~SsY?~kb2(WgGl=fm!43<O#L+%@MH9Gl`~Gq=7;rx
zMc&31@YxsRfz-6`>>4I&2(k1$iaK?FYVZ}~h~1{1T|;>=%b4`yk3XF>siEVHyC@HS
z8OvVW%DeB`K&~H7>f?&^gQU_A0oM<l8+N5oZ4)iV>;p0b*k61j!x*S5X(-unS`9rZ
zG}=vb+R*x})DSq-Q7;uJwKLPuG`Ej6G}#nch4dSqhHo0B2Gq%HbgCyS+pwZ3{?fph
z!Jo*Dxcw7v7a#rIU2IRmVn4KE$x~88+a7J4zd|_!%xo9z$+P;Q6qA*AQ5FvzlPW^f
zY&aJUhO1#_o~&$x>1qJKGpC+K<(u_&1197<WZ2zu79e*q&i9c$DPNGYYw%s_L~d?x
zj;EW8N#6BCjjMs5>VVWxipk10ERAEpLG3^|JWI~<Y~c5vi!sB;W|~-R<=`-_TSLhN
zYlyAlPUkfn-CnHq)Xv2vv1R->DYG*_Qk)fwt)g^KZ*f*K5tEj9C7Ea`HGyPe8U4wd
nX2Iz@%Q6UTm;}-X%j^D0i1fiT)I6)4TdrsMY}`L(<y7krryzQ}
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c
new file mode 100644
index 0000000000..ff83db095b
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
new file mode 100644
index 0000000000..2306e4cf0a
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio1 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
new file mode 100644
index 0000000000..0c69f0bd0e
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x102804a9, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x102804a9),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
new file mode 100644
index 0000000000..9faf27e27b
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
@@ -0,0 +1,37 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1028 0x04a9 inherit
+
+ device ref igd on
+ register "gpu_cpu_backlight" = "0x0000046a"
+ register "gpu_pch_backlight" = "0x13121312"
+ end
+
+ chip southbridge/intel/bd82x6x
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+ register "usb_port_config" = "{
+ { 1, 1, 0 },
+ { 1, 0, 0 },
+ { 1, 1, 1 },
+ { 1, 0, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 0, 6 },
+ { 1, 0, 7 },
+ }"
+
+ device ref pcie_rp4 off end
+ device ref sata1 on
+ register "sata_port_map" = "0x3b"
+ end
+ end
+ end
+end
--
2.39.5
@@ -1,7 +1,7 @@
From ce7d65790b9b8656ebbaa0ca715adff6a9c25588 Mon Sep 17 00:00:00 2001
From 18216387e5c40ec3c80c63ec25e9b0c55a009cff Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 4 May 2024 02:00:53 +0100
Subject: [PATCH 26/51] nb/haswell: lock policy regs when disabling IOMMU
Subject: [PATCH 15/48] nb/haswell: lock policy regs when disabling IOMMU
Angel Pons told me I should do it. See comments here:
https://review.coreboot.org/c/coreboot/+/81016
@@ -51,5 +51,5 @@ index 1a7e0b1076..e9506ee830 100644
/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
u32 reg32;
--
2.39.5
2.47.3
@@ -1,436 +0,0 @@
From 0889cc6b6f62cba616feff5ae8558be31f298069 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 8 Mar 2024 09:33:03 -0700
Subject: [PATCH 16/51] mb/dell: Add Latitude E6330 (Ivy Bridge)
Mainboard is QAL70/LA-7741P. I do not physically have this system;
someone with physical access to one sent me the output of autoport which
I then modified to produce this port. I was also sent the VBT binary,
which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
version A21 of the vendor firmware. This port has not been tested.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I827826e9ff8a9a534c50250458b399104478e06c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/Kconfig | 11 +-
.../dell/snb_ivb_latitude/Kconfig.name | 3 +
.../snb_ivb_latitude/variants/e6330/data.vbt | Bin 0 -> 6144 bytes
.../variants/e6330/early_init.c | 14 ++
.../snb_ivb_latitude/variants/e6330/gpio.c | 192 ++++++++++++++++++
.../variants/e6330/hda_verb.c | 32 +++
.../variants/e6330/overridetree.cb | 37 ++++
7 files changed, 288 insertions(+), 1 deletion(-)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index baa83baa41..49bf225fe2 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530
select BOARD_ROMSIZE_KB_12288
select SOUTHBRIDGE_INTEL_C216
+config BOARD_DELL_LATITUDE_E6330
+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ select BOARD_ROMSIZE_KB_12288
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select SOUTHBRIDGE_INTEL_C216
+
config BOARD_DELL_LATITUDE_E6430
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_12288
@@ -84,6 +90,7 @@ config MAINBOARD_PART_NUMBER
default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
+ default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330
default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
@@ -101,13 +108,15 @@ config VARIANT_DIR
default "e6420" if BOARD_DELL_LATITUDE_E6420
default "e6520" if BOARD_DELL_LATITUDE_E6520
default "e5530" if BOARD_DELL_LATITUDE_E5530
+ default "e6330" if BOARD_DELL_LATITUDE_E6330
default "e6430" if BOARD_DELL_LATITUDE_E6430
default "e6530" if BOARD_DELL_LATITUDE_E6530
config VGA_BIOS_ID
default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \
|| BOARD_DELL_LATITUDE_E5420
- default "8086,0166" if BOARD_DELL_LATITUDE_E5530
+ default "8086,0166" if BOARD_DELL_LATITUDE_E5530 \
+ || BOARD_DELL_LATITUDE_E6330
default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
|| BOARD_DELL_LATITUDE_E5520 \
|| BOARD_DELL_LATITUDE_E6220 \
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
index 349ee7f79e..d6fc8eb224 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520
config BOARD_DELL_LATITUDE_E5530
bool "Latitude E5530"
+config BOARD_DELL_LATITUDE_E6330
+ bool "Latitude E6330"
+
config BOARD_DELL_LATITUDE_E6430
bool "Latitude E6430"
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..18856746656058651c571ecbb3708e0543b19d62
GIT binary patch
literal 6144
zcmeHKU2GiH75-*tc6WAmW_LYygMSkDB*E^Q*zv5f7dLg)@$NQV2a{}!yImnfyvQ4D
z;n-$v0!RpNi<_o@ktI-@2a590stC0zRi%iRR%stvi&hAs3R<K}X~hFddB_6@s8W`5
zXJ!q~E{TOme<a`8@BW;7?l<?GIp@yo&H2<M-FZ0GKbBAR-Ekx}HvVOrhK1*2?{QsU
zQe#K%JeC=q96gpAKa#$keu^D99ee*0FfB=@F_0J<9-Ch-&BZ5r1T6`{$;1%Fm+qfk
zTr5pfAz@KB*NGlFzEGx2aqh%IxkQOuX*`{wy~+KQo+-}XSE7aaxko77OBtFgoh;4K
z(#-7f<x+WxmKSK)vQFgtt^L+?s+Z<V57E7|^TqOPX{mn0n<VLl#Yf7s_suL*Jl#VB
zmSyz~ScwEVTc-3vd2v6D&dt$;&{?91(o(5>vNXNl&<qW@AghW5NPYw#ha~-b0Dc7_
z6}t(eHgpwn6<HNi1Vcp^p-07-iXve~MTs!0A_ku!`4nKciajxJYXsOYuuT4N%smA!
zPazgl&bNRSrvAz|_6r3+B;r1=!7D;RUUw8Ke+vNt7E3`(BA-woPvJFBK^3Gzfh4Nk
zOX!J0PJNB)Mk&Z_i?S2ez+iItz=)m79LydX&rM9`3wPaJ`T92=Uv0;g-!<4*M6z%+
z*omwb#VI+CU&%iFS{_DGS;sE}7G4juqRMCww!+k6=+abJj4v>Dsr*z_6HAP5GJeST
znX2JD;{xLa#;c6KGychVn-L6YXkv6Qx)}Y8&ok1DI~ZSM6dCt39%QUAzRh@o@gqjy
zL0qZ&DhN8ZR3xu$a$Cd{oasU3DNp{CCl6f~PYlq!Hte;Ia0^wn8Vut7>Wl1)s`^E-
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zgVc!G9?@=&(4mNVcSJiLq3=b^rz6@k5qdFVUW{m$A{2|7d!kxz)VSrcQt@4sDoq^f
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zEMK3YKB+`*xOu>iR|LbzHLa*mLXlH${^b4c9%>9%)HO-?LA1gT0mlz!M}8&;(;^x|
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zewtgef*II~y;k>*B!+(8*blXsY-~kcJa9zG2yfcMCt+|-0ex$pY`h1<*#rEv=~*<+
ztV``Um!q33-Aap9fUshX^N~GS2@X3^U9+MwgYQ74^?~6&yU^#oY#cvC9R_}P2d<wN
zJvOE)Xr7A2n#3x14}2_g(YN^0+oYDbb#|V{ze3pzGb9FiF#6Ra&L}bT(ZOvswS7RY
zxLjWFRwWXHR5&={t;%K+Vkd6NX2iF<SF)LXv@y472OmG!_W%Ni*ZDuev-S0%b!dfW
wz4{IL!+uT9t2XI4@_L@?Ri*bc_<n8A+wHaowmq=zfo%_LdtloGpN<DU00~N<ApigX
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
new file mode 100644
index 0000000000..ff83db095b
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
new file mode 100644
index 0000000000..777570765a
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
new file mode 100644
index 0000000000..804733b172
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x10280533, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280533),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
new file mode 100644
index 0000000000..4125159367
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
@@ -0,0 +1,37 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1028 0x0533 inherit
+
+ device ref igd on
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_pch_backlight" = "0x13121312"
+ end
+
+ chip southbridge/intel/bd82x6x
+ register "usb_port_config" = "{
+ { 1, 2, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 2, 3 },
+ { 1, 2, 3 },
+ { 1, 2, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 0, 6 },
+ }"
+
+ device ref xhci on
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ end
+ end
+ end
+end
--
2.39.5
@@ -1,7 +1,7 @@
From c6181fe0c8b58cb5a4523d5763fc5fcdf61b3f10 Mon Sep 17 00:00:00 2001
From d797b9d19c6bc3224897000756caef29e98dd266 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 10 May 2021 22:40:59 +0200
Subject: [PATCH 27/51] nb/intel/gm45: Make DDR2 raminit work
Subject: [PATCH 16/48] nb/intel/gm45: Make DDR2 raminit work
List of changes:
- Update some timing and ODT values
@@ -20,7 +20,7 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
3 files changed, 106 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index 5d9ac56606..338260ea7a 100644
index f68bfdee7a..b76117bc3a 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
@@ -31,9 +31,9 @@ index 5d9ac56606..338260ea7a 100644
+void raminit_rcomp_calibration(int ddr_type, stepping_t stepping);
void raminit_reset_readwrite_pointers(void);
void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume);
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index b7e013959a..df8f46fbbc 100644
index def9e1e331..7b091cc567 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping,
@@ -70,7 +70,7 @@ index b7e013959a..df8f46fbbc 100644
}
mchbar_write32(CxODT_HIGH(ch), reg);
@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume)
raminit_write_training(timings->mem_clock, dimms, s3resume);
}
@@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
}
--
2.39.5
2.47.3
@@ -1,440 +0,0 @@
From 84d7f3201eb4492acd7d290a02d19c4850c85791 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Oct 2017 21:26:43 +0800
Subject: [PATCH 17/51] mb/dell: Add Latitude E6230 (Ivy Bridge)
This was adapted from CB:22693 from Iru Cai, which was based on
autoport. I do not physically have this system. Someone with physical
access to an E6230 running version A11 of the vendor firmware sent me
the VBT after running the command `intelvbttool --inlegacy --outvbt
data.vbt`. This new version of the port has not yet been tested.
The EC is the SMSC MEC5055, which seems to be compatible with the
existing MEC5035 code. As with the other Dell systems with this EC, this
board is assumed to be internally flashable using an EC command that
tells it to pull the FDO pin low on the next boot, which also tells the
vendor firmware to disable all write protections to the flash [1].
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Original-Change-Id: I8cdc01e902e670310628809416290045c2102340
Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/Kconfig | 11 +-
.../dell/snb_ivb_latitude/Kconfig.name | 3 +
.../snb_ivb_latitude/variants/e6230/data.vbt | Bin 0 -> 4280 bytes
.../variants/e6230/early_init.c | 12 ++
.../snb_ivb_latitude/variants/e6230/gpio.c | 193 ++++++++++++++++++
.../variants/e6230/hda_verb.c | 32 +++
.../variants/e6230/overridetree.cb | 40 ++++
7 files changed, 290 insertions(+), 1 deletion(-)
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
index 49bf225fe2..f6e097930b 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530
select BOARD_ROMSIZE_KB_12288
select SOUTHBRIDGE_INTEL_C216
+config BOARD_DELL_LATITUDE_E6230
+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ select BOARD_ROMSIZE_KB_12288
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select SOUTHBRIDGE_INTEL_C216
+
config BOARD_DELL_LATITUDE_E6330
select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
select BOARD_ROMSIZE_KB_12288
@@ -90,6 +96,7 @@ config MAINBOARD_PART_NUMBER
default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
+ default "Latitude E6230" if BOARD_DELL_LATITUDE_E6230
default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330
default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
@@ -108,6 +115,7 @@ config VARIANT_DIR
default "e6420" if BOARD_DELL_LATITUDE_E6420
default "e6520" if BOARD_DELL_LATITUDE_E6520
default "e5530" if BOARD_DELL_LATITUDE_E5530
+ default "e6230" if BOARD_DELL_LATITUDE_E6230
default "e6330" if BOARD_DELL_LATITUDE_E6330
default "e6430" if BOARD_DELL_LATITUDE_E6430
default "e6530" if BOARD_DELL_LATITUDE_E6530
@@ -121,7 +129,8 @@ config VGA_BIOS_ID
|| BOARD_DELL_LATITUDE_E5520 \
|| BOARD_DELL_LATITUDE_E6220 \
|| BOARD_DELL_LATITUDE_E6320
- default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
+ default "8086,0166" if BOARD_DELL_LATITUDE_E6230 \
+ || BOARD_DELL_LATITUDE_E6430 \
|| BOARD_DELL_LATITUDE_E6530
endif
diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
index d6fc8eb224..cb7bbd5cdb 100644
--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520
config BOARD_DELL_LATITUDE_E5530
bool "Latitude E5530"
+config BOARD_DELL_LATITUDE_E6230
+ bool "Latitude E6230"
+
config BOARD_DELL_LATITUDE_E6330
bool "Latitude E6330"
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..45ce8f435eea647a0bddaab3fd1e9282c87afc66
GIT binary patch
literal 4280
zcmdT{Yiu0V75-*tAG5PFyX&zDekA7P<*tbx&o1`j23L%CmvkLWvN7(mLa6alZ?J`9
zo3#m4YVlG`2;w12Ajppt<qra(R;8*G@uw*8gIcsg2vxi!q_pBkmGUD$s9IGi+jD1T
zO`Kg43n@JA>~|mMp8L%`XU@4ZyCa_(r`z|Z`bP4p-rEkOMn-R;Ntk#o`b)0sOKRl6
z?T0eM<HLtiqX*Kr(o5Kc<Iyk90h5ws=!y8i;K=M^X(l$-Eoeyyj>ZS*@LZWP#hD{>
z<r2jcJ;b8e!oAb;^QB2D#7*krI^IpA=?ra8?xvqj6=&}$QL2a1J(QuD($UfkElf=x
zUM!UtXmO4PP4h^;&)jWJvd(Pj0lIs7wpgAnE!1!MB1w8~{^#ZCd!`mCmhPs6X_~zW
zGae^<%aoog&+n$;nHd@rItw&bS}2u|mL_-Ws;&ZOWW_51k`IALAW8pAz~@C!!B)bs
z1x-OrK~}*8L07Po(5+xZL6I<}phTEf5QRsVJYHa{f^AWEV+2@lvrPVS%snsOn?N)w
zpKbvwOnk&Q_6Y?aB;r1=!TYwts;yA@BnbFfECo!7JVJq7g^yhYMUV;wlBjksp(hI2
z^<}E7r698{-pw!*{mH>SLslxYH@j~%H#VLx+<8~!;a@$n+>Q%xHrQ8KGI21_iL4sI
zF*$}m$R7Mr9z@Z*ir@Q9eClsSmC+t(g`q~VQ&nIxZenav_^Buc78s8*o@e|<QE{4a
zhVeGz1IFJN|784&5eTYiVstQeGWr-lWTY9lG45a#8TT^oXDl%uXFS9BHN$^DE>t}g
z1Z-O>lG`>pEuvmL-HpmgSANo!2hWQq2B>Zua$8%tfvQ>!1n@=m9ri_4`H|Rx#SH9n
zDdRF_-FDP&WjW`L$GK%a6x?yO8l2!^g0HJrtA7TknNzCO?|U!wCv2^-5pJ%LW6!+P
z)anX%E>`gP%3Er4c6+J9x=Atk1{Abrr1|WSY3P`SO5j!R5F*vbbQ%AaSHnR_+x&Op
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zla9Tu=Jhyn5T<3$H#?Hfm-`+(d$7IBDx9cEvNv1i-LEDr>r7438bfkPcKod+mwd22
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z8!Of7<|N(^R#xcjmZ&nZ%~{pC5y_T*PB2LdDjuI#Te}-4Qccvj+u4N3TBx|oVy*mP
z<9xfFziy4n?sPv3Sqo7jWMo3>{tzvOjAJ2nB}At~#%f4?FGT+d8LFnXXtYN&Mm06B
z(JwUPX-z$$(d(M=uBLvh@h6#K=;~&jQo1p&t3TCgSvQ{3)l)jXr5hjW>fd!z!bW>o
z-4UjJVdJi_dN@o^hK(1(>dRqzCv2PztLMTLjTqY^YEMMJ{=B#1IV)9~IMg|yl(NPF
zQSfMX`?(b5)))B!zjy0B$ua20CCLTPl^IS&2=T&Zid9-1*K{VAJP?rxjYC+zGDCe*
ziQI7VfF17@3`3W-qCN>lPC5CL_c?p0F<ekqB;g0q3P1R5KNubPsT>TGXaGB3i~{ZE
zr=QtIprytDnU7C*Wj%x0k)O{Y%nUnl%}K%F|J_iVaD&ubW4Qbtx;pZEb9}f^Yd;Ea
zI1Ha{7Yt~z{LAY++1QG{F6*_4WsUziY{x?%I9B}i5-Tphhk8FGm%J<d_0CUoV^%N&
zTe02j+LXk=ZyWoe7L$#wsEY@VC>f!3d-ysG_9>uk%#)4xpxb+ZkJdel#+h}l9j9`1
zt*M!5u?i4YtZ+WECo6$LJF06|G-mMZskGiV*lQJf-ItB+hltI<?{5E<^P=0rL<P+g
z(P)!c<?MlvMK0O~UwZ4*;x|ms(&&#Vn_-4{KM#g~a=;$N2QD7mSX0{t<cf>sId@e&
z-cN<SWA3VKCN6g3lx#+PySpWu*+pw}>vr(fgI)K*zkikg6TDJi?^}ghc*U*%A%EGg
Y$$8Z}9a~<{Q@y10T!W`-d%n2+Kj)*Kg#Z8m
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
new file mode 100644
index 0000000000..24c1b32467
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
new file mode 100644
index 0000000000..c07e4b1c56
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio17 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
new file mode 100644
index 0000000000..f6876f9e09
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x10280532, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280532),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
new file mode 100644
index 0000000000..3a0fa720da
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
@@ -0,0 +1,40 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+ device domain 0 on
+ subsystemid 0x1028 0x0532 inherit
+
+ device ref igd on
+ register "gpu_cpu_backlight" = "0x000009e9"
+ register "gpu_pch_backlight" = "0x13121312"
+ end
+
+ chip southbridge/intel/bd82x6x
+ register "usb_port_config" = "{
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 0, 1 },
+ { 1, 2, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 1, 3 },
+ { 1, 2, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 0, 6 },
+ }"
+
+ device ref xhci on
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ end
+ device ref sata1 on
+ register "sata_port_map" = "0x31"
+ end
+ end
+ end
+end
--
2.39.5
@@ -1,7 +1,7 @@
From b6f75374fa38e0b097c9eadb4916112707cb6747 Mon Sep 17 00:00:00 2001
From e573065ac900d4decfd4dbd0a1464d82501ac3c5 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Tue, 6 Aug 2024 00:50:24 +0100
Subject: [PATCH 28/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
Subject: [PATCH 17/48] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
We add this patch:
@@ -32,7 +32,7 @@ Signed-off-by: Leah Rowe <info@minifree.org>
2 files changed, 88 insertions(+), 82 deletions(-)
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index df8f46fbbc..433db3a68c 100644
index 7b091cc567..478898564a 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
@@ -47,7 +47,7 @@ index df8f46fbbc..433db3a68c 100644
} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume)
raminit_write_training(timings->mem_clock, dimms, s3resume);
}
@@ -236,5 +236,5 @@ index b74765fd9c..5d4505e063 100644
+ }
}
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From d3045b3dcebd94b78df2129cd81a20adf215e46a Mon Sep 17 00:00:00 2001
From 130a5ca25fbedb58e49b613e4a7cece715b545ae Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 20 May 2024 10:24:16 -0600
Subject: [PATCH 29/51] mb/dell/e6400: Use 100 MHz reference clock for display
Subject: [PATCH 18/48] mb/dell/e6400: Use 100 MHz reference clock for display
The E6400 uses a 100 MHz reference clock for spread spectrum support on
LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
@@ -14,26 +14,25 @@ display in the pre-OS graphics environment provided by libgfxinit.
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6400/Kconfig | 3 +++
src/northbridge/intel/gm45/Kconfig | 4 ++++
2 files changed, 7 insertions(+)
src/mainboard/dell/gm45_latitude/Kconfig | 2 ++
src/northbridge/intel/gm45/Kconfig | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
index 417d95fd5d..6fe1b1c456 100644
--- a/src/mainboard/dell/e6400/Kconfig
+++ b/src/mainboard/dell/e6400/Kconfig
@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_GMA_HAVE_VBT
select EC_DELL_MEC5035
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
index edc79b0d43..5020744990 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
@@ -22,6 +22,8 @@ config BOARD_DELL_E6400
select BOARD_DELL_GM45_LATITUDE_COMMON
if BOARD_DELL_GM45_LATITUDE_COMMON
+config INTEL_GMA_DPLL_REF_FREQ
+ default 100000000
+
config MAINBOARD_DIR
default "dell/e6400"
config MAINBOARD_DIR
default "dell/gm45_latitude"
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 8059e7ee80..5df5a93296 100644
index a776217475..35e89b0c88 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
@@ -48,5 +47,5 @@ index 8059e7ee80..5df5a93296 100644
select VBOOT_STARTS_IN_BOOTBLOCK
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From 53f2d47ee6ebaa8d47b076a6c2a1514c91247b95 Mon Sep 17 00:00:00 2001
From 7641a4b9b91c385223026cd566e0ffc2a2aa0d8f Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Mon, 12 Aug 2024 02:15:24 +0100
Subject: [PATCH 47/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
Subject: [PATCH 19/48] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
set it to 96MHz. fixes the following build error when
building for x4x boards e.g. gigabyte ga-g41m-es2l:
@@ -33,7 +33,7 @@ Signed-off-by: Leah Rowe <info@minifree.org>
1 file changed, 4 insertions(+)
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 9af063819b..93ba575b95 100644
index 6fa4551957..646af3510b 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
@@ -48,5 +48,5 @@ index 9af063819b..93ba575b95 100644
default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From ac8ac2543e3ebbc05f79f37d1460cde532a7ee1c Mon Sep 17 00:00:00 2001
From 36126c093a9b9e01d41f0a68977cd09070c3c276 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Sep 2024 19:51:25 -0600
Subject: [PATCH 49/51] mb/dell/gm45_latitudes: Add E4300 variant
Subject: [PATCH 20/48] mb/dell/gm45_latitudes: Add E4300 variant
Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -21,7 +21,7 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
index ba76fb6e8c..144f9bcdf0 100644
index 5020744990..d27d5728a8 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
@@ -32,9 +32,9 @@ index ba76fb6e8c..144f9bcdf0 100644
+ select BOARD_DELL_GM45_LATITUDE_COMMON
+
if BOARD_DELL_GM45_LATITUDE_COMMON
config INTEL_GMA_DPLL_REF_FREQ
@@ -31,12 +34,14 @@ config MAINBOARD_DIR
default 100000000
@@ -30,12 +33,14 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "Latitude E6400" if BOARD_DELL_E6400
@@ -328,5 +328,5 @@ index 0000000000..20dfa245fb
+ end
+end
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From 5e8b899654c31fe771e4b1e96c74c93d4509c3b2 Mon Sep 17 00:00:00 2001
From 4caca6e6e349fa1913df622081025ea53bfd136f Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 16:31:12 -0600
Subject: [PATCH 50/51] mb/dell: Add S3 SMI handler for Dell Latitudes
Subject: [PATCH 21/48] mb/dell: Add S3 SMI handler for Dell Latitudes
Integrate the previously added mec5035_smi_sleep() function into
mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
@@ -12,19 +12,19 @@ the power LED while in S3. Without it, all LEDs turn off during S3.
Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e7240/smihandler.c | 9 +++++++++
src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++
src/mainboard/dell/haswell_latitude/smihandler.c | 9 +++++++++
src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
3 files changed, 27 insertions(+)
create mode 100644 src/mainboard/dell/e7240/smihandler.c
create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c
create mode 100644 src/mainboard/dell/haswell_latitude/smihandler.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
diff --git a/src/mainboard/dell/e7240/smihandler.c b/src/mainboard/dell/e7240/smihandler.c
diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
new file mode 100644
index 0000000000..00e55b51db
--- /dev/null
+++ b/src/mainboard/dell/e7240/smihandler.c
+++ b/src/mainboard/dell/gm45_latitude/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
@@ -35,11 +35,11 @@ index 0000000000..00e55b51db
+{
+ mec5035_smi_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
diff --git a/src/mainboard/dell/haswell_latitude/smihandler.c b/src/mainboard/dell/haswell_latitude/smihandler.c
new file mode 100644
index 0000000000..00e55b51db
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/smihandler.c
+++ b/src/mainboard/dell/haswell_latitude/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
@@ -66,5 +66,5 @@ index 0000000000..00e55b51db
+ mec5035_smi_sleep(slp_typ);
+}
--
2.39.5
2.47.3
@@ -0,0 +1,31 @@
From 669ef0d2c72326134f64a4fe70f67220ec690c5e Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Tue, 31 Dec 2024 14:42:24 +0000
Subject: [PATCH 22/48] Disable compression on refcode insertion
Compression is not reliably reproducible. In an lbmk release
context, this means we cannot rely on vendorfile insertion.
Therefore, use uncompressed refcode.
Signed-off-by: Leah Rowe <info@minifree.org>
---
Makefile.mk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile.mk b/Makefile.mk
index 5fccb4a52d..c40e06c453 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1414,7 +1414,7 @@ endif
cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
$(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
$(CONFIG_CBFS_PREFIX)/refcode-type := stage
-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG)
+$(CONFIG_CBFS_PREFIX)/refcode-compression := none
cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
--
2.47.3
@@ -0,0 +1,187 @@
From c7b136f1f4fa2bc1a783711b5a1ee82c5d9ce69f Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 21 Apr 2025 02:58:47 +0100
Subject: [PATCH 23/48] nb/intel/*: Disable stack overflow debug options
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/northbridge/intel/e7505/Kconfig | 9 +++++++++
src/northbridge/intel/gm45/Kconfig | 9 +++++++++
src/northbridge/intel/haswell/Kconfig | 9 +++++++++
src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++
src/northbridge/intel/i945/Kconfig | 9 +++++++++
src/northbridge/intel/ironlake/Kconfig | 9 +++++++++
src/northbridge/intel/pineview/Kconfig | 9 +++++++++
src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++
src/northbridge/intel/x4x/Kconfig | 9 +++++++++
9 files changed, 85 insertions(+)
diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
index 039a7396f8..ddcb986f10 100644
--- a/src/northbridge/intel/e7505/Kconfig
+++ b/src/northbridge/intel/e7505/Kconfig
@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505
select NO_CBFS_MCACHE
select SMM_TSEG
select NEED_SMALL_2MB_PAGE_TABLES
+
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 35e89b0c88..c5456d0ddf 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index c57f1ec380..0a5181b183 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL
if NORTHBRIDGE_INTEL_HASWELL
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
config USE_NATIVE_RAMINIT
bool "[NOT COMPLETE] Use native raminit"
default n
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
index dbb2d7436b..5e9418b6a9 100644
--- a/src/northbridge/intel/i440bx/Kconfig
+++ b/src/northbridge/intel/i440bx/Kconfig
@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM
If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.
+
+if NORTHBRIDGE_INTEL_I440BX
+
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
+endif
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index c4e17f90bf..b12f5be091 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index 39566a6e5f..f46acf6937 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index a05b866dad..50e3a7cdb9 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE
config DOMAIN_RESOURCE_32BIT_LIMIT
default 0xfec00000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 9972a43da0..fe4ac5106c 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX
default 2 if IGD_DEFAULT_UMA_SIZE_96MB
default 3 if IGD_DEFAULT_UMA_SIZE_128MB
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 646af3510b..069fa0244d 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
--
2.47.3
@@ -1,91 +0,0 @@
From a1566875789469ebd91e472301be4b359aac0a4c Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Tue, 28 May 2024 17:23:21 -0600
Subject: [PATCH 24/51] ec/dell/mec5035: Replace defines with enums
Instead of using defines for command IDs and argument values, use enums
to provide more type safety. This also has the effect of moving the
command IDs to a more central location instead of defines spread out
throughout the header.
Change-Id: I788531e8b70e79541213853f177326d217235ef2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
---
src/ec/dell/mec5035/mec5035.c | 10 +++++-----
src/ec/dell/mec5035/mec5035.h | 20 ++++++++++++--------
2 files changed, 17 insertions(+), 13 deletions(-)
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index 68b6b2f7fb..dffbb7960c 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -66,17 +66,17 @@ static enum cb_err write_mailbox_regs(const u8 *data, u8 start, u8 count)
return CB_SUCCESS;
}
-static void ec_command(u8 cmd)
+static void ec_command(enum mec5035_cmd cmd)
{
outb(0, MAILBOX_INDEX);
- outb(cmd, MAILBOX_DATA);
+ outb((u8)cmd, MAILBOX_DATA);
wait_ec();
}
-u8 mec5035_mouse_touchpad(u8 setting)
+u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting)
{
- u8 buf[15] = {0};
- write_mailbox_regs(&setting, 2, 1);
+ u8 buf[15] = {(u8)setting};
+ write_mailbox_regs(buf, 2, 1);
ec_command(CMD_MOUSE_TP);
/* The vendor firmware reads 15 bytes starting at index 1, presumably
to get some sort of return code. Though I don't know for sure if
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index fa15a9d621..32f791cb01 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -7,16 +7,20 @@
#define NUM_REGISTERS 32
+enum mec5035_cmd {
+ CMD_MOUSE_TP = 0x1a,
+ CMD_RADIO_CTRL = 0x2b,
+ CMD_CPU_OK = 0xc2,
+};
+
/* Touchpad (TP) and mouse related. The EC seems to
default to 0 which results in the TP not working. */
-#define CMD_MOUSE_TP 0x1a
-#define SERIAL_MOUSE 0 /* Disable TP, force use of a serial mouse */
-#define PS2_MOUSE 1 /* Disable TP when using a PS/2 mouse */
-#define TP_PS2_MOUSE 2 /* Leave TP enabled when using a PS/2 mouse */
-
-#define CMD_CPU_OK 0xc2
+enum ec_mouse_setting {
+ SERIAL_MOUSE = 0, /* Disable TP, force use of a serial mouse */
+ PS2_MOUSE, /* Disable TP when using a PS/2 mouse */
+ TP_PS2_MOUSE /* Leave TP enabled when using a PS/2 mouse */
+};
-#define CMD_RADIO_CTRL 0x2b
#define RADIO_CTRL_NUM_ARGS 3
enum ec_radio_dev {
RADIO_WLAN = 0,
@@ -29,7 +33,7 @@ enum ec_radio_state {
RADIO_ON
};
-u8 mec5035_mouse_touchpad(u8 setting);
+u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
void mec5035_cpu_ok(void);
void mec5035_early_init(void);
void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
--
2.39.5
@@ -1,7 +1,7 @@
From 534d696a570a50057153669247933ec1a4a2480f Mon Sep 17 00:00:00 2001
From c15a0ef9b964e9df9a5578ed271af4f1c0419f38 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 30 Sep 2024 20:44:38 -0400
Subject: [PATCH 5/8] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
Subject: [PATCH 24/48] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -704,5 +704,5 @@ index 0000000000..555b1c1f5c
+ end
+end
--
2.39.5
2.47.3
@@ -1,7 +1,7 @@
From 636cb8ae8610cd99b637448add778c8e4f364f3e Mon Sep 17 00:00:00 2001
From bfd5f6628a69d8704a84b30c4027149fe1b21efa Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 30 Oct 2024 20:55:25 -0600
Subject: [PATCH 8/8] mb/dell/optiplex_780: Add USFF variant
Subject: [PATCH 25/48] mb/dell/optiplex_780: Add USFF variant
Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -322,5 +322,5 @@ index 0000000000..555b1c1f5c
+ end
+end
--
2.39.5
2.47.3
@@ -0,0 +1,33 @@
From 82f47133c20abc720f5d5fa8a54be465ebd95f28 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 6 Jan 2025 01:53:53 +0000
Subject: [PATCH 26/48] src/intel/x4x: Disable stack overflow debug
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/northbridge/intel/x4x/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 069fa0244d..8c70344846 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER
int
default 256
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
# This number must be equal or lower than what's reported in ACPI PCI _CRS
config DOMAIN_RESOURCE_32BIT_LIMIT
default 0xfec00000
--
2.47.3
@@ -0,0 +1,42 @@
From 5c4439fb513c315ef3effff19146b331c492fa9b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 22 Apr 2025 10:21:59 +0100
Subject: [PATCH 27/48] hp/8300cmt: remove xhci_overcurrent_mapping
No longer needed, as per the following commit:
commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1
Author: Keith Hui <buurin@gmail.com>
Date: Tue Dec 31 18:19:31 2024 -0500
sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping
Removing this from the devicetree also allows the
board to compile, otherwise an error is thrown:
build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping'
147 | .xhci_overcurrent_mapping = 0x00000c03,
| ^~~~~~~~~~~~~~~~~~~~~~~~
build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror]
147 | .xhci_overcurrent_mapping = 0x00000c03,
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
index 3d21739b72..3a0b6d5c59 100644
--- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
- register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 0, 0 },
--
2.47.3
@@ -1,7 +1,7 @@
From adfeaeabcf98878814b463f14aba7871721d7606 Mon Sep 17 00:00:00 2001
From 71ec1f7a6480e72b77a567f8cc0c2673a5e7905f Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Wed, 11 Dec 2024 01:06:01 +0000
Subject: [PATCH 1/1] dell/3050micro: disable nvme hotplug
Subject: [PATCH 28/48] dell/3050micro: disable nvme hotplug
in my testing, when running my 3050micro for a few days,
the nvme would sometimes randomly rename.
@@ -24,34 +24,24 @@ new device (the one that you booted from).
the fix there was to disable hotplugging on that pci-e slot
for the nvme, so apply the same fix here for 3050 micro
Signed-off-by: Leah Rowe <info@minifree.org>
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
3rdparty/vboot | 2 +-
src/mainboard/dell/optiplex_3050/devicetree.cb | 4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
.../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/3rdparty/vboot b/3rdparty/vboot
index f1f70f46dc..902fe8af96 160000
--- a/3rdparty/vboot
+++ b/3rdparty/vboot
@@ -1 +1 @@
-Subproject commit f1f70f46dc5482bb7c654e53ed58d4001e386df2
+Subproject commit 902fe8af96ad662fac127cb8f51596491cf8272f
diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb
index 039709aa4a..0678ed1765 100644
--- a/src/mainboard/dell/optiplex_3050/devicetree.cb
+++ b/src/mainboard/dell/optiplex_3050/devicetree.cb
@@ -45,7 +45,9 @@ chip soc/intel/skylake
diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
index c5f1749b2c..ff48a8121a 100644
--- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
+++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
@@ -46,7 +46,7 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[20]" = "1"
register "PcieRpLtrEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieRpClkSrcNumber[20]" = "3"
- register "PcieRpHotPlug[20]" = "1"
+# disable hotplug on nvme to prevent renaming e.g. nvme0n1 rename to nvme0n2,
+# which could cause crashes in linux if booting from nvme
+ register "PcieRpHotPlug[20]" = "0"
end
# Realtek LAN
end
--
2.39.5
2.47.3
@@ -0,0 +1,61 @@
From 95a0af0eea56e1bddcb243ed135835448b90fa56 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 6 Jan 2025 01:36:23 +0000
Subject: [PATCH 29/48] src/intel/skylake: Disable stack overflow debug options
The option was appearing in T480/3050micro configs of lbmk,
after updating on the coreboot/next uprev for 20241206 rev8:
CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y
I did some digging. See coreboot commit:
commit 51cc2bacb6b07279b97e9934d079060475481fb6
Author: Subrata Banik <subratabanik@google.com>
Date: Fri Dec 13 13:07:28 2024 +0530
soc/intel/pantherlake: Disable stack overflow debug options
Well now:
I'm disabling this behaviour on Skylake, for the same
behaviour, because I want as few behaviour changes in general,
as possible, for the rev8 release.
According to Subrata's patch, which was for Pantherlake,
without this change, stack corruption can occur on verstage
and romstage early on. Please look at that coreboot patch,
referenced above, for clarity.
I see no harm in disabling this option for Skylake, since
the behaviour that it otherwise enables was not present
before.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/skylake/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 7c530f2c75..70c2a7643c 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -131,6 +131,15 @@ config DCACHE_RAM_SIZE
The size of the cache-as-ram region required during bootblock
and/or romstage.
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x20400 if FSP_USES_CB_STACK
--
2.47.3
@@ -1,348 +0,0 @@
From 0966980e52286985fcd0fac6325bdd99f35ebcb8 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Thu, 11 Apr 2024 17:25:07 +0200
Subject: [PATCH 30/51] haswell NRI: Initialise MPLL
Add code to initialise the MPLL (Memory PLL). The procedure is similar
to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 2 +
.../intel/haswell/native_raminit/init_mpll.c | 210 ++++++++++++++++++
.../haswell/native_raminit/io_comp_control.c | 22 ++
.../haswell/native_raminit/raminit_main.c | 3 +-
.../haswell/native_raminit/raminit_native.h | 11 +
.../intel/haswell/registers/mchbar.h | 3 +
6 files changed, 250 insertions(+), 1 deletion(-)
create mode 100644 src/northbridge/intel/haswell/native_raminit/init_mpll.c
create mode 100644 src/northbridge/intel/haswell/native_raminit/io_comp_control.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index ebf7abc6ec..c125d84f0b 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -1,5 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-or-later
+romstage-y += init_mpll.c
+romstage-y += io_comp_control.c
romstage-y += raminit_main.c
romstage-y += raminit_native.c
romstage-y += spd_bitmunching.c
diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
new file mode 100644
index 0000000000..1f3f2c29a9
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static uint32_t get_mem_multiplier(const struct sysinfo *ctrl)
+{
+ const uint32_t mult = NS2MHZ_DIV256 / (ctrl->tCK * ctrl->base_freq);
+
+ if (ctrl->base_freq == 100)
+ return clamp_u32(7, mult, 12);
+
+ if (ctrl->base_freq == 133)
+ return clamp_u32(3, mult, 10);
+
+ die("Unsupported base frequency\n");
+}
+
+static void normalize_tck(struct sysinfo *ctrl, const bool pll_ref100)
+{
+ /** TODO: Haswell supports up to DDR3-2600 **/
+ if (ctrl->tCK <= TCK_1200MHZ) {
+ ctrl->tCK = TCK_1200MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 1200;
+
+ } else if (ctrl->tCK <= TCK_1100MHZ) {
+ ctrl->tCK = TCK_1100MHZ;
+ ctrl->base_freq = 100;
+ ctrl->mem_clock_mhz = 1100;
+
+ } else if (ctrl->tCK <= TCK_1066MHZ) {
+ ctrl->tCK = TCK_1066MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 1066;
+
+ } else if (ctrl->tCK <= TCK_1000MHZ) {
+ ctrl->tCK = TCK_1000MHZ;
+ ctrl->base_freq = 100;
+ ctrl->mem_clock_mhz = 1000;
+
+ } else if (ctrl->tCK <= TCK_933MHZ) {
+ ctrl->tCK = TCK_933MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 933;
+
+ } else if (ctrl->tCK <= TCK_900MHZ) {
+ ctrl->tCK = TCK_900MHZ;
+ ctrl->base_freq = 100;
+ ctrl->mem_clock_mhz = 900;
+
+ } else if (ctrl->tCK <= TCK_800MHZ) {
+ ctrl->tCK = TCK_800MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 800;
+
+ } else if (ctrl->tCK <= TCK_700MHZ) {
+ ctrl->tCK = TCK_700MHZ;
+ ctrl->base_freq = 100;
+ ctrl->mem_clock_mhz = 700;
+
+ } else if (ctrl->tCK <= TCK_666MHZ) {
+ ctrl->tCK = TCK_666MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 666;
+
+ } else if (ctrl->tCK <= TCK_533MHZ) {
+ ctrl->tCK = TCK_533MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 533;
+
+ } else if (ctrl->tCK <= TCK_400MHZ) {
+ ctrl->tCK = TCK_400MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 400;
+
+ } else {
+ ctrl->tCK = 0;
+ ctrl->base_freq = 1;
+ ctrl->mem_clock_mhz = 0;
+ return;
+ }
+ if (!pll_ref100 && ctrl->base_freq == 100) {
+ /* Skip unsupported frequency */
+ ctrl->tCK++;
+ normalize_tck(ctrl, pll_ref100);
+ }
+}
+
+#define MIN_CAS 4
+#define MAX_CAS 24
+
+static uint8_t find_compatible_cas(struct sysinfo *ctrl)
+{
+ printk(RAM_DEBUG, "With tCK %u, try CAS: ", ctrl->tCK);
+ const uint8_t cas_lower = MAX(MIN_CAS, DIV_ROUND_UP(ctrl->tAA, ctrl->tCK));
+ const uint8_t cas_upper = MIN(MAX_CAS, 19); /* JEDEC MR0 limit */
+
+ if (!(ctrl->cas_supported >> (cas_lower - MIN_CAS))) {
+ printk(RAM_DEBUG, "DIMMs do not support CAS >= %u\n", cas_lower);
+ ctrl->tCK++;
+ return 0;
+ }
+ for (uint8_t cas = cas_lower; cas <= cas_upper; cas++) {
+ printk(RAM_DEBUG, "%u ", cas);
+ if (ctrl->cas_supported & BIT(cas - MIN_CAS)) {
+ printk(RAM_DEBUG, "OK\n");
+ return cas;
+ }
+ }
+ return 0;
+}
+
+static enum raminit_status find_cas_tck(struct sysinfo *ctrl)
+{
+ /** TODO: Honor all possible PLL_REF100_CFG values **/
+ uint8_t pll_ref100 = (pci_read_config32(HOST_BRIDGE, CAPID0_B) >> 21) & 0x7;
+ printk(RAM_DEBUG, "PLL_REF100_CFG value: 0x%x\n", pll_ref100);
+ printk(RAM_DEBUG, "100MHz reference clock support: %s\n", pll_ref100 ? "yes" : "no");
+
+ uint8_t selected_cas;
+ while (true) {
+ /* Round tCK up so that it is a multiple of either 133 or 100 MHz */
+ normalize_tck(ctrl, pll_ref100);
+ if (!ctrl->tCK) {
+ printk(BIOS_ERR, "Couldn't find compatible clock / CAS settings\n");
+ return RAMINIT_STATUS_MPLL_INIT_FAILURE;
+ }
+ selected_cas = find_compatible_cas(ctrl);
+ if (selected_cas)
+ break;
+
+ ctrl->tCK++;
+ }
+ printk(BIOS_DEBUG, "Found compatible clock / CAS settings\n");
+ printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK);
+ printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", selected_cas);
+ ctrl->multiplier = get_mem_multiplier(ctrl);
+ return RAMINIT_STATUS_SUCCESS;
+}
+
+enum raminit_status initialise_mpll(struct sysinfo *ctrl)
+{
+ if (ctrl->tCK > TCK_400MHZ) {
+ printk(BIOS_ERR, "tCK is too slow. Increasing to 400 MHz as last resort\n");
+ ctrl->tCK = TCK_400MHZ;
+ }
+ while (true) {
+ if (!ctrl->qclkps) {
+ const enum raminit_status status = find_cas_tck(ctrl);
+ if (status)
+ return status;
+ }
+
+ /*
+ * Unlike previous generations, Haswell's MPLL won't shut down if the
+ * requested frequency isn't supported. But we cannot reinitialize it.
+ * Another different thing: MPLL registers are 4-bit instead of 8-bit.
+ */
+
+ /** FIXME: Obtain current clock frequency if we want to skip this **/
+ //if (mchbar_read32(MC_BIOS_DATA) != 0)
+ // break;
+
+ uint32_t mc_bios_req = ctrl->multiplier;
+ if (ctrl->base_freq == 100) {
+ /* Use 100 MHz reference clock */
+ mc_bios_req |= BIT(4);
+ }
+ mc_bios_req |= BIT(31);
+ printk(RAM_DEBUG, "MC_BIOS_REQ = 0x%08x\n", mc_bios_req);
+ printk(BIOS_DEBUG, "MPLL busy... ");
+ mchbar_write32(MC_BIOS_REQ, mc_bios_req);
+
+ for (unsigned int i = 0; i <= 5000; i++) {
+ if (!(mchbar_read32(MC_BIOS_REQ) & BIT(31))) {
+ printk(BIOS_DEBUG, "done in %u us\n", i);
+ break;
+ }
+ udelay(1);
+ }
+ if (mchbar_read32(MC_BIOS_REQ) & BIT(31))
+ printk(BIOS_DEBUG, "did not lock\n");
+
+ /* Verify locked frequency */
+ const uint32_t mc_bios_data = mchbar_read32(MC_BIOS_DATA);
+ printk(RAM_DEBUG, "MC_BIOS_DATA = 0x%08x\n", mc_bios_data);
+ if ((mc_bios_data & 0xf) >= ctrl->multiplier)
+ break;
+
+ printk(BIOS_DEBUG, "Retrying at a lower frequency\n\n");
+ ctrl->tCK++;
+ }
+ if (!ctrl->mem_clock_mhz) {
+ printk(BIOS_ERR, "Could not program MPLL frequency\n");
+ return RAMINIT_STATUS_MPLL_INIT_FAILURE;
+ }
+ printk(BIOS_DEBUG, "MPLL frequency is set to: %u MHz ", ctrl->mem_clock_mhz);
+ ctrl->mem_clock_fs = 1000000000 / ctrl->mem_clock_mhz;
+ printk(BIOS_DEBUG, "(period: %u femtoseconds)\n", ctrl->mem_clock_fs);
+ ctrl->qclkps = ctrl->mem_clock_fs / 2000;
+ printk(BIOS_DEBUG, "Quadrature clock period: %u picoseconds\n", ctrl->qclkps);
+ return wait_for_first_rcomp();
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
new file mode 100644
index 0000000000..d45b608dd3
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+enum raminit_status wait_for_first_rcomp(void)
+{
+ struct stopwatch timer;
+ stopwatch_init_msecs_expire(&timer, 2000);
+ do {
+ if (mchbar_read32(RCOMP_TIMER) & BIT(16))
+ return RAMINIT_STATUS_SUCCESS;
+
+ } while (!stopwatch_expired(&timer));
+ printk(BIOS_ERR, "Timed out waiting for RCOMP to complete\n");
+ return RAMINIT_STATUS_POLL_TIMEOUT;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 19ec5859ac..bf745e943f 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -19,7 +19,8 @@ struct task_entry {
};
static const struct task_entry cold_boot[] = {
- { collect_spd_info, true, "PROCSPD", },
+ { collect_spd_info, true, "PROCSPD", },
+ { initialise_mpll, true, "INITMPLL", },
};
/* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 8078c9c386..15a1550424 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -24,6 +24,8 @@ enum raminit_status {
RAMINIT_STATUS_SUCCESS = 0,
RAMINIT_STATUS_NO_MEMORY_INSTALLED,
RAMINIT_STATUS_UNSUPPORTED_MEMORY,
+ RAMINIT_STATUS_MPLL_INIT_FAILURE,
+ RAMINIT_STATUS_POLL_TIMEOUT,
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
};
@@ -83,10 +85,19 @@ struct sysinfo {
uint8_t rankmap[NUM_CHANNELS];
uint8_t rank_mirrored[NUM_CHANNELS];
uint32_t channel_size_mb[NUM_CHANNELS];
+
+ uint8_t base_freq; /* Memory base frequency, either 100 or 133 MHz */
+ uint32_t multiplier;
+ uint32_t mem_clock_mhz;
+ uint32_t mem_clock_fs; /* Memory clock period in femtoseconds */
+ uint32_t qclkps; /* Quadrature clock period in picoseconds */
};
void raminit_main(enum raminit_boot_mode bootmode);
enum raminit_status collect_spd_info(struct sysinfo *ctrl);
+enum raminit_status initialise_mpll(struct sysinfo *ctrl);
+
+enum raminit_status wait_for_first_rcomp(void);
#endif
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 5610e7089a..45f8174995 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -13,6 +13,8 @@
#define MC_INIT_STATE_G 0x5030
#define MRC_REVISION 0x5034 /* MRC Revision */
+#define RCOMP_TIMER 0x5084
+
#define MC_LOCK 0x50fc /* Memory Controller Lock register */
#define GFXVTBAR 0x5400 /* Base address for IGD */
@@ -61,6 +63,7 @@
#define BIOS_RESET_CPL 0x5da8 /* 8-bit */
+#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */
#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */
#define SAPMCTL 0x5f00
--
2.39.5
@@ -0,0 +1,36 @@
From 7d94457ba0e2be10d781c5fd0659d895c9b558b1 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Thu, 26 Dec 2024 19:45:20 +0000
Subject: [PATCH 30/48] soc/intel/skylake: Don't compress FSP-S
Build systems like lbmk need to reproducibly insert
certain vendor files on release images.
Compression isn't always reproducible, and making it
so costs a lot more time than simply disabling compression.
With this change, the FSP-S module will now be inserted
without compression, which means that there will now be
about 40KB of extra space used in the flash.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/soc/intel/skylake/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 70c2a7643c..a2854923e7 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -14,7 +14,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
select DRAM_SUPPORT_DDR4
select DRIVERS_USB_ACPI
select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
- select FSP_COMPRESS_FSP_S_LZ4
+# select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
--
2.47.3
@@ -1,249 +0,0 @@
From 1dc22174b9b28b9ea9af59183ffd5d86d19a2721 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 16:29:55 +0200
Subject: [PATCH 31/51] haswell NRI: Post-process selected timings
Once the MPLL has been initialised, convert the timings from the SPD to
be in DCLKs, which is what the hardware expects. In addition, calculate
the values for tREFI and tXP.
Change-Id: Id02caf858f75b9e08016762b3aefda282b274386
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../haswell/native_raminit/lookup_timings.c | 62 +++++++++++
.../haswell/native_raminit/raminit_main.c | 1 +
.../haswell/native_raminit/raminit_native.h | 8 ++
.../haswell/native_raminit/spd_bitmunching.c | 100 ++++++++++++++++++
5 files changed, 172 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/lookup_timings.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index c125d84f0b..2769e0bbb4 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -1,5 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-or-later
+romstage-y += lookup_timings.c
romstage-y += init_mpll.c
romstage-y += io_comp_control.c
romstage-y += raminit_main.c
diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
new file mode 100644
index 0000000000..8b81c7c341
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+struct timing_lookup {
+ uint32_t clock;
+ uint32_t value;
+};
+
+static uint32_t lookup_timing(
+ const uint32_t mem_clock_mhz,
+ const struct timing_lookup *const lookup,
+ const size_t length)
+{
+ /* Fall back to the last index */
+ size_t i;
+ for (i = 0; i < length - 1; i++) {
+ /* Account for imprecise frequency values */
+ if ((mem_clock_mhz - 5) <= lookup[i].clock)
+ break;
+ }
+ return lookup[i].value;
+}
+
+static const uint32_t fmax = UINT32_MAX;
+
+uint8_t get_tCWL(const uint32_t mem_clock_mhz)
+{
+ const struct timing_lookup lut[] = {
+ { 400, 5 },
+ { 533, 6 },
+ { 666, 7 },
+ { 800, 8 },
+ { 933, 9 },
+ { 1066, 10 },
+ { 1200, 11 },
+ { fmax, 12 },
+ };
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+/* tREFI = 7800 ns * DDR MHz */
+uint32_t get_tREFI(const uint32_t mem_clock_mhz)
+{
+ return (mem_clock_mhz * 7800) / 1000;
+}
+
+uint32_t get_tXP(const uint32_t mem_clock_mhz)
+{
+ const struct timing_lookup lut[] = {
+ { 400, 3 },
+ { 666, 4 },
+ { 800, 5 },
+ { 933, 6 },
+ { 1066, 7 },
+ { fmax, 8 },
+ };
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index bf745e943f..2fea658415 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -21,6 +21,7 @@ struct task_entry {
static const struct task_entry cold_boot[] = {
{ collect_spd_info, true, "PROCSPD", },
{ initialise_mpll, true, "INITMPLL", },
+ { convert_timings, true, "CONVTIM", },
};
/* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 15a1550424..e0ebd3a2a7 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -79,6 +79,9 @@ struct sysinfo {
uint32_t tCWL;
uint32_t tCMD;
+ uint32_t tREFI;
+ uint32_t tXP;
+
uint8_t lanes; /* 8 or 9 */
uint8_t chanmap;
uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */
@@ -97,7 +100,12 @@ void raminit_main(enum raminit_boot_mode bootmode);
enum raminit_status collect_spd_info(struct sysinfo *ctrl);
enum raminit_status initialise_mpll(struct sysinfo *ctrl);
+enum raminit_status convert_timings(struct sysinfo *ctrl);
enum raminit_status wait_for_first_rcomp(void);
+uint8_t get_tCWL(uint32_t mem_clock_mhz);
+uint32_t get_tREFI(uint32_t mem_clock_mhz);
+uint32_t get_tXP(uint32_t mem_clock_mhz);
+
#endif
diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
index eff993800b..4f7fe46494 100644
--- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
@@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl)
get_spd_data(ctrl);
return find_common_spd_parameters(ctrl);
}
+
+#define MIN_CWL 5
+#define MAX_CWL 12
+
+/* Except for tCK, hardware expects all timing values in DCLKs, not nanoseconds */
+enum raminit_status convert_timings(struct sysinfo *ctrl)
+{
+ /*
+ * Obtain all required timing values, in DCLKs.
+ */
+
+ /* Convert primary timings from nanoseconds to DCLKs */
+ ctrl->tAA = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
+ ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK);
+ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
+ ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
+ ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK);
+ ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
+ ctrl->tRC = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK);
+ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
+ ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
+ ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
+ ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
+ ctrl->tCWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
+ ctrl->tCMD = DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK);
+
+ /* Constrain primary timings to hardware limits */
+ /** TODO: complain when clamping? **/
+ ctrl->tAA = clamp_u32(4, ctrl->tAA, 24);
+ ctrl->tWR = clamp_u32(5, ctrl->tWR, 16);
+ ctrl->tRCD = clamp_u32(4, ctrl->tRCD, 20);
+ ctrl->tRRD = clamp_u32(4, ctrl->tRRD, 65535);
+ ctrl->tRP = clamp_u32(4, ctrl->tRP, 15);
+ ctrl->tRAS = clamp_u32(10, ctrl->tRAS, 40);
+ ctrl->tRC = clamp_u32(1, ctrl->tRC, 4095);
+ ctrl->tRFC = clamp_u32(1, ctrl->tRFC, 511);
+ ctrl->tWTR = clamp_u32(4, ctrl->tWTR, 10);
+ ctrl->tRTP = clamp_u32(4, ctrl->tRTP, 15);
+ ctrl->tFAW = clamp_u32(10, ctrl->tFAW, 54);
+
+ /** TODO: Honor tREFI from XMP **/
+ ctrl->tREFI = get_tREFI(ctrl->mem_clock_mhz);
+ ctrl->tXP = get_tXP(ctrl->mem_clock_mhz);
+
+ /*
+ * Check some values, and adjust them if necessary.
+ */
+
+ /* If tWR cannot be written into DDR3 MR0, adjust it */
+ switch (ctrl->tWR) {
+ case 9:
+ case 11:
+ case 13:
+ case 15:
+ ctrl->tWR++;
+ }
+
+ /* If tCWL is not supported or unspecified, look up a reasonable default */
+ if (ctrl->tCWL < MIN_CWL || ctrl->tCWL > MAX_CWL)
+ ctrl->tCWL = get_tCWL(ctrl->mem_clock_mhz);
+
+ /* This is needed to support ODT properly on 2DPC */
+ if (ctrl->tAA - ctrl->tCWL > 4)
+ ctrl->tCWL = ctrl->tAA - 4;
+
+ /* If tCMD is invalid, use a guesstimate default */
+ if (!ctrl->tCMD) {
+ ctrl->tCMD = MAX(ctrl->dpc[0], ctrl->dpc[1]);
+ printk(RAM_DEBUG, "tCMD was zero, picking a guesstimate value\n");
+ }
+ ctrl->tCMD = clamp_u32(1, ctrl->tCMD, 3);
+
+ /*
+ * Print final timings.
+ */
+
+ /* tCK is special */
+ printk(BIOS_DEBUG, "Selected tCK : %u ps\n", ctrl->tCK * 1000 / 256);
+
+ /* Primary timings */
+ printk(BIOS_DEBUG, "Selected tAA : %uT\n", ctrl->tAA);
+ printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR);
+ printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD);
+ printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD);
+ printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP);
+ printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS);
+ printk(BIOS_DEBUG, "Selected tRC : %uT\n", ctrl->tRC);
+ printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC);
+ printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR);
+ printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP);
+ printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW);
+ printk(BIOS_DEBUG, "Selected tCWL : %uT\n", ctrl->tCWL);
+ printk(BIOS_DEBUG, "Selected tCMD : %uT\n", ctrl->tCMD);
+
+ /* Derived timings */
+ printk(BIOS_DEBUG, "Selected tREFI : %uT\n", ctrl->tREFI);
+ printk(BIOS_DEBUG, "Selected tXP : %uT\n", ctrl->tXP);
+
+ return RAMINIT_STATUS_SUCCESS;
+}
--
2.39.5
@@ -1,7 +1,7 @@
From 91c7d772f4803a94950b3224ccd11ffd162b4e36 Mon Sep 17 00:00:00 2001
From 8768e53f3b2ceb00ec0c8abf0fc0af03993820b1 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Wed, 18 Dec 2024 02:06:18 +0000
Subject: [PATCH 1/1] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
Subject: [PATCH 31/48] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
This is used by lbmk to know where a tb.bin file goes,
when extracting and padding TBT.bin from Lenovo ThunderBolt
@@ -74,5 +74,5 @@ index 2ffbaab85f..512b326381 100644
+
endif # VENDOR_LENOVO
--
2.39.5
2.47.3
@@ -0,0 +1,37 @@
From 579c60fd77517497eb18dfeca8d73cdca94c15da Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 21 Apr 2025 05:14:45 +0100
Subject: [PATCH 32/48] Conditional TBFW setting for kabylake thinkpads
Otherwise, other boards will define it, which
might trigger the vendor download script, and
lead to a non-zero exit.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index 512b326381..b2c7763198 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY
string
default MAINBOARD_PART_NUMBER
+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580
+
config LENOVO_TBFW_BIN
string "Lenovo ThunderBolt firmware bin file"
default ""
@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN
Just leave this blank if you don't care about this option. It's not
useful for every ThinkPad, only certain models.
+endif # BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580
+
endif # VENDOR_LENOVO
--
2.47.3
@@ -1,541 +0,0 @@
From 8f94c0428eea2145a97de943b093dee29001c4f9 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 20:59:58 +0200
Subject: [PATCH 33/51] haswell NRI: Add timings/refresh programming
Program the registers with timing and refresh parameters.
Change-Id: Id2ea339d2c9ea8b56c71d6e88ec76949653ff5c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../haswell/native_raminit/lookup_timings.c | 102 ++++++++
.../haswell/native_raminit/raminit_native.h | 14 ++
.../haswell/native_raminit/reg_structs.h | 93 +++++++
.../haswell/native_raminit/timings_refresh.c | 233 +++++++++++++++++-
.../intel/haswell/registers/mchbar.h | 12 +
5 files changed, 452 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
index 8b81c7c341..b8d6c1ef40 100644
--- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
@@ -60,3 +60,105 @@ uint32_t get_tXP(const uint32_t mem_clock_mhz)
};
return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
}
+
+static uint32_t get_lpddr_tCKE(const uint32_t mem_clock_mhz)
+{
+ const struct timing_lookup lut[] = {
+ { 533, 4 },
+ { 666, 5 },
+ { fmax, 6 },
+ };
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+static uint32_t get_ddr_tCKE(const uint32_t mem_clock_mhz)
+{
+ const struct timing_lookup lut[] = {
+ { 533, 3 },
+ { 800, 4 },
+ { 933, 5 },
+ { 1200, 6 },
+ { fmax, 7 },
+ };
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tCKE(const uint32_t mem_clock_mhz, const bool lpddr)
+{
+ return lpddr ? get_lpddr_tCKE(mem_clock_mhz) : get_ddr_tCKE(mem_clock_mhz);
+}
+
+uint32_t get_tXPDLL(const uint32_t mem_clock_mhz)
+{
+ const struct timing_lookup lut[] = {
+ { 400, 10 },
+ { 533, 13 },
+ { 666, 16 },
+ { 800, 20 },
+ { 933, 23 },
+ { 1066, 26 },
+ { 1200, 29 },
+ { fmax, 32 },
+ };
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tAONPD(const uint32_t mem_clock_mhz)
+{
+ const struct timing_lookup lut[] = {
+ { 400, 4 },
+ { 533, 5 },
+ { 666, 6 },
+ { 800, 7 }, /* SNB had 8 */
+ { 933, 8 },
+ { 1066, 10 },
+ { 1200, 11 },
+ { fmax, 12 },
+ };
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tMOD(const uint32_t mem_clock_mhz)
+{
+ const struct timing_lookup lut[] = {
+ { 800, 12 },
+ { 933, 14 },
+ { 1066, 16 },
+ { 1200, 18 },
+ { fmax, 20 },
+ };
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tXS_offset(const uint32_t mem_clock_mhz)
+{
+ return DIV_ROUND_UP(mem_clock_mhz, 100);
+}
+
+static uint32_t get_lpddr_tZQOPER(const uint32_t mem_clock_mhz)
+{
+ return (mem_clock_mhz * 360) / 1000;
+}
+
+static uint32_t get_ddr_tZQOPER(const uint32_t mem_clock_mhz)
+{
+ const struct timing_lookup lut[] = {
+ { 800, 256 },
+ { 933, 299 },
+ { 1066, 342 },
+ { 1200, 384 },
+ { fmax, 427 },
+ };
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+/* tZQOPER defines the period required for ZQCL after SR exit */
+uint32_t get_tZQOPER(const uint32_t mem_clock_mhz, const bool lpddr)
+{
+ return lpddr ? get_lpddr_tZQOPER(mem_clock_mhz) : get_ddr_tZQOPER(mem_clock_mhz);
+}
+
+uint32_t get_tZQCS(const uint32_t mem_clock_mhz, const bool lpddr)
+{
+ return DIV_ROUND_UP(get_tZQOPER(mem_clock_mhz, lpddr), 4);
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index fffa6d5450..5915a2bab0 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -156,6 +156,12 @@ struct sysinfo {
uint8_t cke_cmd_pi_code[NUM_CHANNELS][NUM_GROUPS];
uint8_t cmd_north_pi_code[NUM_CHANNELS][NUM_GROUPS];
uint8_t cmd_south_pi_code[NUM_CHANNELS][NUM_GROUPS];
+
+ union tc_bank_reg tc_bank[NUM_CHANNELS];
+ union tc_bank_rank_a_reg tc_bankrank_a[NUM_CHANNELS];
+ union tc_bank_rank_b_reg tc_bankrank_b[NUM_CHANNELS];
+ union tc_bank_rank_c_reg tc_bankrank_c[NUM_CHANNELS];
+ union tc_bank_rank_d_reg tc_bankrank_d[NUM_CHANNELS];
};
static inline bool is_hsw_ult(void)
@@ -201,6 +207,14 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
void configure_timings(struct sysinfo *ctrl);
void configure_refresh(struct sysinfo *ctrl);
+uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
+uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
+uint32_t get_tAONPD(uint32_t mem_clock_mhz);
+uint32_t get_tMOD(uint32_t mem_clock_mhz);
+uint32_t get_tXS_offset(uint32_t mem_clock_mhz);
+uint32_t get_tZQOPER(uint32_t mem_clock_mhz, bool lpddr);
+uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr);
+
enum raminit_status wait_for_first_rcomp(void);
uint8_t get_rx_bias(const struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index d11cda4b3d..70487e1640 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -335,6 +335,99 @@ union mcscheds_cbit_reg {
uint32_t raw;
};
+union tc_bank_reg {
+ struct __packed {
+ uint32_t tRCD : 5; // Bits 4:0
+ uint32_t tRP : 5; // Bits 9:5
+ uint32_t tRAS : 6; // Bits 15:10
+ uint32_t tRDPRE : 4; // Bits 19:16
+ uint32_t tWRPRE : 6; // Bits 25:20
+ uint32_t tRRD : 4; // Bits 29:26
+ uint32_t tRPab_ext : 2; // Bits 31:30
+ };
+ uint32_t raw;
+};
+
+union tc_bank_rank_a_reg {
+ struct __packed {
+ uint32_t tCKE : 4; // Bits 3:0
+ uint32_t tFAW : 8; // Bits 11:4
+ uint32_t tRDRD_sr : 3; // Bits 14:12
+ uint32_t tRDRD_dr : 4; // Bits 18:15
+ uint32_t tRDRD_dd : 4; // Bits 22:19
+ uint32_t tRDPDEN : 5; // Bits 27:23
+ uint32_t : 1; // Bits 28:28
+ uint32_t cmd_3st_dis : 1; // Bits 29:29
+ uint32_t cmd_stretch : 2; // Bits 31:30
+ };
+ uint32_t raw;
+};
+
+union tc_bank_rank_b_reg {
+ struct __packed {
+ uint32_t tWRRD_sr : 6; // Bits 5:0
+ uint32_t tWRRD_dr : 4; // Bits 9:6
+ uint32_t tWRRD_dd : 4; // Bits 13:10
+ uint32_t tWRWR_sr : 3; // Bits 16:14
+ uint32_t tWRWR_dr : 4; // Bits 20:17
+ uint32_t tWRWR_dd : 4; // Bits 24:21
+ uint32_t tWRPDEN : 6; // Bits 30:25
+ uint32_t dec_wrd : 1; // Bits 31:31
+ };
+ uint32_t raw;
+};
+
+union tc_bank_rank_c_reg {
+ struct __packed {
+ uint32_t tXPDLL : 6; // Bits 5:0
+ uint32_t tXP : 4; // Bits 9:6
+ uint32_t tAONPD : 4; // Bits 13:10
+ uint32_t tRDWR_sr : 5; // Bits 18:14
+ uint32_t tRDWR_dr : 5; // Bits 23:19
+ uint32_t tRDWR_dd : 5; // Bits 28:24
+ uint32_t : 3; // Bits 31:29
+ };
+ uint32_t raw;
+};
+
+/* NOTE: Non-ULT only implements the lower 21 bits (odt_write_delay is 2 bits) */
+union tc_bank_rank_d_reg {
+ struct __packed {
+ uint32_t tAA : 5; // Bits 4:0
+ uint32_t tCWL : 5; // Bits 9:5
+ uint32_t tCPDED : 2; // Bits 11:10
+ uint32_t tPRPDEN : 2; // Bits 13:12
+ uint32_t odt_read_delay : 3; // Bits 16:14
+ uint32_t odt_read_duration : 2; // Bits 18:17
+ uint32_t odt_write_duration : 3; // Bits 21:19
+ uint32_t odt_write_delay : 3; // Bits 24:22
+ uint32_t odt_always_rank_0 : 1; // Bits 25:25
+ uint32_t cmd_delay : 2; // Bits 27:26
+ uint32_t : 4; // Bits 31:28
+ };
+ uint32_t raw;
+};
+
+union tc_rftp_reg {
+ struct __packed {
+ uint32_t tREFI : 16; // Bits 15:0
+ uint32_t tRFC : 9; // Bits 24:16
+ uint32_t tREFIx9 : 7; // Bits 31:25
+ };
+ uint32_t raw;
+};
+
+union tc_srftp_reg {
+ struct __packed {
+ uint32_t tXSDLL : 12; // Bits 11:0
+ uint32_t tXS_offset : 4; // Bits 15:12
+ uint32_t tZQOPER : 10; // Bits 25:16
+ uint32_t : 2; // Bits 27:26
+ uint32_t tMOD : 4; // Bits 31:28
+ };
+ uint32_t raw;
+};
+
union mcmain_command_rate_limit_reg {
struct __packed {
uint32_t enable_cmd_limit : 1; // Bits 0:0
diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
index a9d960f31b..54fee0121d 100644
--- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
@@ -1,13 +1,242 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <assert.h>
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+
#include "raminit_native.h"
+#define BL 8 /* Burst length */
+#define tCCD 4
+#define tRPRE 1
+#define tWPRE 1
+#define tDLLK 512
+
+static bool is_sodimm(const enum spd_dimm_type_ddr3 type)
+{
+ return type == SPD_DDR3_DIMM_TYPE_SO_DIMM || type == SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM;
+}
+
+static uint8_t get_odt_stretch(const struct sysinfo *const ctrl)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ /* Only stretch with 2 DIMMs per channel */
+ if (ctrl->dpc[channel] != 2)
+ continue;
+
+ const struct raminit_dimm_info *dimms = ctrl->dimms[channel];
+
+ /* Only stretch when using SO-DIMMs */
+ if (!is_sodimm(dimms[0].data.dimm_type) || !is_sodimm(dimms[1].data.dimm_type))
+ continue;
+
+ /* Only stretch with mismatched card types */
+ if (dimms[0].data.reference_card == dimms[1].data.reference_card)
+ continue;
+
+ /* Stretch if one SO-DIMM is card F */
+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+ if (dimms[slot].data.reference_card == 5)
+ return 1;
+ }
+ }
+ return 0;
+}
+
+static union tc_bank_reg make_tc_bank(struct sysinfo *const ctrl)
+{
+ return (union tc_bank_reg) {
+ .tRCD = ctrl->tRCD,
+ .tRP = ctrl->tRP,
+ .tRAS = ctrl->tRAS,
+ .tRDPRE = ctrl->tRTP,
+ .tWRPRE = 4 + ctrl->tCWL + ctrl->tWR,
+ .tRRD = ctrl->tRRD,
+ .tRPab_ext = 0, /** TODO: For LPDDR, this is ctrl->tRPab - ctrl->tRP **/
+ };
+}
+
+static union tc_bank_rank_a_reg make_tc_bankrank_a(struct sysinfo *ctrl, uint8_t odt_stretch)
+{
+ /* Use 3N mode for DDR during training, but always use 1N mode for LPDDR */
+ const uint32_t tCMD = ctrl->lpddr ? 0 : 3;
+ const uint32_t tRDRD_drdd = BL / 2 + 1 + tRPRE + odt_stretch + !!ctrl->lpddr;
+
+ return (union tc_bank_rank_a_reg) {
+ .tCKE = get_tCKE(ctrl->mem_clock_mhz, ctrl->lpddr),
+ .tFAW = ctrl->tFAW,
+ .tRDRD_sr = tCCD,
+ .tRDRD_dr = tRDRD_drdd,
+ .tRDRD_dd = tRDRD_drdd,
+ .tRDPDEN = ctrl->tAA + BL / 2 + 1,
+ .cmd_3st_dis = 1, /* Disable command tri-state before training */
+ .cmd_stretch = tCMD,
+ };
+}
+
+static union tc_bank_rank_b_reg make_tc_bankrank_b(struct sysinfo *const ctrl)
+{
+ const uint8_t tWRRD_drdd = ctrl->tCWL - ctrl->tAA + BL / 2 + 2 + tRPRE;
+ const uint8_t tWRWR_drdd = BL / 2 + 2 + tWPRE;
+
+ return (union tc_bank_rank_b_reg) {
+ .tWRRD_sr = tCCD + ctrl->tCWL + ctrl->tWTR + 2,
+ .tWRRD_dr = ctrl->lpddr ? 8 : tWRRD_drdd,
+ .tWRRD_dd = ctrl->lpddr ? 8 : tWRRD_drdd,
+ .tWRWR_sr = tCCD,
+ .tWRWR_dr = tWRWR_drdd,
+ .tWRWR_dd = tWRWR_drdd,
+ .tWRPDEN = ctrl->tWR + ctrl->tCWL + BL / 2,
+ .dec_wrd = ctrl->tCWL >= 6,
+ };
+}
+
+static uint32_t get_tRDWR_sr(const struct sysinfo *ctrl)
+{
+ if (ctrl->lpddr) {
+ const uint32_t tdqsck_max = DIV_ROUND_UP(5500, ctrl->qclkps * 2);
+ return ctrl->tAA - ctrl->tCWL + tCCD + tWPRE + tdqsck_max + 1;
+ } else {
+ const bool fast_clock = ctrl->mem_clock_mhz > 666;
+ return ctrl->tAA - ctrl->tCWL + tCCD + tWPRE + 2 + fast_clock;
+ }
+}
+
+static union tc_bank_rank_c_reg make_tc_bankrank_c(struct sysinfo *ctrl, uint8_t odt_stretch)
+{
+ const uint32_t tRDWR_sr = get_tRDWR_sr(ctrl);
+ const uint32_t tRDWR_drdd = tRDWR_sr + odt_stretch;
+
+ return (union tc_bank_rank_c_reg) {
+ .tXPDLL = get_tXPDLL(ctrl->mem_clock_mhz),
+ .tXP = MAX(ctrl->tXP, 7), /* Use a higher tXP for training */
+ .tAONPD = get_tAONPD(ctrl->mem_clock_mhz),
+ .tRDWR_sr = tRDWR_sr,
+ .tRDWR_dr = tRDWR_drdd,
+ .tRDWR_dd = tRDWR_drdd,
+ };
+}
+
+static union tc_bank_rank_d_reg make_tc_bankrank_d(struct sysinfo *ctrl, uint8_t odt_stretch)
+{
+ const uint32_t odt_rd_delay = ctrl->tAA - ctrl->tCWL;
+ if (!ctrl->lpddr) {
+ return (union tc_bank_rank_d_reg) {
+ .tAA = ctrl->tAA,
+ .tCWL = ctrl->tCWL,
+ .tCPDED = 1,
+ .tPRPDEN = 1,
+ .odt_read_delay = odt_rd_delay,
+ .odt_read_duration = odt_stretch,
+ };
+ }
+
+ /* tCWL has 1 extra clock because of tDQSS, subtract it here */
+ const uint32_t tCWL_lpddr = ctrl->tCWL - 1;
+ const uint32_t odt_wr_delay = tCWL_lpddr + DIV_ROUND_UP(3500, ctrl->qclkps * 2);
+ const uint32_t odt_wr_duration = DIV_ROUND_UP(3500 - 1750, ctrl->qclkps * 2) + 1;
+
+ return (union tc_bank_rank_d_reg) {
+ .tAA = ctrl->tAA,
+ .tCWL = tCWL_lpddr,
+ .tCPDED = 2, /* Required by JEDEC LPDDR3 spec */
+ .tPRPDEN = 1,
+ .odt_read_delay = odt_rd_delay,
+ .odt_read_duration = odt_stretch,
+ .odt_write_delay = odt_wr_delay,
+ .odt_write_duration = odt_wr_duration,
+ .odt_always_rank_0 = ctrl->lpddr_dram_odt
+ };
+}
+
+/* ZQCS period values, in (tREFI * 128) units */
+#define ZQCS_PERIOD_DDR3 128 /* tREFI * 128 = 7.8 us * 128 = 1ms */
+#define ZQCS_PERIOD_LPDDR3 256 /* tREFI * 128 = 3.9 us * 128 = 0.5ms */
+
+static uint32_t make_tc_zqcal(const struct sysinfo *const ctrl)
+{
+ const uint32_t zqcs_period = ctrl->lpddr ? ZQCS_PERIOD_LPDDR3 : ZQCS_PERIOD_DDR3;
+ const uint32_t tZQCS = get_tZQCS(ctrl->mem_clock_mhz, ctrl->lpddr);
+ return tZQCS << (is_hsw_ult() ? 10 : 8) | zqcs_period;
+}
+
+static union tc_rftp_reg make_tc_rftp(const struct sysinfo *const ctrl)
+{
+ /*
+ * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow
+ * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024.
+ */
+ return (union tc_rftp_reg) {
+ .tREFI = ctrl->tREFI,
+ .tRFC = ctrl->tRFC,
+ .tREFIx9 = ctrl->tREFI * 89 / 10240,
+ };
+}
+
+static union tc_srftp_reg make_tc_srftp(const struct sysinfo *const ctrl)
+{
+ return (union tc_srftp_reg) {
+ .tXSDLL = tDLLK,
+ .tXS_offset = get_tXS_offset(ctrl->mem_clock_mhz),
+ .tZQOPER = get_tZQOPER(ctrl->mem_clock_mhz, ctrl->lpddr),
+ .tMOD = get_tMOD(ctrl->mem_clock_mhz) - 8,
+ };
+}
+
void configure_timings(struct sysinfo *ctrl)
{
- /** TODO: Stub **/
+ if (ctrl->lpddr)
+ die("%s: Missing support for LPDDR\n", __func__);
+
+ const uint8_t odt_stretch = get_odt_stretch(ctrl);
+ const union tc_bank_reg tc_bank = make_tc_bank(ctrl);
+ const union tc_bank_rank_a_reg tc_bank_rank_a = make_tc_bankrank_a(ctrl, odt_stretch);
+ const union tc_bank_rank_b_reg tc_bank_rank_b = make_tc_bankrank_b(ctrl);
+ const union tc_bank_rank_c_reg tc_bank_rank_c = make_tc_bankrank_c(ctrl, odt_stretch);
+ const union tc_bank_rank_d_reg tc_bank_rank_d = make_tc_bankrank_d(ctrl, odt_stretch);
+
+ const uint8_t wr_delay = tc_bank_rank_b.dec_wrd + 1;
+ uint8_t sc_wr_add_delay = 0;
+ sc_wr_add_delay |= wr_delay << 0;
+ sc_wr_add_delay |= wr_delay << 2;
+ sc_wr_add_delay |= wr_delay << 4;
+ sc_wr_add_delay |= wr_delay << 6;
+
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ ctrl->tc_bank[channel] = tc_bank;
+ ctrl->tc_bankrank_a[channel] = tc_bank_rank_a;
+ ctrl->tc_bankrank_b[channel] = tc_bank_rank_b;
+ ctrl->tc_bankrank_c[channel] = tc_bank_rank_c;
+ ctrl->tc_bankrank_d[channel] = tc_bank_rank_d;
+
+ mchbar_write32(TC_BANK_ch(channel), ctrl->tc_bank[channel].raw);
+ mchbar_write32(TC_BANK_RANK_A_ch(channel), ctrl->tc_bankrank_a[channel].raw);
+ mchbar_write32(TC_BANK_RANK_B_ch(channel), ctrl->tc_bankrank_b[channel].raw);
+ mchbar_write32(TC_BANK_RANK_C_ch(channel), ctrl->tc_bankrank_c[channel].raw);
+ mchbar_write32(TC_BANK_RANK_D_ch(channel), ctrl->tc_bankrank_d[channel].raw);
+ mchbar_write8(SC_WR_ADD_DELAY_ch(channel), sc_wr_add_delay);
+ }
}
void configure_refresh(struct sysinfo *ctrl)
{
- /** TODO: Stub **/
+ const union tc_srftp_reg tc_srftp = make_tc_srftp(ctrl);
+ const union tc_rftp_reg tc_rftp = make_tc_rftp(ctrl);
+ const uint32_t tc_zqcal = make_tc_zqcal(ctrl);
+
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ mchbar_setbits32(TC_RFP_ch(channel), 0xff);
+ mchbar_write32(TC_RFTP_ch(channel), tc_rftp.raw);
+ mchbar_write32(TC_SRFTP_ch(channel), tc_srftp.raw);
+ mchbar_write32(TC_ZQCAL_ch(channel), tc_zqcal);
+ }
}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 4c3f399b5d..2acc5cbbc8 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -86,9 +86,21 @@
#define DDR_COMP_VSSHI_CONTROL 0x3a24
/* MCMAIN per-channel */
+#define TC_BANK_ch(ch) _MCMAIN_C(0x4000, ch)
+#define TC_BANK_RANK_A_ch(ch) _MCMAIN_C(0x4004, ch)
+#define TC_BANK_RANK_B_ch(ch) _MCMAIN_C(0x4008, ch)
+#define TC_BANK_RANK_C_ch(ch) _MCMAIN_C(0x400c, ch)
#define COMMAND_RATE_LIMIT_ch(ch) _MCMAIN_C(0x4010, ch)
+#define TC_BANK_RANK_D_ch(ch) _MCMAIN_C(0x4014, ch)
+#define SC_ROUNDT_LAT_ch(ch) _MCMAIN_C(0x4024, ch)
+#define SC_WR_ADD_DELAY_ch(ch) _MCMAIN_C(0x40d0, ch)
+
+#define TC_ZQCAL_ch(ch) _MCMAIN_C(0x4290, ch)
+#define TC_RFP_ch(ch) _MCMAIN_C(0x4294, ch)
+#define TC_RFTP_ch(ch) _MCMAIN_C(0x4298, ch)
#define MC_INIT_STATE_ch(ch) _MCMAIN_C(0x42a0, ch)
+#define TC_SRFTP_ch(ch) _MCMAIN_C(0x42a4, ch)
/* MCMAIN broadcast */
#define MCSCHEDS_CBIT 0x4c20
--
2.39.5
@@ -0,0 +1,30 @@
From 23d8a97ff213f744b4e6333d92fc90e9ea97e879 Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Sat, 27 Sep 2025 23:30:46 +0300
Subject: [PATCH 33/48] soc/intel/alderlake: Disable
MRC_CACHE_USING_MRC_VERSION
There's some issue with building against the FSP headers in src/vendorcode.
Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing
from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force.
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
---
src/soc/intel/alderlake/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 34c9baf544..e0ab6b10fd 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE
select INTEL_GMA_VERSION_2
select INTEL_TXT_LIB
select MP_SERVICES_PPI_V2
- select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO
select MRC_SETTINGS_PROTECT
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_2
--
2.47.3
@@ -0,0 +1,76 @@
From e2e070ab1f080c0ae59c43131faa57f3499fd813 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 28 Sep 2025 03:17:50 +0100
Subject: [PATCH 34/48] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks)
if you pass -k (keep fptr modules), don't use -r, don't
use -t, you can essentially just use me_cleaner to
extract a ME image without changing it. this is useful
when for example, you just want to set the HAP bit.
however, me_cleaner still performs a FPTR check.
on some newer ME versions, it's always invalid according
to me_cleaner, because for example it doesn't handle
ME16 very well yet.
this patch adds an option to override the FPTR check
either pass -p or --pass-fptr
NOTE: we probably won't use this on coreboot's me_cleaner,
which is the corna version. we only need it on the newer
me_cleaner versions for e.g. ME16, on certain setups.
still, it's best to have the patch here too, just in case.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/me_cleaner/me_cleaner.py | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py
index fae5e56732..228bac899f 100755
--- a/util/me_cleaner/me_cleaner.py
+++ b/util/me_cleaner/me_cleaner.py
@@ -246,8 +246,10 @@ def check_partition_signature(f, offset):
return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME
-def print_check_partition_signature(f, offset):
- if check_partition_signature(f, offset):
+def print_check_partition_signature(f, offset, pass_fptr):
+ if pass_fptr:
+ print("Skipping FPTR checks because the user told us to")
+ elif check_partition_signature(f, offset):
print("VALID")
else:
print("INVALID!!")
@@ -486,6 +488,8 @@ if __name__ == "__main__":
"--extract-me)", action="store_true")
parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR "
"modules, even when possible", action="store_true")
+ parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks"
+ "regardless of other operations", action="store_true")
bw_list.add_argument("-w", "--whitelist", metavar="whitelist",
help="Comma separated list of additional partitions "
"to keep in the final image. This can be used to "
@@ -871,12 +875,14 @@ if __name__ == "__main__":
print("Checking the FTPR RSA signature of the extracted ME "
"image... ", end="")
print_check_partition_signature(mef_copy,
- ftpr_offset + ftpr_mn2_offset)
+ ftpr_offset + ftpr_mn2_offset,
+ args.pass_fptr)
mef_copy.close()
if not me6_ignition:
print("Checking the FTPR RSA signature... ", end="")
- print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset)
+ print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset,
+ args.pass_fptr)
f.close()
--
2.47.3
@@ -1,263 +0,0 @@
From ded914f236f76715aa43cb439a3de7df9a3dfa11 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 21:24:50 +0200
Subject: [PATCH 34/51] haswell NRI: Program memory map
This is very similar to Sandy/Ivy Bridge, except that there's several
registers to program in GDXCBAR. One of these GDXCBAR registers has a
lock bit that must be set in order for the memory controller to allow
normal access to DRAM. And it took me four months to realize this one
bit was the only reason why native raminit did not work.
Change-Id: I3af73a018a7ba948701a542e661e7fefd57591fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../intel/haswell/native_raminit/memory_map.c | 183 ++++++++++++++++++
.../haswell/native_raminit/raminit_main.c | 1 +
.../haswell/native_raminit/raminit_native.h | 1 +
.../intel/haswell/registers/host_bridge.h | 2 +
5 files changed, 188 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/memory_map.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index fc55277a65..37d527e972 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -4,6 +4,7 @@ romstage-y += configure_mc.c
romstage-y += lookup_timings.c
romstage-y += init_mpll.c
romstage-y += io_comp_control.c
+romstage-y += memory_map.c
romstage-y += raminit_main.c
romstage-y += raminit_native.c
romstage-y += spd_bitmunching.c
diff --git a/src/northbridge/intel/haswell/native_raminit/memory_map.c b/src/northbridge/intel/haswell/native_raminit/memory_map.c
new file mode 100644
index 0000000000..e3aded2b37
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/memory_map.c
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <southbridge/intel/lynxpoint/me.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+/* GDXCBAR */
+#define MPCOHTRK_GDXC_MOT_ADDRESS_LO 0x10
+#define MPCOHTRK_GDXC_MOT_ADDRESS_HI 0x14
+#define MPCOHTRK_GDXC_MOT_REGION 0x18
+
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_LO 0x20
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_HI 0x24
+#define MPCOHTRK_GDXC_OCLA_REGION 0x28
+
+/* This lock bit made me lose what little sanity I had left. - Angel Pons */
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK BIT(2)
+
+static inline uint32_t gdxcbar_read32(const uintptr_t offset)
+{
+ return read32p((mchbar_read32(GDXCBAR) & ~1) + offset);
+}
+
+static inline void gdxcbar_write32(const uintptr_t offset, const uint32_t value)
+{
+ write32p((mchbar_read32(GDXCBAR) & ~1) + offset, value);
+}
+
+static inline void gdxcbar_clrsetbits32(const uintptr_t offset, uint32_t clear, uint32_t set)
+{
+ const uintptr_t address = (mchbar_read32(GDXCBAR) & ~1) + offset;
+ clrsetbits32((void *)address, clear, set);
+}
+
+#define gdxcbar_setbits32(offset, set) gdxcbar_clrsetbits32(offset, 0, set)
+#define gdxcbar_clrbits32(offset, clear) gdxcbar_clrsetbits32(offset, clear, 0)
+
+/* All values stored in here (except the bool) are specified in MiB */
+struct memory_map_data {
+ uint32_t dpr_size;
+ uint32_t tseg_size;
+ uint32_t gtt_size;
+ uint32_t gms_size;
+ uint32_t me_stolen_size;
+ uint32_t mmio_size;
+ uint32_t touud;
+ uint32_t remaplimit;
+ uint32_t remapbase;
+ uint32_t tom;
+ uint32_t tom_minus_me;
+ uint32_t tolud;
+ uint32_t bdsm_base;
+ uint32_t gtt_base;
+ uint32_t tseg_base;
+ bool reclaim_possible;
+};
+
+static void compute_memory_map(struct memory_map_data *map)
+{
+ map->tom_minus_me = map->tom - map->me_stolen_size;
+
+ /*
+ * MMIO size will actually be slightly smaller than computed,
+ * but matches what MRC does and is more MTRR-friendly given
+ * that TSEG is treated as WB, but SMRR makes TSEG UC anyway.
+ */
+ const uint32_t mmio_size = MIN(map->tom_minus_me, 4096) / 2;
+ map->gtt_base = ALIGN_DOWN(mmio_size, map->tseg_size);
+ map->tseg_base = map->gtt_base - map->tseg_size;
+ map->bdsm_base = map->gtt_base + map->gtt_size;
+ map->tolud = map->bdsm_base + map->gms_size;
+ map->reclaim_possible = map->tom_minus_me > map->tolud;
+
+ if (map->reclaim_possible) {
+ map->remapbase = MAX(4096, map->tom_minus_me);
+ map->touud = MIN(4096, map->tom_minus_me) + map->remapbase - map->tolud;
+ map->remaplimit = map->touud - 1;
+ } else {
+ map->remapbase = 0;
+ map->remaplimit = 0;
+ map->touud = map->tom_minus_me;
+ }
+}
+
+static void display_memory_map(const struct memory_map_data *map)
+{
+ if (!CONFIG(DEBUG_RAM_SETUP))
+ return;
+
+ printk(BIOS_DEBUG, "============ MEMORY MAP ============\n");
+ printk(BIOS_DEBUG, "\n");
+ printk(BIOS_DEBUG, "dpr_size = %u MiB\n", map->dpr_size);
+ printk(BIOS_DEBUG, "tseg_size = %u MiB\n", map->tseg_size);
+ printk(BIOS_DEBUG, "gtt_size = %u MiB\n", map->gtt_size);
+ printk(BIOS_DEBUG, "gms_size = %u MiB\n", map->gms_size);
+ printk(BIOS_DEBUG, "me_stolen_size = %u MiB\n", map->me_stolen_size);
+ printk(BIOS_DEBUG, "\n");
+ printk(BIOS_DEBUG, "touud = %u MiB\n", map->touud);
+ printk(BIOS_DEBUG, "remaplimit = %u MiB\n", map->remaplimit);
+ printk(BIOS_DEBUG, "remapbase = %u MiB\n", map->remapbase);
+ printk(BIOS_DEBUG, "tom = %u MiB\n", map->tom);
+ printk(BIOS_DEBUG, "tom_minus_me = %u MiB\n", map->tom_minus_me);
+ printk(BIOS_DEBUG, "tolud = %u MiB\n", map->tolud);
+ printk(BIOS_DEBUG, "bdsm_base = %u MiB\n", map->bdsm_base);
+ printk(BIOS_DEBUG, "gtt_base = %u MiB\n", map->gtt_base);
+ printk(BIOS_DEBUG, "tseg_base = %u MiB\n", map->tseg_base);
+ printk(BIOS_DEBUG, "\n");
+ printk(BIOS_DEBUG, "reclaim_possible = %s\n", map->reclaim_possible ? "Yes" : "No");
+}
+
+static void map_write_reg64(const uint16_t reg, const uint64_t size)
+{
+ const uint64_t value = size << 20;
+ pci_write_config32(HOST_BRIDGE, reg + 4, value >> 32);
+ pci_write_config32(HOST_BRIDGE, reg + 0, value >> 0);
+}
+
+static void map_write_reg32(const uint16_t reg, const uint32_t size)
+{
+ const uint32_t value = size << 20;
+ pci_write_config32(HOST_BRIDGE, reg, value);
+}
+
+static void program_memory_map(const struct memory_map_data *map)
+{
+ map_write_reg64(TOUUD, map->touud);
+ map_write_reg64(TOM, map->tom);
+ if (map->reclaim_possible) {
+ map_write_reg64(REMAPBASE, map->remapbase);
+ map_write_reg64(REMAPLIMIT, map->remaplimit);
+ }
+ if (map->me_stolen_size) {
+ map_write_reg64(MESEG_LIMIT, 0x80000 - map->me_stolen_size);
+ map_write_reg64(MESEG_BASE, map->tom_minus_me);
+ pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, ME_STLEN_EN);
+ }
+ map_write_reg32(TOLUD, map->tolud);
+ map_write_reg32(BDSM, map->bdsm_base);
+ map_write_reg32(BGSM, map->gtt_base);
+ map_write_reg32(TSEG, map->tseg_base);
+
+ const uint32_t dpr_reg = map->tseg_base << 20 | map->dpr_size << 4;
+ pci_write_config32(HOST_BRIDGE, DPR, dpr_reg);
+
+ const uint16_t gfx_stolen_size = GGC_IGD_MEM_IN_32MB_UNITS(map->gms_size / 32);
+ const uint16_t ggc = map->gtt_size << 8 | gfx_stolen_size;
+ pci_write_config16(HOST_BRIDGE, GGC, ggc);
+
+ /** TODO: Do not hardcode these? GDXC has weird alignment requirements, though. **/
+ gdxcbar_write32(MPCOHTRK_GDXC_MOT_ADDRESS_LO, 0);
+ gdxcbar_write32(MPCOHTRK_GDXC_MOT_ADDRESS_HI, 0);
+ gdxcbar_write32(MPCOHTRK_GDXC_MOT_REGION, 0);
+
+ gdxcbar_write32(MPCOHTRK_GDXC_OCLA_ADDRESS_LO, 0);
+ gdxcbar_write32(MPCOHTRK_GDXC_OCLA_ADDRESS_HI, 0);
+ gdxcbar_write32(MPCOHTRK_GDXC_OCLA_REGION, 0);
+
+ gdxcbar_setbits32(MPCOHTRK_GDXC_OCLA_ADDRESS_HI, MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK);
+}
+
+enum raminit_status configure_memory_map(struct sysinfo *ctrl)
+{
+ struct memory_map_data memory_map = {
+ .tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1],
+ .dpr_size = CONFIG_INTEL_TXT_DPR_SIZE,
+ .tseg_size = CONFIG_SMM_TSEG_SIZE >> 20,
+ .me_stolen_size = intel_early_me_uma_size(),
+ };
+ /** FIXME: MRC hardcodes iGPU parameters, but we should not **/
+ const bool igpu_on = pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN;
+ if (CONFIG(ONBOARD_VGA_IS_PRIMARY) || igpu_on) {
+ memory_map.gtt_size = 2;
+ memory_map.gms_size = 64;
+ pci_or_config32(HOST_BRIDGE, DEVEN, DEVEN_D2EN);
+ }
+ compute_memory_map(&memory_map);
+ display_memory_map(&memory_map);
+ program_memory_map(&memory_map);
+ return 0;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index fcc981ad04..559dfc3a4e 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -23,6 +23,7 @@ static const struct task_entry cold_boot[] = {
{ initialise_mpll, true, "INITMPLL", },
{ convert_timings, true, "CONVTIM", },
{ configure_mc, true, "CONFMC", },
+ { configure_memory_map, true, "MEMMAP", },
};
/* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 5915a2bab0..8f937c4ccd 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -203,6 +203,7 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl);
enum raminit_status initialise_mpll(struct sysinfo *ctrl);
enum raminit_status convert_timings(struct sysinfo *ctrl);
enum raminit_status configure_mc(struct sysinfo *ctrl);
+enum raminit_status configure_memory_map(struct sysinfo *ctrl);
void configure_timings(struct sysinfo *ctrl);
void configure_refresh(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h
index 1ee0ab2890..0228cf6bb9 100644
--- a/src/northbridge/intel/haswell/registers/host_bridge.h
+++ b/src/northbridge/intel/haswell/registers/host_bridge.h
@@ -34,6 +34,8 @@
#define MESEG_BASE 0x70 /* Management Engine Base */
#define MESEG_LIMIT 0x78 /* Management Engine Limit */
+#define MELCK (1 << 10) /* ME Range Lock */
+#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */
#define PAM0 0x80
#define PAM1 0x81
--
2.39.5
@@ -0,0 +1,35 @@
From fee89a6c872ec26c2ea128ecdce62d6c3abe53f1 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sat, 4 Oct 2025 21:57:43 +0100
Subject: [PATCH 35/48] soc/intel/alderlake: Don't compress FSP-S
Build systems like lbmk need to reproducibly insert
certain vendor files on release images.
Compression isn't always reproducible, and making it
so costs a lot more time than simply disabling compression.
With this change, FSP-S uses slightly more space inside
the flash, but it's not that much.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/alderlake/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index e0ab6b10fd..a2e7cff6f6 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE
select DRAM_SUPPORT_DDR5
select DRIVERS_USB_ACPI
select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
- select FSP_COMPRESS_FSP_S_LZ4
+# select FSP_COMPRESS_FSP_S_LZ4
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
select FSP_M_XIP
select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN
--
2.47.3
@@ -0,0 +1,33 @@
From abd26006eff71c9570bc90fdbce3a76f8f559cea Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sat, 4 Oct 2025 22:20:11 +0100
Subject: [PATCH 36/48] alderlake: don't require full fsp repo for fd path
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/alderlake/Kconfig | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index a2e7cff6f6..3402c1e3d5 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -430,7 +430,14 @@ config FSP_HEADER_PATH
config FSP_FD_PATH
string
- depends on FSP_USE_REPO
+# dependency removed for lbmk purposes, so that the path is present
+# in the config regardless of whether it's used. this is for ./mk -d
+# on alderlake boards, which is used by lbmk to manually split fsp,
+# even though the result is identical to what coreboot produces, because
+# this enables lbmk to strip the fsp in release archives, and re-insert
+# for compliance reasons (due to technicalities in intel's licensing),
+# and to enable lbmk's advanced checksum verification of vendor files
+# depends on FSP_USE_REPO
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P
--
2.47.3
@@ -1,392 +0,0 @@
From 19bc8d27c8f52b205df218d5917ae67ac4646024 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 23:12:18 +0200
Subject: [PATCH 36/51] haswell NRI: Add pre-training steps
Implement pre-training steps, which consist of enabling ECC I/O and
filling the WDB (Write Data Buffer, stores test patterns) through a
magic LDAT port.
Change-Id: Ie2e09e3b218c4569ed8de5c5e1b05d491032e0f1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../haswell/native_raminit/raminit_main.c | 35 ++++
.../haswell/native_raminit/raminit_native.h | 24 +++
.../haswell/native_raminit/reg_structs.h | 45 +++++
.../intel/haswell/native_raminit/setup_wdb.c | 159 ++++++++++++++++++
.../intel/haswell/registers/mchbar.h | 9 +
6 files changed, 273 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/setup_wdb.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index e9212df9e6..8d7d4e4db0 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -10,5 +10,6 @@ romstage-y += memory_map.c
romstage-y += raminit_main.c
romstage-y += raminit_native.c
romstage-y += reut.c
+romstage-y += setup_wdb.c
romstage-y += spd_bitmunching.c
romstage-y += timings_refresh.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 94b268468c..5e4674957d 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -3,6 +3,7 @@
#include <assert.h>
#include <console/console.h>
#include <cpu/intel/haswell/haswell.h>
+#include <delay.h>
#include <device/pci_ops.h>
#include <northbridge/intel/haswell/chip.h>
#include <northbridge/intel/haswell/haswell.h>
@@ -12,6 +13,39 @@
#include "raminit_native.h"
+static enum raminit_status pre_training(struct sysinfo *ctrl)
+{
+ /* Skip on S3 resume */
+ if (ctrl->bootmode == BOOTMODE_S3)
+ return RAMINIT_STATUS_SUCCESS;
+
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+ if (!rank_in_ch(ctrl, slot + slot, channel))
+ continue;
+
+ printk(RAM_DEBUG, "C%uS%u:\n", channel, slot);
+ printk(RAM_DEBUG, "\tMR0: 0x%04x\n", ctrl->mr0[channel][slot]);
+ printk(RAM_DEBUG, "\tMR1: 0x%04x\n", ctrl->mr1[channel][slot]);
+ printk(RAM_DEBUG, "\tMR2: 0x%04x\n", ctrl->mr2[channel][slot]);
+ printk(RAM_DEBUG, "\tMR3: 0x%04x\n", ctrl->mr3[channel][slot]);
+ printk(RAM_DEBUG, "\n");
+ }
+ if (ctrl->is_ecc) {
+ union mad_dimm_reg mad_dimm = {
+ .raw = mchbar_read32(MAD_DIMM(channel)),
+ };
+ /* Enable ECC I/O */
+ mad_dimm.ecc_mode = 1;
+ mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
+ /* Wait 4 usec after enabling the ECC I/O, needed by HW */
+ udelay(4);
+ }
+ }
+ setup_wdb(ctrl);
+ return RAMINIT_STATUS_SUCCESS;
+}
+
struct task_entry {
enum raminit_status (*task)(struct sysinfo *);
bool is_enabled;
@@ -25,6 +59,7 @@ static const struct task_entry cold_boot[] = {
{ configure_mc, true, "CONFMC", },
{ configure_memory_map, true, "MEMMAP", },
{ do_jedec_init, true, "JEDECINIT", },
+ { pre_training, true, "PRETRAIN", },
};
/* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 759d755d6d..4d9487d79c 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -36,6 +36,13 @@
#define RTTNOM_MASK (BIT(9) | BIT(6) | BIT(2))
+#define BASIC_VA_PAT_SPREAD_8 0x01010101
+
+#define WDB_CACHE_LINE_SIZE 8
+
+#define NUM_WDB_CL_MUX_SEEDS 3
+#define NUM_CADB_MUX_SEEDS 3
+
/* ZQ calibration types */
enum {
ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */
@@ -317,6 +324,23 @@ void reut_issue_mrs_all(
enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type);
+void write_wdb_fixed_pat(
+ const struct sysinfo *ctrl,
+ const uint8_t patterns[],
+ const uint8_t pat_mask[],
+ uint8_t spread,
+ uint16_t start);
+
+void write_wdb_va_pat(
+ const struct sysinfo *ctrl,
+ uint32_t agg_mask,
+ uint32_t vic_mask,
+ uint8_t vic_rot,
+ uint16_t start);
+
+void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup);
+void setup_wdb(const struct sysinfo *ctrl);
+
uint8_t get_rx_bias(const struct sysinfo *ctrl);
uint8_t get_tCWL(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index 9929f617fe..7aa8d8c8b2 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -335,6 +335,18 @@ union mcscheds_cbit_reg {
uint32_t raw;
};
+union reut_pat_cl_mux_lmn_reg {
+ struct __packed {
+ uint32_t l_data_select : 1; // Bits 0:0
+ uint32_t en_sweep_freq : 1; // Bits 1:1
+ uint32_t : 6; // Bits 7:2
+ uint32_t l_counter : 8; // Bits 15:8
+ uint32_t m_counter : 8; // Bits 23:16
+ uint32_t n_counter : 8; // Bits 31:24
+ };
+ uint32_t raw;
+};
+
union reut_pat_cadb_prog_reg {
struct __packed {
uint32_t addr : 16; // Bits 15:0
@@ -439,6 +451,39 @@ union reut_misc_odt_ctrl_reg {
uint32_t raw;
};
+union ldat_pdat_reg {
+ struct __packed {
+ uint32_t fast_addr : 12; // Bits 11:0
+ uint32_t : 4; // Bits 15:12
+ uint32_t addr_en : 1; // Bits 16:16
+ uint32_t seq_en : 1; // Bits 17:17
+ uint32_t pol_0 : 1; // Bits 18:18
+ uint32_t pol_1 : 1; // Bits 19:19
+ uint32_t cmd_a : 4; // Bits 23:20
+ uint32_t cmd_b : 4; // Bits 27:24
+ uint32_t cmd_c : 4; // Bits 31:28
+ };
+ uint32_t raw;
+};
+
+union ldat_sdat_reg {
+ struct __packed {
+ uint32_t bank_sel : 4; // Bits 3:0
+ uint32_t : 1; // Bits 4:4
+ uint32_t array_sel : 5; // Bits 9:5
+ uint32_t cmp : 1; // Bits 10:10
+ uint32_t replicate : 1; // Bits 11:11
+ uint32_t dword : 4; // Bits 15:12
+ uint32_t mode : 2; // Bits 17:16
+ uint32_t mpmap : 6; // Bits 23:18
+ uint32_t mpb_offset : 4; // Bits 27:24
+ uint32_t stage_en : 1; // Bits 28:28
+ uint32_t shadow : 2; // Bits 30:29
+ uint32_t : 1; // Bits 31:31
+ };
+ uint32_t raw;
+};
+
union mcscheds_dft_misc_reg {
struct __packed {
uint32_t wdar : 1; // Bits 0:0
diff --git a/src/northbridge/intel/haswell/native_raminit/setup_wdb.c b/src/northbridge/intel/haswell/native_raminit/setup_wdb.c
new file mode 100644
index 0000000000..ec37c48415
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/setup_wdb.c
@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static void ldat_write_cacheline(
+ const struct sysinfo *const ctrl,
+ const uint8_t chunk,
+ const uint16_t start,
+ const uint64_t data)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ /*
+ * Do not do a 64-bit write here. The register is not aligned
+ * to a 64-bit boundary, which could potentially cause issues.
+ */
+ mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 0), data & UINT32_MAX);
+ mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 1), data >> 32);
+ /*
+ * Set REPLICATE = 0 as you don't want to replicate the data.
+ * Set BANK_SEL to the chunk you want to write the 64 bits to.
+ * Set ARRAY_SEL = 0 (the MC WDB) and MODE = 1.
+ */
+ const union ldat_sdat_reg ldat_sdat = {
+ .bank_sel = chunk,
+ .mode = 1,
+ };
+ mchbar_write32(QCLK_ch_LDAT_SDAT(channel), ldat_sdat.raw);
+ /*
+ * Finally, write the PDAT register indicating which cacheline
+ * of the WDB you want to write to by setting FAST_ADDR field
+ * to one of the 64 cache lines. Also set CMD_B in the PDAT
+ * register to 4'b1000, indicating that this is a LDAT write.
+ */
+ const union ldat_pdat_reg ldat_pdat = {
+ .fast_addr = MIN(start, 0xfff),
+ .cmd_b = 8,
+ };
+ mchbar_write32(QCLK_ch_LDAT_PDAT(channel), ldat_pdat.raw);
+ }
+}
+
+static void clear_ldat_mode(const struct sysinfo *const ctrl)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
+ mchbar_write32(QCLK_ch_LDAT_SDAT(channel), 0);
+}
+
+void write_wdb_fixed_pat(
+ const struct sysinfo *const ctrl,
+ const uint8_t patterns[],
+ const uint8_t pat_mask[],
+ const uint8_t spread,
+ const uint16_t start)
+{
+ for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
+ uint64_t data = 0;
+ for (uint8_t b = 0; b < 64; b++) {
+ const uint8_t beff = b % spread;
+ const uint8_t burst = patterns[pat_mask[beff]];
+ if (burst & BIT(chunk))
+ data |= 1ULL << b;
+ }
+ ldat_write_cacheline(ctrl, chunk, start, data);
+ }
+ clear_ldat_mode(ctrl);
+}
+
+static inline uint32_t rol_u32(const uint32_t val)
+{
+ return (val << 1) | ((val >> 31) & 1);
+}
+
+void write_wdb_va_pat(
+ const struct sysinfo *const ctrl,
+ const uint32_t agg_mask,
+ const uint32_t vic_mask,
+ const uint8_t vic_rot,
+ const uint16_t start)
+{
+ static const uint8_t va_mask_to_compressed[4] = {0xaa, 0xc0, 0xcc, 0xf0};
+ uint32_t v_mask = vic_mask;
+ uint32_t a_mask = agg_mask;
+ for (uint8_t v = 0; v < vic_rot; v++) {
+ uint8_t compressed[32] = {0};
+ /* Iterate through all 32 bits and create a compressed version of cacheline */
+ for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++) {
+ const uint8_t vic = !!(v_mask & BIT(b));
+ const uint8_t agg = !!(a_mask & BIT(b));
+ const uint8_t index = !vic << 1 | agg << 0;
+ compressed[b] = va_mask_to_compressed[index];
+ }
+ for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
+ uint32_t data = 0;
+ for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++)
+ data |= !!(compressed[b] & BIT(chunk)) << b;
+
+ const uint64_t data64 = (uint64_t)data << 32 | data;
+ ldat_write_cacheline(ctrl, chunk, start + v, data64);
+ }
+ v_mask = rol_u32(v_mask);
+ a_mask = rol_u32(a_mask);
+ }
+ clear_ldat_mode(ctrl);
+}
+
+void program_wdb_lfsr(const struct sysinfo *ctrl, const bool cleanup)
+{
+ /* Cleanup LFSR seeds are sequential */
+ const uint32_t cleanup_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xaaaaaa, 0xcccccc, 0xf0f0f0 };
+ const uint32_t regular_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xa10ca1, 0xef0d08, 0xad0a1e };
+ const uint32_t *seeds = cleanup ? cleanup_seeds : regular_seeds;
+
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ for (uint8_t i = 0; i < NUM_WDB_CL_MUX_SEEDS; i++) {
+ mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_RD_x(channel, i), seeds[i]);
+ mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_WR_x(channel, i), seeds[i]);
+ }
+ }
+}
+
+void setup_wdb(const struct sysinfo *ctrl)
+{
+ const uint32_t amask[9] = {
+ 0x86186186, 0x18618618, 0x30c30c30,
+ 0xa28a28a2, 0x8a28a28a, 0x14514514,
+ 0x28a28a28, 0x92492492, 0x24924924,
+ };
+ const uint32_t vmask = 0x41041041;
+
+ /* Fill first 8 entries with simple 2-LFSR VA pattern */
+ write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
+
+ /* Fill next 54 entries with 3-LFSR VA pattern */
+ for (uint8_t a = 0; a < ARRAY_SIZE(amask); a++)
+ write_wdb_va_pat(ctrl, amask[a], vmask, 6, 8 + a * 6);
+
+ program_wdb_lfsr(ctrl, false);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ const union reut_pat_cl_mux_lmn_reg wdb_cl_mux_lmn = {
+ .en_sweep_freq = 1,
+ .l_counter = 1,
+ .m_counter = 1,
+ .n_counter = 10,
+ };
+ mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_LMN(channel), wdb_cl_mux_lmn.raw);
+ }
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 4fc78a7f43..f8408e51a0 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -94,6 +94,11 @@
#define TC_BANK_RANK_D_ch(ch) _MCMAIN_C(0x4014, ch)
#define SC_ROUNDT_LAT_ch(ch) _MCMAIN_C(0x4024, ch)
+#define REUT_ch_PAT_WDB_CL_MUX_WR_x(ch, x) _MCMAIN_C_X(0x4048, ch, x) /* x in 0 .. 2 */
+#define REUT_ch_PAT_WDB_CL_MUX_RD_x(ch, x) _MCMAIN_C_X(0x4054, ch, x) /* x in 0 .. 2 */
+
+#define REUT_ch_PAT_WDB_CL_MUX_LMN(ch) _MCMAIN_C(0x4078, ch)
+
#define SC_WR_ADD_DELAY_ch(ch) _MCMAIN_C(0x40d0, ch)
#define REUT_ch_MISC_CKE_CTRL(ch) _MCMAIN_C(0x4190, ch)
@@ -110,6 +115,10 @@
#define MC_INIT_STATE_ch(ch) _MCMAIN_C(0x42a0, ch)
#define TC_SRFTP_ch(ch) _MCMAIN_C(0x42a4, ch)
+#define QCLK_ch_LDAT_PDAT(ch) _MCMAIN_C(0x42d0, ch)
+#define QCLK_ch_LDAT_SDAT(ch) _MCMAIN_C(0x42d4, ch)
+#define QCLK_ch_LDAT_DATA_IN_x(ch, x) _MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
+
#define REUT_GLOBAL_ERR 0x4804
#define REUT_ch_SEQ_CFG(ch) (0x48a8 + 8 * (ch))
--
2.39.5
File diff suppressed because it is too large Load Diff
@@ -0,0 +1,46 @@
From 6a4a79d82df982c2fca859101040e407623f519c Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 6 Oct 2025 04:47:06 +0100
Subject: [PATCH 37/48] soc/alderlake: disable stack overflow debug option
same as on other boards. based on this commit:
commit 51cc2bacb6b07279b97e9934d079060475481fb6
Author: Subrata Banik <subratabanik@google.com>
Author: Subrata Banik <subratabanik@google.com>
Date: Fri Dec 13 13:07:28 2024 +0530
soc/intel/pantherlake: Disable stack overflow debug options
yeah, i've been replicating this change per platform.
we do alderlake now in libreboot, so let's set that here too.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/alderlake/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 3402c1e3d5..06b9199e84 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -331,6 +331,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ
int
default 19200000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 133
--
2.47.3
@@ -0,0 +1,92 @@
From bb286d13cb7702e9396deab04023cc58dcc01a15 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 11 May 2025 15:41:22 -0600
Subject: [PATCH 38/48] ec/dell/mec5035: Add command to disable EC-initiated
thermal shutdown
If command 0xBF isn't sent, the EC shuts down the system without warning
as soon as the CPU temperature reaches about 87 degrees, without letting
the CPU thermal throttle to try and reduce the temperature. With vendor
firmware, the CPU is able to reach around 100 degrees before thermal
throttling.
This command was found by collecting EC commands by logging the LPC bus
while running with vendor firmware and then replaying observed commands
from coreboot. By systematically replaying subsets of commands in a
binary search pattern and then stress testing the system, the command to
disable the shutdown was isolated.
The exact meaning of the parameters for this command are unknown at this
time, but do seem to differ between different generations of these
laptops. Due to this, the commmand should be called by mainboard
specific code which passes the specific parameter value used.
The Google Wilco EC code, which runs on Latitude Chromebooks and shares
many commands with the standard Latitude ECs, suggests that command 0xBF
tells the EC about the processors CPUID. However, the values observed in
LPC bus logs do not seem to correspond with any CPUID values on the
non-Chromebook systems I tested.
Observed command parameter values (sent on mailbox registers 2-4):
- E6430 (Ivy Bridge): 0x07, 0x00, 0x00
- M6800 (Haswell): 0x14, 0x00, 0x00
Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++
src/ec/dell/mec5035/mec5035.h | 2 ++
2 files changed, 21 insertions(+)
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index c5067c16f6..b316fa4989 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -114,6 +114,25 @@ void mec5035_sleep_enable(void)
ec_command(CMD_SLEEP_ENABLE);
}
+void mec5035_cmd_bf(u8 i)
+{
+ /*
+ * If this command isn't sent, the EC shuts down the system as soon as
+ * the CPU temperature reaches about 87 degrees. It is unknown exactly
+ * what the parameters represent. The Google Wilco EC code, which runs
+ * on Latitude Chromebooks and shares some commands with the standard
+ * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but
+ * the values observed in LPC bus logs don't seem to match any CPUID
+ * values of the normal Latitudes this was tested with.
+ * Observed i values:
+ * - E6430 (Ivy Bridge): 0x7
+ * - M6800 (Haswell): 0x14
+ */
+ u8 buf[3] = {i, 0, 0};
+ write_mailbox_regs(buf, 2, 3);
+ ec_command(CMD_BF);
+}
+
void mec5035_early_init(void)
{
/* If this isn't sent the EC shuts down the system after about 15
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index 5cd907bf71..71d1a71075 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -14,6 +14,7 @@ enum mec5035_cmd {
CMD_POWER_BUTTON_TO_HOST = 0x3e,
CMD_ACPI_WAKEUP_CHANGE = 0x4a,
CMD_SLEEP_ENABLE = 0x64,
+ CMD_BF = 0xbf,
CMD_CPU_OK = 0xc2,
};
@@ -65,5 +66,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change);
void mec5035_sleep_enable(void);
void mec5035_smi_sleep(int slp_type);
+void mec5035_cmd_bf(u8 i);
#endif /* _EC_DELL_MEC5035_H_ */
--
2.47.3
@@ -1,222 +0,0 @@
From 36b206a88281796458e6ebc30fe34a7c51c86548 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 00:56:00 +0200
Subject: [PATCH 38/51] haswell NRI: Add range tracking library
Implement a small library used to keep track of passing ranges. This
will be used by 1D training algorithms when margining some parameter.
Change-Id: I8718e85165160afd7c0c8e730b5ce6c9c00f8a60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../intel/haswell/native_raminit/ranges.c | 109 ++++++++++++++++++
.../intel/haswell/native_raminit/ranges.h | 68 +++++++++++
3 files changed, 178 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.c
create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.h
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 6e1b365602..2da950771d 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -9,6 +9,7 @@ romstage-y += io_comp_control.c
romstage-y += memory_map.c
romstage-y += raminit_main.c
romstage-y += raminit_native.c
+romstage-y += ranges.c
romstage-y += reut.c
romstage-y += setup_wdb.c
romstage-y += spd_bitmunching.c
diff --git a/src/northbridge/intel/haswell/native_raminit/ranges.c b/src/northbridge/intel/haswell/native_raminit/ranges.c
new file mode 100644
index 0000000000..cdebc1fa66
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/ranges.c
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <types.h>
+
+#include "ranges.h"
+
+void linear_record_pass(
+ struct linear_train_data *const data,
+ const bool pass,
+ const int32_t value,
+ const int32_t start,
+ const int32_t step)
+{
+ /* If this is the first time, initialize all values */
+ if (value == start) {
+ /*
+ * If value passed, create a zero-length region for the current value,
+ * which may be extended as long as the successive values are passing.
+ *
+ * Otherwise, create a zero-length range for the preceding value. This
+ * range cannot be extended by other passing values, which is desired.
+ */
+ data->current.start = start - (pass ? 0 : step);
+ data->current.end = data->current.start;
+ data->largest = data->current;
+ } else if (pass) {
+ /* If this pass is not contiguous, it belongs to a new region */
+ if (data->current.end != (value - step))
+ data->current.start = value;
+
+ /* Update end of current region */
+ data->current.end = value;
+
+ /* Update largest region */
+ if (range_width(data->current) > range_width(data->largest))
+ data->largest = data->current;
+ }
+}
+
+void phase_record_pass(
+ struct phase_train_data *const data,
+ const bool pass,
+ const int32_t value,
+ const int32_t start,
+ const int32_t step)
+{
+ /* If this is the first time, initialize all values */
+ if (value == start) {
+ /*
+ * If value passed, create a zero-length region for the current value,
+ * which may be extended as long as the successive values are passing.
+ *
+ * Otherwise, create a zero-length range for the preceding value. This
+ * range cannot be extended by other passing values, which is desired.
+ */
+ data->current.start = start - (pass ? 0 : step);
+ data->current.end = data->current.start;
+ data->largest = data->current;
+ data->initial = data->current;
+ return;
+ }
+ if (!pass)
+ return;
+
+ /* Update initial region */
+ if (data->initial.end == (value - step))
+ data->initial.end = value;
+
+ /* If this pass is not contiguous, it belongs to a new region */
+ if (data->current.end != (value - step))
+ data->current.start = value;
+
+ /* Update end of current region */
+ data->current.end = value;
+
+ /* Update largest region */
+ if (range_width(data->current) > range_width(data->largest))
+ data->largest = data->current;
+}
+
+void phase_append_initial_to_current(
+ struct phase_train_data *const data,
+ const int32_t start,
+ const int32_t step)
+{
+ /* If initial region is valid and does not overlap, append it */
+ if (data->initial.start == start && data->initial.end != data->current.end)
+ data->current.end += step + range_width(data->initial);
+
+ /* Update largest region */
+ if (range_width(data->current) > range_width(data->largest))
+ data->largest = data->current;
+}
+
+void phase_append_current_to_initial(
+ struct phase_train_data *const data,
+ const int32_t start,
+ const int32_t step)
+{
+ /* If initial region is valid and does not overlap, append it */
+ if (data->initial.start == start && data->initial.end != data->current.end) {
+ data->initial.start -= (step + range_width(data->current));
+ data->current = data->initial;
+ }
+
+ /* Update largest region */
+ if (range_width(data->current) > range_width(data->largest))
+ data->largest = data->current;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/ranges.h b/src/northbridge/intel/haswell/native_raminit/ranges.h
new file mode 100644
index 0000000000..235392df96
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/ranges.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef HASWELL_RAMINIT_RANGES_H
+#define HASWELL_RAMINIT_RANGES_H
+
+#include <types.h>
+
+/*
+ * Many algorithms shmoo some parameter to determine the largest passing
+ * range. Provide a common implementation to avoid redundant boilerplate.
+ */
+struct passing_range {
+ int32_t start;
+ int32_t end;
+};
+
+/* Structure for linear parameters, such as roundtrip delays */
+struct linear_train_data {
+ struct passing_range current;
+ struct passing_range largest;
+};
+
+/*
+ * Phase ranges are "circular": the first and last indices are contiguous.
+ * To correctly determine the largest passing range, one has to combine
+ * the initial range and the current range when processing the last index.
+ */
+struct phase_train_data {
+ struct passing_range initial;
+ struct passing_range current;
+ struct passing_range largest;
+};
+
+static inline int32_t range_width(const struct passing_range range)
+{
+ return range.end - range.start;
+}
+
+static inline int32_t range_center(const struct passing_range range)
+{
+ return range.start + range_width(range) / 2;
+}
+
+void linear_record_pass(
+ struct linear_train_data *data,
+ bool pass,
+ int32_t value,
+ int32_t start,
+ int32_t step);
+
+void phase_record_pass(
+ struct phase_train_data *data,
+ bool pass,
+ int32_t value,
+ int32_t start,
+ int32_t step);
+
+void phase_append_initial_to_current(
+ struct phase_train_data *data,
+ int32_t start,
+ int32_t step);
+
+void phase_append_current_to_initial(
+ struct phase_train_data *data,
+ int32_t start,
+ int32_t step);
+
+#endif
--
2.39.5
@@ -1,294 +0,0 @@
From 926b1af1033c26ad231587fd3a4506efb4b0d8a3 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 01:11:03 +0200
Subject: [PATCH 39/51] haswell NRI: Add library to change margins
Implement a library to change Rx/Tx margins. It will be expanded later.
Change-Id: I0b55aba428d8b4d4e16d2fbdec57235ce3ce8adf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../haswell/native_raminit/change_margin.c | 154 ++++++++++++++++++
.../haswell/native_raminit/raminit_native.h | 50 ++++++
.../intel/haswell/registers/mchbar.h | 9 +
4 files changed, 214 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/change_margin.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 2da950771d..ebe9e9b762 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -1,5 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-or-later
+romstage-y += change_margin.c
romstage-y += configure_mc.c
romstage-y += ddr3.c
romstage-y += jedec_reset.c
diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
new file mode 100644
index 0000000000..055c666eee
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+
+#include "raminit_native.h"
+
+void update_rxt(
+ struct sysinfo *ctrl,
+ const uint8_t channel,
+ const uint8_t rank,
+ const uint8_t byte,
+ const enum rxt_subfield subfield,
+ const int32_t value)
+{
+ union ddr_data_rx_train_rank_reg rxt = {
+ .rcven = ctrl->rcven[channel][rank][byte],
+ .dqs_p = ctrl->rxdqsp[channel][rank][byte],
+ .rx_eq = ctrl->rx_eq[channel][rank][byte],
+ .dqs_n = ctrl->rxdqsn[channel][rank][byte],
+ .vref = ctrl->rxvref[channel][rank][byte],
+ };
+ int32_t new_value;
+ switch (subfield) {
+ case RXT_RCVEN:
+ new_value = clamp_s32(0, value, 511);
+ rxt.rcven = new_value;
+ break;
+ case RXT_RXDQS_P:
+ new_value = clamp_s32(0, value, 63);
+ rxt.dqs_p = new_value;
+ break;
+ case RXT_RX_EQ:
+ new_value = clamp_s32(0, value, 31);
+ rxt.rx_eq = new_value;
+ break;
+ case RXT_RXDQS_N:
+ new_value = clamp_s32(0, value, 63);
+ rxt.dqs_n = new_value;
+ break;
+ case RXT_RX_VREF:
+ new_value = clamp_s32(-32, value, 31);
+ rxt.vref = new_value;
+ break;
+ case RXT_RXDQS_BOTH:
+ new_value = clamp_s32(0, value, 63);
+ rxt.dqs_p = new_value;
+ rxt.dqs_n = new_value;
+ break;
+ case RXT_RESTORE:
+ new_value = value;
+ break;
+ default:
+ die("%s: Unhandled subfield index %u\n", __func__, subfield);
+ }
+
+ if (new_value != value) {
+ printk(BIOS_ERR, "%s: Overflow for subfield %u: %d ---> %d\n",
+ __func__, subfield, value, new_value);
+ }
+ mchbar_write32(RX_TRAIN_ch_r_b(channel, rank, byte), rxt.raw);
+ download_regfile(ctrl, channel, false, rank, REG_FILE_USE_RANK, byte, true, false);
+}
+
+void update_txt(
+ struct sysinfo *ctrl,
+ const uint8_t channel,
+ const uint8_t rank,
+ const uint8_t byte,
+ const enum txt_subfield subfield,
+ const int32_t value)
+{
+ union ddr_data_tx_train_rank_reg txt = {
+ .dq_delay = ctrl->tx_dq[channel][rank][byte],
+ .dqs_delay = ctrl->txdqs[channel][rank][byte],
+ .tx_eq = ctrl->tx_eq[channel][rank][byte],
+ };
+ int32_t new_value;
+ switch (subfield) {
+ case TXT_TX_DQ:
+ new_value = clamp_s32(0, value, 511);
+ txt.dq_delay = new_value;
+ break;
+ case TXT_TXDQS:
+ new_value = clamp_s32(0, value, 511);
+ txt.dqs_delay = new_value;
+ break;
+ case TXT_TX_EQ:
+ new_value = clamp_s32(0, value, 63);
+ txt.tx_eq = new_value;
+ break;
+ case TXT_DQDQS_OFF:
+ new_value = value;
+ txt.dqs_delay += new_value;
+ txt.dq_delay += new_value;
+ break;
+ case TXT_RESTORE:
+ new_value = value;
+ break;
+ default:
+ die("%s: Unhandled subfield index %u\n", __func__, subfield);
+ }
+ if (new_value != value) {
+ printk(BIOS_ERR, "%s: Overflow for subfield %u: %d ---> %d\n",
+ __func__, subfield, value, new_value);
+ }
+ mchbar_write32(TX_TRAIN_ch_r_b(channel, rank, byte), txt.raw);
+ download_regfile(ctrl, channel, false, rank, REG_FILE_USE_RANK, byte, false, true);
+}
+
+void download_regfile(
+ struct sysinfo *ctrl,
+ const uint8_t channel,
+ const bool multicast,
+ const uint8_t rank,
+ const enum regfile_mode regfile,
+ const uint8_t byte,
+ const bool read_rf_rd,
+ const bool read_rf_wr)
+{
+ union reut_seq_base_addr_reg reut_seq_base_addr;
+ switch (regfile) {
+ case REG_FILE_USE_START:
+ reut_seq_base_addr.raw = mchbar_read64(REUT_ch_SEQ_ADDR_START(channel));
+ break;
+ case REG_FILE_USE_CURRENT:
+ reut_seq_base_addr.raw = mchbar_read64(REUT_ch_SEQ_ADDR_CURRENT(channel));
+ break;
+ case REG_FILE_USE_RANK:
+ reut_seq_base_addr.raw = 0;
+ if (rank >= NUM_SLOTRANKS)
+ die("%s: bad rank %u\n", __func__, rank);
+ break;
+ default:
+ die("%s: Invalid regfile param %u\n", __func__, regfile);
+ }
+ uint8_t phys_rank = rank;
+ if (reut_seq_base_addr.raw != 0) {
+ /* Map REUT logical rank to physical rank */
+ const uint32_t log_to_phys = mchbar_read32(REUT_ch_RANK_LOG_TO_PHYS(channel));
+ phys_rank = log_to_phys >> (reut_seq_base_addr.rank_addr * 4) & 0x3;
+ }
+ uint32_t reg = multicast ? DDR_DATA_ch_CONTROL_0(channel) : DQ_CONTROL_0(channel, byte);
+ union ddr_data_control_0_reg ddr_data_control_0 = {
+ .raw = mchbar_read32(reg),
+ };
+ ddr_data_control_0.read_rf_rd = read_rf_rd;
+ ddr_data_control_0.read_rf_wr = read_rf_wr;
+ ddr_data_control_0.read_rf_rank = phys_rank;
+ mchbar_write32(reg, ddr_data_control_0.raw);
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index f029e7f076..8707257b27 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -118,6 +118,30 @@ enum test_stop {
ALSOE = 3, /* Stop on all lanes error */
};
+enum rxt_subfield {
+ RXT_RCVEN = 0,
+ RXT_RXDQS_P = 1,
+ RXT_RX_EQ = 2,
+ RXT_RXDQS_N = 3,
+ RXT_RX_VREF = 4,
+ RXT_RXDQS_BOTH = 5,
+ RXT_RESTORE = 255,
+};
+
+enum txt_subfield {
+ TXT_TX_DQ = 0,
+ TXT_TXDQS = 1,
+ TXT_TX_EQ = 2,
+ TXT_DQDQS_OFF = 3,
+ TXT_RESTORE = 255,
+};
+
+enum regfile_mode {
+ REG_FILE_USE_RANK, /* Used when changing parameters for each rank */
+ REG_FILE_USE_START, /* Used when changing parameters before the test */
+ REG_FILE_USE_CURRENT, /* Used when changing parameters after the test */
+};
+
struct wdb_pat {
uint32_t start_ptr; /* Starting pointer in WDB */
uint32_t stop_ptr; /* Stopping pointer in WDB */
@@ -451,6 +475,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas
void run_mpr_io_test(bool clear_errors);
uint8_t run_io_test(struct sysinfo *ctrl, uint8_t chanmask, uint8_t dq_pat, bool clear_errors);
+void update_rxt(
+ struct sysinfo *ctrl,
+ uint8_t channel,
+ uint8_t rank,
+ uint8_t byte,
+ enum rxt_subfield subfield,
+ int32_t value);
+
+void update_txt(
+ struct sysinfo *ctrl,
+ uint8_t channel,
+ uint8_t rank,
+ uint8_t byte,
+ enum txt_subfield subfield,
+ int32_t value);
+
+void download_regfile(
+ struct sysinfo *ctrl,
+ uint8_t channel,
+ bool multicast,
+ uint8_t rank,
+ enum regfile_mode regfile,
+ uint8_t byte,
+ bool read_rf_rd,
+ bool read_rf_wr);
+
uint8_t get_rx_bias(const struct sysinfo *ctrl);
uint8_t get_tCWL(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 817a9f8bf8..a81559bb1e 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -15,7 +15,11 @@
/* Register definitions */
/* DDR DATA per-channel per-bytelane */
+#define RX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0000, ch, rank, byte)
+#define TX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0020, ch, rank, byte)
+
#define DQ_CONTROL_2(ch, byte) _DDRIO_C_R_B(0x0064, ch, 0, byte)
+#define DQ_CONTROL_0(ch, byte) _DDRIO_C_R_B(0x0074, ch, 0, byte)
/* DDR CKE per-channel */
#define DDR_CKE_ch_CMD_COMP_OFFSET(ch) _DDRIO_C_R_B(0x1204, ch, 0, 0)
@@ -38,6 +42,9 @@
#define DDR_SCRAMBLE_ch(ch) (0x2000 + 4 * (ch))
#define DDR_SCRAM_MISC_CONTROL 0x2008
+/* DDR DATA per-channel multicast */
+#define DDR_DATA_ch_CONTROL_0(ch) _DDRIO_C_R_B(0x3074, ch, 0, 0)
+
/* DDR CMDN/CMDS per-channel (writes go to both CMDN and CMDS fubs) */
#define DDR_CMD_ch_COMP_OFFSET(ch) _DDRIO_C_R_B(0x3204, ch, 0, 0)
#define DDR_CMD_ch_PI_CODING(ch) _DDRIO_C_R_B(0x3208, ch, 0, 0)
@@ -147,6 +154,8 @@
#define REUT_ch_SEQ_ADDR_WRAP(ch) (0x48e8 + 8 * (ch))
+#define REUT_ch_SEQ_ADDR_CURRENT(ch) (0x48f8 + 8 * (ch))
+
#define REUT_ch_SEQ_MISC_CTL(ch) (0x4908 + 4 * (ch))
#define REUT_ch_SEQ_ADDR_INC_CTL(ch) (0x4910 + 8 * (ch))
--
2.39.5
@@ -0,0 +1,36 @@
From a93c01173c2f88b4a09286740c030314040c39fc Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 11 May 2025 16:28:23 -0600
Subject: [PATCH 39/48] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown
at 87 degrees
If command 0xBF isn't sent, the EC will shut down the system without
warning once the CPU reaches approximately 87 degrees, without the
system thermal throttling first. Call the newly added function from the
MEC5035 code to send this command and disable this behavior.
Tested on the Latitude E6430.
Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c
index ff83db095b..ef385a0a70 100644
--- a/src/mainboard/dell/snb_ivb_latitude/early_init.c
+++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c
@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void)
| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
| COMB_LPC_EN | COMA_LPC_EN);
mec5035_early_init();
+
+ /* Observed from LPC logs with vendor firmware. Seems to disable
+ * EC-initiated shutdown when the CPU reaches approximately 87 degrees.
+ * The exact meaning of the parameter is currently unknown. */
+ mec5035_cmd_bf(0x07);
}
--
2.47.3
@@ -0,0 +1,28 @@
From dc4036353483c5fc0c140fc269d9bddb0bb7a967 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sat, 20 Dec 2025 20:12:48 +0100
Subject: [PATCH 40/48] fix ifdtool build
not my mistake. someone messed up.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index cab934c3a5..d181888e0f 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -2598,7 +2598,7 @@ int main(int argc, char *argv[])
}
mode_nuke = 1;
break;
- Case 'v':
+ case 'v':
print_version();
exit(EXIT_SUCCESS);
break;
--
2.47.3
@@ -1,708 +0,0 @@
From 61435822eb1d65b919bec45076737ce4ea91e1b1 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 00:05:41 +0200
Subject: [PATCH 40/51] haswell NRI: Add RcvEn training
Implement the RcvEn (Receive Enable) calibration procedure.
Change-Id: Ifbfa520f3e0486c56d0988ce67af2ddb9cf29888
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../haswell/native_raminit/raminit_main.c | 1 +
.../haswell/native_raminit/raminit_native.h | 14 +
.../haswell/native_raminit/reg_structs.h | 13 +
.../native_raminit/train_receive_enable.c | 561 ++++++++++++++++++
.../intel/haswell/registers/mchbar.h | 3 +
6 files changed, 593 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index ebe9e9b762..e2fbfb4211 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -16,3 +16,4 @@ romstage-y += setup_wdb.c
romstage-y += spd_bitmunching.c
romstage-y += testing_io.c
romstage-y += timings_refresh.c
+romstage-y += train_receive_enable.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 5e4674957d..7d444659c3 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = {
{ configure_memory_map, true, "MEMMAP", },
{ do_jedec_init, true, "JEDECINIT", },
{ pre_training, true, "PRETRAIN", },
+ { train_receive_enable, true, "RCVET", },
};
/* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 8707257b27..eaaaedad1e 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -43,6 +43,9 @@
#define NUM_WDB_CL_MUX_SEEDS 3
#define NUM_CADB_MUX_SEEDS 3
+/* Specified in PI ticks. 64 PI ticks == 1 qclk */
+#define tDQSCK_DRIFT 64
+
/* ZQ calibration types */
enum {
ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */
@@ -189,6 +192,7 @@ enum raminit_status {
RAMINIT_STATUS_MPLL_INIT_FAILURE,
RAMINIT_STATUS_POLL_TIMEOUT,
RAMINIT_STATUS_REUT_ERROR,
+ RAMINIT_STATUS_RCVEN_FAILURE,
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
};
@@ -271,6 +275,10 @@ struct sysinfo {
union ddr_data_vref_adjust_reg dimm_vref;
+ uint8_t io_latency[NUM_CHANNELS][NUM_SLOTRANKS];
+ uint8_t rt_latency[NUM_CHANNELS][NUM_SLOTRANKS];
+ uint32_t rt_io_comp[NUM_CHANNELS];
+
uint32_t data_offset_train[NUM_CHANNELS][NUM_LANES];
uint32_t data_offset_comp[NUM_CHANNELS][NUM_LANES];
@@ -345,6 +353,11 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl)
memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train));
}
+static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint8_t byte)
+{
+ return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte));
+}
+
/* Number of ticks to wait in units of 69.841279 ns (citation needed) */
static inline void tick_delay(const uint32_t delay)
{
@@ -400,6 +413,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
enum raminit_status configure_mc(struct sysinfo *ctrl);
enum raminit_status configure_memory_map(struct sysinfo *ctrl);
enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+enum raminit_status train_receive_enable(struct sysinfo *ctrl);
void configure_timings(struct sysinfo *ctrl);
void configure_refresh(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index b943259b91..b099f4bb82 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -297,6 +297,19 @@ union ddr_scram_misc_control_reg {
uint32_t raw;
};
+union sc_io_latency_reg {
+ struct __packed {
+ uint32_t iolat_rank0 : 4; // Bits 3:0
+ uint32_t iolat_rank1 : 4; // Bits 7:4
+ uint32_t iolat_rank2 : 4; // Bits 11:8
+ uint32_t iolat_rank3 : 4; // Bits 15:12
+ uint32_t rt_iocomp : 6; // Bits 21:16
+ uint32_t : 9; // Bits 30:22
+ uint32_t dis_rt_clk_gate : 1; // Bits 31:31
+ };
+ uint32_t raw;
+};
+
union mcscheds_cbit_reg {
struct __packed {
uint32_t dis_opp_cas : 1; // Bits 0:0
diff --git a/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
new file mode 100644
index 0000000000..576c6bc21e
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
@@ -0,0 +1,561 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+#include "ranges.h"
+
+#define RCVEN_PLOT RAM_DEBUG
+
+static enum raminit_status change_rcven_timing(struct sysinfo *ctrl, const uint8_t channel)
+{
+ int16_t max_rcven = -4096;
+ int16_t min_rcven = 4096;
+ int16_t max_rcven_rank[NUM_SLOTRANKS];
+ int16_t min_rcven_rank[NUM_SLOTRANKS];
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ max_rcven_rank[rank] = max_rcven;
+ min_rcven_rank[rank] = min_rcven;
+ }
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ int16_t new_rcven = ctrl->rcven[channel][rank][byte];
+ new_rcven -= ctrl->io_latency[channel][rank] * 64;
+ if (max_rcven_rank[rank] < new_rcven)
+ max_rcven_rank[rank] = new_rcven;
+
+ if (min_rcven_rank[rank] > new_rcven)
+ min_rcven_rank[rank] = new_rcven;
+ }
+ if (max_rcven < max_rcven_rank[rank])
+ max_rcven = max_rcven_rank[rank];
+
+ if (min_rcven > min_rcven_rank[rank])
+ min_rcven = min_rcven_rank[rank];
+ }
+
+ /*
+ * Determine how far we are from the ideal center point for RcvEn timing.
+ * (PiIdeal - AveRcvEn) / 64 is the ideal number of cycles we should have
+ * for IO latency. command training will reduce this by 64, so plan for
+ * that now in the ideal value. Round to closest integer.
+ */
+ const int16_t rre_pi_ideal = 256 + 64;
+ const int16_t pi_reserve = 64;
+ const int16_t rcven_center = (max_rcven + min_rcven) / 2;
+ const int8_t iolat_target = DIV_ROUND_CLOSEST(rre_pi_ideal - rcven_center, 64);
+
+ int8_t io_g_offset = 0;
+ int8_t io_lat[NUM_SLOTRANKS] = { 0 };
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ io_lat[rank] = iolat_target;
+
+ /* Check for RcvEn underflow/overflow */
+ const int16_t rcven_lower = 64 * io_lat[rank] + min_rcven_rank[rank];
+ if (rcven_lower < pi_reserve)
+ io_lat[rank] += DIV_ROUND_UP(pi_reserve - rcven_lower, 64);
+
+ const int16_t rcven_upper = 64 * io_lat[rank] + max_rcven_rank[rank];
+ if (rcven_upper > 511 - pi_reserve)
+ io_lat[rank] -= DIV_ROUND_UP(rcven_upper - (511 - pi_reserve), 64);
+
+ /* Check for IO latency over/underflow */
+ if (io_lat[rank] - io_g_offset > 14)
+ io_g_offset = io_lat[rank] - 14;
+
+ if (io_lat[rank] - io_g_offset < 1)
+ io_g_offset = io_lat[rank] - 1;
+
+ const int8_t cycle_offset = io_lat[rank] - ctrl->io_latency[channel][rank];
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ ctrl->rcven[channel][rank][byte] += 64 * cycle_offset;
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+ }
+ }
+
+ /* Calculate new IO comp latency */
+ union sc_io_latency_reg sc_io_lat = {
+ .raw = mchbar_read32(SC_IO_LATENCY_ch(channel)),
+ };
+
+ /* Check if we are underflowing or overflowing this field */
+ if (io_g_offset < 0 && sc_io_lat.rt_iocomp < -io_g_offset) {
+ printk(BIOS_ERR, "%s: IO COMP underflow\n", __func__);
+ printk(BIOS_ERR, "io_g_offset: %d\n", io_g_offset);
+ printk(BIOS_ERR, "rt_iocomp: %u\n", sc_io_lat.rt_iocomp);
+ return RAMINIT_STATUS_RCVEN_FAILURE;
+ }
+ if (io_g_offset > 0 && io_g_offset > 0x3f - sc_io_lat.rt_iocomp) {
+ printk(BIOS_ERR, "%s: IO COMP overflow\n", __func__);
+ printk(BIOS_ERR, "io_g_offset: %d\n", io_g_offset);
+ printk(BIOS_ERR, "rt_iocomp: %u\n", sc_io_lat.rt_iocomp);
+ return RAMINIT_STATUS_RCVEN_FAILURE;
+ }
+ sc_io_lat.rt_iocomp += io_g_offset;
+ ctrl->rt_io_comp[channel] = sc_io_lat.rt_iocomp;
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (ctrl->rankmap[channel] & BIT(rank))
+ ctrl->io_latency[channel][rank] = io_lat[rank] - io_g_offset;
+
+ const uint8_t shift = rank * 4;
+ sc_io_lat.raw &= ~(0xf << shift);
+ sc_io_lat.raw |= ctrl->io_latency[channel][rank] << shift;
+ }
+ mchbar_write32(SC_IO_LATENCY_ch(channel), sc_io_lat.raw);
+ return RAMINIT_STATUS_SUCCESS;
+}
+
+#define RL_START (256 + 24)
+#define RL_STOP (384 + 24)
+#define RL_STEP 8
+
+#define RE_NUM_SAMPLES 6
+
+static enum raminit_status verify_high_region(const int32_t center, const int32_t lwidth)
+{
+ if (center > RL_STOP) {
+ /* Check if center of high was found where it should be */
+ printk(BIOS_ERR, "RcvEn: Center of high (%d) higher than expected\n", center);
+ return RAMINIT_STATUS_RCVEN_FAILURE;
+ }
+ if (lwidth <= 32) {
+ /* Check if width is large enough */
+ printk(BIOS_ERR, "RcvEn: Width of high region (%d) too small\n", lwidth);
+ return RAMINIT_STATUS_RCVEN_FAILURE;
+ }
+ if (lwidth >= 96) {
+ /* Since we're calibrating a phase, a too large region is a problem */
+ printk(BIOS_ERR, "RcvEn: Width of high region (%d) too large\n", lwidth);
+ return RAMINIT_STATUS_RCVEN_FAILURE;
+ }
+ return RAMINIT_STATUS_SUCCESS;
+}
+
+static void program_io_latency(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
+{
+ const uint8_t shift = rank * 4;
+ const uint8_t iolat = ctrl->io_latency[channel][rank];
+ mchbar_clrsetbits32(SC_IO_LATENCY_ch(channel), 0xf << shift, iolat << shift);
+}
+
+static void program_rl_delays(struct sysinfo *ctrl, const uint8_t rank, const uint16_t rl_delay)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ update_rxt(ctrl, channel, rank, byte, RXT_RCVEN, rl_delay);
+ }
+}
+
+static bool sample_dqs(const uint8_t channel, const uint8_t byte)
+{
+ return (get_data_train_feedback(channel, byte) & 0x1ff) >= BIT(RE_NUM_SAMPLES - 1);
+}
+
+enum raminit_status train_receive_enable(struct sysinfo *ctrl)
+{
+ const struct reut_box reut_addr = {
+ .col = {
+ .start = 0,
+ .stop = 1023,
+ .inc_rate = 0,
+ .inc_val = 1,
+ },
+ };
+ const struct wdb_pat wdb_pattern = {
+ .start_ptr = 0,
+ .stop_ptr = 9,
+ .inc_rate = 32,
+ .dq_pattern = BASIC_VA,
+ };
+
+ const uint16_t bytemask = BIT(ctrl->lanes) - 1;
+ const uint8_t fine_step = 1;
+
+ const uint8_t rt_delta = is_hsw_ult() ? 4 : 2;
+ const uint8_t rt_io_comp = 21 + rt_delta;
+ const uint8_t rt_latency = 16 + rt_delta;
+ setup_io_test(
+ ctrl,
+ ctrl->chanmap,
+ PAT_RD,
+ 2,
+ RE_NUM_SAMPLES + 1,
+ &reut_addr,
+ 0,
+ &wdb_pattern,
+ 0,
+ 8);
+
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ union ddr_data_control_2_reg data_control_2 = {
+ .raw = ctrl->dq_control_2[channel][byte],
+ };
+ data_control_2.force_rx_on = 1;
+ mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
+ }
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = ctrl->dq_control_0[channel],
+ };
+ if (ctrl->lpddr) {
+ /**
+ * W/A for b4618574 - @todo: remove for HSW ULT C0
+ * Can't have force_odt_on together with leaker, disable LPDDR
+ * mode during this training step. lpddr_mode is restored
+ * at the end of this function from the host structure.
+ */
+ data_control_0.lpddr_mode = 0;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ }
+ data_control_0.force_odt_on = 1;
+ data_control_0.rl_training_mode = 1;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ mchbar_write32(SC_IO_LATENCY_ch(channel), (union sc_io_latency_reg) {
+ .rt_iocomp = rt_io_comp,
+ }.raw);
+ }
+ enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!does_rank_exist(ctrl, rank))
+ continue;
+
+ /*
+ * Set initial roundtrip latency values. Assume -4 QCLK for worst board
+ * layout. This is calculated as HW_ROUNDT_LAT_DEFAULT_VALUE plus:
+ *
+ * DDR3: Default + (2 * tAA) + 4 QCLK + PI_CLK + N-mode value * 2
+ * LPDDR3: Default + (2 * tAA) + 4 QCLK + PI_CLK + tDQSCK_max
+ *
+ * N-mode is 3 during training mode. Both channels use the same timings.
+ */
+ /** TODO: differs for LPDDR **/
+ const uint32_t tmp = MAX(ctrl->multiplier, 4) + 5 + 2 * ctrl->tAA;
+ const uint32_t initial_rt_latency = MIN(rt_latency + tmp, 0x3f);
+
+ uint8_t chanmask = 0;
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ ctrl->io_latency[channel][rank] = 0;
+ mchbar_write8(SC_ROUNDT_LAT_ch(channel) + rank, initial_rt_latency);
+ ctrl->rt_latency[channel][rank] = initial_rt_latency;
+ }
+
+ printk(BIOS_DEBUG, "Rank %u\n", rank);
+ printk(BIOS_DEBUG, "Steps 1 and 2: Find middle of high region\n");
+ printk(RCVEN_PLOT, "Byte");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(RCVEN_PLOT, "\t");
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ printk(RCVEN_PLOT, "%u ", byte);
+ }
+ printk(RCVEN_PLOT, "\nRcvEn\n");
+ struct phase_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
+ for (uint16_t rl_delay = RL_START; rl_delay < RL_STOP; rl_delay += RL_STEP) {
+ printk(RCVEN_PLOT, " % 3d", rl_delay);
+ program_rl_delays(ctrl, rank, rl_delay);
+ run_io_test(ctrl, chanmask, BASIC_VA, true);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(RCVEN_PLOT, "\t");
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ const bool high = sample_dqs(channel, byte);
+ printk(RCVEN_PLOT, high ? ". " : "# ");
+ phase_record_pass(
+ &region_data[channel][byte],
+ high,
+ rl_delay,
+ RL_START,
+ RL_STEP);
+ }
+ }
+ printk(RCVEN_PLOT, "\n");
+ }
+ printk(RCVEN_PLOT, "\n");
+ printk(BIOS_DEBUG, "Update RcvEn timing to be in the center of high region\n");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(BIOS_DEBUG, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\n",
+ channel, rank);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ struct phase_train_data *const curr_data =
+ &region_data[channel][byte];
+ phase_append_current_to_initial(curr_data, RL_START, RL_STEP);
+ const int32_t lwidth = range_width(curr_data->largest);
+ const int32_t center = range_center(curr_data->largest);
+ printk(BIOS_DEBUG, " B%u: \t%d\t%d\t%d\t%d\n",
+ byte,
+ curr_data->largest.start,
+ curr_data->largest.end,
+ lwidth,
+ center);
+
+ status = verify_high_region(center, lwidth);
+ if (status) {
+ printk(BIOS_ERR,
+ "RcvEn problems on channel %u, byte %u\n",
+ channel, byte);
+ goto clean_up;
+ }
+ ctrl->rcven[channel][rank][byte] = center;
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+
+ printk(BIOS_DEBUG, "Step 3: Quarter preamble - Walk backwards\n");
+ printk(RCVEN_PLOT, "Byte");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(RCVEN_PLOT, "\t");
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ printk(RCVEN_PLOT, "%u ", byte);
+ }
+ printk(RCVEN_PLOT, "\nIOLAT\n");
+ bool done = false;
+ while (!done) {
+ run_io_test(ctrl, chanmask, BASIC_VA, true);
+ done = true;
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(RCVEN_PLOT, " %2u\t", ctrl->io_latency[channel][rank]);
+ uint16_t highs = 0;
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ const bool high = sample_dqs(channel, byte);
+ printk(RCVEN_PLOT, high ? "H " : "L ");
+ if (high)
+ highs |= BIT(byte);
+ }
+ if (!highs)
+ continue;
+
+ done = false;
+
+ /* If all bytes sample high, adjust timing globally */
+ if (highs == bytemask && ctrl->io_latency[channel][rank] < 14) {
+ ctrl->io_latency[channel][rank] += 2;
+ ctrl->io_latency[channel][rank] %= 16;
+ program_io_latency(ctrl, channel, rank);
+ continue;
+ }
+
+ /* Otherwise, adjust individual bytes */
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ if (!(highs & BIT(byte)))
+ continue;
+
+ if (ctrl->rcven[channel][rank][byte] < 128) {
+ printk(BIOS_ERR,
+ "RcvEn underflow: walking backwards\n");
+ printk(BIOS_ERR,
+ "For channel %u, rank %u, byte %u\n",
+ channel, rank, byte);
+ status = RAMINIT_STATUS_RCVEN_FAILURE;
+ goto clean_up;
+ }
+ ctrl->rcven[channel][rank][byte] -= 128;
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+ }
+ }
+ printk(RCVEN_PLOT, "\n");
+ }
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(BIOS_DEBUG, "\nC%u: Preamble\n", channel);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ printk(BIOS_DEBUG,
+ " B%u: %u\n", byte, ctrl->rcven[channel][rank][byte]);
+ }
+ }
+ printk(BIOS_DEBUG, "\n");
+
+ printk(BIOS_DEBUG, "Step 4: Add 1 qclk\n");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ ctrl->rcven[channel][rank][byte] += 64;
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+ }
+ }
+ printk(BIOS_DEBUG, "\n");
+
+ printk(BIOS_DEBUG, "Step 5: Walk forward to find rising edge\n");
+ printk(RCVEN_PLOT, "Byte");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(RCVEN_PLOT, "\t");
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ printk(RCVEN_PLOT, "%u ", byte);
+ }
+ printk(RCVEN_PLOT, "\n inc\n");
+ uint16_t ch_result[NUM_CHANNELS] = { 0 };
+ uint8_t inc_preamble[NUM_CHANNELS][NUM_LANES] = { 0 };
+ for (uint8_t inc = 0; inc < 64; inc += fine_step) {
+ printk(RCVEN_PLOT, " %2u\t", inc);
+ run_io_test(ctrl, chanmask, BASIC_VA, true);
+ done = true;
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ if (ch_result[channel] & BIT(byte)) {
+ /* Skip bytes that are already done */
+ printk(RCVEN_PLOT, ". ");
+ continue;
+ }
+ const bool pass = sample_dqs(channel, byte);
+ printk(RCVEN_PLOT, pass ? ". " : "# ");
+ if (pass) {
+ ch_result[channel] |= BIT(byte);
+ continue;
+ }
+ ctrl->rcven[channel][rank][byte] += fine_step;
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+ inc_preamble[channel][byte] = inc;
+ }
+ printk(RCVEN_PLOT, "\t");
+ if (ch_result[channel] != bytemask)
+ done = false;
+ }
+ printk(RCVEN_PLOT, "\n");
+ if (done)
+ break;
+ }
+ printk(BIOS_DEBUG, "\n");
+ if (!done) {
+ printk(BIOS_ERR, "Error: Preamble edge not found for all bytes\n");
+ printk(BIOS_ERR, "The final RcvEn results are as follows:\n");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(BIOS_ERR, "Channel %u Rank %u: preamble\n",
+ channel, rank);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ printk(BIOS_ERR, " Byte %u: %u%s\n", byte,
+ ctrl->rcven[channel][rank][byte],
+ (ch_result[channel] ^ bytemask) & BIT(byte)
+ ? ""
+ : " *** Check this byte! ***");
+ }
+ }
+ status = RAMINIT_STATUS_RCVEN_FAILURE;
+ goto clean_up;
+ }
+
+ printk(BIOS_DEBUG, "Step 6: center on preamble and clean up rank\n");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(BIOS_DEBUG, "C%u: Preamble increment\n", channel);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ /*
+ * For Traditional, pull in RcvEn by 64. For ULT, take the DQS
+ * drift into account to the specified guardband: tDQSCK_DRIFT.
+ */
+ ctrl->rcven[channel][rank][byte] -= tDQSCK_DRIFT;
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+ printk(BIOS_DEBUG, " B%u: %u %u\n", byte,
+ ctrl->rcven[channel][rank][byte],
+ inc_preamble[channel][byte]);
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+
+clean_up:
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ if (ctrl->lpddr) {
+ /**
+ * W/A for b4618574 - @todo: remove for HSW ULT C0
+ * Can't have force_odt_on together with leaker, disable LPDDR mode for
+ * this training step. This write will disable force_odt_on while still
+ * keeping LPDDR mode disabled. Second write will restore LPDDR mode.
+ */
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = ctrl->dq_control_0[channel],
+ };
+ data_control_0.lpddr_mode = 0;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ }
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ mchbar_write32(DQ_CONTROL_2(channel, byte),
+ ctrl->dq_control_2[channel][byte]);
+ }
+ }
+ io_reset();
+ if (status)
+ return status;
+
+ printk(BIOS_DEBUG, "Step 7: Sync IO latency across all ranks\n");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ status = change_rcven_timing(ctrl, channel);
+ if (status)
+ return status;
+ }
+ printk(BIOS_DEBUG, "\nFinal Receive Enable and IO latency settings:\n");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ const union sc_io_latency_reg sc_io_latency = {
+ .raw = mchbar_read32(SC_IO_LATENCY_ch(channel)),
+ };
+ printk(BIOS_DEBUG, " C%u.R%u: IOLAT = %u rt_iocomp = %u\n", channel,
+ rank, ctrl->io_latency[channel][rank], sc_io_latency.rt_iocomp);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ printk(BIOS_DEBUG, " B%u: %u\n", byte,
+ ctrl->rcven[channel][rank][byte]);
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+ }
+ return status;
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index a81559bb1e..9172d4f2b0 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -18,6 +18,8 @@
#define RX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0000, ch, rank, byte)
#define TX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0020, ch, rank, byte)
+#define DDR_DATA_TRAIN_FEEDBACK(ch, byte) _DDRIO_C_R_B(0x0054, ch, 0, byte)
+
#define DQ_CONTROL_2(ch, byte) _DDRIO_C_R_B(0x0064, ch, 0, byte)
#define DQ_CONTROL_0(ch, byte) _DDRIO_C_R_B(0x0074, ch, 0, byte)
@@ -100,6 +102,7 @@
#define COMMAND_RATE_LIMIT_ch(ch) _MCMAIN_C(0x4010, ch)
#define TC_BANK_RANK_D_ch(ch) _MCMAIN_C(0x4014, ch)
#define SC_ROUNDT_LAT_ch(ch) _MCMAIN_C(0x4024, ch)
+#define SC_IO_LATENCY_ch(ch) _MCMAIN_C(0x4028, ch)
#define REUT_ch_PAT_WDB_CL_MUX_CFG(ch) _MCMAIN_C(0x4040, ch)
--
2.39.5
@@ -1,272 +0,0 @@
From fc6c3edf561dd11eeb2ebe7f4cb93542e664935a Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 11:58:59 +0200
Subject: [PATCH 41/51] haswell NRI: Add function to change margins
Implement a function to change margin parameters. Haswell provides a
register to apply an offset to margin parameters during training, so
make use of it. There are other margin parameters that have not been
implemented yet, as they are not needed for now and special handling
is needed to provide offset training functionality.
Change-Id: I5392380e13de3c44e77b7bc9f3b819e2661d1e2d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../haswell/native_raminit/change_margin.c | 136 ++++++++++++++++++
.../haswell/native_raminit/raminit_native.h | 39 +++++
.../haswell/native_raminit/reg_structs.h | 12 ++
.../intel/haswell/registers/mchbar.h | 1 +
4 files changed, 188 insertions(+)
diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
index 055c666eee..299c44a6b0 100644
--- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <assert.h>
#include <commonlib/bsd/clamp.h>
#include <console/console.h>
#include <delay.h>
@@ -152,3 +153,138 @@ void download_regfile(
ddr_data_control_0.read_rf_rank = phys_rank;
mchbar_write32(reg, ddr_data_control_0.raw);
}
+
+static void update_data_offset_train(
+ struct sysinfo *ctrl,
+ const uint8_t param,
+ const uint8_t en_multicast,
+ const uint8_t channel_in,
+ const uint8_t rank,
+ const uint8_t byte_in,
+ const bool update_ctrl,
+ const enum regfile_mode regfile,
+ const uint32_t value)
+{
+ bool is_rd = false;
+ bool is_wr = false;
+ switch (param) {
+ case RdT:
+ case RdV:
+ case RcvEna:
+ is_rd = true;
+ break;
+ case WrT:
+ case WrDqsT:
+ is_wr = true;
+ break;
+ default:
+ die("%s: Invalid margin parameter %u\n", __func__, param);
+ }
+ if (en_multicast) {
+ mchbar_write32(DDR_DATA_OFFSET_TRAIN, value);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ download_regfile(ctrl, channel, true, rank, regfile, 0, is_rd, is_wr);
+ if (update_ctrl) {
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ ctrl->data_offset_train[channel][byte] = value;
+ }
+ }
+ } else {
+ mchbar_write32(DDR_DATA_OFFSET_TRAIN_ch_b(channel_in, byte_in), value);
+ download_regfile(ctrl, channel_in, false, rank, regfile, byte_in, is_rd, is_wr);
+ if (update_ctrl)
+ ctrl->data_offset_train[channel_in][byte_in] = value;
+ }
+}
+
+static uint32_t get_max_margin(const enum margin_parameter param)
+{
+ switch (param) {
+ case RcvEna:
+ case RdT:
+ case WrT:
+ case WrDqsT:
+ return MAX_POSSIBLE_TIME;
+ case RdV:
+ return MAX_POSSIBLE_VREF;
+ default:
+ die("%s: Invalid margin parameter %u\n", __func__, param);
+ }
+}
+
+void change_margin(
+ struct sysinfo *ctrl,
+ const enum margin_parameter param,
+ const int32_t value0,
+ const bool en_multicast,
+ const uint8_t channel,
+ const uint8_t rank,
+ const uint8_t byte,
+ const bool update_ctrl,
+ const enum regfile_mode regfile)
+{
+ /** FIXME: Remove this **/
+ if (rank == 0xff)
+ die("%s: rank is 0xff\n", __func__);
+
+ if (!en_multicast && !does_ch_exist(ctrl, channel))
+ die("%s: Tried to change margin of empty channel %u\n", __func__, channel);
+
+ const uint32_t max_value = get_max_margin(param);
+ const int32_t v0 = clamp_s32(-max_value, value0, max_value);
+
+ union ddr_data_offset_train_reg ddr_data_offset_train = {
+ .raw = en_multicast ? 0 : ctrl->data_offset_train[channel][byte],
+ };
+ bool update_offset_train = false;
+ switch (param) {
+ case RcvEna:
+ ddr_data_offset_train.rcven = v0;
+ update_offset_train = true;
+ break;
+ case RdT:
+ ddr_data_offset_train.rx_dqs = v0;
+ update_offset_train = true;
+ break;
+ case WrT:
+ ddr_data_offset_train.tx_dq = v0;
+ update_offset_train = true;
+ break;
+ case WrDqsT:
+ ddr_data_offset_train.tx_dqs = v0;
+ update_offset_train = true;
+ break;
+ case RdV:
+ ddr_data_offset_train.vref = v0;
+ update_offset_train = true;
+ break;
+ default:
+ die("%s: Invalid margin parameter %u\n", __func__, param);
+ }
+ if (update_offset_train) {
+ update_data_offset_train(
+ ctrl,
+ param,
+ en_multicast,
+ channel,
+ rank,
+ byte,
+ update_ctrl,
+ regfile,
+ ddr_data_offset_train.raw);
+ }
+}
+
+void change_1d_margin_multicast(
+ struct sysinfo *ctrl,
+ const enum margin_parameter param,
+ const int32_t value0,
+ const uint8_t rank,
+ const bool update_ctrl,
+ const enum regfile_mode regfile)
+{
+ change_margin(ctrl, param, value0, true, 0, rank, 0, update_ctrl, regfile);
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index eaaaedad1e..1c8473056b 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -36,6 +36,18 @@
#define RTTNOM_MASK (BIT(9) | BIT(6) | BIT(2))
+/* Margin parameter limits */
+#define MAX_POSSIBLE_TIME 31
+#define MAX_POSSIBLE_VREF 54
+
+#define MAX_POSSIBLE_BOTH MAX_POSSIBLE_VREF
+
+#define MIN_TIME (-MAX_POSSIBLE_TIME)
+#define MAX_TIME (MAX_POSSIBLE_TIME)
+
+#define MIN_VREF (-MAX_POSSIBLE_VREF)
+#define MAX_VREF (MAX_POSSIBLE_VREF)
+
#define BASIC_VA_PAT_SPREAD_8 0x01010101
#define WDB_CACHE_LINE_SIZE 8
@@ -46,6 +58,14 @@
/* Specified in PI ticks. 64 PI ticks == 1 qclk */
#define tDQSCK_DRIFT 64
+enum margin_parameter {
+ RcvEna,
+ RdT,
+ WrT,
+ WrDqsT,
+ RdV,
+};
+
/* ZQ calibration types */
enum {
ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */
@@ -515,6 +535,25 @@ void download_regfile(
bool read_rf_rd,
bool read_rf_wr);
+void change_margin(
+ struct sysinfo *ctrl,
+ const enum margin_parameter param,
+ const int32_t value0,
+ const bool en_multicast,
+ const uint8_t channel,
+ const uint8_t rank,
+ const uint8_t byte,
+ const bool update_ctrl,
+ const enum regfile_mode regfile);
+
+void change_1d_margin_multicast(
+ struct sysinfo *ctrl,
+ const enum margin_parameter param,
+ const int32_t value0,
+ const uint8_t rank,
+ const bool update_ctrl,
+ const enum regfile_mode regfile);
+
uint8_t get_rx_bias(const struct sysinfo *ctrl);
uint8_t get_tCWL(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index b099f4bb82..a0e36ed082 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -25,6 +25,18 @@ union ddr_data_tx_train_rank_reg {
uint32_t raw;
};
+union ddr_data_offset_train_reg {
+ struct __packed {
+ int32_t rcven : 6; // Bits 5:0
+ int32_t rx_dqs : 6; // Bits 11:6
+ int32_t tx_dq : 6; // Bits 17:12
+ int32_t tx_dqs : 6; // Bits 23:18
+ int32_t vref : 7; // Bits 30:24
+ int32_t : 1; // Bits 31:31
+ };
+ uint32_t raw;
+};
+
union ddr_data_control_0_reg {
struct __packed {
uint32_t rx_training_mode : 1; // Bits 0:0
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 9172d4f2b0..0acafbc826 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -21,6 +21,7 @@
#define DDR_DATA_TRAIN_FEEDBACK(ch, byte) _DDRIO_C_R_B(0x0054, ch, 0, byte)
#define DQ_CONTROL_2(ch, byte) _DDRIO_C_R_B(0x0064, ch, 0, byte)
+#define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte) _DDRIO_C_R_B(0x0070, ch, 0, byte)
#define DQ_CONTROL_0(ch, byte) _DDRIO_C_R_B(0x0074, ch, 0, byte)
/* DDR CKE per-channel */
--
2.39.5
@@ -0,0 +1,30 @@
From 5b7bbc6fcc6f737f259906f1919c1e28b6628a7e Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sat, 20 Dec 2025 22:36:18 +0100
Subject: [PATCH 41/48] tests/Makefile.mk: use 3rdparty/cmocka by default
(tests)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
tests/Makefile.mk | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/Makefile.mk b/tests/Makefile.mk
index 9e3f86a138..a5a518cd35 100644
--- a/tests/Makefile.mk
+++ b/tests/Makefile.mk
@@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage
endif
# Use system cmoka in default, or build from 3rdparty source code if requested
-USE_SYSTEM_CMOCKA ?= 1
+# PATCH NOTE: lbmk sets it to 0 by default. You can still override it to 1
+# if you wish; upstream sets this to 1 by default, but we do 0
+USE_SYSTEM_CMOCKA ?= 0
ifeq ($(USE_SYSTEM_CMOCKA),1)
ifeq ($(shell $(HOSTPKG_CONFIG) --exists cmocka || echo 1),1)
$(warning No system cmocka, build from 3rdparty instead...)
--
2.47.3
@@ -1,332 +0,0 @@
From 8f07ea076572dd3371dca7b3dbd5ff9c9b332c55 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 11:35:49 +0200
Subject: [PATCH 42/51] haswell NRI: Add read MPR training
Implement read training using DDR3 MPR (Multi-Purpose Register).
Change-Id: Id17cb2c4c399ac9bcc937b595b58f863c152461b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../haswell/native_raminit/raminit_main.c | 1 +
.../haswell/native_raminit/raminit_native.h | 4 +
.../haswell/native_raminit/train_read_mpr.c | 241 ++++++++++++++++++
.../intel/haswell/registers/mchbar.h | 2 +-
5 files changed, 248 insertions(+), 1 deletion(-)
create mode 100644 src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index e2fbfb4211..c442be0728 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -16,4 +16,5 @@ romstage-y += setup_wdb.c
romstage-y += spd_bitmunching.c
romstage-y += testing_io.c
romstage-y += timings_refresh.c
+romstage-y += train_read_mpr.c
romstage-y += train_receive_enable.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 7d444659c3..264d1468f5 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -61,6 +61,7 @@ static const struct task_entry cold_boot[] = {
{ do_jedec_init, true, "JEDECINIT", },
{ pre_training, true, "PRETRAIN", },
{ train_receive_enable, true, "RCVET", },
+ { train_read_mpr, true, "RDMPRT", },
};
/* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 1c8473056b..7a486479ea 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -28,6 +28,8 @@
/* Always use 12 legs for emphasis (not trained) */
#define TXEQFULLDRV (3 << 4)
+#define LOOPCOUNT_INFINITE 0xff
+
/* DDR3 mode register bits */
#define MR0_DLL_RESET BIT(8)
@@ -213,6 +215,7 @@ enum raminit_status {
RAMINIT_STATUS_POLL_TIMEOUT,
RAMINIT_STATUS_REUT_ERROR,
RAMINIT_STATUS_RCVEN_FAILURE,
+ RAMINIT_STATUS_RMPR_FAILURE,
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
};
@@ -434,6 +437,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
enum raminit_status configure_memory_map(struct sysinfo *ctrl);
enum raminit_status do_jedec_init(struct sysinfo *ctrl);
enum raminit_status train_receive_enable(struct sysinfo *ctrl);
+enum raminit_status train_read_mpr(struct sysinfo *ctrl);
void configure_timings(struct sysinfo *ctrl);
void configure_refresh(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
new file mode 100644
index 0000000000..ade1e36148
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+#include "ranges.h"
+
+#define RMPR_START (-32)
+#define RMPR_STOP (32)
+#define RMPR_STEP 1
+
+#define RMPR_MIN_WIDTH 12
+
+#define RMPR_PLOT RAM_DEBUG
+
+/*
+ * Clear rx_training_mode. For LPDDR, we first need to disable odt_samp_extend_en,
+ * then disable rx_training_mode, and finally re-enable odt_samp_extend_en.
+ */
+static void clear_rx_training_mode(struct sysinfo *ctrl, const uint8_t channel)
+{
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ mchbar_write32(DQ_CONTROL_2(channel, byte), ctrl->dq_control_2[channel][byte]);
+
+ if (ctrl->lpddr) {
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = mchbar_read32(DDR_DATA_ch_CONTROL_0(channel)),
+ };
+ data_control_0.odt_samp_extend_en = 0;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ tick_delay(1);
+ data_control_0.rx_training_mode = 0;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ tick_delay(1);
+ }
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+}
+
+static void set_rxdqs_edges_to_midpoint(struct sysinfo *ctrl)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ update_rxt(ctrl, channel, rank, byte, RXT_RXDQS_BOTH, 32);
+ }
+ }
+}
+
+static void enter_mpr_train_ddr_mode(struct sysinfo *ctrl, const uint8_t rank)
+{
+ /* Program MR3 and mask RAS/WE to prevent scheduler from issuing non-read commands */
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ if (!ctrl->lpddr)
+ reut_issue_mrs(ctrl, channel, BIT(rank), 3, 1 << 2);
+
+ union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
+ .raw = mchbar_read32(REUT_ch_MISC_ODT_CTRL(channel)),
+ };
+ reut_misc_odt_ctrl.mpr_train_ddr_on = 1;
+ mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
+ }
+}
+
+static void leave_mpr_train_ddr_mode(struct sysinfo *ctrl, const uint8_t rank)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ /*
+ * The mpr_train_ddr_on bit will force a special command.
+ * Therefore, clear it before issuing the MRS command.
+ */
+ union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
+ .raw = mchbar_read32(REUT_ch_MISC_ODT_CTRL(channel)),
+ };
+ reut_misc_odt_ctrl.mpr_train_ddr_on = 0;
+ mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
+ if (!ctrl->lpddr)
+ reut_issue_mrs(ctrl, channel, BIT(rank), 3, 0 << 2);
+ }
+}
+
+enum raminit_status train_read_mpr(struct sysinfo *ctrl)
+{
+ set_rxdqs_edges_to_midpoint(ctrl);
+ clear_data_offset_train_all(ctrl);
+ setup_io_test_mpr(ctrl, ctrl->chanmap, LOOPCOUNT_INFINITE, NSOE);
+ enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!does_rank_exist(ctrl, rank))
+ continue;
+
+ printk(BIOS_DEBUG, "Rank %u\n", rank);
+ printk(RMPR_PLOT, "Channel");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(RMPR_PLOT, "\t%u\t\t", channel);
+ }
+ printk(RMPR_PLOT, "\nByte");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(RMPR_PLOT, "\t");
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ printk(RMPR_PLOT, "%u ", byte);
+ }
+ enter_mpr_train_ddr_mode(ctrl, rank);
+ struct linear_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
+ select_reut_ranks(ctrl, channel, BIT(rank));
+
+ printk(RMPR_PLOT, "\nDqsDelay\n");
+ int8_t dqs_delay;
+ for (dqs_delay = RMPR_START; dqs_delay < RMPR_STOP; dqs_delay += RMPR_STEP) {
+ printk(RMPR_PLOT, "% 5d", dqs_delay);
+ const enum regfile_mode regfile = REG_FILE_USE_START;
+ /* Looks like MRC uses rank 0 here, but it feels wrong */
+ change_1d_margin_multicast(ctrl, RdT, dqs_delay, rank, false, regfile);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ union ddr_data_control_2_reg data_control_2 = {
+ .raw = ctrl->dq_control_2[channel][byte],
+ };
+ data_control_2.force_bias_on = 1;
+ data_control_2.force_rx_on = 1;
+ data_control_2.leaker_comp = 0;
+ mchbar_write32(DQ_CONTROL_2(channel, byte),
+ data_control_2.raw);
+ }
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = ctrl->dq_control_0[channel],
+ };
+ data_control_0.rx_training_mode = 1;
+ data_control_0.force_odt_on = !ctrl->lpddr;
+ data_control_0.en_read_preamble = 0;
+ data_control_0.odt_samp_extend_en = ctrl->lpddr;
+ const uint32_t reg_offset = DDR_DATA_ch_CONTROL_0(channel);
+ mchbar_write32(reg_offset, data_control_0.raw);
+ }
+ run_mpr_io_test(false);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(RMPR_PLOT, "\t");
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ uint32_t fb = get_data_train_feedback(channel, byte);
+ const bool pass = fb == 1;
+ printk(RMPR_PLOT, pass ? ". " : "# ");
+ linear_record_pass(
+ &region_data[channel][byte],
+ pass,
+ dqs_delay,
+ RMPR_START,
+ RMPR_STEP);
+ }
+ }
+ printk(RMPR_PLOT, "\n");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ clear_rx_training_mode(ctrl, channel);
+ }
+ io_reset();
+ }
+ printk(RMPR_PLOT, "\n");
+ leave_mpr_train_ddr_mode(ctrl, rank);
+ clear_data_offset_train_all(ctrl);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(BIOS_DEBUG, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\tRxDqsPN\n",
+ channel, rank);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ struct linear_train_data *data = &region_data[channel][byte];
+ const int32_t lwidth = range_width(data->largest);
+ if (lwidth <= RMPR_MIN_WIDTH) {
+ printk(BIOS_ERR,
+ "Bad eye (lwidth %d <= min %d) for byte %u\n",
+ lwidth, RMPR_MIN_WIDTH, byte);
+ status = RAMINIT_STATUS_RMPR_FAILURE;
+ }
+ /*
+ * The MPR center may not be ideal on certain platforms for
+ * unknown reasons. If so, adjust it with a magical number.
+ * For Haswell, the magical number is zero. Hell knows why.
+ */
+ const int32_t center = range_center(data->largest);
+ ctrl->rxdqsp[channel][rank][byte] = center - RMPR_START;
+ ctrl->rxdqsn[channel][rank][byte] = center - RMPR_START;
+ printk(BIOS_DEBUG, " B%u: \t%d\t%d\t%d\t%d\t%u\n", byte,
+ data->largest.start, data->largest.end, lwidth,
+ center, ctrl->rxdqsp[channel][rank][byte]);
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+ }
+
+ /*
+ * Now program the DQS center values on populated ranks. data is taken from
+ * the host struct. We need to do it after all ranks are trained, because we
+ * need to keep the same DQS value on all ranks during the training procedure.
+ */
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+ }
+ }
+ change_1d_margin_multicast(ctrl, RdT, 0, 0, false, REG_FILE_USE_CURRENT);
+ io_reset();
+ return status;
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 0acafbc826..6a31d3a32c 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -122,7 +122,7 @@
#define REUT_ch_ERR_DATA_MASK(ch) _MCMAIN_C(0x40d8, ch)
#define REUT_ch_MISC_CKE_CTRL(ch) _MCMAIN_C(0x4190, ch)
-
+#define REUT_ch_MISC_ODT_CTRL(ch) _MCMAIN_C(0x4194, ch)
#define REUT_ch_MISC_PAT_CADB_CTRL(ch) _MCMAIN_C(0x4198, ch)
#define REUT_ch_PAT_CADB_MRS(ch) _MCMAIN_C(0x419c, ch)
#define REUT_ch_PAT_CADB_MUX_CTRL(ch) _MCMAIN_C(0x41a0, ch)
--
2.39.5
@@ -0,0 +1,51 @@
From ecbf5a133d839b6c8579e384e9db0a036eca939d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 23 Dec 2025 18:41:27 +0100
Subject: [PATCH 42/48] mb/dell/optiplex_780: use legacy HDA verb table
See:
commit 31fc5b06a6be62b30739d33eeabe6c2727679bb1
Author: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu Aug 7 08:31:24 2025 +0900
device: Introduce reworked azalia verb table
and:
commit 50a59d4464917503847eeeb2df4320c35cf2f6cc
Author: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Mon Sep 15 16:25:21 2025 +0900
device: Add Kconfig to prepare for reworked verb table implementation
Without this change, lbmk gets the following error
when building for Dell OptiPlex 780:
i386-elf-ld.bfd: build/ramstage/device/azalia_device.o: in function `azalia_codecs_init':
/path/to/corebootclone/src/device/azalia_device.c:318:(.text.azalia_codecs_init+0xa): undefined reference to `mainboard_azalia_codecs'
This is a temporary fix. Upstream will require that the code
be fully adapted at a future date. Therefore, one could consider
the current functionality to be "deprecated".
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/optiplex_780/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
index fc649e35d5..172bb2fa87 100644
--- a/src/mainboard/dell/optiplex_780/Kconfig
+++ b/src/mainboard/dell/optiplex_780/Kconfig
@@ -2,6 +2,7 @@
config BOARD_DELL_OPTIPLEX_780_COMMON
def_bool n
+ select AZALIA_USE_LEGACY_VERB_TABLE
select BOARD_ROMSIZE_KB_8192
select CPU_INTEL_SOCKET_LGA775
select DRIVERS_I2C_CK505
--
2.47.3
@@ -1,689 +0,0 @@
From 6df4b7eb0512c24a5f53bc92e81ad6cf42cd28a7 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 12:56:04 +0200
Subject: [PATCH 43/51] haswell NRI: Add write leveling
Implement JEDEC write leveling, which is done in two steps. The first
step uses the JEDEC procedure to do "fine" write leveling, i.e. align
the DQS phase to the clock signal. The second step performs a regular
read-write test to correct "coarse" cycle errors.
Change-Id: I27678523fe22c38173a688e2a4751c259a20f009
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../haswell/native_raminit/raminit_main.c | 1 +
.../haswell/native_raminit/raminit_native.h | 10 +
.../train_jedec_write_leveling.c | 581 ++++++++++++++++++
.../intel/haswell/registers/mchbar.h | 2 +
5 files changed, 595 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index c442be0728..40c2f5e014 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -16,5 +16,6 @@ romstage-y += setup_wdb.c
romstage-y += spd_bitmunching.c
romstage-y += testing_io.c
romstage-y += timings_refresh.c
+romstage-y += train_jedec_write_leveling.c
romstage-y += train_read_mpr.c
romstage-y += train_receive_enable.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 264d1468f5..1ff23be615 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -62,6 +62,7 @@ static const struct task_entry cold_boot[] = {
{ pre_training, true, "PRETRAIN", },
{ train_receive_enable, true, "RCVET", },
{ train_read_mpr, true, "RDMPRT", },
+ { train_jedec_write_leveling, true, "JWRL", },
};
/* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 7a486479ea..d6b11b9d3c 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -60,6 +60,9 @@
/* Specified in PI ticks. 64 PI ticks == 1 qclk */
#define tDQSCK_DRIFT 64
+/* Maximum additional latency */
+#define MAX_ADD_DELAY 2
+
enum margin_parameter {
RcvEna,
RdT,
@@ -216,6 +219,7 @@ enum raminit_status {
RAMINIT_STATUS_REUT_ERROR,
RAMINIT_STATUS_RCVEN_FAILURE,
RAMINIT_STATUS_RMPR_FAILURE,
+ RAMINIT_STATUS_JWRL_FAILURE,
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
};
@@ -381,6 +385,11 @@ static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint
return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte));
}
+static inline uint16_t get_byte_group_errors(const uint8_t channel)
+{
+ return mchbar_read32(4 + REUT_ch_ERR_MISC_STATUS(channel)) & 0x1ff;
+}
+
/* Number of ticks to wait in units of 69.841279 ns (citation needed) */
static inline void tick_delay(const uint32_t delay)
{
@@ -438,6 +447,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
enum raminit_status do_jedec_init(struct sysinfo *ctrl);
enum raminit_status train_receive_enable(struct sysinfo *ctrl);
enum raminit_status train_read_mpr(struct sysinfo *ctrl);
+enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
void configure_timings(struct sysinfo *ctrl);
void configure_refresh(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
new file mode 100644
index 0000000000..ef6483e2bd
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
@@ -0,0 +1,581 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+#include "ranges.h"
+
+#define JWLC_PLOT RAM_DEBUG
+#define JWRL_PLOT RAM_DEBUG
+
+static void reset_dram_dll(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
+{
+ const uint16_t mr0reg = ctrl->mr0[channel][rank / 2];
+ reut_issue_mrs(ctrl, channel, BIT(rank), 0, mr0reg | MR0_DLL_RESET);
+}
+
+static void program_wdb_pattern(struct sysinfo *ctrl, const bool invert)
+{
+ /* Pattern to keep DQ-DQS simple but detect any failures. Same as NHM/WSM. */
+ const uint8_t pat[4][2] = {
+ { 0x00, 0xff },
+ { 0xff, 0x00 },
+ { 0xc3, 0x3c },
+ { 0x3c, 0xc3 },
+ };
+ const uint8_t pmask[2][8] = {
+ { 0, 0, 1, 1, 1, 1, 0, 0 },
+ { 1, 1, 0, 0, 0, 0, 1, 1 },
+ };
+ for (uint8_t s = 0; s < ARRAY_SIZE(pat); s++)
+ write_wdb_fixed_pat(ctrl, pat[s], pmask[invert], ARRAY_SIZE(pmask[invert]), s);
+}
+
+static int16_t set_add_delay(uint32_t *add_delay, uint8_t rank, int8_t target_off)
+{
+ const uint8_t shift = rank * 2;
+ if (target_off > MAX_ADD_DELAY) {
+ *add_delay &= ~(3 << shift);
+ *add_delay |= MAX_ADD_DELAY << shift;
+ return 128 * (target_off - MAX_ADD_DELAY);
+ } else if (target_off < 0) {
+ *add_delay &= ~(3 << shift);
+ *add_delay |= 0 << shift;
+ return 128 * target_off;
+ } else {
+ *add_delay &= ~(3 << shift);
+ *add_delay |= target_off << shift;
+ return 0;
+ }
+}
+
+static enum raminit_status train_jedec_write_leveling_cleanup(struct sysinfo *ctrl)
+{
+ const struct reut_box reut_addr = {
+ .col = {
+ .start = 0,
+ .stop = 1023,
+ .inc_val = 1,
+ },
+ };
+ const struct wdb_pat wdb_pattern = {
+ .start_ptr = 0,
+ .stop_ptr = 3,
+ .inc_rate = 1,
+ .dq_pattern = BASIC_VA,
+ };
+ const int8_t offsets[] = { 0, 1, -1, 2, 3 };
+ const int8_t dq_offsets[] = { 0, -10, 10, -5, 5, -15, 15 };
+ const uint8_t dq_offset_max = ARRAY_SIZE(dq_offsets);
+
+ /* Set LFSR seeds to be sequential */
+ program_wdb_lfsr(ctrl, true);
+ setup_io_test(
+ ctrl,
+ ctrl->chanmap,
+ PAT_WR_RD,
+ 2,
+ 4,
+ &reut_addr,
+ NSOE,
+ &wdb_pattern,
+ 0,
+ 0);
+
+ const union reut_pat_wdb_cl_mux_cfg_reg reut_wdb_cl_mux_cfg = {
+ .mux_0_control = REUT_MUX_BTBUFFER,
+ .mux_1_control = REUT_MUX_BTBUFFER,
+ .mux_2_control = REUT_MUX_BTBUFFER,
+ .ecc_data_source_sel = 1,
+ };
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_CFG(channel), reut_wdb_cl_mux_cfg.raw);
+ }
+
+ int8_t byte_off[NUM_CHANNELS][NUM_LANES] = { 0 };
+ uint32_t add_delay[NUM_CHANNELS] = { 0 };
+ enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+ bool invert = false;
+ const uint16_t valid_byte_mask = BIT(ctrl->lanes) - 1;
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ uint8_t chanmask = 0;
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
+ chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
+
+ if (!chanmask)
+ continue;
+
+ printk(BIOS_DEBUG, "Rank %u\n", rank);
+ printk(JWLC_PLOT, "Channel");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(JWLC_PLOT, "\t\t%u\t", channel);
+ }
+ printk(JWLC_PLOT, "\nByte\t");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(JWLC_PLOT, "\t");
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ printk(JWLC_PLOT, "%u ", byte);
+ }
+ printk(JWLC_PLOT, "\nDelay DqOffset");
+ bool done = false;
+ int8_t byte_sum[NUM_CHANNELS] = { 0 };
+ uint16_t byte_pass[NUM_CHANNELS] = { 0 };
+ for (uint8_t off = 0; off < ARRAY_SIZE(offsets); off++) {
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ const int16_t global_byte_off =
+ set_add_delay(&add_delay[channel], rank, offsets[off]);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ update_txt(ctrl, channel, rank, byte, TXT_DQDQS_OFF,
+ global_byte_off);
+ }
+ mchbar_write32(SC_WR_ADD_DELAY_ch(channel),
+ add_delay[channel]);
+ }
+ /* Reset FIFOs and DRAM DLL (Micron workaround) */
+ if (!ctrl->lpddr) {
+ io_reset();
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ reset_dram_dll(ctrl, channel, rank);
+ }
+ udelay(1);
+ }
+ for (uint8_t dq_offset = 0; dq_offset < dq_offset_max; dq_offset++) {
+ printk(JWLC_PLOT, "\n% 3d\t% 3d",
+ offsets[off], dq_offsets[dq_offset]);
+ change_1d_margin_multicast(
+ ctrl,
+ WrT,
+ dq_offsets[dq_offset],
+ rank,
+ false,
+ REG_FILE_USE_RANK);
+
+ /*
+ * Re-program the WDB pattern. Change the pattern
+ * for the next test to avoid false pass issues.
+ */
+ program_wdb_pattern(ctrl, invert);
+ invert = !invert;
+ run_io_test(ctrl, chanmask, BASIC_VA, true);
+ done = true;
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(JWLC_PLOT, "\t");
+ uint16_t result = get_byte_group_errors(channel);
+ result &= valid_byte_mask;
+
+ /* Skip bytes that have failed or already passed */
+ const uint16_t skip_me = result | byte_pass[channel];
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ const bool pass = result & BIT(byte);
+ printk(JWLC_PLOT, pass ? "# " : ". ");
+ if (skip_me & BIT(byte))
+ continue;
+
+ byte_pass[channel] |= BIT(byte);
+ byte_off[channel][byte] = offsets[off];
+ byte_sum[channel] += offsets[off];
+ }
+ if (byte_pass[channel] != valid_byte_mask)
+ done = false;
+ }
+ if (done)
+ break;
+ }
+ if (done)
+ break;
+ }
+ printk(BIOS_DEBUG, "\n\n");
+ if (!done) {
+ printk(BIOS_ERR, "JWLC: Could not find a pass for all bytes\n");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(BIOS_ERR, "Channel %u, rank %u fail:", channel, rank);
+ const uint16_t passing_mask = byte_pass[channel];
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ if (BIT(byte) & passing_mask)
+ continue;
+
+ printk(BIOS_ERR, " %u", byte);
+ }
+ printk(BIOS_ERR, "\n");
+ }
+ status = RAMINIT_STATUS_JWRL_FAILURE;
+ break;
+ }
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ /* Refine target offset to make sure it works for all bytes */
+ int8_t target_off = DIV_ROUND_CLOSEST(byte_sum[channel], ctrl->lanes);
+ int16_t global_byte_off = 0;
+ uint8_t all_good_loops = 0;
+ bool all_good = 0;
+ while (!all_good) {
+ global_byte_off =
+ set_add_delay(&add_delay[channel], rank, target_off);
+ all_good = true;
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ int16_t local_offset;
+ local_offset = byte_off[channel][byte] - target_off;
+ local_offset = local_offset * 128 + global_byte_off;
+ const uint16_t tx_dq = ctrl->tx_dq[channel][rank][byte];
+ if (tx_dq + local_offset >= (512 - 64)) {
+ all_good = false;
+ all_good_loops++;
+ target_off++;
+ break;
+ }
+ const uint16_t txdqs = ctrl->tx_dq[channel][rank][byte];
+ if (txdqs + local_offset < 96) {
+ all_good = false;
+ all_good_loops++;
+ target_off--;
+ break;
+ }
+ }
+ /* Avoid an infinite loop */
+ if (all_good_loops > 3)
+ break;
+ }
+ if (!all_good) {
+ printk(BIOS_ERR, "JWLC: Target offset refining failed\n");
+ status = RAMINIT_STATUS_JWRL_FAILURE;
+ break;
+ }
+ printk(BIOS_DEBUG, "C%u.R%u: Offset\tFinalEdge\n", channel, rank);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ int16_t local_offset;
+ local_offset = byte_off[channel][byte] - target_off;
+ local_offset = local_offset * 128 + global_byte_off;
+ ctrl->tx_dq[channel][rank][byte] += local_offset;
+ ctrl->txdqs[channel][rank][byte] += local_offset;
+ update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
+ printk(BIOS_DEBUG, " B%u: %d\t%d\n", byte, local_offset,
+ ctrl->txdqs[channel][rank][byte]);
+ }
+ mchbar_write32(SC_WR_ADD_DELAY_ch(channel), add_delay[channel]);
+ if (!ctrl->lpddr) {
+ reset_dram_dll(ctrl, channel, rank);
+ udelay(1);
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+
+ /* Restore WDB after test */
+ write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
+ program_wdb_lfsr(ctrl, false);
+ mchbar_write32(DDR_DATA_OFFSET_TRAIN, 0);
+
+ /** TODO: Do full JEDEC init instead? **/
+ io_reset();
+ return status;
+}
+
+static enum raminit_status verify_wl_width(const int32_t lwidth)
+{
+ if (lwidth <= 32) {
+ /* Check if width is valid */
+ printk(BIOS_ERR, "WrLevel: Width region (%d) too small\n", lwidth);
+ return RAMINIT_STATUS_JWRL_FAILURE;
+ }
+ if (lwidth >= 96) {
+ /* Since we're calibrating a phase, a too large region is a problem */
+ printk(BIOS_ERR, "WrLevel: Width region (%d) too large\n", lwidth);
+ return RAMINIT_STATUS_JWRL_FAILURE;
+ }
+ return 0;
+}
+
+enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl)
+{
+ /*
+ * Enabling WL mode causes DQS to toggle for 1024 QCLK.
+ * Wait for this to stop. Round up to nearest microsecond.
+ */
+ const bool wl_long_delay = ctrl->lpddr;
+ const uint32_t dqs_toggle_time = wl_long_delay ? 2048 : 1024;
+ const uint32_t wait_time_us = DIV_ROUND_UP(ctrl->qclkps * dqs_toggle_time, 1000 * 1000);
+
+ const uint16_t wl_start = 192;
+ const uint16_t wl_stop = 192 + 128;
+ const uint16_t wl_step = 2;
+
+ /* Do not use cached MR values */
+ const bool save_restore_mrs = ctrl->restore_mrs;
+ ctrl->restore_mrs = 0;
+
+ /* Propagate delay values (without a write command) */
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ /* Propagate delay values from rank 0 to prevent assertion failures in RTL */
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = ctrl->dq_control_0[channel],
+ };
+ data_control_0.read_rf_rd = 0;
+ data_control_0.read_rf_wr = 1;
+ data_control_0.read_rf_rank = 0;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ union ddr_data_control_2_reg data_control_2 = {
+ .raw = ctrl->dq_control_2[channel][byte],
+ };
+ data_control_2.force_bias_on = 1;
+ data_control_2.force_rx_on = 0;
+ data_control_2.wl_long_delay = wl_long_delay;
+ mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
+ }
+ }
+
+ if (ctrl->lpddr)
+ die("%s: Missing LPDDR support\n", __func__);
+
+ if (!ctrl->lpddr)
+ ddr3_program_mr1(ctrl, 0, 1);
+
+ enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+ struct phase_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!does_rank_exist(ctrl, rank))
+ continue;
+
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ /** TODO: Differs for LPDDR **/
+ uint16_t mr1reg = ctrl->mr1[channel][rank / 2];
+ mr1reg &= ~MR1_QOFF_ENABLE;
+ mr1reg |= MR1_WL_ENABLE;
+ if (is_hsw_ult()) {
+ mr1reg &= ~RTTNOM_MASK;
+ mr1reg |= encode_ddr3_rttnom(120);
+ } else if (ctrl->dpc[channel] == 2) {
+ mr1reg &= ~RTTNOM_MASK;
+ mr1reg |= encode_ddr3_rttnom(60);
+ }
+ reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
+
+ /* Assert ODT for myself */
+ uint8_t odt_matrix = BIT(rank);
+ if (ctrl->dpc[channel] == 2) {
+ /* Assert ODT for non-target DIMM */
+ const uint8_t other_dimm = ((rank + 2) / 2) & 1;
+ odt_matrix |= BIT(2 * other_dimm);
+ }
+
+ union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
+ .raw = 0,
+ };
+ if (ctrl->lpddr) {
+ /* Only one ODT pin for ULT */
+ reut_misc_odt_ctrl.odt_on = 1;
+ reut_misc_odt_ctrl.odt_override = 1;
+ } else if (!is_hsw_ult()) {
+ reut_misc_odt_ctrl.odt_on = odt_matrix;
+ reut_misc_odt_ctrl.odt_override = 0xf;
+ }
+ mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
+ }
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ /*
+ * Enable write leveling mode in DDR and propagate delay
+ * values (without a write command). Stay in WL mode.
+ */
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = ctrl->dq_control_0[channel],
+ };
+ data_control_0.wl_training_mode = 1;
+ data_control_0.tx_pi_on = 1;
+ data_control_0.read_rf_rd = 0;
+ data_control_0.read_rf_wr = 1;
+ data_control_0.read_rf_rank = rank;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ }
+ printk(BIOS_DEBUG, "\nRank %u\n", rank);
+ printk(JWRL_PLOT, "Channel\t");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(JWRL_PLOT, "%u", channel);
+ if (channel > 0)
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ printk(JWRL_PLOT, "\t");
+ }
+ printk(JWRL_PLOT, "\nByte");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ printk(JWRL_PLOT, "\t%u", byte);
+ }
+ printk(JWRL_PLOT, "\nWlDelay");
+ for (uint16_t wl_delay = wl_start; wl_delay < wl_stop; wl_delay += wl_step) {
+ printk(JWRL_PLOT, "\n %3u:", wl_delay);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ update_txt(ctrl, channel, rank, byte, TXT_TXDQS,
+ wl_delay);
+ }
+ }
+ /* Wait for the first burst to finish */
+ if (wl_delay == wl_start)
+ udelay(wait_time_us);
+
+ io_reset();
+ udelay(wait_time_us);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ const uint32_t feedback =
+ get_data_train_feedback(channel, byte);
+ const bool pass = (feedback & 0x1ff) >= 16;
+ printk(JWRL_PLOT, "\t%c%u", pass ? '.' : '#', feedback);
+ phase_record_pass(
+ &region_data[channel][byte],
+ pass,
+ wl_delay,
+ wl_start,
+ wl_step);
+ }
+ }
+ }
+ printk(JWRL_PLOT, "\n");
+ printk(BIOS_DEBUG, "\n\tInitSt\tInitEn\tCurrSt\tCurrEn\tLargSt\tLargEn\n");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ printk(BIOS_DEBUG, "C%u\n", channel);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ struct phase_train_data *data = &region_data[channel][byte];
+
+ phase_append_initial_to_current(data, wl_start, wl_step);
+ printk(BIOS_DEBUG, " B%u:\t%d\t%d\t%d\t%d\t%d\t%d\n",
+ byte,
+ data->initial.start,
+ data->initial.end,
+ data->current.start,
+ data->current.end,
+ data->largest.start,
+ data->largest.end);
+ }
+ }
+
+ /*
+ * Clean up after test. Very coarsely adjust for
+ * any cycle errors. Program values for TxDQS.
+ */
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ /* Clear ODT before MRS (JEDEC spec) */
+ mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), 0);
+
+ /** TODO: Differs for LPDDR **/
+ const uint16_t mr1reg = ctrl->mr1[channel][rank / 2] | MR1_QOFF_ENABLE;
+ reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
+
+ printk(BIOS_DEBUG, "\nC%u.R%u: LftEdge Width\n", channel, rank);
+ const bool rank_x16 = ctrl->dimms[channel][rank / 2].data.width == 16;
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ struct phase_train_data *data = &region_data[channel][byte];
+ const int32_t lwidth = range_width(data->largest);
+ int32_t tx_start = data->largest.start;
+ printk(BIOS_DEBUG, " B%u: %d\t%d\n", byte, tx_start, lwidth);
+ status = verify_wl_width(lwidth);
+ if (status) {
+ printk(BIOS_ERR,
+ "WrLevel problems on channel %u, byte %u\n",
+ channel, byte);
+ goto clean_up;
+ }
+
+ /* Align byte pairs if DIMM is x16 */
+ if (rank_x16 && (byte & 1)) {
+ const struct phase_train_data *const ref_data =
+ &region_data[channel][byte - 1];
+
+ if (tx_start > ref_data->largest.start + 64)
+ tx_start -= 128;
+
+ if (tx_start < ref_data->largest.start - 64)
+ tx_start += 128;
+ }
+
+ /* Fix for b4618067 - need to add 1 QCLK to DQS PI */
+ if (is_hsw_ult())
+ tx_start += 64;
+
+ assert(tx_start >= 0);
+ ctrl->txdqs[channel][rank][byte] = tx_start;
+ ctrl->tx_dq[channel][rank][byte] = tx_start + 32;
+ update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
+ }
+ }
+ printk(BIOS_DEBUG, "\n");
+ }
+
+clean_up:
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ mchbar_write32(DQ_CONTROL_2(channel, byte),
+ ctrl->dq_control_2[channel][byte]);
+ }
+ }
+ if (!ctrl->lpddr)
+ ddr3_program_mr1(ctrl, 0, 0);
+
+ ctrl->restore_mrs = save_restore_mrs;
+
+ if (status)
+ return status;
+
+ /** TODO: If this step fails and dec_wrd is set, clear it and try again **/
+ return train_jedec_write_leveling_cleanup(ctrl);
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 6a31d3a32c..7c0b5a49de 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -121,6 +121,8 @@
#define REUT_ch_ERR_DATA_MASK(ch) _MCMAIN_C(0x40d8, ch)
+#define REUT_ch_ERR_MISC_STATUS(ch) _MCMAIN_C(0x40e8, ch)
+
#define REUT_ch_MISC_CKE_CTRL(ch) _MCMAIN_C(0x4190, ch)
#define REUT_ch_MISC_ODT_CTRL(ch) _MCMAIN_C(0x4194, ch)
#define REUT_ch_MISC_PAT_CADB_CTRL(ch) _MCMAIN_C(0x4198, ch)
--
2.39.5
@@ -0,0 +1,30 @@
From 962bfe1366598145a93cf6a7ed0f78393e5e9ff7 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 23 Dec 2025 18:46:45 +0100
Subject: [PATCH 43/48] hp8300cmt: use legacy verb table
same as for the 780 optiplex patch
coreboot is making some changes to the way verbs are
handled. for now, this change is being made to adapt.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/hp/compaq_elite_8300_cmt/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
index d2bfd35dc4..30be7fb3fe 100644
--- a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
@@ -2,6 +2,7 @@ if BOARD_HP_COMPAQ_ELITE_8300_CMT
config BOARD_SPECIFIC_OPTIONS
def_bool y
+ select AZALIA_USE_LEGACY_VERB_TABLE
select BOARD_ROMSIZE_KB_16384
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
--
2.47.3
@@ -1,570 +0,0 @@
From 9d1b945702006db5678c5dc81699699bf6e6741a Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 8 May 2022 14:29:05 +0200
Subject: [PATCH 44/51] haswell NRI: Add final raminit steps
Implement the remaining raminit steps. Although many training steps are
missing, this is enough to boot on the Asrock B85M Pro4.
Change-Id: I94f3b65f0218d4da4fda4d84592dfd91f77f8f21
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
src/northbridge/intel/haswell/Kconfig | 4 +-
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../haswell/native_raminit/activate_mc.c | 388 ++++++++++++++++++
.../haswell/native_raminit/raminit_main.c | 5 +-
.../haswell/native_raminit/raminit_native.c | 5 +-
.../haswell/native_raminit/raminit_native.h | 2 +
.../haswell/native_raminit/reg_structs.h | 12 +
.../intel/haswell/registers/mchbar.h | 7 +
8 files changed, 416 insertions(+), 8 deletions(-)
create mode 100644 src/northbridge/intel/haswell/native_raminit/activate_mc.c
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 4b83a25bc1..c6ab27184e 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -11,12 +11,12 @@ config NORTHBRIDGE_INTEL_HASWELL
if NORTHBRIDGE_INTEL_HASWELL
config USE_NATIVE_RAMINIT
- bool "[NOT WORKING] Use native raminit"
+ bool "[NOT COMPLETE] Use native raminit"
default n
select HAVE_DEBUG_RAM_SETUP
help
Select if you want to use coreboot implementation of raminit rather than
- MRC.bin. Currently incomplete and does not boot.
+ MRC.bin. Currently incomplete and does not support S3 resume.
config HASWELL_VBOOT_IN_BOOTBLOCK
depends on VBOOT
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 40c2f5e014..d97da72890 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -1,5 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-or-later
+romstage-y += activate_mc.c
romstage-y += change_margin.c
romstage-y += configure_mc.c
romstage-y += ddr3.c
diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
new file mode 100644
index 0000000000..78a7ad27ef
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
@@ -0,0 +1,388 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static void update_internal_clocks_on(struct sysinfo *ctrl)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ bool clocks_on = false;
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ const union ddr_data_control_1_reg data_control_1 = {
+ .raw = ctrl->dq_control_1[channel][byte],
+ };
+ const int8_t o_on = data_control_1.odt_delay;
+ const int8_t s_on = data_control_1.sense_amp_delay;
+ const int8_t o_off = data_control_1.odt_duration;
+ const int8_t s_off = data_control_1.sense_amp_duration;
+ if (o_on + o_off >= 7 || s_on + s_off >= 7) {
+ clocks_on = true;
+ break;
+ }
+ }
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = ctrl->dq_control_0[channel],
+ };
+ data_control_0.internal_clocks_on = clocks_on;
+ ctrl->dq_control_0[channel] = data_control_0.raw;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ }
+}
+
+/* Switch off unused segments of the SDLL to save power */
+static void update_sdll_length(struct sysinfo *ctrl)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ uint8_t max_pi = 0;
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ const uint8_t rx_dqs_p = ctrl->rxdqsp[channel][rank][byte];
+ const uint8_t rx_dqs_n = ctrl->rxdqsn[channel][rank][byte];
+ max_pi = MAX(max_pi, MAX(rx_dqs_p, rx_dqs_n));
+ }
+ /* Update SDLL length for power savings */
+ union ddr_data_control_1_reg data_control_1 = {
+ .raw = ctrl->dq_control_1[channel][byte],
+ };
+ /* Calculate which segments to turn off */
+ data_control_1.sdll_segment_disable = (7 - (max_pi >> 3)) & ~1;
+ ctrl->dq_control_1[channel][byte] = data_control_1.raw;
+ mchbar_write32(DQ_CONTROL_1(channel, byte), data_control_1.raw);
+ }
+ }
+}
+
+static void set_rx_clk_stg_num(struct sysinfo *ctrl, const uint8_t channel)
+{
+ const uint8_t rcven_drift = ctrl->lpddr ? DIV_ROUND_UP(tDQSCK_DRIFT, ctrl->qclkps) : 1;
+ uint8_t max_rcven = 0;
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ max_rcven = MAX(max_rcven, ctrl->rcven[channel][rank][byte] / 64);
+ }
+ const union ddr_data_control_1_reg ddr_data_control_1 = {
+ .raw = ctrl->dq_control_1[channel][0],
+ };
+ const bool lpddr_long_odt = ddr_data_control_1.lpddr_long_odt_en;
+ const uint8_t rcven_turnoff = max_rcven + 18 + 2 * rcven_drift + lpddr_long_odt;
+ const union ddr_data_control_0_reg ddr_data_control_0 = {
+ .raw = ctrl->dq_control_0[channel],
+ };
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ union ddr_data_control_2_reg ddr_data_control_2 = {
+ .raw = ctrl->dq_control_2[channel][byte],
+ };
+ if (ddr_data_control_0.odt_samp_extend_en) {
+ if (ddr_data_control_2.rx_clk_stg_num < rcven_turnoff)
+ ddr_data_control_2.rx_clk_stg_num = rcven_turnoff;
+ } else {
+ const int8_t o_on = ddr_data_control_1.odt_delay;
+ const int8_t o_off = ddr_data_control_1.odt_duration;
+ ddr_data_control_2.rx_clk_stg_num = MAX(17, o_on + o_off + 14);
+ }
+ ctrl->dq_control_2[channel][byte] = ddr_data_control_2.raw;
+ mchbar_write32(DQ_CONTROL_2(channel, byte), ddr_data_control_2.raw);
+ }
+}
+
+#define SELF_REFRESH_IDLE_COUNT 0x200
+
+static void enter_sr(void)
+{
+ mchbar_write32(PM_SREF_CONFIG, SELF_REFRESH_IDLE_COUNT | BIT(16));
+ udelay(1);
+}
+
+enum power_down_mode {
+ PDM_NO_PD = 0,
+ PDM_APD = 1,
+ PDM_PPD = 2,
+ PDM_PPD_DLL_OFF = 6,
+};
+
+static void power_down_config(struct sysinfo *ctrl)
+{
+ const enum power_down_mode pd_mode = ctrl->lpddr ? PDM_PPD : PDM_PPD_DLL_OFF;
+ mchbar_write32(PM_PDWN_CONFIG, pd_mode << 12 | 0x40);
+}
+
+static void train_power_modes_post(struct sysinfo *ctrl)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ /* Adjust tCPDED and tPRPDEN */
+ if (ctrl->mem_clock_mhz >= 933)
+ ctrl->tc_bankrank_d[channel].tCPDED = 2;
+
+ if (ctrl->mem_clock_mhz >= 1066)
+ ctrl->tc_bankrank_d[channel].tPRPDEN = 2;
+
+ mchbar_write32(TC_BANK_RANK_D_ch(channel), ctrl->tc_bankrank_d[channel].raw);
+ }
+ power_down_config(ctrl);
+ mchbar_write32(MCDECS_CBIT, BIT(30)); /* dis_msg_clk_gate */
+}
+
+static uint8_t compute_burst_end_odt_delay(const struct sysinfo *const ctrl)
+{
+ /* Must be disabled for LPDDR */
+ if (ctrl->lpddr)
+ return 0;
+
+ const uint8_t beod = MIN(7, DIV_ROUND_CLOSEST(14300 * 20 / 100, ctrl->qclkps));
+ if (beod < 3)
+ return 0;
+
+ if (beod < 4)
+ return 4;
+
+ return beod;
+}
+
+static void program_burst_end_odt_delay(struct sysinfo *ctrl)
+{
+ /* Program burst_end_odt_delay - it should be zero during training steps */
+ const uint8_t beod = compute_burst_end_odt_delay(ctrl);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ union ddr_data_control_1_reg ddr_data_control_1 = {
+ .raw = ctrl->dq_control_1[channel][byte],
+ };
+ ddr_data_control_1.burst_end_odt_delay = beod;
+ ctrl->dq_control_1[channel][byte] = ddr_data_control_1.raw;
+ mchbar_write32(DQ_CONTROL_1(channel, byte), ddr_data_control_1.raw);
+ }
+ }
+}
+
+/*
+ * Return a random value to use for scrambler seeds. Try to use RDRAND
+ * first and fall back to hardcoded values if RDRAND does not succeed.
+ */
+static uint16_t get_random_number(const uint8_t channel)
+{
+ /* The RDRAND instruction is only available 100k cycles after reset */
+ for (size_t i = 0; i < 100000; i++) {
+ uint32_t status;
+ uint32_t random;
+ /** TODO: Clean up asm **/
+ __asm__ __volatile__(
+ "\n\t .byte 0x0F, 0xC7, 0xF0"
+ "\n\t movl %%eax, %0"
+ "\n\t pushf"
+ "\n\t pop %%eax"
+ "\n\t movl %%eax, %1"
+ : "=m"(random),
+ "=m"(status)
+ : /* No inputs */
+ : "eax", "cc");
+
+ /* Only consider non-zero random values as valid */
+ if (status & 1 && random)
+ return random;
+ }
+
+ /* https://xkcd.com/221 */
+ if (channel)
+ return 0x28f4;
+ else
+ return 0x893e;
+}
+
+/* Work around "error: 'typeof' applied to a bit-field" */
+static inline uint32_t max(const uint32_t a, const uint32_t b)
+{
+ return MAX(a, b);
+}
+
+enum raminit_status activate_mc(struct sysinfo *ctrl)
+{
+ const bool enable_scrambling = true;
+ const bool enable_cmd_tristate = true;
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ if (enable_scrambling && ctrl->stepping < STEPPING_C0) {
+ /* Make sure tRDRD_(sr, dr, dd) are at least 6 for scrambler W/A */
+ union tc_bank_rank_a_reg tc_bank_rank_a = {
+ .raw = mchbar_read32(TC_BANK_RANK_A_ch(channel)),
+ };
+ tc_bank_rank_a.tRDRD_sr = max(tc_bank_rank_a.tRDRD_sr, 6);
+ tc_bank_rank_a.tRDRD_dr = max(tc_bank_rank_a.tRDRD_dr, 6);
+ tc_bank_rank_a.tRDRD_dd = max(tc_bank_rank_a.tRDRD_dd, 6);
+ mchbar_write32(TC_BANK_RANK_A_ch(channel), tc_bank_rank_a.raw);
+ }
+ if (enable_scrambling) {
+ const union ddr_scramble_reg ddr_scramble = {
+ .scram_key = get_random_number(channel),
+ .scram_en = 1,
+ };
+ mchbar_write32(DDR_SCRAMBLE_ch(channel), ddr_scramble.raw);
+ }
+ if (ctrl->tCMD == 1) {
+ /* If we are in 1N mode, enable and set command rate limit to 3 */
+ union mcmain_command_rate_limit_reg cmd_rate_limit = {
+ .raw = mchbar_read32(COMMAND_RATE_LIMIT_ch(channel)),
+ };
+ cmd_rate_limit.enable_cmd_limit = 1;
+ cmd_rate_limit.cmd_rate_limit = 3;
+ mchbar_write32(COMMAND_RATE_LIMIT_ch(channel), cmd_rate_limit.raw);
+ }
+ if (enable_cmd_tristate) {
+ /* Enable command tri-state at the end of training */
+ union tc_bank_rank_a_reg tc_bank_rank_a = {
+ .raw = mchbar_read32(TC_BANK_RANK_A_ch(channel)),
+ };
+ tc_bank_rank_a.cmd_3st_dis = 0;
+ mchbar_write32(TC_BANK_RANK_A_ch(channel), tc_bank_rank_a.raw);
+ }
+ /* Set MC to normal mode and clean the ODT and CKE */
+ mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12);
+ /* Set again the rank occupancy */
+ mchbar_write8(MC_INIT_STATE_ch(channel), ctrl->rankmap[channel]);
+ if (ctrl->is_ecc) {
+ /* Enable ECC I/O and logic */
+ union mad_dimm_reg mad_dimm = {
+ .raw = mchbar_read32(MAD_DIMM(channel)),
+ };
+ mad_dimm.ecc_mode = 3;
+ mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
+ }
+ }
+
+ if (!is_hsw_ult())
+ update_internal_clocks_on(ctrl);
+
+ update_sdll_length(ctrl);
+
+ program_burst_end_odt_delay(ctrl);
+
+ if (is_hsw_ult()) {
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ set_rx_clk_stg_num(ctrl, channel);
+ }
+ /** TODO: Program DDRPL_CR_DDR_TX_DELAY if Memory Trace is enabled **/
+ }
+
+ /* Enable periodic COMP */
+ mchbar_write32(M_COMP, (union pcu_comp_reg) {
+ .comp_interval = COMP_INT,
+ }.raw);
+
+ /* Enable the power mode before PCU starts working */
+ train_power_modes_post(ctrl);
+
+ /* Set idle timer and self refresh enable bits */
+ enter_sr();
+
+ /** FIXME: Do not hardcode power weights and RAPL settings **/
+ mchbar_write32(0x5888, 0x00000d0d);
+ mchbar_write32(0x5884, 0x00000004); /* 58.2 pJ */
+
+ mchbar_write32(0x58e0, 0);
+ mchbar_write32(0x58e4, 0);
+
+ mchbar_write32(0x5890, 0xffff);
+ mchbar_write32(0x5894, 0xffff);
+ mchbar_write32(0x5898, 0xffff);
+ mchbar_write32(0x589c, 0xffff);
+ mchbar_write32(0x58d0, 0xffff);
+ mchbar_write32(0x58d4, 0xffff);
+ mchbar_write32(0x58d8, 0xffff);
+ mchbar_write32(0x58dc, 0xffff);
+
+ /* Overwrite thermal parameters */
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ mchbar_write32(_MCMAIN_C(0x42ec, channel), 0x0000000f);
+ mchbar_write32(_MCMAIN_C(0x42f0, channel), 0x00000009);
+ mchbar_write32(_MCMAIN_C(0x42f4, channel), 0x00000093);
+ mchbar_write32(_MCMAIN_C(0x42f8, channel), 0x00000087);
+ mchbar_write32(_MCMAIN_C(0x42fc, channel), 0x000000de);
+
+ /** TODO: Differs for LPDDR **/
+ mchbar_write32(PM_THRT_CKE_MIN_ch(channel), 0x30);
+ }
+ mchbar_write32(PCU_DDR_PTM_CTL, 0x40);
+ return RAMINIT_STATUS_SUCCESS;
+}
+
+static void mc_lockdown(void)
+{
+ /* Lock memory controller registers */
+ mchbar_write32(MC_LOCK, 0x8f);
+
+ /* MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK is set when programming the memory map */
+
+ /* Lock memory map registers */
+ pci_or_config16(HOST_BRIDGE, GGC, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, DPR, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, 1 << 10);
+ pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, TOM, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0);
+ pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
+}
+
+enum raminit_status raminit_done(struct sysinfo *ctrl)
+{
+ union mc_init_state_g_reg mc_init_state_g = {
+ .raw = mchbar_read32(MC_INIT_STATE_G),
+ };
+ mc_init_state_g.refresh_enable = 1;
+ mc_init_state_g.pu_mrc_done = 1;
+ mc_init_state_g.mrc_done = 1;
+ mchbar_write32(MC_INIT_STATE_G, mc_init_state_g.raw);
+
+ /* Lock the memory controller to enable normal operation */
+ mc_lockdown();
+
+ /* Poll for mc_init_done_ack to make sure memory initialization is complete */
+ printk(BIOS_DEBUG, "Waiting for mc_init_done acknowledgement... ");
+
+ struct stopwatch timer;
+ stopwatch_init_msecs_expire(&timer, 2000);
+ do {
+ mc_init_state_g.raw = mchbar_read32(MC_INIT_STATE_G);
+
+ /* DRAM will NOT work without the acknowledgement. There is no hope. */
+ if (stopwatch_expired(&timer))
+ die("\nTimed out waiting for mc_init_done acknowledgement\n");
+
+ } while (mc_init_state_g.mc_init_done_ack == 0);
+ printk(BIOS_DEBUG, "DONE!\n");
+
+ /* Provide some data for the graphics driver. Yes, it's hardcoded. */
+ mchbar_write32(SSKPD + 0, 0x05a2404f);
+ mchbar_write32(SSKPD + 4, 0x140000a0);
+ return RAMINIT_STATUS_SUCCESS;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 1ff23be615..3a65fb01fb 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -63,6 +63,8 @@ static const struct task_entry cold_boot[] = {
{ train_receive_enable, true, "RCVET", },
{ train_read_mpr, true, "RDMPRT", },
{ train_jedec_write_leveling, true, "JWRL", },
+ { activate_mc, true, "ACTIVATE", },
+ { raminit_done, true, "RAMINITEND", },
};
/* Return a generic stepping value to make stepping checks simpler */
@@ -143,7 +145,4 @@ void raminit_main(const enum raminit_boot_mode bootmode)
if (status != RAMINIT_STATUS_SUCCESS)
die("Memory initialization was met with utmost failure and misery\n");
-
- /** TODO: Implement the required magic **/
- die("NATIVE RAMINIT: More Magic (tm) required.\n");
}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index 2fed93de5b..5f7ceec222 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -199,8 +199,6 @@ void perform_raminit(const int s3resume)
else
me_status = ME_INIT_STATUS_SUCCESS;
- /** TODO: Remove this once raminit is implemented **/
- me_status = ME_INIT_STATUS_ERROR;
intel_early_me_init_done(me_status);
}
@@ -214,7 +212,8 @@ void perform_raminit(const int s3resume)
}
/* Save training data on non-S3 resumes */
- if (!s3resume)
+ /** TODO: Enable this once training data is populated **/
+ if (0 && !s3resume)
save_mrc_data(&md);
/** TODO: setup_sdram_meminfo **/
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index d6b11b9d3c..a0a913f926 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -448,6 +448,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
enum raminit_status train_receive_enable(struct sysinfo *ctrl);
enum raminit_status train_read_mpr(struct sysinfo *ctrl);
enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+enum raminit_status activate_mc(struct sysinfo *ctrl);
+enum raminit_status raminit_done(struct sysinfo *ctrl);
void configure_timings(struct sysinfo *ctrl);
void configure_refresh(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
index a0e36ed082..0d9aaa1f7c 100644
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
@@ -294,6 +294,18 @@ union ddr_cke_ctl_controls_reg {
uint32_t raw;
};
+union ddr_scramble_reg {
+ struct __packed {
+ uint32_t scram_en : 1; // Bits 0:0
+ uint32_t scram_key : 16; // Bits 16:1
+ uint32_t clk_gate_ab : 2; // Bits 18:17
+ uint32_t clk_gate_c : 2; // Bits 20:19
+ uint32_t en_dbi_ab : 1; // Bits 21:21
+ uint32_t : 10; // Bits 31:17
+ };
+ uint32_t raw;
+};
+
union ddr_scram_misc_control_reg {
struct __packed {
uint32_t wl_wake_cycles : 2; // Bits 1:0
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 7c0b5a49de..49a215aa71 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -20,6 +20,7 @@
#define DDR_DATA_TRAIN_FEEDBACK(ch, byte) _DDRIO_C_R_B(0x0054, ch, 0, byte)
+#define DQ_CONTROL_1(ch, byte) _DDRIO_C_R_B(0x0060, ch, 0, byte)
#define DQ_CONTROL_2(ch, byte) _DDRIO_C_R_B(0x0064, ch, 0, byte)
#define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte) _DDRIO_C_R_B(0x0070, ch, 0, byte)
#define DQ_CONTROL_0(ch, byte) _DDRIO_C_R_B(0x0074, ch, 0, byte)
@@ -147,6 +148,8 @@
#define QCLK_ch_LDAT_SDAT(ch) _MCMAIN_C(0x42d4, ch)
#define QCLK_ch_LDAT_DATA_IN_x(ch, x) _MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
+#define PM_THRT_CKE_MIN_ch(ch) _MCMAIN_C(0x4328, ch)
+
#define REUT_GLOBAL_CTL 0x4800
#define REUT_GLOBAL_ERR 0x4804
@@ -175,6 +178,8 @@
#define MCSCHEDS_DFT_MISC 0x4c30
+#define PM_PDWN_CONFIG 0x4cb0
+
#define REUT_ERR_DATA_STATUS 0x4ce0
#define REUT_MISC_CKE_CTRL 0x4d90
@@ -186,8 +191,10 @@
#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */
#define MAD_DIMM(ch) (0x5004 + (ch) * 4)
#define MAD_ZR 0x5014
+#define MCDECS_CBIT 0x501c
#define MC_INIT_STATE_G 0x5030
#define MRC_REVISION 0x5034 /* MRC Revision */
+#define PM_SREF_CONFIG 0x5060
#define RCOMP_TIMER 0x5084
--
2.39.5
@@ -0,0 +1,34 @@
From 88d29f792de89bb0a138e671432227cb5679b5ae Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 6 Jan 2026 21:42:21 +0000
Subject: [PATCH 44/48] topton x2e n150: use old fsp
i added the old fsp back, so that we didn't have to
mess around with vendor files in lbmk, because coreboot
upstream updated the fsp repo, which modified this
fsp file.
we know the old fsp worked. there's no point testing
the new one yet, unless someone can tell me about
real bugs that got fixed.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/alderlake/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 06b9199e84..f260d10285 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -451,6 +451,7 @@ config FSP_FD_PATH
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S
+ default "3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if BOARD_TOPTON_X2E_N150
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N
default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P
default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S
--
2.47.3
@@ -1,722 +0,0 @@
From b6b89013630d535b68a005cede9e2540f273f4e7 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 13 Apr 2024 01:16:30 +0200
Subject: [PATCH 45/51] Haswell NRI: Implement fast boot path
When the memory configuration hasn't changed, there is no need to do
full memory training. Instead, boot firmware can use saved training
data to reinitialise the memory controller and memory.
Unlike native RAM init for other platforms, Haswell does not save the
main structure (the "mighty ctrl" struct) to flash. Instead, separate
structures define the data to be saved, which can be smaller than the
main structure.
This makes S3 suspend and resume work: RAM contents MUST be preserved
for a S3 resume to succeed, but RAM training destroys RAM contents.
Change-Id: I06f6cd39ceecdca104fae89159f28e85cf7ff4e6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../haswell/native_raminit/activate_mc.c | 17 +
.../intel/haswell/native_raminit/ddr3.c | 41 ++
.../haswell/native_raminit/raminit_main.c | 34 +-
.../haswell/native_raminit/raminit_native.c | 30 +-
.../haswell/native_raminit/raminit_native.h | 18 +
.../haswell/native_raminit/save_restore.c | 387 ++++++++++++++++++
7 files changed, 504 insertions(+), 24 deletions(-)
create mode 100644 src/northbridge/intel/haswell/native_raminit/save_restore.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index d97da72890..8fdd17c542 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -13,6 +13,7 @@ romstage-y += raminit_main.c
romstage-y += raminit_native.c
romstage-y += ranges.c
romstage-y += reut.c
+romstage-y += save_restore.c
romstage-y += setup_wdb.c
romstage-y += spd_bitmunching.c
romstage-y += testing_io.c
diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
index 78a7ad27ef..0b3eb917da 100644
--- a/src/northbridge/intel/haswell/native_raminit/activate_mc.c
+++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
@@ -333,6 +333,23 @@ enum raminit_status activate_mc(struct sysinfo *ctrl)
return RAMINIT_STATUS_SUCCESS;
}
+enum raminit_status normal_state(struct sysinfo *ctrl)
+{
+ /* Enable periodic COMP */
+ mchbar_write32(M_COMP, (union pcu_comp_reg) {
+ .comp_interval = COMP_INT,
+ }.raw);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ /* Set MC to normal mode and clean the ODT and CKE */
+ mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12);
+ }
+ power_down_config(ctrl);
+ return RAMINIT_STATUS_SUCCESS;
+}
+
static void mc_lockdown(void)
{
/* Lock memory controller registers */
diff --git a/src/northbridge/intel/haswell/native_raminit/ddr3.c b/src/northbridge/intel/haswell/native_raminit/ddr3.c
index 6ddb11488b..9b6368edb1 100644
--- a/src/northbridge/intel/haswell/native_raminit/ddr3.c
+++ b/src/northbridge/intel/haswell/native_raminit/ddr3.c
@@ -2,6 +2,7 @@
#include <assert.h>
#include <console/console.h>
+#include <delay.h>
#include <northbridge/intel/haswell/haswell.h>
#include <types.h>
@@ -215,3 +216,43 @@ enum raminit_status ddr3_jedec_init(struct sysinfo *ctrl)
ddr3_program_mr0(ctrl, 1);
return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT);
}
+
+enum raminit_status exit_selfrefresh(struct sysinfo *ctrl)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ /* Fields in ctrl aren't populated on a warm boot */
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = mchbar_read32(DQ_CONTROL_0(channel, 0)),
+ };
+ data_control_0.read_rf_rd = 1;
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ data_control_0.read_rf_rank = rank;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ }
+ }
+
+ /* Time needed to stabilize the DCLK (~6 us) */
+ udelay(6);
+
+ /* Pull the DIMMs out of self refresh by asserting CKE high */
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ const union reut_misc_cke_ctrl_reg reut_misc_cke_ctrl = {
+ .cke_on = ctrl->rankmap[channel],
+ };
+ mchbar_write32(REUT_ch_MISC_CKE_CTRL(channel), reut_misc_cke_ctrl.raw);
+ }
+ mchbar_write32(REUT_MISC_ODT_CTRL, 0);
+
+ const enum raminit_status status = reut_issue_zq(ctrl, ctrl->chanmap, ZQ_LONG);
+ if (status) {
+ /* ZQCL errors don't seem to be a fatal problem here */
+ printk(BIOS_ERR, "ZQ Long failed during S3 resume or warm reset flow\n");
+ }
+ return RAMINIT_STATUS_SUCCESS;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 3a65fb01fb..056dde1adc 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -64,6 +64,22 @@ static const struct task_entry cold_boot[] = {
{ train_read_mpr, true, "RDMPRT", },
{ train_jedec_write_leveling, true, "JWRL", },
{ activate_mc, true, "ACTIVATE", },
+ { save_training_values, true, "SAVE_TRAIN", },
+ { save_non_training, true, "SAVE_NONT", },
+ { raminit_done, true, "RAMINITEND", },
+};
+
+static const struct task_entry fast_boot[] = {
+ { collect_spd_info, true, "PROCSPD", },
+ { restore_non_training, true, "RST_NONT", },
+ { initialise_mpll, true, "INITMPLL", },
+ { configure_mc, true, "CONFMC", },
+ { configure_memory_map, true, "MEMMAP", },
+ { do_jedec_init, true, "JEDECINIT", },
+ { pre_training, true, "PRETRAIN", },
+ { restore_training_values, true, "RST_TRAIN", },
+ { exit_selfrefresh, true, "EXIT_SR", },
+ { normal_state, true, "NORMALMODE", },
{ raminit_done, true, "RAMINITEND", },
};
@@ -102,11 +118,11 @@ static void initialize_ctrl(struct sysinfo *ctrl)
ctrl->bootmode = bootmode;
}
-static enum raminit_status try_raminit(struct sysinfo *ctrl)
+static enum raminit_status try_raminit(
+ struct sysinfo *ctrl,
+ const struct task_entry *const schedule,
+ const size_t length)
{
- const struct task_entry *const schedule = cold_boot;
- const size_t length = ARRAY_SIZE(cold_boot);
-
enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
for (size_t i = 0; i < length; i++) {
@@ -140,8 +156,16 @@ void raminit_main(const enum raminit_boot_mode bootmode)
mighty_ctrl.bootmode = bootmode;
initialize_ctrl(&mighty_ctrl);
+ enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
+
+ if (bootmode != BOOTMODE_COLD) {
+ status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot));
+ if (status == RAMINIT_STATUS_SUCCESS)
+ return;
+ }
+
/** TODO: Try more than once **/
- enum raminit_status status = try_raminit(&mighty_ctrl);
+ status = try_raminit(&mighty_ctrl, cold_boot, ARRAY_SIZE(cold_boot));
if (status != RAMINIT_STATUS_SUCCESS)
die("Memory initialization was met with utmost failure and misery\n");
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index 5f7ceec222..3ad8ce29e7 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -54,23 +54,17 @@ static bool early_init_native(enum raminit_boot_mode bootmode)
return cpu_replaced;
}
-#define MRC_CACHE_VERSION 1
-
-struct mrc_data {
- const void *buffer;
- size_t buffer_len;
-};
-
-static void save_mrc_data(struct mrc_data *md)
+static void save_mrc_data(void)
{
- mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len);
+ mrc_cache_stash_data(MRC_TRAINING_DATA, reg_frame_rev(),
+ reg_frame_ptr(), reg_frame_size());
}
static struct mrc_data prepare_mrc_cache(void)
{
struct mrc_data md = {0};
md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
- MRC_CACHE_VERSION,
+ reg_frame_rev(),
&md.buffer_len);
return md;
}
@@ -94,14 +88,15 @@ static void raminit_reset(void)
}
static enum raminit_boot_mode do_actual_raminit(
- struct mrc_data *md,
const bool s3resume,
const bool cpu_replaced,
const enum raminit_boot_mode orig_bootmode)
{
+ struct mrc_data md = prepare_mrc_cache();
+
enum raminit_boot_mode bootmode = orig_bootmode;
- bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/
+ bool save_data_valid = md.buffer && md.buffer_len == reg_frame_size();
if (s3resume) {
if (bootmode == BOOTMODE_COLD) {
@@ -154,7 +149,7 @@ static enum raminit_boot_mode do_actual_raminit(
assert(save_data_valid != (bootmode == BOOTMODE_COLD));
if (save_data_valid) {
printk(BIOS_INFO, "Using cached memory parameters\n");
- die("RAMINIT: Fast boot is not yet implemented\n");
+ memcpy(reg_frame_ptr(), md.buffer, reg_frame_size());
}
printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]);
printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]);
@@ -181,10 +176,8 @@ void perform_raminit(const int s3resume)
wait_txt_clear();
wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
- struct mrc_data md = prepare_mrc_cache();
-
const enum raminit_boot_mode bootmode =
- do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode);
+ do_actual_raminit(s3resume, cpu_replaced, orig_bootmode);
/** TODO: report_memory_config **/
@@ -212,9 +205,8 @@ void perform_raminit(const int s3resume)
}
/* Save training data on non-S3 resumes */
- /** TODO: Enable this once training data is populated **/
- if (0 && !s3resume)
- save_mrc_data(&md);
+ if (!s3resume)
+ save_mrc_data();
/** TODO: setup_sdram_meminfo **/
}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index a0a913f926..2ac16eaad3 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -170,6 +170,8 @@ enum regfile_mode {
REG_FILE_USE_CURRENT, /* Used when changing parameters after the test */
};
+struct register_save_frame;
+
struct wdb_pat {
uint32_t start_ptr; /* Starting pointer in WDB */
uint32_t stop_ptr; /* Stopping pointer in WDB */
@@ -220,6 +222,7 @@ enum raminit_status {
RAMINIT_STATUS_RCVEN_FAILURE,
RAMINIT_STATUS_RMPR_FAILURE,
RAMINIT_STATUS_JWRL_FAILURE,
+ RAMINIT_STATUS_INVALID_CACHE,
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
};
@@ -229,6 +232,11 @@ enum generic_stepping {
STEPPING_C0 = 3,
};
+struct mrc_data {
+ const void *buffer;
+ size_t buffer_len;
+};
+
struct raminit_dimm_info {
spd_ddr3_raw_data raw_spd;
struct dimm_attr_ddr3_st data;
@@ -448,12 +456,22 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
enum raminit_status train_receive_enable(struct sysinfo *ctrl);
enum raminit_status train_read_mpr(struct sysinfo *ctrl);
enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+enum raminit_status save_training_values(struct sysinfo *ctrl);
+enum raminit_status restore_training_values(struct sysinfo *ctrl);
+enum raminit_status save_non_training(struct sysinfo *ctrl);
+enum raminit_status restore_non_training(struct sysinfo *ctrl);
+enum raminit_status exit_selfrefresh(struct sysinfo *ctrl);
+enum raminit_status normal_state(struct sysinfo *ctrl);
enum raminit_status activate_mc(struct sysinfo *ctrl);
enum raminit_status raminit_done(struct sysinfo *ctrl);
void configure_timings(struct sysinfo *ctrl);
void configure_refresh(struct sysinfo *ctrl);
+struct register_save_frame *reg_frame_ptr(void);
+size_t reg_frame_size(void);
+uint32_t reg_frame_rev(void);
+
uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
uint32_t get_tAONPD(uint32_t mem_clock_mhz);
diff --git a/src/northbridge/intel/haswell/native_raminit/save_restore.c b/src/northbridge/intel/haswell/native_raminit/save_restore.c
new file mode 100644
index 0000000000..f1f50e3ff8
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/save_restore.c
@@ -0,0 +1,387 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+uint32_t reg_frame_rev(void)
+{
+ /*
+ * Equivalent to MRC_CACHE_REVISION, but hidden via abstraction.
+ * The structures that get saved to flash are contained within
+ * this translation unit, so changes outside this file shouldn't
+ * require invalidating the cache.
+ */
+ return 1;
+}
+
+struct register_save {
+ uint16_t lower;
+ uint16_t upper;
+};
+
+/** TODO: Haswell DDRIO aliases writes: 0x80 .. 0xff => 0x00 .. 0x7f **/
+static const struct register_save ddrio_per_byte_list[] = {
+ {0x0000, 0x003c}, /* 16 registers */
+// {0x0048, 0x0084}, /* 16 registers */ /** TODO: BDW support **/
+ {0x0048, 0x004c}, /* 2 registers */
+ {0x005c, 0x0078}, /* 8 registers */
+};
+#define DDRIO_PER_BYTE_REGISTER_COUNT (16 + 2 + 8)
+
+static const struct register_save ddrio_per_ch_list[] = {
+ /* CKE */
+ {0x1204, 0x1208}, /* 2 registers */
+ {0x1214, 0x121c}, /* 3 registers */
+ /* CMD North */
+ {0x1404, 0x140c}, /* 3 registers */
+ /* CLK */
+ {0x1808, 0x1810}, /* 3 registers */
+ /* CMD South */
+ {0x1a04, 0x1a0c}, /* 3 registers */
+ /* CTL */
+ {0x1c14, 0x1c1c}, /* 3 registers */
+};
+#define DDRIO_PER_CH_REGISTER_COUNT (2 + 3 * 5)
+
+static const struct register_save ddrio_common_list[] = {
+ {0x2000, 0x2008}, /* 3 registers */
+ {0x3a14, 0x3a1c}, /* 3 registers */
+ {0x3a24, 0x3a24}, /* 1 registers */
+};
+
+#define DDRIO_COMMON_REGISTER_COUNT (3 + 3 + 1)
+
+static const struct register_save mcmain_per_ch_list[] = {
+ {0x4000, 0x4014}, /* 6 registers */
+ {0x4024, 0x4028}, /* 2 registers */
+ {0x40d0, 0x40d0}, /* 1 registers */
+ {0x4220, 0x4224}, /* 2 registers */
+ {0x4294, 0x4294}, /* 1 registers */
+ {0x429c, 0x42a0}, /* 2 registers */
+ {0x42ec, 0x42fc}, /* 5 registers */
+ {0x4328, 0x4328}, /* 1 registers */
+ {0x438c, 0x4390}, /* 2 registers */
+};
+#define MCMAIN_PER_CH_REGISTER_COUNT (6 + 2 + 1 + 2 + 1 + 2 + 5 + 1 + 2)
+
+static const struct register_save misc_common_list[] = {
+ {0x5884, 0x5888}, /* 2 registers */
+ {0x5890, 0x589c}, /* 4 registers */
+ {0x58a4, 0x58a4}, /* 1 registers */
+ {0x58d0, 0x58e4}, /* 6 registers */
+ {0x5880, 0x5880}, /* 1 registers */
+ {0x5000, 0x50dc}, /* 56 registers */
+ {0x59b8, 0x59b8} /* 1 registers */
+};
+#define MISC_COMMON_REGISTER_COUNT (2 + 4 + 1 + 6 + 1 + 56 + 1)
+
+struct save_params {
+ bool is_initialised;
+
+ /* Memory base frequency, either 100 or 133 MHz */
+ uint8_t base_freq;
+
+ /* Multiplier */
+ uint32_t multiplier;
+
+ /* Memory clock in MHz */
+ uint32_t mem_clock_mhz;
+
+ /* Memory clock in femtoseconds */
+ uint32_t mem_clock_fs;
+
+ /* Quadrature clock in picoseconds */
+ uint16_t qclkps;
+
+ /* Bitfield of supported CAS latencies */
+ uint16_t cas_supported;
+
+ /* CPUID value */
+ uint32_t cpu;
+
+ /* Cached CPU stepping value */
+ uint8_t stepping;
+
+ uint16_t vdd_mv;
+
+ union dimm_flags_ddr3_st flags;
+
+ /* Except for tCK, everything is stored in DCLKs */
+ uint32_t tCK;
+ uint32_t tAA;
+ uint32_t tWR;
+ uint32_t tRCD;
+ uint32_t tRRD;
+ uint32_t tRP;
+ uint32_t tRAS;
+ uint32_t tRC;
+ uint32_t tRFC;
+ uint32_t tWTR;
+ uint32_t tRTP;
+ uint32_t tFAW;
+ uint32_t tCWL;
+ uint32_t tCMD;
+
+ uint32_t tREFI;
+ uint32_t tXP;
+
+ uint8_t lpddr_cke_rank_map[NUM_CHANNELS];
+
+ struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS];
+
+ uint8_t chanmap;
+
+ uint32_t channel_size_mb[NUM_CHANNELS];
+
+ /* DIMMs per channel */
+ uint8_t dpc[NUM_CHANNELS];
+
+ uint8_t rankmap[NUM_CHANNELS];
+
+ /* Whether a rank is mirrored or not (only rank 1 of each DIMM can be) */
+ uint8_t rank_mirrored[NUM_CHANNELS];
+
+ /*
+ * FIXME: LPDDR support is incomplete. The largest chunks are missing,
+ * but some LPDDR-specific variations in algorithms have been handled.
+ * LPDDR-specific functions have stubs which will halt upon execution.
+ */
+ bool lpddr;
+
+ uint8_t lanes;
+
+ /* FIXME: ECC support missing */
+ bool is_ecc;
+};
+
+struct register_save_frame {
+ uint32_t ddrio_per_byte[NUM_CHANNELS][NUM_LANES][DDRIO_PER_BYTE_REGISTER_COUNT];
+ uint32_t ddrio_per_ch[NUM_CHANNELS][DDRIO_PER_CH_REGISTER_COUNT];
+ uint32_t ddrio_common[DDRIO_COMMON_REGISTER_COUNT];
+ uint32_t mcmain_per_ch[NUM_CHANNELS][MCMAIN_PER_CH_REGISTER_COUNT];
+ uint32_t misc_common[MISC_COMMON_REGISTER_COUNT];
+ struct save_params params;
+};
+
+struct register_save_frame *reg_frame_ptr(void)
+{
+ /* The chonky register save frame struct, used for fast boot and S3 resume */
+ static struct register_save_frame register_frame = { 0 };
+ return &register_frame;
+}
+
+size_t reg_frame_size(void)
+{
+ return sizeof(struct register_save_frame);
+}
+
+typedef void (*reg_func_t)(const uint16_t offset, uint32_t *const value);
+
+static void save_value(const uint16_t offset, uint32_t *const value)
+{
+ *value = mchbar_read32(offset);
+}
+
+static void restore_value(const uint16_t offset, uint32_t *const value)
+{
+ mchbar_write32(offset, *value);
+}
+
+static void save_restore(
+ uint32_t *reg_frame,
+ const uint16_t g_offset,
+ const struct register_save *reg_save_list,
+ const size_t reg_save_length,
+ reg_func_t handle_reg)
+{
+ for (size_t i = 0; i < reg_save_length; i++) {
+ const struct register_save *entry = &reg_save_list[i];
+ for (uint16_t offset = entry->lower; offset <= entry->upper; offset += 4) {
+ handle_reg(offset + g_offset, reg_frame++);
+ }
+ }
+}
+
+static void save_restore_all(struct register_save_frame *reg_frame, reg_func_t handle_reg)
+{
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ for (uint8_t byte = 0; byte < NUM_LANES; byte++) {
+ const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, byte);
+ save_restore(
+ reg_frame->ddrio_per_byte[channel][byte],
+ g_offset,
+ ddrio_per_byte_list,
+ ARRAY_SIZE(ddrio_per_byte_list),
+ handle_reg);
+ }
+ }
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, 0);
+ save_restore(
+ reg_frame->ddrio_per_ch[channel],
+ g_offset,
+ ddrio_per_ch_list,
+ ARRAY_SIZE(ddrio_per_ch_list),
+ handle_reg);
+ }
+ save_restore(
+ reg_frame->ddrio_common,
+ 0,
+ ddrio_common_list,
+ ARRAY_SIZE(ddrio_common_list),
+ handle_reg);
+
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ const uint16_t g_offset = _MCMAIN_C(0, channel);
+ save_restore(
+ reg_frame->mcmain_per_ch[channel],
+ g_offset,
+ mcmain_per_ch_list,
+ ARRAY_SIZE(mcmain_per_ch_list),
+ handle_reg);
+ }
+ save_restore(
+ reg_frame->misc_common,
+ 0,
+ misc_common_list,
+ ARRAY_SIZE(misc_common_list),
+ handle_reg);
+}
+
+enum raminit_status save_training_values(struct sysinfo *ctrl)
+{
+ save_restore_all(reg_frame_ptr(), save_value);
+ return RAMINIT_STATUS_SUCCESS;
+}
+
+enum raminit_status restore_training_values(struct sysinfo *ctrl)
+{
+ save_restore_all(reg_frame_ptr(), restore_value);
+ return RAMINIT_STATUS_SUCCESS;
+}
+
+enum raminit_status save_non_training(struct sysinfo *ctrl)
+{
+ struct register_save_frame *reg_frame = reg_frame_ptr();
+ struct save_params *params = &reg_frame->params;
+
+ params->is_initialised = true;
+
+ params->base_freq = ctrl->base_freq;
+ params->multiplier = ctrl->multiplier;
+ params->mem_clock_mhz = ctrl->mem_clock_mhz;
+ params->mem_clock_fs = ctrl->mem_clock_fs;
+ params->qclkps = ctrl->qclkps;
+ params->cas_supported = ctrl->cas_supported;
+ params->cpu = ctrl->cpu;
+ params->stepping = ctrl->stepping;
+ params->vdd_mv = ctrl->vdd_mv;
+ params->flags = ctrl->flags;
+
+ params->tCK = ctrl->tCK;
+ params->tAA = ctrl->tAA;
+ params->tWR = ctrl->tWR;
+ params->tRCD = ctrl->tRCD;
+ params->tRRD = ctrl->tRRD;
+ params->tRP = ctrl->tRP;
+ params->tRAS = ctrl->tRAS;
+ params->tRC = ctrl->tRC;
+ params->tRFC = ctrl->tRFC;
+ params->tWTR = ctrl->tWTR;
+ params->tRTP = ctrl->tRTP;
+ params->tFAW = ctrl->tFAW;
+ params->tCWL = ctrl->tCWL;
+ params->tCMD = ctrl->tCMD;
+ params->tREFI = ctrl->tREFI;
+ params->tXP = ctrl->tXP;
+
+ params->chanmap = ctrl->chanmap;
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ params->lpddr_cke_rank_map[channel] = ctrl->lpddr_cke_rank_map[channel];
+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++)
+ params->dimms[channel][slot] = ctrl->dimms[channel][slot];
+ }
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ params->dpc[channel] = ctrl->dpc[channel];
+ params->rankmap[channel] = ctrl->rankmap[channel];
+ params->rank_mirrored[channel] = ctrl->rank_mirrored[channel];
+ params->channel_size_mb[channel] = ctrl->channel_size_mb[channel];
+ }
+ params->lpddr = ctrl->lpddr;
+ params->lanes = ctrl->lanes;
+ params->is_ecc = ctrl->is_ecc;
+ return RAMINIT_STATUS_SUCCESS;
+}
+
+#define RAMINIT_COMPARE(_s1, _s2) \
+ ((sizeof(_s1) == sizeof(_s2)) && !memcmp(_s1, _s2, sizeof(_s1)))
+
+enum raminit_status restore_non_training(struct sysinfo *ctrl)
+{
+ struct register_save_frame *reg_frame = reg_frame_ptr();
+ struct save_params *params = &reg_frame->params;
+
+ if (!params->is_initialised) {
+ printk(BIOS_WARNING, "Cannot fast boot: saved data is invalid\n");
+ return RAMINIT_STATUS_INVALID_CACHE;
+ }
+
+ if (!RAMINIT_COMPARE(ctrl->dimms, params->dimms)) {
+ printk(BIOS_WARNING, "Cannot fast boot: DIMMs have changed\n");
+ return RAMINIT_STATUS_INVALID_CACHE;
+ }
+
+ if (ctrl->cpu != params->cpu) {
+ printk(BIOS_WARNING, "Cannot fast boot: CPU has changed\n");
+ return RAMINIT_STATUS_INVALID_CACHE;
+ }
+
+ ctrl->base_freq = params->base_freq;
+ ctrl->multiplier = params->multiplier;
+ ctrl->mem_clock_mhz = params->mem_clock_mhz;
+ ctrl->mem_clock_fs = params->mem_clock_fs;
+ ctrl->qclkps = params->qclkps;
+ ctrl->cas_supported = params->cas_supported;
+ ctrl->cpu = params->cpu;
+ ctrl->stepping = params->stepping;
+ ctrl->vdd_mv = params->vdd_mv;
+ ctrl->flags = params->flags;
+
+ ctrl->tCK = params->tCK;
+ ctrl->tAA = params->tAA;
+ ctrl->tWR = params->tWR;
+ ctrl->tRCD = params->tRCD;
+ ctrl->tRRD = params->tRRD;
+ ctrl->tRP = params->tRP;
+ ctrl->tRAS = params->tRAS;
+ ctrl->tRC = params->tRC;
+ ctrl->tRFC = params->tRFC;
+ ctrl->tWTR = params->tWTR;
+ ctrl->tRTP = params->tRTP;
+ ctrl->tFAW = params->tFAW;
+ ctrl->tCWL = params->tCWL;
+ ctrl->tCMD = params->tCMD;
+ ctrl->tREFI = params->tREFI;
+ ctrl->tXP = params->tXP;
+
+ ctrl->chanmap = params->chanmap;
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ ctrl->lpddr_cke_rank_map[channel] = params->lpddr_cke_rank_map[channel];
+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++)
+ ctrl->dimms[channel][slot] = params->dimms[channel][slot];
+ }
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ ctrl->dpc[channel] = params->dpc[channel];
+ ctrl->rankmap[channel] = params->rankmap[channel];
+ ctrl->rank_mirrored[channel] = params->rank_mirrored[channel];
+ ctrl->channel_size_mb[channel] = params->channel_size_mb[channel];
+ }
+ ctrl->lpddr = params->lpddr;
+ ctrl->lanes = params->lanes;
+ ctrl->is_ecc = params->is_ecc;
+ return RAMINIT_STATUS_SUCCESS;
+}
--
2.39.5
@@ -0,0 +1,31 @@
From 5b52abaa8529f7493f9d4ecf402e9ee130f4f8d2 Mon Sep 17 00:00:00 2001
From: Ron Nazarov <ron@noisytoot.org>
Date: Sat, 14 Feb 2026 20:13:01 +0000
Subject: [PATCH 45/48] mb/supermicro/x11-lga1151-series: Disable ME HECI in
devicetree
Since we always use me_cleaner, this speeds up boot time by preventing
coreboot from wasting a few seconds waiting for HECI.
Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350
Signed-off-by: Ron Nazarov <ron@noisytoot.org>
---
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index fbf896c6ae..aa09a41f2f 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -15,7 +15,7 @@ chip soc/intel/skylake
device ref sa_thermal on end
device ref south_xhci on end
device ref thermal on end
- device ref heci1 on end
+ device ref heci1 off end
device ref sata on
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{
--
2.47.3
@@ -1,476 +0,0 @@
From 02aa0c5612388e35f5dd1ff9c5f7a7b5b48fb9c0 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Wed, 17 Apr 2024 13:20:32 +0200
Subject: [PATCH 46/51] haswell NRI: Do sense amplifier offset training
Quoting Wikipedia:
A sense amplifier is a circuit that is used to amplify and detect
small signals in electronic systems. It is commonly used in memory
circuits, such as dynamic random access memory (DRAM), to read and
amplify the weak signals stored in memory cells.
In this case, we're calibrating the sense amplifiers in the memory
controller. This training procedure uses a magic "sense amp offset
cancel" mode of the DDRIO to observe the sampled logic levels, and
sweeps Vref to find the low-high transition for each bit lane. The
procedure consists of two stages: the first stage centers per-byte
Vref (to ensure per-bit Vref offsets are as small as possible) and
the second stage centers per-bit Vref.
Because this procedure uses the "sense amp offset cancel" mode, it
does not rely on DRAM being trained. It is assumed that the memory
controller simply makes sense amp output levels observable via the
`DDR_DATA_TRAIN_FEEDBACK` register and that the memory bus is idle
during this training step (so the lane voltage is Vdd / 2).
Note: This procedure will need to be adapted for Broadwell because
it has per-rank per-bit RxVref registers, whereas Haswell only has
a single per-bit RxVref register for all ranks.
Change-Id: Ia07db68763f90e9701c8a376e01279ada8dbbe07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.mk | 1 +
.../haswell/native_raminit/raminit_main.c | 1 +
.../haswell/native_raminit/raminit_native.h | 12 +
.../native_raminit/train_sense_amp_offset.c | 341 ++++++++++++++++++
.../intel/haswell/registers/mchbar.h | 2 +
5 files changed, 357 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
index 8fdd17c542..4bd668a2d6 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
@@ -21,3 +21,4 @@ romstage-y += timings_refresh.c
romstage-y += train_jedec_write_leveling.c
romstage-y += train_read_mpr.c
romstage-y += train_receive_enable.c
+romstage-y += train_sense_amp_offset.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 056dde1adc..ce637e2d03 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = {
{ configure_memory_map, true, "MEMMAP", },
{ do_jedec_init, true, "JEDECINIT", },
{ pre_training, true, "PRETRAIN", },
+ { train_sense_amp_offset, true, "SOT", },
{ train_receive_enable, true, "RCVET", },
{ train_read_mpr, true, "RDMPRT", },
{ train_jedec_write_leveling, true, "JWRL", },
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 2ac16eaad3..07eea98831 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -23,6 +23,8 @@
#define NUM_LANES 9
#define NUM_LANES_NO_ECC 8
+#define NUM_BITS 8
+
#define COMP_INT 10
/* Always use 12 legs for emphasis (not trained) */
@@ -219,6 +221,7 @@ enum raminit_status {
RAMINIT_STATUS_MPLL_INIT_FAILURE,
RAMINIT_STATUS_POLL_TIMEOUT,
RAMINIT_STATUS_REUT_ERROR,
+ RAMINIT_STATUS_SAMP_OFFSET_FAILURE,
RAMINIT_STATUS_RCVEN_FAILURE,
RAMINIT_STATUS_RMPR_FAILURE,
RAMINIT_STATUS_JWRL_FAILURE,
@@ -244,6 +247,12 @@ struct raminit_dimm_info {
bool valid;
};
+struct vref_margin {
+ uint8_t low;
+ uint8_t center;
+ uint8_t high;
+};
+
struct sysinfo {
enum raminit_boot_mode bootmode;
enum generic_stepping stepping;
@@ -331,6 +340,8 @@ struct sysinfo {
uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
int8_t rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ struct vref_margin rxdqvrefpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
+
uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
uint8_t ctl_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
uint8_t cke_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
@@ -453,6 +464,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
enum raminit_status configure_mc(struct sysinfo *ctrl);
enum raminit_status configure_memory_map(struct sysinfo *ctrl);
enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl);
enum raminit_status train_receive_enable(struct sysinfo *ctrl);
enum raminit_status train_read_mpr(struct sysinfo *ctrl);
enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
diff --git a/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
new file mode 100644
index 0000000000..d4f199fefb
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
@@ -0,0 +1,341 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <lib.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+#define VREF_OFFSET_PLOT RAM_DEBUG
+#define SAMP_OFFSET_PLOT RAM_DEBUG
+
+struct vref_train_data {
+ int8_t best_sum;
+ int8_t best_vref;
+ int8_t sum_bits;
+ uint8_t high_mask;
+ uint8_t low_mask;
+};
+
+static enum raminit_status train_vref_offset(struct sysinfo *ctrl)
+{
+ const int8_t vref_start = -15;
+ const int8_t vref_stop = 15;
+ const struct vref_train_data initial_vref_values = {
+ .best_sum = -NUM_LANES,
+ .best_vref = 0,
+ .high_mask = 0,
+ .low_mask = 0xff,
+ };
+ struct vref_train_data vref_data[NUM_CHANNELS][NUM_LANES];
+
+ printk(VREF_OFFSET_PLOT, "Plot of sum_bits across Vref settings\nChannel");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ printk(VREF_OFFSET_PLOT, "\t%u\t\t", channel);
+ }
+
+ printk(VREF_OFFSET_PLOT, "\nByte");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ printk(VREF_OFFSET_PLOT, "\t");
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ printk(VREF_OFFSET_PLOT, "%u ", byte);
+ vref_data[channel][byte] = initial_vref_values;
+ union ddr_data_control_2_reg data_control_2 = {
+ .raw = ctrl->dq_control_2[channel][byte],
+ };
+ data_control_2.force_bias_on = 1;
+ data_control_2.force_rx_on = 1;
+ mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
+ }
+ }
+
+ /* Sweep through Vref settings and find point SampOffset of +/- 7 passes */
+ printk(VREF_OFFSET_PLOT, "\n1/2 Vref");
+ for (int8_t vref = vref_start; vref <= vref_stop; vref++) {
+ printk(VREF_OFFSET_PLOT, "\n% 3d", vref);
+
+ /*
+ * To perform this test, enable offset cancel mode and enable ODT.
+ * Check results and update variables. Ideal result is all zeroes.
+ * Clear offset cancel mode at end of test to write RX_OFFSET_VDQ.
+ */
+ change_1d_margin_multicast(ctrl, RdV, vref, 0, false, REG_FILE_USE_RANK);
+
+ /* Program settings for Vref and SampOffset = 7 (8 + 7) */
+ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0xffffffff);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ /* Propagate delay values (without a read command) */
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = ctrl->dq_control_0[channel],
+ };
+ data_control_0.read_rf_rd = 1;
+ data_control_0.read_rf_wr = 0;
+ data_control_0.read_rf_rank = 0;
+ data_control_0.force_odt_on = 1;
+ data_control_0.samp_train_mode = 1;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ udelay(1);
+ data_control_0.samp_train_mode = 0;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ const uint8_t feedback = get_data_train_feedback(channel, byte);
+ struct vref_train_data *curr_data = &vref_data[channel][byte];
+ curr_data->low_mask &= feedback;
+ curr_data->sum_bits = -popcnt(feedback);
+ }
+ }
+
+ /* Program settings for Vref and SampOffset = -7 (8 - 7) */
+ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0x11111111);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ /* Propagate delay values (without a read command) */
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = ctrl->dq_control_0[channel],
+ };
+ data_control_0.read_rf_rd = 1;
+ data_control_0.read_rf_wr = 0;
+ data_control_0.read_rf_rank = 0;
+ data_control_0.force_odt_on = 1;
+ data_control_0.samp_train_mode = 1;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ udelay(1);
+ data_control_0.samp_train_mode = 0;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ printk(VREF_OFFSET_PLOT, "\t");
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ const uint8_t feedback = get_data_train_feedback(channel, byte);
+ struct vref_train_data *curr_data = &vref_data[channel][byte];
+ curr_data->high_mask |= feedback;
+ curr_data->sum_bits += popcnt(feedback);
+ printk(VREF_OFFSET_PLOT, "%d ", curr_data->sum_bits);
+ if (curr_data->sum_bits > curr_data->best_sum) {
+ curr_data->best_sum = curr_data->sum_bits;
+ curr_data->best_vref = vref;
+ ctrl->rxvref[channel][0][byte] = vref;
+ } else if (curr_data->sum_bits == curr_data->best_sum) {
+ curr_data->best_vref = vref;
+ }
+ }
+ }
+ }
+ printk(BIOS_DEBUG, "\n\nHi-Lo (XOR):");
+ enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ printk(BIOS_DEBUG, "\n C%u:", channel);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ struct vref_train_data *const curr_data = &vref_data[channel][byte];
+ const uint8_t bit_xor = curr_data->high_mask ^ curr_data->low_mask;
+ printk(BIOS_DEBUG, "\t0x%02x", bit_xor);
+ if (bit_xor == 0xff)
+ continue;
+
+ /* Report an error if any bit did not change */
+ status = RAMINIT_STATUS_SAMP_OFFSET_FAILURE;
+ }
+ }
+ if (status)
+ printk(BIOS_ERR, "\nUnexpected bit error in Vref offset training\n");
+
+ printk(BIOS_DEBUG, "\n\nRdVref:");
+ change_1d_margin_multicast(ctrl, RdV, 0, 0, false, REG_FILE_USE_RANK);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ printk(BIOS_DEBUG, "\n C%u:", channel);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ struct vref_train_data *const curr_data = &vref_data[channel][byte];
+ const int8_t vref_width =
+ curr_data->best_vref - ctrl->rxvref[channel][0][byte];
+
+ /*
+ * Step size for Rx Vref in DATA_OFFSET_TRAIN is about 3.9 mV
+ * whereas Rx Vref step size in RX_TRAIN_RANK is about 7.8 mV
+ */
+ int8_t vref = ctrl->rxvref[channel][0][byte] + vref_width / 2;
+ if (vref < 0)
+ vref--;
+ else
+ vref++;
+
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+ if (!rank_in_ch(ctrl, rank, channel))
+ continue;
+
+ ctrl->rxvref[channel][rank][byte] = vref / 2;
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+ }
+ printk(BIOS_DEBUG, "\t% 4d", ctrl->rxvref[channel][0][byte]);
+ }
+ }
+ printk(BIOS_DEBUG, "\n\n");
+ return status;
+}
+
+/**
+ * LPDDR has an additional bit for DQS per each byte.
+ *
+ * TODO: The DQS value must be written into Data Control 2.
+ */
+#define NUM_OFFSET_TRAIN_BITS (NUM_BITS + 1)
+
+#define PLOT_CH_SPACE " "
+
+struct samp_train_data {
+ uint8_t first_zero;
+ uint8_t last_one;
+};
+
+static void train_samp_offset(struct sysinfo *ctrl)
+{
+ const uint8_t max_train_bits = ctrl->lpddr ? NUM_OFFSET_TRAIN_BITS : NUM_BITS;
+
+ struct samp_train_data samp_data[NUM_CHANNELS][NUM_LANES][NUM_OFFSET_TRAIN_BITS] = {0};
+
+ printk(BIOS_DEBUG, "Channel ");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ printk(BIOS_DEBUG, "%u ", channel); /* Same length as PLOT_CH_SPACE */
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ printk(BIOS_DEBUG, " %s ", ctrl->lpddr ? " " : "");
+ }
+ printk(BIOS_DEBUG, "\nByte ");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ printk(BIOS_DEBUG, "%u %s ", byte, ctrl->lpddr ? " " : "");
+
+ printk(BIOS_DEBUG, PLOT_CH_SPACE);
+ }
+ printk(SAMP_OFFSET_PLOT, "\nBits ");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ printk(SAMP_OFFSET_PLOT, "01234567%s ", ctrl->lpddr ? "S" : "");
+
+ printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
+ }
+ printk(SAMP_OFFSET_PLOT, "\n SAmp\n");
+ for (uint8_t samp_offset = 1; samp_offset <= 15; samp_offset++) {
+ printk(SAMP_OFFSET_PLOT, "% 5d\t", samp_offset);
+
+ uint32_t rx_offset_vdq = 0;
+ for (uint8_t bit = 0; bit < NUM_BITS; bit++) {
+ rx_offset_vdq += samp_offset << (4 * bit);
+ }
+ mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, rx_offset_vdq);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ /* Propagate delay values (without a read command) */
+ union ddr_data_control_0_reg data_control_0 = {
+ .raw = ctrl->dq_control_0[channel],
+ };
+ data_control_0.read_rf_rd = 1;
+ data_control_0.read_rf_wr = 0;
+ data_control_0.read_rf_rank = 0;
+ data_control_0.force_odt_on = 1;
+ data_control_0.samp_train_mode = 1;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ udelay(1);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ const uint32_t feedback =
+ get_data_train_feedback(channel, byte);
+
+ for (uint8_t bit = 0; bit < max_train_bits; bit++) {
+ struct samp_train_data *const curr_data =
+ &samp_data[channel][byte][bit];
+ const bool result = feedback & BIT(bit);
+ if (result) {
+ curr_data->last_one = samp_offset;
+ } else if (curr_data->first_zero == 0) {
+ curr_data->first_zero = samp_offset;
+ }
+ printk(SAMP_OFFSET_PLOT, result ? "." : "#");
+ }
+ printk(SAMP_OFFSET_PLOT, " ");
+ }
+ printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
+ data_control_0.samp_train_mode = 0;
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+ }
+ printk(SAMP_OFFSET_PLOT, "\n");
+ }
+ printk(BIOS_DEBUG, "\nBitSAmp ");
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+ uint32_t rx_offset_vdq = 0;
+ for (uint8_t bit = 0; bit < max_train_bits; bit++) {
+ struct samp_train_data *const curr_data =
+ &samp_data[channel][byte][bit];
+
+ uint8_t vref = curr_data->first_zero + curr_data->last_one;
+ vref = clamp_u8(0, vref / 2, 15);
+ /*
+ * Check for saturation conditions to make sure
+ * we are as close as possible to Vdd/2 (750 mV).
+ */
+ if (curr_data->first_zero == 0)
+ vref = 15;
+ if (curr_data->last_one == 0)
+ vref = 0;
+
+ ctrl->rxdqvrefpb[channel][0][byte][bit].center = vref;
+ rx_offset_vdq += vref & 0xf << (4 * bit);
+ printk(BIOS_DEBUG, "%x", vref);
+ }
+ mchbar_write32(RX_OFFSET_VDQ(channel, byte), rx_offset_vdq);
+ printk(BIOS_DEBUG, " ");
+ download_regfile(ctrl, channel, 1, 0, REG_FILE_USE_RANK, 0, 1, 0);
+ }
+ printk(BIOS_DEBUG, PLOT_CH_SPACE);
+ }
+ printk(BIOS_DEBUG, "\n");
+}
+
+enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl)
+{
+ printk(BIOS_DEBUG, "Stage 1: Vref offset training\n");
+ const enum raminit_status status = train_vref_offset(ctrl);
+
+ printk(BIOS_DEBUG, "Stage 2: Samp offset training\n");
+ train_samp_offset(ctrl);
+
+ /* Clean up after test */
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ if (!does_ch_exist(ctrl, channel))
+ continue;
+
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+ mchbar_write32(DQ_CONTROL_2(channel, byte),
+ ctrl->dq_control_2[channel][byte]);
+ }
+ io_reset();
+ return status;
+}
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 49a215aa71..1a168a3fc8 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -18,6 +18,8 @@
#define RX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0000, ch, rank, byte)
#define TX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0020, ch, rank, byte)
+#define RX_OFFSET_VDQ(ch, byte) _DDRIO_C_R_B(0x004c, ch, 0, byte)
+
#define DDR_DATA_TRAIN_FEEDBACK(ch, byte) _DDRIO_C_R_B(0x0054, ch, 0, byte)
#define DQ_CONTROL_1(ch, byte) _DDRIO_C_R_B(0x0060, ch, 0, byte)
--
2.39.5
@@ -0,0 +1,60 @@
From b9cc1be6f9d591dbc4f73b1448f8fce5ea20a0b4 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 20 Feb 2026 01:23:32 +0000
Subject: [PATCH 46/48] util/ifdtool: option to allow region override
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index d181888e0f..dfefe316a9 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -78,6 +78,8 @@ static unsigned int max_regions = 0;
static int selected_chip = 0;
static int platform = -1;
+static int ignore_region_override = 0;
+
static const struct region_name region_names[MAX_REGIONS] = {
{ "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" },
{ "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" },
@@ -2093,7 +2095,9 @@ static void new_layout(const char *filename, char *image, int size,
}
for (j = i + 1; j < max_regions; j++) {
- if (regions_collide(&new_regions[i], &new_regions[j])) {
+ if (ignore_region_override) {
+ printf("Ignoring region overlap by user's will.\n");
+ } else if (regions_collide(&new_regions[i], &new_regions[j])) {
fprintf(stderr, "Regions would overlap.\n");
exit(EXIT_FAILURE);
}
@@ -2351,10 +2355,11 @@ int main(int argc, char *argv[])
{"newvalue", 1, NULL, 'V'},
{"topswapsize", 1, NULL, 'T'},
{"nuke", 1, NULL, 'N'},
+ {"ignore-region-overlap", 0, NULL, 'I'},
{0, 0, 0, 0}
};
- while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?",
+ while ((opt = getopt_long(argc, argv, "I:S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?",
long_options, &option_index)) != EOF) {
switch (opt) {
case 'd':
@@ -2598,6 +2603,9 @@ int main(int argc, char *argv[])
}
mode_nuke = 1;
break;
+ case 'I':
+ ignore_region_override = 1;
+ break;
case 'v':
print_version();
exit(EXIT_SUCCESS);
--
2.47.3
@@ -0,0 +1,44 @@
From 1bc6028bf88ca6306ad89fc17fa6f31b9788b248 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 20 Feb 2026 19:31:19 +0000
Subject: [PATCH 47/48] me_cleaner: don't modify if -k is used
don't remove *anything*. in libreboot, we only
ever use -k when we werely want to extract the
ME, but otherwise not modify it. this is because
we rely on bruteforce, detecting when me.bin is
found based on mecleaner validation.
this way, we can much more reliable get the ME
images.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/me_cleaner/me_cleaner.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py
index 228bac899f..269aa4ad04 100755
--- a/util/me_cleaner/me_cleaner.py
+++ b/util/me_cleaner/me_cleaner.py
@@ -677,7 +677,7 @@ if __name__ == "__main__":
# ME 6 Ignition: wipe everything
me6_ignition = False
if not args.check and not args.soft_disable_only and \
- variant == "ME" and version[0] == 6:
+ variant == "ME" and version[0] == 6 and not args.keep_modules:
mef.seek(ftpr_offset + 0x20)
num_modules = unpack("<I", mef.read(4))[0]
mef.seek(ftpr_offset + 0x290 + (num_modules + 1) * 0x60)
@@ -689,7 +689,7 @@ if __name__ == "__main__":
me6_ignition = True
if not args.check:
- if not args.soft_disable_only and not me6_ignition:
+ if not args.soft_disable_only and not me6_ignition and not args.keep_modules:
print("Reading partitions list...")
unremovable_part_fpt = b""
extra_part_end = 0
--
2.47.3
@@ -1,243 +0,0 @@
From 92556743e92cc02524296b653de5241160876218 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Sep 2024 19:48:26 -0600
Subject: [PATCH 48/51] mb/dell: Convert E6400 into a variant
All the GM45 Dell Latitudes should be nearly identical, so convert the
E6400 port into a variant so that future ports for the other systems can
share code with each other.
Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6400/Makefile.mk | 10 --------
.../dell/{e6400 => gm45_latitude}/Kconfig | 22 +++++++++++++-----
.../{e6400 => gm45_latitude}/Kconfig.name | 0
src/mainboard/dell/gm45_latitude/Makefile.mk | 11 +++++++++
.../dell/{e6400 => gm45_latitude}/acpi/ec.asl | 0
.../acpi/ich9_pci_irqs.asl | 0
.../{e6400 => gm45_latitude}/acpi/superio.asl | 0
.../dell/{e6400 => gm45_latitude}/blc.c | 0
.../{e6400 => gm45_latitude}/board_info.txt | 0
.../dell/{e6400 => gm45_latitude}/bootblock.c | 0
.../{e6400 => gm45_latitude}/cmos.default | 0
.../dell/{e6400 => gm45_latitude}/cmos.layout | 0
.../dell/{e6400 => gm45_latitude}/cstates.c | 0
.../{e6400 => gm45_latitude}/devicetree.cb | 1 -
.../dell/{e6400 => gm45_latitude}/dsdt.asl | 0
.../dell/{e6400 => gm45_latitude}/mainboard.c | 0
.../dell/{e6400 => gm45_latitude}/romstage.c | 0
.../variants}/e6400/data.vbt | Bin
.../variants}/e6400/gma-mainboard.ads | 0
.../{ => gm45_latitude/variants}/e6400/gpio.c | 0
.../variants}/e6400/hda_verb.c | 0
.../variants/e6400/overridetree.cb | 7 ++++++
22 files changed, 34 insertions(+), 17 deletions(-)
delete mode 100644 src/mainboard/dell/e6400/Makefile.mk
rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig (64%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig.name (100%)
create mode 100644 src/mainboard/dell/gm45_latitude/Makefile.mk
rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ec.asl (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ich9_pci_irqs.asl (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/superio.asl (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/blc.c (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/board_info.txt (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/bootblock.c (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.default (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.layout (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/cstates.c (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/devicetree.cb (98%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/dsdt.asl (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/mainboard.c (100%)
rename src/mainboard/dell/{e6400 => gm45_latitude}/romstage.c (100%)
rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/data.vbt (100%)
rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gma-mainboard.ads (100%)
rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gpio.c (100%)
rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/hda_verb.c (100%)
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
diff --git a/src/mainboard/dell/e6400/Makefile.mk b/src/mainboard/dell/e6400/Makefile.mk
deleted file mode 100644
index ca3a82db48..0000000000
--- a/src/mainboard/dell/e6400/Makefile.mk
+++ /dev/null
@@ -1,10 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += gpio.c
-
-ramstage-y += cstates.c
-ramstage-y += blc.c
-
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
similarity index 64%
rename from src/mainboard/dell/e6400/Kconfig
rename to src/mainboard/dell/gm45_latitude/Kconfig
index 6fe1b1c456..ba76fb6e8c 100644
--- a/src/mainboard/dell/e6400/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
@@ -1,9 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
-if BOARD_DELL_E6400
-
-config BOARD_SPECIFIC_OPTIONS
- def_bool y
+config BOARD_DELL_GM45_LATITUDE_COMMON
+ def_bool n
select SYSTEM_TYPE_LAPTOP
select CPU_INTEL_SOCKET_P
select NORTHBRIDGE_INTEL_GM45
@@ -19,19 +17,31 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_GMA_HAVE_VBT
select EC_DELL_MEC5035
+
+config BOARD_DELL_E6400
+ select BOARD_DELL_GM45_LATITUDE_COMMON
+
+if BOARD_DELL_GM45_LATITUDE_COMMON
+
config INTEL_GMA_DPLL_REF_FREQ
default 100000000
config MAINBOARD_DIR
- default "dell/e6400"
+ default "dell/gm45_latitude"
config MAINBOARD_PART_NUMBER
default "Latitude E6400" if BOARD_DELL_E6400
+config OVERRIDE_DEVICETREE
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config VARIANT_DIR
+ default "e6400" if BOARD_DELL_E6400
+
config USBDEBUG_HCD_INDEX
default 1
config CBFS_SIZE
default 0x1A0000
-endif # BOARD_DELL_E6400
+endif # BOARD_DELL_GM45_LATITUDE_COMMON
diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
similarity index 100%
rename from src/mainboard/dell/e6400/Kconfig.name
rename to src/mainboard/dell/gm45_latitude/Kconfig.name
diff --git a/src/mainboard/dell/gm45_latitude/Makefile.mk b/src/mainboard/dell/gm45_latitude/Makefile.mk
new file mode 100644
index 0000000000..5295d5be22
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/Makefile.mk
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+
+ramstage-y += cstates.c
+ramstage-y += blc.c
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/gm45_latitude/acpi/ec.asl
similarity index 100%
rename from src/mainboard/dell/e6400/acpi/ec.asl
rename to src/mainboard/dell/gm45_latitude/acpi/ec.asl
diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
similarity index 100%
rename from src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
rename to src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/gm45_latitude/acpi/superio.asl
similarity index 100%
rename from src/mainboard/dell/e6400/acpi/superio.asl
rename to src/mainboard/dell/gm45_latitude/acpi/superio.asl
diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/gm45_latitude/blc.c
similarity index 100%
rename from src/mainboard/dell/e6400/blc.c
rename to src/mainboard/dell/gm45_latitude/blc.c
diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/gm45_latitude/board_info.txt
similarity index 100%
rename from src/mainboard/dell/e6400/board_info.txt
rename to src/mainboard/dell/gm45_latitude/board_info.txt
diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/gm45_latitude/bootblock.c
similarity index 100%
rename from src/mainboard/dell/e6400/bootblock.c
rename to src/mainboard/dell/gm45_latitude/bootblock.c
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/gm45_latitude/cmos.default
similarity index 100%
rename from src/mainboard/dell/e6400/cmos.default
rename to src/mainboard/dell/gm45_latitude/cmos.default
diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/gm45_latitude/cmos.layout
similarity index 100%
rename from src/mainboard/dell/e6400/cmos.layout
rename to src/mainboard/dell/gm45_latitude/cmos.layout
diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/gm45_latitude/cstates.c
similarity index 100%
rename from src/mainboard/dell/e6400/cstates.c
rename to src/mainboard/dell/gm45_latitude/cstates.c
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
similarity index 98%
rename from src/mainboard/dell/e6400/devicetree.cb
rename to src/mainboard/dell/gm45_latitude/devicetree.cb
index e9f3915d17..76dae87153 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
@@ -15,7 +15,6 @@ chip northbridge/intel/gm45
register "pci_mmio_size" = "2048"
device domain 0 on
- subsystemid 0x1028 0x0233 inherit
ops gm45_pci_domain_ops
device pci 00.0 on end # host bridge
diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/gm45_latitude/dsdt.asl
similarity index 100%
rename from src/mainboard/dell/e6400/dsdt.asl
rename to src/mainboard/dell/gm45_latitude/dsdt.asl
diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/gm45_latitude/mainboard.c
similarity index 100%
rename from src/mainboard/dell/e6400/mainboard.c
rename to src/mainboard/dell/gm45_latitude/mainboard.c
diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/gm45_latitude/romstage.c
similarity index 100%
rename from src/mainboard/dell/e6400/romstage.c
rename to src/mainboard/dell/gm45_latitude/romstage.c
diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
similarity index 100%
rename from src/mainboard/dell/e6400/data.vbt
rename to src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
similarity index 100%
rename from src/mainboard/dell/e6400/gma-mainboard.ads
rename to src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
similarity index 100%
rename from src/mainboard/dell/e6400/gpio.c
rename to src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
similarity index 100%
rename from src/mainboard/dell/e6400/hda_verb.c
rename to src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
diff --git a/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
new file mode 100644
index 0000000000..acc34a2252
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/gm45
+ device domain 0 on
+ subsystemid 0x1028 0x0233 inherit
+ end
+end
--
2.39.5
@@ -0,0 +1,600 @@
From f5f73c2539e05cf85bf5eec795e4f91da50838ba Mon Sep 17 00:00:00 2001
From: Kat Inskip <kat@inskip.me>
Date: Tue, 17 Feb 2026 16:18:15 -0800
Subject: [PATCH 48/48] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant
This machine is somewhat dissimilar from the X280 in the PCIe allocations in the overridetree. It also lacks soldered RAM, having a single SODIMM slot.
This port was based upon the work done by Johann C Rode for the X280 and the VBT and hda verbs were obtained from that work, not obtained separately. GPIO ports and PCI-e allocations have been checked against schematics after editing.
Functionality has been validated on a ThinkPad X270 with machine type model 20HMS2WU03 with 16GB onboard RAM and i5-7300U CPU. The laptop has been tested running libreboot, booting Guix via GRUB payload. A check of the hardware shows no issues (video, wifi, wired ethernet, reboot, sleep, NVMe).
An untested variety allowing for a Skylake CPU (for 20K5 and 20K6) has been included.
---
src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 14 ++
.../lenovo/sklkbl_thinkpad/Kconfig.name | 3 +
.../sklkbl_thinkpad/variants/x270/data.vbt | Bin 0 -> 6144 bytes
.../variants/x270/gma-mainboard.ads | 19 ++
.../sklkbl_thinkpad/variants/x270/gpio.c | 200 ++++++++++++++++++
.../sklkbl_thinkpad/variants/x270/hda_verb.c | 124 +++++++++++
.../variants/x270/memory_init_params.c | 19 ++
.../variants/x270/overridetree.cb | 89 ++++++++
8 files changed, 468 insertions(+)
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
index b7cc705699..5945fe7b99 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -58,6 +58,16 @@ config BOARD_LENOVO_X280
select SOC_INTEL_KABYLAKE
select HAVE_SPD_IN_CBFS
+config BOARD_LENOVO_X270_20K6
+ bool
+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+ select SOC_INTEL_SKYLAKE
+
+config BOARD_LENOVO_X270_20HM
+ bool
+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+ select SOC_INTEL_KABYLAKE
+
if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
config MAINBOARD_DIR
@@ -69,6 +79,8 @@ config VARIANT_DIR
default "t480s" if BOARD_LENOVO_T480S
default "t580" if BOARD_LENOVO_T580
default "x280" if BOARD_LENOVO_X280
+ default "x270" if BOARD_LENOVO_X270_20HM
+ default "x270" if BOARD_LENOVO_X270_20K6
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
@@ -79,6 +91,8 @@ config MAINBOARD_PART_NUMBER
default "T480s" if BOARD_LENOVO_T480S
default "T580" if BOARD_LENOVO_T580
default "X280" if BOARD_LENOVO_X280
+ default "X270" if BOARD_LENOVO_X270_20HM
+ default "X270" if BOARD_LENOVO_X270_20K6
config CBFS_SIZE
default 0x900000
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
index 1d2888840f..43f9296bc5 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
@@ -14,3 +14,6 @@ config BOARD_LENOVO_T580
config BOARD_LENOVO_X280
bool "ThinkPad X280"
+
+config BOARD_LENOVO_X270_20HM
+ bool "ThinkPad X270"
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..bfb312850e0ab4ea834c535df35edb45834ed248
GIT binary patch
literal 6144
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zX3{w6L5jA=55^B2O=tEU8cII^4Wm=b)7I1A=v1~qV!HDZ{Y9GY{GJ!)WJ`0;WudU2
z?%VTZTSVK|z$@((W&{}Qr^71++qk#jN4{YO;LIHTH^k+$U4C26Ksf{D43sla&OkW>
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literal 0
HcmV?d00001
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads
new file mode 100644
index 0000000000..fcfbd75a92
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (eDP,
+ DP1,
+ DP2,
+ HDMI1,
+ HDMI2,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c
new file mode 100644
index 0000000000..ec5db9c53c
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c
@@ -0,0 +1,200 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../variant.h"
+
+static const struct pad_config gpio_table[] = {
+ /* ------- GPIO Community 0 ------- */
+
+ /* ------- GPIO Group GPP_A ------- */
+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */
+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */
+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */
+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */
+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */
+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */
+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */
+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */
+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */
+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */
+ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */
+ PAD_NC(GPP_A11, NONE),
+ PAD_NC(GPP_A12, NONE), /* BM_BUSY#/ISH_GP6 */
+ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */
+ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */
+ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSACK*/
+ PAD_NC(GPP_A16, NONE),
+ PAD_NC(GPP_A17, NONE),
+ PAD_NC(GPP_A18, NONE), /* ISH_GP0 */
+ PAD_NC(GPP_A19, NONE), /* ISH_GP1 */
+ PAD_NC(GPP_A20, NONE), /* ISH_GP2 */
+ PAD_NC(GPP_A21, NONE), /* ISH_GP3 */
+ PAD_NC(GPP_A22, NONE), /* ISH_GP4 */
+ PAD_NC(GPP_A23, NONE), /* ISH_GP5 */
+
+ /* ------- GPIO Group GPP_B ------- */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */
+ PAD_NC(GPP_B2, NONE),
+ PAD_NC(GPP_B3, NONE),
+ PAD_NC(GPP_B4, NONE),
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (Card Reader / SD) */
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE1 (WLAN) */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE2 (GBE) */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (NVMe) */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WWAN) */
+ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* -EXT_PWR_GATE */
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */
+ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */
+ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */
+ PAD_NC(GPP_B16, NONE), /* GSPIO0_CLK */
+ PAD_NC(GPP_B17, NONE),
+ PAD_NC(GPP_B18, NONE),
+ PAD_NC(GPP_B19, NONE),
+ PAD_NC(GPP_B20, NONE),
+ PAD_NC(GPP_B21, NONE),
+ PAD_NC(GPP_B22, NONE),
+ PAD_NC(GPP_B23, NONE),
+
+ /* ------- GPIO Community 1 ------- */
+
+ /* ------- GPIO Group GPP_C ------- */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
+ PAD_NC(GPP_C2, NONE), /* -SMBALERT */
+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */
+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
+ PAD_NC(GPP_C5, NONE),
+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */
+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */
+ PAD_NC(GPP_C8, NONE),
+ PAD_NC(GPP_C9, NONE),
+ PAD_NC(GPP_C10, NONE),
+ PAD_NC(GPP_C11, NONE),
+ PAD_NC(GPP_C12, NONE),
+ PAD_NC(GPP_C13, NONE),
+ PAD_NC(GPP_C14, NONE),
+ PAD_NC(GPP_C15, NONE),
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */
+ PAD_NC(GPP_C18, NONE),
+ PAD_NC(GPP_C19, NONE),
+ PAD_NC(GPP_C20, NONE),
+ PAD_NC(GPP_C21, NONE), /* X280: TBT_FORCE_PWR X270: INT#_TYPEC_CPU */
+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
+
+ /* ------- GPIO Group GPP_D ------- */
+ PAD_NC(GPP_D0, NONE),
+ PAD_NC(GPP_D1, NONE),
+ PAD_NC(GPP_D2, NONE),
+ PAD_NC(GPP_D3, NONE),
+ PAD_NC(GPP_D4, NONE),
+ PAD_NC(GPP_D5, NONE),
+ PAD_NC(GPP_D6, NONE),
+ PAD_NC(GPP_D7, NONE),
+ PAD_NC(GPP_D8, NONE),
+ PAD_NC(GPP_D9, UP_20K),
+ PAD_NC(GPP_D10, NONE),
+ PAD_NC(GPP_D11, UP_20K),
+ PAD_NC(GPP_D12, UP_20K),
+ PAD_NC(GPP_D13, NONE),
+ PAD_NC(GPP_D14, NONE),
+ PAD_NC(GPP_D15, NONE),
+ PAD_NC(GPP_D16, NONE),
+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */
+ PAD_NC(GPP_D18, NONE),
+ PAD_NC(GPP_D19, NONE),
+ PAD_NC(GPP_D20, NONE),
+ PAD_NC(GPP_D21, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */
+ PAD_NC(GPP_D23, NONE),
+
+ /* ------- GPIO Group GPP_E ------- */
+ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */
+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -SATA1_DTCT */
+ PAD_NC(GPP_E2, NONE),
+ PAD_NC(GPP_E3, NONE), /* X280: -TBT_PLUG_EVENT X270: ? */
+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */
+ PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA1_DEVSLP */
+ PAD_NC(GPP_E6, NONE),
+ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* -WWAN_DISABLE */
+ PAD_NC(GPP_E8, NONE),
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */
+ PAD_NC(GPP_E11, NONE),
+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */
+ PAD_NC(GPP_E15, NONE),
+ PAD_NC(GPP_E16, NONE),
+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
+ PAD_NC(GPP_E18, NONE),
+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */
+ PAD_NC(GPP_E22, NONE),
+ PAD_NC(GPP_E23, NONE),
+
+ /* ------- GPIO Community 2 ------- */
+
+ /* -------- GPIO Group GPD -------- */
+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */
+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */
+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */
+ PAD_NC(GPD7, NONE),
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */
+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */
+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
+
+ /* ------- GPIO Community 3 ------- */
+
+ /* ------- GPIO Group GPP_F ------- */
+ PAD_NC(GPP_F0, NONE), /* NFC_ACTIVE */
+ PAD_NC(GPP_F1, NONE),
+ PAD_NC(GPP_F2, NONE),
+ PAD_NC(GPP_F3, NONE),
+ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */
+ PAD_NC(GPP_F5, UP_20K),
+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI), /* -INT_MIC_DTCT */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG1 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG2 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG3 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI), /* PLANARID0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI), /* PLANARID1 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI), /* PLANARID2 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI), /* PLANARID3 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID1 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID2 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID3 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID4 */
+ PAD_NC(GPP_F21, UP_20K),
+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI), /* -TAMPER_SW_DTCT */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI), /* -SC_DTCT */
+
+ /* ------- GPIO Group GPP_G ------- */
+ PAD_NC(GPP_G0, NONE), /* SD_CMD */
+ PAD_NC(GPP_G1, NONE), /* SD_DATA0 */
+ PAD_NC(GPP_G2, NONE), /* SD_DATA1 */
+ PAD_NC(GPP_G3, NONE), /* SD_DATA2 */
+ PAD_NC(GPP_G4, NONE), /* X280: TBT_RTD3_PWR_EN X270: SD_DATA3 */
+ PAD_NC(GPP_G5, NONE), /* X280: TBT_FORCE_USB_PWR X270: SD_CD# */
+ PAD_NC(GPP_G6, NONE), /* X280: -TBT_PERST X270: SD_CLK */
+ PAD_NC(GPP_G7, NONE), /* X280: -TBT_PCIE_WAKE X270: SD_WP */
+
+};
+
+void variant_config_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
new file mode 100644
index 0000000000..089e605eaf
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257
+ 0x17aa2256, // Subsystem ID
+ 18,
+ AZALIA_SUBVENDOR(0, 0x17aa2256),
+
+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+ AZALIA_INTEGRATED,
+ AZALIA_INTERNAL,
+ AZALIA_MIC_IN,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_NO_JACK_PRESENCE_DETECT,
+ 2, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+ AZALIA_INTEGRATED,
+ AZALIA_INTERNAL,
+ AZALIA_SPEAKER,
+ AZALIA_OTHER_ANALOG,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_NO_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+ AZALIA_MIC_IN,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_BLACK,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 3, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+ AZALIA_HP_OUT,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_BLACK,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 15
+ )),
+
+ //==========Widget node 0x20 - 0 :Hidden register SW reset
+ 0x0205001A,
+ 0x0204C003,
+ 0x0205001A,
+ 0x0204C003,
+ 0x05850000,
+ 0x0584F880,
+ 0x05850000,
+ 0x0584F880,
+ //==========Widget node 0x20 - 1 : ClassD 2W
+ 0x02050038,
+ 0x02048981,
+ 0x0205001B,
+ 0x02040A4B,
+ //==========Widget node 0x20 - 2
+ 0x0205003C,
+ 0x02043154,
+ 0x0205003C,
+ 0x02043114,
+ //==========Widget node 0x20 - 3 :
+ 0x02050046,
+ 0x02040004,
+ 0x05750003,
+ 0x057409A3,
+ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD
+ 0x02050009,
+ 0x02046003,
+ 0x0205000A,
+ 0x02047770,
+ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB)
+ 0x02050037,
+ 0x0204FE15,
+ 0x02050030,
+ 0x02049004,
+
+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
+ 0x80860101, // Subsystem ID
+ 4,
+ AZALIA_SUBVENDOR(2, 0x80860101),
+
+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+};
+
+const u32 pc_beep_verbs[] = {};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c
new file mode 100644
index 0000000000..a2317c026d
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/romstage.h>
+#include <spd_bin.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+ mem_cfg->DqPinsInterleaved = false; /* DDR_DQ probably not in interleave mode */
+ mem_cfg->CaVrefConfig = 1; /* VREF_CA to CH_A */
+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
+
+ /* Get SPD for memory slots */
+ struct spd_block blk = { .addr_map = { 0x50 } };
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb
new file mode 100644
index 0000000000..3191cdfac5
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+ device domain 0 on
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on)
+ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A)
+ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot)
+ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB docking station)
+ [4] = USB2_PORT_MID(OC_SKIP), // JIRCAM (IR camera)
+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB)
+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB)
+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam)
+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader)
+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel)
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on)
+ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A)
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader)
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSB3 (USB docking station)
+ }"
+ end
+
+ # PCIe
+ # PCIe Controller 1 - 1x2 + 2x1
+ # PCIE 1 - RP1 - Media / SD - CLKOUT0 - CLKREQ0
+ # PCIE 2 - USB3 Port
+ # PCIE 3 - RP3 - WiGig - CLKOUT1 - CLKREQ1
+ # PCIE 3 - RP3 - WLAN - CLKOUT2 - CLKREQ2
+ # PCIE 4 - GbE - GbE - CLKOUT3 - CLKREQ3
+ # PCIe Controller 2 - 1x4
+ # PCIE 5 - RP5 - NVMe - CLKOUT4 - CLKREQ4
+ # PCIe Controller 3 - 4x1
+ # PCIE 7 - RP8 - WWAN - CLKOUT5 - CLKREQ5
+ # PCIE 8 - Optane
+
+ # Media / SD - x2
+ device ref pcie_rp1 on
+ register "PcieRpClkReqSupport[0]" = "true"
+ register "PcieRpClkReqNumber[0]" = "0"
+ register "PcieRpClkSrcNumber[0]" = "0"
+ register "PcieRpAdvancedErrorReporting[0]" = "true"
+ register "PcieRpHotPlug[0]" = "true"
+ end
+
+ # M.2 WLAN x1
+ device ref pcie_rp3 on
+ register "PcieRpClkReqSupport[2]" = "true"
+ register "PcieRpClkReqNumber[2]" = "2"
+ register "PcieRpClkSrcNumber[2]" = "2"
+ register "PcieRpAdvancedErrorReporting[2]" = "true"
+ register "PcieRpLtrEnable[2]" = "true"
+ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
+ end
+
+ # Ethernet (clobbers RP4)
+ device ref gbe on
+ register "LanClkReqSupported" = "true"
+ register "LanClkReqNumber" = "3"
+ register "PcieRpClkReqNumber[3]" = "3"
+ register "PcieRpClkSrcNumber[3]" = "3"
+ register "EnableLanLtr" = "true"
+ register "EnableLanK1Off" = "true"
+ end
+
+ # M.2 2280 SSD - x4 (RP9)
+ device ref pcie_rp5 on
+ register "PcieRpClkReqSupport[4]" = "true"
+ register "PcieRpClkReqNumber[4]" = "4"
+ register "PcieRpClkSrcNumber[4]" = "4"
+ register "PcieRpAdvancedErrorReporting[4]" = "true"
+ register "PcieRpLtrEnable[4]" = "true"
+ register "PcieRpHotPlug[4]" = "false"
+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
+ end
+
+ # M.2 WWAN x1
+ device ref pcie_rp8 on
+ register "PcieRpClkReqSupport[7]" = "true"
+ register "PcieRpClkReqNumber[7]" = "5"
+ register "PcieRpClkSrcNumber[7]" = "5"
+ register "PcieRpAdvancedErrorReporting[7]" = "true"
+ register "PcieRpLtrEnable[7]" = "true"
+ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
+ end
+ end
+end
--
2.47.3
@@ -0,0 +1,132 @@
From 9d39437b9447ab6e6164440bddf459111bd4903f Mon Sep 17 00:00:00 2001
From: Kat Inskip <kat@inskip.me>
Date: Sat, 21 Feb 2026 19:48:17 +0000
Subject: [PATCH] mb/lenovo/x270: Provide correct vbt and hda_verb
---
.../sklkbl_thinkpad/variants/x270/data.vbt | Bin 6144 -> 4449 bytes
.../sklkbl_thinkpad/variants/x270/hda_verb.c | 29 +++++++++---------
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt
index bfb312850e0ab4ea834c535df35edb45834ed248..c6561a9c57e4e600bc0adb5f6679f2f5d6b6c640 100644
GIT binary patch
delta 1043
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z_MVtzqhMg55a6s}XrgCqqM%@?Z)B)%WMF8jpkQcVWoTw)YB_PgJ|n}#S5l0olUW%J
zmH8bQ7#aQ=F)(m2Ft9K%I51!UfyozHMC%0@m~0uDSQr@8IT+X^kQH$;FffDp4h#xl
z8bl~CurORpU|?Wi|HJ{}Gcd3-Ft9R!tPx;TV1x)UFbFU>fRs5fu(NPN#30UK;9yW-
zRA7P#ft0y`jTR8#5QD0NNii@mDnP7fU|>*S5CDk_2ry`1Q#Lt(Nn)}ATY5b+BLl;q
zDh37ys6!YT7(sx6fsfIEA&*mz!Jk=!p@x}>p^e#sL5t-Cg8-)jgE6N7gBzy+LnNmF
z!(~=3hP$j>49{7)7(TLcG5lubVqj(CV&G@vVvuCxVo+w|V$fydVlZdpVsK>RV(@0;
zVhCm9Vu)wsV#s9k=3-zgW%%=-sR0x!3=9knjO-wHGc*W7Xa)fmhCWS(hB;92IZ$!V
z4=iAHTu_?(1IuJZHeH|p|Jm6Y{{25E!SMe-hb_othYu_u&oR0{ReC^aA27|#8~~;n
z7(yWG7$Ttj|Nl2@GH+mFWY~O*Rg<|MY#YO>RjXDpFlbI;V0PwG$m9~L=HhDQQdrF;
zw3mzPIG4g(E}{QiT%6nr`rJZ}++5z=3WeN4&D>nQ+zOkyg^qG_o#$5g$}Pms!zIY0
zV9q1t$-@=Qqfp5s)Xl>+l}BMWkI-2juIoGse|d!XdATHc73_J10(rTjc@?x9d4(qP
za?RycILs?_m6z*2uL3KdkT@TgBA<dgpHL(pS27>3mJn+L(*wrIjyy_}&vV92KFDLv
zD6u(}E1HG>1Or3FDlZ6mhk<$WLq5C7@A-r#%kwKri!pS#F)%QAGH@}3G6XQBFz7H&
kV|c;Lpl851c_M$+Bmr(DBv}6+5)=${r;WiWnGIq+0Ot0jSpWb4
delta 808
zcmaE;)L<|{f|X04kilTGBa`q%0|BLr3}Oto`2W3PU`SzPl;klqFf;bdD@o1K2+~vt
z_V&^DcA6MxqiANV5a6s}XrgCqqM%@4sBdVdZ)9L-si0tBY-MU@WoSNem;S_eVvL59
zSs4xM*_{{|8U7kE@Nlqra5!jiC`fP!xUe{=uqcSI2n09?BseG-C<yqlIOwn_$Z!Z4
zC<sJ22t)`t2rw|2GBU9+FsN}b9IIe}0tE(x>s$;B%pfk41A_vHW&l$x4A&AE92giP
zgh70R>+B2+tPBhcP7Le<j0%ikbs*IaP-R(AWgH9)EFejC1x5uX5Cd!&m?0p*Q3Fyn
zS&>OpPyu8rNLWCCp${g?0TZ2U$Rsz}l1X5)C6gG8t_NAi%*ep-r;34r0pbFX0T9f`
zXuz<9Lk_}$k_pTw7~D7%7&18o7-~2K82UK`7&uwE7=&557-U(w7}Qz07z|mt7_3>j
z7+hJo82nke7$RA@7?N4J7;;&;7|L0>7#dl*7`j=x7^bqaaWTwi<zm?UnRx>frvL*3
zg8+j7gW=>2Y~q^_vvD!kgT2kLYSpS$3=Eo67?>+L73OmaZRF(I&8hH^Q|L1%*I!Nr
zWiBC8E-rg6g;Xw~axSh$E`{Y>LOZ#*4s$8I<P!SL#l_04pv^60%gyD^t&qztRL{-T
z$*r)STj(G+*J*BrkK97cJY2jy3dTG_t~^}+JPM^eLhU?U6L}PrxAO>{<l(x^qwteQ
zh?|#7lvlx;SIC!_E1XxMmRG2smun{P<b19U?gn-XmIgsS1{-FB$p^Tkh5XGL78F=0
zIT+cjV-T4mz`!86S)V(ag<n9OA!3!+2?h{(kC|oiMt+OQ`}rj%zvNex5@qOgV_;zL
yWZ+^5We8wMVbEcm#_)n!Zv(^RK!MiD2L!|>9}tk){DbW~<0kg^a6CDHNgDv8%8_CK
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
index 089e605eaf..60289355f8 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
@@ -3,10 +3,10 @@
#include <device/azalia_device.h>
const u32 cim_verb_data[] = {
- 0x10ec0257, // Vendor/Device ID: Realtek ALC257
- 0x17aa2256, // Subsystem ID
- 18,
- AZALIA_SUBVENDOR(0, 0x17aa2256),
+ 0x10ec0298, // Vendor/Device ID: Realtek ALC298
+ 0x17aa5062, // Subsystem ID
+ 19,
+ AZALIA_SUBVENDOR(0, 0x17aa5062),
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
AZALIA_INTEGRATED,
@@ -15,7 +15,7 @@ const u32 cim_verb_data[] = {
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_NO_JACK_PRESENCE_DETECT,
- 2, 0
+ 4, 0
)),
AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
@@ -27,28 +27,29 @@ const u32 cim_verb_data[] = {
AZALIA_NO_JACK_PRESENCE_DETECT,
1, 0
)),
- AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
- AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC(
AZALIA_JACK,
- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
AZALIA_MIC_IN,
AZALIA_STEREO_MONO_1_8,
AZALIA_BLACK,
AZALIA_JACK_PRESENCE_DETECT,
3, 0
)),
+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
- AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
- AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
+ AZALIA_PIN_CFG(0, 0x1d, 0x40648605), // does not describe a jack or internal device
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
AZALIA_JACK,
- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
AZALIA_HP_OUT,
AZALIA_STEREO_MONO_1_8,
AZALIA_BLACK,
AZALIA_JACK_PRESENCE_DETECT,
- 1, 15
+ 2, 0
)),
//==========Widget node 0x20 - 0 :Hidden register SW reset
@@ -107,7 +108,7 @@ const u32 cim_verb_data[] = {
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
- 1, 0
+ 2, 0
)),
AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
AZALIA_JACK,
@@ -116,7 +117,7 @@ const u32 cim_verb_data[] = {
AZALIA_OTHER_DIGITAL,
AZALIA_COLOR_UNKNOWN,
AZALIA_JACK_PRESENCE_DETECT,
- 1, 0
+ 3, 0
)),
};
--
2.52.0
File diff suppressed because it is too large Load Diff
@@ -1,92 +0,0 @@
From 1a342c20b8705bbea02d27a73e383ee2808f2558 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Tue, 18 Jun 2024 21:31:08 -0600
Subject: [PATCH 51/51] ec/dell/mec5035: Route power button event to host
If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
power button results in the EC powering off the system without letting
the OS cleanly shutting itself down. This command and argument tells the
EC to route power button events to the host so that it can determine
what to do.
The EC command was identified from the ec/google/wilco code, which is
used for Dell's Latitude Chromebooks. According to the EC_GOOGLE_WILCO
Kconfig help text, those ECs run a modified version of Dell's typical
Latitude EC firmware, so it is likely that the two firmware
implementations use similar commands. Examining LPC traffic between the
host and the EC on the Latitude E6400 did reveal that the same command
was being sent by the vendor firmware to the EC, but this does not
confirm that it has the same meaning as the command from the Wilco code.
Sending the command using inb/outb calls in a userspace C program while
running coreboot without this patch did allow subsequent power button
events to be handled by the host, confirming that the command was indeed
the same.
Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/mec5035.c | 8 ++++++++
src/ec/dell/mec5035/mec5035.h | 7 +++++++
2 files changed, 15 insertions(+)
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index 85c2ab0140..bdae929a27 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
ec_command(CMD_RADIO_CTRL);
}
+void mec5035_power_button_route(enum ec_power_button_route target)
+{
+ u8 buf = (u8)target;
+ write_mailbox_regs(&buf, 2, 1);
+ ec_command(CMD_POWER_BUTTON_TO_HOST);
+}
+
void mec5035_change_wake(u8 source, enum ec_wake_change change)
{
u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
@@ -121,6 +128,7 @@ static void mec5035_init(struct device *dev)
/* Unconditionally use this argument for now as this setting
is probably the most sensible default out of the 3 choices. */
mec5035_mouse_touchpad(TP_PS2_MOUSE);
+ mec5035_power_button_route(HOST);
pc_keyboard_init(NO_AUX_DEVICE);
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index 8d4fded28b..51422598c4 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -11,6 +11,7 @@
enum mec5035_cmd {
CMD_MOUSE_TP = 0x1a,
CMD_RADIO_CTRL = 0x2b,
+ CMD_POWER_BUTTON_TO_HOST = 0x3e,
CMD_ACPI_WAKEUP_CHANGE = 0x4a,
CMD_SLEEP_ENABLE = 0x64,
CMD_CPU_OK = 0xc2,
@@ -36,6 +37,11 @@ enum ec_radio_state {
RADIO_ON
};
+enum ec_power_button_route {
+ EC = 0,
+ HOST
+};
+
#define ACPI_WAKEUP_NUM_ARGS 4
enum ec_wake_change {
WAKE_OFF = 0,
@@ -55,6 +61,7 @@ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
void mec5035_cpu_ok(void);
void mec5035_early_init(void);
void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
+void mec5035_power_button_route(enum ec_power_button_route target);
void mec5035_change_wake(u8 source, enum ec_wake_change change);
void mec5035_sleep_enable(void);
--
2.39.5
@@ -0,0 +1,46 @@
From 88519aed6c7f305f7f2319e335c1421137df7ce3 Mon Sep 17 00:00:00 2001
From: Ron Nazarov <ron@noisytoot.org>
Date: Mon, 23 Mar 2026 17:04:03 +0000
Subject: [PATCH] mb/supermicro/x11-lga1151-series: Enable SATA hotplug
Before this patch, hotplugging only worked to replace drives (if you
tried to plug a drive into a SATA port that no drive was plugged in to
at boot, it wouldn't be detected) and you'd have to manually rescan
the bus (echo "- - -" > /sys/class/scsi_host/host*/scan) to make
plugs/unplugs get detected by the operating system.
Now, hotplugging works for all ports (tested and working on Supermicro
X11SSH-LN4F) and there's no need to manually rescan (it sometimes
takes a few seconds for unplugs to be detected, but plugs are detected
instantly).
Change-Id: Id978a047697795ea657048fb6dc6665736c293f9
Signed-off-by: Ron Nazarov <ron@noisytoot.org>
---
.../supermicro/x11-lga1151-series/devicetree.cb | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index fbf896c6ae..d25288420f 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -28,6 +28,16 @@ chip soc/intel/skylake
[6] = 1,
[7] = 1,
}"
+ register "SataPortsHotPlug" = "{
+ [0] = 1,
+ [1] = 1,
+ [2] = 1,
+ [3] = 1,
+ [4] = 1,
+ [5] = 1,
+ [6] = 1,
+ [7] = 1,
+ }"
end
device ref lpc_espi on
register "serirq_mode" = "SERIRQ_CONTINUOUS"
--
2.52.0
+3 -1
View File
@@ -1,2 +1,4 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
rev="97bc693abc482139774a656212935387d43df8e2"
rev="ed5a993f0f98a47d5e780e375e5861860019b183"
@@ -18,6 +18,7 @@ CONFIG_COMPILER_GCC=y
# CONFIG_UTIL_GENPARSER is not set
CONFIG_OPTION_BACKEND_NONE=y
# CONFIG_USE_OPTION_TABLE is not set
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_SEPARATE_ROMSTAGE=y
@@ -86,7 +87,9 @@ CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@@ -111,12 +114,12 @@ CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3040 Micro"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/optiplex_3050"
CONFIG_MAINBOARD_DIR="dell/optiplex_3040"
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=512
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
@@ -144,16 +147,17 @@ CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3040 Micro"
# CONFIG_CONSOLE_POST is not set
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_USE_PM_ACPI_TIMER=y
# CONFIG_BOARD_DELL_E6400 is not set
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
CONFIG_BOARD_DELL_OPTIPLEX_3050=y
# CONFIG_BOARD_DELL_E4300 is not set
# CONFIG_BOARD_DELL_E6400 is not set
CONFIG_BOARD_DELL_OPTIPLEX_3040=y
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
@@ -178,23 +182,23 @@ CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_USE_LEGACY_8254_TIMER=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
CONFIG_IFD_BIN_PATH="../../../config/ifd/3040micro/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/3040micro/me.bin"
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
CONFIG_USE_LEGACY_8254_TIMER=y
# CONFIG_DEBUG_SMI is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
CONFIG_HAVE_IFD_BIN=y
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
CONFIG_TTYS0_BAUD=115200
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
CONFIG_D3COLD_SUPPORT=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
@@ -202,9 +206,6 @@ CONFIG_DRIVERS_UART_8250IO=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -238,8 +239,8 @@ CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
# SoC
#
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd"
CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd"
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
@@ -286,8 +287,9 @@ CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
CONFIG_SOC_INTEL_KABYLAKE=y
CONFIG_SKYLAKE_SOC_PCH_H=y
CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
# CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU is not set
# CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU is not set
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FSP_T_LOCATION=0xfffe0000
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
@@ -314,7 +316,7 @@ CONFIG_INTEL_CAR_NEM_ENHANCED=y
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
CONFIG_HAVE_HYPERTHREADING=y
CONFIG_FSP_HYPERTHREADING=y
# CONFIG_FSP_HYPERTHREADING is not set
# CONFIG_INTEL_KEYLOCKER is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
@@ -329,10 +331,7 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME="ME_RW_A"
CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME="ME_RW_B"
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
CONFIG_SOC_INTEL_CSE_RW_HASH_CBFS_NAME="me_rw.hash"
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
CONFIG_SOC_INTEL_CSE_RW_FILE=""
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
@@ -432,6 +431,7 @@ CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_CPU_PT_ROM_MAP_GB=512
CONFIG_SMM_TSEG=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
@@ -548,6 +548,7 @@ CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -574,6 +575,7 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_CACHE_MRC_SETTINGS=y
CONFIG_MRC_SETTINGS_PROTECT=y
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -582,6 +584,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -589,21 +592,18 @@ CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_FSP_USE_REPO=y
# CONFIG_FSP_USE_REPO is not set
# CONFIG_DISPLAY_HOBS is not set
# CONFIG_DISPLAY_UPD_DATA is not set
# CONFIG_BMP_LOGO is not set
CONFIG_PLATFORM_USES_FSP2_0=y
CONFIG_PLATFORM_USES_FSP2_X86_32=y
CONFIG_HAVE_INTEL_FSP_REPO=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_S_CBFS="fsps.bin"
CONFIG_FSP_M_CBFS="fspm.bin"
CONFIG_FSP_FULL_FD=y
# CONFIG_FSP_FULL_FD is not set
CONFIG_FSP_T_RESERVED_SIZE=0x0
CONFIG_FSP_M_XIP=y
CONFIG_HAVE_FSP_LOGO_SUPPORT=y
CONFIG_FSP_COMPRESS_FSP_S_LZ4=y
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
@@ -806,6 +806,13 @@ CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
@@ -18,6 +18,7 @@ CONFIG_COMPILER_GCC=y
# CONFIG_UTIL_GENPARSER is not set
CONFIG_OPTION_BACKEND_NONE=y
# CONFIG_USE_OPTION_TABLE is not set
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_SEPARATE_ROMSTAGE=y
@@ -86,7 +87,9 @@ CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@@ -111,12 +114,12 @@ CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3040 Micro"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/optiplex_3050"
CONFIG_MAINBOARD_DIR="dell/optiplex_3040"
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=512
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
@@ -142,16 +145,17 @@ CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3040 Micro"
# CONFIG_CONSOLE_POST is not set
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_MAX_SOCKET=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_USE_PM_ACPI_TIMER=y
# CONFIG_BOARD_DELL_E6400 is not set
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
CONFIG_BOARD_DELL_OPTIPLEX_3050=y
# CONFIG_BOARD_DELL_E4300 is not set
# CONFIG_BOARD_DELL_E6400 is not set
CONFIG_BOARD_DELL_OPTIPLEX_3040=y
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
@@ -176,23 +180,23 @@ CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_USE_LEGACY_8254_TIMER=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
CONFIG_IFD_BIN_PATH="../../../config/ifd/3040micro/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/3040micro/me.bin"
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
CONFIG_USE_LEGACY_8254_TIMER=y
# CONFIG_DEBUG_SMI is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
CONFIG_HAVE_IFD_BIN=y
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
CONFIG_TTYS0_BAUD=115200
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
CONFIG_D3COLD_SUPPORT=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
@@ -200,9 +204,6 @@ CONFIG_DRIVERS_UART_8250IO=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
CONFIG_EC_GPE_SCI=0x50
CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
CONFIG_BOARD_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -236,8 +237,8 @@ CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
# SoC
#
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd"
CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd"
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
@@ -284,8 +285,9 @@ CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
CONFIG_SOC_INTEL_KABYLAKE=y
CONFIG_SKYLAKE_SOC_PCH_H=y
CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
# CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU is not set
# CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU is not set
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FSP_T_LOCATION=0xfffe0000
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
@@ -312,7 +314,7 @@ CONFIG_INTEL_CAR_NEM_ENHANCED=y
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
CONFIG_HAVE_HYPERTHREADING=y
CONFIG_FSP_HYPERTHREADING=y
# CONFIG_FSP_HYPERTHREADING is not set
# CONFIG_INTEL_KEYLOCKER is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
@@ -327,10 +329,7 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME="ME_RW_A"
CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME="ME_RW_B"
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
CONFIG_SOC_INTEL_CSE_RW_HASH_CBFS_NAME="me_rw.hash"
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
CONFIG_SOC_INTEL_CSE_RW_FILE=""
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
@@ -430,6 +429,7 @@ CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_CPU_PT_ROM_MAP_GB=512
CONFIG_SMM_TSEG=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
@@ -540,6 +540,7 @@ CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -566,6 +567,7 @@ CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_CACHE_MRC_SETTINGS=y
CONFIG_MRC_SETTINGS_PROTECT=y
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -574,6 +576,7 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -581,21 +584,18 @@ CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_FSP_USE_REPO=y
# CONFIG_FSP_USE_REPO is not set
# CONFIG_DISPLAY_HOBS is not set
# CONFIG_DISPLAY_UPD_DATA is not set
# CONFIG_BMP_LOGO is not set
CONFIG_PLATFORM_USES_FSP2_0=y
CONFIG_PLATFORM_USES_FSP2_X86_32=y
CONFIG_HAVE_INTEL_FSP_REPO=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_S_CBFS="fsps.bin"
CONFIG_FSP_M_CBFS="fspm.bin"
CONFIG_FSP_FULL_FD=y
# CONFIG_FSP_FULL_FD is not set
CONFIG_FSP_T_RESERVED_SIZE=0x0
CONFIG_FSP_M_XIP=y
CONFIG_HAVE_FSP_LOGO_SUPPORT=y
CONFIG_FSP_COMPRESS_FSP_S_LZ4=y
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
@@ -799,6 +799,13 @@ CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
@@ -0,0 +1,13 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
payload_grub="y"
payload_memtest="y"
grub_scan_disk="nvme ahci"
grubtree="xhci_nvme"
vcfg="3040micro"
build_depend="seabios/default grub/xhci_nvme memtest86plus u-boot/amd64coreboot"
IFD_platform="sklkbl"
payload_uboot="amd64"
@@ -1,11 +0,0 @@
tree="next"
xarch="i386-elf"
payload_seabios="y"
payload_grub="y"
payload_memtest="y"
grub_scan_disk="nvme ahci"
grubtree="xhci"
vcfg="3050micro"
build_depend="seabios/default grub/xhci memtest86plus u-boot/amd64coreboot"
IFD_platform="sklkbl"
payload_uboot_amd64="y"

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