coreboot/default: rev 9e41c7cec7, 18 July 2025

T480/T480s patches were dropped since they're included as part of the upstream code now. This update brings the following upstream changes: * 9e41c7cec7 soc/intel/cmn/block/fast_spi: Lock DMA before exiting coreboot * c1d45ef93b mb/google/trulo/var/kaladin: Update touchpad settings * f13f980e03 mb/google/trulo/var/kaladin: Add fw_config probe for storage * 50c39b3a22 mb/google/trulo/var/kaladin: Fix Type C function * f0d50aa404 commonlib/include/commonlib: Add volatile qualifier * 3828153ea5 soc/intel/xeon_sp/gnr: Use official microcodes * a87cbcd3c9 soc/intel/xeon_sp/ibl: Config ACPI base using PMC device * 480ac15044 util/cbfstool: Prevent overflow when sorting fit table entries * bf4f08f3b6 mb/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff: early VGA output * dd19f6bc5a util/cbmem: Extract devmem and common code to separate files * def945f3ba soc/intel/apollolake: Measure the IBBL, IBB and OBB from the bootblock * fbb0738272 mb/google/brox/var/lotso: Decrease cpu power limits * ce88b12420 mb/google/ocelot: Set correct TPM I2C bus for all ocelot model variants * e050e2fbfc mb/google/ocelot/var/ocelot: Remove irrelevant comment * b66c8ea3d3 mb/google/ocelot/var/ocelot: Remove Bluetooth Audio offload * d5d633f607 mb/google/ocelot/var/ocelot: Update variant.c * 3b069d320c cbfs: Add a function to wait for all CBFS preload operations to complete * a7710ed8fd Documentation: coding_style: Add *long* to long multi-line comment example * 19d7104d85 drivers/intel/touch: Use recommended short multi-line comment style * 451988d015 mb/google/trulo/var/pujjolo: Fix Goodix touchscreen function * 542e52c126 soc/qualcomm/x1p42100: Optimize memory layout for X1P42100 * 2e47bd50f2 mb/google/trulo/var/pujjocento: Add 6W and 15W DPTF parameters * 6e4f4538bb soc/intel/{tgl,adl,mtl,ptl}: Default to Software Connection Manager * 1b8dd662a9 soc/qualcomm/x1p42100: Add PCIE Clock support for x1p42100 * 4d3def7514 soc/mediatek/mt8189: Fix timer reset in BL31 by using time_prepare_v2 * d898653b0e soc/meidatek/mt8196: Extract common timer code for reuse * d1c096a5b9 src/soc/mt8196: Correct systimer register offset * edaa67d0c9 mb/google/skywalker: Add thermal init flow in romstage * 6aec09875b soc/mediatek/mt8189: Add thermal driver * 5cc4b9e6ce soc/amd/common/cpu/noncar: Add bootblock overlap detection * 67cd138df9 soc/intel/apollolake: Add missing header in measured_boot.h * a428481574 mb/google/nissa/var/dirks: Update power limits * 55ae0d8a37 mb/google/nissa/var/baseboard/nissa: Add power limits functions * 82163aedc6 soc/amd/common/block/cpu/noncar: Move BSS and DATA out of PT_LOAD * 6405641647 mb/google/fatcat: Use same mainboard part number for all fatcat variants * c5613469ae device: Make a note that SeaBIOS doesn't support above 4G MMIO * ced4c09359 soc/intel/xeon_sp/gnr: Implement get_mmio_high_base_size * 7100f226ca vc/intel/fsp/fsp2_0/wcl: Add FSP headers for WCL FSP * 5171098814 drivers/qemu/bochs: Allow building for non-x86 architectures * d233b6c903 payloads/external/LinuxBoot/Makefile: Fix build prerequisite * 502d19be89 payloads/external/LinuxBoot/targets/u-root.mk: Add missing prerequisite * cba0f0b8b9 payloads/external/LinuxBoot: Rename build target * 43a54e3b1b util/amdfwtool: Add binary parsing * 85da3954d0 .gitmodules: Ignore changes make by what-jenkins-does * 397c5fe420 Documentation: Add a mainboard entry for the Lenovo T480/T480s * 6768586353 Documentation: Add information about the deguard utility * ad8b738af0 mb/lenovo: Add ThinkPad T480 and ThinkPad T480s * 96e381766e ec/lenovo: Add support for MEC1653 EC * 2181b02765 util/smmstoretool: Properly initialise the authenticated variable header * 3058464263 util/smmstoretool: Add support for creating variable from file contents * b49f567e45 util/smmstoretool: Ensure that the FVB header isn't too large * a6fbaa47ea util/smmstoretool: Clarify the `auth_vars` field * 3698517d82 mb/amd: Use mec152x tool * 5a0953614b util/amdtools: Add ec_usb_pd_fw * e63620012c util: Add Microchip EC FW tool * 0b5ce9d9f0 soc/intel/apollolake: Add support for IFWI Measured Boot * 289cff3423 soc/intel/apollolake: Load the IBB into CAR * 2408695dd3 soc/intel/apollolake: Add a loader for the IBB * 61b66e9a81 soc/intel/apollolake: Add function to clear MCA in Bank 4 * 138402e7ff soc/intel/apollolake: Create IBB, IBBL and OBB * 61b4e1983c mb/google/fatcat: Update PCH reset power cycle duration to 1 second * e9af95d5ab soc/intel/pantherlake: Configure FSP UPDs for minimum assertion widths * 79bd154b49 drivers/genesyslogic/gl9763e: Mask replay timer timeout of AER * a775bfc2b2 soc/mediatek/mt8189: Specify MTKLIB_PATH for building BL31 * e583b2ffb7 soc/meidatek/mt8196: Extract common thermal code for reuse * f62734976c mb/dell: Convert E6400 into a variant * 8d60bf9975 mb/google/fatcat: select MIPI pre-prod if PTL pre-prod SoC is set * 2f978ecab3 mb/google/fatcat: Choose platforms with pre-prod Panther Lake SoC * eb1483ba17 soc/mediatek/mt8189: Increase SCP clock frequency from 26MHz to 416MHz * 9c5557f982 util/abuild: Add --sequential-boards option * 9e5234feee payloads/external/edk2: Drop our toolchain override * 8d9e18a122 payloads/edk2: Indicate whether edk2-platforms is available * 626fd50a94 mb/google/fatcat/var/kinmen: Enable ISH * e7cefe4f41 soc/mediatek/mt8196: Move srclken_rc related code to common * e9731f8925 soc/intel/pantherlake: Add configs for pre-production silicon * 8687b3d108 mb/google/trulo/var/pujjolo: Add ISH firmware config * 722c9314c7 mb/google/dedede/var/awasuki: Add 2 HYNIX modules to RAM id table * 6082bd7711 ec/lenovo/h8: Rework invalid temperature reporting * 621b1061d0 ec/lenovo/h8: Add Kconfig to select use of Thermal Zone 1 * bc116b8797 ec/lenovo/h8: Replace chip regs for BT/WWAN detect with Kconfig options * d9169ef617 ec/lenovo/pmh7: Add CFR objects for existing options * 45d9973a6d ec/lenovo/h8: Add CFR objects for existing options * ce5a1e8a51 mb/google/brox: Create caboc variant * d745d38393 soc/intel/cmn/block/fast_spi: Add DMA support * 8e666c367d soc/qualcomm/x1p42100: Update boot critical firmware memory layout * e35c784847 Doc/gfx/libgfxinit.md: Fix file names in source code references * 0e682859e7 payloads/external/U-Boot: Upgrade from 2024.07 to v2025.07 * 8b52167a9f arch/x86: Add support for cooperative multitasking on x86_64 * 569b7a8861 Docs/releases: Finalize 25.06 release notes * 5db8bf0cfa mb/trulo/var/pujjolo: Enable USB3 WWAN device * e013c9586c mb/trulo/var/pujjolo: Modify mipi camera parameters * 7b8520ab69 mb/trulo/var/pujjolo: Update fingerprint enable pin status * f74027d5ae mb/google/nissa/var/craask: Add elan touchscreen support * 396a883a0c mb/hp/snb_ivb_desktops: Include PS/2 controller ASL code for MS Windows * 18c067d392 mb/google/fatcat/var/kinmen: Add Synaptics touchpad * 2f5b384ba5 soc/mediatek/mt8189: Enable EARLY_MMU_INIT to improve boot time * d5bce8c420 mb/hp: Add HP 260 G1 DM Business PC (Haswell) * 48c6f66fa4 mb/google/ocelot: Update TPM_TIS_ACPI_INTERRUPT value in Kconfig * 0660fe50de mb/google/ocelot: Update GPE configuration * 5b3063802e mb/google/fatcat/var/kinmen: Fix touchscreen IRQ setting * 6c4e502fdd mb/google/nissa/var/pujjocento: Reduce PL4 to 38W with no battery * 6e92554ab6 mb/trulo/var/pujjolo: Modify FW_CONFIG for mipi camera * 4f5f75da34 mb/trulo/var/pujjolo: Correct USB3 Type-A OC pins * a1dfd39e04 mb/google/fatcat/var/kinmen: Add AUDIO_UNKNOWN and probe for ALC721 * 306544b427 mb/google/fatcat/var/francka: Add AUDIO_UNKNOWN and audio probes * edf47d44cd mb/google/fatcat/var/fatcat: Disable Audio for invalid Audio FW_CONFIG * 454079c3bc lib/cbfs: Ensure cache buffer alignment in ramstage * 0ef670a66a mb/google/ocelot/var/ocelot: Configure FPS related changes * 6ab37f0e0e mb/google/ocelot/var/ocelot: Add FW_CONFIG for Finger Print * 3f61df24d5 mb/google/ocelot/var/ocelot: Add FW_CONFIG for Storage * bb95a26cda mb/google/ocelot/var/ocelot: Add FW_CONFIG for WiFi * 410b3c697f mb/google/ocelot/var/ocelot: Add FW_CONIG for ISH * afaf4c3d7b mb/google/brya/variants/pujjolo: Update ISH GPIOs and add ISH firmware name * f6de6f8933 mb/google/fatcat: Drop redundant SNDW GPIO mapping * 584fdd6572 soc/mediatek/mt8196: Remove redundant bootblock.c from Makefile.mk * 24ea6937f2 soc/intel/apollolake: Add the Kconfig options for IFWI Boot Profile * c68645cd88 util/supermicro: Fix mem leak in get_line_as_int error conditions * 05396238da libpayload/drivers: Fix mem-leak in cbmem_console error condition * 1219981177 drivers/emu/qemu: Add a comment about fw_cfg assumptions * d866e72b3a mb/google/fatcat/var/kinmen: Set CRFP to use GPIO for status * 4367daae20 drivers/spi: Add option to generate proper PowerResource _STA * 03c331399c mb/google/nissa/var/craask: Add focaltech touchscreen support * b3d7c40fb5 mb/siemens/mc_rpl: Remove code for board_id * 5de16ed1b8 mb/siemens/mc_rpl: Remove unused embedded controller code * a1067ec6de mb/siemens/mc_rpl: Remove unneeded code to select a VBT name in CBFS * 463cda84d2 mb/siemens/mc_rpl: Remove unused Type-C data definition * dcbe591201 mb/siemens/mc_rpl: Use SPD data from HWInfo instead of from CBFS * 6c059f8af3 IVB mainboards: Drop 1024M option for gfx_uma_size * 3b61dbaa06 mb/asus/p8z77-m_pro: Remove incorrect gfx_uma_size options * 2b7115b139 mb/hp/snb_ivb_desktops: Add gfx_uma_size options up to 512MB * d99769bbde mb/hp/snb_ivb_desktops/variants: enable 4th sata port on tested models * 95784dbafb mb/google/ocelot/var/ocelot: Add FW_CONFIG for Audio * f323adb19f soc/mediatek/mt8189: Increase SPI NOR clock rate from 26MHz to 52MHz * 689af47b52 commonlib: Add pvmfw related timestamps * f1d06a5ad4 soc/intel/common/block/memory: Provide a way to use SPD data from memory * 11b1dc0a97 Reapply "util/cbmem: Consolidate CBMEM and coreboot table access" * 13f1c6118e Documentation: Update cbmem.md with more information * 07267d19ce arch/x86/postcar_loader: Add comment line for reloc_params assignment * e94ac6e655 mb/google/nissa/var/pujjocento: Reduce PL4 to 38 W with no battery * 2eaec1b53a sbom: Fix build with merged bootblock and romstage * 267f08dafd MAINTAINERS: Add KunYi Chen as maintainer for LattePanda Mu Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-07-11 05:52:36 +02:00 · 2025-07-20 04:44:14 +01:00
parent cc2f08e7bb
commit 84a1ff85b0
135 changed files with 273 additions and 2888 deletions
@@ -1,7 +1,7 @@
-From 2a1f4af15aa785776498c17abd5d790e1507bd02 Mon Sep 17 00:00:00 2001
+From 26399f33428040acd69ebe02dd9f7f53d37e62a1 Mon Sep 17 00:00:00 2001
 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
 Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 01/41] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 01/35] add c3 and clockgen to apple/macbook21

 ---
 src/mainboard/apple/macbook21/Kconfig       |  1 +
@@ -1,7 +1,7 @@
-From 089da6f216a8f6c9deec3e6c8d9feb5bf2ff907b Mon Sep 17 00:00:00 2001
+From 190bf09b5260bf94f9654294887cf916aa805fa8 Mon Sep 17 00:00:00 2001
 From: persmule <persmule@gmail.com>
 Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 02/41] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 02/35] lenovo/t400: Enable all SATA ports

 There are 2 SATA ports on the chassis of t400(s), but at least one dock for
 t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -15,7 +15,7 @@ This patch unmasked all SATA ports found within t400s with factory firmware.
 1 file changed, 2 insertions(+), 2 deletions(-)

 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
-index 259c3e1b21..3d007533a4 100644
+index 9e056772e9..9361f330d2 100644
 --- a/src/mainboard/lenovo/t400/devicetree.cb
 +++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
@@ -1,7 +1,7 @@
-From ce328f1fa7e7cd90f31728eb1c1215bcb062acd6 Mon Sep 17 00:00:00 2001
+From c89826daea80f0e0e403808a8158c035a8c0423d Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 03/41] lenovo/x230: set me_state=Disabled in cmos.default
+Subject: [PATCH 03/35] lenovo/x230: set me_state=Disabled in cmos.default

 I only recently found out about this. It's possible to use me_cleaner to
 do the same thing, but some people might just flash coreboot and not do
@@ -1,7 +1,7 @@
-From a7aaa58404cb19e6d89a9c9c5a137f9629d6e140 Mon Sep 17 00:00:00 2001
+From a418125357321304c76c023b243242debf675779 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 04/41] set me_state=Disabled on all cmos.default files!
+Subject: [PATCH 04/35] set me_state=Disabled on all cmos.default files!

 yeah. why the hell isn't this the default

@@ -1,7 +1,7 @@
-From 5a226a91554c70c1c5d56a3184abdea48ea43fbb Mon Sep 17 00:00:00 2001
+From 9e40defe4a539949a8b8dd2d295e49bb1d918d7c Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 05/41] util/ifdtool: add --nuke flag (all 0xFF on region)
+Subject: [PATCH 05/35] util/ifdtool: add --nuke flag (all 0xFF on region)

 When this option is used, the region's contents are overwritten
 with all ones (0xFF).
@@ -1,20 +1,20 @@
-From 0994cde09852b152039f478937875ada3b3933d8 Mon Sep 17 00:00:00 2001
+From 1515f7ea03cd021aba1fcb7aae46693064cda87e Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 06/41] mb/dell/e6400: Enable 01.0 device in devicetree for
+Subject: [PATCH 06/35] mb/dell/e6400: Enable 01.0 device in devicetree for
 dGPU models

 Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
 ---
- src/mainboard/dell/e6400/devicetree.cb | 2 +-
+ src/mainboard/dell/gm45_latitude/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
-index bb954cbd7b..e9f3915d17 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
-+++ b/src/mainboard/dell/e6400/devicetree.cb
-@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
+diff --git a/src/mainboard/dell/gm45_latitude/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
+index 5919803be2..76dae87153 100644
+--- a/src/mainboard/dell/gm45_latitude/devicetree.cb
+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
+@@ -18,7 +18,7 @@ chip northbridge/intel/gm45
 		ops gm45_pci_domain_ops
 
 		device pci 00.0 on end # host bridge
@@ -1,7 +1,7 @@
-From b8f173c3ef36873314d4718cf8a8cbe472c0a62b Mon Sep 17 00:00:00 2001
+From 0a16c780932a176bba062a82df47dfebfa963e39 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 07/41] Remove warning for coreboot images built without a
+Subject: [PATCH 07/35] Remove warning for coreboot images built without a
 payload

 I added this in upstream to prevent people from accidentally flashing
@@ -1,7 +1,7 @@
-From f9ac80501381f464f20b0dfb8b921cfd32267728 Mon Sep 17 00:00:00 2001
+From 894aa0d70567962d2c05e7bbf20fab4093c3f3ef Mon Sep 17 00:00:00 2001
 From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
 Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH 08/41] HACK: Disable coreboot related BL31 features
+Subject: [PATCH 08/35] HACK: Disable coreboot related BL31 features

 I don't know why, but removing this BL31 make argument lets gru-kevin
 power off properly when shut down from Linux. Needs investigation.
@@ -1,7 +1,7 @@
-From 8833d84c55c8fc1c49cf320c1825e89984555900 Mon Sep 17 00:00:00 2001
+From 7b13246f8838344f65cdfc1a5012af757fda45de Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 11:41:41 +0000
-Subject: [PATCH 09/41] dell/e6430: use ME Soft Temporary Disable
+Subject: [PATCH 09/35] dell/e6430: use ME Soft Temporary Disable

 i overlooked this. it's set on other boards.

@@ -1,7 +1,7 @@
-From 40b9ffdb09eb40581ae2ea91a653192a6b7507ba Mon Sep 17 00:00:00 2001
+From c08a6748a8cecb5b6332d7d1ac4e17e6ba7f1095 Mon Sep 17 00:00:00 2001
 From: Riku Viitanen <riku.viitanen@protonmail.com>
 Date: Sat, 23 Dec 2023 19:02:10 +0200
-Subject: [PATCH 10/41] mb/hp: Add Compaq Elite 8300 CMT port
+Subject: [PATCH 10/35] mb/hp: Add Compaq Elite 8300 CMT port

 Based on autoport and Z220 SuperIO code.

@@ -1,7 +1,7 @@
-From 49c11dedc8c12c6868237109c49509729502cc45 Mon Sep 17 00:00:00 2001
+From ce20b7a589ce16190ec161d7e4bd018922fd4362 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 2 Mar 2024 22:51:09 +0000
-Subject: [PATCH 11/41] nb/intel/haswell: make IOMMU a runtime option
+Subject: [PATCH 11/35] nb/intel/haswell: make IOMMU a runtime option

 When I tested graphics cards on a coreboot port for Dell
 OptiPlex 9020 SFF, I could not use a graphics card unless
@@ -1,7 +1,7 @@
-From 49f11a79d59856b9dc2f81c436933ef22077adc6 Mon Sep 17 00:00:00 2001
+From 35ebb618aac374cf50b8bde59cc06c884ff05a98 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 2 Mar 2024 23:00:09 +0000
-Subject: [PATCH 12/41] dell/optiplex_9020: Disable IOMMU by default
+Subject: [PATCH 12/35] dell/optiplex_9020: Disable IOMMU by default

 Needed to make graphics cards work. Turning it on is
 recommended if only using iGPU, otherwise leave it off
@@ -1,7 +1,7 @@
-From bf2779aa7dc40c8b671d231ca041c3532381b723 Mon Sep 17 00:00:00 2001
+From 7e7d44da5e5ee31307e99632e7b4c49b931d2118 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 6 Apr 2024 01:22:47 +0100
-Subject: [PATCH 13/41] nb/haswell: Fully disable iGPU when dGPU is used
+Subject: [PATCH 13/35] nb/haswell: Fully disable iGPU when dGPU is used

 My earlier patch disabled decode *and* disabled the iGPU itself, but
 a subsequent revision disabled only VGA decode. Upon revisiting, I
@@ -1,7 +1,7 @@
-From 44ad334748c8c979a42ece4d3425879d3eb9a2b7 Mon Sep 17 00:00:00 2001
+From d4c7fec4db5d8844260fcd511c77c3c60bc1d881 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 3 May 2024 11:03:32 -0600
-Subject: [PATCH 14/41] ec/dell/mec5035: Add S3 suspend SMI handler
+Subject: [PATCH 14/35] ec/dell/mec5035: Add S3 suspend SMI handler

 This is necessary for S3 resume to work on SNB and newer Dell Latitude
 laptops. If a command isn't sent, the EC cuts power to the DIMMs,
@@ -1,7 +1,7 @@
-From c9b30b3c93acc42b3c4de4f782dd47d519f81a8d Mon Sep 17 00:00:00 2001
+From 426a557f5ed8de5a565564f9d345d449b3255293 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 4 May 2024 02:00:53 +0100
-Subject: [PATCH 15/41] nb/haswell: lock policy regs when disabling IOMMU
+Subject: [PATCH 15/35] nb/haswell: lock policy regs when disabling IOMMU

 Angel Pons told me I should do it. See comments here:
 https://review.coreboot.org/c/coreboot/+/81016
@@ -1,7 +1,7 @@
-From dc5084cfa9526d5ba4a450b4d30f7463d857ba5f Mon Sep 17 00:00:00 2001
+From 403c10efc815b6b58ddf8025916a5840d4f39d16 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH 16/41] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH 16/35] nb/intel/gm45: Make DDR2 raminit work

 List of changes:
 - Update some timing and ODT values
@@ -1,7 +1,7 @@
-From 1afeaab1f511e0fac478560d8da2d378858e2ac9 Mon Sep 17 00:00:00 2001
+From 814f2a4a1daf8bfd923cbfe3e618a153a7ade41e Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Tue, 6 Aug 2024 00:50:24 +0100
-Subject: [PATCH 17/41] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
+Subject: [PATCH 17/35] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards

 We add this patch:

@@ -1,7 +1,7 @@
-From 12d29915dcd43053b7e3a17e778db3627fbbadfb Mon Sep 17 00:00:00 2001
+From bea563e3288d3cae4cab410cf818552abbd3bba4 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Mon, 20 May 2024 10:24:16 -0600
-Subject: [PATCH 18/41] mb/dell/e6400: Use 100 MHz reference clock for display
+Subject: [PATCH 18/35] mb/dell/e6400: Use 100 MHz reference clock for display

 The E6400 uses a 100 MHz reference clock for spread spectrum support on
 LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
@@ -14,24 +14,23 @@ display in the pre-OS graphics environment provided by libgfxinit.

 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
 ---
- src/mainboard/dell/e6400/Kconfig   | 3 +++
- src/northbridge/intel/gm45/Kconfig | 4 ++++
- 2 files changed, 7 insertions(+)
+ src/mainboard/dell/gm45_latitude/Kconfig | 2 ++
+ src/northbridge/intel/gm45/Kconfig       | 4 ++++
+ 2 files changed, 6 insertions(+)

-diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
-index 417d95fd5d..6fe1b1c456 100644
--- a/src/mainboard/dell/e6400/Kconfig
-+++ b/src/mainboard/dell/e6400/Kconfig
-@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS
- 	select INTEL_GMA_HAVE_VBT
- 	select EC_DELL_MEC5035
+diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
+index 98ad18849c..4b026be2ba 100644
+--- a/src/mainboard/dell/gm45_latitude/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
+@@ -21,6 +21,8 @@ config BOARD_DELL_E6400
+ 	select BOARD_DELL_GM45_LATITUDE_COMMON
 
+ if BOARD_DELL_GM45_LATITUDE_COMMON
 +config INTEL_GMA_DPLL_REF_FREQ
 +	default 100000000
-+
- config MAINBOARD_DIR
- 	default "dell/e6400"
 
+ config MAINBOARD_DIR
+ 	default "dell/gm45_latitude"
 diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
 index fef0d735b3..fc5df8b11a 100644
 --- a/src/northbridge/intel/gm45/Kconfig
@@ -1,7 +1,7 @@
-From 25af68c921f62046ea6e939cbe9c7c7936497e96 Mon Sep 17 00:00:00 2001
+From 107e9bda542763b92f6e90031e0e3878d66e40fc Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Mon, 12 Aug 2024 02:15:24 +0100
-Subject: [PATCH 19/41] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
+Subject: [PATCH 19/35] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ

 set it to 96MHz. fixes the following build error when
 building for x4x boards e.g. gigabyte ga-g41m-es2l:
@@ -1,243 +0,0 @@
-From 6421e20fe009e981d6bc28cfd79e79ae2097c80d Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Thu, 26 Sep 2024 19:48:26 -0600
-Subject: [PATCH 20/41] mb/dell: Convert E6400 into a variant
-
-All the GM45 Dell Latitudes should be nearly identical, so convert the
-E6400 port into a variant so that future ports for the other systems can
-share code with each other.
-
-Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/e6400/Makefile.mk          |  10 --------
- .../dell/{e6400 => gm45_latitude}/Kconfig     |  22 +++++++++++++-----
- .../{e6400 => gm45_latitude}/Kconfig.name     |   0
- src/mainboard/dell/gm45_latitude/Makefile.mk  |  11 +++++++++
- .../dell/{e6400 => gm45_latitude}/acpi/ec.asl |   0
- .../acpi/ich9_pci_irqs.asl                    |   0
- .../{e6400 => gm45_latitude}/acpi/superio.asl |   0
- .../dell/{e6400 => gm45_latitude}/blc.c       |   0
- .../{e6400 => gm45_latitude}/board_info.txt   |   0
- .../dell/{e6400 => gm45_latitude}/bootblock.c |   0
- .../{e6400 => gm45_latitude}/cmos.default     |   0
- .../dell/{e6400 => gm45_latitude}/cmos.layout |   0
- .../dell/{e6400 => gm45_latitude}/cstates.c   |   0
- .../{e6400 => gm45_latitude}/devicetree.cb    |   1 -
- .../dell/{e6400 => gm45_latitude}/dsdt.asl    |   0
- .../dell/{e6400 => gm45_latitude}/mainboard.c |   0
- .../dell/{e6400 => gm45_latitude}/romstage.c  |   0
- .../variants}/e6400/data.vbt                  | Bin
- .../variants}/e6400/gma-mainboard.ads         |   0
- .../{ => gm45_latitude/variants}/e6400/gpio.c |   0
- .../variants}/e6400/hda_verb.c                |   0
- .../variants/e6400/overridetree.cb            |   7 ++++++
- 22 files changed, 34 insertions(+), 17 deletions(-)
- delete mode 100644 src/mainboard/dell/e6400/Makefile.mk
- rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig (64%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig.name (100%)
- create mode 100644 src/mainboard/dell/gm45_latitude/Makefile.mk
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ec.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ich9_pci_irqs.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/superio.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/blc.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/board_info.txt (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/bootblock.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.default (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.layout (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cstates.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/devicetree.cb (98%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/dsdt.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/mainboard.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/romstage.c (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/data.vbt (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gma-mainboard.ads (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gpio.c (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/hda_verb.c (100%)
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-
-diff --git a/src/mainboard/dell/e6400/Makefile.mk b/src/mainboard/dell/e6400/Makefile.mk
-deleted file mode 100644
-index ca3a82db48..0000000000
--- a/src/mainboard/dell/e6400/Makefile.mk
-+++ /dev/null
-@@ -1,10 +0,0 @@
-## SPDX-License-Identifier: GPL-2.0-only
-
-bootblock-y += bootblock.c
-
-romstage-y += gpio.c
-
-ramstage-y += cstates.c
-ramstage-y += blc.c
-
-ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
-similarity index 64%
-rename from src/mainboard/dell/e6400/Kconfig
-rename to src/mainboard/dell/gm45_latitude/Kconfig
-index 6fe1b1c456..ba76fb6e8c 100644
--- a/src/mainboard/dell/e6400/Kconfig
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig
-@@ -1,9 +1,7 @@
- ## SPDX-License-Identifier: GPL-2.0-only
- 
-if BOARD_DELL_E6400
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-+config BOARD_DELL_GM45_LATITUDE_COMMON
-+	def_bool n
- 	select SYSTEM_TYPE_LAPTOP
- 	select CPU_INTEL_SOCKET_P
- 	select NORTHBRIDGE_INTEL_GM45
-@@ -19,19 +17,31 @@ config BOARD_SPECIFIC_OPTIONS
- 	select INTEL_GMA_HAVE_VBT
- 	select EC_DELL_MEC5035
- 
-+
-+config BOARD_DELL_E6400
-+	select BOARD_DELL_GM45_LATITUDE_COMMON
-+
-+if BOARD_DELL_GM45_LATITUDE_COMMON
-+
- config INTEL_GMA_DPLL_REF_FREQ
- 	default 100000000
- 
- config MAINBOARD_DIR
-	default "dell/e6400"
-+	default "dell/gm45_latitude"
- 
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E6400" if BOARD_DELL_E6400
- 
-+config OVERRIDE_DEVICETREE
-+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-+
-+config VARIANT_DIR
-+	default "e6400" if BOARD_DELL_E6400
-+
- config USBDEBUG_HCD_INDEX
- 	default 1
- 
- config CBFS_SIZE
- 	default 0x1A0000
- 
-endif # BOARD_DELL_E6400
-+endif # BOARD_DELL_GM45_LATITUDE_COMMON
-diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
-similarity index 100%
-rename from src/mainboard/dell/e6400/Kconfig.name
-rename to src/mainboard/dell/gm45_latitude/Kconfig.name
-diff --git a/src/mainboard/dell/gm45_latitude/Makefile.mk b/src/mainboard/dell/gm45_latitude/Makefile.mk
-new file mode 100644
-index 0000000000..5295d5be22
--- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/Makefile.mk
-@@ -0,0 +1,11 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+bootblock-y += bootblock.c
-+
-+romstage-y += variants/$(VARIANT_DIR)/gpio.c
-+
-+ramstage-y += cstates.c
-+ramstage-y += blc.c
-+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
-+
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/gm45_latitude/acpi/ec.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/ec.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/ec.asl
-diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
-diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/gm45_latitude/acpi/superio.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/superio.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/superio.asl
-diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/gm45_latitude/blc.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/blc.c
-rename to src/mainboard/dell/gm45_latitude/blc.c
-diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/gm45_latitude/board_info.txt
-similarity index 100%
-rename from src/mainboard/dell/e6400/board_info.txt
-rename to src/mainboard/dell/gm45_latitude/board_info.txt
-diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/gm45_latitude/bootblock.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/bootblock.c
-rename to src/mainboard/dell/gm45_latitude/bootblock.c
-diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/gm45_latitude/cmos.default
-similarity index 100%
-rename from src/mainboard/dell/e6400/cmos.default
-rename to src/mainboard/dell/gm45_latitude/cmos.default
-diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/gm45_latitude/cmos.layout
-similarity index 100%
-rename from src/mainboard/dell/e6400/cmos.layout
-rename to src/mainboard/dell/gm45_latitude/cmos.layout
-diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/gm45_latitude/cstates.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/cstates.c
-rename to src/mainboard/dell/gm45_latitude/cstates.c
-diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
-similarity index 98%
-rename from src/mainboard/dell/e6400/devicetree.cb
-rename to src/mainboard/dell/gm45_latitude/devicetree.cb
-index e9f3915d17..76dae87153 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
-+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
-@@ -15,7 +15,6 @@ chip northbridge/intel/gm45
- 	register "pci_mmio_size" = "2048"
- 
- 	device domain 0 on
-		subsystemid 0x1028 0x0233 inherit
- 		ops gm45_pci_domain_ops
- 
- 		device pci 00.0 on end # host bridge
-diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/gm45_latitude/dsdt.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/dsdt.asl
-rename to src/mainboard/dell/gm45_latitude/dsdt.asl
-diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/gm45_latitude/mainboard.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/mainboard.c
-rename to src/mainboard/dell/gm45_latitude/mainboard.c
-diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/gm45_latitude/romstage.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/romstage.c
-rename to src/mainboard/dell/gm45_latitude/romstage.c
-diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
-similarity index 100%
-rename from src/mainboard/dell/e6400/data.vbt
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
-diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
-similarity index 100%
-rename from src/mainboard/dell/e6400/gma-mainboard.ads
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/gpio.c
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
-diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/hda_verb.c
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-new file mode 100644
-index 0000000000..acc34a2252
--- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-@@ -0,0 +1,7 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/gm45
-+	device domain 0 on
-+		subsystemid 0x1028 0x0233 inherit
-+	end
-+end
-- 
-2.39.5
-
@@ -1,7 +1,7 @@
-From 0b5aa25828b0f91a5345c12dfabdc9a0f9b3765b Mon Sep 17 00:00:00 2001
+From aba3cfe3888960b342147f74a65cb436608ae632 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Thu, 26 Sep 2024 19:51:25 -0600
-Subject: [PATCH 21/41] mb/dell/gm45_latitudes: Add E4300 variant
+Subject: [PATCH 20/35] mb/dell/gm45_latitudes: Add E4300 variant

 Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -21,10 +21,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
 create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb

 diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
-index ba76fb6e8c..144f9bcdf0 100644
+index 4b026be2ba..9f0f56e304 100644
 --- a/src/mainboard/dell/gm45_latitude/Kconfig
 +++ b/src/mainboard/dell/gm45_latitude/Kconfig
-@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
+@@ -20,6 +20,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
 config BOARD_DELL_E6400
 	select BOARD_DELL_GM45_LATITUDE_COMMON
 
@@ -32,9 +32,9 @@ index ba76fb6e8c..144f9bcdf0 100644
 +	select BOARD_DELL_GM45_LATITUDE_COMMON
 +
 if BOARD_DELL_GM45_LATITUDE_COMMON
- 
 config INTEL_GMA_DPLL_REF_FREQ
-@@ -31,12 +34,14 @@ config MAINBOARD_DIR
+ 	default 100000000
+@@ -29,12 +32,14 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	default "Latitude E6400" if BOARD_DELL_E6400
@@ -1,7 +1,7 @@
-From 2f07e367c9c5488722619a6a2efd5aa2fb634a05 Mon Sep 17 00:00:00 2001
+From 9b43bbf06f7752045ec76ec5608d14f1d868e7f8 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 3 May 2024 16:31:12 -0600
-Subject: [PATCH 22/41] mb/dell: Add S3 SMI handler for Dell Latitudes
+Subject: [PATCH 21/35] mb/dell: Add S3 SMI handler for Dell Latitudes

 Integrate the previously added mec5035_smi_sleep() function into
 mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
@@ -1,7 +1,7 @@
-From ed8e485c5f719fbd0da34d2e883d002945134796 Mon Sep 17 00:00:00 2001
+From 31b7d8d2e853961ecce0ced86309e9e965a0d008 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Tue, 18 Jun 2024 21:31:08 -0600
-Subject: [PATCH 23/41] ec/dell/mec5035: Route power button event to host
+Subject: [PATCH 22/35] ec/dell/mec5035: Route power button event to host

 If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
 power button results in the EC powering off the system without letting
@@ -1,7 +1,7 @@
-From 5d056590dd6f3899422546a16a59bec6402b96f6 Mon Sep 17 00:00:00 2001
+From 4dfcaaffc1fe01cd7676f804a7f1fd5f899beb36 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Tue, 31 Dec 2024 14:42:24 +0000
-Subject: [PATCH 24/41] Disable compression on refcode insertion
+Subject: [PATCH 23/35] Disable compression on refcode insertion

 Compression is not reliably reproducible. In an lbmk release
 context, this means we cannot rely on vendorfile insertion.
@@ -1,7 +1,7 @@
-From 0b4bce08857e886b15277099cb1a53fe31ddfece Mon Sep 17 00:00:00 2001
+From c314d7a8a858c94d7a95b378951a5f22d62a51f9 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 21 Apr 2025 02:58:47 +0100
-Subject: [PATCH 25/41] nb/intel/*: Disable stack overflow debug options
+Subject: [PATCH 24/35] nb/intel/*: Disable stack overflow debug options

 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -1,7 +1,7 @@
-From 3505474eebdb54c566dfff79286689f1ba4fbb67 Mon Sep 17 00:00:00 2001
+From 1661af1ef80d7dce6aaba575bdcb52cc7c04e0da Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Mon, 30 Sep 2024 20:44:38 -0400
-Subject: [PATCH 29/41] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
+Subject: [PATCH 25/35] mb/dell: Add Optiplex 780 MT (x4x/ICH10)

 Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -1,7 +1,7 @@
-From 77f7b454580edf756c22b38dd78a855fa5b0977f Mon Sep 17 00:00:00 2001
+From ec5c7627e90eb136a41bbe179e744a9d300a79fc Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Wed, 30 Oct 2024 20:55:25 -0600
-Subject: [PATCH 30/41] mb/dell/optiplex_780: Add USFF variant
+Subject: [PATCH 26/35] mb/dell/optiplex_780: Add USFF variant

 Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -1,30 +0,0 @@
-From 6b623421531a04d0d615889b0710dd82a800c0bd Mon Sep 17 00:00:00 2001
-From: Mate Kukri <km@mkukri.xyz>
-Date: Fri, 22 Nov 2024 21:26:48 +0000
-Subject: [PATCH 27/41] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
- bootblock
-
-Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173
-Signed-off-by: Mate Kukri <km@mkukri.xyz>
---
- src/soc/intel/skylake/bootblock/pch.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
-index df00bb85a9..beaece960b 100644
--- a/src/soc/intel/skylake/bootblock/pch.c
-+++ b/src/soc/intel/skylake/bootblock/pch.c
-@@ -100,8 +100,8 @@ static void soc_config_pwrmbase(void)
- 
- void pch_early_iorange_init(void)
- {
-	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
-			LPC_IOE_EC_62_66;
-+	uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F |
-+			LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66;
- 
- 	const config_t *config = config_of_soc();
- 
-- 
-2.39.5
-
@@ -1,7 +1,7 @@
-From 5f34838af23fd4b6dccbab1f60b931fca7762e01 Mon Sep 17 00:00:00 2001
+From e1d09409f6062eb9798b2a63d555ef418a46f47b Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 6 Jan 2025 01:53:53 +0000
-Subject: [PATCH 36/41] src/intel/x4x: Disable stack overflow debug
+Subject: [PATCH 27/35] src/intel/x4x: Disable stack overflow debug

 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -1,7 +1,7 @@
-From 521518c2b9fe32f77937cbd4ff1942f148b1c0f3 Mon Sep 17 00:00:00 2001
+From 1cb3f95c58d501fe33dc2a3d090a84cd7d5d42d3 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Tue, 22 Apr 2025 10:21:59 +0100
-Subject: [PATCH 39/41] hp/8300cmt: remove xhci_overcurrent_mapping
+Subject: [PATCH 28/35] hp/8300cmt: remove xhci_overcurrent_mapping

 No longer needed, as per the following commit:

@@ -1,7 +1,7 @@
-From cf5f29a8cfed97bb7fb5dee2d7539e57b169661e Mon Sep 17 00:00:00 2001
+From 4ac77dd7d5c5759c546266003f7e705aae04860b Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Wed, 11 Dec 2024 01:06:01 +0000
-Subject: [PATCH 31/41] dell/3050micro: disable nvme hotplug
+Subject: [PATCH 29/35] dell/3050micro: disable nvme hotplug

 in my testing, when running my 3050micro for a few days,
 the nvme would sometimes randomly rename.
@@ -1,7 +1,7 @@
-From 0287b792fced5752eef4e14d7bc95a21b318e64d Mon Sep 17 00:00:00 2001
+From c58079787f45fd9d42bfaedfcb540634787c3010 Mon Sep 17 00:00:00 2001
 From: Felix Singer <felixsinger@posteo.net>
 Date: Wed, 26 Jun 2024 04:24:31 +0200
-Subject: [PATCH 26/41] soc/intel/skylake: configure usb acpi
+Subject: [PATCH 30/35] soc/intel/skylake: configure usb acpi

 Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
 Signed-off-by: Felix Singer <felixsinger@posteo.net>
@@ -1,7 +1,7 @@
-From 1f13ade55375d32a65eb5e9cf327f7060353a225 Mon Sep 17 00:00:00 2001
+From f449b429996bab8d6429c7bb83c84061b4b2284e Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 6 Jan 2025 01:36:23 +0000
-Subject: [PATCH 35/41] src/intel/skylake: Disable stack overflow debug options
+Subject: [PATCH 31/35] src/intel/skylake: Disable stack overflow debug options

 The option was appearing in T480/3050micro configs of lbmk,
 after updating on the coreboot/next uprev for 20241206 rev8:
@@ -37,7 +37,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
 1 file changed, 9 insertions(+)

 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index d51ffaef7b..42af82a5d8 100644
+index 9191ed0ff8..493a2d835a 100644
 --- a/src/soc/intel/skylake/Kconfig
 +++ b/src/soc/intel/skylake/Kconfig
@@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE
@@ -1,7 +1,7 @@
-From 2c1616af49bbc353b0946bcedf077d69d79ba293 Mon Sep 17 00:00:00 2001
+From 26716653f9991ca8cce2766024522b8832607006 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Thu, 26 Dec 2024 19:45:20 +0000
-Subject: [PATCH 33/41] soc/intel/skylake: Don't compress FSP-S
+Subject: [PATCH 32/35] soc/intel/skylake: Don't compress FSP-S

 Build systems like lbmk need to reproducibly insert
 certain vendor files on release images.
@@ -19,7 +19,7 @@ Signed-off-by: Leah Rowe <info@minifree.org>
 1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index 9191ed0ff8..d51ffaef7b 100644
+index 493a2d835a..42af82a5d8 100644
 --- a/src/soc/intel/skylake/Kconfig
 +++ b/src/soc/intel/skylake/Kconfig
@@ -12,7 +12,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
@@ -1,7 +1,7 @@
-From 4e269cb66361a5b102f582e41ce8c70a0df3f60f Mon Sep 17 00:00:00 2001
+From ee40e9eee976162a79943618e70714dd4ff1bfb7 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Tue, 31 Dec 2024 01:40:42 +0000
-Subject: [PATCH 34/41] soc/intel/pmc: Hardcoded poweroff after power fail
+Subject: [PATCH 33/35] soc/intel/pmc: Hardcoded poweroff after power fail

 Coreboot can set the power state for power on after previous
 power failure, based on the option table. On the ThinkPad T480,
@@ -1,7 +1,7 @@
-From 17791a403c7887c9b48eab578e3bf977d9ba84a3 Mon Sep 17 00:00:00 2001
+From c0d4d83f662499d501fd0ca606bae9cf2d4de56d Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Wed, 18 Dec 2024 02:06:18 +0000
-Subject: [PATCH 32/41] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
+Subject: [PATCH 34/35] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN

 This is used by lbmk to know where a tb.bin file goes,
 when extracting and padding TBT.bin from Lenovo ThunderBolt
@@ -1,7 +1,7 @@
-From 3b6c8e02eba287727b3abc96ffe5612f28c27df3 Mon Sep 17 00:00:00 2001
+From 2dcd66e38b38b01d765dd8a84d1a866af61306e8 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 21 Apr 2025 05:14:45 +0100
-Subject: [PATCH 37/41] Conditional TBFW setting for T480/T480S
+Subject: [PATCH 35/35] Conditional TBFW setting for T480/T480S

 Otherwise, other boards will define it, which
 might trigger the vendor download script, and
@@ -1,153 +0,0 @@
-From 99086eb3298b01aa9b3c68d78c399261866321d5 Mon Sep 17 00:00:00 2001
-From: gaspar-ilom <gasparilom@riseup.net>
-Date: Thu, 6 Mar 2025 23:00:00 +0000
-Subject: [PATCH 38/41] do not break building other thinkpads with the hacks
- for the t480/s made Mate Kukri
-
-still not fixing things properly but at least it should now be possible to build older thinkpads without regressions.
-prior, some code was just commented or unreachable. now we make this explicit with preprocessor directives.
-heads should build all boards on this coreboot version from the same coreboot tree.
-
-Signed-off-by: gaspar-ilom <gasparilom@riseup.net>
---
- src/device/pci_rom.c         |  9 ++++++---
- src/ec/lenovo/h8/acpi/ec.asl |  4 +++-
- src/ec/lenovo/h8/bluetooth.c | 14 ++++++++++----
- src/ec/lenovo/h8/wwan.c      | 14 ++++++++++----
- 4 files changed, 29 insertions(+), 12 deletions(-)
-
-diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
-index bba98d9dea..db3dbbe2ce 100644
--- a/src/device/pci_rom.c
-+++ b/src/device/pci_rom.c
-@@ -396,16 +396,19 @@ void pci_rom_ssdt(const struct device *device)
- 		rom = cbrom;
- 	}
- 
-#if 0
-+
-+	#if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+	const char *scope = "\\_SB.PCI0.RP01.PEGP";
-+	#else
- 	const char *scope = acpi_device_path(device);
-+	#endif
- 	if (!scope) {
- 		printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device));
- 		return;
- 	}
-#endif
- 
- 	/* write _ROM method */
-	acpigen_write_scope("\\_SB.PCI0.RP01.PEGP");
-+	acpigen_write_scope(scope);
- 	acpigen_write_rom((void *)rom, rom->size * 512);
- 	acpigen_pop_len(); /* pop scope */
- }
-diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
-index 8f4a8e1986..f80c15106c 100644
--- a/src/ec/lenovo/h8/acpi/ec.asl
-+++ b/src/ec/lenovo/h8/acpi/ec.asl
-@@ -331,7 +331,9 @@ Device(EC)
- #include "sleepbutton.asl"
- #include "lid.asl"
- #include "beep.asl"
-//#include "thermal.asl"
-+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+#include "thermal.asl"
-+#endif
- #include "systemstatus.asl"
- #include "thinkpad.asl"
- }
-diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c
-index be71a24ced..e60b6c088c 100644
--- a/src/ec/lenovo/h8/bluetooth.c
-+++ b/src/ec/lenovo/h8/bluetooth.c
-@@ -1,6 +1,8 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
- 
-// #include <southbridge/intel/common/gpio.h>
-+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+#include <southbridge/intel/common/gpio.h>
-+#endif
- #include <console/console.h>
- #include <device/device.h>
- #include <ec/acpi/ec.h>
-@@ -26,23 +28,27 @@ void h8_bluetooth_enable(int on)
-  */
- bool h8_has_bdc(const struct device *dev)
- {
-+	#if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+	printk(BIOS_INFO, "H8: BDC detection not implemented. "
-+			  "Assuming BDC installed\n");
-+	return true;
-+	#else
- 	struct ec_lenovo_h8_config *conf = dev->chip_info;
- 
-	if (1 || !conf->has_bdc_detection) {
-+	if (!conf->has_bdc_detection) {
- 		printk(BIOS_INFO, "H8: BDC detection not implemented. "
- 				  "Assuming BDC installed\n");
- 		return true;
- 	}
- 
-#if 0
- 	if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
- 		printk(BIOS_INFO, "H8: BDC installed\n");
- 		return true;
- 	}
-#endif
- 
- 	printk(BIOS_INFO, "H8: BDC not installed\n");
- 	return false;
-+	#endif
- }
- 
- /*
-diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c
-index 5cdcf77406..b4f5787e01 100644
--- a/src/ec/lenovo/h8/wwan.c
-+++ b/src/ec/lenovo/h8/wwan.c
-@@ -1,6 +1,8 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
- 
-// #include <southbridge/intel/common/gpio.h>
-+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+#include <southbridge/intel/common/gpio.h>
-+#endif
- #include <console/console.h>
- #include <device/device.h>
- #include <ec/acpi/ec.h>
-@@ -24,23 +26,27 @@ void h8_wwan_enable(int on)
-  */
- bool h8_has_wwan(const struct device *dev)
- {
-+	#if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+	printk(BIOS_INFO, "H8: WWAN detection not implemented. "
-+			  "Assuming WWAN installed\n");
-+	return true;
-+	#else
- 	struct ec_lenovo_h8_config *conf = dev->chip_info;
- 
-	if (1 || !conf->has_wwan_detection) {
-+	if (!conf->has_wwan_detection) {
- 		printk(BIOS_INFO, "H8: WWAN detection not implemented. "
- 				  "Assuming WWAN installed\n");
- 		return true;
- 	}
- 
-#if 0
- 	if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
- 		printk(BIOS_INFO, "H8: WWAN installed\n");
- 		return true;
- 	}
-#endif
- 
- 	printk(BIOS_INFO, "H8: WWAN not installed\n");
- 	return false;
-+	#endif
- }
- 
- /*
-- 
-2.39.5
-
@@ -1,113 +0,0 @@
-From eb71b55d2dd7af6f6ddca5e462fc228bdb04af50 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Tue, 8 Jul 2025 17:54:57 +0100
-Subject: [PATCH 1/1] lenovo/t480: Drop redundant PcieRpEnable
-
-This is in line with another change from upstream, in
-the recent revision update:
-
-commit ee30558c49c9c4622277785ee0cd54c32720e489
-Author: Nico Huber <nico.h@gmx.de>
-Date:   Fri Jan 12 16:22:19 2024 +0100
-
-    soc/intel/skylake: Drop redundant PcieRpEnable
-
-This change is necessary, to prevent a build error.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- .../lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb     | 5 -----
- .../lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb    | 5 -----
- 2 files changed, 10 deletions(-)
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
-index bf66bd3a69..316dbcbe8a 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
-@@ -43,7 +43,6 @@ chip soc/intel/skylake
- 
- 		# dGPU - x4
- 		device ref pcie_rp1 on
-			register "PcieRpEnable[0]"			= "1"
- 			register "PcieRpClkReqSupport[0]"		= "1"
- 			register "PcieRpClkReqNumber[0]"		= "0"
- 			register "PcieRpClkSrcNumber[0]"		= "0"
-@@ -61,7 +60,6 @@ chip soc/intel/skylake
- 
- 		# M.2 WLAN - x1
- 		device ref pcie_rp7 on
-			register "PcieRpEnable[6]"			= "1"
- 			register "PcieRpClkReqSupport[6]"		= "1"
- 			register "PcieRpClkReqNumber[6]"		= "2"
- 			register "PcieRpClkSrcNumber[6]"		= "2"
-@@ -71,7 +69,6 @@ chip soc/intel/skylake
- 
- 		# M.2 WWAN - x2
- 		device ref pcie_rp5 on
-			register "PcieRpEnable[4]"			= "1"
- 			register "PcieRpClkReqSupport[4]"		= "1"
- 			register "PcieRpClkReqNumber[4]"		= "3"
- 			register "PcieRpClkSrcNumber[4]"		= "3"
-@@ -81,7 +78,6 @@ chip soc/intel/skylake
- 
- 		# TB3 (Alpine Ridge LP) - x2
- 		device ref pcie_rp9 on
-			register "PcieRpEnable[8]"			= "1"
- 			register "PcieRpClkReqSupport[8]"		= "1"
- 			register "PcieRpClkReqNumber[8]"		= "4"
- 			register "PcieRpClkSrcNumber[8]"		= "4"
-@@ -92,7 +88,6 @@ chip soc/intel/skylake
- 
- 		# M.2 2280 caddy - x2
- 		device ref pcie_rp11 on
-			register "PcieRpEnable[10]"			= "1"
- 			register "PcieRpClkReqSupport[10]"		= "1"
- 			register "PcieRpClkReqNumber[10]"		= "5"
- 			register "PcieRpClkSrcNumber[10]"		= "5"
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
-index d4afca20c4..dcaf15fabf 100644
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
-@@ -43,7 +43,6 @@ chip soc/intel/skylake
- 
- 		# dGPU - x2
- 		device ref pcie_rp1 on
-			register "PcieRpEnable[0]"			= "1"
- 			register "PcieRpClkReqSupport[0]"		= "1"
- 			register "PcieRpClkReqNumber[0]"		= "0"
- 			register "PcieRpClkSrcNumber[0]"		= "0"
-@@ -53,7 +52,6 @@ chip soc/intel/skylake
- 
- 		# M.2 WWAN - x1
- 		device ref pcie_rp4 on
-			register "PcieRpEnable[3]"			= "1"
- 			register "PcieRpClkReqSupport[3]"		= "1"
- 			register "PcieRpClkReqNumber[3]"		= "1"
- 			register "PcieRpClkSrcNumber[3]"		= "1"
-@@ -71,7 +69,6 @@ chip soc/intel/skylake
- 
- 		# M.2 WLAN - x1
- 		device ref pcie_rp7 on
-			register "PcieRpEnable[6]"			= "1"
- 			register "PcieRpClkReqSupport[6]"		= "1"
- 			register "PcieRpClkReqNumber[6]"		= "3"
- 			register "PcieRpClkSrcNumber[6]"		= "3"
-@@ -81,7 +78,6 @@ chip soc/intel/skylake
- 
- 		# TB3 (Alpine Ridge LP) - x2
- 		device ref pcie_rp5 on
-			register "PcieRpEnable[4]"			= "1"
- 			register "PcieRpClkReqSupport[4]"		= "1"
- 			register "PcieRpClkReqNumber[4]"		= "4"
- 			register "PcieRpClkSrcNumber[4]"		= "4"
-@@ -92,7 +88,6 @@ chip soc/intel/skylake
- 
- 		# M.2 2280 SSD - x2
- 		device ref pcie_rp9 on
-			register "PcieRpEnable[8]"			= "1"
- 			register "PcieRpClkReqSupport[8]"		= "1"
- 			register "PcieRpClkReqNumber[8]"		= "5"
- 			register "PcieRpClkSrcNumber[8]"		= "5"
-- 
-2.39.5
-
@@ -1,4 +1,4 @@
 # SPDX-License-Identifier: GPL-3.0-or-later

 tree="default"
-rev="812d0e2f626dfea7e7deb960a8dc08ff0e026bc1"
+rev="9e41c7cec791d84b079251065add7dba66662913"
@@ -176,6 +176,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_BROX_RTK_EC is not set
 # CONFIG_BOARD_GOOGLE_BROX_EC_ISH is not set
 # CONFIG_BOARD_GOOGLE_BROX_TI_PDC is not set
+# CONFIG_BOARD_GOOGLE_CABOC is not set
 # CONFIG_BOARD_GOOGLE_GREENBAYUPOC is not set
 # CONFIG_BOARD_GOOGLE_JUBILANT is not set
 # CONFIG_BOARD_GOOGLE_LOTSO is not set
@@ -176,6 +176,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_BOARD_GOOGLE_BROX_RTK_EC is not set
 # CONFIG_BOARD_GOOGLE_BROX_EC_ISH is not set
 # CONFIG_BOARD_GOOGLE_BROX_TI_PDC is not set
+# CONFIG_BOARD_GOOGLE_CABOC is not set
 # CONFIG_BOARD_GOOGLE_GREENBAYUPOC is not set
 # CONFIG_BOARD_GOOGLE_JUBILANT is not set
 # CONFIG_BOARD_GOOGLE_LOTSO is not set
@@ -173,6 +173,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -169,6 +169,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -170,6 +170,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -168,6 +168,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -173,6 +173,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -173,6 +173,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -169,6 +169,7 @@ CONFIG_PCIEXP_AER=y
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 CONFIG_BOARD_HP_ELITEBOOK_820_G2=y
@@ -167,6 +167,7 @@ CONFIG_PCIEXP_AER=y
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 CONFIG_BOARD_HP_ELITEBOOK_820_G2=y
@@ -172,6 +172,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT=y
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -170,6 +170,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT=y
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -172,6 +172,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -170,6 +170,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -173,6 +173,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -172,6 +172,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -170,6 +170,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -169,6 +169,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -171,6 +171,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -169,6 +169,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -168,6 +168,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -166,6 +166,7 @@ CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_BOARD_HP_260_G1_DM is not set
 # CONFIG_BOARD_HP_280_G2 is not set
 # CONFIG_BOARD_HP_COMPAQ_ELITE_8300_CMT is not set
 # CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
@@ -288,6 +288,9 @@ CONFIG_HAVE_UART_SPECIAL=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_DRIVERS_UART_PL011=y
 # CONFIG_VPD is not set
+CONFIG_DRIVERS_EMULATION_QEMU_BOCHS=y
+CONFIG_DRIVERS_EMULATION_QEMU_XRES=800
+CONFIG_DRIVERS_EMULATION_QEMU_YRES=600
 # CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
@@ -296,6 +299,7 @@ CONFIG_DRIVERS_UART_PL011=y
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
+CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
 CONFIG_DRIVERS_WIFI_GENERIC=y
 CONFIG_DRIVERS_MTK_WIFI=y
@@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -378,6 +378,7 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -376,6 +376,7 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -395,6 +395,7 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -393,6 +393,7 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -395,6 +395,7 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -393,6 +393,7 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -395,6 +395,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -393,6 +393,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -216,11 +216,15 @@ CONFIG_BOARD_LENOVO_T480=y
 # CONFIG_BOARD_LENOVO_X230S is not set
 # CONFIG_BOARD_LENOVO_X230_EDP is not set
 # CONFIG_BOARD_LENOVO_X60 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_THINKPADEC_HKEY_EISAID="IBM0068"
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN0094"
+CONFIG_THINKPADEC_HKEY_EISAID="LEN0268"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
 CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y
+CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
+CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
+CONFIG_MEC1653_DEBUG_UNLOCK_KEY="7a41b149fe2101cf"
+CONFIG_VARIANT_HAS_DGPU=y
 CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480/tb.bin"
 CONFIG_TTYS0_BAUD=115200
 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
@@ -497,11 +501,14 @@ CONFIG_EC_ACPI=y
 CONFIG_EC_LENOVO_H8=y
 CONFIG_H8_BEEP_ON_DEATH=y
 CONFIG_H8_FLASH_LEDS_ON_DEATH=y
-# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
+CONFIG_H8_SUPPORT_BT_ON_WIFI=y
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
 CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
 CONFIG_H8_HAS_LEDLOGO=y
+CONFIG_EC_LENOVO_MEC1653=y
+CONFIG_MEC1653_HAS_DEBUG_UNLOCK=y
+CONFIG_MEC1653_ENABLE_UART=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -645,7 +652,6 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
 CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
 # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
 # CONFIG_BUILDING_WITH_DEBUG_FSP is not set
-CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
 # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
@@ -214,11 +214,15 @@ CONFIG_BOARD_LENOVO_T480=y
 # CONFIG_BOARD_LENOVO_X230S is not set
 # CONFIG_BOARD_LENOVO_X230_EDP is not set
 # CONFIG_BOARD_LENOVO_X60 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_THINKPADEC_HKEY_EISAID="IBM0068"
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN0094"
+CONFIG_THINKPADEC_HKEY_EISAID="LEN0268"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
 CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y
+CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
+CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
+CONFIG_MEC1653_DEBUG_UNLOCK_KEY="7a41b149fe2101cf"
+CONFIG_VARIANT_HAS_DGPU=y
 CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480/tb.bin"
 CONFIG_TTYS0_BAUD=115200
 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
@@ -495,11 +499,14 @@ CONFIG_EC_ACPI=y
 CONFIG_EC_LENOVO_H8=y
 CONFIG_H8_BEEP_ON_DEATH=y
 CONFIG_H8_FLASH_LEDS_ON_DEATH=y
-# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
+CONFIG_H8_SUPPORT_BT_ON_WIFI=y
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
 CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
 CONFIG_H8_HAS_LEDLOGO=y
+CONFIG_EC_LENOVO_MEC1653=y
+CONFIG_MEC1653_HAS_DEBUG_UNLOCK=y
+CONFIG_MEC1653_ENABLE_UART=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -637,7 +644,6 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
 CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
 # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
 # CONFIG_BUILDING_WITH_DEBUG_FSP is not set
-CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
 # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
@@ -216,11 +216,14 @@ CONFIG_BOARD_LENOVO_T480S=y
 # CONFIG_BOARD_LENOVO_X230S is not set
 # CONFIG_BOARD_LENOVO_X230_EDP is not set
 # CONFIG_BOARD_LENOVO_X60 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_THINKPADEC_HKEY_EISAID="IBM0068"
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN0094"
+CONFIG_THINKPADEC_HKEY_EISAID="LEN0268"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
 CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y
+CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
+CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
+CONFIG_VARIANT_HAS_DGPU=y
 CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480s/tb.bin"
 CONFIG_TTYS0_BAUD=115200
 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
@@ -497,11 +500,12 @@ CONFIG_EC_ACPI=y
 CONFIG_EC_LENOVO_H8=y
 CONFIG_H8_BEEP_ON_DEATH=y
 CONFIG_H8_FLASH_LEDS_ON_DEATH=y
-# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
+CONFIG_H8_SUPPORT_BT_ON_WIFI=y
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
 CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
 CONFIG_H8_HAS_LEDLOGO=y
+CONFIG_EC_LENOVO_MEC1653=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -645,7 +649,6 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
 CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
 # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
 # CONFIG_BUILDING_WITH_DEBUG_FSP is not set
-CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
 # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
@@ -214,11 +214,14 @@ CONFIG_BOARD_LENOVO_T480S=y
 # CONFIG_BOARD_LENOVO_X230S is not set
 # CONFIG_BOARD_LENOVO_X230_EDP is not set
 # CONFIG_BOARD_LENOVO_X60 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_THINKPADEC_HKEY_EISAID="IBM0068"
+CONFIG_PS2K_EISAID="LEN0071"
+CONFIG_PS2M_EISAID="LEN0094"
+CONFIG_THINKPADEC_HKEY_EISAID="LEN0268"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
 CONFIG_BOARD_LENOVO_SKLKBL_THINKPAD_COMMON=y
+CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y
+CONFIG_EDK2_FOLLOW_BGRT_SPEC=y
+CONFIG_VARIANT_HAS_DGPU=y
 CONFIG_LENOVO_TBFW_BIN="../../../vendorfiles/t480s/tb.bin"
 CONFIG_TTYS0_BAUD=115200
 # CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
@@ -495,11 +498,12 @@ CONFIG_EC_ACPI=y
 CONFIG_EC_LENOVO_H8=y
 CONFIG_H8_BEEP_ON_DEATH=y
 CONFIG_H8_FLASH_LEDS_ON_DEATH=y
-# CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
+CONFIG_H8_SUPPORT_BT_ON_WIFI=y
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
 CONFIG_H8_HAS_PRIMARY_FN_KEYS=y
 CONFIG_H8_HAS_LEDLOGO=y
+CONFIG_EC_LENOVO_MEC1653=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -637,7 +641,6 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
 CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
 # CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
 # CONFIG_BUILDING_WITH_DEBUG_FSP is not set
-CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
 # CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
@@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -379,6 +379,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -377,6 +377,8 @@ CONFIG_EC_LENOVO_H8=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_2ND_THERMAL_ZONE=y
 CONFIG_EC_LENOVO_PMH7=y

 #
@@ -396,6 +396,8 @@ CONFIG_H8_FLASH_LEDS_ON_DEATH=y
 # CONFIG_H8_SUPPORT_BT_ON_WIFI is not set
 # CONFIG_H8_FN_CTRL_SWAP is not set
 CONFIG_H8_HAS_BAT_THRESHOLDS_IMPL=y
+CONFIG_H8_HAS_BDC_GPIO_DETECTION=y
+CONFIG_H8_HAS_WWAN_GPIO_DETECTION=y
 CONFIG_EC_LENOVO_PMH7=y

 #
--- a/Show More
+++ b/Show More