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1643 Commits

Author SHA1 Message Date
Leah Rowe a0857f449a Libreboot 26.01rev1 Magnanimous Max
This is a hotfix release for Libreboot 26.01, which
contains the following patches:

* 379ccc2177 Re-add x230_12mb corebootfb config
* a9428b65c8 get.sh: properly initialise _ua
* 7aadc1dda3 g43t_am3: make it 2mb, not 4mb
* 8c8c3d7cb1 supermicro x11ssh_f: Remove release="n"
* 7e3c01d8d7 supermicro x11ssh_f: Disable ME HECI in devicetree
* 4f287c85c0 supermicro x11ssh_f: Use deguard-configured ME image instead of SPS
* 47401fc170 Delete unused config/ifd/supermicro-x11-lga1151-series directory
* 0415148e92 supermicro x11ssh_f: set release="n"
* ce5eb284a3 supermicro x11ssh_f: use underscores in dir names
* 1426c9cbd0 Added Danish Keymap dkqwerty.gkb
* 62859905ef Add Supermicro X11SSH-F/LN4F port
* 8d8a1f36a9 GRUB: don't download po files in bootstrap

These fixes are backports from the master branch.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-26 01:39:20 +00:00
Leah Rowe 379ccc2177 Re-add x230_12mb corebootfb config
also for other variants

i removed it because it was reported broken. it's not.

the removal was always temporary, pending further testing.
next time, i will be more sceptical.

everything works fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-26 01:30:50 +00:00
Leah Rowe a9428b65c8 get.sh: properly initialise _ua
it is currently only initialised inside case
conditions. this is fine on most shells, but
some of them can be a bit buggy here.

initialise it empty and then override.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-26 01:26:05 +00:00
Leah Rowe 7aadc1dda3 g43t_am3: make it 2mb, not 4mb
idk why i made it 4

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-26 01:25:56 +00:00
Ron Nazarov 8c8c3d7cb1 supermicro x11ssh_f: Remove release="n"
Since we have redundant downloads for the ME image now, it's no longer
required.
2026-02-26 01:25:38 +00:00
Ron Nazarov 7e3c01d8d7 supermicro x11ssh_f: Disable ME HECI in devicetree
Since we always use me_cleaner, this speeds up boot time by preventing
coreboot from wasting a few seconds waiting for HECI.
2026-02-26 01:25:33 +00:00
Ron Nazarov 4f287c85c0 supermicro x11ssh_f: Use deguard-configured ME image instead of SPS
Using the same ME image as the 3050 Micro.  This fixes the lack of a
backup download URL for the ME and speeds up boot time, since MRC
caching is working with ME (unlike SPS).

Unfortunately, since the MFS partition must be preserved, this does
mean we need a larger ME region than with me_cleaned SPS.
2026-02-26 01:25:22 +00:00
Ron Nazarov 47401fc170 Delete unused config/ifd/supermicro-x11-lga1151-series directory
Left over from the hyphen -> underscore renaming commit.
2026-02-26 01:25:13 +00:00
Leah Rowe 0415148e92 supermicro x11ssh_f: set release="n"
the lack of redundancy in Intel ME downloading is a current
release blocker with this board, so set it to release=n for
now.

it is quite possible to use deguard on this board, which does
have redundant downloading when used with lbmk.

although the board doesn't have bootguard, it is still possible
to use deguard. you can configure the generic ME image that it
fetches, and reconfigure it for each machine.

i've asked ron to look into this, on their test board.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-26 01:24:53 +00:00
Leah Rowe ce5eb284a3 supermicro x11ssh_f: use underscores in dir names
i don't like hyphens in file names, because of how lbmk
has historically handled directories and files in the past;
i've removed a lot of eval statements, to the extent that
it's no longer likely to be a problem (it's barely used now),
but i previously had a problem with using hyphens in config
names.

this design flaw (in lbmk) was fixed ages ago, but i still
maintain this policy. since that time, i use hyphens only.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-26 01:24:47 +00:00
Niel Nielsen 1426c9cbd0 Added Danish Keymap dkqwerty.gkb 2026-02-26 01:24:36 +00:00
Ron Nazarov 62859905ef Add Supermicro X11SSH-F/LN4F port
Surprisingly, SeaBIOS VGA output works (coreboot documentation says it
doesn't).

I'm using a static CMOS option table currently (like most other boards
supported in libreboot), but maybe it would be better to switch to the
CBFS file option table.  The default option table enables
hyperthreading, overriding the compile-time setting.

I'm also using a ME/SPS image extracted from the official BIOS update
for this board.  Unfortunately, https://www.supermicro.com/Bios/* is
excluded from crawlers in robots.txt so it's not in archive.org, so I
haven't been able to find a backup download URL.  I also needed to set
the user-agent for fetching the update to "curl/8.6.0" because the
default user-agent override used by lbmk resulted in a 403 error.
deguard is not required (there's no bootguard on this board).

SPS does not implement CPU replacement detection which means that the
MRC cache does not work and RAM training needs to happen on every
boot.  To avoid this it may be possible to run ME instead of SPS on
this board, but I tried both the ME image used on the OptiPlex 3050
Micro in libreboot and one from the ASRock C236 WSI and they both hung
at "[INFO ] POST: 0x92" (POSTCODE_FSP_MEMORY_INIT).

The memtest86+ build included with libreboot doesn't work with USB
keyboards and this board doesn't have a PS/2 port, which is annoying.
2026-02-26 01:24:26 +00:00
Leah Rowe 8d8a1f36a9 GRUB: don't download po files in bootstrap
The files it downloads are not versioned, and they could
change any time. GRUB has no way to deterministically grab
these.

I've removed GRUB's local for grabbing these, instead
mirroring them myself and checking hashes; no hashes seem
to have been provided by the upstream at Translation Project,
so I just used the hashes I had on the files it had, when
I downloaded them.

From now on, I can just re-download these and re-calculate
the hashes as desired, over time, when updating GRUB revisions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-02-26 01:01:57 +00:00
Leah Rowe 1cf3181537 Libreboot 26.01 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-30 07:14:30 +00:00
Leah Rowe e42eef2d2a Merge pull request 'Update config/dependencies/void' (#400) from lucius1664/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/400
2026-01-30 08:11:39 +01:00
lucius1664 466b01b17e Update config/dependencies/void 2026-01-27 13:14:22 +01:00
Leah Rowe bc5e0bbbbb fix config/submodule/
I accidentally removed a bunch of links in a previous change,
that isn't pushed yet.

due to gitignore rules, files in config/submodule/ have to be
added manually using -f with the git add command. as a result,
i need to be very careful when making changes, especially
temporary changes.

lbmk wasn't downloading files properly, because upstreams weren't
defined. this patch fixes that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-26 06:27:58 +00:00
Leah Rowe a808333c04 Libreboot 26.01 RC4 Magnanimous Max
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-21 01:20:43 +00:00
Leah Rowe baeec45f50 use newer ME on e7240
i accidentally picked an older version from Dell update
A16. this update uses A29.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-21 01:18:06 +00:00
Leah Rowe fc2a521446 Libreboot 26.01 RC3 Magnanimous Max
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-21 00:01:38 +00:00
Leah Rowe e91377b509 cb/default: new rev fcd716d9a2, 14 January 2026
This brings the following changes from upstream:

* fcd716d9a2 mb/google/ocelot: Limit Power Limit when battery is missing
* d246e2ca7e tests/Makefile.common: Fix inverted USE_SYSTEM_CMOCKA condition
* e64507638e tests/lib/ux_locales-test: Avoid double quotes in CMUnitTest.name
* 4427a34b6b drivers/intel/fsp2_0: Fix string length handling in timestamp printing
* 40dbe0807d Documentation/mb: Add missing entry for starfighter_mtl
* f070e0add8 mb/starlabs/byte_adl: Fix WOL
* fc20f238f6 mb/starlabs/*: Select DRIVERS_EFI_FW_INFO
* 225e635ea1 soc/amd/common/block/spi: Operate on multiple SPI flashes
* b9bd924847 soc/amd/common/block/spi: Implement boot_device_spi_cs()
* d7d4b67c6a commonlib/mipi/cmd: Remove unnecessary 'const void *' cast
* 5af56ddf92 mb/google/skywalker: Implement lb_board() to pass LB_TAG_PANEL_POWEROFF
* d110cf4669 commonlib/mipi/cmd: Add mipi_panel_get_commands_len()
* 0ee48a475c drivers/mipi: Add power-off commands for TM_TL121BVMS07_00C
* a974b7668e soc/intel/*: Disable InternalGfx w/o iGPU to prevent FSP-M/S crash
* 18ffcafa61 mb/google/bluey/quartz: Adjust PS8820 init sequence
* 532543027a mb/siemens/{mc_ehl6,mc_ehl7}: Configure GPIO GPP_G5 (SD CD) pull-up
* d420e1fb87 mb/siemens/mc_ehl8: Switch from LPSS UART to legacy 8250 I/O UART
* 483c3e51ae mb/siemens/mc_ehl8: Configure I2C and SMB devices
* d810257008 mb/siemens/mc_ehl8: Configure PCIe root ports
* cf2c2555f4 mb/siemens/mc_ehl8: Add new board variant based on mc_ehl1
* a12663fd88 drivers/spi: Allow SoC to provide the SPI flash CS index
* cacc11de4f include/cpu/x86/msr.h: Update return types from int -> bool
* d5fb4becd5 mb/google/nissa/var/yavilla: Update DTT parameters
* 3b18467e8a payloads/ipxe: Unconditionally restore config files post-build
* 4374bbd37b payloads/ipxe: Update and use the stable version
* c0998983d0 ec/google/chromeec: Fix uninitialized buffer in cbi_get_uint32()
* 03b47f947f soc/mediatek: Add mtk_get_mipi_panel_data() API
* 8cfc71d9e0 libpayload: Pass panel power-off commands to payloads
* d94d4b8a25 mb/starlabs/starlite_adl: Add trace length for the card reader
* 0f450a8d9c mb/starlabs/starlite: Set card_reader fallback value to 0
* 94672e2b45 sb/intel/ibexpeak: Remove 6/7 series chipset PCI IDs
* 2fc8051679 util/autoport: Factor out getting sorted Kconfig option names
* 01d82febb2 util/autoport: Separate handling of Kconfig selects
* b7763a5973 mb/google/fatcat: Implement Google Rex touchscreen integration
* 3f5807ce10 mb/siemens/mc_ehl7: Deactivate SATA interface
* 5f76f78383 mb/siemens/mc_ehl7: Deactivate GbE and PSE GbE 0
* b5ad97a268 mb/google/nissa/var/gothrax: Add wifi sar table
* 7351e663d2 mb/google/nissa: Enable early EC SW sync & eSOL for gothrax/epic
* f9b917d391 soc/qualcomm/x1p42100: Relocate CBMEM top below XBL log
* a306987ae4 util/superiotool: Add experimental Nuvoton NPCD378 support
* 139f6c3e64 mb/google/brya/var/redrix: Configure cameras for Windows/Linux ACPI mode
* 3883118ed9 mb/google/brya/var/kano: Configure cameras for Windows/Linux ACPI mode
* ae7b75fb0d mb/lenovo/sklkbl_thinkpad/cfr.c: Fix X280 build error
* 7639118729 drivers/amd/opensil: Add hooks to populate CBMEM_ID_MEMINFO
* 23f0b0b313 util/xcompile/xcompile: Fix clang target parameter
* f712c965e4 payloads/edk2: Update default MrChromebox branch from 2508 to 2511
* b4917ed44d payloads/edk2: rework serial output configuration
* 282c27c95c arch/x86/acpi_bert_storage.c: Allow vendor specific BERT entries
* 00fbc08b76 Reapply "soc/mediatek/mt8196: Call fsp_init via boot state"
* e6c5ee6450 mb/google/hatch/var/kohaku: Add Samsung S-pen driver support
* b890ca0648 mb/google/brya/var/yaviks: select USE_MTCL only if CHROMEOS
* a8737c5f86 mb/google/cyan: Set CBFS_SIZE default to match IFD BIOS size
* 72af15f1de mb/google/zork: Fix missing comma in CFR object list
* 5db16ea6fc soc/intel/pantherlake: Fix incorrect use of logical OR for TDP selection
* 2c58e525e8 soc/intel/ptl: Add ACPI IOST support
* 52aeb078ce soc/intel/common/acpi: Add IOST device
* d62764df87 soc/intel/common/block/p2sb: Add SSDT function for SoC-specific features
* 96b4754c35 soc/intel: Add CPU ID support for Nova Lake
* b741e2274e acpi: Add enums for TPM2 start method
* 6fd865f409 drivers/amd/ftpm: Add fTPM driver for PSP emulated CRB TPMs
* c09352d58d soc/intel/pantherlake: Update PS1 threshold to the latest recommendations
* 093ae8eeaa mb/siemens/mc_ehl7: Enable reboot after HW Watchdog expiry
* ddf4748c22 mb/siemens/mc_ehl7: Deactivate RTC
* e8ac9ffcd9 mb/siemens/mc_ehl7: Add new board variant based on mc_ehl6
* 94e6e5cd0d mb/google/ocelot: Add option to enable VGA mode 12
* fbf0087918 mb/google/ocelot/var/ocicat: Use GPP_F10 for ISH
* f2788e963f device: Rename PCI_EXP_SEC_CAP_ID -> PCI_CAP_ID_SEC_PCIE
* e01baafbe2 include/cper.h: Add check information structures
* a6407000f1 mipi/panel: Add 'poweroff' field to panel_serializable_data
* b4fbc59c6f treewide: Move mipi_panel_parse_commands() to commonlib
* 1d2b399fd7 lib: Rename `fill_lb_framebuffer` to `get_lb_framebuffer`
* 5f86aba4b3 soc/intel/common: Enable high address support for MCHBAR in ACPI
* f00a2ff7b8 arch/x86/ioapic.c: Support 8-bit IOAPIC IDs
* 3c3fbbaabf arch/x86/acpi_bert_storage.c: Remove unused variable
* 9f4132712f soc/intel/alderlake: add chipsetinit support
* a5c0307e9c commonlib/device_tree: Add dt_add_reserved_memory_region helper
* a3a556f05d mb/google/fatcat/var/ruby: Add wifi SAR table
* 8bc1372f72 sb/intel/common/spi: Prevent transfers across 4KiB boundaries
* 95ad028274 drivers/smmstore: Use lookup_store() for memory-mapped reads
* c421847fe2 util/crossgcc: Fix GNAT detection for gnat-15
* 292d7b9d3d Revert "soc/mediatek/mt8196: Call fsp_init via boot state"
* e705c39009 libpayload/arch/arm64/mmu: Add CB_MEM_TAG to usedmem_ranges
* 18a986c5fe soc/amd/cmn/block/cpu/mca: Support MCA_SYND1 and MCA_SYND2
* c45e153dfb mb/google/bluey/var/quartz: Enable PS8820 support
* e303357cb9 soc/qualcomm/x1p42100: Call mainboard Type-C config hook
* f9efe53cb0 mb/google/bluey: Implement PS8820 retimer configuration
* 657bcd32d9 mb/google/bluey: Add Kconfig for PS8820 retimer support
* 17a52ce94e soc/qualcomm/x1p42100: Add mainboard USB Type-C config hook
* 16cb8d0d0c mb/google/bluey: Add power sequencing for USB-C1 retimer
* 5034f8629f soc/intel/common: Add spinlock protection to fast SPI flash operations
* ceaa41c9e4 drv/intel/mipi_camera: Verify SSDB only for camera sensors
* ede97ef9da mb/google/volteer: Add IPUA device and sensor names
* 65cbf312af mb/google/volteer: Convert MIPI camera cfg from static ASL to devicetree
* 2aca802e85 mb/google/brya/acpi/cnvi_bt_reset: Fix BT re-enumeration under Windows
* 524ad684af mb/google/brya/var/taeko: Fix SOF speaker topology selection
* 829b8be432 libpayload: Add bulk with timeout callback to USB
* f4fe5514fe mb/google/ocelot/var/kodkod: Update gpio settings for NC pins
* c7f0697867 coreboot_tables: Add new CBMEM ID to hold the PCI RB aperture info
* 3ded43722a soc/amd/cmn/block/acpi/ivrs: Use less PCI accesses
* 1da7c31810 include/cpu/x86/msr.h: Add MCA related MSRs
* 7deb82d744 mb/google/bluey: Configure QUPV3_0_SE3 and QUPV3_0_SE7 for USB-C0 and USB-C1 Retimer I2C access
* b00d2ad5c2 vc/intel/fsp/fsp2_0/pantherlake: Update PTL FSP headers to FSP 3442.07
* b7ad850fd6 mb/google/bluey: Add percentage symbol to battery level log
* ae48ff8c0b drivers/wwan/fm: Use _EVT method to enhance GPIO event handling
* 7ed7abbd92 acpigen_ps2_keybd: map screenlock
* 6b52f82df2 util/amdfwtool: Remove AMD_FW_GFXIMU_2 entry
* b9145e1588 util/amdfwtool: Remove duplicated AMD_TA_IKEK
* e393fd00a4 include/cper.h: Update cper_ia32x64_context_t
* 14a7a2315e soc/mediatek/mt8196: Call fsp_init via boot state
* 82f9c593ab payloads/libpayload: Add support for RISC-V 64-bit architecture
* 4decc72c23 drivers/intel/touch: Change ELAN device name for Google's Rex touch device
* 17b36286c8 mb/google/hatch/var/kindred: Drop VBT for KLED variant
* cf280eaa7f amdblocks/root_complex.h: Add new IOHC base addresses
* ba0483c94a soc/amd/common/Makefile.mk: Strip quotes from AMDFW_CONFIG_FILE
* b2b1eb3c5a soc/amd/common/block/smn: Add simple SMN I/O accessors
* f8c10eda36 mb/google/nissa/var/gothrax: Add Rayson parts to RAM ID table
* 0c26c4494d mainboard/google/bluey: Enable display clocks and MMCX power rail
* e1e7b9b203 soc/qualcomm/x1p42100: Add API to enable display clocks
* 02e6f2a214 soc/qualcomm/x1p42100: Add API to intialize RPMh resources for display
* dc162f84be soc/qualcomm/common: Add RPMh driver support
* 999dd8905a lib/bootmem: Replace conditional return with assert in bootmem_add_range_from
* eb814f3b12 lib/bootmem: Remove forward declaration of bootmem_range_string
* 6f394ce50d coreboot_tables: Update CB_MEM_TAG and LB_MEM_TAG values to 17
* 6966885290 mb/google/skywalker: Extend MIPI panel delay to meet T3 timing
* 273e84976b mb/asus/p8z77-v: Apply vendor PCH interrupt mapping
* 573c37a518 sio/nuvoton/common: Refactor nuvoton_pnp_*_config_state()
* 0c2a3002d9 mb/asrock/z87_extreme4: Temporarily refactor nuvoton_pnp_*_conf_state()
* 19deb55f02 mb/asrock/fatal1ty_z87_professional: Temporarily refactor nuvoton_pnp_*()
* 3d980dae22 mb/google/nissa/var/rull: Add 3 DDR modules to RAM id table
* 4030fc5f91 device/Kconfig: Gate early libgfxinit default on ChromeOS
* b8402a8dfc src/qualcomm/common: Remove display buffer region declarations
* 7896d94c76 soc/qualcomm/x1p42100: Avoid reserving display buffer region
* fe0e14d716 soc/qualcomm/x1p42100: Skip SHRM meta firmware load in ramdump mode
* 56013ce0ff mainboard/google/bluey: Skip SHRM firmware load/reset in ramdump mode
* b8680d53ac mb/google/ocelot/var/ocicat: Add fw_config definitions with UFSC
* c3ff1addde mb/google/ocelot/var/ocicat: Add WIFI SAR table
* 9b5d985838 mb/google/ocelot/var/ocicat: Update audio settings
* 091e8140ea spd/lp5: Add SPD for RS1G32LO5D2FDB-23BT
* bc240baba5 Documentation: Add method for GRUB2 to load seabios from drive
* 02c57577f3 superio/nuvoton: Add common ACPI ASL code
* 7273a5b932 mb/asus/p8x7x-series: Move CONFIG_SUPERIO_PNP_BASE to sio/nuvoton
* 40eca2934f soc/mediatek/common: Track firmware splash screen rendering completion
* 49d34a6f6c mb/google/skywalker: Add MIPI panel GPIOs via lb_gpio
* b354b49d58 libpayload: Increase SYSINFO_MAX_GPIOS to 10
* 25d159a7ec mb/google/skywalker: Use FW_CONFIG for storage and dual init support
* 4063a4c3f1 mb/google/skywalker: Create variant Mace
* a1e9cd3669 mb/google/bluey: Configure QUPV3_2_SE4 for ADSP I2C access
* 2b9653cf34 arch/x86/acpi_bert_storage.c: rename check -> proc_err_info
* a3236ef110 arch/x86/acpi_bert_storage.c: Fix array size calculation
* e3fc4a1f69 ec/starlabs/merlin: Reorganize Kconfig and guard options properly
* 4a07174d0e util/cbfstool: Fix RISC-V relocations
* d912ae91b0 mb/google/bluey: Configure GPIOs for USB camera
* a27a7f0c11 mb/google/trulo/var/kaladin: Decrease G2 touch stop delay time to 150 ms
* 3bebadd347 mb/google/bluey: Enable dynamic SoC calculation and log battery level
* bab8ca2bd0 ec/google/chromeec: Refactor Battery SoC calculation
* 02b3674198 ec/google/chromeec: Add SoC calculation from battery dynamic info
* 06c83d473b ec/google/chromeec: Add function to read battery state of charge
* 7c3d45d94f drivers/usb/intel_bluetooth: Correct S-state level for power resource
* 091ac10059 soc/intel/cnvi: Correct S-state level for CNVP
* 4631f94e51 drivers/usb/intel_bluetooth: Advertise D2 for S0W
* ea045bd322 soc/intel/cnvi: Re-enable Bluetooth on reset timeout
* ffac7d90da soc/intel/cnvi: Correct error values for _RST
* f24a2f35bf mb/asrock: Correct vendor name ASROCK to ASRock
* aeb9dcf2fa libpayload: Add new memory type CB_MEM_TAG
* c093b52c20 soc/mediatek: Correct BIAS_ON value to get bias ready
* 531c24cd0a Documentation: Fix typo in 'particularly'
* 331e93cbd2 libpayload/tests: Disable generation of lcov HTML
* 7d38a96c44 mb/google/skywalker: Create variant Vader
* 75333ea7c8 mb/google/bluey: Refactor is_pd_sync_required function
* 3f00ecb05c soc/intel/pantherlake: Add ChromeOS board-specific TDP setting
* 1dfa80f02c soc/intel/pantherlake: Add configurable TDP support
* dc68f5b265 soc/intel/pantherlake: Let common code set PL1 to TDP
* bb3f40627d util/autoport: Fix style issue in generated code
* 94b326469b mb/google/bluey: Increase FW_MAIN_A/B slot size to 8.5MB
* e6c3250912 mipi/panel: Remove pic_width and pic_height from dsc_config
* 456403d9ba soc/mediatek/mt8196: Stop using dsc_config.pic_width
* 7d50f63213 soc/mediatek: Drop mtk_ddp_soc_mode_set()
* 61c9450d62 soc/mediatek/common: Pass dsi_regs to mtk_dsi_cphy_timing()
* ba5b5ea406 soc/mediatek/mt8196: Move DPM and SPM initialization
* 206025754f libpayload/tests: Remove unrecognized flag --ignore-errors inconsistent
* 82c06da584 3rdparty/fsp: Update to upstream master
* c5eecee5e9 mb/google/rex: Add IPUA device and sensor names
* bceb2c83ad mb/{google/intel}: Fix/add missing MIPI camera SSDB lanes_used/link_used
* de4148888c tests: Disable generation of lcov HTML
* 188cd88ac7 soc/mediatek/mt8196: Correct MIPI register control
* 080ca011fe Documentation: Finalize 25.12 release notes
* 695041a9bf mb/starlabs/*: Increase size of SMMSTORE region to 512KB
* 975e48faaf mb/starlabs/starlite_adl: Add CFR option for charge LED brightness
* 951c28c1bf mb/starlabs/starfighter: Add CFR options for power/charge LED brightness
* ab2c69c4f3 mb/starlabs/starbook: Add CFR options for power/charge LED brightness
* 84ff3d3d12 ec/starlabs/merlin: Add charge LED brightness control
* ac170631d5 mb/starlabs/starlite: Fix ddr5 entry
* 0e217cf1d3 soc/mediatek/mt8196: Increase FRAMEBUFFER to 32MiB
* 003ea85115 soc/mediatek/mt8196: Support logo display on DISP_PATH_DUAL_MIPI path
* 7e7ba6fb11 security/lockdown/lockdown.c: option to lock COREBOOT and BOOTBLOCK
* 56a7ae4389 soc/mediatek/mt8196: Notify MCUPM to support MTE
* 7c7feca258 CBFS verification: support Top Swap redundancy
* 739808011a Makefile.mk: don't add bootblock after other files
* cbac0d7a25 Makefile.mk,cpu/intel/fit/Makefile.mk: introduce CBFS_REGIONS
* f773a0faac cpu/intel/fit/Makefile.mk: make FIT in TOPSWAP point at MCU in COREBOOT_TS
* fa80ab0146 src/Kconfig: add MAINBOARD_NEEDS_CMOS_OPTIONS
* 59d438f5c7 mb/google/bluey: Remove GSCVD region from Bluey and BlueyH variants
* 7c4d9e0862 mb/google/*: Update Kconfig names with all known board names
* 35be1ab679 configs: Build test ramstage zstd compressed
* 2d99da12a9 commonlib/bsd: Add zstd support
* 4ca5e9c8c6 rules.h: Add ENV_RAMSTAGE_LOADER
* 0421ef2cd8 util/cbfstool: Add zstd support
* 0302b2ee07 lib/xxhash: Move to commonlib/bsd
* 76e9635346 amdfwread: Parse and print directory sizes
* a3adf4898b mb/google/brya/var/pujjocento: Add 2 Micron modules to RAM id table
* d1e1003217 spd/lp5: Add SPD for MT62F2G32D4DS-031RFWT:C
* d528561130 mb/google/bluey: Use PMIC for off-mode detection
* 65833355ca tests: Disable gcov warnings
* 060d18f070 soc/mediatek/mt8196: Add DSI dual channel

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 23:53:12 +00:00
Leah Rowe 86cbf66b78 NEW MAINBOARD: Dell Latitude E7240 from Iru Cai
Thank you Iru Cai for this coreboot port.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 22:23:10 +00:00
Leah Rowe a494c3c2e2 Revert "coreboot/default: don't remove fsp files"
This reverts commit 2e6f6e2579.

This was a stupid revert. I don't remember why I even did it.

Better to make the releases *not* take up an extra 100MB per
source file, until I actually need these extra files.
2026-01-20 12:15:45 +00:00
Leah Rowe f22d4b1c49 u-boot: update configs
i did: ./mk -u u-boot

otherwise, building u-boot asks for user input

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 12:06:15 +00:00
Leah Rowe 778ae1653a fix grub version name in xhci_nvme
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 12:03:01 +00:00
Leah Rowe 9ea35f3866 Libreboot 26.01 RC2, or: Magnanimous Max
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 04:32:50 +00:00
Leah Rowe b538749c83 remove T480/T580 thunderbolt driver
it causes s3 resume to break on t480s

more testing needed across the board(s)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-20 04:32:34 +00:00
Leah Rowe 4e33b40655 re-add deleted grub border patch
accidentally deleted it during rebase

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-19 16:33:13 +00:00
Leah Rowe d22f7f9633 update grub to 2.14
This brings these extra changes:

* eaa3b8f0f Bump version to 2.15
* d38d6a1a9 Release 2.14
* 35bfd6c47 build: Add grub-core/tests/crypto_cipher_mode_vectors.h file to EXTRA_DIST
* ac042f3f5 configure: Print a more helpful error if autoconf-archive is not installed
* e37d02158 kern/ieee1275/openfw: Add a check for invalid partition number
* f94eae0f8 grub-mkimage: Do not generate empty SBAT metadata
* 1aa0dd0c0 configure: Defer check for -mcmodel=large until PIC/PIE checks are done
* ff1edd975 util/grub-mkimagexx: Stop generating unaligned appended signatures
* 51ebc6f67 tests: Add functional tests for ecb/cbc helpers
* caaf50b9a osdep/aros/hostdisk: Fix use-after-free bug during MsgPort deletion
* 18f08826f kern/efi/sb: Enable loading GRUB_FILE_TYPE_CRYPTODISK_ENCRYPTION_KEY and GRUB_FILE_TYPE_CRYPTODISK_DETACHED_HEADER

NOTE: This patch was reversed:

* ac042f3f5 configure: Print a more helpful error if autoconf-archive is not installed

Because it quite unhelpfully broke the build.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-19 16:03:51 +00:00
Leah Rowe 21d5050fb4 delete x230* corebootfb configs for now
a user reported that there is just a black screen at bootup
in 26.01 rc1 on these, but txtmode works.

only their x230 broke in corebootfb. their t430 and x200 they
tested worked fine.

txtmode works. this bug didn't affect 25.06, according to this
user.

no harm deleting these for now. i'll test it myself later (the
user isn't being very helpful with reporting) and fix whatever
the problem is.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-19 13:47:44 +00:00
Leah Rowe 2e6f6e2579 coreboot/default: don't remove fsp files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-06 22:18:54 +00:00
Leah Rowe bbfee155ba fix fsp extraction for topton x2e n150
coreboot updated the fsp file. we know the old one worked,
so no point testing the new one so close to a stable lbmk
release.

i've modified 3rdparty/fsp/ to re-add the old one as another
file, so that other boards are unaffected, and updated the
Kconfig so that the special file is used for x2e n150 only.

more specifically, added a second fsp submodule.

it's a bit dirty, but avoids bloating lbmk.git

Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-01-06 22:17:05 +00:00
Leah Rowe d5351aee37 inject: fix mac address insertion
during previous re-factoring, i sorted variable initialisations.

that was all well and good, but prior to that, i initialised
the new_mac string to empty at first, and then to
the "xx" letters; the latter made the first initialisation
redundant, but in the re-factoring, I put the blanking of
the string afterward.

this disabled mac address insertion, because the way the script
works is precisely to avoid mac address insertion when the mac
string is empty. this is used when running the "nuke" command.

silly me.

yes, i'm very silly. very very silly. so silly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-25 13:41:37 +01:00
Leah Rowe a59fc6a353 Libreboot 26.01 RC1 Tenacious Tomato
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-25 01:11:59 +01:00
Leah Rowe b259f3493d update pcsx-redux openbios
use revision:
b745534eb231d3699ec57949f16a9a7bd5b79385

This brings the following upstream changes:

*   b745534e Merge pull request #1957 from wheremyfoodat/splash
|\
| *   33adecd6 Merge branch 'main' into splash
| |\
| |/
|/|
* |   d01e438e Merge pull request #1979 from nicolasnoble/upgrade-fmt
|\ \
| * | ae8c5cb8 Updating fmt to 12.1.0
|/ /
* |   fd9959a8 Merge pull request #1978 from malucard/all
|\ \
| * | 3ecd98e6 change deprecated fmt::localtime to std::localtime
|/ /
| * eec812e3 Nix: Stop using the outdated version of stb from nixpkgs (#7)
| *   836a0e10 Merge branch 'main' into splash
| |\
| |/
|/|
* |   e90d74d6 Merge pull request #1968 from wheremyfoodat/fix-coroutine
|\ \
| * | 62a23f8f Fix coroutine build on AppleClang 17
* | |   a56a96be Merge pull request #1974 from njfox/aur-ci-dependencies
|\ \ \
| * | | 98d10525 add --syncdeps to install missing PKGBUILD dependencies
| |/ /
* | |   3c155400 Merge pull request #1977 from aybe/fix-icon-overlay
|\ \ \
| * | | 79de997d Fix spurious folder icon overlay
* | | |   1d573efa Merge pull request #1976 from aybe/fix-missing-directory-extension
|\ \ \ \
| * | | | b13b80c7 Render directory node fully (including extension)
| |/ / /
* | | |   1a678f42 Merge pull request #1975 from aybe/fix-wrong-c-drive
|\ \ \ \
| |/ / /
|/| | |
| * | | c37d0597 Fix C:\ showing current directory
|/ / /
* / / 47d83a2b Padding isos to 2 minutes instead of 2 seconds.
|/ /
* |   718f0912 Merge pull request #1962 from njfox/aur-ci
|\ \
| * \   c70d85e4 Merge branch 'main' into aur-ci
| |\ \
| |/ /
|/| |
* | |   87f8e861 Merge pull request #1964 from nicolasnoble/tpageloc-fix
|\ \ \
| * \ \   acdc7e50 Merge branch 'main' into tpageloc-fix
| |\ \ \
| |/ / /
|/| | |
* | | |   a11e5ed6 Merge pull request #1965 from nicolasnoble/brew-hotfix
|\ \ \ \
| * | | | d6e15260 Now fixing psyqo...
| * | | | a7035f32 Fixing OpenBIOS build under 15.2...
| * | | | 909eb220 Also patching gcc now.
| * | | | c319254e Adding zlib patch for binutils on macos...
| * | | | d56b30e3 Derp.
| * | | | 00bd1db0 Upgrading gcc and gdb as well...
| * | | | 27e6fab9 Adding verbose mode.
| * | | | 5cb9084d Restoring readme properly.
| * | | | d911c2b1 Updating to binutils 2.45.
| * | | | a759cb84 Fixing https://github.com/orgs/Homebrew/discussions/6351
|/ / / /
| * / / 6de0f096 Properly returning a TPageLoc on TPageAttr::getPageLoc
|/ / /
| * |   98c53855 Merge branch 'main' into aur-ci
| |\ \
| |/ /
|/| |
* | |   a285e14e Merge pull request #1955 from wheremyfoodat/mac-bundle
|\ \ \
| * | | 97b9651b MacOS bundle script: Enable game mode support, list app as game
| * | | 0e0fabf2 MacOS bundle script: Clean up temporary image files
* | | |   1d54cbe6 Merge pull request #1958 from wheremyfoodat/aa64-flush-cache
|\ \ \ \
| * | | | 053eb573 arm64 JIT: Fix broken cache invalidation
| |/ / /
* | | |   52d9ddc5 Merge pull request #1956 from wheremyfoodat/jit-fixes
|\ \ \ \
| * | | | 4dd04425 a64 JIT: Fix setRWX function returning nothing on Apple
| |/ / /
* | | |   4e846d89 Merge pull request #1959 from wheremyfoodat/no-portable
|\ \ \ \
| * | | | 169788fb Add --no-portable flag
| |/ / /
* | | |   7bce4ecd Merge pull request #1960 from wheremyfoodat/remove-dynarec-dump
|\ \ \ \
| * | | | 8c995593 arm64 JIT: Don't unconditionally dump a JIT dump in the user's files
| |/ / /
* | | |   3a8ddc79 Merge pull request #1963 from njfox/openbios-fix-function-signatures
|\ \ \ \
| |/ / /
|/| | |
| * | | 98d9684b move pointer asterisk to be consistent
| * | | e7ad2b1e fix function definitions to include correct argument types
|/ / /
| * | bdaa1fe9 remove duplicate git dependency
| * | 53326672 combine dependency updates/installation and fix indentation
| * | f4d1f073 build against PR and push instead of master
|/ /
| * cdec82a4 Fix VS project files
| * 587ce8e9 GUI: Better splash image, bug fixes
| * 0b73a07a Add splash screen generation script
| * 3c4afbb6 Initial splash image draft
|/
*   4f4a00fe Merge pull request #1953 from cleverca22/fix-submodules
|\
| * 2bc000e8 fix submodules
* |   a4d6bcc4 Merge pull request #1954 from yaz0r/gdb_sharedmem
|\ \
| |/
|/|
| * 390ccf63 Address comments
| * 07e9b472 Add monitor command to retrieve the shared memory name. Only for wram so far.
|/
*   1b0cbe5e Merge pull request #1952 from yaz0r/gdbfix
|\
| * b4e77deb Fix GDB packet p (readRegister)
|/
*   a2a6d77c Merge pull request #1951 from nicolasnoble/linuxdeploy
|\
| * 2388bcb1 Switching to linuxdeploy.
|/
*   ec1154ad Merge pull request #1950 from grumpycoders/revert-1947-appimage-bullshit
|\
| * 5a66d37f Revert "Sorting out yet another AppImage breakage."
|/
*   a1f02931 Merge pull request #1940 from Forceh91/patch-1
|\
| * e23f9d01 Re-adding all examples.
| * f1b8694b Fixing test suite.
| *   78b4e9f1 Merge branch 'main' into patch-1
| |\
| |/
|/|
* |   b62b506f Merge pull request #1944 from eliasdaler/authoring_quiet
|\ \
| * \   572e18ba Merge branch 'main' into authoring_quiet
| |\ \
| |/ /
|/| |
* | |   cb651973 Merge pull request #1946 from nicolasnoble/pcsx-io-fixes
|\ \ \
| * \ \   fca66d17 Merge branch 'main' into pcsx-io-fixes
| |\ \ \
| |/ / /
|/| | |
* | | | b2066c72 Merge pull request #1947 from nicolasnoble/appimage-bullshit
* | | | e5244aea Sorting out yet another AppImage breakage.
 / / /
* / / e1be0936 Fixing accesses to the pcsx IO system.
 / /
* / 0fbc4206 autoring: add -q option
 /
* eaff5ed2 Merge branch 'main' into patch-1
* c0fa3b2f chore: nitpick changes from coderabbit
* 3b3e7986 chore: create readme with community examples

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 19:14:43 +01:00
Leah Rowe a4ad3afdbb bump flashprog rev: ffcf92fb, December 2025
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 19:02:08 +01:00
Leah Rowe 68e0b5dddc init.sh: Explicitly export UTF-8 locale
C.UTF-8, instead of just C.

This fixes a build issue in GRUB on my Arch Linux test bench.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 17:16:10 +01:00
Leah Rowe b990d54cff grub modules: add more gcry_ ciphers
Since the libgcrypt update in GRUB, which imported
GNU's own Argon2 implementation, other ciphers have
also been introduced.

This patch adds them to lbmk's GRUB build.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 02:35:30 +01:00
Leah Rowe 5df6b924d7 bump seabios revision
by the time i'd done this, i'd realised that seabios only
modified some documentation upstream. the code has not
changed since last update, upstream.

no point scrapping the update now. now we have slightly
better documentation for seabios!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 01:58:24 +01:00
Leah Rowe 9228a0c02c update grub again, to 25b7f6b93
i had a build error before, when trying this absolute
most up to dave revision.

i found that it was this patch:

commit 1a5417f39a0ccefcdd5440f2a67f84d2d2e26960
Author: Nicholas Vinson <nvinson234@gmail.com>
Date:   Tue Nov 18 19:38:07 2025 -0500

For now, I just revert it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-24 01:47:28 +01:00
Leah Rowe 512cce0770 GRUB: update to rev 2.14-rc1 December 2025
The argon2 patches were dropped (PHC implementation),
because GRUB has now its own Argon2 KDF implementation
as part of its recent libgcrypt update.

Argon2 support is therefore retained, but GNU's implementation
has replaced the one that Libreboot previously used.

This brings in the following upstream changes:

* 280715ec6 Release 2.14~rc1
* e549317e1 windows: Fix symbol table generation during module conversion from PE to ELF
* a340750f9 windows: Fix relocation sections generation during module conversion from PE to ELF
* c602035a9 loader/efi/linux: Fix compile error with Clang
* f62269767 build: Add tpm2key.asn file for reference to dist archive
* 46be4488f build: Include new zstd test support files in dist archive
* fa79d5ea9 build: Include MAINTAINERS and SECURITY files in dist archive
* 8271bcc13 build: Add appended signatures header file to EXTRA_DIST
* 11845da2b lib/xzembed/xz_dec_stream: Replace grub_memcpy() call with memcpy()
* 7ded35fea bootstrap: Fix patching warnings
* 4129e9ad6 tss2: Always init out buffer before calling tpm2_submit_command_real()
* 000e48b42 fs/ntfs: Correct next_attribute validation
* 5ff9c43cf kern/ieee1275/init: Use net config for boot location instead of firmware bootpath
* c2cae77ab net/tftp: Fix NULL pointer dereference in grub_net_udp_close()
* fadc94b91 net/dns: Prevent UAF and double free
* cd24e2591 net/bootp: Prevent a UAF in network interface unregister
* fca6c0afd docs: Document lsmemregions and memtools commands
* 42c099786 commands/memtools: Add lsmemregions command
* 20211246a tests/file_filter: Add zstd tests
* 092449f63 tests/file_filter: Add zstd test file
* 356dcac9a tests/file_filter: Regenerate gpg keys
* 8ea83c3ee io/zstdio: Implement zstdio decompression
* 7c22c1000 fs/btrfs: Update doc link for bootloader support
* 6435551a6 docs: Add Btrfs env block and special env vars
* b63447748 util/grub.d/00_header.in: Wire grub.cfg to use env_block when present
* e4e177661 fs/btrfs: Add environment block to reserved header area
* d6525f0e6 util/grub-editenv: Add probe call for external envblk
* 4b5ea8dca util/grub-editenv: Wire list_variables() to optional fs_envblk
* 84e2bc2f1 util/grub-editenv: Wire unset_variables() to optional fs_envblk
* c7c901916 util/grub-editenv: Wire set_variables() to optional fs_envblk
* 2abdd8cd2 util/grub-editenv: Add fs_envblk write helper
* e4d684cc4 util/grub-editenv: Add fs_envblk open helper
* 512e33ec7 tests: Add "z" length modifier printf tests
* 3c9762b12 kern/misc: Add the "z" length modifier support
* 91ddada64 disk/cryptodisk: Add --hw-accel to enable hardware acceleration
* f8f68f14a libgcrypt: Add hardware acceleration for gcry_sha512
* 70b2f5f08 libgcrypt: Add hardware acceleration for gcry_sha256
* 2158d8e8a libgcrypt: Declare the sha256 shaext function
* 0ff5faf8c libgcrypt: Implement _gcry_get_hw_features()
* 812356191 libgcrypt: Copy sha512 x86_64 assembly files
* 7f9c590af libgcrypt: Copy sha256 x86_64 assembly files
* 8423176f1 lib/hwfeatures-gcry: Enable SSE and AVX for x86_64 EFI
* 06a5b88ba lib/hwfeatures-gcry: Introduce functions to manage hardware features
* d01abd713 configure: Tweak autoconf/automake files to detect x86_64 features
* a122e0262 lib/pbkdf2: Optimize PBKDF2 by reusing HMAC handle
* 961e38b2b lib/crypto: Introduce new HMAC functions to reuse buffers
* 59304a7b5 docs: Document argon2 and argon2_test modules
* 28dbe8a3b kern/misc: Implement faster grub_memcpy() for aligned buffers
* da01eb0c5 tests/util/grub-fs-tester: Use Argon2id for LUKS2 test
* c1bd9fc82 tests: Integrate Argon2 tests into functional_test
* 6a525ee64 tests: Import Argon2 tests from libgcrypt
* 6052fc2cf disk/luks2: Add Argon2 support
* 66b8718f9 argon2: Introduce grub_crypto_argon2()
* de201105d libgcrypt/kdf: Fix 64-bit modulus on 32-bit platforms
* 93544861b libgcrypt/kdf: Remove unsupported KDFs
* 1ff720641 libgcrypt/kdf: Get rid of gpg_err_code_from_errno()
* 0c06a454f libgcrypt/kdf: Implement hash_buffers() for BLAKE2b-512
* bc94dfd54 crypto: Update crypto.h for libgcrypt KDF functions
* 5b81f490c util/import_gcry: Import kdf.c for Argon2
* 6b5c671d3 commands/menuentry: Fix for out of bound access
* 21cdcb125 tests/tpm2_key_protector_test: Add a test for PCR Capping
* afddba012 tpm2_key_protector: Support PCR capping
* ae7a39900 tss2: Implement grub_tcg2_cap_pcr() for emu
* 7b39970e9 tss2: Implement grub_tcg2_cap_pcr() for ieee1275
* 39f98e471 tss2: Implement grub_tcg2_cap_pcr() for EFI
* d47d261ec tss2: Introduce grub_tcg2_cap_pcr()
* b2549b4d3 tss2: Add TPM2_PCR_Event command
* e1b9d92a8 loader/i386/linux: Transfer EDID information to kernel
* a8379e693 fs/hfsplus: Allow reading files created by Mac OS 9
* c5ff0d616 docs: Fix build warnings in libgcrypt and blsuki doc
* fa93f2412 kern/command,commands/extcmd: Perform explicit NULL check in both the unregister helpers
* 9a725391f commands/efi/tpm: Call get_active_pcr_banks() only with TCG2 1.1 or newer
* 894241c85 kern: Include function name on debug and error print functions
* 75a20cc14 kern: Make grub_error() more verbose
* 8abbafa49 net/tcp: Fix TCP port number reused on reboot
* 3dff10a97 docs/grub: Document appended signature
* 0f2dda8cf docs/grub: Document signing GRUB with an appended signature
* 0b59d379f docs/grub: Document signing GRUB under UEFI
* dbfa3d7d7 appended signatures: Verification tests
* 7f68c7195 appended signatures: GRUB commands to manage the hashes
* 6cb58b1c9 appended signatures: GRUB commands to manage the certificates
* ab7b17717 appended signatures: Using db and dbx lists for signature verification
* 97f7001e1 appended signatures: Create db and dbx lists
* b5e872417 appended signatures: Introducing key management environment variable
* 76158ed1a powerpc/ieee1275: Read the db and dbx secure boot variables
* 069f3614e appended signatures: Support verifying appended signatures
* f8e8779d8 powerpc/ieee1275: Enter lockdown based on /ibm, secure-boot
* e95c52f1f appended signatures: Parse X.509 certificates
* a33754979 appended signatures: Parse PKCS#7 signed data
* 3e4ff6ffb appended signatures: Parse ASN1 node
* 7d28bdb0b appended signatures: Import GNUTLS's ASN.1 description files
* 1fca5f397 grub-install: Support embedding x509 certificates
* aefe0de22 pgp: Rename OBJ_TYPE_PUBKEY to OBJ_TYPE_GPG_PUBKEY
* f826cc8b0 crypto: Move storage for grub_crypto_pk_* to crypto.c
* 31cc7dfe5 powerpc/ieee1275: Add support for signing GRUB with an appended signature
* ee789e1a6 lib/b64dec: Use grub_size_t instead of size_t for _gpgrt_b64dec_proc() function definition
* abb8fb6d1 util/grub-mkimagexx: Fix riscv32 relocation offset
* 1f9092bfd libgcrypt: Allow GRUB to build with Clang
* 1d2ee8f8b tests: Add test ISO files to dist package
* dfa3dbf61 tests: Test dates outside of 32-bit Unix range
* 6837293b8 lib/datetime: Support dates outside of 1901..2038 range
* 02788bfdf bootstrap: Ensure shallow gnulib clone works on newer git
* 4e42199f3 docs: Correct some URLs
* 733cc28eb docs: Update Future section to reflect current release
* 54c8573ef docs: Document new libgrypt modules
* 1562dee69 docs: Clarify section heading and fix wording
* cf1b75a14 BUGS: Update to point to bug tracking system
* 236663dfb INSTALL: Document libtasn1 needed for grub-protect
* 7bfb38627 po: Update translations to build with gettext 0.26
* 49e76ad16 term/efi/console: Treat key.scan_code 0x0102 (suspend) as Enter
* de72f3998 util/bash-completion.d/Makefile.am: s/mkrescure/mkrescue/g
* 14c2966c7 blsuki: Add uki command to load Unified Kernel Image entries
* 5190df851 blsuki: Check for mounted /boot in emu
* 51b960132 util/misc.c: Change offset type for grub_util_write_image_at()
* 8cee1c284 blsuki: Add blscfg command to parse Boot Loader Specification snippets
* e016d6d60 kern/misc: Implement grub_strtok()
* 587db89af kern/xen: Add Xen command line parsing
* b2a975bc5 include/xen/xen.h: Add warning comment for cmd_line
* 19c698d12 zfs: Fix LINUX_ROOT_DEVICE when grub-probe fails
* 6898fcf74 relocator: Switch to own page table while moving chunks
* 67a95527b configure: Generate tar-ustar tarball instead of tar-v7
* 29d515b4c build: Add new libgcrypt and libtasn1 related files to EXTRA_DISTS
* eb76b064d build: Add util/import_gcrypt_inth.sed to EXTRA_DISTS
* eb56a6af9 include/xen/xen.h: Rename MAX_GUEST_CMDLINE to GRUB_XEN_MAX_GUEST_CMDLINE
* 80df5e132 loader/arm64/xen_boot: Set correctly bootargs property for modules
* 6831d242a loader/efi/linux: Return correct size from LoadFile2
* f326c5c47 commands/bli: Set LoaderTpm2ActivePcrBanks runtime variable
* 0e367796c docs: Write how to import new libgcrypt
* b930bfa37 libgcrypt: Fix a memory leak
* d48c277c4 libgcrypt: Don't use 64-bit division on platforms where it's slow
* de49514c9 util/import_gcry: Fix pylint warnings
* 334353a97 util/import_gcry: Make compatible with Python 3.4
* 2a6de4209 libgcrypt: Import blake family of hashes
* e54187912 libgcrypt: Ignore sign-compare warnings
* e3b78e49c libgcrypt: Remove now unneeded compilation flag
* e23704ad4 libgcrypt: Fix Coverity warnings
* d65810b01 keccak: Disable acceleration with SSE asm
* f808ef0d2 tests: Add DSA and RSA SEXP tests
* 0739d24cd libgcrypt: Adjust import script, definitions and API users for libgcrypt 1.11
* 3e1c2890b b64dec: Add harness for compilation in GRUB environment
* 5ca0d5e41 b64dec: Import b64dec from gpg-error
* 3312af6e0 libgcrypt: Import libgcrypt 1.11
* a0d4c94ef loader/efi/linux: Use shim loader image handle where available
* 1b9a84e63 loader/efi/chainloader: Use shim loader image handle where available
* e31d0cd7f efi/sb: Add API for retrieving shim loader image handles
* ed7e053a3 efi/sb: Add support for the shim loader protocol
* 70897d3d3 efi: Provide wrappers for load_image, start_image and unload_image
* 030a70fca loader/arm64/xen_boot: Consider alignment calling grub_arch_efi_linux_boot_image()
* e82609a47 loader/arm64/xen_boot: Use bool instead of int
* d1a470b69 loader/arm64/xen_boot: Remove correctly all modules loaded by xen_module command
* cf5e52fa8 dl: Fix grub_dl_is_persistent() for emu
2025-12-23 22:04:30 +01:00
Leah Rowe 8b338404e8 hp8300cmt and dell 780: use legacy verbs
see patches. coreboot making changes upstream. these
are used in the meantime.

this prevents build errors. (again, see patches, specifically
the 780 one explains rationale)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-23 18:49:47 +01:00
Leah Rowe 0ff8110a55 fix 3050micro vbt path again
i got the variable wrong, putting the dollar sign inside
the brackets, rather than outside.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-23 12:15:06 +00:00
Leah Rowe ce302356fc coreboot/dell3050: fix VBT-related build error
During routine build testing, I noticed that the VBT path was
wrong, because this port had been converted into a variant.

This is because of the OptiPlex 5040 port that is under
review on the coreboot Gerrit website.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-23 11:15:43 +00:00
Leah Rowe 2fe3b6ee66 actually enable TBT on T580
lbmk uses make-oldconfig before running a build anyway,
so it would have been fine. however, it's best to just
enable it outright.

this change was generated by doing:

./mk -u coreboot t580_vfsp_16mb

which runs make-oldconfig on the configs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-22 11:58:38 +00:00
Leah Rowe 6e253b3e73 thunderbolt support for thinkpad t580
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-22 11:10:05 +00:00
Leah Rowe 9142c8b419 ThinkPad T580 support.
Yes.

Thank you Johann C. Rode for this excellent coreboot port.

You're a star.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-21 14:49:53 +00:00
Leah Rowe 992b03a383 coreboot/default: use 3rdparty/cmocka by default
this is used by the coreboot build system, for tests.

upstream tries system cmocka by default, but we want the
one in 3rdparty to be used.

i've changed the default to 0 (try 3rdparty cmocka). you
can still override this at runtime.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-21 14:48:30 +00:00
Leah Rowe e7628421d7 coreboot/default: add cmocka submodule
otherwise, we get the following from coreboot's build
system, when performin operations in it:

tests/Makefile.mk:31: No system cmocka, build from 3rdparty instead...

However, *we* (Libreboot project) patch coreboot's build system,
so as to not download submodules itself, because lbmk handles
them manually. This is because lbmk's submodule handling has some
extra redundancy features.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-21 14:48:30 +00:00
Leah Rowe 946ede9e7d fix ifdtool build on coreboot/default
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-21 14:48:30 +00:00
Leah Rowe 24f25bf7bc update deguard
this adds the recent kaby thinkpads

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-19 08:17:44 +00:00
Leah Rowe 63b527e8ff cb/default: bump to rev def7aa7094, December 2025
latest coreboot revision of of today / right now at the
time of this commit

this brings the following upstream changes:

* def7aa7094 arch/riscv/smp: Fix race condition
* fc37085ddb Documentation/vboot: Update vboot supported boards list
* 5bb7a83a7a acpi/acpi_apic.c: Generate MADT LAPIC entries based on current mode
* 077191641b vendorcode/amd/opensil/Makefile.mk: Add 0x prefix for BIOS address
* 4b353affd4 soc/amd/common/acpi/lpc.asl: Add HPET device
* 0a867b3971 acpi/ivrs: Fill second EFR image value
* 92f03c0c28 mb/google/ocelot/var/kodkod: Config touchpad I2C frequency
* a923470688 drv/intel/mipi_camera: Remove duplicate comments for DSM methods
* 896984e800 mb/google/bluey/quartz: Enable parallel charging support
* de87ea0efa mb/google/bluey: Add parallel charging infrastructure
* cfb0d8a144 mb/google/bluey: Enable PD negotiation when battery is missing
* ddc1b51b43 mb/google/bluey: Enable PD negotiation in charging modes
* c4ee22e267 Reapply "mb/google/bluey: Implement EC-based off-mode detection"
* a225eefd4c drivers/spi: Add Macronix MX77U51250F chip id
* 793c15a866 mb/google/ocelot: Fix Gen4 SSD power sequencing
* b689671e79 include/acpi/acpi_apei.h: Add MCE APEI structs
* 7a41dc416b include/acpi/acpi_apei.h: Add NMI APEI struct
* 5251284e39 include/acpi/acpi_apei.h: Add PCIe APEI structs
* 53350d5c8d include/acpi/acpi_apei.h: Add internal acpi_head_t struct
* 5001b07f9c drivers/intel/mipi_camera: Add validation and remove unused defaults
* 0f1ae4ae5f drivers/gfx/generic: Add support for non-VGA devices
* ae0d232402 drivers/intel/mipi_camera: Add ACPI device type selection
* 1532eb60ee drv/intel/mipi_camera: Add CVF Support DSM function
* a64b93562d drv/intel/mipi_camera: Add I2C V2 DSM function
* c8f89e00e4 drv/intel/mipi_camera: Refactor DSM generator functions
* ea099e8b8c drivers/intel/mipi_camera: Split DSM generation into per-UUID functions
* 6459a2007a mb/{google,intel}: Add ROM type and address for MIPI camera sensors
* 11ea868b02 mb/google/volteer/var/drobit: Update pl2 minimum value
* 8ed87f71ec mb/google/volteer: Make touchpad wake user-selectable via CFR
* 7e1962a3cc mb/google/hatch: Make touchpad wake user-selectable via CFR
* 152914272c device/azalia: Drop spurious read-back of STATESTS
* 6e074550a5 device/azalia: Repurpose azalia_set_bits() for link-reset only
* ecf202b8e4 device/azalia: Add missing 521us delay after RESET# de-assertion
* d5d27badd4 Documentation: Add coreboot release 26.03 template
* 8e23c46beb Docs/releases: Update release notes for 25.12 release
* 01bc527afa soc/qualcomm/common: Add CMD-DB driver support
* 2277edff88 soc/qualcomm/x1p42100: Split dram_aop region to map dram_aop_cmd_db as non-cacheable
* a4cc178486 soc/qualcomm/common: Map AOP CMD-DB region as uncached region in MMU
* 1b5f105595 mb/google/ocelot/var/ocelot: disable ISH UART0 RX pin
* b67725d3f5 Revert "mb/google/bluey: Implement EC-based off-mode detection"
* 1dc3e45f7c mipi: Support passing user data to mipi_cmd_func_t
* 42c1947d99 mb/google/bluey: Implement EC-based off-mode detection
* e54b82b85b mb/google/ocelot/var/kodkod: Enable pcie_rp5 to allow proper enumeration of pcie_rp6
* 4cc830349c mb/google/rex/var/karis: Add fw_config probe to enable all wifi
* 173a32aa55 MAINTAINERS: Add Jayvik Desai to Google Bluey & Qualcomm SoCs
* f28997dcdd soc/qualcomm/common: Add PD negotiation attribute macro
* b70309350f arch/x86/acpi_bert_storage.c: Fix Error Section GUID compare
* 847d91b82e include/acpi/acpi_apei.h: Update APEI structs for better readability
* 679ea61d4d include/acpi/acpi_apei.h: Add APEI definitions
* eb79807bec soc/qualcomm/x1p42100: Add mainboard hook for QcLib override
* 8ece648c30 soc/qualcomm/common: Use bitwise OR for global_attributes
* 22e54a701d soc/qualcomm/x1p42100: Add AOP, QDSS, and QSEE regions to SSRAM layout
* 4d53aa7704 soc/qualcomm/x1p42100: Relocate PRERAM stack to BSRAM memory
* a26b718d5a soc/qc/x1p42100: Define pre- & post-RAM stack regions in linker script
* 1b599a8844 arch/arm64: Add an alternative entry point for ramstage code
* 641f7ac677 arch/arm64: Introduce distinct PRERAM and POSTRAM stack regions
* 2183326306 soc/qualcomm/x1p42100: Rename qcsdi region to aop_sdi in memlayout
* fad9878a3e vc/intel/fsp/fsp2_0/wildcatlake: Update WCL FSP headers to FSP WCL.3393.02
* 71b79018da util/release/genrelnotes: Restore to saved HEAD instead of origin/main
* 9f6e297399 vc/intel/fsp/mtl: Fix license header in MemInfoHob.h
* 2171af0f5f mb/lenovo/sklkbl_x280: Fix build failure
* a5d3c4c119 mb/lenovo/sklkbl: Fix headphone jack
* 0b4d41004d mb/lenovo/sklkbl: Add Lenovo Thinkpad X280 as a variant
* 9a3818f9b6 soc/mediatek/common: Print DRAM calibration status as string
* 1e8cea55a0 soc/mediatek/common/emi: Cache SDRAM size
* 9203cc827f soc/mediatek/mt8196: Add MTE tag memory to bootmem
* 3d5135fdd0 lib/bootmem: Add memory type for Armv9 MTE tag storage
* 2d45723d87 lib/bootmem: Add bootmem_add_range_from function
* 4f78a40f53 mb/google/ocelot/var/ocicat: Update Touchscreen settings
* 510f1950b4 mb/google/ocelot/var/ocicat: Update devicetree
* 35cb6aea50 mb/google/hatch: Fix CFR pointer
* 8f34fdfab3 Remove <swab.h> and swabXX() functions
* d556bc65c2 mb/google/fatcat/var/ruby: Change GPIO pins to fix audio function
* 6b5a872ce8 soc/mediatek: Pass dsi_regs/mipi_tx_regs to DSI API
* 74c13eead4 soc/mediatek/mt8196: Define dsi_regs/mipi_tx_regs structs
* a3317182ff soc/mediatek/common: Move dsi0 definition to dsi_register_v*.h
* 3607024944 soc/mediatek: Move mtk_dsi_init declaration to display_dsi.h
* 7ef424c75e soc/mediatek/common: Rename mipi_tx to mipi_tx0
* cf0b91d774 soc/mediatek: Move dsi_regs/mipi_tx_regs definitions to soc/dsi_reg.h
* 403a42f1f0 soc/mediatek/mt8173: Fix mipi_tx1 address
* 72010408b5 mb/google/eve: Add CFR option menu support
* c36b149392 mb/google/eve/Makefile: Organize and group entries by stage
* f61ecfa154 mb/google/link: Add CFR option menu support
* 75460f531c mb/google/poppy: Add CFR option to enable/disable IPU cameras
* ae8f2d8cee mb/google/poppy: Add CFR option menu support
* 99d67bae63 mb/google/glados: Add CFR option menu support
* 0d81d38a31 mb/google/skyrim: Add CFR option menu support
* c397821cb6 mb/google/guybrush: Add CFR option menu support
* c1f0be39da mb/google/zork: Add CFR option menu support
* d105934073 mb/google/kahlee: Add CFR option menu support
* 46a32a2b56 mb/google/sarien: Add CFR option menu support
* e3bee6397d mb/google/rex: Add CFR option menu support
* d0345005ad mb/google/brox: Add CFR option menu support
* ee599486ac mb/google/dedede/galtic: Add CFR option for touchpad type
* 7a78543eca mb/google/dedede/drawcia: Add CFR option for touchscreen selection
* 1890c6d165 mb/google/dedede: Add CFR option menu support
* bd89858f09 mb/google/brya: Add CFR option menu support
* a58e0704c7 mb/google/volteer: Add CFR option menu support
* 8b34490137 mb/google/drallion: Add CFR option menu support
* 0762c7d6ee mb/google/drallion/Makefile: Organize and group entries by stage
* 89902e8c80 mb/google/hatch: Add CFR option menu support
* 0f93d154b2 mb/google/octopus: Add CFR option menu support
* f0346845cd mb/google/reef: Add CFR option menu support
* 2b959f4560 mb/google/puff: Add CFR option for automatic fan control
* a8a77f9da2 mb/google/fizz: Add CFR option for automatic fan control
* cde4280796 soc/intel/apollolake: Add CFR objects for existing options
* 2e10f75751 mb/google/sarien: Increase size of SMMSTORE to 512KB
* 91c6a0b5e6 mb/google/reef: Increase size of SMMSTORE to 512KB
* 36a345f99e mb/google/octopus: Increase size of SMMSTORE to 512KB
* d7cb2d2bc5 mb/google/drallion: Increase size of SMMSTORE to 512KB
* d32a372846 drivers/smmstore: Increase default size of store to 512KB
* c109fc92ff libpayload: Add API to get physical memory size
* 519332de10 mb/google/fatcat/var/ruby: Modify VCCCORE VR Fast Vmode ICC limit
* 7f93e2fe29 soc/intel/*: Add CFR option to enable/disable the Intel iGPU
* d5ea359347 soc/intel/**/cfr.h: Fix typo of "ACPI" in UI help text
* 02a2fe7907 Merge coreboot and libpayload <endian.h> into commonlib
* 5eb7b8bd34 payloads/external/edk2/Makefile: Set SMBIOS to 3.0.0
* c3afc13a0a soc/qualcomm/x1p42100: Update memlayout for BL31 region and realign TA region
* 04f83ff7dc cpu/x86/mtrr: Simplify MTRR solution calculation on AMD systems
* 6957f84aa7 soc/qualcomm/x1p42100: Define MDSS domain registers for display clock enablement
* 9a95aef482 soc/qualcomm/common: Add API to enable Lucidole PLL for X1P42100
* 5eaf85d19b soc/intel/skylake: Use CSE reset status for reset
* 84a4cdc6a5 soc/intel/*: Only skip PMC fallback on successful CSE reset
* 4f52ca6ba6 soc/intel/common/cse: Return usable error codes
* 8795680828 cpu/x86/lapic/lapic.c: Set spurious interrupt vector to 0xF
* 41348477e3 sb/intel/common/firmware/Makefile.mk: fix INTEL_IFD_SET_TOP_SWAP_BOOTBLOCK_SIZE
* c11faad2bf mb/google/skywalker: Correct MIPI panel power sequence
* 459cdd09f4 mb/google/rauru: Add variant-specific firmware config
* fee2befc82 3rdparty/blobs: Update to upstream main
* 626789b40a mb/siemens/mc_ehl{1..5}: Unify devicetrees SerialIoI2cPadsTermination
* 0513c45a38 mb/google/nissa/var/pujjoga: Generate RAM ID for MT62F1G32D2DS-031RF WT:C
* 4a5d0dee4a soc/mediatek/mt8189: Correct AUX LDO mask bit definition
* db01aa6cb2 commonlib/device_tree.c: Fix skipping NOP tokens
* 29bec62a22 cpu/x86/Kconfig: Remove SOC_SETS_MSRS option
* f4aeac4276 soc/amd/glinda: Set FSP UPDs from devicetree for USB4
* f68450e39b vendorcode/amd/fsp/glinda: Update FSP UPDs
* 244e8edf18 soc/amd/glinda/Kconfig: Add Faegan SoC as Glinda variant
* 9e5c7eb3f8 soc/amd/glinda: Add XGBE devices
* 87475d693a soc/amd/glinda: Remove set_resets_to_cold
* dcd4f07188 soc/amd/common/fsp: Fill in DIMM voltages
* 8929659d93 soc/amd/common/acpi/lpc.asl: Report ESPI1 fixed resource
* 3053cd2dad soc/amd/common/acpi/lpc.asl: Report fixed base addresses
* 7e1aa974bf soc/mediatek/common: Refactor mtk_ddp_mode_set to support dual DSI and DSC for MIPI
* 3aaeca8378 soc/mediatek/common: Refactor mtk_dsi_dphy_timing
* aeee9450a2 mb/google/ocelot/var/matsu: Add fw_config definitions with UFSC
* 67a7e06c38 drivers/tpm: Remove duplicated op
* ac5c57d24a drivers/tpm/ppi: Fix generated ACPI
* d922ad79c6 mb/google/fatcat/var/ruby: Add firmware configuration fields with UFSC
* 980c269643 mb/google/ocelot/var/ojal: Enable Audio Codec and update FW config
* 8e7975edfd mb/google/ocelot/var/ojal: enable CS42L43 driver options
* 9a6d1d4d69 mb/ocelot/var/ocicat: Modify ocicat Kconfig for bring up
* 94fe4c6926 mb/google/ocelot/var/kodkod: Add wake configuration to cnvi_bluetooth
* e3588d82bc mb/google/ocelot/var/kodkod: Enable CNVi Wi-Fi and BT cores
* 36edc2e371 soc/qualcomm/x1p42100: Add Dload mode detection and ramdump packing
* 26a18c674d acpi: Clear whole FACS table before filling it
* 5a6addca4b mb/google/fatcat/var/ruby: Change GPIO pins to fix audio function
* e6a8143d8b drivers/intel/touch: Add support for new Intel touch I2C _DSD entries
* 25c4501223 device/dram/ddr3: Fill in voltage fields for SMBIOS type 17
* 273a41c4d9 commonlib/memory_info: Introduce new fields to memory_info structure
* abe1ac0744 mb/google/brya/var/uldrenite: Add memory MT62F1G32D2DS-031RF WT:C
* 0599f3e1bd mb/google/bluey: Condition slow charging enablement on charger presence
* 8b3ceacd93 ec/google: Check AC charger presence by reading host event register
* 5b544c67eb mb/google/rauru: Add MIPI panel support with BOE NS130069-M00
* ed9239cd85 mb/google/nissa/var/gothrax: Add Samsung parts to RAM ID table
* 445961c604 soc/qualcomm/common: Add support for loading ramdump image
* 3c563669b5 soc/qualcomm/x1p42100: Add support for APDP image packing in CBFS
* 1d70286d4e soc/qualcomm/common: Add support for loading APDP image
* fc9f828ac0 mainboard/google/bluey: Select VBOOT_ALWAYS_ENABLE_DISPLAY
* c77d256886 {mb, security}: Use EC_REBOOT_FLAG_IMMEDIATE for cold reboots
* 1a0d123ec1 ec/google/chromeec: Update EC headers
* 3bd554feb2 soc/mediatek/mt8196: Align the struct for storing DRAM calibration data
* 33fc33c132 soc/amd/common/block/cpu/noncar: Add support for bootblock CRTM init
* 8b97968e53 soc/amd/common/block/pci/amd_pci_mmconf.c: Support 64bit ECAM MMCONF
* 7a98a62f7b drivers/intel/gma: Unify coding style
* 23b00a06da drivers/intel/gma: Fix brightness handling with valid-cache logic
* 4068ba39f8 soc/intel/common/block/rtc/rtc.c: Top Swap: add Slot B selection mechanism
* a65b874472 mb/dell: Convert OptiPlex 3050 into variant
* 2ce1068542 mb/google/ocelot/var/ojal: Decrease display count from 5 to 4
* b31e62ae5c mb/intel/ptlrvp: Add LPCAMM T3 RVP board support
* 58cdf9e668 soc/intel/pantherlake: Add LPCAMM memory support
* 67777b7671 soc/intel/common: Add LPCAMM memory topology support
* bb18e0b91d mb/google/skyrim: Increase size of SMMSTORE to 512KB
* dd1e54efc0 mb/google/zork: Increase size of SMMSTORE to 512KB
* 60e375fae4 mb/google/guybrush: Increase size of SMMSTORE to 512KB
* eb52862132 mb/google/brox/var/caboc: Update SSD port and FPMCU setting
* 85101704ae mb/ocelot/var/ocicat: Create ocicat variant
* 2975d7220a mb/google/ocelot/var/matsu: Update devicetree
* 0e9d85425e mb/google/ocelot/var/matsu: Fix GPP_V3 internal pull-up configuration
* 4f257a28f8 mb/google/ocelot: Add EC_GOOGLE_CHROMEEC_SKUID config
* db2ac42405 soc/mediatek/common: Refactor DDP mode setting
* d51f780515 mb/siemens/mc_rpl: Correct SMBIOS socket type to BGA1744
* 2f95552802 mb/siemens/mc_ehl: Move Kconfig switch to variants
* 3c49c13995 util/ifdtool: fix typo PSL->MSL
* a87e699f04 mb/lenovo/m900_tiny: Enable Vboot
* afc191357f 3rdparty/intel-microcode: Update to upstream main
* cbfa28b06e mb/google/fatcat/var/ruby: Modify power limit configuration
* f13e800a71 mb/amd/crater/Kconfig: Use A/B recovery scheme for renoir
* 416f67f670 vendorcode/amd/fsp/.../fsp_h_c99.h: Use fsp2_0 structs
* b94a84a792 drivers/efi: Exclude verstage from EFI variable store files
* bae5262c69 include/option: Add verstage stub for UEFI variable store backend
* 2d78478345 drivers/intel/gma: Reapply cached brightness once BCLM is valid
* 2ad08f9d72 drivers/intel/gma: Expose full brightness ladder
* 2e96a71e6f drivers/intel/gma: Cache brightness level
* 36632a08a8 soc/qualcomm/x1p42100: Reserve 33 MB DRAM memory for Display requirement
* 5807b59fc5 mb/google/rauru: Report panel ID for sapphire
* 49da58dccf drivers/mipi: Add support for BOE NS130069-M00 panel
* e9ebcb2918 mb/{google,intel}: Fix MIPI camera VCM type and address configuration
* 30b4383944 mb/{google,intel}: Set SSDB platform field for MIPI camera sensors
* 4c025191c7 drivers/intel/mipi_camera: Remove disable_ssdb_defaults option
* c75236d436 drivers/intel/mipi_camera: Set additional SSDB defaults
* 866b79c9fe drivers/intel/mipi_camera: Always generate PLD for camera sensors
* c6ed8c91fb drivers/intel/mipi_camera: Document more SSDB fields
* 423fbcd06b drivers/intel/mipi_camera: Adopt SSDB sensor SKU bitfield
* aa18a6fe8d drivers/intel/mipi_camera: Codify SSDB field enums
* f8d12a0bdb drivers/intel/mipi_camera: Add SSDB platform subtype enum
* 99cb6415ba drivers/intel/mipi_camera: Rename flash enum to match SSDB field
* c91ea7c582 drivers/intel/mipi_camera: Flesh out SSDB platform enum
* 0361e1a865 drivers/intel/mipi_camera: Verify SSDB struct size at build time
* b5d68e41a2 drivers/intel/mipi_camera: Tidy SSDB comment wrapping
* ab4c2fd0e8 drivers/intel/mipi_camera: Extract SSDB definitions into separate header
* d09ea1c351 cpu/intel: Add SMBIOS Socket BGA1744 type
* d97cb61b50 ec/google/chromeec: Add CFR option for RGB keyboard boot color
* e695731399 ec/google/chromeec: Add RGB keyboard helper functions and enum
* 4eb524ee9d spd/ddr4: Add three more parts
* e4a809d441 spd/ddr4: Double packageBusWidth of dual die package parts to 16
* 8753155f71 mb/google/slippy/var/peppy: Add CFR menu option for touchpad type
* 6f6a10df88 mb/google/slippy: Add CFR option menu support
* e366e0ba7d mb/google/slippy/Makefile: Organize and group entries by stage
* 6be83443e5 mb/google/auron/var/lulu: Add CFR option to enable/disable touchscreen
* 88d3f563b3 mb/google/auron: Add CFR option menu support
* 7ed515d1c3 mb/google/auron/Makefile: Organize and group entries by stage
* e15895b5c4 mb/google/poppy/var/nautilus/acpi: Fix CI02 comment
* 4dc03c54fc mb/google/poppy/var/nocturne: Hide FPR device in ACPI
* e85a0b7ff1 mb/google/puff: Remove unsupported EC features
* 3459502e0c mb/starlabs/starfighter: Enable pmc_shared_sram device
* 9b0af48604 mb/starlabs/starbook/mtl: Update GPIO config
* d3d4571411 soc/intel/common/block/graphics: Use Xeon W-11865MRE IGD PCI ID
* 1cfe413f95 soc/intel/common/block/lpc: Support RM590E eSPI
* c195859748 soc/amd: add ACPI code for I3C controller
* 02342b31df soc/amd/*/memmap.c: Report FCH MMIO regions as reserved
* 5078d32ccc mb/google/brya: Enable ACPI S3 sleep state support
* eb504eb49a mb/samsung/lumpy: Fix HDA pin configuration issues
* afd5e5d444 mb/samsung/lumpy: Convert HDA verbs to use AZALIA_PIN_DESC macros
* 109672a9a9 drivers/intel/gma: Guard legacy brightness fallback
* 908c2b54c6 mb/starlabs/starbook/mtl: Fix Card Reader USB Port
* 796d3b37aa mb/google/fatcat/var/moonstone: Update fw_config definitions with UFSC
* 2ce4e09469 drivers/intel/fsp2_0: Add typedef FSP_UPD_HEADER
* 7afe1e9f9d mb/google/fatcat/var/lapis: Adjust touchpanel power on timing
* 36f4341533 mb/starlabs/starfighter: Add Arrow Lake (285H) variant
* 80cf2008a9 spd/lp5: Add SPD for MT62F1G32D2DS-031RF WT:C
* f1d1c825dc mb/siemens/mc_rpl1: Enable IBECC
* 866a0591f7 mb/siemens/mc_rpl1: Set coreboot ready LED
* 801795d4dd mb/siemens/mc_ehl6: Alphabetize Kconfig options
* 1a11dca12d mb/siemens/mc_ehl6: Send POST codes to NC FPGA via PCI
* fceb033372 mb/siemens/mc_ehl6: Limit PCIe RP7 speed to Gen2
* 760c3f6abc mb/siemens/mc_ehl6: Activate SATA interface port 1
* 54f2652bde mb/siemens/mc_ehl6: Enable auto impedance calibration on GbE 0
* b6e7f3e005 mb/siemens/mc_ehl6: Change GbE LED settings
* aad2b715ea mb/siemens/mc_ehl6: Remove PSE GbE 1
* e19f2b313e mb/siemens/mc_ehl6: Enable PCHHOT_N via GPIO
* 43d5f70576 mb/siemens/mc_ehl6: Enable PTM for all enabled PCIe RPs
* 864e3ca661 mb/siemens/mc_ehl6: Adjust I2C setup
* 31f44f5521 mipi: Add DSC configuration and rate control parameters to panel header
* 743e31939c drivers/intel/fsp2_0/.../fsp/upd.h: Fix excess endif
* 2aadfc2b5e soc/amd/common/block/acpi: Add ACPI HEST table
* cc542c15f4 include/acpi: Move Error definitions/declarations into acpi_apei.h
* 2462e3a027 soc/mediatek/mt8188: Adjust memlayout for bootblock
* 804aab3abb mb/google/fatcat/var/ruby: Modify usb3 port setting
* fecf05c4f2 mb/google/trulo/var/kaladin: Mute speaker amp to prevent pop noise on reboot
* f35cb39de5 soc/amd/cezanne: Increase APOB DRAM size for Renoir
* 384e6e1c37 soc/amd/cezanne: Remove set_resets_to_cold
* 97291b5838 soc/amd/cezanne: Optionally propagate UART0 through ACPI
* 149d11d1d8 soc/amd/cezanne/Kconfig: Select Kconfig to program the PSP_ADDR MSR
* 520bc70b57 mb/amd/crater: Configure UART1 GPIOs
* 0ed1529ce3 src/vc/amd/fsp: fix type 17 DMI info
* e8599956dc mb/amd/crater: Make NVMe reset GPIO configurable
* 67bf203e52 mb/google/nissa/var/guren: Add missing settings for WWAN
* 3dabe4f857 mb/google/brox/var/caboc: Increase I2C0 touchpad tHD to 0.53 us
* 12e763eece device/pci_ids: Add DIDs for TGL-H (GT1 and RM590E)
* 01540f036e mb/google/fatcat/var/ruby: Use spd-11 for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV
* 14e96b4ef1 mb/google/brox/caboc: Mute speaker amp to prevent pop noise on reboot
* 567186a000 mb/google/bluey: Add support for off-mode charging
* 27fcb8617d commonlib: Add CBMEM ID to store boot mode
* d6132c4c03 mb/google/bluey: Use SOC PMIC API to detect off-mode charging event
* 201ebd48ee soc/qc/x1p42100: Add APIs to read PON reason from PMIC
* 293f3a7f5c soc/qc/spmi: Add API to read byte array
* 9f675eb96b soc/qc/common: Update SPMI_ADDR macro for better type safety
* cb1045a8b8 soc/intel/pantherlake: Update GT domain TDC value for PTL_TDC_1 SKU
* b0ee0c4620 soc/intel/pantherlake: Fix IA domain TDC value for PTL_TDC_2 SKU
* 6dbcf903a5 soc/intel/pantherlake: Add ICC Max and TDC settings for SKU_7
* 2148143ae9 soc/intel/pantherlake: Separate TDC configuration for different TDPs
* c7273c8ddc mb/google/fatcat/var/ruby: Add proto touch panel address
* 8575232317 mb/google/ruby: Migrate to UFSC
* 47101fc224 soc/amd/cezanne/Kconfig: Make AMDFW_CONFIG_FILE configurable
* c9f124a8fb mb/amd/crater/ec: Make macro ENABLE_M2_SSD1 a Kconfig option
* 430e34cd0f mb/amd/crater: Move gpio configuration to early_gpio
* 14b5c004f5 mb/amd/crater/ec: Create function to get board revision
* bd858faee8 mb/amd/crater: Add XGBE support
* f61553c9fa vc/amd/fsp/cezanne: Add Renoir FSP
* 87f8d15c87 ec/google/chromeec/cfr: Fix CFR callback signatures
* 7fb0f14ebe libpayload: arm64: Fix asynchronous exception routing in payload
* b584967d04 mb/google/ocelot: Add wake configuration to cnvi_bluetooth
* fc88b62174 mb/siemens/mc_ehl6: Enable PCIe root ports and clocks
* 5a4c749520 mb/siemens/mc_ehl6: Add new board variant based on mc_ehl2
* f5f304a5f3 mb/google/skywalker: Disable CHROMEOS_USE_EC_WATCHDOG_FLAG
* e4b0410946 soc/mediatek/mt8189: Enable MEDIATEK_WDT_RESET_BY_SW
* 1ae0cebff3 soc/mediatek: Add Kconfig option MEDIATEK_WDT_RESET_BY_SW
* 7d3bf767cc soc/mediatek/mt8189: Move WATCHDOG_TOMBSTONE from SRAM to SRAM_L2C
* a64dd410d8 mb/google/fatcat/var/ruby: Update EN_SPK_PA GPIO pin configuration
* 2f9b4ad6a5 soc/qualcomm/x1p42100: Add DFSR table configuration support
* 51e99de558 soc/intel/common/block/rtc/rtc.c: control Top Swap via CMOS option
* 56be23114e mb/google/rauru: Use chromeos-legacy.fmd for Hylia and Navi
* 10802bac16 spd/lp5: Modify SPD for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV
* e5d10e5d23 mb/lenovo/t480: Fix headphone jack
* 40b2a2b03c soc/mediatek/mt8196/booker: Refactor CMO property clearing with loop
* 1b0f9c5458 mb/google/nissa/var/telith: Add parade touchscreen support
* ddb3f0b17f drivers/hwid_dmi: Populate SMBIOS product name from CBFS hwid file
* 7a1e63308a acpigen_ps2_keybd: map insert
* 607740999d acpigen_ps2_keybd: map capslock
* a7efa40e39 acpigen_ps2_keybd: map KEY_HOMEPAGE to 0xaa scancode and TK_HOME
* fd603e5102 libpayload: Add CBMEM_ID_MEMINFO to sysinfo
* bae3e02662 include: commonlib: Move memory_info and dimm_info to commonlib
* d03799ec3c soc/mediatek/mt8196: Configure registers and parameters required for MTE
* 7521f3ea83 soc/qualcomm/x1p42100: Define pre and post-RAM DMA coherent regions
* d277b35307 soc/qualcomm/x1p42100: Relocate ddr_information and watchdog tombstone
* 958099b114 soc/qualcomm: Map the post-RAM DMA coherent buffer
* 931fa9c01d memlayout: Introduce PRERAM and POSTRAM DMA coherent regions
* af9d809823 soc/qualcomm/x1p42100: Move coreboot stack to SSRAM
* fec1032ee8 arch/arm64: Add timestamps for Secure OS (BL32) loading
* d0177bd102 soc/qualcomm: Add QCLib execution timestamps
* 0145ebe847 commonlib: Add timestamps for Qualcomm QCLib and ARM TFA
* cf2978f4b6 drivers/vpd: Search VPD info at 0x0 first
* a56a97d167 mb/starlabs/common/cfr: Adjust help text for S0IX
* 541fd14fd9 mb/google/nissa/var/uldren: Increase Touch IC enable delay time
* 0c18e7680a mb/google/fatcat/var/ruby: Remove GPP_D16 and GPP_D17 in fw_config.c
* 237944186e mb/google/nissa/pujjolo: update verb table
* cae53bea52 ec/google/chromeec: Add CFR options for keyboard backlight and fan control
* 1ca1dc6c31 ec/google/chromeec: Add ability to enable auto fan control via setup option
* 450389be05 ec/google/chromeec: Add fan presence helper function
* 9d355a39aa mb/amd/crater/ec.c: Enable power/reset for PCIe lanes
* 141fd11d79 mb/amd/crater: Rename ETH_AIC_SLOT_ONLY -> PCIE_DT_SLOT
* 1e28ff6955 src/mb/amd/crater/port_descriptors_renoir.c: Prettify code
* a48fd9ed7f soc/amd/cezanne: Add SOC_AMD_RENOIR as a Cezanne variant
* 760e19e18f mb/lenovo/sklkbl: Use spd_tools infrastructure for SPD binaries
* 8a83b86254 spd/ddr4: add parts
* 0ef4bd807c mb/google/ocelot/var/ocelot: Update DDR5 memory configs
* 7b11254d58 mb/google/ocelot/var/kodkod: Add overridetree
* aa1d44b644 mb/google/ocelot/var/kodkod: Update gpio settings
* a363007c3b ec/dell/mec5035: Route power button event to host
* 18dbeca5f4 util/autoport/azalia.go: Select CONFIG_AZALIA_USE_LEGACY_VERB_TABLE
* e9c47bf99e drivers/intel/fsp2_0: Add 1-bpp monochrome option for VGA mode 12
* f643141728 mb/google/fatcat: Option to enable monochrome VGA mode 12
* e05492cfb4 soc/intel/pantherlake/romstage: Configure VGA mode 12 monochrome buffer
* d3760cdfdf mb/google/bluey: Configure QUP0 SE5 as I2C
* abc87d533d mb/google/bluey: Introduce config to specify absence of USB-A port
* 872e06d60c mb/samsung/stumpy: inline fan thresholds and drop GNVS programming
* 8401bbd2ff mb/google/fatcat/var/ruby: Change touch panel address
* a4242e5c38 ec/starlabs/merlin: Fix get_ec_value_from_option() value validation
* 567470cbb3 payloads/edk2: Add iPXE EFI support for EDK2 payload
* f40de4e162 payloads/ipxe: Default enable serial output only if CONSOLE_SERIAL
* 962edb7e6d payloads/ipxe: Guard PXE_ROM_ID for non-EFI builds
* a907c6fb8d payloads/ipxe: Default to building from master branch
* 4081793ff2 payloads/external/edk2: Replace dependencies on EDK2_REPO_MRCHROMEBOX
* 10d606bfca soc/intel/common/acpi: Add P2SB write functions
* 7436c59875 util/amdtool: Add support for Phoenix AM5 CPUs
* 8f3626c4b5 util/amdtool: Add utility to dump useful information on AMD CPUs
* 3cf976e51a soc/mediatek/mt8196: Add dual display pipe path
* 14595d64de lib/edid_fill_fb: Add dual pipe flag to lb_framebuffer_flags
* 486b1b51af mb/google/bluey: Cache low battery mode check
* 33418b7e68 soc/qc/x1p42100: Disable compression for peripheral firmware binaries
* 5bfc2d23bb soc/qc/x1p42100:: Select Secure OS options in SoC Kconfig
* f5f943c1c3 bluey/kconfig: Consolidate SPI flash driver selection
* ee59936e83 commonlib/device_tree: Add an API to check if a DT is an overlay
* 0416ac9829 mb/google/var/fatcat/lapis: Modify type-A USB3 port0/1 tx_de_emp
* dfe553aebb util/intelvbttool/Makefile: Add install target
* 493e3d182e payloads/external/iPXE: Allow building EFI target
* 62fc93de90 soc/qualcomm/x1p42100: Add NVMe Power Loss Notification GPIO configuration
* 2b7b89ae31 soc/qualcomm/x1p42100: Update PCIE PHY init sequence
* 91594f4894 drivers/option/cfr.c: Replace memcpy() to avoid uninitialized object
* 04ea4724e2 Makefile.mk: separate bootblocks into BOOTBLOCK and TOPSWAP
* f164feba3e ifittool: allow adding files from a separate region
* 91073f37d7 mb/google/brya: Increase RW_SECTION_* by 256KB for 16MiB boards
* a43498e193 util/inteltool: Enable dumping GPIOs from Tiger Lake IoT PCH
* 04778ddd38 drivers/option/cfr: Remove old sm_object from constructor
* b535db8f1e soc/intel/cmn/usb: Add helper macro for USB 3.0 port TX configuration
* c197643d44 drivers/intel/gma/acpi: Add power management methods for GFX0
* 773997c92d drivers/intel/touch: Avoid returning undefined pointer
* 9dc35142ac soc/amd/stoneyridge: Generate SATA ACPI registers at runtime
* d62653749c payloads/libpayload: Support legacy LZ4 compression format
* 29faf77d4a mb/siemens/mc_rpl1: Limit CPU RP1 to PCIe Gen2 speed
* fad0908c5b soc/intel/alderlake: Make CPU RP PCIe speed configurable
* 04d5201426 treewide: Fix include guards
* 971f10d1d7 mb/google/var/fatcat/lapis: set custom SVID/SSID to load fw for CS35L56
* ace2e540d0 soc/intel/pantherlake: Update CONSOLE_UART_BASE_ADDRESS Kconfig value
* a65d9fe589 mb/google/fatcat: Remove FSP_UGOP_EARLY_SIGN_OF_LIFE from Lapis
* 729918628d 3rdparty/blobs: Update to upstream main
* d4bee96484 mb/lenovo/sklkbl: refactor memory_init_params to use gpio_base2_value()
* 2a9deabc35 commonlib/coreboot_tables.h: Fix lb_smmstorev2 alignment
* 0ba4505024 payloads/external/edk2/Makefile: Configure AP wakeup in UEFI payload
* 87c3373925 mb/google/fatcat: Add FW_CONFIG Support for TAS2563
* e08a35f806 drivers/sof: Add support for tas2563 speaker topology
* a3ea128ecf drivers/i2c/tas2563: Add driver for generating device in SSDT
* 240e17025c src/soc/intel/ptl: Add LPSS UART DMA control
* afa6c31ef5 soc/intel/alderlake/romstage/fsp_params.c: Refactor `pcie_rp_init()`
* ec5b5386d4 soc/intel/mtl/romstage/fsp_params.c: Refactor `pcie_rp_init()`
* 4c5c62bc8d mb/google/fatcat/var/ruby: Modify gpio pin for enabling audio function
* 2804a0d771 mb/google/fatcat/var/lapis: Update fw_config definitions with UFSC
* 0e1742a7e2 mb/google/bluey: Control slow battery charging via boot mode
* 113cef70fd soc/intel: Move USB port macros (2.0/3.0/TCSS) to IA common header
* 3c69295ce4 mb/google/fatcat/var/ruby: Add new supported memory part
* d18cc50e6a soc/intel/xeon_sp: Use common smm_relocate
* d0c936eea1 mb/google/nissa/var/guren: Tune SX9324 register for 5G LTE module
* 8851b5b0e7 soc/intel/pantherlake: Program HDA SVID/SSID
* c917ecf21e soc/intel/{adl,mtl}: Fix CLKSRC handling for compliance mode
* 312d455a93 soc/intel/{adl,mtl}/romstage/fsp_params.c: Fix printf specifier
* 786ac14d48 drivers/option/cfr: Add optional override table for default values
* ea84a29a27 mb/google/trulo/var/pujjoquince: Enable Bayhub LV2 driver
* 84e000b88e libpayload: arm64: Fix alignment for exception_state
* 9210f2fd1c mb/google/fatcat/var/lapis: add ILITEK touchscreen support
* b933a554ba mb/google/var/fatcat/lapis: Modify fw_config for audio and touch
* b3b7b7a027 mb/emulation/qemu-q35/Makefile.mk: Use all-y for memmap.c
* bb3e59051a mb/google/brya: Check power state before process _ON method for BT
* 0f7c54d7d1 mb/google/fatcat/var/felino: Disable card reader in coreboot
* 7946d2d65d mb/google/fatcat/var/felino: Add reset_gpio for SSD RTD3 configuration
* 8e2567c7a9 mb/google/fatcat/var/lapis: Adjust touchpad I2C frequency
* f8da2bf9b2 mb/google/fatcat/var/ruby: Modify camera enable gpio pin.
* 45163509cf util/cbfstool/cbfs-payload-linux.c: Remove TODO
* bdcd65bd7f ec/starlabs/merlin: Add battery capacity offsets
* 224ddb85e3 ec/starlabs/merlin: Choose a better default for GPE SCI
* 696344ac01 ec/starlabs/merlin: Optimise Kconfig defaults
* 649a6a591b ec/starlabs/merlin: Correct Kconfig dependancies
* 0d35c3fcc3 mb/starlabs/starbook: Fix inclusion of CPU RP ASPM option
* 87475ef37f mb/starlabs/common: Move power profile enum to common code
* 98e0ff1e4b mb/starlabs/*: Move DMIC disabling code to common dir
* 082ad480d9 mb/starlabs/*: Separate WiFi and Bluetooth controls
* abf630c96b mb/starlabs/byte_adl: Add wireless CFR object
* a58d99575e mb/starlabs/*: Move CFR object defs to common directory
* 74dcb4c679 mb/starlabs/common: Adjust the includes inline with coreboot
* 6b30e1f46b mb/google/dedede/var/pirika: Add support memory for CXMT CXDB5CBAM-MA-B
* d4e8af407c spd/lp4x: Add CXMT CXDB5CBAM-MA-B memory
* 8d7183a904 ec/google/chromeec: Add option to set keyboard backlight level at boot
* 973d0faf65 util/amdfwtool: Move needs_ish and combo_new_rab to data_parse.c
* 8449a15aed soc/qualcomm/x1p42100: Reduce USB OTG state enable timeout to 20ms
* f4af55a008 spd/lp5: Add SPD for MT62F1G32D2DS-020 WT:D and K3KL8L80EM-MGCV
* 9bea3130b5 mb/google/skywalker: Add AW88081 support for beep sound
* d8bcf242c6 Revert "commonlib/endian: Silence GCC -Warray-bounds false positives"
* 66039a61f1 Revert "commonlib/endian: Restore -Warray-bounds at the end of file"
* c27c9db51b mb/samsung/stumpy: Fix thermal configuration issues
* 288889cd98 mb/google/jecht: Fix thermal configuration issues
* 9fa2d55987 mb/google/beltino: Fix thermal configuration issues
* 76a48b5158 mb/google/beltino: Remove unused GNVS fan configuration
* 8cc8f219bf Documentation/drivers: Add ACPI five-level fan control documentation
* 47c4da36c4 util/amdfwtool/data_parse.c: Remove duplicate MP2_CFG_FILE
* fa23504c59 mb/siemens/mc_rpl: Alphabetize Kconfig options
* 8411fef90f mb/siemens/mc_rpl1: Switch from LPSS UART to legacy 8250 I/O UART
* 534fceb36a mb/siemens/mc_rpl1: Set PCI bridge function for NC_FPGA
* 8ce9255f82 mb/samsung/stumpy: Fix ACPI fan control FNP4 power resource
* f12f292d91 mb/google/intel/*: Fix ACPI fan control FNP4 power resource
* b9b95c917a mb/google/guado: Fix ACPI fan control FNP4 power resource
* 8a518b2134 mb/google/beltino: Fix ACPI fan control FNP4 power resource
* 6d751ef987 payloads/edk2: Drop EDK2_PCO_MMIO_EMMC Kconfig option
* 4423a0b390 payloads/edk2: Drop EDK2_UFS_ENABLE Kconfig option
* a86a5ebf7c payloads/edk2: Update default MrChromebox branch from 2502 to 2508
* 40a8466655 mb/google/fatcat: Add option to enable VGA mode 12
* 824992ddef soc/intel/pantherlake/romstage: Configure VGA mode 12 planar buffer
* 74113f5d5e drivers/intel/fsp2_0: Add options to config VGA mode 12
* 75318743c3 commonlib: Add pKVM DRNG related timestamps
* 2646eeffb2 mb/google/skywalker: Create variant Dooku
* 1b2675e4f2 soc/mediatek/mt8189: Require libbl31.a to exist
* 9c0a914192 libpayload: Fix printf edge cases for precision
* ebc2030ff7 soc/intel/pantherlake: Enable HW managed microphone privacy
* 4d9dacae16 mb/google/fatcat/var/ruby: Modify touchpad device setting to enable function
* 2821e8e2ae soc/intel/ptl: Remove redundant HAVE_BMP_LOGO_COMPRESS_LZMA Kconfig
* eadf2ee4a3 ec/starlabs/merlin/cfr: Replace integer literals with named constants
* 2bbc0f1ad3 mb/starlabs/starbook/{kbl,cml,tgl}: Control USB Bluetooth with wireless
* 2c9596555b mb/google/skyrim: Use edge (vs level) triggering for PS2K
* 0c3f304d5a mb/starlabs/byte_adl: Enable Wake On Lan
* ca5b51ef9c mb/google/bluey: Select QTEE firmware dependent Kconfig
* fe7b75d792 mb/google/fatcat/var/moonstone: Add fw_config touchscreen setting
* cfdaff3f70 commonlib/endian: Restore -Warray-bounds at the end of file
* 32ec29a51e mb/google/fatcat/var/kinmen: Disable RT721 clock stop support
* 4b50bc9e5f payloads/external/U-Boot/Makefile: Add custom repo and tag
* 3d41ac370d payloads/external/U-Boot/Makefile: Remove conditional
* c3b5c8723e ec/google/chromeec: Add function to determine keyboard backlight presence
* 7afd731849 ec/google/chromeec/acpi: Fix long battery string reporting for Windows
* bc475414c7 MAINTAINERS: Add Chen-Tsung Hsieh for MediaTek platforms
* 65dc0bdd7e mainboard/fatcat/lapis: Override PMC GPE configuration
* 4ea33e5ffa mb/google/fatcat/var/lapis: Enable THC HID over I2C mode
* 111da2557a mb/google/fatcat: Preserve VGPIO GPE for THC wake on touch
* e167e56883 mb/google/nissa/var/yavilla: Add stop pin for G2 touchscreen
* 1fa24898e2 soc/intel/common/block/pcie: Move speed helper to pcie_helpers.c
* 66f40a86de ec/starlabs/merlin: Move version offsets to ECDEFs
* 82367b8205 mb/google/ocelot/var/matsu: Add overridetree
* 05c0e16593 mb/google/ocelot/var/matsu: Update GPIO table
* 98c7be30ad mb/google/fatcat/var/moonstone: Support new schematic changes
* 5eafe672e3 vc/intel/fsp: Update WCL FSP headers to 3344_03
* 641eeca835 lib/vga_gfx: Fix left-up and right-up orientations
* a4f067c058 Makefile.mk: Align FMAP COREBOOT region to 4k boundary
* 410506b47c Makefile.mk: Print all FMAP region sizes in hexadecimal format
* c189604f43 mb/goog/ocelot/var/ocelot: Enable rp5 if PCIE WiFi detected
* 4a806a6865 ec/starlabs/merlin: Only show EC FW options for ITE EC
* 04d9a0d0f0 ec/starlabs/merlin/Kconfig: Fix typo in description/help text
* 1eda98a16e mb/siemens/mc_rpl1: Document CLKSRC 2 usage for PCIe RP5
* 1815a204b4 src/mainboard/lenovo: Add smbios_slot_desc, fix register types
* da204a92c1 vc/intel/fsp/wildcatlake: Expose PchHdaMicPrivacyMode
* 105598545e soc/intel/pantherlake: Update thermal design current parameters
* a5b51ab285 mb/google/rex/var/kanix: Add H58G66CK8BX147 to RAM ID table
* d7f427a7d2 util/xcompile: Fix compiler detection on newer Linux distros
* 82d90b1f21 Revert "mb/starlabs/*/rpl: Re-enable GpioOverride"
* 784d8f25f9 mb/google/fatcat/var/ruby: Enable panel touch function
* 56a8c40efa mb/starlabs/starlite_adl: Add missing ACPI entry for USB card reader
* 4047a44b68 sio/nuvoton/common/nuvoton.h: Add common Nuvoton SIO LDNs
* 3a1d6d5ded mb/google/brox/var/caboc: Adjust WWAN power off sequence
* b42f74122c Documentation/mb/lenovo: Adjust docs for Thinkpad T470s/T580
* 70e79f43b1 Haswell NRI: Print and fill in memory-related info
* 1730d05ec3 nb/intel/haswell: Factor out `report_memory_config()`
* 3bbfbd37e1 nb/intel/haswell: Factor out `setup_sdram_meminfo()`
* 3ffb01e9cb mb/siemens/mc_rpl1: Disable I2C1 and enable I2C6
* 4563db2807 mb/google/nissa/var/riven: Add H58G66CK8BX147 to RAM ID table
* a748e8b82b mb/google/fatcat/var/ruby: Enable touchpad function using I2C interface
* a92a2ee5d6 mb/starlabs/byte_adl: Expose fan control option in CFR
* bbb895436f mb/nissa/var/pujjoga: Add single ram configuration
* e2cf7f7dc7 soc/mediatek/common: Fix MMU assertion for framebuffer region
* a5ddfa963f mb/starlabs/starlite_adl: Increase ME region size to match IFD
* 7484a887b8 mb/google/ocelot: Fix EC sync IRQ configuration for board variants
* b1ed60b910 mb/google/fatcat/var/ruby: Disable FSP_UGOP_EARLY_SIGN_OF_LIFE temporarily
* fea1b2abbe mb/google/nissa/var/pujjocento: Adjust touch panel timing for stability
* 8f1c54685a drivers/mipi: Fix pixel clock and enable C-PHY for TM_TL121BVMS07_00C
* 979fdee1d9 soc/mediatek/mt8189: Support MIPI C-PHY interface
* 44635f328c soc/mediatek/common: Add C-PHY support for MIPI DSI
* c63e901b99 mipi: Add panel flags to support C-PHY interface
* 385ae6669b mb/gigabyte/ga-h77m-d3h/devicetree.cb: Re-enable IGD and PCIe VGA
* 2c6cf2c2a8 include/cper.h: Update CPER structures with __packed attribute
* d97644dd3f mb/asrock: Add Z77 Extreme4
* a73db6d451 mb/intel/ptlrvp: Add fw_config support for SPD selection
* 3ef1cf9f84 soc/amd/turin_poc: Add Turin SoC structure as a copy of genoa_poc
* 668d643e5c mb/lenovo/sklkbl_thinkpad: Add Lenovo Thinkpad T470s as a variant
* 8a6f9bf731 ec/google/chromeec: Update EC headers
* 745f1312aa include/cper.h: Update comments to UEFI spec version 2.10
* aab8ad98b6 mb/google/ocelot: Create kodkod variant
* 2279ba80e1 .gitignore: Add .clangd as a "Development friendly file"
* cd4af952e7 mb/google/ocelot/var/ocelot: Update DDR5 memory configs
* 1af54d9784 drivers/intel/touch: Change I2C speed type to i2c_speed enum
* 84a348f4bf ec/starlabs/merlin: Remove the fast charge option
* 1699d455e7 vc/intel/fsp: Update PTL FSP headers to FSP 3373_03
* b87a9795de tree: Use boolean for s3resume
* ec1068883f mb/google/nissa/var/guren: Add initial WWAN related settings
* 752d49a4ff mb/google/fatcat/var/moonstone: Disable RT721 clock stop support
* 155041ad4c soc/qualcomm/x1p42100: Add EUSB2 HS repeater support for USB Type-C
* 6e45016610 intel soc,southbridge: Add Kconfig to set TSBS in IFD during build
* f4271cad0a ifdtool: Add set top swap size PCH strap subcommand
* ab4b82fb3c util/lint: Add a license check exception for .gitkeep files
* 03524780ff soc/qualcomm/x1p42100: Support loading QTEE FW config files
* 50adb3f23c mb/google/bluey: Increase FW_MAIN_A/B slot size to 4.5MB
* bbdf2eab6a soc/mediatek: Rename DSI common files for improved readability
* 8a2c04e04d mb/starlabs/*/rpl: Re-enable GpioOverride
* 9ff9f2904b mb/google/bluey/var/quartz: Enable all spi flash drivers
* f6743fba29 mb/google/fatcat/var/moonstone: Enable Intel DPTF support
* fc736de10e ec/starlabs/merlin: Remove the EC_STARLABS_NEED_ITE_BIN option
* 3dee4cd0c0 soc/intel/pantherlake: Correct Touch Controller Speed Configuration
* 7376761bdf mb/nissa/var/pujjoquince: Modify fingerprint configuration
* 6ffbc9a929 soc/mediatek: Move mtk_dsi_reset() to mtk_dsi_common.c for reuse
* 668ea97075 commonlib/endian: Silence GCC -Warray-bounds false positives
* 4a3cc37cbd crossgcc: Upgrade binutils from version 2.44 to 2.45
* 35d4b3f2f4 arch/arm64: Support to load QTEE firmware in x1P42100
* e38056bef8 amdfwtool: Move ISH before PSP L2
* c1c83df3b5 mb/emulation/qemu-riscv: Enable ACPI by default
* 5daf497df4 arch/riscv: Add ACPI support for riscv
* 5c85793d26 mb/google/fatcat/var/lapis: Add cs42l43 and cs35l56 Soundwire links
* 14fc6c3469 crossgcc: Drop nds32le-elf toolchain from default builds
* fce489e9e5 drivers/intel/touch: Check SoC I2C speed function exists before calling
* 249883d5bf mb/starlabs/starlite_adl: Squash SB and non-SB board variants
* 80861a9f69 mb/starlabs/starlite_adl: Add CFR option for USB card reader
* 5c1a9fa809 mb/google/fatcat: Create ruby variant
* 43df7b14ae mb/var/uldrenite: Fix ISH UART port and VR configuration mismatch
* 1a0b7195f9 mb/google/nissa/var/glassway: Removed the flag of DB_1A for pmc_mux
* 9f0f373ff9 mainboard/amd/crater: Select the option to keep the AMD ACP active in S3
* f04c45acee mb/google/fatcat/var/lapis: enable CS35L56_FAMILY and CS42L43 driver options
* 78e7dcb152 drivers/soundwire/cs42l43: Add optional properties for controlling jack and accessory detect
* f1c973bbff drivers/soundwire/cs42l43: Support Cirrus Logic CS42L43 codec
* 35970abcdf mb/google/nissa/var/dirks: Add H58G56CK8BX146 to RAM ID table
* 402ac7cd81 crossgcc: Upgrade acpica from 20250404 to 20250807
* 3aa312e4c9 soc/mediatek/mt8189: Add DSI path support and update mutex
* 6b93516e02 soc/intel/baytrail/acpi: Add missing MMIO window below 4GB
* 321d8c5b21 soc/intel/braswell/acpi: Add missing MMIO window below 4GB
* 74d7a21382 nb/intel/haswell/acpi: Add missing MMIO window below 4GB
* 07f25bef86 mb/google/ocelot/var/ocelot: fix gpio settings
* 10b0697dc3 soc/intel/pantherlake: Update power limits and voltage regulator parameters
* 163e6a502c mb/starlabs/common: Deduplicate Pin Mix
* 7622a57771 mb/starlabs/common: Move the SMBIOS code to common directory
* e7dd184e5f Makefile.mk: Add support for mainboard vendor common code
* dd3d7dcdfa mb/purism/librem_skl: Add CFR option menu support
* 0d50fdf035 mb/purism/librem_l1um_v2: Add CFR option menu support
* e9a01dea32 mb/purism/librem_jsl: Add CFR option menu support
* 08efea5141 mb/purism/librem_cnl: Add CFR option menu support
* 1d02f139d3 mb/google/fatcat: Add wake configuration to cnvi_bluetooth
* cf97e1bc25 mb/intel/ptlrvp: Add power meter acpi changes
* 7e3883633a mb/google/brox/var/jubilant: Apply fw_config to enable/disable I2C1
* 114d24cd7a lib: Generalize BMP_LOGO help text
* e468e32dfb mb/google/*: Update Kconfig.name with actual device names
* 85d7a1c85f drivers/ipmi: add Block Transfer (BT) interface
* fe26234cf2 mb/google/trulo/var/uldrenite: Update DPTF parameters
* 660f71e704 mb/google/trulo/var/uldrenite: Set GPP_E16 to NC for non-WWAN SKU
* 3747b47df1 mb/lenovo/sklkbl_thinkpad: Add Lenovo Thinkpad T580 as a variant
* d23eaa356f util/lint: maintainers-syntax: Add a check to ensure paths exist
* 079c9c47aa soc/amd/cezanne: Add config option to keep ACP running in ACPI S3 state
* f665e189da mb/starlabs/{starbook/mtl,byte_adl}: Select USB4_PCIE_RESOURCES
* a7a49e5f74 mb/starlabs/starfighter: Correct reference for second TBT port
* f22bcc1d42 mb/starlabs/starbook/rpl: Disconnect unused GPIOs
* a8c70f7578 mb/starlabs/starbook/rpl: Reconfigure TBT GPIOs
* 83aa4417cb mb/starlabs/starbook/rpl: Tidy up GPIO config straps
* 7ad632cbc7 mb/starlabs/starbook/adl: Disconnect unused GPIOs
* d7627a39e8 mb/starlabs/starbook/adl: Tidy up GPIO config straps
* 711d49d4ec mb/starlabs/starbook/adl: Configure additional SSD GPIOs
* 90d87c5941 mb/starlabs/starbook/*: Remove comments for unused GPIOs
* f6b5e26fe7 soc/mediatek/mt8196: Add 24MB framebuffer region
* 815f3f7df2 mb/google/rauru: Increase RW firmware sections size to 1756KB
* 193420fe0b soc/mediatek/common: Add bootsplash support
* bdd4561536 soc/mediatek/mt8196: Add mtk_ddp_ovlsys_start for rendering framebuffer
* 0ff213d711 soc/mediatek/common: Conditionally set up framebuffer
* 5271ac7ac5 soc/qualcomm/x1p42100: Reserve DDR carveout region
* 19feafc018 drivers/intel/fsp2_0/ppi/mp_service_ppi: Support CPU_V2_EXTENDED_TOPOLOGY
* 16feb1bb28 mb/google/brya/var/nissa: Add missing device type to gfx device
* f4ecb69314 util/inteltool: Add Twin Lake UHD Graphics PCI IDs
* ed736a47d8 mb/starlabs/byte_adl: Configure additional SSD GPIOs
* 38525716d8 mb/starlabs/starbook/adl: Re-order the config strap GPIOs
* 2c465c0e21 mb/starlabs/starbook/adl: Re-order GPIOs to match other boards
* 115a6ce36a mb/starlabs/starbook/adl: Correct clock request number in comment
* 1b5aaaefd9 soc/intel/meteorlake: Fix IGD IRQ
* 06de11693f mb/starlabs/starfighter: Fix Thunderbolt disabling code
* 5e36d9ba04 mb/starlabs/starbook/mtl: Update the VBT from 256 to 261
* fba8c14c27 mb/google/brya: add cnvi BT recovery mechanism
* 1fb4a7409b soc/intel/pantherlake: Add VR power state current thresholds
* 59ede353c5 soc/intel/pantherlake: Add Thermal Design Current (TDC) configuration
* c54658d200 soc/intel/pantherlake: Add ICC Max configuration support
* 0d1545ffac soc/intel/pantherlake: Add hysteresis window UPDs support
* 8f24546fc4 vc/intel/fsp/fsp2_0/wildcatlake: Expose Thermal current thresholds and mode
* 04affc3354 mb/google/ocelot: Update gpio's for ALC721 sndw
* 3ac1a2b124 MAINTAINERS: Drop non-existant TPM files from VBOOT
* af8b15ae04 Revert "libpayload: Define UCHAR_MAX/CHAR_MIN/CHAR_MAX"
* 5e64ae2554 mb/starlabs/starbook/mtl: Enable PCH Energy
* 375847acfe soc/intel/meteorlake: Configure PmcPchLpmS0ixSubStateEnableMask
* db0faffdb8 mb/starlabs/*: Add comment about not configuring eSPI GPIOs
* 990ad929a0 mb/starlabs/starbook/tgl: Don't configure eSPI GPIOs
* 7ebcd6763f soc/qualcomm/x1p42100: Handle Type-C polarity for USB4/DP PHY init
* f1708cf21a drivers/intel/touch: Enhance Intel touch driver for new devices
* 55bf4ea07e cpu/x86/topology: Add tile and die ID CPU topology fields
* 0c97aed8ac mb/google/fatcat/var/lapis: Modify touchpad and touchpanel configuration
* 9e4a0a6026 mb/starlabs/starbook/mtl: Don't configure eSPI GPIOs
* 3e0457e087 security/vboot/Makefile.mk: Fix building vboot lib with OpenSIL
* 60ef877d93 mb/google/skywalker: Modify the RST pin naming
* d5a8cec748 soc/intel/meteorlake: Rely on FSP_DIMM_INFO
* e168a516e4 soc/intel/pantherlake: Rely on FSP_DIMM_INFO
* 23419df34c drivers/intel/fsp2_0: Implement API to retrieve DIMM info
* 1f328351e6 mb/starlabs/*: Select SPD_READ_BY_WORD
* 88439b4cd3 mb/starlabs/starbook/mtl: Set the VPU default to disabled
* 8ffa58723a soc/qualcomm/x1p42100: Add USB Type-C support
* 45cedbb992 soc/qualcomm/x1p42100: Add HS/SS PHY support for USB Type-C ports
* b18dfde22a soc/qualcomm/x1p42100: Add Clock support for USB Type-C ports
* c7e4ef822d mb/starlabs/{starbook,starfighter}: Remove DRIVER_TPM_SPI_CHIP
* 0c73e45493 ec/starlabs/merlin: Add disabled option for lid switch
* ac7bb7694d mb/starlabs/starbook/mtl: Configure eSPI GPIO Mux
* b37821ac25 mb/starlabs/*: Unify settings across device VBTs
* ac8765c88a mb/starlabs/*: Correct USB Type-C Port Configuration
* f7512c8647 mb/starlabs/starbook/{adl,rpl}: Remove USB OverCurrent Configuration
* bf67771656 mb/google/fatcat/var/lapis: Update gpio GPP_E07 configuration
* ff5daa0581 MAINTAINERS: Remove '/' from the beginning of paths
* 6bfa257eef MAINTAINERS: Correct the path of cbmem_id.h
* d7ae81132b MAINTAINERS: Correct asus/p8z77-series to asus/p8x7x-series
* ef8eb79636 MAINTAINERS: Rename util/ipqheader to util/qualcomm
* 0965bb9f68 MAINTAINERS: Remove non-existant mainboards
* f5d1505c6b mb/google/fatcat/var/moonstone: Add Elan touchpad support
* 24bfeb154e mb/google/fatcat/var/moonstone: Add focaltech touchscreen support
* 1580346fa7 mb/google/fatcat/var/moonstone: correct the Kconfig settting
* 150647a2fb ec/google/chromeec: Fix ACPI _CRS method generation for LPC memory range
* ffa262db59 Documentation/FIT: reference archived copy of Intel TXT lab handout
* f47e6c3905 MAINTAINERS: Fix typo "copperlake_sp" to "cooperlake_sp"
* 1af0497c12 mb/google/dedede: Fix MAINBOARD_FAMILY conditional
* b4b6c3aa55 mb/google/brya/var/{marasov,mithrax,omnigul}: Add SOF chip driver entries
* 738fd2efc9 util/chromeos/extract_blobs: Add support for command line params
* e59c5abd13 ec/google/chromeec: Add EC_GOOGLE_CHROMEEC_FW_CONFIG_FROM_UFSC
* 341b108a71 mb/starlabs/starfighter: Add missing GPP_A5 definition
* 414f1a61dd vc/intel/fsp/fsp2_0/pantherlake: Expose Thermal current thresholds and mode
* 2e92833172 soc/qualcomm/common/usb/qmpv4_usb_phy: Fix delay value in comment to 10 ms
* b48532c694 soc/mediatek: Refactor MMU configuration for DMA region
* 28a8eaa57b soc/mediatek/mt8192: Clean up memlayout.ld
* bca876849a soc/mediatek/common: Add enable parameter for configure_backlight
* 46ce812c1b mb/google/skywalker: Create variant Grogu
* 98a5445328 MAINTAINERS: Correct paths for Dell Latitude mainboards
* 984ee53de8 mb/asus/p8x7x-series: Introduce CFR setup menu
* 830ec89bca mb/google/bluey: Update mainboard part number for QuenbiH
* c2fcf69e41 arch/x86: Use boolean for flag_is_changeable_p()
* 2a791fcd66 mb/imb-1222/hda: Use AZALIA_PIN_CFG_NC() for disabled SPDIF_OUT2 pin
* 217a7962d0 ec/google/chromeec: Update EC headers
* 59cbb073c2 util/chromeos/crosfirmware.sh: Fix download of ninja (baytrail) recovery
* fba92daed3 soc/qualcomm/x1p42100: Clean up DDR and IMEM memory layout
* 5609174786 mb/google/rauru: Create variant Sapphire
* 386feb720e soc/mediatek/mt8196: Add DVFS support for the second SoC SKU
* 4b93b36170 mb/purism: add missing terminators to azalia codec tables
* a927d124be mb/asus: Replace verb tables with reworked implementation
* 9c0c925fe6 mb/siemens/mc_rpl1: Send POST codes to NC FPGA via PCI
* 10361583b3 mb/siemens/mc_rpl: Add code to wait for legacy devices before PCI scan
* d9979ba6a3 mb/siemens/mc_rpl: Sort includes alphabetically
* d9b609b139 nb/intel/haswell: Use boolean for cbmem_was_initted
* 1f2408f573 console: Fix flushing for slow consoles
* 6a016a784b Documentation: Finalize 25.09 release notes
* a0c5669c1b mb/asrock/imb-1222: Use macros for HDA verb table
* c94ca87d40 mb/google/fatcat/var/kinmen: Enable Intel DPTF support
* fe5f8494f6 docs/releases: Remove outdated "Upcoming release" in titles
* aef86a7e89 mb/google/ocelot/var/ocelot: disable HDA GPIOs by default
* 21f6ccf3a4 soc/intel/pantherlake: Use CPU ID mask for all stepping
* 8bc41fc937 mb/google/trulo/var/pujjocento: Update DTT settings for thermal control
* d5f1ecedf7 {device/azalia_codec,mainboard}: Use node ID enums for Realtek ALC887
* 02059c2250 mb/google/trulo/var/pujjoquince: Disable ISH gpio setting by fw_config
* 58459b8210 mb/var/uldrenite,orisa: Include the variant GPIO header
* 88ad238eca mb/google/skywalker: Fix incorrect GPIO_USB3_HUB_RST_L pull-down
* b8a8800152 mb/google/fatcat/var/lapis: Configure gpio of fingerprint sensor
* 4431848ee6 acpi: Move most of HEST ACPI table to common code
* ce1ced7f6a mb/intel/ptlrvp: Fix WIFI driver device settings under root port 4
* 691a23a272 mb/google/fatcat: Fix WIFI driver device settings under root port 4
* 16bf80b9b1 tests/imd: Fix invalid NULL comparison on uintptr_t
* 6d816b3b43 mb/asus/h610i-plus-d4: Add missing AZALIA_USE_LEGACY_VERB_TABLE
* 6f042c6ae4 lib: coreboot_tables: Fix grammar of *These information* in comment
* bcc7fce590 mb/topton/adl: Add TWL variant (X2E_N150)
* f634121fa4 mb/purism: Replace verb tables with reworked implementation
* 20d4042458 mb/asrock: Replace verb tables with reworked implementation
* 2b7dbf80c9 mb/apple: Replace verb tables with reworked implementation
* 970249694f mb/amd: Replace verb tables with reworked implementation
* 94beaa7ab3 mb/acer: Replace verb tables with reworked implementation
* f3db3a19d5 mb/51nb: Replace verb tables with reworked implementation
* bc92d9a666 nb/intel/haswell/minihd.c: Add reworked verb table implementation
* 69781b9806 soc/intel/broadwell/minihd.c: Add reworked verb table implementation
* 31fc5b06a6 device: Introduce reworked azalia verb table
* 50a59d4464 device: Add Kconfig to prepare for reworked verb table implementation
* a3e2073591 lib/vga_gfx: Add API to render text on a bitmap buffer
* ec2875e38f mb/google/ocelot/var/ojal: Enable FPS and update FW config
* beb0951c1c mb/google/ocelot/var/ojal: Update touchpad config
* bd933b641e mb/google/ocelot/var/ojal: Add overridetree
* 82a9e601bd mb/google/ocelot/var/ojal: Add initial GPIOs config
* 622c504a71 mb/emulation/qemu-riscv: Select DRIVERS_EMULATION_QEMU_FW_CFG
* ba3f529681 drivers/emulation/qemu: Adjust fw_cfg driver for Arm and RISCV
* c1e0384367 arch/riscv/include: Cast 'id' to int in OTHER_HLS()
* 67a3fb6abe mb/asus: Add PRIME H610i-PLUS D4 (Alderlake/LGA1700)
* 4f13f72dbc libpayload: Define UCHAR_MAX/CHAR_MIN/CHAR_MAX
* 7f8c442a09 soc/intel/meteorlake: Correct function naming
* 6d265ca31d device/pci_device: Fix typo in comments
* d4b6b55977 payloads/Kconfig: default to Skiboot payload on PPC64
* cb899b0c4d mb/google/brox/var/caboc: Update HDA verb table
* 15b903e1fd soc/intel/pantherlake: Add DDR5 memory type debug message
* a5252bd5b9 drivers/soundwire/cs35l56: Support Cirrus Logic CS35L56 Smart Amplifier Family
* 7d44128b2f mb/asus/p8z77-m_pro: Enable serial port A instead
* 894c8069fc superio/nuvoton: Add NCT5535D
* 69b0541375 sio/nuvoton/nct6779d: Add power loss resume support
* f61ffb68c9 soc/intel/pantherlake: Remove unused TxDqDqs retraining parameter
* 3a84c93b5b soc/intel/pantherlake: Correct function naming and code style
* 3b34079b19 mb/google/trulo/var/kaladin: Enable External bypass config2 settings
* 61488ffd57 mb/google/skywalker: Add CS35L51 support for beep sound for Padme
* 4a7d779ed0 soc/mediatek/mt8196: Set RTC EOSC calibration to 8 seconds
* 07df08836e Docs/releases: Update release notes for 25.09 release
* 8f52c0774e docs/security/vboot: Update supported board list
* 1f08b36f84 Documentation: Add coreboot release 25.12 template
* 02980f0ea6 soc/amd/common/block/psp: Add comments
* a17a41559a soc/amd/common/block/psp: Add BIOS SPI flash semaphore
* 038262155e soc/amd/common/block/psp/psp_smi_flash: Fix flash busy check
* 67e3579d61 sb/intel/lynxpoint: Enable PCIe Relaxed Order
* 865649edc0 util/docker/jenkins-node: Use the correct branch for encapsulate
* 6af7d299b2 mb/google/skywalker: Add MIPI panel support with TM_TL121BVMS07_00C
* 4fc5f7a843 mb/google/fatcat/var/lapis: Modify the gpio order of mem_id
* 2764a508ad mb/google/fatcat/var/lapis: Add 4 DDR modules to RAM id table
* 886bd1d186 spd/lp5: Add Samsung K3KLALA0EM-MGCU memory part
* 0a6f3e3868 mb/google/brox/var/caboc: Add PDC FW hash to hint romstage init
* cbd1529126 mb/google/brox: Update Auxiliary Firmware Version check
* 0d4c0ee7fc ec/google/chromeec: Add API for AP shutdown command
* bbd72abae5 ec/google/chromeec: Update EC headers
* 21ca3c5f3d mb/intel/ptlrvp: Update CKD/QCK mapping parameters
* 3d7b898ff4 mb/google/ocelot/var/ocelot: Disable ALC721 clock stop support
* c822148f2b mb/google/fatcat/var/lapis: Modify dq/dqs setting
* 78fb910fe2 mb/google/fatcat/var/lapis: Update the configuration of fw_config
* eb3497fae4 mb/google/fatcat/var/lapis: Update tpm i2c configuration
* 3a33217349 mb/google/fatcat/var/lapis: Update thermal strategy
* 36d2dc7cb9 mb/google/ocelot: Update wake event mapping for gspi0
* 59bd0e3206 mb/google/ocelot/var/ocelot: Update USB and TCSS port configuration
* c4627e0dda mb/google/ocelot: Remove FP_PRESENT probe from ISH device configuration
* 8e9ec16f45 mb/google/trulo/var/pujjolo: Add tablet mode fw config for ish fw
* e3a2d1cecf soc/qualcomm/qclib: Improve logging on invalid MRC cache data
* 289c01e6fb mb/google/ocelot: implement variant_memory_sku()
* fbb68982c9 mainboard/google/ocelot: Update PCIe root port for SD card interface
* c98155cbcd soc/intel/pantherlake: Generate TME keys only if TME is enabled
* d8ed977358 mb/google/skywalker: Remove space before tabs in gpio.h
* 1e7908fa9f mb/google/skywalker: Set up all output GPIOs
* 14e6c62c10 mb/google/skywalker: Define all GPIO pins
* 2859a5cba5 mb/{google,intel}/{fatcat,ptlrvp}: Prevent access to disconnected camera
* ffae0f7d73 security/vboot: Extend CROS_EC_HASH_TIMEOUT_MS
* d2345e0c60 mb/google/fatcat: Set `SkipExtGfxScan` FSP-M UPD
* 8953c772cf lib: Fix bad whitespace in add_bmp_logo_file_to_cbfs_call
* ef0c650edf soc/intel/cmn/blk/fast_spi: Cancel DMA transfer before locking
* b3ad2aa3e7 mb/google/ocelot: GPIO config for headphone jack detection
* 508c399bc1 mb/goog/ocelot/var/ocelot: add H58G66CK8BX147 memory option
* d8a3f2aedd mb/goog/ocelot/var/ocelot: add H58GE6AK8BX104 memory option
* f4110cebf6 spd/lp5: Add SPD for H58GE6AK8BX104
* 7acc99c3d2 acpi/acpi_pm: Fix compilation without SMBIOS
* c77d3d67cf mb/google/skywalker: Report panel ID and SKU ID for padme
* 6185983028 soc/intel/pantherlake: Standardize macros for core count and SKUs
* 9a8402adf9 mb/google/trulo/var/kaladin: Update HDA verb table
* 9af9e1d1f4 mb/google/trulo/var/kaladin: Add eMMC DLL settings
* 3b4c446fbb mb/google/bluey: Configure QUP0 SE1 as I2C
* ddf5987c1e drivers/mipi: Add support for TM_TL121BVMS07_00C panel
* 0fec287327 mb/google/nissa/var/dirks: Drive GPIO GPP_D2 high to fix noise issue
* 5a9ca2b040 mb/starlabs/starbook/mtl: Set SPD size to 512
* 79119456a2 soc/amd/common/block/iommu: Add missing newline to debug print
* 81bb2663b7 soc/qualcomm/x1p42100: Select HAVE_CBFS_FILE_OPTION_BACKEND
* bf83dd9927 soc/qualcomm/common/qclib: Introduce runtime debug log level control
* cf3af46e50 mb/google/skywalker: Create variant Padme
* 2b1809e026 mb/google/fatcat: Increase Fast VMode I_TRIP threshold to 63A
* 2a7a0e86cd mb/google/fatcat: Configure Acoustic noise mitigation
* 6c06602c75 mb/google/brya/var/uldrenite: Add fw_config probe for touchpad
* a3b73464b5 soc/qualcomm/x1p42100/usb: Fix code comments and debug messages
* e924021e69 mb/google/trulo/var/kaladin: Add GTH1563 and GTH7503
* d1967d927a spd/lp5: Add SPD for MT62F1G32D2DS-031 WT:C and MT62F2G32D4DS-031 WT:C
* 2e10ddb1ee mb/starlabs/starbook/mtl: Make TCSS notify the IGD of changes
* 47fb46e0e4 vc/intel/fsp/mtl: Update the headers to 5124_47 (13.0.228.64)
* bb760bc9f3 Kconfig: Introduce HAVE_CBFS_FILE_OPTION_BACKEND
* f1b83c8759 mb/google/rex/var/kanix: Add K3KL8L80EM-MGCU to RAM ID table
* bcb3263078 mb/goog/ocelot/var/ocelot: add H58G66BK8BX067 memory option
* 751afeb060 mb/google/brox/var/caboc: Update HDA verb table
* 56700713de mb/google/trulo/var/kaladin: Disable eMMC GPIOs via firmware config
* 93c147c5e6 commonlib/device_tree: Add dt_add_iommu_addr_prop function
* d3d2f0f1c8 mb/google/fatcat/var/moonstone: Add to support ALC1320 Smart Amp
* 1da045f6a5 mb/google/skywalker: Add API support for regulator VCN18
* fe70426dd7 soc/mediatek/common: Add support for regulator VCN18
* f4a123f055 tests: Allow specifying using system Cmocka or building from source
* e7d598ba2c Reland "tests: Allow specifying vboot source directory"
* a348ef46db mb/google/trulo/var/pujjolo: Change setting for lite ISH fw
* 16db59ccef mb/google/rex/var/karis: Add K3KL8L80EM-MGCU to RAM ID table
* 3639648f81 mb/google/fatcat/var/felino: Set GPP_A15 and GPP_B23 as not used
* 8585591596 mb/google/fatcat/var/lapis: Set GPP_A15 as not used
* b9af91dfe1 mb/starlabs/starlite_adl: Drop HDMI entries from verb table
* 461c6a7d31 mb/starlabs/starfighter/rpl: Drop HDMI entries from verb table
* fc3a647579 mb/starlabs/starbook/rpl: Drop HDMI entries from verb table
* a88d9e1033 mb/starlabs/starbook/mtl: Drop HDMI entries from verb table
* 90f94287fd mb/starlabs/starbook/adl_n: Drop HDMI entries from verb table
* 684530ebdc mb/starlabs/starbook/adl: Drop HDMI entries from verb table
* 258da6b1ef mb/goog/ocelot/var/ocelot: add H58G66BK7BX067 memory option
* 883103c77f mb/google/ocelot: Disable memory training progress bar
* f3a49c8b3d mb/google/ocelot/var/ocelot: Disable audio for invalid Audio FW_CONFIG
* be3148575e mainboard/google/ocelot: Set OEM footer logo bottom margin
* 092fca3210 mb/google/fatcat/var/kinmen: Add support ALC1320 Smart Amp
* 4ba1b615db mb/starlabs/starlite_adl: Use macros for HDA verb table
* ca8d6a7512 mb/starlabs/starfighter/rpl: Use macros for HDA verb table
* c30163dace mb/starlabs/starbook/tgl: Use macros for HDA verb table
* 15111ebb21 mb/starlabs/starbook/rpl: Use macros for HDA verb table
* 6d6a280ab2 mb/starlabs/starbook/mtl: Use macros for HDA verb table
* 543f6c2a52 mb/starlabs/starbook/kbl: Use macros for HDA verb table
* 6d7c8f5477 mb/starlabs/starbook/cml: Use macros for HDA verb table
* 515f566840 mb/starlabs/starbook/adl_n: Use macros for HDA verb table
* 4b61d4de5f mb/starlabs/starbook/adl: Use macros for HDA verb table
* 8bc0eddf15 soc/intel/pantherlake: Add support for a new Panther Lake B0 SKU
* 2b84d26f55 payloads/edk2: configure capsule updates
* f3211e9639 soc/intel/pantherlake: Add support for Acoustic Noise Mitigation UPDs
* 2c03fd06a9 mb/google/trulo/var/kaladin: Disable ISH via firmware config
* f8574f7145 soc/intel/ptl: Add Wildcat Lake SKU power map
* b1fe32dd9e mb/{intel,google}/{fatcat,ptlrvp}: Update GPP_A15 GPIO configuration
* 6074ca18d3 mb/google/ocelot: Create matsu variant
* 76e0f64035 mb/google/brya: Update GPIO_PCH_WP for trulo variants
* b69e66721d mb/google/brya: Update GPIO_PCH_WP configuration in trulo baseboard
* 17c623277b mb/google/trulo/var/pujjolo: Change stylus settings
* 7f74155aa4 mb/google/trulo/var/uldrenite: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
* f373faa9c8 mb/google/trulo/var/uldrenite: Add fw_config probe for storage
* a262cdbc27 mb/intel/ptlrvp: Add wake configuration to cnvi_bluetooth
* 1c0186f280 soc/intel/common/block/cnvi: Add CNVi chip configuration support
* bdbe8b9b6f util/kconfig: Fix xconfig
* 241b940ac7 mb/google/nissa/var/rull: add RAM ID H58G56CK8BX146
* 599d660c4b mb/google/fatcat: Enable support for Realtek EC
* 89a3ae3d80 mb/google/trulo/var/pujjolo: Update GPP_D15 setting
* b849c9daa1 3rdparty/qc_blobs: Update submodule to upstream main
* 8159b2e06c device/azalia_codec: Add header with enums for Realtek node IDs
* 18ae0c48e1 mb/google/fatcat/var/moonstone: Support new schematic changes
* c1f76dd87e mb/google/brya/var/dochi: Add H58G56CK8BX146 to RAM ID table
* 164b4a1d90 mb/google/nissa/var/craask: Add parade touchscreen support
* 492826771e mb/google/bluey: Enable USB support
* 96eb6a3ac1 soc/qualcomm/x1p42100: Add USB Type-A Host support
* 2908a955e5 mb/google/rex/var/kanix: Add H58G56CK8BX146 to RAM ID table
* 7fc414c886 mb/google/trulo/var/kaladin: Enable EC keyboard backlight
* 859cc31e3a mb/google/brox/jubilant: Generate RAM IDs
* a6c15129a7 mb/google/fatcat/var/moonstone: Generate SPD ID for memory module
* 1028f3e846 soc/intel/pantherlake: Add Bluetooth to PME wake source mapping
* 3f926bc110 commonlib/bsd: Add Bluetooth wake source in ELOG event data
* 84ec1493a3 drivers/wifi/generic: Fix typo in header guard comment
* 2e2490256f soc/qualcomm/x1p42100: Add USB clock support for X1P42100
* 159afbc5d5 lib/lzmadecode: Increase decoding speed by 30%
* 0b8ad35ac1 mb/starlabs/byte_adl: Adjust the VBT
* d3cea61907 mb/starlabs/starlite_adl: Adjust the VBT
* 3507992d1d mb/starlabs/starbook/adl_n: Adjust the VBT
* 05cd5a7ab9 mb/google/nissa/var/telith: Generate RAM IDs for telith
* a0bdf3961c soc/qualcomm/common: Add clock reset function support
* cf11722e68 soc/mediatek/mt8189: Enable tracker debug hardware
* 382a7caff3 soc/mediatek/mt8196: Refactor tracker driver to support new platform
* 97f9ebb5c2 mb/google/ocelot: Create ojal variant
* ef1d48ee1d util/lint: Don't check for Kconfig.name in common directory
* 5cb36eb16c util/lint: Don't check for board_info.txt in common directory
* 46b03e682c util/amdfwtool: Handle address mode properly for Turin
* 97cf4a1919 util/amdfwtool/amdfwread: fix offset decision for PSP/BIOS directory lookup
* 73dd7bb046 util/amdfwtool/amdfwread: add initial parsing for EFW structure
* d4da533473 smbios.h: Update smbios_memory_type
* 183589dcbd smbios.h: Update smbios_memory_form_factor
* 58726e58e4 mb/starlabs/starbook/mtl: Adjust the VBT to fix hot plug
* 80df8c336f mb/intel/ptlrvp: Update Kconfig for ptlrvp_chromeec4s and ptlrvp4es support
* ed59c1de34 soc/qualcomm/x1p42100: Update TF-A memory reservation
* 56dbafcff4 soc/intel/pantherlake: Remove UFS support
* 5b46caef93 mainboard/intel/ptlrvp: Remove UFS support
* 621633af9b mainboard/google/fatcat: Remove UFS support
* 5e2f5050ba mb/starlabs/starbook/kbl: Update HDA verb table
* 4626c053dd mb/starlabs/starbook/adl_n: Update HDA verb table
* 6f11c31354 mb/starlabs/starbook/mtl: Update HDA verb table
* b748a5e10b mb/starlabs/{starbook,starfighter}/rpl: Disable GPIO override
* 29ca9c8bfa mb/google/bluey: Disable charging during normal boot
* e82338b0a2 mb/google/bluey: Add boot mode to coreboot tables
* 893a2b008a libpayload: Add coreboot boot mode table
* a45c8441af lib: Add boot mode information to coreboot tables
* c73f30e74b mb/google/nissa/var/riven: Add H58G56CK8BX146 to RAM ID table
* 8c717df03a soc/intel/ptl: Update Wildcat Lake PCIe root port numbering
* afaef0b904 mainboard/google/ocelot: Update GPIO configuration for SLP_S0_GATE
* 97dbfd3098 cpu/intel/car/non-evict: Improve CAR setup
* cd48dc7d69 mb/google/rex/var/karis: Add H58G66CK8BX147 to RAM ID table
* ffbf40f6c0 ec/google/chromeec: Update EC headers
* 517185eca2 mb/google/bluey: Configure touchpad power GPIO
* baf159a1c8 mb/google/bluey: Configure GSC and EC for Quartz
* f8685bb2ee soc/mediatek/mt8189: Enable lastbus debug hardware
* 6e61ea65a8 mb/google/bluey: Add disable slow charging support
* 45d1f9cce4 mb/google/bluey: Move charging functions to dedicated file
* 9fb306f53c soc/qualcomm/x1p42100: Add SPMI driver to ramstage
* ac5bb861d8 mb/google/brya/var/uldrenite: Update HDA verb table
* f2d3051631 ec/lenovo/h8: Turn on PWR LED
* d8de1c4974 ec/lenovo/h8: Disable POST codes
* d5a92542aa mb/google/fatcat/var/fatcat: Disable ALC721 & ALC722 clock stop support
* 3b2962929b lib/timestamp: Init TSC frequency early on x86
* b0a63052b7 sb/intel/bd82x6x: Fix CPU replaced check
* 9ecf04c2bc mb/google/nissa/var/quandiso: Generate RAM ID for MT62F512M32D1DS-023 WT:E
* 16318a32ce spd/lp5x: Generate initial SPD for MT62F512M32D1DS-023 WT:E
* 283c25beec mb/google/trulo/var/kaladin: Select Strauss keyboard to show G icon
* 2709ae443b cpu/x86/entry16.S: Move reset vector to this file
* 53810448fc cpu/x86/reset16.S: Remove handcoded reset vector
* a1b7f5e1b8 mb/siemens/mc_rpl: Disable EIST to improve deterministic behavior
* e6f8900c2d mb/siemens/mc_rpl: Disable S0ix power states
* c71071397f soc/intel/common/fast_spi: Add static bus scanning
* e73b4579c6 mb/siemens/mc_rpl: Disable DPTF
* 77061d8427 mb/google/bluey: Add Quartz board (Qualcomm Hamoa)
* ee1446a791 mainboard/emulation/qemu-q35: Do not compile memmap into SMM
* a7b6590aca  mb/google/dedede/var/dexi: Add and use VBT
* 70ce81c86f mb/google/dedede/var/dita: Add and use VBT
* 87f5d4c54a tree: use boolean for PcieRpLtrEnable[]
* 725ab7b066 soc/mediatek/common: Increase WAIT_AUX_READY_TIME_MS
* f02e755364 config/builder/mitac: Hook up public FSP repo and microcode
* fc62ffab48 soc/amd/common/fsp/dmi: Skip parsing when memory type UNKNOWN
* c3071b7150 soc/amd/cezanne/fsp_m_params: add UPD pointer parameter to mb callback
* eb9a673a8e soc/amd/cezanne: Add a Kconfig option for SERIRQ_CONTINUOUS_MODE
* c590e8e75c mb/brya/var/uldrenite: Increase Touch IC enable delay time
* 9996fc58fd mb/siemens/mc_rpl: Disable C1E state via MSR_POWER_CTL
* c58c988b8e mb/siemens/mc_rpl: Remove unused code and power limit functionality
* 8e5e87a1cf mb/siemens/mc_rpl1: Configure CPU power limits to 28W TDP
* 4853f16a59 mb/google/fatcat/var/kinmen: Support new schematic changes
* 9d67120078 mb/google/moonstone: Create moonstone variant
* 00d954977c util/smmstoretool: Support other block sizes
* 4fd3cb35c2 util/cbmem: Change abort() to exit(1) in die()
* 62b6d1e336 mb/siemens/mc_rpl: Enable master bit in PCI config space if allowed
* a8bce33b82 mb/siemens/mc_rpl: Disable Intel Turbo Boost
* 1a9008b261 device/azalia: Use clrsetbits32() and friends
* cbf8527345 device/azalia: Amend the mistake of codec_is_operative()
* 0a328282ec device/azalia: Add enums for HDA verb and parameter IDs
* c15006eb0c soc/intel/alderlake: Add 28W TDP support for RPL-P ID 8 (0xa716)
* d7a996cf44 mb/siemens/mc_rpl1: Enable 4 P-Cores, disable E-Cores
* 2f9273f1f4 mb/siemens/mc_rpl: Select FSP_TYPE_IOT
* 1b14664311 mb/siemens/mc_rpl: Remove unused DPTF settings
* 66a3f2a1b1 mb/siemens/mc_rpl: Disable SaGv
* 993a9c9e14 mb/siemens/mc_rpl1: Configure SATA Ports
* e03f50bf5f mb/siemens/mc_rpl: Enable Siemens NC_FPGA driver
* 699c28c01d sb/intel/bd82x6x: Fix replay issues
* c2110e3161 tree: Use true, false for PcieRpClkReqSupport
* ebab858d92 soc/intel/pantherlake: Enable memory bandwidth compression for IGD
* ad10d4a977 soc/intel/cmn/blk/graphics: Reserve memory compression region
* 8a52418e9a commonlib/device_tree: Fix memory leak in fdt_unflatten()
* 7896f4950c mb/google/skywalker: Turn off UFS power for eMMC SKUs
* 22fe08c04b soc/mediatek/mt8189: Implement UFS power-off API for non-UFS SKUs
* 5f0225a7b5 drivers/intel/fsp2_0: Refactor for earlier graphics memory WC MTRR
* 1c571446ec soc/intel/common/block/systemagent: Increase MTRR region size to 32 MiB
* 67afbf5f96 soc/intel/pantherlake: Add TDP mappings for Panther Lake-U SKUs
* ec69479bdb mb/google/ocelot: Drop redundant SNDW GPIO mapping
* 5f168e9441 mb/google/ocelot/var/ocelot: Conditionally init ALC256 HDA using fw_config
* 152b584167 mb/goog/ocelot/var/ocelot: Add AUDIO_MAX98360_ALC5682I_I2S
* 8f2633cd60 soc/power9/rom_media.c: find CBFS in PNOR
* 44ec090551 ppc64: Kconfig switch for bootblock in SEEPROM, zero HRMOR
* 921027e09b src/lib/cbmem_common: Delete a space(' ') in the source code
* acb86babdf mb/protectli/vault_kbl/mainboard.c: bring back the beep
* 76d45a8219 soc/amd/genoa_poc/root_complex.c: Explain the order of IOHCs
* 8dcfa915f2 soc/amd/common/block/psp: Probe SPI flash early
* 00217275b2 soc/amd/common/block: Don't clobber SPI registers
* c13eadeadb soc/amd/common/block/psp/psp_smi_flash: Fix busy check
* fbcf031181 mb/qemu-riscv: set PCI_IOBASE
* bf0ee592f5 soc/intel/alderlake: Make SATA speed limit configurable
* 482a2d6548 nb/intel/sandybridge/northbridge.c: Disable non-active PEG devices
* 7e73d4ef30 Documentation: mb/erying/tgl: Update documentation
* 73cba1fdea mb/erying/tgl: Introduce CFR
* 23cf7c64f9 mb/erying/tgl: Use booleans in devicetree
* 261b6b4fd1 soc/intel/skylake: Allow generating USB ACPI code
* 23e92a5ac0 mb/erying/tgl: Map remaining USB ports
* 762a535551 mb/erying/tgl: Clean up the GPIO table
* 179b8444c3 soc/intel/xeon-sp/gnr: Hook up public FSP bin and headers
* 42ba7a9e48 soc/intel/xeon_sp/gnr: Add Kconfig symbols for SKUs GNR-AP and GNR-SP
* c732f406c7 mb/google/ocelot: ec.h: Disable sync IRQ, sync IRQ wake capable for OCELOT4ES
* 73961bf680 mb/google/ocelot: Use same mainboard part number for all ocelot variants
* 691d5e84cd mainboard/google/oceot: Drop redundant logo_valignment selection
* b67d88aecb mb/google/bluey: Enable PMIC based slow charging in romstage
* dcb7c317c2 mb/siemens/mc_rpl1: Enable Intel I210 MACPHY driver
* 2b26ea0eda mb/siemens/mc_rpl1: Configure SPI and implement TPM support
* 2bcd7f1522 mb/siemens/mc_rpl1: Adjust UART settings and enable LPSS UART
* 524fd18bd6 mb/siemens/mc_rpl1: Create variant specific Kconfig file
* c7cd4e3305 mb/siemens/mc_rpl: Move SOC selection to baseboard
* 6427e51c4f mb/siemens/mc_rpl1: Adjust USB port settings in devicetree
* 71c4619045 mb/siemens/mc_rpl: Remove unused devices from devicetree and Kconfig
* 296f5968d3 mb/siemens/mc_rpl1: Adjust I2C bus enablement in devicetree
* a1dd6bfc22 mb/siemens/mc_rpl1: Adjust PCIe settings in devicetree
* f94469c2a9 mb/google/nissa/var/pujjolo/pujjoquince: Add wifi sar table
* 6781f458ee mb/google/trulo/var/pujjolo: Enable fivr settings
* 17a88540fd soc/qualcomm/x1p42100: Use SPMI driver
* c1128ae649 soc/qualcomm/cmn: Add SPMI driver
* 0eebd5596b mb/google/fatcat: Create lapis variant
* 4931b978d9 soc/mediatek: Increase CBFS cache to 8MB in memlayout.ld
* 234eb53ed9 nb/intel/sandybridge/raminit: Speed up reading SPD EEPROMs
* 7d57333529 ec/starlabs/merlin: Add a "off" mode for the power LED
* 36624072a6 mb/google/trulo/var/pujjolo: Update wlan rtd3 settings
* 42a5c189b2 mb/lenovo/X220: Add CFR support
* 8509798006 sb/intel/common/smbus: Use proper delay instruction
* 5f7b5fcb19 mb/starlabs/byte: Lower the PL4 value to 65W
* 4a6a0de029 3rdparty/fsp: Update to upstream master
* de98da43fa 3rdparty/intel-microcode: Update to upstream main
* bdee19ba87 soc/qualcomm/x1p42100: Add ASCII memory map diagram to memlayout.ld
* 51a8e238b0 lib: Correct logo bottom margin handling for all panel orientations
* 9999a4aebb mb/google/nissa/var/pujjocento: Change touchscreen properties
* 8d2df573a8 soc/qualcomm/x1p42100/qclib: Support to pack and load CPR binary in CBFS
* a484a6529c soc/qualcomm/common/qclib: Support to declare cpr_settings region
* dc04ee827b mb/google/fatcat/var/kinmen: Generate SPD ID for memory modules
* e7cdf035fb mb/google/brox/var/caboc: Enable RTD3 for SSD to resolve S0ix issue
* cec34128d0 soc/qualcomm/x1p42100: Support to load CPUCP firmware in x1p42100
* a2b6e20509 soc/mediatek/common: Increase per-channel SPMI max byte count to 2
* 6ba2df9be5 soc/mediatek/common: Use polling to reduce eDP HPD wait time
* ee347d8812 soc/qualcomm/common/qclib: Support to load AOP config and meta in CBFS
* 3f4c84513d soc/qualcomm/x1p42100/qclib: Support to pack AOP config and meta in CBFS
* 5de5b519ca mb/prodrive/atlas/vpd.c: Replace union {0} initializers with {} for C23 compliance
* 48207895af lint: Warn about using change IDs for merged changes
* 6acf07022d Doc/contributing: Add clarification on how to reference other commits
* 40d0ec0fa4 Revert "soc/mediatek/common: Remove 200 ms delay from eDP init path"
* 244a34b3d0 cpu/x86/mp_init: Refactor ICR wait logic
* eee5be070a cpu/intel: Use mtrr_use_temp_range()
* e37a53a2fc arch/x86/memcpy: Fix undefined behaviour
* 7c0f7e0b3f vc/intel/fsp: Update PTL FSP headers to FSP 3272_04
* d315f26217 payload/seabios: Update from 1.16.3 to 1.17.0
* c61a762a47 mb/google/bluey: Add QuenbiH board
* 9edf49b008 mb/google/bluey: Add BlueyH board
* 9868417d5e mb/google/bluey: Refactor Kconfig for Hamoa SoC
* 74d91d0b76 mb/google/nissa/var/glassway: Support Memory MICRON MT62F512M32D2DR-031WT:B
* 7eb832b1dc mb/google/skywalker: Configure GPIO GPIO_AP_EDP_BKLTEN as output
* cdd42ccde8 soc/qualcomm/x1p42100: Use 4K for memory region alignment
* 2146ecc8e1 mb/google/brox/caboc: Enable PEG60 with PEG62
* 6925fd69f8 soc/qualcomm: Move common region macros to `soc/memlayout.h`
* d220b65b8f soc/qualcomm/qcs405: Add common include path
* b25939786d soc/qualcomm/x1p42100: Refactor CBMEM top address to use linker symbols
* d6ec4f108d soc/qualcomm/x1p42100: Mark additional reserved memory ranges
* 1b760645b9 soc/qc/x1p42100: Dynamically configure DRAM resources in ramstage
* 276432faf7 soc/qualcomm/common: Add MMU configuration for fragmented DRAM regions
* b4347f11d9 include: Make DRAM an explicit region
* 11c8d423d1 soc/qc/common: Remove ddr_base from qc_mmu_dram_config_post_dram_init
* 73de3f95ac mb/google/bluey: Support hardware watchdog logging
* 25e0a4642c mb/google/brox/var/caboc: Update LAN LED behavior
* e5ff7cb186 mb/google/ocelot/var/ocelot: Update DDI port Configuration
* 8df079c609 mb/lattepanda/mu: Enable CRB TPM (Intel fTPM)
* 6e9c0a26e3 device/device_util: Fix format specifier for DEVICE_PATH_GICC_V3
* 4a82f37525 mb/google/nissa/var/quandiso: Generate new RAM ID
* 17a7c351b8 mb/google/brya/var/kaladin/hda_verb.c: Correct number of entries to 21
* b65b98ace6 mb/goog/ocelot/var/ocelot: switch to H58G56BK8BX068 memory part
* 8097809c8a libpayload: Fix strsep() edge cases
* e38a216368 soc/intel/pantherlake: Rearm and clear only for valid crashlog in PMC
* 510686add4 soc/intel/pantherlake: Rearm crashlog using watcher
* 609eb4c5f1 mb/google/ocelot/var/ocelot:  Remove unused I2C controllers
* df7bf9404d soc/mediatek/common: Remove 200 ms delay from eDP init path
* a70bf82036 soc/mediatek/common: Measure eDP initialization time
* 6bb1ba95e1 soc/mediatek/common/dp: Move mtk_edp_init to dptx_common.c
* e49e8c6355 soc/qc/x1p42100: Add memory layouts for CPUCP and TZ regions
* c418a3b843 mb/google/brox/var/caboc: Update WWAN gpio
* 77b52ed3cc mb/google/brox/var/caboc: HDA: Correct number of jacks to 35
* e31fbc493d soc/qualcomm/cmn/qclib: Support reuse of existing DDR training data
* bdcf19f404 mb/google/trulo/var/pujjolo: Add fw config for PDC
* 13897bde9a mb/google/trulo/var/pujjolo: Add wlan rtd3 setting
* 90589d44d2 soc/qualcomm/x1p42100: Reserve DDR memory regions for AOP and BL31
* 2e61995b2f soc/qualcomm/x1p42100: Add support for Hamoa SoC
* 281b01ce5e soc/qualcomm/x1p42100: Remove unused PMIC file from CBFS
* ecbca16bf4 tree: Replace union {0} initializers with {} for C23 compliance
* b74d2b77d2 mb/google/trulo/var/kaladin: Add WIFI SAR table
* 4b46a0690e mb/hp: Add HP ProDesk 600 G1 SFF Business PC (Haswell / NPCD379 SIO)
* 2339508b6c mb/google/trulo/var/pujjolo: Update P-sensor parameters
* cd2a969c82 soc/intel/pantherlake: Remove storage-off related code
* fe6fa36504 mb/asrock: Add SPR 1S server board ASRock Rack SPC741D8-2L2T/BCM
* b486c84b23 mb/google/trulo/var/pujjolo: Update DTT settings for thermal control
* ece0072d1c mb/google/trulo/var/pujjolo: Update verb table to fix pop noise
* 795157a606 mb/google/bluey: Increase MRC cache size
* 34d9305dcc soc/qc/x1p42100: Pack QcLib DTB into CBFS
* 8f09629fb1 spi_flash: Fix initialization of `flags` field in lb_spi_flash
* ab2ef8878c mb/google/trulo/var/pujjocento: Update touchscreen information
* 0bedce05d8 mb/google/nissa/var/pujjocento: Change touchpanel sequence to meet spec
* 543fb60ec4 mb/google/brox/var/lotso: Set slew rate to 1/8
* c114906239 mb/google/trulo/var/pujjocento: Update DTT settings for thermal control
* b603f23088 mb/google/bluey: Avoid using function call table
* dc64b9659d soc/qc/cmn: Refactor qclib_load_and_run function
* e290bb6750 mb/baseboard/ptlrvp: Disable memory training progress bar
* 05a38e2af3 mb/google/fatcat: Disable memory training progress bar
* f789899dac sb/intel/common/gpio: Move register defines
* d6ceaf72da mb/samsung/lumpy: Use gpio_base2_value
* 21639c3771 mb/getac/p470: Use common gpio functions
* 8d4bb94663 sb/intel/common/gpio: Add and use gpio_invert()
* 85306062d8 mb/google/skywalker: Create variant Tarkin
* 1da2f46db8 soc/intel/alderlake: Restore mem_init_override_channel_mask()
* f0d5b25e02 mb/google/trulo/var/kaladin: Add firmware name and gpio for ISH
* 0b3fc8ce2d mb/google/nissa/var/pujjoniru: Decrease cpu power limits
* f01cc9258b mb/google/rex/var/screebo: Use ACPI for touchscreen power sequencing
* ef11f95125 soc/qualcomm/x1p42100: Set 1ms TX delay
* 2c8d157ea4 {drivers, soc/qualcomm/common}: Add configurable delay for UART bitbang
* b0d2d522ea soc/qualcomm/x1p42100: Enable bootblock compression
* 1e11bda5d0 soc/intel/cmn/smbus: Drop use of update_spd_len()
* 910f111891 soc/intel/mtl: Fill in SPD data on both channels of DDR5 memory
* 0da943ed99 soc/intel/meteorlake: Fix DDR5 channel mapping
* 87c9bb3994 soc/intel/adl: Fill in SPD data on both channels of DDR5 memory
* a23be7a6fe mb/google/fatcat/var/francka: Disable ALC721 & ALC722 clock stop support
* 227d434e2d drivers/soundwire/alc711: Support clock stop flag from devicetree
* 49219f1ce1 Docs: Use markdown autolinks instead of Sphinx doc directive
* 6afc1ff9ac soc/mediatek/mt8189: Disable 8189G APU power to reduce power consumption
* 965131e40f soc/mediatek/common: Fix build error by including stdint.h in cpu_id.h
* e49743755d mb/google/ocelot: Select EC_GOOGLE_CHROMEEC_MEC for MCHP variants
* 32b944b77a mb/google/brox/var/caboc: Update hda_verb table
* ba228d160f mb/google/fatcat: Create new kinmen4es variant
* 6a42eb9134 soc/intel/pantherlake: Disable memory training progress bar
* e9cb352706 soc/common/smbus: Support reading SPD5 hubs for DDR5
* cba46a41b7 mainboard/{hardkernel,protectli}: Drop use of DRAM_SUPPORT_DDR5
* a79f341d29 mb/google/trulo/var/pujjolo: Disable mipi camera dmic LED
* 9411c6e7c7 util/amdfwtool: Fix NULL pointer dereference in fill_dir_header
* 280d3a25e8 util/lint/kconfig_lint: Fix operator precedence issue
* fbc2d76ab3 soc/intel/*: Select 'DRAM_SUPPORT_DDRx' as appropriate
* 008f0ec078 util/smmstoretool: Alias EfiImageSecurityDatabaseGuid to "secureboot"
* 88aeb8b7cd util/smmstoretool: Allow setting authenticated variable
* e977560e72 payloads/edk2: Increase non-full-screen menu size
* ac7487d766 mb/google/fatcat: Use same MAINBOARD_PART_NUMBER for felino variants
* 0f84878c89 mb/google/brox: Handle NULL return value in variant_get_auxfw_version_file
* 749fd1a8d8 soc/intel/pantherlake: Use macro for VGA Init Control
* 3c4fb7b729 mb/google/trulo/var/pujjolo: Update verb table
* 2ae0f6cdb9 mb/google/trulo/var/kaladin: Add fw config for ELAN touchscreen
* 53dd93ff14 libpayload/drivers/pci_qcom: Fix address during ATU config
* 54016e273e util/cbmem/sysfs_drv: Fix incompatible pointer type for 'size'
* a9997f2d7f soc/intel/cmn/block: Request bus master in final op for DSP and HDA
* fea789ed63 mb/google/fatcat/var/francka: Use ACPI for touchscreen power sequencing
* 211526ff38 Revert "mb/google/brya: Fix mux_conn index used by ec/google/chromeec"
* 7b91339e55 Revert "mb/google/brya: Fix pmc_mux port mapping for mithrax and felwinter"
* 8a45e505b9 soc/mediatek/common/dp: Change dptx_hal_phy_wait_aux_ldo_ready to static
* 350c977fef soc/intel/pantherlake: Clear crashlog record using watcher
* ae942a70b8 mb/google/trulo/var/kaladin: Update GPIOs table
* 0a4bc79685 mb/google/trulo/var/kaladin: Update USB2 driving settings
* f34bc61ca7 mb/google/trulo/var/pujjolo: Correct the Goodix touchpad description
* d4b735f9f1 mb/google/ocelot: Turn off unused I2C ports
* 190c27d08b mb/google/brya/var/marasov: Add SPD ID for K3KL6L60GM-MGCT and K3KL8L80EM-MGCU
* d79febf356 soc/qc/x1p42100: Enable QcLib, SHRM and AOP firmware load
* db10b681b4 soc/qc/x1p42100: Load and populate QcLib interface table entries
* eee3ea0346 mb/google/bluey: Enable PCIE Feature for bluey
* 6f115f7bf0 soc/qualcomm/x1p42100: Configure Gen4 PHY link for x1p42100
* 823fa6b8f6 soc/qualcomm/common: Integrate QMP PCIe 4.0 PHY 2x2/1x4
* 6bb199d258 mb/google/fatcat/var/fatcat: Move `ISH_GP_x` pads to fw_config.c
* a5212f15ce mb/google/fatcat/var/fatcat: Remove unused GPP_B06 GPIO configuration
* d7415f5d9a mb/google/trulo/var/kaladin: Remove external bypass settings
* 479b39c3e9 mb/google/ocelot: Update wake on touch GPIO
* 7095c99a87 util/cbmem: Add support for CBMEM in sysfs
* eeb15e83cb mb/gigabyte: Add ga-h81m-d2w (ITE8620E superio)
* 5537ce7c2f mb/google/fatcat: Fix GPIO config for headphone jack detection
* 953957e961 mb/google/trulo/var/pujjolo: Change ICCmax at VCCIN_AUX from 25A to 27A
* 87d5c7224b mb/google/trulo/var/pujjolo: Select Strauss keyboard to show G icon
* eb005f5f5c mb/google/brya/var: Clarify comment for 'tcss_aux_ori'
* 85b26f75d2 soc/intel/xeon_sp: Remove fast_spi_cache_bios_region
* fc4911ec35 soc/qualcomm/x1p42100: Add CPU Clock boost support for X1P42100
* 1a9fb29a53 soc/qualcomm/common: Add API to enable Zondaole PLL for X1P42100
* e272b20c85 sb/intel/common: Remove unused function prototype
* c54fde5040 sb/inte/common/gpio: Implement gpio_input() and gpio_output()
* 55bed620a4 mb/dell: Use gpio_base2_value
* 84899e6fb7 sb/intel: Convert set_gpio to gpio_set
* 0c79443ca9 sb/intel/*/gpio: Convert get_gpios to gpio_base2_value
* 69364fc9e0 sb/intel: Convert get_gpio() to gpio_get()
* 2d7891abe2 sb/intel: Add soc/gpio.h
* 6a20caea01 drivers/lenovo/hybrid_graphics: Add missing header
* 04cc15feb4 sb/intel/common/pmutil: Drop unused header
* b44c0ab25b ec/lenovo/pmh7: Include stdbool.h
* b20f6d27e2 device/dram: Rename 'USE_DDRx' config options
* 1ade8247ce mb/google/trulo/var/pujjocento: update hda_verb table for ALC257
* 28848dc4fb mb/google/trulo/var/kaladin: Add elan touchscreen support
* 9a89e3b4c6 mb/google/trulo/var/kaladin: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS
* f84934a203 mb/google/trulo/var/kaladin: Add DRAM part H58G56CK8BX146
* dd76bcc4c3 soc/qc/sc7280: Relocate SHRM firmware load to common Qualcomm path
* 88b10e09b6 mb/google/ocelot: Set TPM_TIS_ACPI_INTERRUPT for all ocelot variants
* c2dfe61016 mb/google/ocelot: Disable CNVi bluetooth core in the baseboard code
* 69e6d96aad mb/google/fatcat: Configure host command ranges for FATCAT4ES variant
* 8bdc170901 mb/google/brox/var/lotso: Update VR domain config
* a6842184ab mb/google/fatcat/var/kinmen: Use ACPI for touchscreen power sequencing
* 712aac780f mb/google/rex/kanix: Use ACPI for touchscreen power sequencing
* 26e6d0be00 mb/google/rex/var/karis: Use ACPI for touchscreen power sequencing
* 00d99a6e9b mb/google/brox/var/lotso: Configure Acoustic noise mitigation
* 4b6ebbdd94 mb/google/skywalker: Initialize clkbuf and srclken in romstage
* f131f0e336 soc/mediatek/mt8189: Add clk_buf and srclken_rc drivers
* 2de0158eec soc/intel/pantherlake: Add asynchronous CBFS file loading support
* eb1b5ee116 soc/intel/cmn/block/fast_spi: Introduce a DMA transfer queue
* 182ba52792 soc/intel/pantherlake: Remove mailbox interface offset
* 2ee78458be soc/intel/pantherlake: Use CONSUMED_BIOS bit
* 9a8ba5b39a {lib, drivers/intel}: Move BMP rendering logic out of SoC code
* a617317775 mb/google/fatcat/var/kinmen: Support SAR table selection via FW_CONFIG
* 92dd8cea59 mb/google/nissa/var/riven: Add parade touchscreen support
* b98f786375 mb/google/fatcat/var/francka: Increase reset delay to 100ms for ILTK0001
* 5f0177ac5d mb/google/trulo/var/pujjolo: Update Stylus IRQ wakeup group
* 5b1a8b53b6 soc/amd/common/i23c_pad_ctrl: add I3C pad config options
* 4b58ec5ac2 soc/amd/common/block/psp: Add fTPM specific bits
* 15bf25de78 Documentation/soc/intel: Update the referenced linuxboot_defconfig
* debfac6352 mb/google/ocelot/var/ocelot: Add wake support for touchpad
* b6425a9a78 soc/amd/common: Add comments about bootblock
* 69888bc7fc util/cbfstool/amdcompress: Bail out on invalid ELF
* 3b008bde8c soc/mediatek/mt8196: Fix intermittent black screen issue
* da33feeb51 soc/mediatek/mt8189: Correct thermal SRAM base address and length

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-19 07:47:18 +00:00
Leah Rowe aa0e4205d6 re-base the T480 thunderbolt patch
i noticed that the enablement patch came first,
before the actual driver. while this functioned
overall, it was obviously flawed in terms of
the resulting git history. the person who sent
the patch previously had 0046- on both patch
names, which meant that alphabetical sorting
caused the enablement patch to be applied
before the driver patch.

furthermore:

it seems that the submitted had manually re-applied
the same Kconfig changes in the enablement patch,
adding their own name - since Kconfig is not
copyrightable anyway, in this specific example, or
otherwise trivial, it's probably fine, but the
original author on the gerrit patch is actually
Matt DeVillier:

https://review.coreboot.org/c/coreboot/+/88490

I have therefore simply re-based by checking out
Matt's patch, on patchset 1.

However, patchset 1 of Matt's patch uses patch
set 16 of:

https://review.coreboot.org/c/coreboot/+/75286

HustlerOne's lbmk merge uses patchset 18:

https://review.coreboot.org/c/coreboot/+/75286/18

The differences between the two can be observed, thus:

https://review.coreboot.org/c/coreboot/+/75286/16..18

It should be clarified that these patches are not
upstreamed yet, but under heavy review on gerrit.
However, testing has revealed that the patch is
mostly stable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-15 14:06:12 +00:00
Leah Rowe f3dc54432e Merge pull request 'T480: Add Thunderbolt support' (#387) from hustlerone/lbmk-alpine_ridge:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/387
2025-12-15 14:57:52 +01:00
Hustler One 809e5d29a4 T480(s): Add Thunderbolt support 2025-12-11 14:58:33 +01:00
Leah Rowe ec8617f27a coreboot/t480s: fix headphone jack detection
this is merged from a patch sent to coreboot by
Matt DeVillier, based upon the work done by
Arthur Heymans for the regular T480

https://review.coreboot.org/c/coreboot/+/90450/2

yes

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-12-10 22:30:09 +00:00
Leah Rowe 724f905aaf Merge pull request 'T480: Fix headphone jack detection' (#385) from Riku_V/lbmk:t480verbfix into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/385
2025-12-02 22:17:21 +01:00
Riku Viitanen 2dea4b79b2 T480: Fix headphone jack detection
Recently, a HDA verb bugfix was merged to coreboot:
https://review.coreboot.org/c/coreboot/+/90023

Tested on a T480. Before the fix, detection *never* worked.
After fix, it seems to reliably work.

TODO: update docs to reflect this.

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2025-12-02 21:58:53 +02:00
Leah Rowe 9d740e9512 grub: add a keyboard layout for norway
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-22 21:26:40 +00:00
Leah Rowe 7a9977af72 rebase recent dell thermal safety patch
it didn't apply. i will soon update the coreboot revisions
ready for Libreboot 25.12

just rebase this patch for now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-18 18:47:23 +00:00
Leah Rowe efd17fde19 Merge pull request 'removed duplicate "payload_uboot" for e6230_12mb' (#374) from honzo/lbmk:e6230_12mb_deduplicated into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/374
2025-11-18 15:13:22 +01:00
Leah Rowe d1606ef11f Merge pull request 'fixed typo in "grub_scan_disk" for macbook11_16mb' (#375) from honzo/lbmk:macbook11_16mb_fixed_typo into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/375
2025-11-18 15:12:48 +01:00
Leah Rowe 48b00ce3c8 Merge pull request 'config/coreboot/default: Disable Latitude early thermal shutdown' (#376) from nic3-14159/lbmk:mec5035-updates into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/376
2025-11-18 15:12:28 +01:00
Nicholas Chin c0dab33972 config/coreboot/default: Disable Latitude early thermal shutdown
Disable the sudden EC initiated shutdown on the Sandy Bridge/Ivy Bridge
Dell Latitude laptops as soon as the reaches 87 degrees, allowing the
standard CPU thermal throttling mechanisms to work.

Fixes: https://codeberg.org/libreboot/lbmk/issues/202

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2025-11-18 06:48:38 -07:00
libreboot Contributor fda3ac975a removed duplicate "payload_uboot" for e6230_12mb 2025-11-16 00:19:36 +00:00
libreboot Contributor 831fa657de fixed typo in "grub_scan_disk" for macbook11_16mb 2025-11-16 00:18:31 +00:00
Leah Rowe 1b10c072d3 tree.sh: tidy up check_gnu_path
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-15 16:57:48 +00:00
Leah Rowe 7ef7e02f73 lib.sh: reduce indentation in setvars
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-15 16:55:27 +00:00
Leah Rowe 214ed3efd2 get.sh: reduce indendation in fetch_targets
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-15 16:51:59 +00:00
Leah Rowe 9d6af0063b get.sh: reduce indentation in clone_project
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-15 16:51:10 +00:00
Leah Rowe d7869a56f5 WIP: chromebook integration script
I intend to merge every Chromebook that Mrchromebox supports,
into Libreboot, ready for the Libreboot 25.12 release. Work
is still ongoing, and several changes need to happen in lbmk.

I started working on it a few weeks ago (today is
14 November 2025 as I push this).

Still TODO:

* Automatically create lbmk coreboot targets, based
  on the configs present in MrChromebox git
* Re-work git repository management in lbmk, such that
  a list of upstreams is used, instead of a hardcoded
  list per configuration; this will allow us to use
  different remotes across the same project, even where
  they diverge. This would then allow us to use the
  MrChromebook repository directly, instead of cherry-picking
  patches into upstream coreboot
* The note above about remotes would also mean that we can
  use MrChromebox's own edk2 repository directly. All of this
  would reduce the burden on lbmk.git
* Support building edk2 payloads, exactly mirroring the
  setups used on MrChromebox builds

There are some things that need to be checked first, for
boards that use MMC-based or eMMC-based storage, for the
GRUB and SeaBIOS payloads, also U-Boot, because I will
also be using these.

As such, this current script shall sit in lbmk master, but
it is not yet finished.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-11-14 18:22:51 +00:00
Leah Rowe 25f523bbac get.sh: return clone_project if multi-tree
this is the true fix, replacing the fixes previously
reverted.

the problem with the old fix was that it was a hack,
and could result in the archived backup of a code repo
being the wrong one; the destination was the one for
the main repo, but what if we were cloning the backup?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 22:40:29 +01:00
Leah Rowe bec7e6d4cb Revert "get.sh: don't frivolously copy tmp git clones"
This reverts commit b840cf3a83.
2025-10-17 22:32:43 +01:00
Leah Rowe f632b8aed7 Revert "get.sh: remove a redundant check"
This reverts commit e2a97455cc.
2025-10-17 22:32:35 +01:00
Leah Rowe e2a97455cc get.sh: remove a redundant check
loc is never empty.

if it is, it's a bug. don't hide bugs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 21:01:31 +01:00
Leah Rowe b840cf3a83 get.sh: don't frivolously copy tmp git clones
this fixes a regression in a previous patch, this time
also taking account for the different cache locations.

all of get.sh needs to be purged, and re-written clean.
it looks clean. but it's years of hacks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 20:57:18 +01:00
Leah Rowe 2aea7f6229 Revert "get.sh: make forcepull a macro"
This reverts commit b3232a7c4a.
2025-10-17 16:07:16 +01:00
Leah Rowe b3232a7c4a get.sh: make forcepull a macro
:

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 14:02:55 +01:00
Leah Rowe 54aa5b7d32 tree.sh: unify -f/-F in case/switch handling
they're the same commands, but -F does forcepull

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 13:57:14 +01:00
Leah Rowe 96f786b962 tree.sh: convert do_make into a macro
use it similarly to if_dry_build/if_not_dry_build

there is nothing cooler than an sh macro

:

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-17 13:29:56 +01:00
Leah Rowe 47f08e2e6d git: don't use review.coreboot.org as main
where backup links are available, use those as main instead.

this is because of the new XBMK_CACHE_MIRROR variable, which
makes --mirror be used

when performed on review.coreboot.org, this also pulls down
all changes from gerrit code review; the github backups for
example only contain the official branches, but gerrit creates
a new ref per merge request.

a user can still run ./mk -F to force pulling all repos,
including the coreboot.org ones, but use of -f will skip the
coreboot.org ones if the backup links worked and contain the
local commit needed, by a given project used in xbmk.

this patch won't change any real-world behaviour for xbmk
users, but it is done as a courtesy to the coreboot project,
in that it largely avoids a sudden surge in coreboot.org's
traffic if lots of users start doing XBMK_CACHE_MIRROR=y

if XBMK_CACHE_MIRROR is not set, or set to anything other
than y, a regular clone is performed, saving cached sources
to cache/clone/ - otherwise, cache/mirror/ is used.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-16 15:57:31 +01:00
Leah Rowe e1b6ccf69e xbmk: sort global variables alphabetically
also separate some of the special ones.

this makes the variables easier to read/find.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-16 15:46:44 +01:00
Leah Rowe d84a556bf0 get.sh: use the same directory map as --mirror
Don't hardcode the cache directory, and don't store
remotes anymore. This change retains compatibility
in practice, with the older directory location, because
it's extremely unlikely that newly generated locations
would conflict with old ones.

With this new change, non-mirror git clone caches are
now done twice; one directory per remote, rather than
one directory with two remotes.

This is just inherently much more reliable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-16 14:22:06 +01:00
Leah Rowe b333ddfe73 get.sh: use --keep-cr on git-am
Some repositories might use CR-LF line endings. This option
keeps Git from mangling patches when merging.

Repositories that don't do this, such as ALL repositories
currently used by xbmk, will be unaffected by this change.

This is being done in preparation for importing MrChromebox
edk2, as Intel's own edk2 repository on GitHub uses these.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-16 13:30:55 +01:00
Leah Rowe d83dd506c2 get.sh: More reliable git remote caching
Don't do one repository for all remotes. Do one *clone* per
remote.

This also means that users no longer download information twice,
in practice, because the backup repository will only be downloaded
if the main one didn't work.

Theoretically, this change is makes the process less efficient, but
in practise it's more reliable now.

We do now use --mirror on the git clone command for caches, but we
already did git pull --all before.

This just ensures that we absolutely have all local code.

NOTE:

The new code isn't used by default. To use it, you must do:

export XBMK_CACHE_MIRROR="y"

Otherwise, the old behaviour will continue to be used. This is
because the new code, while correct, puts more strain on upstream
servers (more code being downloaded), and can result in higher amounts
of disk space being used. The old behaviour wasn't broken, so we'll
also support that method.

TODO: perhaps also have a check in place to re-use both caches,
where available, regardless of XBMK_CACHE_MIRROR?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-16 13:29:59 +01:00
Leah Rowe 18c63682e7 Merge pull request 'Add Fedora 43 to dependencies' (#364) from bauduser/lbmk:fedora43dependency into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/364
2025-10-09 12:07:15 +02:00
bauduser 7b42779912 Add Fedora 43 to dependencies 2025-10-09 02:56:09 -07:00
Leah Rowe 11a3e9d887 xbmk: minor code cleanup (79 character rule)
recent re-factoring lead to certain code lines that
exceeded 79 characters in length.

we like to avoid this, whenever possible.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-07 05:52:36 +01:00
Leah Rowe fb95e4ad68 tree.sh: add missing -F flag
i support -F, but didn't include it in the
actual getopt string.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-07 03:02:01 +01:00
Leah Rowe ca5f0a5edd get.sh: use git-show instead, for rev checks
whatchanged is deprecated, and results in an error
on modern git versions, prompting you to include
the --i-still-use-this argument

what absolute, utter fucking arrogance. i use the
whatchanged feature every fucking day.

i will be complaining to git-scm.com about this.

but that's what we do in libreboot. we adapt.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-07 01:25:19 +01:00
Leah Rowe 8636d7497c rom.sh/tree.sh: clean up if_not_dry_build
the way it was used is messy, and a relic of the
old chained command coding style, from before when
i recently loosened that requirement.

the new focus is simple, readable code, regardless
of size.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 13:28:34 +01:00
Leah Rowe 1b54c7a744 rom.sh: use if_dry_build macro
instead of checking if_not_dry_build.

use it here the same way.

yes. shell script macros. it's how i roll.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 12:43:04 +01:00
Leah Rowe afccecbde0 rom.sh: don't run add_cbfs_option on dry builds
i added this in an earlier version of the patch, but
for some reason removed it.

this is necessary, or the build system will fail.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 07:44:38 +01:00
Leah Rowe 7d597bc4a1 disable stack overflow debug on alderlake
see patch

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 04:48:48 +01:00
Leah Rowe c716341c13 cb/kabylake: don't hardcode power_on_after_fail
I realised that the Dell OptiPlex 3050 Micro has NVRAM available.
Use that backend, and hardcode power_on_after_fail to Disable,
which is already done in cmos.default.

The Lenovo ThinkPad T480 currently has no option table in coreboot,
besides the CBFS one. For this, the CBFS option table has been
enabled, and the build system has been modified to insert
a relevant config for power_on_after_fail.

Nicholas Chin informs me that Kabylake generally has legacy NVRAM,
so enabling it for the T480/T480s should work, but we'll need
to use it in the future anyway; better to just use CBFS now.

I *could* use the CBFS backend on 3050micro as well.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 04:03:36 +01:00
Leah Rowe b5ad829ffe Merge pull request 'config/coreboot/default: Add Haswell NRI SMBIOS type 16/17 patch' (#363) from noisytoot/haswell-nri-smbios-memory into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/363
2025-10-06 03:22:07 +02:00
Ron Nazarov e82e2a1332 config/coreboot/default: Add Haswell NRI SMBIOS type 16/17 patch
This patch implements SMBIOS type 16 and 17 for Haswell NRI, making
`dmidecode -t memory` work.

From https://review.coreboot.org/c/coreboot/+/89385
2025-10-06 01:12:25 +01:00
Leah Rowe 9b104fca44 init.sh: only create cache/ here
also, the check is -e, not -d, because we
might be operating on a symlink.

it's a bit hacky but this should work.

the previous change (now reverted) broke
re-use of the main cache/ in release work
directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-05 01:23:32 +01:00
Leah Rowe ee2bca65f6 Revert "init.sh: explicitly create cache/"
This reverts commit 23f98c2958.
2025-10-05 01:21:26 +01:00
Leah Rowe 23f98c2958 init.sh: explicitly create cache/
otherwise, an error occurs when doing ./mk release

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-05 01:04:25 +01:00
Leah Rowe 1e488aae78 Revert "remove unar from dependencies"
This reverts commit e8a3cd8cd0.

We still need this for extracting the CAB files containing
KBC1126 EC firmware.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 23:57:08 +01:00
Leah Rowe c1d6cd22c2 xbmk: don't call mkdir. use xbmkdir (new function)
xbmkdir checks if a directory exists, before running
mkdir, and then still uses -p

i was testing xbmk on arch linux today, and noticed
that it errored out when a directory already exists.

i'm mitigating against buggy or differently behaving
mkdir implementations this way, by wrapping around
it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 22:42:42 +01:00
Leah Rowe f358cfaa55 coreboot/x2e_n150: fix the alderlake n fsp link
this fixes ./mk inject

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 22:23:52 +01:00
Leah Rowe 6a00b7a584 coreboot/default: don't require alderlake fsp repo
we need the full fd path to be automatically set. this
patch prevents it from being removed by ./mk -u coreboot

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 22:21:23 +01:00
Leah Rowe 247cb85489 don't compress alderlake fsp
for reproducibility, we must not compress it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 22:02:03 +01:00
Leah Rowe 183f378150 coreboot/x2e_n150: unset CONFIG_FSP_FULL_FD
otherwise, ./mk -u screws up the FSP path

we were still using the correct path for downloading
in ./mk inject, and in practise, the file used by
coreboot would have been the same, but without our
hash verification after splitting up the FSP.

that's the main reason we split FSP in lbmk, rather
than relying on coreboot's logic for this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 20:11:17 +01:00
Leah Rowe 31fa7ea591 vendor.sh: re-do the previously reverted change
but do it better. this time, the change won't cause any
behavioural differences.

the reason for the change is we don't want "$@" inside
an eval statement, if such calamity can be avoided.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 16:57:36 +01:00
Leah Rowe 2956fcc051 vendor.sh: fix setvfile
this reverts change made to this function in:

commit 4f01dc704a
Author: Leah Rowe <leah@libreboot.org>
Date:   Sat Oct 4 06:13:15 2025 +0100

    xbmk: remove even more eval statements

for some reason, the new code caused sch5545 ec firmware
to never download.

the old code wasn't horribly broken, so just use that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 16:14:36 +01:00
Leah Rowe 8334c93dac release.sh: preserve clean sbase before building
this way, the clean version can be placed inside the
release tarball.

there is a make clean option in sbase, but we should
not really on this.

the design of xbmk is that a clean src tarball is
created. there must not be build artifications in it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 10:09:24 +01:00
Leah Rowe 8969cc734f xbmk: use sbase sha512sum, not host sha512sum
the --status flag seems to be a GNUism

as stated in the previous commit, i import sbase
suckless now, so as to have a consistent implementation
of sha512sum.

this ensures that its output is reliable, when i'm using
the output of this command within backticks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 09:58:24 +01:00
Leah Rowe e9a910b33c config/git: import suckless sbase
i currently use the output of sha512sum in several
places of xbmk, which is a bit unreliable in case
output changes.

other cases where i use util outputs in variables
are probably reliable, because i'm using mostly
posix utilities in those.

to mitigate this, i now import suckless sbase, which
has a reasonable sha512sum implementation.

*every* binary it builds is being placed in build.list,
because i'll probably start using more of them.

for example, i may start modifying the "date"
implementation, adding the GNU-specific options that
i need as mentioned on init.sh

i'm importing it in util/ because the sha512sum
util is needed for verifying project sources, so
if sbase itself is a "project source", that means
we can into a chicken and egg bootstrapping problem.

this is sbase at revision:
055cc1ae1b3a13c3d8f25af0a4a3316590efcd48

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 09:20:12 +01:00
Leah Rowe 2cfaba181b xbmk: rename cv variables, for clarity
the new names are still a bit crap, but a bit better.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:41:25 +01:00
Leah Rowe 1943dba608 tree.sh: rename xtree to xgcctree, for clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:37:41 +01:00
Leah Rowe 51e424c7d1 tree.sh: rename btype to buildtype, for clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:36:18 +01:00
Leah Rowe d95af9ba44 vendor.sh: rename _t to blobtype, for code clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:33:26 +01:00
Leah Rowe 63002732f5 tree.sh: rename _f to flag, for code clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:29:33 +01:00
Leah Rowe b7a9aad9fc get.sh: delete tmp patch list when done
yet another oversight

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:20:27 +01:00
Leah Rowe a115679c57 get.sh: sort patches when applying
this was an oversight in my recent patch unrolling
the condensed code lines, to remove eval statements.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:17:53 +01:00
Leah Rowe 0776eb414c vendor.sh: make the fsp hack a bit cleaner
it's still a dirty hack. i really should make
a better check here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:12:24 +01:00
Leah Rowe 70cdb03f7f vendor.sh: correction to fsp hack
i unrolled these lines earlier, but this line was
incorrect; dl was already handled. it's dl_bkup
that we have to handle here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:08:34 +01:00
Leah Rowe 1eafcf9029 vendor.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:07:07 +01:00
Leah Rowe efd1db1ca3 release.sh: remove eval statement in nuke()
the symlink check is what made me use eval, but the
symlink check is not required, since i check every
entry that goes in nuke.list anyway.

not having that symlink check is safer than having
an eval statement on that line.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 08:03:12 +01:00
Leah Rowe b4c7cac8a2 xbmk: rename the "dry" variable to if_not_dry_run
and add a line break where it is used

now it is essentially a macro of sorts, used in
terms of syntax, to mean the same as:

if [ "$dry" != ":" ]; do
	thing
fi

in this case, we say:

$if_not_dry_build \
	thing

yes. macros in sh are a thing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 07:50:34 +01:00
Leah Rowe 9f84bd4f34 coreboot/mkhelper: don't use eval
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 07:36:19 +01:00
Leah Rowe 4f01dc704a xbmk: remove even more eval statements
in one or two cases, the use of eval is retained, but
modified so as to be safer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 07:17:42 +01:00
Leah Rowe 7f8d85140f xbmk: remove the setcfg function
this allows me to remove several eval calls, and the
errors relating to configs can now show exactly which
function they occured in, allowing for easier debugging.

once again, eval should be used sparingly if at all.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 05:23:47 +01:00
Leah Rowe 0a74cc8ec6 xbmk: clean up a few err calls
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 03:05:23 +01:00
Leah Rowe a09ec1d02b xbmk: remove more eval statements
i will eventually find a way to remove them all,
while still leaving the code completely clean.

in practise, i never use the contents of a file
for eval and the inputs are carefully checked.

however, over-use of eval is always a bad idea
in shell scripting.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 02:55:52 +01:00
Leah Rowe 0605fbe720 xbmk: general cleanup: unroll condensed code lines
i overlooked a number of lines, during previous cleanup

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-04 02:43:24 +01:00
Leah Rowe e1c70f4319 vendor.sh: remove superfluous AND
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-03 22:43:06 +01:00
Leah Rowe e1c580f6bc grub/xhci_nvme: fix target.cfg
it still said tree="xhci"

it should say  xhci_nvme

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-03 00:04:23 +01:00
Leah Rowe 093606784a add fedora42 dependencies from bauduser
this was sent by bauduser, who messed up the pull
request (number 362). i'm simply merging the
change manually.

once again, i instructed this contributor to
properly learn git vcs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 23:59:57 +01:00
Leah Rowe 5e35b0684d dependency/debian: libstdc++-arm-none-eabi-newlib
this is needed to make pico-serprog compile.

this change is submitted by "bauduser" in lbmk pull
request #362, but the PR was messed up. for such
a trivial change, I simply  merged this change
manually, instructing the contributor to properly
learn git vcs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 23:57:49 +01:00
Leah Rowe af88a066d0 grub/xhci: rename to grub/xhci_nvme
we have the "default" tree, then the "nvme" tree which adds
nvme support.

the "xhci" tree adds xhci patches, *and* nvme patches.

riku suggested that i rename it accordingly, and his advice
was quite correct, indeed wise.

this will reduce confusion for contributors, including *myself*.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 23:48:48 +01:00
Leah Rowe d90defeae3 mrc.sh: remove superfluous eval statement
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 07:09:37 +01:00
Leah Rowe a74af6aa05 tree.sh: remove superfluous eval statements
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 06:55:29 +01:00
Leah Rowe 15cefca84b rom.sh: remove superfluous eval statement
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 06:53:36 +01:00
Leah Rowe 2b4b5bf82e inject: remove superfluous use of eval
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 06:52:10 +01:00
Leah Rowe 85b10a674b init.sh: reduce the use of eval statements
also remove the unused _nogit variable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 06:51:03 +01:00
Leah Rowe 99f2c0fcf9 get.sh: reduce the number of eval statements
also split up try_fetch()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-02 06:27:39 +01:00
Leah Rowe be1f4ebb9c get.sh: allow force-pull via -F instead of -f
use of ./mk -F behaves the same as -f before the
previous commit.

this can be useful, during development when we want
to update revisions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 16:51:00 +01:00
Leah Rowe 24f120d1b8 get.sh: only pull if the local revision is missing
we pull from upstream in cached git repos, before performing
an operation, and we run from the cache, but we do this every
time, even if a local revision exists, defeating the purpose
of the caching; on unreliable/intermittent internet connections,
this can cause a problem.

this also causes us problems with gnulib.git and grub.cfg, which
for *some reason* are really slow, even when doing a pull.

this change improves the efficiency of the build system, during
release builds, on a development repository where we already
have lots of caches.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 16:28:04 +01:00
Leah Rowe 084b8b65c6 u-boot: make the libreboot logo rainbow again
i like the rainbow

removing it was a mistake

this patch brings it back

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 09:26:46 +01:00
Leah Rowe 2ac51f442b init.sh: break up xbmk_set_env
what this function does will differ wildly,
depending on whether it's a child instance
or a parent instance of xbmk.

break up this function accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 07:57:39 +01:00
Leah Rowe 8b351e51aa tree.sh: break up check_gnu_path to subfunctions
this whole check could probably be removed, honestly.

it was only put in place during the debian trixie testing
release cycle, before they finally updated gnat just before
the stable release of trixie came out.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 07:43:12 +01:00
Leah Rowe 3b6d2b799c vendor.sh: break up the extract_kbc1126 subshell
stick it in a new function, for easier reading.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-01 07:19:04 +01:00
Leah Rowe 347330a611 coreboot/x2e_n150: rename config to fspgop
because it's using fspgop init code, not libgfxinit

this is enabled by the previous patch, which now properly
handles seabios payloads when dealing with this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 23:20:25 +01:00
Leah Rowe f272c4d1c4 rom.sh: support "fspgop" init mode
for all intents and purposes, this functions like libgfxinit
corebootfb, but uses intel fsp's video initialisation instead
of coreboot's native initialisation code

this is currently in use on the x2e n150 mainboard, whose
config is dubiously named "libgfxinit_corebootfb"

now the config can be renamed, and will be, in the next commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 23:18:50 +01:00
Leah Rowe aa3ccf0433 fix up old comment in vendor/x2e_n150
theu current comment is for an old version of the n150
patch, before it was actually merged. the comment has
been adjusted, to match the actual implementation that
was merged.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 22:09:58 +01:00
Leah Rowe b786918b2b vendor.sh: use bsdunzip, not unzip
most implementations of unzip are info-zip

we already compile libarchive for bsdtar, to extract
rar archives in vendor.sh

now we also use bsdunzip

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 11:27:16 +01:00
Leah Rowe c6939cf390 libarchive: also copy bsdunzip and bsdcpio
bsdunzip in particular, can be used instead of relying
on the host to provide unzip.

most linux hosts use info-zip as the implementation,
which bsdzip is compatible with.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 11:23:52 +01:00
Leah Rowe 06c1ed009d add -p flag to old me_cleaner too
this lets you skip fptr checks

not currently used on this version, but i want this
patch here so that it can be in the future

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 03:20:07 +01:00
Leah Rowe e8a3cd8cd0 remove unar from dependencies
we use bsdtar now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 02:31:43 +01:00
Leah Rowe 8e8f29c2e5 vendor.sh: remove false error message
mkdst cycles through a bunch of outputted files
when running an extract function, to find the
right file as per defined checksums; if one is
found, it can still show errors for the others,
leading the user to think something is wrong.

remove their fear by removing this benign error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 02:29:04 +01:00
Leah Rowe 4075c8be38 vendor.sh: use bsdtar, not unar
unar is buggy and crap

and bsdtar has superior licensing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 01:56:05 +01:00
Leah Rowe e527820ceb vendor.sh: don't use unrar
the only practical way to use it is to to use
the non-free version; currently used as a
fallback if unar fails.

however, i'm also going to scrap unar and
use bsdtar instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 01:45:36 +01:00
Leah Rowe 7b297a44ce config/git: Support building libarchive
This is for bsdtar, which we will use in place
of unar, because unar is not available on all
of the distros, and we had some recent problems
with it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 01:45:36 +01:00
Leah Rowe d4f5fdec06 Merge pull request 'New mainboard: X2E_N150' (#361) from Riku_V/lbmk:x2en150 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/361
2025-09-28 01:25:27 +02:00
Riku Viitanen b4c3bafb0e New mainboard: X2E_N150
Patch in Gerrit: https://review.coreboot.org/c/coreboot/+/89281
Not working: USB3 ports only work at USB2 speeds.

IFD:
Modified the original by:
- Removing Device Exp2 region (empty anyway)
- Enlarging the BIOS region to use this freed space
- Setting the HAP bit in PCHSTRP55 using a fork of
  me_cleaner: https://github.com/XutaxKamay/me_cleaner

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-28 02:21:15 +03:00
Leah Rowe 9da4fa64a6 coreboot/default: allow alderlake fsp in releases
i delete unneeded fsp modules in releases, to cut down
on the tarball size. so, currently, only kabylake fsp
is distributed.

i'm now also allowing alderlake fsp, because riku has
sent a patch adding an alderlake machine to libreboot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-27 15:56:39 +01:00
Leah Rowe c9d6143e20 gru bob/kevin: make u-boot bootflow timeout 8secs
not 30secs

it's 8 seconds on x86

8 is more reasonable. 30 feels too long.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 13:33:36 +01:00
Leah Rowe fa6c3512d6 rom.sh: remove TODO note
the return is necessary when release=n while doing
release builds, because it prevents a build error
since the given images don't exist in that scenario.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:25:13 +01:00
Leah Rowe 574fd30cde inject.sh: don't exit from patch_release
return instead. xbmk's coding style specifically
prohibits anything other than x_ or err from
running "exit".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:21:40 +01:00
Leah Rowe 4fbafaaa46 init.sh: remove comment in pybin
the following checks on the path mitigates the
lack of error handling in the findpath command
that sets pypath.

this was all thought of when i initially wrote
this code. it's perfectly fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:14:45 +01:00
Leah Rowe 204e310f5a get.sh: remove unnecessary check in try_copy
the check for whether a file is present is unnecessary,
because the following cp command would also print the
file name if it doesn't exist, and exit with the same
non-zero status.

let cp do the work.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:13:17 +01:00
Leah Rowe b4fbdb448d get.sh: rename try_file to try_fetch
the previous function name was misleading, because
this tries multiple methods including git and curl.

therefore, this was renamed to match what it dose.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:12:21 +01:00
Leah Rowe e42cb4f4cd xbmk: tidy up some if statements
this is an extension of the previous work to unroll
most of the condensed code lines.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-26 00:09:46 +01:00
Leah Rowe f5060232e1 init.sh: remove TODO note
on further inspection, the following check ensures that the
python version number is 3.

if anything went wrong, the possibility alluded to in the
comment wouldn't actually matter in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-25 23:54:16 +01:00
Leah Rowe 0303167e25 init.sh: create TMPDIR *after* suid check
otherwise, it may get created as the root user, disabling
further use of lbmk until manual user intervention.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-25 02:26:48 +01:00
Leah Rowe 1a74172a17 release.sh: use cache src on release builds
use what's in cache/clone/ from the main directory

this speeds up the build process

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-25 02:25:59 +01:00
Leah Rowe 6bb4e2c72a init.sh: remove symlink check on XBMK_CACHE
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 23:34:12 +01:00
Leah Rowe dc722b5bb8 init.sh: switch back to old TMPDIR checks
the new check is still retained, to the extent that
the lock file still contains the TMPDIR string, and
it's checked whether this changed during execution.

however, the current TMPDIR handling is over-engineered
and prevents the re-use of project source caches when
doing release builds; this means that the release builds
happen much more slowly, especially for slow internet
connections.

this change *fixes* that bug. now release builds once
again re-use the main cache/ directory.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 23:26:11 +01:00
Leah Rowe 4686ba8a4a make notices a bit more readable
add line breaks, so that the license and author are
visually separated. this makes it easier to read.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 20:14:51 +01:00
Leah Rowe 5a8f350bc7 release.sh: fix typo in script: ./mk, not ./mx
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 18:19:48 +01:00
Leah Rowe 8347e2c85d xbmk: cleanup of recent code refactoring
be a bit less pedantic about if else clauses. leave the
big ones still with then on separate lines, where else
is specified.

also unroll a few condensed code lines where i missed
a few.

sloccount 2303 in lbmk. that's still only slightly bigger
than libreboot 20260907 which was 2180, and still much
smaller than libreboot 20230625 which was 3322.

this is *without* the condensed codelines, so now the only
thing that's reduced is the overall amount of logic present
in the build system.

and i should clarify that lbmk is presently much more powerful
than both of those two versions (20160907/20230625).

the 2016 one is useful for comparison historically, since that
was the last major version of libreboot prior to the great
second coming of leah in 2021; and the 2023 june release was
basically the last one before the great audits of 2023 to
2025 began.

not to brag (not much anyway), but all of this means that lbmk
is an insanely efficient build system, considering all the
features it has and what it does.

i unrolled the condensed code style in lbmk, making the scripts
a lot easier to read, because i received complainst about the
condensed style previously used; nicholas chin and alper nebi
yasak both told me that it sucked, and riku viitanen had hinted
at that same fact several months prior.

so hopefully now, lbmk is a bit nicer. those and other people
often find it challenging to challenge me because for reason
they assume i'll get upset and fly off the handle, but it's the
opposite. i want constant criticism, so that i know to improve!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 13:19:23 +01:00
Leah Rowe 03bf6c185b mk: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 08:53:24 +01:00
Leah Rowe 0275c60111 get.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 08:40:45 +01:00
Leah Rowe 193001bc71 init.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 06:54:36 +01:00
Leah Rowe ace167445f inject.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 03:13:42 +01:00
Leah Rowe 94ab695457 lib.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-24 02:15:41 +01:00
Leah Rowe 8d5d6a3e2a mrc.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-23 12:19:47 +01:00
Leah Rowe 45c4d4045c release.sh: unroll condensed code lines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-23 12:18:15 +01:00
Leah Rowe f5c91ff0ee rom.sh: unroll condensed code lines
ditto to last commit

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-23 11:47:25 +01:00
Leah Rowe e282586427 tree.sh: unroll condensed commands
i went further than in the previosu commit. in this
commit, i also provide indentation inside subshells,
to make it clearer that soomething is being done
inside a subshell.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-23 05:55:18 +01:00
Leah Rowe 8b3f476b57 vendor.sh: unroll condensed code lines
this is part of a general effort to make lbmk
easier for novices to understand.

more commits to follow (one for every script).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-23 02:34:00 +01:00
Leah Rowe 6b796e2b4c init.sh: make TMPDIR *after* calling xbmkpkg
otherwise, running ./mk dependencies as root will
create xbmkwd/ (temporary directories) as root,
which will then prevent non-root instances of lbmk
from being able to make temporary files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-21 19:52:14 +01:00
Leah Rowe 2c02b17810 lenovo/t440p: add a target with 4mb cbfs
this is exactly the same as the normal t440p config,
except that cbfs is 4mb instead of 8mb.

this is useful when externally updating libreboot,
or unbricking; it could also be used for lazier
installation, where you only flash the 2nd chip
without doing a disassembly to get at the other one,
if the user didn't care about neutering the ME.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-19 16:48:05 +01:00
Leah Rowe c11c5a7a14 Revert "xbmk: don't use backticks for command substitution"
This reverts commit 4999a49de3.
2025-09-18 23:35:12 +01:00
Leah Rowe 14bcb3a6fa config/dependencies: cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-18 14:55:52 +01:00
Leah Rowe fe301a019b vendor.sh: add missing error handle on sha512sum
it's still outputting to a file, with an error handle
there, but use of x_ on the sha512sum command itself
adds further assurance of reliability.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-17 17:27:39 +01:00
Leah Rowe c734a6e757 tree.sh: fix bad variable reference
we didn't want to say a variable name here.
we only wanted to say "trees".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-14 19:23:40 +01:00
Leah Rowe 995963baf4 xbmk: much more verbose error messages
use the new functionality in err(), whereby a given
function name and arguments can be provided, for
debugging purposes.

something similar was already done in a few places,
and replaced with this unified functionality.

this patch will make xbmk much easier to debug, under
fault conditions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-13 13:27:47 +01:00
Leah Rowe 7bed68f5b7 lib.sh: use xprintf in err()
if more than one argument is provided, it is interpreted
as a command, and the command is outputted.

this means that now for example, where you have:

ls -l foo | err "could not list directory"

you could do:

ls -l foo | err "could not list directory" "$@"

this would show all the arguments given to the calling
function that tried to run "ls"

let's say that function was called bar, you might do:

ls -l foo | err "could not list directory" bar "$@"

right now, it's not easy to provide good debug info
where err is used, unless it was called with x_, which
provides the command/arguments that was bugging out.

with this, we now have an easy and readable/maintainable
way to do the same thing everywhere in xbmk.

this will now be done, in a follow-up commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-13 12:09:55 +01:00
Leah Rowe edcf8cead8 lib.sh: use xprintf in x_
don't echo the arguments

this new logic shows quotes, in error outputs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-13 11:50:44 +01:00
Leah Rowe 333739961a lib.sh: check args for errors in fx_ and dx_
check that there are at least two arguments, and ensure that
they are not empty.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-13 11:47:10 +01:00
Leah Rowe ce5127e46b inject.sh: add missing semicolon in case
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 12:16:33 +01:00
Leah Rowe 0deac58e41 vendor.sh: tidy up apply_deguard_hack()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 11:26:19 +01:00
Leah Rowe c738698cca vendor.sh: tidy up extract_intel_me()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 11:20:35 +01:00
Leah Rowe e9c7338cda vendor.sh: clean out 7ztest on startup
otherwise, some files from a previous me.bin scan
might still be there, which could lead to the wrong
me.bin being found.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 10:55:18 +01:00
Leah Rowe 07cda7fa12 vendor.sh: remove unnecessary rm -Rf command
this file being deleted was never created.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 10:53:38 +01:00
Leah Rowe 4999a49de3 xbmk: don't use backticks for command substitution
the newer way handles escaped characters better, and it
can be nested more easily. it's also more readable.

personally, i prefer the old way, because it's more
minimalist, but it occurs to me that a lot of people
nowadays don't know about backticks, but they do know
of the modern way.

to make the code more readable, i have modernised it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-11 10:29:59 +01:00
Leah Rowe 5cfe54b06d Revert "inject.sh: put tmpromdel in xbtmp, not cache/"
This reverts commit a444910bf2.
2025-09-09 19:59:46 +01:00
Polarian 9d32af58eb Update arch dependencies
* unifont was split into pcf-unifont and psf-unifont
* mipsel packages have dropped the cross prefix

Signed-off-by: Polarian <polarian@polarian.dev>
2025-09-09 14:01:52 +01:00
Leah Rowe 269fa65b93 init.sh: write-protect the lock file on startup
you can still remove it with the -f flag on rm, but
xbmk only does that on exit from the main parent
instance, or after each build stage in release.sh

because of this, the user could still manually override
the lock file; this would cause running instances of lbmk
to restart wrongly as parent instances.

there's no way to fix any of this, but users don't normally
put -f in their rm commands.

however, this is also a preventative bug fix. if a bug
is ever caused in the future, where the lock file is
created erroneously, the write protection will prevent that,
so long as *it* is still done.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-09 11:56:36 +01:00
Leah Rowe dea587a16f Revert "git/grub: use codeberg as the main mirror"
This reverts commit d06d6a1905.
2025-09-07 19:43:08 +01:00
Leah Rowe c3e52bc2ee Revert "change grub git again"
This reverts commit 1e07c4eb02.
2025-09-07 19:37:23 +01:00
Leah Rowe a00f4153c6 Revert "vendor.sh: put _pre_dest in xbtmp, not cache/"
This reverts commit 69934d18cc.
2025-09-07 19:13:50 +01:00
Leah Rowe 2873ed5e7e Revert "vendor.sh: put appdir in xbtmp"
This reverts commit 4c74311eae.
2025-09-07 19:13:36 +01:00
Leah Rowe 1e07c4eb02 change grub git again
this time to source hut.

for some reason, *grub* is slow no matter what repo
provider i host it on??

i tested srht just now, and it seems ok. let's use that.

i'm *paying* for this sourcehut account, so it better be
good!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 18:33:21 +01:00
Leah Rowe 53491bdca2 tree.sh: don't combine remkdir/cd gnupath
it's stupid. separate them, to make the code readable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 17:49:12 +01:00
Leah Rowe c4cd9c08df release.sh: delete xbmkwd on src tarballs
the previously deleted tmp/ directory was a relic
from prior to recent tmpdir changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 17:45:36 +01:00
Leah Rowe 4c74311eae vendor.sh: put appdir in xbtmp
do away with redundant variable "vendir"

the "appdir" directory is for files extracted from
vendor updates, which are then further processed to
create the real files that we need, such as me.bin
images processed via me_cleaner.

thus, appdir should go in xbtmp.

the appdir currently clutters vendorfiles/, which is
not ideal.

we want it to be that the vendorfiles/ directory only
contains the final firmwares.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 17:34:24 +01:00
Leah Rowe a444910bf2 inject.sh: put tmpromdel in xbtmp, not cache/
cache/ is meant for permanent cached files, not for
temporary files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 17:28:19 +01:00
Leah Rowe 23fb10c3f5 mk: include mrc.sh before inject.sh
and vendor.sh before mrc.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 17:04:58 +01:00
Leah Rowe 69934d18cc vendor.sh: put _pre_dest in xbtmp, not cache/
XBMK_CACHE (cache/) is meant for permanently cached
files, not temporary files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 15:26:35 +01:00
Leah Rowe 4475b4db4b init.sh/tree.sh: put PATH dirs in xbtmp
e.g. gnupath, xbmkpath

these currently go in XBMK_CACHE/, which is bad
because they're meant to be temporary.

XBMK_CACHE is for permanent files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 15:24:02 +01:00
Leah Rowe f5e8483f41 init.sh: bail if date is non-GNU (for now)
We currently use GNU-only options in the date command,
when initialising a Git repository.

This isn't a problem in practise, on non-GNU implementations
if not initialising a Git repository, because it's only
used in that situation.

In practise, only those systems with GNU coreutils and libc
are used to compile releases, so this is OK for me at least.

Future portability improvements will correct the issue, and
then this error check can be removed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 14:20:21 +01:00
Leah Rowe 882a6917bc lib/init.sh: sanitize the version string
the release functions in release.sh rely on the
version string *not* being a path containing slashes.
just a single string e.g. "foo", not e.g. "foo/bar"

this is because several checks there make that
assumption. in practise, we always ensure that tags
and such do not contain these characters.

however, someone else working on their own version
of xbmk might not know of this design flaw, so let's
try to correct it in code.

we can add more filtering as designed, in the relevant
function (xbmk_sanitize_version).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 14:06:57 +01:00
Leah Rowe 1c02f2a770 release.sh: put vdir in xmtmp, not XBMK_CACHE
XBMK_CACHE is meant for permanent cached files, not
temporarily files.

the temporary release files are copied upon successful
return, to their rightful place under release/

this new change also reduces the chance of race
conditions, if multiple xbmk instances are used; while
not yet supported as a use-case, this is a goal for a
future design change.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-07 13:37:02 +01:00
Leah Rowe 5096e0040f mk: hardened PWD check (deny symlinks)
we check if the first argument is "./mk" and bail if not,
which forces you to be in the xbmk work directory.

however, this check is flawed because symlinks were still
possible.

this patch prevents a same-named symlink "mk" pointing to
the real mk from being used.

this hardening is necessary, due to several built-in
assumptions inherent within the design of xbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-05 11:46:16 +01:00
Leah Rowe d06d6a1905 git/grub: use codeberg as the main mirror
the gnu one is often really slow, for some reason.

use the official gnu mirror only as a backup.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-05 11:16:51 +01:00
Leah Rowe 92ecf145fa get.sh: put tmpgit in xbtmp
similar to the previous failed patch, which tried to
also generate it each time, but that led to issues.

this version of the same change merely maintains the
current hardcoding logic, while putting it in xbtmp.

that way, it's more robustly cleared upon exit from
the parent instance of xbmk.

this also reduces the chance of race conditions,
since it's in a unique place each time, rather than
going in XBMK_CACHE.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-05 03:59:50 +01:00
Leah Rowe ddbefea475 Revert "get.sh: put tmpclone dirs in xbtmp"
This reverts commit 01a779d4eb.

This commit broke ./mk -d coreboot for vendor files in lbmk.
2025-09-04 15:27:20 +01:00
Leah Rowe aa38608bff Revert "tree.sh: add missing colon at the end of trees()"
This reverts commit 568887cd5e.

This commit broke ./mk -d coreboot for vendor files in lbmk.
2025-09-04 15:27:07 +01:00
Leah Rowe f6d5b44757 Revert "vendor.sh: looser error handling on find_me"
This reverts commit c9a81292e5.

This never caused actual issues. Keep it strict.
2025-09-04 15:26:56 +01:00
Leah Rowe c9a81292e5 vendor.sh: looser error handling on find_me
i added a stricter check recently, but this broke
extraction on fresh lbmk clones, tested when doing
a release-build test.

loosen it up again, but only for find_me

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 07:37:32 +01:00
Leah Rowe 769d645c2a init.sh: create separate lock in release dirs
this removes the current hackiness, preventing
build errors since xbtmp is now based on xbmkpwd,
which changes when we're in the release dir.

XBMK_RELEASE is still set accordingly, so this
will still work the same way.

this is also cleaner in general.

XBMK_CACHE is still the same, so the release work
directory still re-uses files from the main work
directory, rather than re-creating them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 07:01:24 +01:00
Leah Rowe 568887cd5e tree.sh: add missing colon at the end of trees()
this is because when using chained commands at the end
of functions, sometimes you have to explicitly terminate
the line.

the way i do it in this patch is common across the
build system, to mitigate this sh quirk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 06:49:38 +01:00
Leah Rowe 01a779d4eb get.sh: put tmpclone dirs in xbtmp
and generate them, don't hardcode them - this reduces
the chance of race conditions, which we have seen in
the past and which current execution flow in xbmk even
mitigates in a few places, by doing things in a certain
order.

this change makes the code more robust and easier to
maintain.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 06:33:31 +01:00
Leah Rowe 0d107ad872 xbmk: remove xbloc, re-use xbtmp instead
we no longer separate them. xbloc was the on-disk
tmp directory, whereas xbtmp used to be in /tmp
which we assumed to be tmpfs (it may not be, but
often is on many workstation setups - and our
documentation recommended doing this).

as mentioned in the previous commit, benchmarking
shows little speed difference using tmpfs /tmp
versus on-disk /tmp, for our purposes at least.
therefore, the handling of tmp files is being
greatly simplified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 06:29:20 +01:00
Leah Rowe 64b69907ab init.sh: put TMPDIR inside xbmkpwd, not /tmp
This way, all operations will be done inside the xbmk
work directory. This is being done, so that I can then
reliably sandybox certain commands in future commits,
for example the "rm" command.

This will also allow me to unify the location of all
temporary files, in future commits. I previously used
the /tmp directory because it's tmpfs-based on many
setups, and this is great for performance. However, in
practise, I never noticed any difference in performance
when benchmarking it (testing /tmp on-disk versus tmpfs).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 06:02:57 +01:00
Leah Rowe 8a8be1dec9 get.sh: remove unnecessary variable, repofail
it is entirely unused

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 04:02:49 +01:00
Leah Rowe 3af4c7bcb1 rom.sh: simplify rmodtool copy handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 03:35:48 +01:00
Leah Rowe bec4c63b25 release.sh: remove support for the -d flag
this lets you change the directory for outputted
release files, versus the default "release" directory.

this code is buggy, because it could let you overwrite
a part of xbmk or worse - and checking for such bad
usage would require a lot more code.

knobs are for nobs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 03:31:34 +01:00
Leah Rowe e059614589 get.sh xbget: don't use eval for file/dir checks
the actual code works fine, but it's quite hacky.

there are times when use of eval is acceptable; this
is not one of those times, but i'd used it in this
instance when i was being a bit crazy about code size
reductions during my audits.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 03:26:26 +01:00
Leah Rowe 934e89510e vendor.sh: remove unnecessary error check
setting a variable in this way will never result in
an error. this is a relic from a prior re-factoring
versus older versions of the code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-02 00:19:37 +01:00
Leah Rowe b1f485d0f2 release.sh: fix broken release lock file handling
we need to copy the main lock file, rather than creating
a new, empty one. this is because the new lock file
handling requires it, and the release lock file will
be used during release builds.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-01 08:46:20 +01:00
Leah Rowe ed84d33e59 lib.sh and rom.sh: stricter mktemp usage
error out under fault condition

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-01 08:14:49 +01:00
Leah Rowe 40f064ae33 inject/vendor.sh: stricter set + usage
set - as soon as possible, for example in the extract_me
function.

we only turn off error handling when certain error-prone
tasks are performed, and mitigations are in place after
these commands run to make sure that the result was valid.

this is because in some cases, we want certain buggy behaviours
to be permitted, with errors handled in a more fine-tuned way,
because sh can sometimes be much stricter depending on the
implementation; otherwise, we almost always rely on -e -u in
most of the build system.

this mainly affects the vendorfile insertion logic.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-09-01 07:08:47 +01:00
Leah Rowe 24a8226fee init.sh: tidy up xbmk_set_env
this is a general function that sets variables,
but there are many types of variables to be set.

rather than have all the logic inside this function,
handle it in subfunctions called by xbmk_set_env.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 21:37:30 +01:00
Leah Rowe 7c04cd37b5 init.sh: tidy up xbmk_child_set_tmp
the checks of xbmk cache/threads is unrelated.

this has been moved back to the calling function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 21:33:00 +01:00
Leah Rowe 2d20be3d99 init.sh: remove unnecessary lockfile checks
we don't need these anymore, because we now know
whether or not the lock file exists in these cases.

this is because child/parent instance determination
is now done based on the presence of that file, rather
than how TMPDIR is set; and TMPDIR is now set accordingly,
via more robust logic as in previous patching.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 21:30:29 +01:00
Leah Rowe c148b220d8 init.sh: move TMPDIR handling to own functions
this makes xbmk_set_env easier to read

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 21:28:12 +01:00
Leah Rowe f96bf2b2cd init.sh: prevent race condition with TMPDIR
it is extremely unlikely to occur, but this patch reduces
the likelihood even further. that unlikely occurance is:

when creating a TMPDIR, it's possible that it was already
created before. this is OK on child instances, where that
is the intended behaviour (unified TMPDIR), but not for
parent instances.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 20:39:07 +01:00
Leah Rowe bbce74d78a init.sh: MUCH safer TMPDIR handling
we previously checked whether xbmk was running a child
instance, based on the initialisation of TMPDIR, but
this relied on unreliable string substitutions, which
could not be made inherently reliable. there were also
no checks on whether the given TMPDIR, even if correct,
was a directory or whether it was a symlink; there were
also no checks on whether it changed.

now with this change, child instances are detected by
the presence of the lock file. the parent instance
writes the generated TMPDIR location in that file, and
this is checked again in the child instance, to ensure
that the TMPDIR didn't change; it also errors out if
the TMPDIR doesn't exist or if it is a symlink.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 20:25:00 +01:00
Leah Rowe ad58364e18 mk: simplify the main script check
it's still not perfect, but now it's unambiguous.

the previous generic check was written based on the
fact that xbmk's main script used to also be called
via several symlinks, which is no longer the case.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-31 18:27:09 +01:00
Leah Rowe 09646783a5 config/dependencies: add --no-install-recommends
use this on the debian dependencies, otherwise it installs
a bunch of extra crap e.g. xorg crap, in some circumstances,
which someone probably won't want when they're in a minimal
chroot or something.

reported by ron nazarov. thank you ron!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-30 07:22:38 +01:00
Leah Rowe d9011da0eb inject.sh: redirect stderer to /dev/null FIRST
for the grep command, we must ensure that errors are
suppressed *BEFORE* outputting to a file. depending
on the sh implementation, the previous code might
have begun outputting to a file before suppressing
errors.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-29 04:44:52 +01:00
Leah Rowe 50a0bac01c vendor.sh: tidy up extract_intel_me
too many chained commands. break it out a bit.

this makes it more readable, without changing behaviour.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-26 07:01:35 +01:00
Leah Rowe 9fb707b49b rom.sh: safer use of cat in copyps1bios
the output to a file also has its own error handling,
but x_ can be used safely to provide additional assurance
that the script will break if an error occurs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 18:31:33 +01:00
Leah Rowe 89238c0579 tree.sh: tidy up check_cross_compiler
group related operations together, without whitespace.

declare all variables at the start of the function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 17:38:29 +01:00
Leah Rowe 07562e3f28 tree.sh: don't re-check xgcc needlessly
instead, create a file indicating that a given xgcc
target had already been built successfully, within a
given coreboot tree.

this will considerably speed up the building of release
archives, especially when there are a lot of boards.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 16:02:40 +01:00
Leah Rowe 66f1be1ba7 tree.sh: check xgcc AFTER checking elfdir
if e.g. elf/coreboot/default/w500_16mb contains readied
images from before, crossgcc is still being checked.

if you already built all the coreboot images, and wanted
to just modify all the payloads for example, this would
result in a much slower re-build process, because it is
needlessly re-checking crossgcc every time.

by doing it this way, we need up the testing of payloads
quite considerably, during xbmk development.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 15:49:10 +01:00
Leah Rowe c12965f8e4 lib.sh: safer pad_one_byte function
instead of copying to a temp file and then
concatenating with padding back to the main
file, we concatenate and create the temp file,
then move the temp file back to the main file.

this is because cat can be quite error prone,
more so than mv, so this will reduce the chance
of corrupt files being left behind depending
on the context (of course, the latter is often
avoided due to xbmk's design, which emphasises
use of temporary files first).

this matches the same design used in the function
unpad_one_byte, which creates the deconcatenated
output in a temporary file first, moving it back.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 15:38:29 +01:00
Leah Rowe 7e6f52ec0a vendor.sh: use pad/unpad functions
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 03:59:35 +01:00
Leah Rowe 616ef52a6f lib.sh: additional error handling on cat
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-23 03:48:27 +01:00
Leah Rowe 41945a2220 tree.sh: Delete files *before* updating hashes
The current logic deletes old project files e.g. sources,
but *after* updating the project hash.

This means that if a deletion fails, and the directory
is still there (e.g. src/coreboot/default/) afterward, it's
now a tainted archive, yet the hash has been updated, so
subsequent runs of the build system will cause unknown
errors.

This patch fixes that, by first copying the new hash to
a temporary file. *Then*, deletions are handled, and the
final hash file is updated afterward.

The code is now a bit more bloated as a result, but this will
reduce the risk of tainted sources being handled under fault
conditions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-10 14:50:32 +01:00
Leah Rowe d44c143846 tree.sh: rename hashtype to hashname
since it's the name, e.g. "default", referring to a
project tree (in this example, coreboot/default).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-10 14:17:57 +01:00
Leah Rowe 289c4e1c2f tree.sh: rename hashname to hashdir
since it's only ever used as a directory name

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-10 14:15:55 +01:00
Leah Rowe b31f2387ee tree.sh: rename hashvar to badhashvar
now the code that uses it makes a bit more sense
to the casual reader.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-10 14:13:47 +01:00
Leah Rowe 2c24b94d80 tree.sh: rename function and remove comments
the new function names make the comments redundant. the
code is now self-explanatory.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-10 14:12:48 +01:00
Leah Rowe ef79b11082 tree.sh: don't delete builds if tree==target
in that case, the previous tree-wide check will cover
it, so the current logic wastes computational time.

this patch therefore somewhat optimises the code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-04 09:33:33 +01:00
Leah Rowe 1c5c28f2cb tree.sh: re-add comments to check_hashes
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-04 09:16:58 +01:00
Leah Rowe 3d5a6bccae tree.sh: unified project hash handling
the target/project hash checks are basically identical,
so let's unify them under a single function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-02 11:31:28 +01:00
Leah Rowe a499d5bba2 rom.sh: Don't run mkhelpers if release=n
This fixes the following error on ./mk release:

cp: cannot stat 'elf/coreboot/default/d510mo/libgfxinit_txtmode/coreboot.rom': No such file or directory

I recently re-wrote the handling of coreboot images, and
I overlooked this entirely. When a given target specifies
release=n, it has to be skipped, so builds are not done.

The "release" variable is already checked, in mkcoreboottar.

Let's also put it in the other mkhelper functions, to make sure
there are no errors.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-08-01 05:32:25 +01:00
Leah Rowe 84a1ff85b0 coreboot/default: rev 9e41c7cec7, 18 July 2025
T480/T480s patches were dropped since they're included as
part of the upstream code now.

This update brings the following upstream changes:

* 9e41c7cec7 soc/intel/cmn/block/fast_spi: Lock DMA before exiting coreboot
* c1d45ef93b mb/google/trulo/var/kaladin: Update touchpad settings
* f13f980e03 mb/google/trulo/var/kaladin: Add fw_config probe for storage
* 50c39b3a22 mb/google/trulo/var/kaladin: Fix Type C function
* f0d50aa404 commonlib/include/commonlib: Add volatile qualifier
* 3828153ea5 soc/intel/xeon_sp/gnr: Use official microcodes
* a87cbcd3c9 soc/intel/xeon_sp/ibl: Config ACPI base using PMC device
* 480ac15044 util/cbfstool: Prevent overflow when sorting fit table entries
* bf4f08f3b6 mb/hp/snb_ivb_desktops/variants/compaq_8300_elite_sff: early VGA output
* dd19f6bc5a util/cbmem: Extract devmem and common code to separate files
* def945f3ba soc/intel/apollolake: Measure the IBBL, IBB and OBB from the bootblock
* fbb0738272 mb/google/brox/var/lotso: Decrease cpu power limits
* ce88b12420 mb/google/ocelot: Set correct TPM I2C bus for all ocelot model variants
* e050e2fbfc mb/google/ocelot/var/ocelot: Remove irrelevant comment
* b66c8ea3d3 mb/google/ocelot/var/ocelot: Remove Bluetooth Audio offload
* d5d633f607 mb/google/ocelot/var/ocelot: Update variant.c
* 3b069d320c cbfs: Add a function to wait for all CBFS preload operations to complete
* a7710ed8fd Documentation: coding_style: Add *long* to long multi-line comment example
* 19d7104d85 drivers/intel/touch: Use recommended short multi-line comment style
* 451988d015 mb/google/trulo/var/pujjolo: Fix Goodix touchscreen function
* 542e52c126 soc/qualcomm/x1p42100: Optimize memory layout for X1P42100
* 2e47bd50f2 mb/google/trulo/var/pujjocento: Add 6W and 15W DPTF parameters
* 6e4f4538bb soc/intel/{tgl,adl,mtl,ptl}: Default to Software Connection Manager
* 1b8dd662a9 soc/qualcomm/x1p42100: Add PCIE Clock support for x1p42100
* 4d3def7514 soc/mediatek/mt8189: Fix timer reset in BL31 by using time_prepare_v2
* d898653b0e soc/meidatek/mt8196: Extract common timer code for reuse
* d1c096a5b9 src/soc/mt8196: Correct systimer register offset
* edaa67d0c9 mb/google/skywalker: Add thermal init flow in romstage
* 6aec09875b soc/mediatek/mt8189: Add thermal driver
* 5cc4b9e6ce soc/amd/common/cpu/noncar: Add bootblock overlap detection
* 67cd138df9 soc/intel/apollolake: Add missing header in measured_boot.h
* a428481574 mb/google/nissa/var/dirks: Update power limits
* 55ae0d8a37 mb/google/nissa/var/baseboard/nissa: Add power limits functions
* 82163aedc6 soc/amd/common/block/cpu/noncar: Move BSS and DATA out of PT_LOAD
* 6405641647 mb/google/fatcat: Use same mainboard part number for all fatcat variants
* c5613469ae device: Make a note that SeaBIOS doesn't support above 4G MMIO
* ced4c09359 soc/intel/xeon_sp/gnr: Implement get_mmio_high_base_size
* 7100f226ca vc/intel/fsp/fsp2_0/wcl: Add FSP headers for WCL FSP
* 5171098814 drivers/qemu/bochs: Allow building for non-x86 architectures
* d233b6c903 payloads/external/LinuxBoot/Makefile: Fix build prerequisite
* 502d19be89 payloads/external/LinuxBoot/targets/u-root.mk: Add missing prerequisite
* cba0f0b8b9 payloads/external/LinuxBoot: Rename build target
* 43a54e3b1b util/amdfwtool: Add binary parsing
* 85da3954d0 .gitmodules: Ignore changes make by what-jenkins-does
* 397c5fe420 Documentation: Add a mainboard entry for the Lenovo T480/T480s
* 6768586353 Documentation: Add information about the deguard utility
* ad8b738af0 mb/lenovo: Add ThinkPad T480 and ThinkPad T480s
* 96e381766e ec/lenovo: Add support for MEC1653 EC
* 2181b02765 util/smmstoretool: Properly initialise the authenticated variable header
* 3058464263 util/smmstoretool: Add support for creating variable from file contents
* b49f567e45 util/smmstoretool: Ensure that the FVB header isn't too large
* a6fbaa47ea util/smmstoretool: Clarify the `auth_vars` field
* 3698517d82 mb/amd: Use mec152x tool
* 5a0953614b util/amdtools: Add ec_usb_pd_fw
* e63620012c util: Add Microchip EC FW tool
* 0b5ce9d9f0 soc/intel/apollolake: Add support for IFWI Measured Boot
* 289cff3423 soc/intel/apollolake: Load the IBB into CAR
* 2408695dd3 soc/intel/apollolake: Add a loader for the IBB
* 61b66e9a81 soc/intel/apollolake: Add function to clear MCA in Bank 4
* 138402e7ff soc/intel/apollolake: Create IBB, IBBL and OBB
* 61b4e1983c mb/google/fatcat: Update PCH reset power cycle duration to 1 second
* e9af95d5ab soc/intel/pantherlake: Configure FSP UPDs for minimum assertion widths
* 79bd154b49 drivers/genesyslogic/gl9763e: Mask replay timer timeout of AER
* a775bfc2b2 soc/mediatek/mt8189: Specify MTKLIB_PATH for building BL31
* e583b2ffb7 soc/meidatek/mt8196: Extract common thermal code for reuse
* f62734976c mb/dell: Convert E6400 into a variant
* 8d60bf9975 mb/google/fatcat: select MIPI pre-prod if PTL pre-prod SoC is set
* 2f978ecab3 mb/google/fatcat: Choose platforms with pre-prod Panther Lake SoC
* eb1483ba17 soc/mediatek/mt8189: Increase SCP clock frequency from 26MHz to 416MHz
* 9c5557f982 util/abuild: Add --sequential-boards option
* 9e5234feee payloads/external/edk2: Drop our toolchain override
* 8d9e18a122 payloads/edk2: Indicate whether edk2-platforms is available
* 626fd50a94 mb/google/fatcat/var/kinmen: Enable ISH
* e7cefe4f41 soc/mediatek/mt8196: Move srclken_rc related code to common
* e9731f8925 soc/intel/pantherlake: Add configs for pre-production silicon
* 8687b3d108 mb/google/trulo/var/pujjolo: Add ISH firmware config
* 722c9314c7 mb/google/dedede/var/awasuki: Add 2 HYNIX modules to RAM id table
* 6082bd7711 ec/lenovo/h8: Rework invalid temperature reporting
* 621b1061d0 ec/lenovo/h8: Add Kconfig to select use of Thermal Zone 1
* bc116b8797 ec/lenovo/h8: Replace chip regs for BT/WWAN detect with Kconfig options
* d9169ef617 ec/lenovo/pmh7: Add CFR objects for existing options
* 45d9973a6d ec/lenovo/h8: Add CFR objects for existing options
* ce5a1e8a51 mb/google/brox: Create caboc variant
* d745d38393 soc/intel/cmn/block/fast_spi: Add DMA support
* 8e666c367d soc/qualcomm/x1p42100: Update boot critical firmware memory layout
* e35c784847 Doc/gfx/libgfxinit.md: Fix file names in source code references
* 0e682859e7 payloads/external/U-Boot: Upgrade from 2024.07 to v2025.07
* 8b52167a9f arch/x86: Add support for cooperative multitasking on x86_64
* 569b7a8861 Docs/releases: Finalize 25.06 release notes
* 5db8bf0cfa mb/trulo/var/pujjolo: Enable USB3 WWAN device
* e013c9586c mb/trulo/var/pujjolo: Modify mipi camera parameters
* 7b8520ab69 mb/trulo/var/pujjolo: Update fingerprint enable pin status
* f74027d5ae mb/google/nissa/var/craask: Add elan touchscreen support
* 396a883a0c mb/hp/snb_ivb_desktops: Include PS/2 controller ASL code for MS Windows
* 18c067d392 mb/google/fatcat/var/kinmen: Add Synaptics touchpad
* 2f5b384ba5 soc/mediatek/mt8189: Enable EARLY_MMU_INIT to improve boot time
* d5bce8c420 mb/hp: Add HP 260 G1 DM Business PC (Haswell)
* 48c6f66fa4 mb/google/ocelot: Update TPM_TIS_ACPI_INTERRUPT value in Kconfig
* 0660fe50de mb/google/ocelot: Update GPE configuration
* 5b3063802e mb/google/fatcat/var/kinmen: Fix touchscreen IRQ setting
* 6c4e502fdd mb/google/nissa/var/pujjocento: Reduce PL4 to 38W with no battery
* 6e92554ab6 mb/trulo/var/pujjolo: Modify FW_CONFIG for mipi camera
* 4f5f75da34 mb/trulo/var/pujjolo: Correct USB3 Type-A OC pins
* a1dfd39e04 mb/google/fatcat/var/kinmen: Add AUDIO_UNKNOWN and probe for ALC721
* 306544b427 mb/google/fatcat/var/francka: Add AUDIO_UNKNOWN and audio probes
* edf47d44cd mb/google/fatcat/var/fatcat: Disable Audio for invalid Audio FW_CONFIG
* 454079c3bc lib/cbfs: Ensure cache buffer alignment in ramstage
* 0ef670a66a mb/google/ocelot/var/ocelot: Configure FPS related changes
* 6ab37f0e0e mb/google/ocelot/var/ocelot: Add FW_CONFIG for Finger Print
* 3f61df24d5 mb/google/ocelot/var/ocelot: Add FW_CONFIG for Storage
* bb95a26cda mb/google/ocelot/var/ocelot: Add FW_CONFIG for WiFi
* 410b3c697f mb/google/ocelot/var/ocelot: Add FW_CONIG for ISH
* afaf4c3d7b mb/google/brya/variants/pujjolo: Update ISH GPIOs and add ISH firmware name
* f6de6f8933 mb/google/fatcat: Drop redundant SNDW GPIO mapping
* 584fdd6572 soc/mediatek/mt8196: Remove redundant bootblock.c from Makefile.mk
* 24ea6937f2 soc/intel/apollolake: Add the Kconfig options for IFWI Boot Profile
* c68645cd88 util/supermicro: Fix mem leak in get_line_as_int error conditions
* 05396238da libpayload/drivers: Fix mem-leak in cbmem_console error condition
* 1219981177 drivers/emu/qemu: Add a comment about fw_cfg assumptions
* d866e72b3a mb/google/fatcat/var/kinmen: Set CRFP to use GPIO for status
* 4367daae20 drivers/spi: Add option to generate proper PowerResource _STA
* 03c331399c mb/google/nissa/var/craask: Add focaltech touchscreen support
* b3d7c40fb5 mb/siemens/mc_rpl: Remove code for board_id
* 5de16ed1b8 mb/siemens/mc_rpl: Remove unused embedded controller code
* a1067ec6de mb/siemens/mc_rpl: Remove unneeded code to select a VBT name in CBFS
* 463cda84d2 mb/siemens/mc_rpl: Remove unused Type-C data definition
* dcbe591201 mb/siemens/mc_rpl: Use SPD data from HWInfo instead of from CBFS
* 6c059f8af3 IVB mainboards: Drop 1024M option for gfx_uma_size
* 3b61dbaa06 mb/asus/p8z77-m_pro: Remove incorrect gfx_uma_size options
* 2b7115b139 mb/hp/snb_ivb_desktops: Add gfx_uma_size options up to 512MB
* d99769bbde mb/hp/snb_ivb_desktops/variants: enable 4th sata port on tested models
* 95784dbafb mb/google/ocelot/var/ocelot: Add FW_CONFIG for Audio
* f323adb19f soc/mediatek/mt8189: Increase SPI NOR clock rate from 26MHz to 52MHz
* 689af47b52 commonlib: Add pvmfw related timestamps
* f1d06a5ad4 soc/intel/common/block/memory: Provide a way to use SPD data from memory
* 11b1dc0a97 Reapply "util/cbmem: Consolidate CBMEM and coreboot table access"
* 13f1c6118e Documentation: Update cbmem.md with more information
* 07267d19ce arch/x86/postcar_loader: Add comment line for reloc_params assignment
* e94ac6e655 mb/google/nissa/var/pujjocento: Reduce PL4 to 38 W with no battery
* 2eaec1b53a sbom: Fix build with merged bootblock and romstage
* 267f08dafd MAINTAINERS: Add KunYi Chen as maintainer for LattePanda Mu

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-23 04:09:47 +01:00
Leah Rowe cc2f08e7bb Revert "coreboot: rev 8b52167a9f 13 July 2025, rebase t480"
This reverts commit 32dfdfbb01.

The update caused an issue on T480:

Backlight comes on, then off, then on, then off, repeatedly, and
never gets to the payload. Will have to investigate further.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-14 11:26:58 +01:00
Leah Rowe 32dfdfbb01 coreboot: rev 8b52167a9f 13 July 2025, rebase t480
coreboot/default: update t480 patches to set 38

see: https://review.coreboot.org/c/coreboot/+/83274/38

I was previously using:
https://review.coreboot.org/c/coreboot/+/83274/25

Matt DeViller aka MrChromeBox, recently took over the
patch set, tidying up and re-factoring the code so that
it's more suitable for upstream. Several hacky behaviours
were removed, for example the MEC1663 code is now its own
code in coreboot, rather than being bolted onto the H8s code.

Certain T480-specific changes made to global parts of the
coreboot code are now done only on the tree itself.

Mate Kukri has also tested Matt's recent updates. More
testing still needed on Nvidia dGPU models, which never
worked before anyway; Intel GPU models should still work.

Thermas zone handling is also improved. See patch:
https://review.coreboot.org/c/coreboot/+/88415/1
https://review.coreboot.org/c/coreboot/+/88416/2

Functionally, this is mostly the same as before. As I said,
Matt has focused on code cleanup, so that the board can be
properly upstreamed. Hopefully this will be merged soon,
in coreboot-main.

Besides this, the following upstream changes were imported:

* 8b52167a9f arch/x86: Add support for cooperative multitasking on x86_64
* 569b7a8861 Docs/releases: Finalize 25.06 release notes
* 5db8bf0cfa mb/trulo/var/pujjolo: Enable USB3 WWAN device
* e013c9586c mb/trulo/var/pujjolo: Modify mipi camera parameters
* 7b8520ab69 mb/trulo/var/pujjolo: Update fingerprint enable pin status
* f74027d5ae mb/google/nissa/var/craask: Add elan touchscreen support
* 396a883a0c mb/hp/snb_ivb_desktops: Include PS/2 controller ASL code for MS Windows
* 18c067d392 mb/google/fatcat/var/kinmen: Add Synaptics touchpad
* 2f5b384ba5 soc/mediatek/mt8189: Enable EARLY_MMU_INIT to improve boot time
* d5bce8c420 mb/hp: Add HP 260 G1 DM Business PC (Haswell)
* 48c6f66fa4 mb/google/ocelot: Update TPM_TIS_ACPI_INTERRUPT value in Kconfig
* 0660fe50de mb/google/ocelot: Update GPE configuration
* 5b3063802e mb/google/fatcat/var/kinmen: Fix touchscreen IRQ setting
* 6c4e502fdd mb/google/nissa/var/pujjocento: Reduce PL4 to 38W with no battery
* 6e92554ab6 mb/trulo/var/pujjolo: Modify FW_CONFIG for mipi camera
* 4f5f75da34 mb/trulo/var/pujjolo: Correct USB3 Type-A OC pins
* a1dfd39e04 mb/google/fatcat/var/kinmen: Add AUDIO_UNKNOWN and probe for ALC721
* 306544b427 mb/google/fatcat/var/francka: Add AUDIO_UNKNOWN and audio probes
* edf47d44cd mb/google/fatcat/var/fatcat: Disable Audio for invalid Audio FW_CONFIG
* 454079c3bc lib/cbfs: Ensure cache buffer alignment in ramstage
* 0ef670a66a mb/google/ocelot/var/ocelot: Configure FPS related changes
* 6ab37f0e0e mb/google/ocelot/var/ocelot: Add FW_CONFIG for Finger Print
* 3f61df24d5 mb/google/ocelot/var/ocelot: Add FW_CONFIG for Storage
* bb95a26cda mb/google/ocelot/var/ocelot: Add FW_CONFIG for WiFi
* 410b3c697f mb/google/ocelot/var/ocelot: Add FW_CONIG for ISH
* afaf4c3d7b mb/google/brya/variants/pujjolo: Update ISH GPIOs and add ISH firmware name
* f6de6f8933 mb/google/fatcat: Drop redundant SNDW GPIO mapping
* 584fdd6572 soc/mediatek/mt8196: Remove redundant bootblock.c from Makefile.mk
* 24ea6937f2 soc/intel/apollolake: Add the Kconfig options for IFWI Boot Profile
* c68645cd88 util/supermicro: Fix mem leak in get_line_as_int error conditions
* 05396238da libpayload/drivers: Fix mem-leak in cbmem_console error condition
* 1219981177 drivers/emu/qemu: Add a comment about fw_cfg assumptions
* d866e72b3a mb/google/fatcat/var/kinmen: Set CRFP to use GPIO for status
* 4367daae20 drivers/spi: Add option to generate proper PowerResource _STA
* 03c331399c mb/google/nissa/var/craask: Add focaltech touchscreen support
* b3d7c40fb5 mb/siemens/mc_rpl: Remove code for board_id
* 5de16ed1b8 mb/siemens/mc_rpl: Remove unused embedded controller code
* a1067ec6de mb/siemens/mc_rpl: Remove unneeded code to select a VBT name in CBFS
* 463cda84d2 mb/siemens/mc_rpl: Remove unused Type-C data definition
* dcbe591201 mb/siemens/mc_rpl: Use SPD data from HWInfo instead of from CBFS
* 6c059f8af3 IVB mainboards: Drop 1024M option for gfx_uma_size
* 3b61dbaa06 mb/asus/p8z77-m_pro: Remove incorrect gfx_uma_size options
* 2b7115b139 mb/hp/snb_ivb_desktops: Add gfx_uma_size options up to 512MB
* d99769bbde mb/hp/snb_ivb_desktops/variants: enable 4th sata port on tested models
* 95784dbafb mb/google/ocelot/var/ocelot: Add FW_CONFIG for Audio
* f323adb19f soc/mediatek/mt8189: Increase SPI NOR clock rate from 26MHz to 52MHz
* 689af47b52 commonlib: Add pvmfw related timestamps
* f1d06a5ad4 soc/intel/common/block/memory: Provide a way to use SPD data from memory
* 11b1dc0a97 Reapply "util/cbmem: Consolidate CBMEM and coreboot table access"
* 13f1c6118e Documentation: Update cbmem.md with more information
* 07267d19ce arch/x86/postcar_loader: Add comment line for reloc_params assignment
* e94ac6e655 mb/google/nissa/var/pujjocento: Reduce PL4 to 38 W with no battery
* 2eaec1b53a sbom: Fix build with merged bootblock and romstage
* 267f08dafd MAINTAINERS: Add KunYi Chen as maintainer for LattePanda Mu

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-14 03:19:31 +01:00
Leah Rowe 122d009af1 coreboot/default: probe EDID twice in libgfxinit
this mitigates buggy video converters e.g. displayport
to hdmi, where sometimes the display doesn't come up.

sometimes you have to probe them twice. this is apparently
what linux does, according to nicholas chin's interpretation.

this is a really quick and dirty patch that worked for
Noisytoot on IRC, tested on their Dell OptiPlex 5050 SFF
which they are porting; the port otherwise works, and this
patch enables them to use their displayport adapter.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-13 15:21:46 +01:00
Leah Rowe dac3d6d06a rom.sh: Don't build coreboot utils if dry=":"
This fixes a build error when doing ./mk release, after
a regression caused by the last few commits.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-10 10:43:53 +01:00
Leah Rowe 6f7525a5b3 cache coreboot builds in elf/ again
This was a problem when I did it before, because individual
target builds weren't automatically re-compiled when needed.

The recent design improvements in lbmk enable this to be
done again.

Cached images in elf/ have no payloads, so they are a liability,
therefore they are padded by one byte to prevent flashing. This
solves the problem that the previous caching had.

With this change, modifying payloads can be tested without
needing to re-build coreboot each time.

The cached coreboot builds are also automatically re-built when
needed, which is another improvement this time, compared to
the last time coreboot builds were cached in this manner.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-10 04:26:31 +01:00
Leah Rowe 7c6c9ff547 tree.sh: delete individual target builds if needed
Detect when a config changes. This is done even if the
entire tree doesn't change.

This is already done per-tree if files change, but
individual project files don't change.

For example, if a grub.cfg changes, the given cached
build for that GRUB tree isn't deleted. Same thing if
a given U-Boot config doesn't change.

This patch fixes a longstanding design flaw of lbmk,
making auto-re-builds more reliable. This complements
another recent change, that deletes all target builds
of a given tree when the tree changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-10 02:00:13 +01:00
Leah Rowe fb95230a4c tree.sh: Remove redundant deletion
Target builds go inside a common directory for
the given tree now, which gets deleted, thus
deleting all target builds of that given tree.

Therefore, the deletion being removed is redundant.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-10 01:07:55 +01:00
Leah Rowe e25bca2ef7 T480/T480: Drop redundant PcieRpEnable from dt
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-08 17:57:53 +01:00
Leah Rowe cc82b733d3 tree.sh: Place target builds under tree/target/
as opposed to target/

for example:

image the command:

./mk -b u-boot amd64coreboot

This would put the U-Boot binaries here:
elf/u-boot/amd64coreboot/default/

With this change, they now go here:

elf/u-boot/x86_64/amd64coreboot/default/

This solves a problem that existed previously, where
you could modify a given tree in a multi-tree project,
but cached builds for targets branching separately off
of each tree would not be deleted, and thus not re-built.

This accomplishes such a result, without needing to
further check hashes of individual targets.

The latter will still be done, in a future change, because
this change doesn't fix another problem:

If you change a given config, e.g. targetname "foo" which
uses tree "bar", elf/foo/ would not be removed automatically
for re-build.

So this change only deletes individual target builds when
their master tree changes.

Where the target and tree are the same, this also means
elf/tree/target/

for example: seabios/default would create binaries in:

elf/seabios/default/default/

not:

elf/seabios/default/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-08 13:38:59 +01:00
Leah Rowe 9541dfcefa rom.sh: bump pcsx-redux copyright date to 2025
it's 2019-2025 now, not 2019-2024, because i recently imported
new pcsx-redux upstream changes that go up to June 2025.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-08 10:39:54 +01:00
Leah Rowe 91a63ccd1f hppro3500: enlarge CBFS to match the BIOS region
i enlarged the BIOS region in a previos commit, but I forgot
to enlarge CBFS. it's the policy of lbmk to enlarge CBFS when
possible, after applying a truncated ME configuration.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-08 01:59:13 +01:00
Leah Rowe ed839db0a0 pcsx-redux: bump rev 8f8cc3d5, 20 June 2025
Many other changes were imported into the wider pcsx-redux
tree, but we're mainly concerned with the OpenBIOS diffs.

This update brings in the following upstream changes, for
PCSX-Redux OpenBIOS:

* 35de25bb Fixing realloc's edge case.
* b8a9080d OpenBIOS: Annotate sio0/driver.c with enums
* c7cec91e OpenBIOS: Refactor card driver
* 4e42a6b6 Move OpenBIOS SIO to a seperate header and add enums
* a50434c5 Remove OpenBIOS dead sio1 code
* 9c3d3a1e Renaming readAligned to load32Aligned.
* 1b8312e5 [Chores] Format code
* 8b9df484 Simplifying openbios allocation scenario.
* a658a18d Brand new memory allocator.
* ba48f01b Bumped copyright date to 2025
* 64b63a13 Bumped copyright date to 2025
* 3ada28e3 [Chores] Format code
* d25af104 Fixing setjmp/longjmp attributes.
* e51ffafa Assign _bu_init alias to 0x55.
* ae1dd51e Split out the common thread structures to its own file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 21:07:19 +01:00
Leah Rowe dd65f55b29 coreboot/default: bump rev 812d0e2f62, 5 Apr 2025
There are *many* excellent changes. These changes are of note,
for Haswell mainboards (raminit improvements, courtesy Angel Pons):

* d5854e4139 Haswell NRI: Implement COMP offset optimisation
* f14880934b Haswell NRI: Use final timings after basic training
* ab29f52ee2 Haswell NRI: Measure per-task execution time
* 4ae9a79d8d Haswell NRI: Remove unused `SPD_LEN` define
* 0c5286ba34 Haswell NRI: Tidy up REUT subsequence programming
* 7766228798 Haswell NRI: Deduplicate PCODE mailbox functions

My GMP fixes have been removed, because upstream did
similar fixes which accomplish the same result.

This brings in the following upstream changes:

* 812d0e2f62 Documentation/lib: Update Timestamp documentation
* d461627668 payloads/Kconfig: Allow compression for Linux payloads
* f3ca3aa16b util/cbfstool/cbfs-payload-linux: Copy segments when compression fails
* 29440057b0 mb/starlabs/{adl_n,twl}: Don't use the IOT FSP
* eaf76d2dd1 vc/intel/fsp2_0/twinlake: Update FSP headers
* d5854e4139 Haswell NRI: Implement COMP offset optimisation
* 2739c4b773 SBOM: Change makefile to get versions from build.h
* a4156f99ff soc/intel/ptl: Add Wildcat Lake CPU ID to platform reporting
* 9f73b04074 soc/intel/pantherlake: Add new MCH ID for Wildcat Lake
* 167c771bc5 mb/google/fatcat/var/francka: Enable audio codec ALC722/ALC1320
* d8455dfbf6 mb/trulo/var/pujjolo: Change wifi SAR id fw config bits
* a9e97268fe crossgcc: Fix acpica base url version
* dabc200abb mb/lenovo/m900_tiny: enable power LED blink in S3 and S4
* cb86b9a089 mb/lenovo/m900_tiny: Put options in CFR cbtable
* 26d6da4533 mb/lattepanda/mu: Correct UART1 pinmux for native mode
* 2ec9a9f17d mb/lattepanda/mu: Update eDP/HDMI in devicetree
* 3cfa24c1bf mb/lattepanda/mu: Enable PMC drivers
* c3dba4da2b mb/lattepanda/mu: Add flashmap definition
* b5db9bcc9d soc/intel/alderlake: Enable USB3 HSIO related parameters for USB3 GEN2 support
* da49da6c82 soc/intel: Add Arrow Lake-S/HX IDs
* 8cec500968 mb/google/skywalker: Configure firmware display for eDP panel
* 78a89d4d70 soc/mediatek/mt8189: Extract code to disable secure mode from DDP driver
* 8d8d0f9746 soc/qualcomm/x1p42100: Add Clock support for x1p42100
* 20c2813891 soc/qualcomm/common: Update QUP register structure for QUP v3.2
* d24c4086e1 Documentation: Add Ramstage Bootstates
* 10d01fc2de Documentation: Add Threads
* faf0f29f8d mb/google/ocelot: Update EC host command range for variants
* ac4dfa5762 mb/hp/snb_ivb_desktops: Add Compaq Pro 6300 MT/SFF variant
* 984c64295b drivers/crb/tpm: Add new method to retrieve base address
* 1e8e5d902a mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer
* 5993dd6ef5 Documentation: Add Timers, Stopwatch, and Delays
* 4f1f502fd5 soc/mediatek/mt8189: Add PI image loader in ramstage
* e3ffa3c14f soc/meidatek/mt8196: Move PI image related code to common
* e96bf7e094 soc/qc/x1p42100: Support to generate Bootblock as multi ELF
* ae5810e358 util/qualcomm: Add MBN v7 format support
* 626c5364b8 tree: Use boolean for PcieRpSlotImplemented[]
* a90a7e0aed mb/google/bluey: Specify ROM size per board variant
* 0c9204046a mb/google/bluey: Update SPI flash vendor selection
* d636b38577 soc/qualcomm/x1p42100: Select ARM64_USE_ARM_TRUSTED_FIRMWARE
* 17abedaef6 include/smp/node: Drop unused is_smp_boot
* c0413336bc acpi/acpi.h: Use boolean
* 9be383b855 drivers/lenovo/hybrid_graphics/chip: Use boolean when appropriate
* f33507c1d8 mb/{google/zork,novacustom/mtl-h}: Use true/false for boolean
* ae282fe502 drivers/generic/bayhub: Use boolean for power_saving
* 0a94fcd2db crossgcc: upgrade binutils from version 2.43 to 2.44
* 316f76635f soc/mediatek/mt8189: Use pmif_spmi_v2 for MT8189
* f3bd8b7a07 soc/mediatek/pmif_spmi: Move pmif_spmi_force_normal_mode() to common
* ef10e93e0a tree: Replace scan-build by clang-tidy
* 6707e9281c mb/google/brox: Update cpu power limits
* f1aa0a175b util/crossgcc: Build compiler-rt using runtimes
* b0e0c688c8 buildgcc: Use -d to check libstdc++ include directory
* f2fed71533 crossgcc: Upgrade acpica from 20241212 to 20250404
* 07a8737cbd crossgcc:Initialize OPT_LDFLAGS to avoid unset variable in IASL build
* ad9bfd4243 crossgcc: Always update HOSTCFLAGS from GMP headers if already built
* c3f5d7c1ee crossgcc: Upgrade MPFR from 4.2.1 to 4.2.2
* a3ea1cb542 util/crossgcc: Upgrade CMake from 3.31.3 to 4.0.3
* f9cde87f5a crossgcc/buildgcc: Fix GMP-6.3.0 build with GCC 15 using proper prototypes
* 35d6ee9223 crossgcc/buildgcc: Remove invalid option for CMake
* bd36a4a465 util/lint: Remove missing dirs from checkpatch linter
* a0f2e42879 util/lint: Improve final newline check
* 6cb9efa19a util/lint: Ignore opensil for Kconfig linter
* 5228b3ef7b util/lint: Ignore binary files for cb lowercase linter
* 58d450d2dc util/crossgcc/buildgcc: Reorganize toolchain version variables
* baf28f8668 mb/trulo/var/pujjolo: Add GPE configuration
* eb749f2416 spd/lp5: Add SPD for MT62F2G32D4DS-023 WT:C
* 731bea2fc1 mb/lattepanda/mu: Make VBT compatible with ADL-N FSP IPU25.3
* 6b7f697309 util/amdfwtool/amdfwread.c: Properly error out in relative_offset()
* 4a99023e0f util/amdfwtool/amdfwread.c: Remove APOB_NV special case
* 000ac2cc38 util/amdfwtool/amdfwtool.c: Use physical address for APOB_NV
* d0355cb647 util/amdfwtool: Move APOB_NV quirk to amdfwtool.c
* 6fa44461e7 mb/google/fatcat/var/kinmen: Add Fn key scancode
* dd7956bfc5 mb/google/ocelot: Update GPIO table
* 1222c704b5 mb/google/fatcat/var/felino: Add pull high setting on GPP_V12 and NC_LOCK GPP_F09
* 61d74dc8f7 payloads: Propagate SPI flash address mode flag to libpayload
* 8dec5fcaf8 drivers/spi: Add 4-byte address mode flag to lb_spi_flash
* a01c368a8a drivers/spi: Refactor 4-byte addressing mode handling in SPI flash
* 30e7e604fb mb/google/fatcat/var/fatcat Align I2S and DMIC pad configuration
* 9fe1546ffe Docs/releases: Update 25.06 release notes
* 5c281529ea mb/trulo/var/pujjolo: Add FW_CONFIG for mipi camera
* e5e79de8cc mb/trulo/var/pujjoquince: Add Fingerprint function
* 0dcea61e7c cbfstool: Add multi ELF support
* 6a02f2d4a7 util/qualcomm: Add script to concatenate ELF images
* 3a0b6f625a mb/google/trulo/var/pujjocento: Enable WiFi SAR table
* 64a79d23e8 mb/trulo/var/pujjoquince: Add SD card function
* b726a9c7e9 mb/google/fatcat: Create new fatcatite4es variant
* e7984f39eb mb/google/fatcat: Create new fatcatnuvo4es variant
* cdf0c76dc8 mb/google/fatcat: Create new fatcat4es variant
* 8e5bdde028 mb/intel/ptlrvp: Add support for H58G66BK7BX067 memory
* 110aebb4d2 mb/google/nissa/var/riven: Add focaltech touchscreen support
* bc8876d56d Revert "soc/intel/xeon_sp/uncore.c: mark TSEG/SMM region as reserved"
* 64d4888349 mb/google/dedede/var/magolor: Generate SPD ID for CXMT CXDB4CBAM-ML-A
* cc116e08aa mb/google/nissa/var/quandiso: Add touchscreen FTSC1000 support
* 35648dc37b acpi: Add _func suffix for callback functions
* 03be570994 mb/google/rauru: Remove unused get_oled_description
* cc0a410ff5 soc/mediatek/dp: Correct eDP register settings for dptx_v2
* 056405a10d mb/google/ocelot: convert variants for use with ES silicon
* 4ef51ffbd7 mb/google/skywalker: Add panel driver in mainboard
* cdb49c4d2e soc/mediatek/mt8189: Add ddp driver to support eDP output
* d8fc5eba2d soc/mediatek/mt8189: Add eDP driver
* cfd0b4dd20 soc/mediatek/mt8189: Change msdcpll default freq to 384MHz
* a60c5d205b mb/google/nissa/var/meliks: Initialize display signals on user mode
* f846ec1e37 mainboard/google/fatcat: Set OEM footer logo bottom margin
* 97f92d5c69 drivers/intel: Add support for configurable footer logo bottom margin
* 3e0d8a2f2c mb/google/bluey: Enable 4-byte addressing mode
* 5568bee055 drivers/spi: Support forced 4-byte address mode via 0xB7 command
* a66d2d41f5 mb/lenovo/m900/devicetree.cb: Use OC6 enum
* f14880934b Haswell NRI: Use final timings after basic training
* 0e5d1d29bd soc/intel/skylake: Expand USB OC pins enum to OC7
* 1f28803dcd mb/trulo/var/kaladin: Create kaladin variant
* 1c2978dba6 mb/google/dedede/var/awasuki: Add ChangXin modules to RAM id table
* 912161e52d spd/lp4x: Modify parameters of SPD for NT6AP1024F32BL-J1
* 47f1b798e4 util/amdfwtool/amdfwtool.c: Remove APOB_NV src address check
* c7fe471482 mb/novacustom/mtl-h/var/dgpu: Add NVIDIA dGPU ASL code
* 24d8e6f35e Revert "mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE"
* cf7159af64 mb/siemens/mc_ehl3: Limit eMMC speed mode to DDR50
* 68ede7b860 mb/google/nissa/var/meliks: Configure Acoustic noise mitigation
* ea3cc3231c mb/intel/ptlrvp: Remove power limit constraints
* cae47dfd44 soc/intel/pantherlake: Correct DRHC and SATC in DMAR table
* e58883aace soc/intel/pantherlake: Refactor VR Fast Vmode I_TRIP threshold settings
* abbf549558 mb/google/fatcat: Add support for new Panther Lake IDs
* 57bffed893 soc/intel/pantherlake: Add new PCI and CPU IDs
* 59fce656b1 soc/intel/pantherlake: Enable Thermal Design Current for various SKUs
* 5a2de49baa soc/intel/cmn/blk/power_limit: Add helper functions to romstage
* 2207a4b59a vc/intel/fsp/fsp2_0/pantherlake: Add TDC current limit configuration
* efa24540b0 drivers/wifi/generic: Implement Bluetooth PRR DSM functions
* d92b6163e7 drivers/wifi/generic: Implement Wi-Fi PRR DSM functions
* 81d7bc386e soc/intel/cmn/blk/cnvi: Set WFDL default value to 50 ms
* 1be1ccb42e soc/intel/cmn/blk/cnvi: Use WFDL field for Wi-Fi PLDR reset delay
* ff46501d6d soc/intel/cmn/blk/cnvi: Correct generated ACPI code in comments
* 782ae11bc7 soc/intel/cmn/blk/cnvi: Add _PRR method for Bluetooth CNVi Reset
* 23f5df6eae mb/google/nissa/var/yavilla: Add H58G66CK8BX147 to RAM ID table
* 4a2c61a8a0 soc/qc/x1p42100: Allow building QC platform without upstream blobs
* 2a09db3c29 drivers/intel: Refactor logo rendering with helper functions
* 57d29ebd74 vc/google/chromeos: Don't pack `cb_plus_logo.bmp` if footer is present
* ef051256dc mainboard/google/fatcat: Drop logo_valignment selection
* dfeaead9f2 drivers/intel: Add horizontal logo alignment for splash screen
* ced9f91ae9 soc/intel/cmn: Improve comments for fw_splash_vertical_alignment enum
* d309a9dfa8 drivers/intel/fsp2_0: Suppress OEM footer in low-battery mode
* 4373eea5d8 {lib, drivers/intel}: Add splash screen footer
* be5609bdaf lib: Introduce a new function `bmp_load_logo_by_type()`
* a1dbb4076c lib: Add support for different bootsplash types
* f48865ab9a drivers/intel/fsp2_0: Refactor bitmap loading and GOP BLT conversion
* f3f9c0bd8e soc/intel/ptl: Add PCIe ACPI support for Wildcat Lake SoC
* ba715b3d25 mb/google/nissa/var/guren: Add SPD ID for MT62F512M32D2DR-031 WT:B
* 43b6f44e22 soc/mediatek/mt8189: Remove ulposc1 hardware calibration
* f63016c36f soc/mediatek: Unify DPTX swing/preemphasis API
* df91698b11 soc/mediatek/mt8196: Refactor mt8196 eDP driver for better code sharing
* 03fca0f0b4 mb/google/brox: Enable support for Realtek EC
* c8eb52c10c ec/google/chromeec: Modify Realtek EC initialization timing
* e2ac46bcc7 spd/lp5: Add SPD for hynix H58G66CK8BX147
* 812379f500 soc/mediatek/common: Move map_to_lpddr_dram_type() to common for reuse
* 7c19b1fa58 mb/google/skywalker: Run MTK FSP binary in ramstage
* 89e4fff2d3 crossgcc/buildgcc: introduce RISCV_ISA_SPEC for RISC-V ISA specification
* 620c8d9f71 mb/google/brask/var/constitution: Generate RAM ID for B3221XM3BDGVI
* 57b12d2171 spd/lp4x: Generate initial SPD for B3221XM3BDGVI
* 7c0da94aeb mb/google/brya/var/pujjoga: Add and select VBT
* bcd569faf1 mb/google/skywalker: Create variant Baze
* fb2c834f7c mb/trulo/var/pujjolo: Fix p-sensor function
* a7cd5c8c6b mb/trulo/var/pujjolo: Enable USB3 functions
* 2c53151c0c mb/trulo/var/pujjolo: Enable Ax211 wifi function
* ad78fc535a mb/trulo/var/pujjolo: Add single ram configuration
* f941b51e0e soc/mediatek/mt8189: Correct MFG MUX OPP init setting
* a1d9b69f47 soc/qc/x1p42100: Add metadata files for shrm and cpucp
* b369756680 util/qualcomm: Add script to extract a segment from ELF
* 19d1604fd7 mb/google/bluey: Update flash layout
* b9aae6180b mb/google/nissa/var/meliks: Link touchscreen device with display panel
* 6e58c0148b Reland "libpayload: arm64: Reduce DMA allocator space to 1MB"
* f18420b6a9 mb/google/fatcat: Create new felino4es variant
* 992ba78142 mb/google/fatcat: Create `felino` model for easier variant integration
* afbc9126f9 mb/trulo/var/pujjolo: Update GPIOs and probe SD card to fix S0ix suspend
* b3b1809764 mb/google/octopus: Correct channel count for DMIC
* 9accaa7238 mb/google/poppy: Correct channel count for DMIC
* 41e09a5c59 mb/google/fizz/var/karma: Correct channel count for DMIC
* fed7ad967a mb/google/reef: Correct channel count for DMIC
* 686dea9883 mb/google/glados: Correct channel count for DMIC
* ea6f150d9d soc/intel/cmd/blk/cnvi: Correct conditional logic for CNVI readiness
* 29dd511628 soc/intel: Move CNVI sideband definitions to SoC-specific files
* ea8a3e685f soc/intel/cmn/blk/cnvi: Add descriptive comments for PRRS and RSTT
* d17ace2c1b soc/intel/cmn/blk/cnvi: Remove hardcoded offset in OperationRegion
* bb3a484e36 soc/intel/*/acpi: Move the BASE ACPI method to northbridge
* 3c88e629d9 mb/google/brox/var/lotso: Generate RAM IDs for lotso
* 1bdf89d78c device/device_util.c: Complete function documentation
* bc84e1ba42 soc/intel/cmn/acpi: Refactor `SPCO` ASL method
* 4bf0f4fab3 mb/google/fatcat/var/felino: Add PIXART touchpad to devicetree
* 8269a89d32 mb/google/fatcat/var/felino: Add Synaptics touchpad to devicetree
* 4d9dfb63bd Documentation: fix broken flashrom.org link
* 3696fea4e0 mb/google/ocelot: add BOARD_GOOGLE_OCELOTMCHP
* 6ebd30bf7d mb/google/ocelot: add BOARD_GOOGLE_OCELOTITE
* da122fe8f5 mb/starlabs/*: Use PLTRST for PCH Strap GPIOs
* 7f03e3bd6c drivers/efi/efivars: Change printk level from ERROR to DEBUG
* c740786f12 drivers/gfx/generic: Use 'noop_read_resources'
* b1759c9bd6 mb/starlabs/starlite: Adjust the Flash Map to match the Twin Lake IFD
* cc1f0e5c90 mb/starlabs/starbook: Disable TME_KEY_REGENERATION_ON_WARM_BOOT
* 9381dd0cbf soc/intel/meteorlake: Make TME_KEY_REGENERATION_ON_WARM_BOOT selectable
* 9b91d50fc1 mb/siemens/mc_rpl1: Add GPIO configuration
* f44b19f2dc soc/intel/pantherlake: Fix ACPI can't tag data node error
* fad0064377 soc/intel/ptl: Add UFS support for Wildcat Lake SOC
* 3a065dbbfc mb/google/nissa/var/yavilla: Add H58G56CK8BX146 to RAM ID table
* 98f1886c89 mb/google/nissa/var/yaviks: Add H58G56CK8BX146 to RAM ID table
* 3711be4e18 soc/intel/xeon_sp: Use Kconfig to define SPI_BASE_ADDRESS
* ad05c65d72 soc/intel/xeon_sp: Initialize SPI before using it
* b4f2a51533 libpayload/arch/arm64/mmu: Fix missing CBMEM in used ranges
* 6da913bd46 docs/security/vboot: Update supported board list
* a0e6fd9a95 Documentation: Add coreboot release 25.09 template
* d4a33638f5 mb/trulo/var/pujjolo: Change dram id table
* 2ee72eaab1 soc/intel/pantherlake: Update CONSOLE_UART_BASE_ADDRESS Kconfig value
* 25385df017 vc/intel/fsp/ptl: Update PTL header files to FSP 3182_01
* 2286134002 mb/google/fatcat/var/felino: Configure CAM_VDD_EN_SOC GPIO to restore camera function
* 486604360c mb/google/ocelot: add BOARD_GOOGLE_MODEL_OCELOT
* f6926dc8a5 mb/google/nissa/var/pujjoniru: Update DTT settings for thermal control
* bb022f18d5 mb/google/dedede/var/awasuki: Add 2 NANYA modules to RAM id table
* 4ef1258436 spd/lp4x: Add Nanya memory part
* 99c138ec50 soc/mediatek: Don't attempt de-assert PERST# without pci_root_bus
* b9754131a6 mb/google/ocelot/var/ocelot: Update initial overridetree settings
* 4199351c1b Revert "libpayload: arm64: Reduce DMA allocator space to 1MB"
* a11eacc204 mb/msi/{ms7d25,ms7e06}/devicetree.cb: Add fan control config
* a069c920f5 mb/msi/{ms7d25,ms7e06}: Mimic the vendor BIOS early SIO init
* 3c23d7b3a9 src/superio/nuvoton: Add HWM initialization code
* ace18dea15 mainboard: Add 2S Intel Birch Stream MiTAC Computing R520G6SB
* 4569adeedc mainboard: Add 1S Intel Birch Stream MiTAC Computing SC513G6
* ab29f52ee2 Haswell NRI: Measure per-task execution time
* 925845c38c mb/google/ocelot: Update Kconfig
* c796c68dec mb/google/ocelot: Update MAINBOARD_PART_NUMBER
* b322d30944 mb/google/brya/var/moxie: Enable RTD3 for SSD to resolve S0ix issue
* f85f7d7aed mb/intel/beechnutcity_crb: Use host address for BiosRegionBase
* 4d3dc433f9 mb/intel/avenuecity_crb: Use host address for BiosRegionBase
* 881fe9cef6 soc/intel/alderlake: Add cpuid_to_adl mapping for Core 3 N350 SoC
* 08c8a74170 mb/trulo/var/pujjolo: Add MB usb-a port3 function.
* 317affb0ad mb/trulo/var/pujjolo: Enable Elan touchscreen function.
* de259ad970 mb/trulo/var/pujjolo: Enable s0ix function
* 712dfb3761 Revert "util/cbmem: Consolidate CBMEM and coreboot table access"
* 30865c2fb1 mb/amd/birman_plus: Skip i2c_early init
* f2e488cfbf mb/google/fatcat: Add power limit overrides for H204 and H404 SKUs
* 1537c89e8d soc/intel/cmn/block/power_limit: Enforce variant PL4 for Fast VMode
* d9c5cef7f0 soc/intel/pantherlake: Add Fast VMode PL4 Power Limit configuration
* b879342fe6 soc/intel/pantherlake: Add support for the H204 SKU
* b42842bbe5 mb/google/brox: Add brox_rtk_ec variant
* 73cc8a413a treewide: Work around GCC 15 Werror=unterminated-string-initialization
* d00f5c2d8c mb/google/skywalker: Reset xsphy0 in mainboard_init
* 40bf6c28f8 soc/mediatek/mt8189: Add support for USB port 0 reset
* 26fd33a92a mb/starlabs/starlite_adl/acpi: Fix _GPE callback type
* d14a3e23da mb/starlabs/starlite_adl: Clarify pmc_gpe0_dw0 mapping in devicetree
* 2c0417ea06 mb/starlabs/starlite_adl: Remove duplicate GPP_E12 entry
* 7e711a5bef Reland "soc/mediatek/mt8196: Specify MTKLIB_PATH for building BL31"
* 47f2c17961 mb/starlabs/*: Add CFR option to enable/disable S0ix
* dc3d524d19 mb/starlabs/starlite_adl: Use SoC common CFR forms
* 808c982104 mb/starlabs/starfighter: Use SoC common CFR forms
* 644fd7b7f5 mb/starlabs/starbook: Use SoC common CFR forms
* c7a1539d87 mb/starlabs/lite: Use SoC common CFR forms
* 3f16609ba2 mb/starlabs/byte: Use SoC common CFR forms
* c3be703b71 soc/intel/common/cfr: Add bool option for auto power on
* b3ac5ecdac soc/intel/cmn/block/cfr: Add CFR form for pciexp_aspm_cpu
* 9f8e5ab661 soc/intel/cmn/block/aspm: Use separate option variable for CPU RP
* 4247128e39 soc/intel/cmn/block/aspm: Fix ASPM control for CPU root ports
* b66b7f7860 commonlib/device_tree.c: Add a function that reads FDT ints
* c776d2dbd6 ec/google: Add support for Realtek EC in ChromeOS EC
* 8b54428200 mb/google/nissa: Override GPIO_PCH_WP for pujjocento variant
* 2060f24d60 mb/system76/mtl: Add Darter Pro 11 variants
* c2496bc62e drivers/analogix/anx7625: Add a retry mechanism to decode EDID
* 7b1eac4192 soc/mediatek/mt8189: Enable MUXes for improved peripheral stability
* da54093bb9 Update arm-trusted-firmware submodule to upstream master
* 40c84c2577 mb/starlabs/*: Tidy up the devicetree files
* cb7d2ebe5c mb/starlabs/starbook/{kbl,cml,tgl}: Remove generic.detect from the touchpad
* c4eb645a0b update_submodules: Fix submodule path handling
* 581af94115 ec/dasharo/ec: Add DTT power and battery participants
* f6dd8f534f MAINTAINERS: Add Dinesh as intel/pantherlake and google/fatcat maintainer
* f2310ab35e update_submodules: Prefix commit title with relative path
* 5fcbc709ec mb/google/fatcat/fmap: Add 1 MB from SI_BIOS to SI_All
* 24778a25de mb/trulo/var/pujjolo: Fix gtx functions.
* 619699648f soc/intel/pantherlake: Simplify P2SB and P2SB2 device operations
* beafbfd29a soc/intel/pantherlake: Remove IOE support and references
* 5277bc4efc soc/intel/pantherlake: Resolve memory corruption by using P2SB2 driver
* 61ac238bb5 soc/intel/common/block/p2sb: Add driver for second P2SB device
* 8961f6681f soc/intel/common/acpi/pcie_clk: Fix ACPI conditional compilation error
* 471df8ca5e util/crossgcc/buildgcc: Fix GMP build on GCC 15
* c24a12db86 util/cbmem: Consolidate CBMEM and coreboot table access
* 99e5a386c2 mb/amd/birman_plus/glinda: Add onboard devices
* 033810a7db payloads/libpayload/Makefile.mk: Replace nm with $(NM)
* a1738e87b5 soc/intel/panterlake: avoid SPI access delay
* 359ae67668 elog: Handle elog in later boot phase
* bf330f2dd0 security/vboot: Back up CMOS data later boot phase
* 45febdec26 mb/starlabs/starfighter: Add reset GPIO for the USB Bluetooth
* a9a51f9916 mb/starlabs/starfighter: Add missing ASPM config for the SSD
* 644ebf5ebc mb/starlabs/starbook/{adl,rpl}: Add generic Graphics driver config
* 902df45eab mb/starlabs/starfighter: Remove the overcurrent config
* b872c50f90 mb/starlabs/starfighter: Add generic Graphics driver config
* cfdf5906fd mb/starlabs/starfighter: Tidy comments for board ID GPIOs
* 9950825a2b mb/starlabs/starlite_adl: Remove extra lines
* 6d079d45d1 mb/starlabs/byte_adl: Remove comments for disconnected GPIOs
* f6a45f6856 mb/starlabs/byte_adl: Re-organise GPIOs
* 63f781b508 mb/starlabs/byte_adl: Disconnect unused GPIOs
* 6aeebc4b4b mb/starlabs/byte_adl: Reconfigure PCH Strap GPIOs
* 5f9046cbb4 mb/starlabs/byte_adl: Remove vGPIO configuration
* c589142c28 mb/starlabs/byte_adl: Add the Byte Mk III variant
* 2cb9c3ee46 mb/starlabs/byte_adl: Update the VBT to the Twin Lake version
* ad8ccf4822 Update arm-trusted-firmware submodule to upstream master
* c615de7248 soc/amd/glinda: Don't let OS put debug UART into D3
* 0251e98e9e util/amdfwtool: Do not attempt to continue processing `--help`
* 0af68855c0 mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port
* bba9d27145 mb/google/ocelot: Remove power limit override functionality
* b3776e23a7 ec/google/chromeec: Add SPI/I2C EC communication files to bootblock
* be6787a55e mb/google/skywalker: Add storage types to fw_config
* 0a41779e2e mb/google/skywalker: Add eMMC configuration
* 3e6b47980a mb/google/skywalker: Add support for getting storage id
* de251dd677 soc/mediatek/mt8189: Add support AUXADC
* a283246ef7 soc/mediatek/common: Refactor auxadc driver to support new platform
* 94686e581a mb/google/skywalker: Add DVFS support in romstage
* 8ede4bc67b soc/mediatek/mt8189: Add DVFS driver
* 096ce4b244 soc/mediatek/mt8196: Move dvfs_init() declaration to dvfs_common.h
* 0b1bc3df2c mb/trulo/var/pujjocento: Support x32 memory configuration
* 7690442d88 mb/starlabs/byte_adl: Tidy the Kconfig selections
* ab8339770e 3rdparty/fsp: Update submodule to upstream master
* 8e3adf778b soc/mediatek: Add data_version to ddr_base_info struct
* 0cdd4125be mb/trulo/var/pujjolo: Fix touchscreen function and boot up issue
* 99e0484000 mb/google/bluey: Increase bootblock size to 120KB
* 1840fb49e0 mb/google/trulo/var/pujjocento: Update gpio setting for DDI-B
* 69a067a9d6 mb/google/skywalker: Add RT1019 support for beep sound
* 4caf5131b9 mb/google/skywalker: Add ALC5645 support for beep sound
* 623caa537f mb/google/skywalker: Add RT9123 support for beep sound
* 16ff3b33ce mb/google/skywalker: Add SD card configurations
* 3b68408693 mb/google/trulo/var/pujjocento: Configure USB related settings
* 6c87853a83 mb/google/bluey: Implement board and SKU ID retrieval
* 830a887ecb mb/google/bluey: Add WLAN and SSD PCI devices to devicetree
* 891c208835 soc/qualcomm/x1p42100: Enable basic PCIe support
* a5d99a814a soc/qc/x1p42100: Perform `soc_mmu_init` inside early bootblock init
* 481001e13b soc/qualcomm/x1p42100: Add placeholder for early clock initialization
* 77c6104645 Revert "mb/google/rex: Enable use_gpio_for_status for touchscreen"
* 715e7e51c5 mb/google/fatcat/var/francka: Add support for DMIC0
* c16891ecbd soc/intel/meteorlake: Use CACHE_TMP_RAMTOP for TME exclusion range
* 394dfcaa7b mb/intel/ptlrvp: Handle GPIO support for DDR5 configuration
* 58165618da mb/google/byra/var/craask: Add VBT for HDMI variant
* ab160ca301 mb/google/byra/var/teliks: Add default VBT
* 4d5b32f7f7 mb/google/ocelot/var/ocelot: remove unused gpios
* 0e5757bfa7 mb/google/trulo/var/pujjocento: Update DTT settings for thermal control
* c34baacc72 soc/mediatek/common: Add UFS2.2 and eMMC definitions to storage.h
* f325409784 soc/mediatek/mt8189: Add SD card support
* ae435c014c soc/mediatek/mt8189: Configure and early initialize eMMC
* 91ebbb8d35 mb/trulo/var/pujjolo: Modify pujjolo variant
* aea05e51a7 mb/google/trulo/var/pujjocento: Enable WWAN function
* 47133a716d mb/google/trulo/var/pujjocento: Add P-sensor support
* 04c0527aba soc/mediatek/mt8189: Support different PMIC soluitons for MT8189(G/H)
* 80149f55f7 soc/mediatek/common: Convert spmi_dev_cnt to a function
* dcf403e43a mb/google/skywalker: Configure fingerprint pins
* 508d910ed4 libpayload/arch/mock: Select ARCH_HAS_NDELAY for ARCH_MOCK
* 96ac0224ab pci: Add support for assigning resources to SR-IOV VF BARs
* ba8be19122 mb/intel/ptlrvp: Update Kconfig for PTLRVP_CHROMEEC
* 7cbbf786cc update_submodules: Use relative paths to submodules
* dcc8400e27 mb/google/fatcat/var/felino: Modify GPIOs config
* 99af85ad36 mb/google/puff: Add VBTs for Moonbuggy and Scout variants
* 4ae9a79d8d Haswell NRI: Remove unused `SPD_LEN` define
* 0c5286ba34 Haswell NRI: Tidy up REUT subsequence programming
* 7766228798 Haswell NRI: Deduplicate PCODE mailbox functions
* ae68ef3684 cpu/intel/haswell: Export PCODE mailbox functions
* ddce240d34 cpu/intel/haswell: Clean up Makefile
* 2117ed850f mb/google/ocelot/var/ocelot: fix storage configs for ocelot
* c5488c0d6d mb/google/ocelot/var/ocelot: update gpios
* 6602a4462b mb/google/ocelot/var/ocelot: Enable hda device for AUDIO_ALC721_SNDW.
* 99b6ff25d4 soc/mediatek/mt8189: Add MTK FSP loader in ramstage
* c4fe5e2483 mb/google/skywalker: Pass reset GPIO parameter to BL31
* f59ced2c7c mb/google/fatcat/var/francka: boot up by pressing power button in S5
* df0221e62a libpayload: Protect against trying to use weak symbols in the wrong way
* d27e8ef460 update_submodules: Add an empty log line between each iteration
* d9bd7ce89f mb/google/fatcat/var/francka: Enable audio codec ALC721
* 48fbd99223 mb/google/fatcat/var/francka: Set the default HDA GPIO pin to an NC pin
* 3b975f92c7 soc/intel/pantherlake: Select TME support for the SoC
* 8408bd4863 soc/intel/pantherlake: Add TME configuration
* dc36a725d6 3rdparty/fsp: Update submodule to upstream master
* 1f47b0e018 3rdparty/intel-microcode: Update submodule to upstream main
* 4c446751c6 {commonlib, drivers}: Track firmware splash screen rendering completion
* ccb8b34194 Revert "mb/var/uldrenite: Use VBT with limited resolution for 4GBx32 memory"
* 1a00629ae2 mb/google/skywalker: Set up open-drain ChromeOS pins
* 0f2942b513 mb/google/skywalker: Raise little core CPU frequency to 2.0 GHz
* 0ba0d03140 mb/google/skywalker: Implement regulator interface
* 090bce1042 soc/mediatek/common: Add VMODEM and VSRAM_MD bucks support for MT6359
* c74610afae soc/mediatek/mt8189: Shut down PMIC on power key long press
* d1f7565403 mb/google/skywalker: Notify EC that AP is in S0
* da45a88dd3 util/abuild: Fix checking of missing_arches
* cdcbb71936 mb/google/link: Use chromeec_smi_sleep()
* 885aacf004 mb/google/byra/var/teliks: Add VBT for 11" panel option
* 2ce777f178 mb/google/byra/var/yaviks: Add VBT for yavilla
* 0db4444446 mb/google/byra/var/pujjo: Add VBT for pujjo1e
* 8c3e6ea319 mb/google/nissa/var/pujjocento: Enable touchpad
* 643bba345c mb/google/trulo/var/pujjocento: Enable touchscreen
* 3ecaf04dad mb/var/uldrenite: Use VBT with limited resolution for 4GBx32 memory
* 71ae2c7366 mb/google/octopus: Add VBTs for DOOD and FOOB variants
* 7a703fc1fb mb/google/rex: Select IOM_ACPI_DEVICE_VISIBLE
* 0121d0e3e0 ec/google/chromeec/smi: Clear events before enabling wake mask
* 5a947da94e mb/google/sarien: Update VBT from v221 to v228
* 0fba735482 soc/intel/cmn/blk: Refactor CSE status flag and optimize forced sync
* bb8d069dd3 vc/google/chromeos: Move pvmfw cbmem and enable
* f562992da1 mb/google/trulo/var/pujjocento: Enable EC keyboard backlight
* d281a3c559 mb/google/trulo/var/pujjocento: Configure tcss_aux_ori
* 7150c5e2fe mb/google/skywalker: Create variant Anakin
* aedc177f00 libpayload: arm64: Reduce DMA allocator space to 1MB
* 4ccb4a78c4 libpayload: Use Kconfig instead of weak symbol for arch_ndelay()
* 37513297d3 libpayload: Use Kconfig for architecture memcpy, not weak symbols
* bcbe17dea3 mb/google/skywalker: Configure TPM
* 3d40b7d018 soc/mediatek/mt8189: Increase bootblock size from 60KB to 70KB
* 8d25cf3ae7 soc/mediatek/mt8189: Add SSPM loader
* 8ab9f56470 mb/google/skywalker: Set up SPM in mainboard
* 368eeb7da4 soc/mediatek/mt8189: Add MCUPM loader
* bc3af56fdd soc/mediatek/mt8189: Add SPM loader
* 98782a59e9 mb/google/fatcat/var/kinmen: Add overridetree
* bbcb222f0b mb/google/fatcat/var/kinmen: Update GPIO table
* 743e3a07f5 mb/google/brya/var/nissa: Remove duplicate ACPI device GFX0
* 87110309d4 mt8196: Remove mcupm_plat.h header from mcupm_plat.h
* d6fe379e9c mb/google/ocelot: Enable LP5 and DDR5 memory configuration
* 2985af84c3 mb/google/trulo/var/pujjocento: Add Fn key scancode
* dafd7d6eb9 mb/google/nissa/var/dirks: Deassert RTL8111H's ISOLATE_ODL earlier
* c1df30db18 mb/siemens/mc_rpl: Delete fw_config since it is not used
* 7fbea3175d mb/siemens/mc_rpl: Remove unused gpio and devicetree files
* 8fdf8694e3 mb/siemens/mc_rpl: Remove Chrome OS and EC as they are not used
* e020979993 mb/siemens/mc_rpl: Adjust the flash map file
* 71fb8f63e0 mb/siemens/mc_rpl: Add new mainboard based on Intel's Alder Lake RVP
* 918f21b72d drivers/spi/winbond.c: Add W25Q64JV signature
* 278a6d2682 mb/google/trulo/var/pujjocento: update hda_verb table for ALC257
* 43f7c537f8 mb/google/trulo/var/pujjocento: update GPP_R4/GPP_R5 setting
* e4fc00adbe soc/amd/common/block: Enable MMCONF first
* cbbf380fa4 soc/amd/common/block/lpc: Use ROM3 window if possible
* 9d878fc6c0 soc/intel/xeon_sp: Add support for Emerald Rapids (5th Gen Xeon-SP) CPUs
* bd66b8cdd2 mb/google/nissa/var/rull: Enable VBOOT_EC_SYNC_ESOL for rull device
* 3155b2f64c mb/dell/haswell_latitude: Correct BOARD_ROMSIZE_KB_* for E7240
* 4d30d06637 mainboard/google/ocelot: Configure middle logo vertical alignment
* 583bf972c5 mb/google/ocelot: Remove NPK device
* 2bec5a9d9a soc/mediatek/mt8189: Check eFuse ECC in WDT init
* a89406790a mb/google/nissa/var/meliks: Set vccin_aux_imon_iccmax to 25A
* ccd4d1d1db mb/var/uldrenite: Make two pins NC to reduce S0ix power consumption
* e2baa9c7ed mb/google/bluey: Create Quenbi variant
* a98511fd23 mb/google/bluey: Only select EC_GOOGLE_CHROMEEC_SWITCHES with VBOOT
* 756d02f779 mb/google/fatcat: Remove extraneous space in Felino Kconfig name
* 8de02842d5 soc/intel/common/block/cpu: Execute post_cpus_init at BS_DEV_ENABLE
* 0baf47e03b vc/intel/fsp/ptl: Update header files from FSP 3071_00 to FSP 3144_01
* 61f043de4a mb/google/skywalker: Initialize DPM in ramstage
* 3f8702a0d6 soc/mediatek/mt8189: Add DPM v2 driver configuration
* d5bfa1c697 soc/mediatek/common: Add DPM V2 non-broadcast mode support
* 24ab31f477 mb/google/skywalker: Enable RTC boot init
* b288aaee85 soc/mediatek/mt8189: Use common RTC driver MT6359
* 12d6d0606c mb/google/skywalker: Initialize PMIC in romstage
* 2a3fd0659d soc/mediatek/mt8189: Add PMIC MT6315 driver
* 42ac3ccff4 soc/mediatek/mt8189: Add PMIC MT6359 driver
* a2010cf5ee mb/novacustom/mtl-h/Makefile.mk: include tas5825m.c in the build
* 2033075753 intel/alderlake/romstage: Implement eSOL during EC software sync
* e6a7666bcd cpu/intel/car: Skip EC software sync in common code
* ac4503d0dd security/vboot: Introduce VBOOT_EC_SYNC_ESOL Kconfig option
* 8a4b3e1346 cpu/intel/microcode: Add error handling if microcode directory is empty
* cb77cafbb4 soc/mediatek/mt8189: Add SPMI and PWRAP driver
* b9a4d6ede1 soc/mediatek/common: Correct MT6359 RTC EOSC setting
* ae2f3ab153 mb/system76: Add SMBIOS slot descriptions
* c0113106fa nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled
* 5e2aee4474 soc/mediatek/mt8196: Move sspm_enable_sram() to common code
* c81b08c4ba util/abuild: Fix building ChromeOS boards
* 62b823f69e mb/google/bluey: Increase flash size to 64MB for W25Q512NWEIM
* 276eb20b04 mb/google/bluey: Limit SPI flash support to Winbond
* 47c171a157 mb/google/bluey: Make Chrome EC optional
* 139a5b6fe0 mb/google/bluey: Select MISSING_BOARD_RESET due to lack of Chrome EC
* f9d933db36 mb/google/bluey: Introduce MAINBOARD_HAS_GOOGLE_TPM Kconfig
* e8450f78a0 mb/google/bluey: Make GPIO setups conditional on Kconfig options
* 4e8ea210bb mb/google/fatcat/var/felino: Add pull high setting on GPP_C03/GPP_C04 in gpio.c
* 65523e98a6 soc/mediatek: Extract DPM common code
* aaf373c253 mb/google/skywalker: Implement sku_id()
* be675e5369 mb/google/skywalker: Configure GPIO XHCI_INIT_DONE as output
* 9a60da5297 mb/google/skywalker: Enable ChromeOS EC
* c443478509 mb/trulo/var/pujjolo: Create pujjolo variant
* 24757047e5 util/abuild: Fix merge error
* d93f7f01a6 mb/topton/adl: Use CFR setup menu to manage options
* b59fef9678 soc/intel/cmn/cse: Add Kconfig to set ME default CFR option state
* 50a5fe77de soc/intel/meteorlake: Add CFR objects for existing options
* d53f00fbd9 soc/intel/meteorlake: Hook up the VT-d setting to option API
* e356483eb6 soc/intel/jasperlake: Add CFR objects for existing options
* 87663d1c0a soc/intel/jasperlake: Hook up the VT-d setting to option API
* 2c0c2f46d7 soc/intel/tigerlake: Add CFR objects for existing options
* d06c8dde58 soc/intel/tigerlake: Hook up the VT-d setting to option API
* 3cfb24a326 soc/intel/alderlake: Hook up the VT-d setting to option API
* 6f9df7ace4 soc/intel/cannonlake: Add/use enums for IGD config
* c8199f26e0 soc/intel/skylake: Add/use enums for IGD config
* 947dd07823 soc/intel/jasperlake: Hook up IGD config to option API
* 09adda95b9 soc/intel/meteorlake: Hook up IGD config to option API
* dcbb5771c9 soc/intel/tigerlake: Hook up IGD config to option API
* d930a3542c soc/intel/alderlake: Hook up IGD config to option API
* 9faf7ce4f4 soc/intel/alderlake: Add CFR objects for existing options
* 011baca89d cpu/x86/smm/smm_module_loader: Install bigger page tables
* aa121a9bbe payloads/external/edk2/Makefile: Set OemId Pcd
* ca9616b984 ec/system76/ec: Add config for 2nd fan without GPU
* f1f58b20b9 soc/mediatek/mt8189: Add SPI driver support
* d4a759a068 mb/system76/mtl: darp10: Add TCSS configs
* 85972101e6 commonlib/device_tree: Make *path const in dt_find_node()
* de9d76c761 mb/starlabs/starbook/tgl: Configure the eSPI GPIOs
* af7fb83ed0 soc/intel/apollolake: Hook up S0ix setting to option API
* 9979be7482 drivers/intel/fsp2_0: Remove redundant NULL checks and simplify code
* 6f9de346ae Revert "soc/amd/glinda/Makefile.mk: Use relative address for APOB_NV"
* d263e0bd92 soc/amd/glinda/Makefile.mk: Use relative address for APOB_NV
* 4f7ea3667c mb/google/rex/var/kanix: Tune camera I2C timing
* f0ad05b57e mb/google/brya/var/uldrenite: Fix USB_OC1 for USB3 A0 port
* 1140891211 mb/google/bluey: Initialize I2C, SPI, and GPIOs in bootblock
* ba8407f0c1 soc/intel: Add Arrow Lake-H/U IDs
* 3e1f96a0f4 mb/system76/mtl: Add Lemur Pro 13
* 3008b8de53 soc/intel/skylake: Show that SMRAM is unconditionally locked
* e6dc71fe9f util/superiotool: Dump one more NCT6779D register
* b50ceba64a mb/amd: Increase ROM size on boards, incorrectly limited to 16 MB
* 850703b32b mb/google/bluey: Configure FPMCU power, reset, and QUPv3 peripherals
* b4c6984a40 soc/qualcomm/x1p42100: Initialize QSPI and QUPv3 in bootblock
* fe34206442 soc/mediatek/mt8189: Add audio/display bus protection release functions
* c2b17a083d soc/mediatek/mt8189: Add PLL and clock init support
* e4cbd9ea9f soc/mediatek/mt8189: Add MTCMOS init support
* 5cf460dce9 soc/mediatek/mt8196: Fix RTC protection register unlock failure
* 2c986d016e MAINTAINERS: Add Google Bluey and Qualcomm SOC maintainers
* 64fe6fd94a util/abuild: fix TODO and update targets variable to an array
* 902288db22 util/abuild: Update version and date string
* 8504c796fc util/abuild: Remove obsolete FIXME
* a8e1113e3b util/abuild: Check functions directly instead of with $?
* b128abcdad util/abuild: Add quotes around variables
* 52b932df3b util/abuild: Group printfs to timestamps file together
* ad19c94d87 util/abuild: Fix shellcheck warnings about local vars
* d88ea14e8d util/abuild: Remove unused debug() function
* 82dea9d6d1 util/abuild: Disable shellcheck warning on interrupt()
* a2baaec067 util/abuild: Use ${} around variable names
* 9ddb54e6ad util/abuild: Update syntax from 'function func' to 'func()'
* f66c7c1037 util/abuild: Update echo to printf for consistency.
* 49ae935b37 util/abuild: Change [...] to [[...]] for consistency
* ea32e30a18 mb/starlabs/*/cfr: Remove `reboot_counter` CFR option
* d4cb553986 mb/starlabs/*/cfr: Remove `boot_option` CFR option
* 452e179727 mb/starlabs/*/cfr: Use global console CFR object
* aebef78622 xcompile: Use Walloc-size GCC option
* 074dd4f6f5 mb/google/fatcat: Set logo vertical alignment to middle for variants
* 02ca72b2d4 soc/intel/meteorlake: Hook up Pch Sleep Assertion widths
* 166f0ea146 util/abuild: Identify abuild builds with an env variable
* 511872dae3 mb/dell: Convert Latitude E7240 into a variant
* b5581d556b drivers/mrc_cache: Measure MRC cache as runtime data
* 05eb3e3716 mb/google/skywalker: Create variant Yoda
* c8ddae9ebe mb/google/puff: Use CFR setup menu to manage options
* dc19824e56 mb/google/fizz: Use CFR setup menu to manage options
* 1d62a1e857 mb/google/jecht: Clean up makefile
* 4112c77919 mb/google/jecht: Use CFR setup menu to manage options
* 6eddde31bb mb/google/beltino: Clean up makefile
* 445575525c mb/google/beltino: Use CFR setup menu to manage options
* 376a5acc24 util/lint: Add lint file for gofmt
* 4456c125f6 soc/mediatek/common: Move PMIF SPI macros to per-SoC's header
* 8efdbf0c34 mb/google/nissa/var/meliks: Use default domain_vr_config[] settings
* f07a1a76f3 mb/google/brya: Enable GNA scoring accelerator
* 6c830088da mb/google/rex/var/screebo: Generate RAM IDs
* ac2bd75817 spd/lp5: Add SPD for K3KL9L90EM-MGCU
* 66873a3812 vc/amd/fsp/glinda: Update SMBIOS Type 17 information
* b23db384a9 vc/amd/fsp: Update SMBIOS Type 17 PartNumber size
* 0b120de7c0 Documentation: Update documentation for Topton X2F-N100
* d50019d432 mb/starlabs/starbook_mtl: Select SKIP_SEND_CONNECT_TOPOLOGY_CMD
* 4aa1861fbb mb/starlabs/starbook/mtl: Configure sleep assertion times
* 183c414577 soc/intel/meteorlake: Add Kconfig to skip FSP TBT connect topology
* aa1eba2f25 drivers/intel/fsp2_0: Enable firmware splash using 24-bit BMP logo
* da29107572 mb/google/fatcat/var/francka: Reduce generic reset delay to 10ms
* 60916d0f10 mb/trulo/var/uldrenite: Support different ISH UART mappings
* 3fe4b00966 mb/trulo/var/uldrenite: Swap ISH UART from UART1 to UART0
* 407c7d0da3 Documentation: Add Device Operations
* 20d7eaeb0f Documentation: Add chip operations
* bf38f8eddc vc/intel/fsp2: Drop superfluous header for Raptor Lake S
* eec228987e mb/intel/coffelake_rvp: Make use of chipset devicetree
* c9f4cfa463 AUTHORS: Update list to 25.03
* da5101fde4 cpu/x86/smm: Drop unused label
* 9154070320 mb/asus/h61-series: Add H61M-A/USB3
* e8c724fe1a mb/lenovo/m900_tiny: Update VBT to build 1037 with Kaby Lake gfx support
* 21ca6701ff mb/google/{drallion,hatch,sarien}: Skip adding DTT/TCPU to SSDT
* 5bf88a44e9 drivers/smmstore: Support 64-bit MMIO addresses
* 2706ce0266 mb/intel/ptlrvp: Add GPIO support for T4 LP5 board
* 40b62ff6c4 mb/intel/ptlrvp: Add memory configuration support for T4 LP5 board
* 7f826fddc5 mb/intel/ptlrvp: Compile variant.c in ramstage for ptlrvp
* 0ca46ac0d2 soc/intel/pantherlake: Enable coreboot native logo rendering
* 210371e25b mainboard/google/fatcat: Configure middle logo vertical alignment
* e446c1f917 drivers/intel/fsp2_0: Introduce coreboot native logo rendering
* 2f23896299 soc/intel/intelblocks/cfg: Add splash screen vertical alignment options
* 78d15d9a12 drivers/intel/fsp2_0: Add Kconfig to select FSP for BMP rendering
* 5f941893ef cpu/x86/mtrr: Introduce mtrrlib with common MTRR helper functions
* e180971560 drivers/intel/fsp2_0: Move graphics info struct/GUID to FSP header
* 18b4349422 mb/var/uldrenite: Fix fw_config_gpio_padbased_override not being called
* a6be271e63 arch/x86: Unify GDT entries
* 1e7e4e943f soc/intel/tigerlake: Hook up S0ix setting to option API
* ba4b26c4fc soc/intel/meteorlake: Hook up S0ix setting to option API
* 514ad949e3 soc/intel/jasperlake: Hook up S0ix setting to option API
* 55afbe250d soc/intel/elkhartlake: Hook up S0ix setting to option API
* 3cc728110d soc/intel/alderlake: Hook up S0ix setting to option API
* 245cba6795 cpu/x86/smm: Add support for exception handling
* 2e27ceed67 mb/google/volteer/var/elemi: Check FP presence against SKU ID
* 663dbd462a soc/amd/phoenix: Remove outdated TODO comments
* b1b8b0e8e1 mb/starlabs/starbook/tgl: Reconfigure PCH Strap GPIOs
* 36ac6226ff util/autoport: Add function to create empty files
* f8071719e7 soc/intel/ptl: Add Wildcat Lake platform reporting
* db4162adce soc/intel/ptl: Add Wildcat Lake PCIe Device details
* 1baf0baf58 soc/intel/ptl: Add Wildcat Lake SoC device tree
* 2fc246cd2d mb/google/ocelot: Remove unused devices from devicetree
* 3278551f8c drivers/intel/fsp2_0: Include coreboot_tables.h in fsp_gop_blt.h
* 18172b6009 mb/google/bluey: Add SoundWire amp and SD card GPIOs to lb_gpios
* 80901a4494 mb/google/bluey: Add GPIOs for Soundwire, Display, and SD Card
* 1015d4332f mainboard/google/bluey: Add fingerprint sensor GPIO entries
* a85b9a21b2 mb/intel/ptlrvp: Add support for DDR5 configuration
* c1bcb43f7c cbgfx: Prevent divide-by-zero edge case in Lanczos kernel
* 565c768c20 soc/intel/alderlake: only add wifi Mitigation if DRIVERS_WIFI_GENERIC
* ac948173ad mb/starlabs/starfighter/rpl: Add ramstage.c to makefile
* f1509a467c mb/starlabs/starfighter: Add CFR option to use native panel resolution
* 3593314cf5 mb/starlabs/starlite_adl: Add CFR option to use native panel resolution
* d13afbbbca mb/starlabs/starbook: Add CFR option to use native panel resolution
* 8fa84d9111 mb/starlabs/*: Add CFR entry for Bluetooth RTD3
* d2b0220a38 allocator_v4: Re-enable top-down allocation for edk2
* 4d7b56cdaa soc/intel/cmn/cse_lite: Fix handling of soft disable state
* 33b3269d91 soc/intel/cmn/cse: Add function to check if ME state is M3_NO_UMA
* 30a4fec86e mb/google/fatcat/var/kinmen: Generate SPD ID for Micron modules
* cf5696834b soc/intel/ptl: Refactor Panther Lake SoC configuration
* e99532d99b soc/mediatek/common: Update SPMI calibration process
* f83fb11e5f soc/mediatek/mt8189: Add CPU segment ID support
* 7b27b1ca99 soc/mediatek/mt8189: Fix incorrect GPIO register address
* f2cf732997 libpayload: usbmsc: Correctly deal with disks larger than 2TB
* 173c5d0aad src/arch/x86/c_start: Delete duplicated code masking stack pointer
* 1166f9be0d include/console: Add CFR object for setting the logging level
* 0f0d5fc725 soc/intel/apollolake/acpi: Add function to get PCIe BAR
* 5d3664ce3b mb/starlabs/starbook/adl_n: Update VBT to fix HDMI output
* 4b765fdd98 mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC
* f63c3bb297 soc/intel/cannonlake: Hook up DPTF device to devicetree
* b7d59185ab soc/intel/common/dtt: Add Kconfig to skip SSDT generation
* 094f75162f cpu/x86/64bit/pt: Fix integer arithmethic in assembly
* bbd8f0aef8 soc/intel/ptl: Refactoring NUM_COMx_GRP_PADS calculation
* cf47edb173 ec/google/wilco/acpi: Add UCSI port data
* 89e915e981 ec/google/wilco/acpi: Fix S3/S4 support
* 4a89d1b77d soc/intel/ptl: Add GPIO ACPI support for Wildcat Lake SoC
* a4a2cdeb17 soc/intel/ptl: Add GPIOs for Wildcat Lake SoC
* 2ce567f1d0 soc/intel/common/block/cse: Prevent HECI commands when flash descriptor override is set
* 9660279966 drivers/usb/intel_bluetooth: Hook RTD3 up to the option API
* e2705d93d8 soc/intel/pantherlake: Reduce IGD stolen memory size from 128MB to 64MB
* 9f98a2a78a mb/asus/p8z77-v_le_plus: Use additional rt8168 MAC programming
* 2b598a9472 drivers/net/r8168.c: Add option to program MAC address to ERI registers
* 4b871c6314 ec/intel: read board ID one time from EC per stage
* 08722cd9f9 mb/google/dedede/var/beadrix: Add Ziliatech part to RAM ID table
* c0920396d0 mb/google/bluey: Make GSC_AP_INT GPIO configurable via Kconfig
* 2e387e13f5 mb/google/fatcat/var/francka: Conditionally init HDA
* e545494f6d mb/google/fatcat/var/fatcat: Conditionally init ALC256 HDA
* 03d2ef67d7 soc/intel/cmn/hda: Introduce mainboard hook for HDA initialization
* 85c65b0c20 mb/google/fatcat: Remove NPK device from fatcat and francka variants
* 92955fbfa6 mb/google/trulo/var/uldrenite: Configure GPP_E9 as NF2
* aafcb01ec4 mb/intel/ptlrvp: Synchronize codebase with fatcat
* effd1ffdad mb/google/ocelot: Update Ocelot board
* 1044f03878 payloads/external/edk2: Set StatusD register to work around failing AMD boot
* 2170ad0c60 Documentation/lib/timestamp.md: Reformat to 72 characters per line
* 22118a137b mb/google/fatcat/var/kinmen: Add memory settings
* 54c87dbed0 mb/google/trulo/var/uldrenite: Update DPTF parameters
* 9ef62ad64c mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations
* 7c965f9df0 MAINTAINERS: Add Nick, Avi, and Pranava for new google/ocelot entry
* d2e698056e mb/google/bluey: Set correct Kconfig defaults for peripherals
* 34d6bc8784 soc/qualcomm/x1p42100: Set correct Kconfig defaults for peripherals
* 2201f57493 soc/qualcomm/x1p42100: Add QUP Serial Engine (SE) entries
* 6a503fe5a4 mb/google/var/uldrenite: Configure GPP_A16 as NF4
* c2c95fbd24 sb/intel/lynxpoint: Add CFR objects for existing options
* 96fd20c5e0 soc/intel/broadwell: Add CFR objects for existing options
* ce6f7820f4 ec/google/chromeec: Increase EC status timeout to 30 seconds
* 17347eedc3 soc/intel/cannonlake: Add CFR objects for existing options
* ad704e0500 soc/intel/cannonlake: Hook up the VT-d setting to option API
* 7f8d1f2086 mb/google/nissa/var/pujjoniru: Support x32 memory configuration
* fe881c990c mb/google/brya: Create pujjocento variant
* 7da36ad79a mb/google/bluey: Add initial support for Bluey
* 57d7957e3c soc/qualcomm/x1p42100: Add initial SoC skeleton for X1P-42-100
* c82f5fe133 soc/amd/glinda: Select SOC_FILL_CPU_CACHE_INFO
* ee76692571 payload/external/edk2: Add Kconfig to support use of PCIe OpROMs
* fb3f025ea6 soc/amd/common/cpu/noncar: Add SMBIOS helper
* 36f01c3481 mb/google/fatcat/var/felino: Add Write Protect GPIO to cros_gpios
* 934fcfb6a0 soc/mediatek/mt8189: Add I2C driver support
* b3bdffa475 soc/mediatek/common: Move I2C functions to common code
* 1e0941c295 mb/google/ocelot: Select Wildcat Lake(WCL) SoC config
* b249275e3d mb/amd/crater: Fix some ec defines
* 443f514365 mb/amd/crater: Add touchscreen support
* 4e55225f2c mb/amd/crater: Add missing dxio descriptors
* 608db150f1 smmrelocate: Drop unused parameter
* 157b7ae778 payloads/edk2: Update default branch for MrChromebox repo to 2025-02
* 76a1e81b10 mb/starlabs/*: Unify Sleep S3 and S4 GPIO configurations
* fed584e100 soc/intel: Add Wildcat Lake CPU and PCIe device IDs
* 5d7e2b4c0c mb/google/fatcat: Disable VR settings on Panther Lake H SoC
* 8be95806a6 mb/google/ocelot/var/ocelot: update gpios
* 92f9c8a985 mb/google/ocelot: update FW_CONFIG
* 49bf8f94a0 soc/intel/common: Add CFR objects for existing options
* 509b01c3b6 soc/intel/cannonlake: Hook up S0ix setting to option API
* b830fdc2d7 soc/intel/cannonlake: Hook up IGD config to option API
* 5efb54d371 soc/intel/broadwell: Allow ME enable/disable to be set via option
* 42379e7f76 sb/intel/lynxpoint: Allow ME enable/disable via option
* 204aae207d mb/samsung/stumpy: Clean up makefile
* e3d3fc5b4a mb/samsung/stumpy: Use CFR setup menu to manage options
* 936ca8404a drivers/option/cfr: Select EFI variable store when edk2 payload used
* 20ceed1929 drivers/efi/fw_info: Select necessary UDK binding as needed
* c0e3f6d1d2 drivers/efi/variable_store: Select necessary UDK binding as needed
* a899359720 sb/intel/bd82x6x: Add CFR objects for existing options
* ada6b98766 nb/intel/sandybridge: Add CFR objects for existing options
* f14aa06606 soc/intel/skylake: Add CFR objects for existing options
* f51c0bb090 soc/intel/skylake: Hook up IGD config to option API
* 32c78b7e22 soc/intel/skylake: Hook up S0ix setting to option API
* 73b095d5ea mb/starlabs/*: Select DRIVERS_OPTION_CFR_ENABLED
* 4eba4e3f26 superio/ite/it8772f: Program power state after failure
* fbca3e6806 superio/ite/*: Move setting of power state to common code
* 60b414fc13 soc/intel/cannonlake: Drop redundant PcieRpEnable
* ee30558c49 soc/intel/skylake: Drop redundant PcieRpEnable
* 439d7fb7d0 mb/google/brya: Create epic variant
* c4e6050146 mb/google/skywalker: Create variant Obiwan
* 0cc0e6996c drivers/smmstore: allow full flash access for capsule updates
* 7814b8a6be Revert "soc/mediatek/mt8196: Specify MTKLIB_PATH for building BL31"
* 14b66cb01b soc/intel/pantherlake: Add new SoC config for Intel Wildcat Lake(WCL)
* d14ebe3957 mb/google/fatcat/var/felino: Use GPP_C08 for GPIO_PCH_WP
* 6322be7992 sb/intel/bd82x6x/me.h: Add missing definitions
* 2f62dd8a6b mb/google/brya/var/uldrenite: Configure ISH_GP5 GPIO
* 3ce612194c mb/google/rex: Generate RAM IDs
* 430ab9257b spd/lp5: Add SPD for K3KL8L80EM-MGCU
* c7a450ba7d Documentation/mainboard/asrock/imb-1222.md: Update information
* ac7717a7b0 mainboard/asrock/imb-1222: Enable USB3 port in WWAN slot
* eb68ff66eb mb/asrock/imb-1222: Update GPIO config using new intelp2m
* a1210875e9 mb/imb-1222: Update some GPIOs according to new vendor config
* fc8e88da9b drivers/intel/mipi_camera: Rework info print output
* d04d7d80b0 drivers/intel/mipi_camera: Only generate ADR if no HID supplied
* 36c89598a7 mb/erying/tgl: fsp_params: Replace half_populated with statement
* 0307f52cd9 soc/mediatek/mt8196: Move SPM loader functions to common part

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 19:18:50 +01:00
Leah Rowe f6da49b3a7 deguard: bump to rev 0ed3e4f
There really isn't anything functionally different. However,
this means one less patch is needed in lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 17:54:51 +01:00
Leah Rowe 81dc1a7f89 GRUB: Bump to rev a68a7dece, 23 June 2025
NOTE: gfxterm_menu module removed, because of this
change by upstream:

commit ca2a91f43bf6e1df23a07c295534f871ddf2d401
Author: Glenn Washburn <development@efficientek.com>
Date:   Mon May 5 16:11:36 2025 -0500

    tests: Disable gfxterm_menu and cmdline_cat tests

This brings in the following changes from upstream:

* a68a7dece loader/i386/pc/linux: Fix resource leak
* de80acf36 loader/efi/linux: Unload previous Linux kernel/initrd before updating kernel size
* 249db11d8 loader/efi/linux: Correctly terminate load_options member
* f3b339af1 loader/efi/linux: Use sizeof() instead of constant
* c2b2e0dcf loader/efi/linux: Use proper type for len variable
* de4e8e2aa loader/efi/linux: Do not pass excessive size for source string
* 8c8f96664 loader/efi/linux: Remove useless assignment
* 8ebf155af include/grub/charset.h: Update documentation
* 2f2ed28d5 Revert "lzma: Make sure we don't dereference past array"
* 2539ede82 tests/util/grub-shell: Correct netboot and file_filter test failure
* 8c2d4e64f normal/charset: Fix underflow and overflow in loop init
* ba8eadde6 dl: Provide a fake grub_dl_set_persistent() and grub_dl_is_persistent() for the emu target
* 409e72ced util/grub-protect: Correct uninit "err" variable
* 5eca564b1 gnulib: Bring back the fix for resolving unused variable issue
* ac1512b87 gnulib: Add patch to allow GRUB w/GCC-15 compile
* db506b3b8 gnulib/regexec: Fix resource leak
* bba7dd736 gnulib/regcomp: Fix resource leak
* 91cb7ff6b tests/tpm2_key_protector_test: Add tests for SHA-384 PCR bank
* 451e227e5 tpm2_key_protector: Dump the PCR bank for key unsealing
* 11caacdb2 util/grub-protect: Fix the hash algorithm of PCR digest
* ce23919ca build: Add new header files to dist to allow building from tar
* e3b15bafd build: Remove extra_deps.lst from EXTRA_DIST
* 40e261b89 lib/LzmaEnc: Validate "len" before subtracting
* 86e8f2c4b osdep/unix/hostdisk: Fix signed integer overflow
* 438f05581 disk/luks2: Add attempting to decrypt message to align with luks and geli modules
* 20e6d0c4a osdep/linux/getroot: Detect DDF container similar to IMSM
* b71bc0f8b fs/fshelp: Avoid possible NULL pointer deference
* 272ff81cb fs/ntfs: Correct possible infinite loops/hangs
* 8c95307a0 fs/ntfs: Correct possible access violations
* 06914b614 fs/ntfs: Correct attribute vs attribute list validation
* 0e1762c8a fs/ntfs: Correct regression with run list calculation
* be303f8c1 lib/envblk: Ignore empty new lines while parsing env files
* 34bd00ee2 fs/zfs: Fix another memory leak in ZFS code
* ca2a91f43 tests: Disable gfxterm_menu and cmdline_cat tests

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 16:26:49 +01:00
Leah Rowe 5b2661a485 SeaBIOS/default: Bump to rev b686f460, 28 Jun 2025
This brings in the following changes:

* b686f460 sercon: Fix keycodes for F11 and F12
* b52ca86e docs: Note v1.17.0 release
* a6c8e8bb ahci: Fix hangs due to controller reset

The serial console fix is useful to us, as is the AHCI
fix; the latter was previously mitigated by removing
SeaBIOS's AHCI reset patch.

Upstream realised that the AHCI controllers need to have
a timeout on them when resetting them, because they don't
always react immediately to commands.

This makes the AHCI behaviour more correct, in SeaBIOS.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 15:31:48 +01:00
Leah Rowe 248192ad9a ifd/hppro3500: use truncated ME, enlarge BIOS size
i did:

ifdtool -f layout.txt ifd.bin

changed layout.txt to say this:

00000000:00000fff fd
00019000:007fffff bios
00001000:00018fff me
00fff000:00000fff gbe
00fff000:00000fff pd

then i did:

ifdtool -n layout.txt ifd.bin -O ifd.bin

this was done to the ifd for hp 3500 pro, based on
the 96KB size of the truncated me.bin via me_cleaner,
when downloading vendor files in lbmk.

it's the policy of libreboot that me.bin should always
be shrunk, and the BIOS region enlarged.

in the original HP 3500 PRO patch submitted, the ME region
was larger, with region boundaries like this:

00000000:00000fff fd
00400000:007fffff bios
00001000:003fffff me
00fff000:00000fff gbe
00fff000:00000fff pd

In the above example, you see that the BIOS region is 4MB.

In the new setup, BIOS is about 7.9MB.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 04:34:14 +01:00
Leah Rowe 1cd8353082 ifd/hppro3500: unlock regions by default
coreboot already unlocks the regions during build, by default,
anyway, and this was present in the submitter's patch.

however, it's also good to unlock the IFD regions. like so:

ifdtool --unlock ifd.bin -O ifd.bin

this has been done, on the ifd for hp pro 3500

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 04:25:22 +01:00
Leah Rowe 67858207eb ifd/hppro3500: set HAP bit by default
ifdtool --altmedisable 1 ifd.bin -O ifd.bin

always remember to do this, when adding a new
ifd to lbmk. i merged the 3500 port anyway, since
the submitted already used me_cleaner anyway, but
setting the HAP bit is also useful. for example, if
someone was to only flash the BIOS region, which is
possible in this case since the submitter also
didn't truncate the ME region or enlarge the BIOS
region.

in that case, flashing IFD and BIOS is another valid
way to do it, where IFD's HAP bit is set

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 04:22:48 +01:00
Leah Rowe a13772bf31 cb/hppro3500: use seagrub, not grubsea
We want graphics cards to work out of the box. This is
why SeaGRUB is default, on desktops; SeaBIOS also has
better code quality and is less likely to break, so it
provides a nice fallback in case the GRUB payload is ever
buggy during development (this decision was made ever
since the botched May 2024 release)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 04:15:22 +01:00
Leah Rowe 047ddf40d8 Merge pull request 'Add HP Pro 3500 Series' (#350) from JoelLinn/lbmk:feature-port-hppro3500 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/350
2025-07-06 05:10:17 +02:00
Leah Rowe d25aaac9ad lib.sh: remove erroneous break from fx_
it means nothing here. in context, if a non-zero return
is observed, we should not do anything here, which is
already the behaviour anyway, except that "break" means
nothing since we're not in a loop here.

where an error exit should be observed, x_ is used inside
the command given for fx_

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 03:25:35 +01:00
Leah Rowe c46a71138c Libreboot 25.06 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-30 14:08:48 +01:00
Joel Linn 587af4a7b6 Add HP Pro 3500 Series
Everything should work except cpu fan control because ME cleaning breaks PECI.
2025-06-15 15:20:32 +02:00
Leah Rowe b1ef562b76 tree.sh: add sha512 error for check_project_hashes
handle errors on sha512sum - also handle awk errors inside
the mini subshell, and provide overall error handling.

we know that the project.hash file should always exist, and
always be read no matter what; technically, the find command
that proceeds it might not yield any results, but an empty
file would then be produced.

the edge case of an empty file would have lead to an error
beforehand, when configuring the project in function,
configure_project(), so we've already got that covered.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:41:09 +01:00
Leah Rowe 04bee3834d tree.sh: add error check in check_project_hashes()
when reading old_pjhash, we need to error out where a read
error occurs. such an error is unlikely, but could occur under
certain edge cases.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:41:03 +01:00
Leah Rowe 677dfc4d10 tree.sh: more reliable clean in run_make_command
Don't do no-op if it fails; fall back to "clean" instead,
and fail if that fails.

The no-op was there was not all projects have distclean,
but we do intend for them all to be cleaned.

We mitigate further error by only running make-clean if
a makefile exists.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:40:33 +01:00
Leah Rowe 267d4c9034 inject.sh: add missing semicolons
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-06-05 23:39:57 +01:00
Leah Rowe 974bdbb381 vendor.sh: fix bad cbfstool path
i overlooked this one in the previous commit

there is always one.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-27 11:18:18 +01:00
Leah Rowe dc6996252a put coreboot utils in elf/coreboot/TREE
not elf/UTIL/TREE

This way, they are automatically deleted when a tree
has to be re-built.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-27 10:11:42 +01:00
Leah Rowe b77154640d release.sh: use printf to create version files
Don't copy the files directly, because we might be doing
this from a work directory that has no files; in this case,
generic "unknown" variables are used, without generating
any files, so the current logic would produce an error.

However, we do need to create those dot files, because
we then rely on them for building release binaries.

The new logic maintains current behaviour, while fixing
this technical edge-case scenario via mitigation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 18:46:58 +01:00
Leah Rowe dee6997d0c lib.sh: simplify setvars()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:49:55 +01:00
Leah Rowe 79ded40f3d lib.sh: simplify chkvars()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:45:12 +01:00
Leah Rowe 5036a0bc50 mk: simplify main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:33:56 +01:00
Leah Rowe 41308ee924 get.sh: simplify fetch_project()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:26:34 +01:00
Leah Rowe b5867be214 get.sh: simplify try_copy()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:23:06 +01:00
Leah Rowe 495098d6a7 get.sh: tidy up bad_checksum()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:19:06 +01:00
Leah Rowe 671e3aa27b get.sh: simplify fetch_targets()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 13:11:20 +01:00
Leah Rowe 09b6e91803 general cleanup in get.sh and vendor.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 01:30:33 +01:00
Leah Rowe 18dacd4c22 xbmk: rename xbmklocal/xbmktmp variables
shorten them

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:57:50 +01:00
Leah Rowe e981132c82 get.sh: consolidate printf statements
stick it in git_prep, which both single- and multi-tree
projects will use, when downloading git repositories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:50:06 +01:00
Leah Rowe afc36754b1 get.sh: remove redundant printf in fetch_project
The following execution will result in another printf
that says exactly what is being downloaded.

There is no need to inform the user twice about
what is being downloaded.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:44:57 +01:00
Leah Rowe ffe387ac6b get.sh: remove superfluous command in try_git()
A git-pull is performed immediately after git-fetch.
Git-pull already performs git-fetch as a prerequisite.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:35:38 +01:00
Leah Rowe ba7c49c090 vendor.sh: simplify fetch()
the checks at the end of the function are mostly
superfluous, because bad_checksum() is immediately
called just beforehand, and performs the same checks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-26 00:33:36 +01:00
Leah Rowe 30bc3732c3 init.sh: error out if .git/ is a symlink
the current behaviour is a relic from the older lbmk
design, before recent auditing.

the current logic would cause xbmk to continue execution,
going into a child process with .git/ being a symlink.

The .git/ directory should never be a symlink, because
it is extremely error-prone.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 17:01:10 +01:00
Leah Rowe 2493203ee5 get.sh: Properly error out if tmpclone fails
We rely on a non-zero exit on other try_ commands, which
works fine there because we then check the file afterward
and error out accordingly.

For git repositories, we assume that both mirrors are
identical and therefore once we get to the first clone
attempt, we assume that it must succeed.

Therefore, if it does not succeed, we must fail. This fixes
a regression I found in testing, where sometimes a failed
patching attempt would not result in an error exit, and
would therefore result in broken sources being present.

In practise, I always very closely watch the terminal when
testing xbmk, especially when updating project patches, so
we probably didn't introduce any broken sources in practice.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 14:46:33 +01:00
Leah Rowe ad333ae248 tree.sh: Don't auto-run make-oldconfig
This code was introduced to provide fault tolerance,
so that if I forgot to manually update the configs
myself, builds would still succeed, e.g. coreboot
builds.

However, there have been cases in the past where this
introduces settings we don't want, and in general we
do want to know when there is an error in the configs.

The policy should always be: fail early, fail hard.

This also mitigates bugs in U-Boot's build system; for
example, when I last attempted to update the U-Boot
tree for x86, make-oldconfig introduced a lot of junk
settings unrelated, which then introduced code that
would brick the board if you tried it on one, e.g.
it broke booting most Linux kernels via bootflow.

With this change, U-Boot will be easier to handle,
which normally requires manual configuration; the
automated make-oldconfig reconfiguration feature
breaks U-Boot. This will no longer occur, since we
no longer run it manually.

On the other hand, this feature has also prevented
other disastrous bugs in the past, such as when I
forgot to properly set the SPD size on T480; it was
set to 256 bytes, not 512 as is correct. Therefore,
this new design change means I must also be more
vigilant about config changes in project trees.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 14:35:02 +01:00
Leah Rowe 97ce531c34 rom.sh: simplify mkcoreboottar()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 05:03:03 +01:00
Leah Rowe a47e981172 rom.sh: rename mkvendorfiles
it mainly does general tasks, like handling utils
and enabling ccache. the vfiles are a small part.

rename the function accordingly. it is called by
premake, so let's call it corebootpremake.

this change will also make sense when cherry-picked
into cbmk, which does not handle vfiles at all.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 04:46:08 +01:00
Leah Rowe d2e148fdd9 rom.sh: simplify ccache handling for coreboot
we simply do not need to run the make-oldconfig command
at all, and after removing it, the "cook" function seemed
quite redundant so i merged it with mkvendorfiles()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 04:40:30 +01:00
Leah Rowe 8c3f10ba40 rom.sh: simplify u-boot payload handling
define it with a single variable, rather than several.

this allows several checks to be greatly simplified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-25 03:09:29 +01:00
Leah Rowe 3e28873532 ifd/hp8300usdt: set the HAP bit by default
In practise, coreboot can set this bit at build time.
We also use ME Soft Temporary Disable by default, on
this platform.

We also use me_cleaner by default, so the me.bin file
added to flash only contains the code that would run
with HAP set anyway.

Therefore, this change is of little practical consequence,
but as a friend put it to me, this change is most technically
correct.

And I'm all about technical correctness.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-23 04:52:36 +01:00
Leah Rowe 452aeb6001 coreboot: Remove unused vboot tests
Futility tests enlarge the src tarballs, without much utility.

Uttterly futile.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 14:13:11 +01:00
Leah Rowe 64cc91bca3 coreboot/default: Remove unneeded FSP modules
We only need the Kabylake version. We can safely
remove the other ones, thereby significantly
reducing the size of the lbmk release archive.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 13:48:20 +01:00
Leah Rowe 0216a3104a get.sh: Always update git remotes
Right now, if cache/clone/PROJECT/ already exists,
the logic for pulling new changes doesn't execute,
and neither does the logic for updating remotes.

This is bad when updating revisions, because then
manual updating is required, defeating the purpose
of xbmk's own automation in this regard.

Fix it by only checking the cached download on files,
not Git repositories; the try_git function itself will
already perform this check, before updating remotes
and pulling in new commits from upstream.

The updating only happens when a given target directory
doesn't exist, e.g. src/flashprog/ or src/grub/default/,
so this won't slow down release builds for example.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 12:45:59 +01:00
Leah Rowe 419733d307 get.sh: re-generate remotes every time
that way, when a remote changes in config/, it
will be updated automatically, without user
intervention.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 12:22:07 +01:00
Leah Rowe 231b320e63 release.sh: copy version files to rsrc
Otherwise, an "unknown" version number is created.

This regression was caused by the recent optimisation
that reduces the amount of extra work done by init.sh
on child instances of xbmk.

As a result of those changes, now release.sh has to
do some minor initialisation of its own, such as this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 11:51:31 +01:00
Leah Rowe fc0720184d xbmk: add fake config makefile args to flashprog
also pcsx-redux

this way, commands like "./mk -u" without argument
will not fail. these fake makefile commands do nothing.

otherwise, an error errors because their makefiles
do not define these options.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 11:34:28 +01:00
Leah Rowe f9266601b8 vendor.sh: add colon at the end of a for loop
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 11:27:22 +01:00
Leah Rowe 8e0c6059d1 rom.sh: skip copyps1bios on dry builds
otherwise, ./mk -d (without arguments) will fail.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 01:47:02 +01:00
Leah Rowe a3250d1447 tree.sh: Don't run make-clean on dry runs
Otherwise, ./mk -d (without arguments) fails for GRUB,
which first requires running autoconf to get a Makefile.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-22 01:17:27 +01:00
Leah Rowe 24b8e633e0 GRUB: Update to revision 73d1c959e (14 March 2025)
This brings in several changes from upstream:

* 73d1c959e cryptocheck: Add --quiet option
* dbc0eb5bd disk/cryptodisk: Wipe the passphrase from memory
* 301b4ef25 disk/cryptodisk: Add the "erase secrets" function
* 23ec4535f docs: Document available crypto disks checks
* 10d778c4b commands/search: Add the diskfilter support
* 7a584fbde disk/diskfilter: Introduce the "cryptocheck" command
* ed691c0e0 commands/search: Introduce the --cryptodisk-only argument
* c448f511e kern/rescue_reader: Block the rescue mode until the CLI authentication
* 4abac0ad5 fs/xfs: Fix large extent counters incompat feature support

This commit is of particular interest:

* dbc0eb5bd disk/cryptodisk: Wipe the passphrase from memory

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-21 13:34:18 +01:00
Leah Rowe f6b7782283 Revert "vendor.sh: optimise find_me()"
This reverts commit fb7aaa78bb.

it caused a few issues. will re-do later

the old code isn't really broken, just inefficient, because
several files are scanned twice, but in practise the overhead
isn't that great

The error occurs sometimes, when bruteforcing me.bin:

ERROR ./mk: Unhandled error for: mv /home/user/lbmk/tmp/me.bin /home/user/lbmk/cache/tmpdl/check

This revert should fix the issue, for now.
2025-05-20 20:14:09 +01:00
Leah Rowe fb7aaa78bb vendor.sh: optimise find_me()
i'm adding characters to 7ztest, which isn't being passed
on through because everything runs in subshells; the next
pass would default back to the original string, so a given
file may be checked multiple times.

fix this by mitigation; use the random string from mktemp
as a suffix instead.

in practice, this has not affected performance much, but it
will nevertheless avoid unnecessary work by xbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-20 02:58:33 +01:00
Leah Rowe 903f78bf08 get.sh: add missing check in fetch_project()
we check the main url, but not backup urls.

this patch fixes that oversight.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 23:13:29 +01:00
Leah Rowe f15bb8153a get.sh: stricter URL check in xbmkget()
don't skip if the URL is empty. throw an error instead.

i decree that all links must be properly initialised, because
that is the design of lbmk. where only one link is provided,
such as in a local copy operation, the second would succeed no
better than the first so two identical paths are given.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 23:09:37 +01:00
Leah Rowe cdc0fb49e1 get.sh: make xbmkget() easier to understand
the intent once again is that this for loop shall
return, with zero status, if success is observed.

otherwise, the loop breaks and an error is thrown.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 23:07:01 +01:00
Leah Rowe 620c1dd6fa get.sh: Make xbmkget err on exiting the loop check
The idea in this function is that if a file or repo is
successfully handled, a return will be performed from the
loop.

If the loop exits for any reason, an error is thrown. The
current code is probably fine, but I can forsee future
modifications possibly causing bugs here.

Make it unambiguous, by always throwing an error if execution
reaches the end of the function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 22:59:20 +01:00
Leah Rowe 900da04efa tree.sh: fix up copy_elf(), bad for loop
Because of how sh works, having just the [] line causes
sh to exit, annoyingly without an error message, but it
does cause a non-zero exit.

This bug will have already been triggering, before I added
the recent error handling on files for this for loop.

also do it to the other loop in lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 19:58:55 +01:00
Leah Rowe 8aaf404dde lib.sh: Use while, not for, to process arguments
This is more reliable against globbing, in context of for.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 19:29:59 +01:00
Leah Rowe d9c64b2675 xbmk: stricter handling of files on while loops
i overlooked these!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 19:24:43 +01:00
Leah Rowe b25a487643 init.sh: looser XBMK_THREADS validation
on child processes, we can simply correct it.

we currently provide an error message, but this is silly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 18:53:22 +01:00
Leah Rowe 769a97aed5 init.sh: Hardcode XBMK_CACHE for integrity
I never really intended for this to be configurable,
but the cache directory is also used during release
builds.

There's too much that can go wrong, letting the user
decide where their cache is. Simplify it by hardcoding.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 18:50:06 +01:00
Leah Rowe 265ec0b767 dependencies/debian: add libx86
already present on a few other config files, e.g. arch

i noticed on debian-experimental that i needed to explicitly
install it, whereas it was implicitly installed on debian 12

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-19 17:40:44 +01:00
Leah Rowe 2702a43a86 init.sh: merge xbmk_lock() with xbmk_set_env()
it's just two lines, and we want much more granular
control of where the lock is enforced. it should be
JUST after confirming that the instance is a parent.

it is at this moment that we should bail if a lock
file exists, because this signals that another instance
of xbmk is running.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:32:24 +01:00
Leah Rowe fc4006ce87 init.sh: move xbmk_set_version
it's called before set_pyver, so move it above that

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:29:51 +01:00
Leah Rowe 962902a1c4 init.sh: set pyver from set_env
it's related to this function, no point calling from main

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:28:31 +01:00
Leah Rowe 158c56072c init.sh: merge xbmk_mkdirs with set_env
it's just two lines, and they relate.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:25:37 +01:00
Leah Rowe 5f022acbf4 init.sh: check version/versiondate once read
once again, we are being stricter in child instances.

we must ensure that these variables are set by xbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:10:22 +01:00
Leah Rowe 485a60e2f6 init.sh: error if version not read
we no longer rely on the .git version being
read by child instances, so we MUST ensure
that it is being read.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:08:49 +01:00
Leah Rowe 99f09f25ef init.sh: only update version files on parent
don't update them on child instances, since it's a waste
of time; the lock file prevents further execution, so we
are just wasting time writing to disk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 13:03:09 +01:00
Leah Rowe 94437278dc init.sh: simplify unknown version creation
we don't need to read or write a file at all, in that case.
we only then need to generate one if running ./mk release.

the scenario in which no .git and no version files exist
is when someone grabs the build system from a snapshot
generated by e.g. forgejo instances. it's ill advised, so
we advise against it, but it is mitigated in code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 12:54:31 +01:00
Leah Rowe 6b603b9fbf init.sh: only set xbmk version on parent instance
On child instances, we need only read.

Apply the principle of least privilege.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 12:07:10 +01:00
Leah Rowe ac36ea7f95 init.sh: initialise variables AFTER path
That way, unnecessary work is avoided on child instances.

Of course, the current check assumes that TMPDIR wasn't
already set by a wily user before running lbmk, but then
those sorts of users probably know what they're doing.

If they don't know, they will soon find out. Therefore, I
have added additional checks on child instances, preventing
the build system from running if XBMK_CACHE is not set; if
it isn't, then that could very easy lead to certain system
files being overwritten.

The user must never know what happens if XBMK_CACHE is unset.
We simply will not allow it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 12:02:51 +01:00
Leah Rowe 484afcb919 init.sh: merge create_pathdirs with set_pyver
all this function does now is create the python symlink,
based on work that was already performed in set_pyver

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:40:58 +01:00
Leah Rowe d0bee6b4eb init.sh: Set python version only on parent
Do it after the creation of xbmkpath.

This avoids performing an unnecessary check, since
PATH will have already been corrected for child
instances; Python will already be correct there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:38:11 +01:00
Leah Rowe 4aa69a7d1f init.sh: remove useless command
we mkdir -p xbmklocal, only to remkdir it immediately
afterward, which is the intended behaviour; on parent
instances, xbmklocal is to be re-created fresh.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:30:11 +01:00
Leah Rowe 36ffe6ef50 init.sh: remove useless comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:29:54 +01:00
Leah Rowe 0343081d90 init.sh: xbmk_create_tmpdir to xbmk_mkdirs
this function now simply creates directories that lbmk
will use, rather than creating specific directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:28:57 +01:00
Leah Rowe c75bc0449d init.sh: move gnupath creation to create_tmpdir
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:28:15 +01:00
Leah Rowe 253aa81a3f init.sh: move PATH init to set_env
we must only set this in the parent instance, not
child instances. this prevents the variable from
being over-populated with repeated entries.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:26:28 +01:00
Leah Rowe e05a18d351 init.sh: check the lock file BEFORE git init
this way, initialisation will not be performed erroneously
while another parent instance of lbmk is running.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:21:30 +01:00
Leah Rowe cde3b7051e init.sh: return from child in set_env instead
This is earlier than the current check, thus preventing
the initialisation of a git repository and/or the recreation
of xbmktmp and xbmklocal by erroneous parent executions of lbmk
while another parent is running - the latter of which could have
caused a massively unpredictable build failure, so this is also
a pre-emptive bug fix, fixing all kinds of weird bugs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:18:45 +01:00
Leah Rowe 7ec9ee4228 inject.sh: shorten the nukemode variable name
just call it "nuke". this is what tells whether to remove
vendor files from an archive.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:12:20 +01:00
Leah Rowe b48eb161e4 vendor.sh: simplify mksha512sum()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 11:10:57 +01:00
Leah Rowe ac609d5aae vendor.sh: Remove _dest if it's bad
Also, provide more ample warning to the user

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 10:59:16 +01:00
Leah Rowe a3e1ed9823 release.sh: rename relsrc to rsrc
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 10:51:03 +01:00
Leah Rowe 44df3b2bff release.sh: tidy up nuke()
i wasn't ok having that variable initialisation and
then the commands on the same line. it looks messy.

having the commands on a separate line makes the code nice
to read, so let's separate them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-18 10:33:23 +01:00
Leah Rowe 3c58181f69 get.sh: remove useless message
the user doesn't care where the temporary git repo is

git shows that information anyway, in the git clone command

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 16:53:23 +01:00
Leah Rowe 01a0217c1e get.sh: simplify bad_checksum()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 16:51:12 +01:00
Leah Rowe 4ca57943d7 release.sh: simplify nuke() EVEN MORE, yet again
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 16:03:08 +01:00
Leah Rowe 47a3982bbe release.sh: use x_ on find command for nuke()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 15:49:24 +01:00
Leah Rowe 6dc71cc024 release.sh: simplify nuke() EVEN MORE
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 15:38:20 +01:00
Leah Rowe 05c07f7401 get.sh: move nuke() to release.sh
we really only need it there, because the context is
for release archives. normal use of the git repository
doesn't matter in the context of deletions, because that
will not be distributed. only the result of ./mk release
will be distributed.

the builds produced will not change as a result of this,
for people using the normal git repository, because the
files in question are never used anyway, in our configs.

this is being done to make working on local repos easier.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 15:20:02 +01:00
Leah Rowe 587d245caf release.sh: simplify prep_release_bin()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 13:17:09 +01:00
Leah Rowe 136bd66c28 mrc.sh: merge extract_mrc with extract_shellball
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 13:00:17 +01:00
Leah Rowe dbe109d7b5 release.sh: don't move src/docs/
otherwise, ./mk -b (without argument) will fail, on release
archives. also, perhaps i should add an mkhelper to build it?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 12:43:25 +01:00
Leah Rowe 840d6a1d27 get.sh: FURTHER simplify nuke()
this is getting almost comical now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 12:17:36 +01:00
Leah Rowe d2564fd945 get.sh: simplify tmpclone()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 11:08:06 +01:00
Leah Rowe 6dea381614 get.sh: fix bad mkdir command
this is the mkdir call that createsn the directory where
a cached git repository is moved to, during creation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-17 09:46:54 +01:00
Leah Rowe 6a2ed9428b vendor.sh: Fix broken KBC1126 insertion
On release archives, I overlooked the previous change to
downloads, during the recent implementation of extra safety
checks. I previously checked there whether the variable named
CONFIG_KBC1126_FIRMWARE was defined, and grabbed both; now I
check CONFIG_KBC1126_FW1 and CONFIG_KBC1126_FW2 separately,
grabbing each file separately.

This patch replicates that change for insertions. Otherwise,
hash verification on ROM images will fail, when running the
inject script on release images.

Downloading was being done, reliably, and the extracted files
were correct, so there was no danger if the user was building
from source and flashing that way.

However, checksum verification on full images failed when
inserting into archives. This is not because the files were
wrong; they were *correct*. However, the EC firmware was not
being inserted *at all* on HP EliteBooks, because of this
oversight. The check is now based on whether the paths to
the files themselves are defined, not whether EC firmware
is enabled in the coreboot config; the latter is implied.

With this patch, vendor file insertion once again works
perfectly, without error, on every board. There was no real
danger for users, just a minor inconvenience. Sorry!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-16 09:44:34 +01:00
Leah Rowe 4313b474a5 vendor.sh: additional safety check
the exit from mkdst can also be non-zero if mv or cp
failed, but there's no way to handle that reliably.

therefore, the checksum verification should be done
one final time, to compensate.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-16 07:03:08 +01:00
Leah Rowe d668f3a352 vendor.sh: Properly verify SHA512SUM on extraction
I currently check the downloaded files e.g. .exe file, but
then I don't check - or even define - sha512sums for the
files extracted from them e.g. me.bin

This patch fixes that. It also caches the hashed files, so
that extraction is faster on a re-run - this makes release
builds go faster, when running ./mk release

If a checksum is not defined, i.e. blank, then a warning is
given, telling you to check a specific directory. This way,
when adding new vendor files, you can add it first without
specifying the checksum, e.g. me.bin checksum. Then you can
manually inspect the files that were extracted, and define it,
then test again.

In a given pkg.cfg for config/vendor, the following variables
are now available for use:

FSPM_bin_hash for fsp m module
FSPS_bin_hash for fsp s module
EC_FW1_hash for KBC1126 EC firmware (1st file)
EC_FW2_hash for KBC1126 EC firmware (2nd file)
ME_bin_hash for me.bin
MRC_bin_hash for mrc.bin (broadwell boards)
REF_bin_hash for refcode (broadwell boards)
SCH5545EC_bin_hash for sch5545 firmware (Dell Precision T1650)
TBFW_bin_hash for Lenovo ThunderBolt firmware (e.g. T480/T480s)
E6400_VGA_bin_hash for Dell E6400 Nvidia VGA ROM

In practise, most people use release archives, and the
inject script, so I knew those were reliable, because the ROM
images were hashed prior to removing files. This patch benefits
people using lbmk.git directly, without using release files,
because now they know they have a valid file e.g. me.bin

Previously, only the download was checked, not the extracted
files, which meant that the only thing preventing a brick was
the code not being buggy. Any number of bugs could pop up in
the future, so this new level of integrity will protect against
such a scenario, and provide early warning prompting bug fixes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-16 05:39:18 +01:00
Leah Rowe a191d22bd6 get.sh: add missing eval to dx_ in nuke()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-15 02:41:04 +01:00
Leah Rowe c8813c9a14 properly exit 1 when calling fx_
in a few places, we use the presence of a file found
by fx_ to cause an exit, but the command that runs
looks something like:

exit 1 "string"

this yields an error, and a non-zero exit, because of
too many arguments to "exit", but we wanted a non-zero
exit anyway.

nevertheless, this is incorrect.

to fix it, eval is used instead. if the never-going-to-exist
condition one day exists where exit 1 actually returns, not,
you know, exits, we will use err instead, with the string
as argument.

this should be fine. it's a bit hacky, but so is fx_, and
it works. fx_ is used in several places to keep the sloccount
down, providing a common way to perform while loops on the
output of a command; that is its only purpose..

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-15 02:25:02 +01:00
Leah Rowe 208dfc89bd get.sh: simplify nuke()
more specifically, re-write it so that it can be called with fx_

this means that the single-tree check for nuke.list can be made
much simpler

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-15 02:12:04 +01:00
Leah Rowe 46f42291d3 get.sh: fix broken printf statement
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 18:06:29 +01:00
Leah Rowe f29aa9c8d5 get.sh: use subshells on try_ functions
This way, we can use x_ which will then print the command
that failed, if we need to debug future errors.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 17:03:32 +01:00
Leah Rowe e62886deda get.sh: simplify try_copy()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:59:59 +01:00
Leah Rowe d9ed03f9ea get.sh submodules: Don't delete files recursively
I overlooked this in a previous patch. It doesn't really
matter, since we're operating on a file anyway, but it's
not correct.

Files should have rm -f on them, not rm -Rf, for deletion.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:52:33 +01:00
Leah Rowe 8d5475ed5b get.sh: simplify fetch_submodules() config check
We already do what the old code does in setcfg, by
virtue of the fact that the st variable is later
checked, after loading this config conditionally,
where the st variable is otherwise blank.

We can avoid the unnecessary work after loading
the config, by returning if the config is absent.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:48:25 +01:00
Leah Rowe 21867b7d80 get.sh: simplify fetch_submodules()
We are calling xbmkget in the same way, whether it's
a subfile or subrepo.

Rename these variables to subcurl and subgit, so that we
can call xbmkget unconditionally.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:39:51 +01:00
Leah Rowe e9fe5a74a2 get.sh: fix caching of crossgcc tarballs
they were always re-downloading every time.

i've basically re-written most of xbmkget.

there was some erroneous conditions under which
it wrongly deleted the cached file, resulting in
it being downloaded again.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-14 16:28:29 +01:00
Leah Rowe 6089716f07 release.sh: Don't run prep_release with fx_
The result of the printf statement is sorted, making
it do binaries first, which results in a lot of junk
files then being present inside the source archive.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 22:17:37 +01:00
Leah Rowe b04c86e574 git.sh: rename to get.sh
it now handles more than just git, and i forsee
it handling even more in the future, e.g. rsync,
ftp, bittorrent.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 22:00:28 +01:00
Leah Rowe 3c23ff4fa1 git.sh: Only create destination repo on success
Don't leave a broken cache laying around, which would
otherwise break lbmk for the user.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 21:57:34 +01:00
Leah Rowe ed8a33d6fb git.sh: cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 20:47:41 +01:00
Leah Rowe 1ca26c5d23 git.sh: Re-implement redundant git downloads
And this time it works.

I'm now calling xbmkget() which in turn calls tmpclone(),
instead of me calling tmpclone() directly.

The git-pull is done on both remotes, regardless of whether
the first succeeds. This way, if I forgot to update a mirror,
downloads would probably still work.

This also fixes an issue people were having, for example where
the gnulib repository of GRUB was always being downloaded
every time.

I'm using a new directory, XBMK_CACHE/clone, instead
of XBMK_CACHE/repo (which I used before), in case people
still have the old caches from before.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-13 20:25:37 +01:00
Leah Rowe e38805a944 rom.sh: reduce indendation in check_coreboot_utils
call it via fx_, instead of using a for loop

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 21:32:07 +01:00
Leah Rowe 6bf24221e6 release.sh: simplify release()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 21:11:34 +01:00
Leah Rowe 66f7ecdb2d release.sh: clean up the vdir after release
do this after moving the version directory within it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 21:04:48 +01:00
Leah Rowe d4c0479093 release.sh: remove src_dirname variable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 20:25:35 +01:00
Leah Rowe 6d3a6347c3 release.sh: build in tmp directory first
don't move to the real directory until the work
is done.

that way, a re-try can be done, while analysing
the old files. it is created based on the tmpdir,
under XBMK_CACHE/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 20:23:41 +01:00
Leah Rowe a0105e1ab4 release.sh: remove unnecessary mkdir command
the following git clone command creates that directory

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 20:07:50 +01:00
Leah Rowe f4871da9bc release.sh: split up build_release()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 19:49:50 +01:00
Leah Rowe c85aff5c54 release.sh: delete tmp/cache from the tarball
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 19:29:58 +01:00
Leah Rowe 92954eeb38 lib.sh: remove rmgit()
We don't need to call it from git.sh, because it's
only being done when building a release anyway,
and we already run rmgit when doing a release.

The function itself is only two simple fx_ calls,
so we can just do that from build_release().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 19:20:50 +01:00
Leah Rowe 05b5914b35 lib.sh: remove mk()
i don't need it. i can use fx_ instead, on functions
that previously called mk().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 18:05:32 +01:00
Leah Rowe c9696e2333 lib.sh: move xbmkget() to git.sh
in cbmk, it's only used from there.

in lbmk, it's also used from vendor.sh.

however, i plan to further expand git.sh at
some point, tidying it up so that git cloning
is also done from xbmkget, with dlop=git and
git.sh would then be renamed to get.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 16:30:05 +01:00
Leah Rowe 23913bb8d2 lib.sh: move mksha512sum() to vendor.sh
this is unused in cbmk.

it's only used from vendor.sh.

therefore, lbmk shall have it in vendor.sh.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 16:20:34 +01:00
Leah Rowe 80f0562e8d lib.sh: split up try_file()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:44:31 +01:00
Leah Rowe 89cd828e87 lib.sh: move _ua to try_file()
it's only used there

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:32:50 +01:00
Leah Rowe 308a9ab1e1 mrc.sh: minor cleanup
group the cbfs command to the extract command, since they
are related. this makes it clearer that the following
command to extract refcode is unrelated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:06:25 +01:00
Leah Rowe 40163dcfa4 mrc.sh: update copyright year to include 2025
I've made several modifications to the file, this year.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 15:05:21 +01:00
Leah Rowe ef800b652c inject.sh: remove the hashfiles variable
we only use it once, and it's a trivial string

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:52:27 +01:00
Leah Rowe 311ae2f8df inject.sh: define xchanged here instead
this is used here, and also needed in cbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:49:14 +01:00
Leah Rowe 76f81697e6 vendor.sh: remove check_vcfg()
We don't need it. The vfile variable is only used in
one place, and only once, for use with setcfg.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:47:43 +01:00
Leah Rowe 97d4d020d9 vendor.sh: simplify getvfile()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:30:27 +01:00
Leah Rowe 57f896ac01 vendor.sh: simplify setvfile()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 14:23:32 +01:00
Leah Rowe 3879f6c4d8 lib.sh: use fx_ in rmgit()
with fx_, i have more much granular control over
how errors are handled.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 13:21:59 +01:00
Leah Rowe 0911a5a5ae lib.sh: split up xbmkget()
it was too complicated. most of the logic has been moved
to a new function, try_file()

the for loop is handled by xbmkget(), whereas each try
is now handled in try_file()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-12 13:16:10 +01:00
Leah Rowe a449afb287 inject.sh: only compile nvmutil if needed
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:56:28 +01:00
Leah Rowe 2bbf2ae80b inject.sh: simplified serprog check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:52:47 +01:00
Leah Rowe 9c27b7437c vendor.sh: tidy up variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:43:34 +01:00
Leah Rowe 0cc816167b vendor.sh: split up setvfile()
split the actual bootstrapping to getvfile()

setvfile only sets the config, but then it will
call getvfile() to act on that config.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-11 00:39:01 +01:00
Leah Rowe 7d90d43425 remove another confusing message
the current message says the file name, and implies that
the given file has already been updated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:51:38 +01:00
Leah Rowe a0c436ad4b inject.sh: Remove confusing path on tar creation
The path is wrong. The correct path is printed afterward.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:48:38 +01:00
Leah Rowe dcfd3e632e inject.sh: re-add mac address confirmation
it just makes the script more user-friendly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:23:46 +01:00
Leah Rowe e5af201060 inject.sh: further cleanup for vendor.sh
i moved out more code to vendor.sh, to reduce the
amount of lbmk-only code on inject.sh

this should reduce the number of merge conflicts
even further, when cherry picking from lbmk to cbmk.

in particular, vendor file insertion is now handled
entirely through the "setvfile" function, instead
of from inject.sh, which seems counterintuitive,
but remember that inject.sh also does MAC addresses.

therefore, the inject.sh script is now primarily for
inserting MAC addresses, and handles vendor downloads
in a slightly more convoluted way, but still easy
enough to understand if you read it a bit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 20:06:41 +01:00
Leah Rowe 0aa99f4bf8 tree.sh: only create elfdir in copy_elf()
otherwise, we create empty directories where build.list
doesn't exist, like on coreboot.

we already create a directory when needed, when actually
copying elf files, so let's just leave it at that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 17:58:22 +01:00
Leah Rowe a8e374020c tree.sh: simplified srcdir check on make-clean
this is the check that ksips a given target if the tree
directory does not exist, on the clean command.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 17:19:00 +01:00
Leah Rowe 0f931b508a inject.sh: split to vendor.sh the download parts
to the extent feasible, keep lbmk-specific parts on
inject.sh to a minimum. this will later be used to
re-sync cbmk's inject.sh with lbmk's, because cbmk's
one doesn't handle vendor files.

the way this is designed now, with this patch, will
make cherry-picking lbmk to cbmk easier in the future,
when keeping this part of cbmk in sync with lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 13:03:16 +01:00
Leah Rowe 3554b5aad9 inject.sh: split up the inject functions
generally go for a more linear function order, and
split up any functions.

the objective is to have functions only suitable to
libreboot be separate. more splitting will be done,
and eventually the vendor-download functions will be
split into a new file, as will several other functions.

this is being done as part of an effort to bring the
libreboot and canoeboot versions of inject.sh in sync,
so that from now on, cherry picking between the two
projects will produce fewer merge conflicts and require
a lesser amount of post-merge maintenance.

some other minor cleanup has also been done; for example,
the "need_files" variable is redundant and was removed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-10 10:45:48 +01:00
Leah Rowe 81dbde7e09 lbmk: use x_ instead of err, where appropriate
many places in lbmk used err, because older versions
of x_ did not handle globbing properly.

however, use of x_ is preferable on trivial commands.

the only time err() should be called is what it has
to be, when x_ can't work, or when a more useful error
message is needed, for context.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 20:54:23 +01:00
Leah Rowe 14d46abced mrc.sh: operate on refcode in tmp area first
that way, the Intel GbE device can be enabled there,
and only then would the refcode file be copied.

otherwise, the current behaviour would leave buggy
refcode in place, if the dd command failed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 20:31:00 +01:00
Leah Rowe 6e521c2e1e mrc.sh: fix outdated info in the comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 20:21:58 +01:00
Leah Rowe 23486abef3 inject.sh: use direct comparison for metmp
use of the e function would slow down execution,
and it's mostly unnecessary in this case.

the e function is only needed if we want to confirm
via user message that a file exists. that is not
needed here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 00:26:33 +01:00
Leah Rowe 91220ce183 inject.sh: use subshell to speed up find_me()
the current test allows a further extraction after
running mecleaner, even if me.bin was found.

further, any recursive calls that exit non-ze
don't lot the loop acthually stop, unless we
subshell that too, otherwise fx_ is returned to
return 0 when a given command it runs returns 1,
or more specifically: the for loop in x_ breaks.

this is by design, and there's not much that can
be done, but this patch should pseed up extraction
a little bit, when dealing with intel me files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-09 00:20:33 +01:00
Leah Rowe ff33ec3352 mk: use zero exit instead, to run trees
that way, with set -u -e, we aren't risking some
buggy sh implementations from causing an error exit
where it shouldn't.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:41:24 +01:00
Leah Rowe c2b627dc6d remove useless comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:36:44 +01:00
Leah Rowe 066402b7e7 mk: remove unnecessary line break
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:35:40 +01:00
Leah Rowe 7012c00ed1 mk: re-split tree logic to include/tree.sh
I really think mk should just be a small stub.

Better to keep everything separate.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:33:49 +01:00
Leah Rowe 50ce1ac9b2 mk: move release functions to idnclude/release.sh
The idea with mk is that it's meant to basically be a
stub for running everything else, while mainly having
the trees logic within it (what was once script/trees).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 23:28:49 +01:00
Leah Rowe 1ce3e7a3d3 mk: add missing error handli for mk -f
on the release command, that is

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 22:17:35 +01:00
Leah Rowe 0d876622fc git.sh: re-write tmpclone without caching
remove caching for now. it's buggy as hell.

will re-write the caching feature next.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 22:14:43 +01:00
Leah Rowe 454f11bdd7 git.sh: use setvars for fail variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 21:50:17 +01:00
Leah Rowe 6bdb15fd32 git.sh: hard fail if git am fails
similar to the last patch, we must ensure that the
inability to patch will cause a hard exit, regardless
of any redundancy we have for cloning.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 21:36:37 +01:00
Leah Rowe 93d4eca04a git.sh: Hard fail if reset fails
We allow a re-try when cloning fails, to account
for redundancy, but resetfail currently doesn't
cause any error exit at all.

This patch mitigates that bug.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 21:33:17 +01:00
Leah Rowe a3ba8acfac init.sh: Only check XBMK_CACHE if it exists
Otherwise, if it doesn't exist, the current check will
wrongly exit with error status, preventing you from
running the build system at all!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 20:49:49 +01:00
Leah Rowe 021e7615c8 HP 820 G2: Use fam15h cbfstool tree for refcode
We used cbfstool from coreboot 4.13, because it was the
last version to work with the particular format used
for stage files, before the CBFS standard changed in newer
releases of cbfstool.

When I added this board to Libreboot, it was source-only at
first so it didn't matter. I didn't want to do a standalone
cbfstool binary, in case some people decided to use that one
on newer boards, which would cause all sorts of issues.

So I bodged it and just included an import of coreboot 4.13.

Well, the cbfstool from coreboot 4.11, as used for FAM15H
AMD boards, is compatible. I checked the code diff between
the two, and there is no meaningful difference.

I've tested this, and it works, since the last release or
two now includes 820 G2 images, so I  was able to use those
with ./mk inject, to verify whether the refcode file is
still grabbed properly. We need the refcode to handle MRC
on Broadwell platform, but we extract it from an old Google
Chromebook image, that uses the old CBFS stage file layout.

This change solves my problem: the problem was that releases
are bloated further, due to including this extra coreboot
version. This should reduce the size of the next release
considerably, especially after decompressing the tarball.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 20:46:05 +01:00
Leah Rowe fe92605244 also fix the other grub trees
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-08 11:12:34 +01:00
Leah Rowe a8594762d2 Merge pull request 'fix trying to boot all logical volumes after unlocking an encrypted volume' (#330) from cqst/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/330
2025-05-08 10:11:13 +00:00
cqst e084b06dc7 fix trying to boot all logical volumes after unlocking an encrypted volume 2025-05-08 02:28:58 -07:00
Leah Rowe 2cea8517f3 init.sh: remove useless export
we already reset to n if not y, afterward

just rely on that

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 21:16:50 +01:00
Leah Rowe 1b0afdcea2 init.sh: also allow XBMK_RELEASE=Y or N
as opposed to =n or =y

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:23:32 +01:00
Leah Rowe 570f1417a8 init.sh: Resolve XBMK_CACHE via readlink
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:14:36 +01:00
Leah Rowe e1af1055ed init.sh: check XBMK_CACHE is a directory instead
it doesn't matter if it's not a file. that's the wrong check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:09:29 +01:00
Leah Rowe e1628ad8f3 init.sh: export LOCALVERSION in set_env
Don't do it in set_version

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:04:52 +01:00
Leah Rowe 40a944118f init.sh: run set_version before set_env
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:03:51 +01:00
Leah Rowe cba04aa74b init.sh: Use readlink in pybin()
Use realpath only as a fallback.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 19:00:13 +01:00
Leah Rowe a94bd3c093 inject.sh: simplify extract_kbc1126ec()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 17:08:42 +01:00
Leah Rowe e3098c61f4 inject.sh: simplified MAC address handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 17:00:41 +01:00
Leah Rowe d530e68594 inject.sh: Simplify patch_release_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 16:53:57 +01:00
Leah Rowe 7f71328f0e lib.sh: Remove useless command in err()
We don't need this, since we're exiting anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 16:23:12 +01:00
Leah Rowe 394b4ea7a5 inject.sh: rename copytb and preprom functions
make them shorter so they go on one line again

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 15:17:45 +01:00
Leah Rowe ec5c954337 lib.sh: Simplified fx_() and removed fe_()
Instead of calling fe_, prefix x_ as indicated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 15:12:10 +01:00
Leah Rowe 1390f7f800 mk: Create serprog tarballs here instead
i simplified rom.sh to use mkhelper for actual image
building.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 14:21:28 +01:00
Leah Rowe 0ef77e6583 build serprog using fe_ *defined inside mkhelper*
sh macros ftw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 14:01:50 +01:00
Leah Rowe d2e6f989d7 rom.sh: build serprog images with fe_
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 13:44:05 +01:00
Leah Rowe 0faef89946 lib.sh: support any command on find_exec()
right now, we assume "find", but it adds any number of
arguments next to that.

change it instead to support any command, where the
assumption is that it would generate a list of files
and directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 13:28:55 +01:00
Leah Rowe 2b7f6b7d7c inject.sh: Simplify extract_intel_me_bruteforce()
This is probably about as small as it's going to get.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-07 10:20:59 +01:00
Leah Rowe 485d785d33 inject.sh: clean up tmp me file before extract
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 21:16:06 +01:00
Leah Rowe fac99aa2d4 lib.sh: re-add missing break in fe/fx_
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 20:24:32 +01:00
Leah Rowe 03300766d1 inject.sh: tidy up extract_intel_me_bruteforce
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:47:08 +01:00
Leah Rowe 4781dbd2a0 inject.sh: fix oversight in me bruteforce
i used i instead of 1, in the variable when running
the extract_archive function.

this didn't trigger since +u was set, and +e was set.

in practise, then, it seems that because of this, and
because my ME extract/insert test was a success, that
none of the archives we use actually have a ME inside
of a file inside of a given downloaded archive.

still, this is technically incorrect, so fix it!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:43:44 +01:00
Leah Rowe cf78583a6d inject.sh: remove unnecessary check
the call stack already falls through with  a bunch of return
1s after a successful run of me_cleaner, so it's really not
necessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:32:18 +01:00
Leah Rowe 5657cc1afb inject.sh: don't use subshell for me bruteforce
i needed it on the old version, which used cd

this one stays in the same directory at all times

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 19:30:55 +01:00
Leah Rowe 5686f35e0f inject.sh: insanely optimise the me bruteforce
use fe_

fe_ ftw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 18:59:32 +01:00
Leah Rowe e8be3fd1d4 git.sh: Simplify git am handling
fx_ and fe_ really are the best shell functions ever.

really. they're the best.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 11:09:39 +01:00
Leah Rowe 4c1de1ad12 inject.sh: remove unused function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-06 04:49:56 +01:00
Leah Rowe 282b939d9d init.sh: New function dx_ to execute path files
Generated by find, this is a wrapper in place of using
for loops everywhere. This simplification temporarily
increases the amount of code, because we don't do this
a lot, but this will reduce the growth of the build
system code size in future changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 21:37:16 +01:00
Leah Rowe 73074dedee inject.sh: Further simplified FSP extraction
We don't need the copy command at all, since the files
it copies are the only ones that the Python script does
anyway, so now we just make that script output to the
directory, directly, where these files must go.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 21:13:28 +01:00
Leah Rowe 7585336b91 inject.sh: simplify kconfig scanning
Use fe_ with a new function, scankconfig, to do the
same thing. Not only is this simpler, it now also
operates on all coreboot configs for a given target,
whereas it previously only operated on the first one.

This is useful for cases where one config might use a
file that the other one does not; in practise, we don't
do this yet, but it's a theoretical possibility

Also: don't use the function check_defconfig, which is
now redundant and has been removed.

That function also conflicted with another function by
the same name in mk, but fortunately didn't cause an
issue in practise, due to how sh works; when vendor.sh
was used, it was without running the tree commands,
except under a separate lbmk instance.

So this is a simplification, a feature enhancement and
even a bug fix, all wrapped into one!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 21:05:45 +01:00
Leah Rowe ef38333f8b lib.sh find_ex: Write sort errors to /dev/null
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:45:31 +01:00
Leah Rowe c275f35e7e lib.sh x_(): Remove warning of empty args
It's completely unnecessary, and I forsee this
check breaking the build system at some point,
since some commands rely on the output of other
commands. Therefore, I've removed this check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:41:48 +01:00
Leah Rowe 17d826d3a9 lbmk: Replace err with much simpler implementation
The current implementation is insanely over-engineered,
and completely unnecessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:38:19 +01:00
Leah Rowe f98e34a24d singletree/elfcheck: use fx_, not fe_
fe_ returns an error on the find command, but we rely
on the only error ever being our intentional exit, upon
discovering files.

in singletree, the directory being checked was already
checked first, so we know it's safe not to err on find;
and find not reporting an error if no files are found is
ok.

on elfcheck, it's very much the same thing. In fact, we
very much want it to return 0 if the directory doesn't
exist, or if files don't exist within it.

Therefore, use fx_ which is designed for this use-case.

Quick re-cap: fx and fe execute a given function name with
each line outputting by find as an argument, each time. It
is somewhat similar in scope to find's -exec command.

We use fe_ as shorthand in several places all over lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 20:33:02 +01:00
Leah Rowe 8ca06463eb rom.sh: Print the rom image path being generated
This message used to exist, and it's a nice feedback
for the user, to confirm that the build went OK.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 18:14:44 +01:00
Leah Rowe dc9fe517cb rom.sh: Safer cprom()
Don't insert special files like GRUB keymaps after
copying to the final destination.

Instead, copy the tmprom to /tmp and operate on that,
in these instances.

This is less efficient, depending on the user's
configuration; if /tmp is on the same file system as
the user's xbmkpwd, it should be fine. However, the
actual performance hit isn't that bad in practise,
on most setups.

If the user's /tmp is a tmpfs, then that means using
tmpfs, but it's one image at a time. It should be OK.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 18:08:55 +01:00
Leah Rowe 2be8d1c798 rom.sh: specifically check keymaps in cprom()
"not seauboot" is a valid check at present, but if
i start supporting other arguments in the future,
this code would have to change.

therefore, i change it in advance, on that theory.

this new check is more technically correct. these
lines are triggered when inserting grub keymaps.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 17:53:43 +01:00
Leah Rowe 89a8cd4936 rom.sh: simplify mkseagrub()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 17:48:57 +01:00
Leah Rowe c2182d8219 mk: simplify elfcheck()
fe_() called inside subshell, ftw

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 15:51:04 +01:00
Leah Rowe 437ac2454c lib.sh: simplify singletree()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 15:40:08 +01:00
Leah Rowe 62ec3dac07 git.sh: move singletree() to lib.sh
it's also used by mk, to determine which build function
to use (build_project or build_targets).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 15:31:33 +01:00
Leah Rowe 6b247c93e2 mk: Fix bad error handling for gnu_setver
I mixed logical OR and AND by mistake. Oops!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe ee8bb28ba2 GRUB: Mark E820 reserved on coreboot memory
See, coreboot bug report:

https://ticket.coreboot.org/issues/590

We hadn't noticed this for quite a while, since we always
just booted with iomem=relaxed when needing to run cbmem,
since in practise it was always combined with other tasks
that require access to lower memory.

GRUB currently matches coreboot's own mmap for cbmem, but
for example SeaBIOS marks cbmem as E820 reserved. Therefore,
this change replicates the SeaBIOS behaviour.

Without this patch, Linux needs to boot with iomem=relaxed
for cbmem access, for example when running ./cbmem -1

With this patch, cbmem is now accessible regardless. This
patch also prevents Linux from overwriting parts of CBMEM.

Thanks go to Paul Menzel, who wrote this GRUB patch.

Thanks also go to Nicholas Chin, who provided testing, all
the way from Coreboot 25.03 back to Coreboot 4.20. It seems
that this is just something the payloads have to handle.

This means that both SeaBIOS and GRUB no longer have this
bug, in Libreboot; now what remains is to replicate the
test with our U-Boot payload.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe 61ec396ef6 inject.sh: simplify extract_intel_me_bruteforce()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe e4edc2194d inject.sh: Remove unnecessary check
_dest is already checked in the calling function fetch(),
after extract_tbfw() has been called.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe f4057d7daa inject.sh extract_intel_me(): reduce indentation
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:18 +01:00
Leah Rowe b7ca59debe inject.sh: Move FSP extraction only to extract_fsp
Don't do FSP-specific extraction in extract_archive, as
that is not what the latter is for.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 12:16:07 +01:00
Leah Rowe eb882de94c inject.sh: tidy up intel me handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 05:43:38 +01:00
Leah Rowe 153dd76a82 inject.sh: tidy up the deguard command
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 05:41:21 +01:00
Leah Rowe 428c46ca2b lib.sh: set -u -e in err()
Some parts of lbmk set +u +e, to be reset later on
under normal conditions upon exit. We must ensure
such level of integrity in err() as well.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-05 05:20:47 +01:00
Leah Rowe 20c8730858 lib.sh: Provide error message where none is given
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:53:02 +01:00
Leah Rowe 35265731c5 init.sh: Silence the output of git config --global
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:50:50 +01:00
Leah Rowe 5e3aaa1eb8 init.sh: Run git name/email check before init
Otherwise, it returns if init is already done, which
later leads to build errors in coreboot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:49:30 +01:00
Leah Rowe a3b5626f53 lib.sh: stricter xbmk_err check in err()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:35:31 +01:00
Leah Rowe 51b2a1159d lib.sh: simplify err-not-set handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:31:08 +01:00
Leah Rowe 61e5fd1a0b lib.sh: Add warning if x_ is called without args
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:28:22 +01:00
Leah Rowe 4020fb4328 lib.sh: simplify err()
Rely once again on err_, but still explicitly add an exit
just below, in case I made a mistake one day.

err() is essentially a trap that triggers in case I mess
up an error function, so that it doesn't reliably exit.

So, the idea is that everything calls err(), and err() is
almost never modified, or modified very carefully.

If error exits were ever broken, the result could be quite
unpredictable, so lbmk has very strict error handling, and
great care is taken to ensure that it does reliably exit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:23:11 +01:00
Leah Rowe b51846da6d init.sh: single-quote xbmklock in xbmk_lock()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:14:50 +01:00
Leah Rowe 8b7bd992f6 init.sh: define lock file in a variable instead
don't hardcode it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:12:23 +01:00
Leah Rowe 9611c19e7e init.sh: tidy up xbmk_child_exec()
make the command style more consistent, for example
relying on x_ inside a subshell to print the command
and arguments if a command failed.

this is a good style, and i'll probably use it in other
places on lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 16:03:34 +01:00
Leah Rowe 37ca0c90e1 lib.sh err: add missing redirect to stderr
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 10:18:33 +01:00
Leah Rowe 54291ebb72 lbmk: MUCH safer err function
Don't directly call a variable. Call a function that
checks the variable instead.

The new err function also checks whether an exit was
actually done, and exits 1 if not.

If an exit was done by the given function, but the exit
was zero, this is also corrected to perform an exit 1.

This fixes a longstanding design flaw of lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 10:13:42 +01:00
Leah Rowe 3f7dc2a55f lib.sh: rename errx to xmsg
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 09:17:23 +01:00
Leah Rowe 59c94664e3 lib.sh: Make x_ err if first arg is empty
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 09:14:09 +01:00
Leah Rowe 91bb6cbede lib.sh: Make err_ always exit no matter what
Always certainly redundant, since if -u -e isn't
set, it'll continue to exit anyway.

However, we want to be pedantic about this, since
the safety of lbmk relies entirely on this function
NOT misbehaving.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 09:10:24 +01:00
Leah Rowe b19c4f8f67 inject.sh: tidy up TBFW handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:50:23 +01:00
Leah Rowe 439020fbda inject.sh: remove useless comment block
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:47:56 +01:00
Leah Rowe 6e447876cc init.sh: tidy up the python version check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:47:12 +01:00
Leah Rowe 7392f6fc8e init.sh: move non-init functions to lib.sh
these were missed in a previous cleanup

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:33:17 +01:00
Leah Rowe 7acec7a3a1 init.sh: simplify dependencies handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:29:19 +01:00
Leah Rowe 93ba36ae45 rom.sh: tidy up copyps1bios()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:19:17 +01:00
Leah Rowe fc71e52fdf mk: tidy up xgccargs handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:15:00 +01:00
Leah Rowe 184871bc17 mk: remove useless code
this was added a few commits ago, but the previous commit
made me realise it's not needed at all.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:10:59 +01:00
Leah Rowe b6a2dc4ea3 init.sh: tidy up pathdir creation
we can use remkdir here. it does the same thing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:10:36 +01:00
Leah Rowe f5b2bdb886 mk: re-make gnupath/ after handling crossgcc
instead of deleting every file within

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:07:53 +01:00
Leah Rowe 1b7a9fd637 mk: tidy up check_cross_compiler
only initialise variables at the point they're needed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:07:06 +01:00
Leah Rowe 488d52e784 mk: re-make gnupath/ for each cross compiler
it could be that some were left over before, for some
reason. that isn't currently the case, but this will
avoid the possibility in future.

therefore, this is a preemptive bug fix.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:05:19 +01:00
Leah Rowe c33467df1e mk: reduce indentation in check_cross_compiler()
we only call it in one place. the resulting code is still
quite clear.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-04 08:02:14 +01:00
Leah Rowe aa4083443b mk: Allow use of x_ on prefix functions
Use this for the sha512sum command, on the main mk
script at the function check_project_hashes().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 18:30:37 +01:00
Leah Rowe 8f828e6cd3 mk: tidy up check_project_hashes() sha512sum check
the extra function isn't needed at all. awk can just
handle every line all at once.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 18:18:41 +01:00
Leah Rowe 7a2f33264d mk: simplify check_gnu_path()
the initial checks are unnecessary, since i always know
what arguments are being provided.

the -f check in the for loop is now an -x instead, more
efficient and complete.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 18:05:37 +01:00
Leah Rowe 46b968a6e8 inject.sh: minor code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 13:49:49 +01:00
Leah Rowe 5499ae66bd inject.sh: simplify extract_archive()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 13:35:28 +01:00
Leah Rowe 72f4412a52 inject.sh: simplified fsp extraction
we know that _dest is always what's set in the coreboot config,
without the ../../../ in it, so just copy both files in a single
function, and call the function twice.

if both files are done on the first call, the second call will
be skipped. if only the first file was done on the  first call,
running the download script again will skip the  first one, and
grab the second one.

this also avoids having to run the decat function twice, in most
cases, so it's a tiny optimisation.

this optimisation only works if both fsp files (s and m) are to
be extracted into the same directory, which is the case anyway,
and this will always be the case.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 13:28:47 +01:00
Leah Rowe bf569d2b4d inject.sh: Remove redundant code in copy_tbfw
We don't use the tbtmp variable anymore, in this function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:20:48 +01:00
Leah Rowe 8de0ed811f inject.sh: Stricter TBFW handling
Don't copy it until it has been padded properly.

Otherwise, erroneous padding would result in an error,
and who knows what would be left in vendorfiles/ ?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:17:21 +01:00
Leah Rowe 530e4109a2 init.sh: *Re-create* tmpdirs on parent instance
To make sure any old files are removed, always re-create.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:05:38 +01:00
Leah Rowe 498f5a26cc init.sh: Always create xbmklocal
If we're in a release work directory, TMPDIR is already
set, so the local ./tmp won't be created, which would
lead to an error.

Fix it by creating xbmklocal before checking TMPDIR.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:04:34 +01:00
Leah Rowe 00d22f2082 lbmk: Unified local ./tmp handling
Make it an absolute directory, relative to xbmktmp.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 07:01:19 +01:00
Leah Rowe 0f7b3691ab lib.sh: redirect find errors to /dev/null
this silences confusing error messages that the user
sees on the screen, that are actually benign, and it
will thus reduce the number of people who ask questions
on #libreboot irc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:41:20 +01:00
Leah Rowe 7fadb17fd9 lib.sh: Fix bad touch command
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:36:43 +01:00
Leah Rowe 0b09d97073 inject.sh: Only build nvmutil once
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:35:48 +01:00
Leah Rowe 308df9ca40 inject.sh: always re-build nvmutil
it's not a lot of code, and takes less than a second.

the previous change uses x instead of ?, but this would
cause an error if the nvmutil was already built, because
the makefile might cause a build to be skipped.

therefore, force a re-build to mitigate the error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:28:14 +01:00
Leah Rowe 44a1cc9ef8 util/nvmutil: use x, not ?, for random characters
A user reported that '?' causes an error on zsh. See:

https://codeberg.org/libreboot/lbmk/issues/261

For example:

./mk inject libreboot-XXXXXX.tar.xz setmac ??:??:??:??:??:??

The user got:

 zsh: no matches found: ??:??:??:??:??:??

The mitigation here is to double-quote, e.g.:

./mk inject libreboot-XXXXXX.tar.xz setmac "??:??:??:??:??:??"

However, a lot of people won't do that. Therefore, I will
retain the current behaviour but support x/X for randomness.

Now lbmk uses x by default, instead. I will now update the
documentation, accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 06:23:10 +01:00
Leah Rowe a17875c345 lib.sh find_ex: explicitly create the tmp file
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:57:39 +01:00
Leah Rowe 0ffaf5c733 init.sh: Explicitly create the xbmktmp directory
mktemp would normally do it, but we must not rely on that

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:33:02 +01:00
Leah Rowe fcc52b986e init.sh: unified handling of ./tmp
not to be confused with /tmp

we use ./tmp inside the lbmk work directory, for large files,
because /tmp might not be very big, or might be a tmpfs

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:32:01 +01:00
Leah Rowe 47762c84ad lib.sh: add fe_ which is fx_ but err on find
In the mk script, we need fx_ to not return errors on the
find command, since it's searching a bunch of directories
where some of them may not exist.

All other instances where fx_ is used, must return an error
if the directory being searched doesn't exist.

For this, fe_() is introduced, which does the same as fx_
but with this much stricter check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:25:11 +01:00
Leah Rowe d18d1c2cae lbmk: unified execution on find commands
We have a lot of places in lbmk where the output of find is
used, and then some function is executed on the result.

This is messy, and bloats several of these functions.

Now this is unified, into a new function: fx_

What fx_ does is execute a given function, for each result
found, with the arguments for a find command appended.

For example:

find -name ".git"

If you wanted to do: foo "$arg"

Where "arg" is a search result from find, and you wanted
to execute "foo" on each one, you would do:

fx_ foo -name ".git"

The find utility does have an -exec feature, but I've found
that it only works for executables, not functions.

fx_ does not return errors, so "foo" in this example
would have to do its own error handling.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-03 05:02:31 +01:00
Leah Rowe 773d2deaca NEW MAINBOARD: Dell Precision T1700 SFF and MT
This is similar to the 9020SFF, but this board has ECC support.
However, the native raminit isn't used here, even though it is
otherwise compatible, because the native init doesn't do ECC yet.

The broadwell mrc.bin has ECC support, which is also used on the
HP EliteBook 820 G2. The MRC for broadwell can be used on haswell
boards such as the T1700.

Add both the SFF and MT variants. Since these are identical to the
9020 variants, except for slightly different PCH enabling ECC, we
can just re-use the 9020 port without issue.

We *could* add a variant to coreboot, for T1700, but there is not
really any pressing need. It is simply the 9020sff/mt with mrc.bin

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 17:18:55 +01:00
Leah Rowe 9b11e93686 mk: include rom.sh directly
remove it from mkhelper files, because rom.sh doesn't
initialise any variables globally, except one that
never changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 11:20:55 +01:00
Leah Rowe 1f7e4b35cb mk: Download vendorfiles before building release
Do it just after creating the src archive. This way,
everything is downloaded all at once.

Otherwise, a momentary lapse of internet uptime will
cause a release build to fail later on, and one of
lbmk's flaws is that this would then mean you must
re-build from scratch.

If we assume that the internet is working within a
short period of time, then this change would mitigate
that possibility. If something did happen during tar
archive creation, that's a much shorter amount of time
that is "wasted".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 10:56:14 +01:00
Leah Rowe acb0ea202f lib.sh: Simplify rmgit()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 10:52:38 +01:00
Leah Rowe 15b76bc202 lib.sh: support multiple arguments in remkdir()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 07:26:39 +01:00
Leah Rowe f3ae3dbbbe lib.sh: simplify remkdir()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 07:26:17 +01:00
Leah Rowe 6c4d88f268 move x_() to lib.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 07:24:11 +01:00
Leah Rowe 2ae565ba93 init.sh: move setvars/err_ to lib.sh
these functions make more sense in lib.sh

i made mk link lib.sh first, so that the
functions on init.sh can still use them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 05:54:36 +01:00
Leah Rowe c073ee9d4f Restore SeaBIOS 9029a010 update, but with AHCI fix
I fixed the AHCI bug, with a patch that I wrote. It works by
restoring the old SeaBIOS AHCI initialisation behaviour, whereby
the AHCI controller is enabled from its current state; the patch
that broke AHCI in coreboot (tested on ThinkPad T420), changed
AHCI initialisation behaviour so that the controller's state is
first reset, prior to enablement.

However, my patch also retains the new AHCI initialisation
behaviour, when a CSM is in use. The AHCI reset patch was done,
by the author, specifically for SeaBIOS in CSM mode, so it makes
sense to only change the behaviour conditionally according to that.

This reverts commit 8245f0b321.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-02 02:24:07 +01:00
Leah Rowe 8245f0b321 Revert "seabios: bump to rev 9029a010, 4 March 2025"
This reverts commit a08b8d94fc.

From #libreboot IRC today:

07:02 <irys> ooh this is fun. seabios commit 8863cbbd15a73b03153553c562f5b1fb939ad4d7 (ahci: add controller reset) breaks ahci entirely on t420
07:05 <irys> cbmem console on that seabios commit has a timeout then "AHCI/0: device not ready"
07:07 <irys> AHCI works fine if i change config/seabios/default/target.cfg to use the immediate previous seabios commit (df9dd418b3b0e586cb208125094620fc7f90f23d)
07:07 <irys> works in grub payload either way though
07:31 <irys> here, `cbmem -c` after booting the broken rev: https://0x0.st/84oQ.log
07:31 <irys> compared to the working one https://0x0.st/84o1.log
07:33 <irys> i can't report to upstream myself *right now* but i figure you might want to know about this leah

I have downloaded those logs locally for reference, so that an upstream
report can be made to SeaBIOS. For the purposes of this Libreboot commit,
the diff of the logs is as follows (diff -u broken.log working.log):

Taking each diff line out of the log, the relevant entries
seem to be:

Searching bootorder for: /pci@i0cf8/*@1f,2/drive@0/disk@0
+AHCI/0: Set transfer mode to UDMA-6
+Searching bios-geometry for: /pci@i0cf8/*@1f,2/drive@0/disk@0
+AHCI/0: registering: "AHCI/0: Netac SSD 128GB ATA-11 Hard-Disk (119 GiBytes)"

-WARNING - Timeout at ahci_port_setup:477!
-AHCI/0: device not ready (tf 0x80)
-All threads complete.

-2. Payload [memtest]
+2. AHCI/0: Netac SSD 128GB ATA-11 Hard-Disk (119 GiBytes)
+3. Payload [memtest]

-Space available for UMB: c7000-eb800, f5880-f5ff0
-Returned 16777216 bytes of ZoneHigh
+drive 0x000f5fa0: PCHS=16383/16/63 translation=lba LCHS=1024/255/63 s=250069680
+Space available for UMB: c7000-eb800, f5880-f5fa0
+Returned 16773120 bytes of ZoneHigh

Therefore, the revision will be reverted back for now. It was
only about 8 additional patches imported in the update anyway.
2025-05-01 14:30:14 +01:00
Leah Rowe 4c50157234 coreboot/t420_8mb: add missing txtmode config
Reported by irys on #libreboot irc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-05-01 14:29:22 +01:00
Leah Rowe f21749da8b Libreboot 25.04 Corny Calamity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 12:28:46 +01:00
Leah Rowe bb5f5cd576 add pico-sdk backport patch fixing gcc 14.x
src/rp2_common/boot_stage2/boot2_w25x10cl.S:142: Error: junk at end of line, first unrecognized character is `0'
src/rp2_common/boot_stage2/boot2_w25x10cl.S:145: Error: garbage following instruction -- `beq 00b'

This should also fix it on Debian sid Experimental, where I'm testing
with GCC 15 and other bleeding edge dependencies.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 11:11:03 +01:00
Leah Rowe 4f77125066 coreboot/fam15h: update submodule for nasm
i forgot to in the last commit, but it didn't matter because
it just meant that coreboot.git's own download logic kicked
in as a fallback. however, it's better to rely on libreboot's
build system for this, since it has redundancy.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 04:38:07 +01:00
Leah Rowe 0f2202554a coreboot/fam15h: update nasm to 2.16.03
this fixed kgpe-d16 build errors on gcc 15 when tested
on debian sid (with gcc-15 installed from experimental)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 04:32:49 +01:00
Leah Rowe 2009c26f0a serprog: Remove pico2 support for the time being
Many users report bugs, so I'm reverting lbmk back to only
supporting the rp2040 dongles for the time being. The
documentation will be updated to reflect this.

Pico2 support will be re-added at a later date, once more
testing has been done, and fixes made if necessary.
2025-04-30 02:35:34 +01:00
Leah Rowe a08b8d94fc seabios: bump to rev 9029a010, 4 March 2025
This brings in the following improvements from upstream:

* 9029a010 kconfig: fix the check-lxdialog.sh to work with gcc 14+
* 8863cbbd ahci: add controller reset
* df9dd418 update pci_pad_mem64 handling
* a4fc1845 add romfile_loadbool()
* a2725e28 drop acpi tables and hex includes
* 35aa9a72 drop obsolete acpi table code
* 1b598a1d usb-hid: Support multiple USB HID devices by storing them in a linked list

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 01:52:56 +01:00
Leah Rowe 342eca6f3d update untitled
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 01:26:34 +01:00
Leah Rowe b0a6d4711a coreboot413: add alper's fix to cbfstool for gcc15
otherwise, it won't compile on gcc 15 (pragma fix from
earlier on, used on the other coreboot trees)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 00:59:39 +01:00
Leah Rowe 628ae867c9 flashprog: bump to rev e060018 (1 March 2025)
This brings in the following upstream changes:

* e060018 flashchips: Explicitly zero-initialize in .qpi_read_params
* ff9526b dediprog: Use dual-i/o default only for SF600Plus-G2
* 5a72cfb flashchips: Fix block-protection bits for 4BA Puya chips
* 284d55b flashchips: Add WPS bit description for GD25Q128C
* 37e07a8 flashchips: Add missing QE bit descriptions
* 3646b18 flashchips: Add GigaDevice GD25LF128E 166MHz, 1.8V part
* d4eb532 flashchips: Add GigaDevice GD25LF80E..GD25LF64E 166MHz, 1.8V parts
* 38d037f flashchips: Add GigaDevice GD25LB512MF..GD55LB02GF 1.8V parts
* 1da0293 flashchips: Add GigaDevice GD25LB512ME..GD55LB02GE 1.8V parts
* 6d728e6 flashchips: Add GigaDevice GD25B512MF..GD55B02GF 3.3V parts
* 493a4e0 flashchips: Update and split GD25Q256D entry
* 648dfdc spi25: Fix cosmetic debug-print error due to unitialized buffer
* cfd607d layout: Show a warning if no region is included
* ec287e2 ich_descriptors_tool: Change region name EC/BMC -> EC_BMC
* 39a4f7d sb600spi: Request more `lspci` details
* 404529d memory_bus.c: Add missing copyright notice
* fbea0fe udev rules: Restore mode/group configuration
* c90d6c4 flashchips: Add some 25LC series EEPROMs
* ee8cf1c Provide no-op probe function, always returning 1
* 4e6155a spi25: Add SPI25_EEPROM enum and handle < 3-byte addresses
* 9512c9c Add missing copyright notices to recently created files
* 06fbccc flashchips: Add GigaDevice GD25LB256E 1.8V part
* bc001da flashchips: Add some GigaDevice GD25L*256 1.8V parts
* 7d0f556 flashchips: Update GigaDevice 1.8V family up to GD25LQ128
* 7f8c12d flashchips: Add GigaDevice GD25LQ20, update family up to GD25LQ16
* 565471c flashchips: Add GigaDevice GD25B512ME..GD55B02GE 3.3V parts
* 6ee2f89 flashchips: Update GigaDevice GD25Q/B/R 128Mbit, 3.3V parts
* c230c69 flashchips: Add remaining Puya PY25Q..H 3.3V parts
* 06e0264 flashchips: Add Puya PY25Q..H family up to PY25Q128H
* fe21b43 flashchips: Add remaining P25Q..H family 3.3V chips
* 1c5d829 flashchips: Add Puya P25Q40SH, P25Q80SH, P25Q16SH 3.3V parts
* b0cae5e flashchips: Add Puya P25Q06H, P25Q11H, P25Q21H 3.3V parts
* b09136b flashchips: Add Puya P25Q05..16H 3.3V parts
* ed8b82c flashchips: Add Fudan FM25Q128 3.3V part
* 4a35134 flashchips: Add Fudan FM25Q08A 3.3V part
* 7f7bffa flashchips: Add Fudan FM25Q64, update FM25Q08..Q32
* c591518 flashchips: Add Fudan FM25Q02/Q04 3.3V parts
* fea6e16 flashchips: Add Winbond W25Q16JV_M (DTR version)
* 56d727e flashchips: Add newer gen. XTX Tech. XT25F..F 3.3V parts
* c64a803 flashchips: Add XTX Tech. XT25F..B 3.3V family
* 46e4209 flashchips: Add XTX Tech. XT25F02E/04D/08B 3.3V parts
* 6bc88e7 flashchips: Add Boya/BoHong BY25Q32/64/128 3.3V variants
* 3cddff4 flashchips: Complete Boya/BoHong BY25D family
* 34e3de6 flashchips: Add Zetta Device ZD25LQ64/128 1.8V parts
* f050370 selfcheck: Check dummy-cycle settings when QPI is advertised
* d40037a selfcheck: Check for WP functions when BP bits are given
* 2a1036b flashchips: Fix up GD25Q128C write-protect support
* d4e41d3 flashchips: Add SST26VF080A
* 04c1cf7 Add .envrc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-30 00:43:45 +01:00
Leah Rowe 5e96db5a2b further gcc-15 fix for gmp on -std=23
the fix in the previous revision wasn't being applied
properly, because the build system of gmp generates
a conftest.c file, and the entry being made for it was
actually coming from this place in the configure file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 23:21:59 +01:00
Leah Rowe 9a9cd26b2d coreboot/default and fam15h: gmp fix, gcc15 hostcc
gcc 15 defaults to -std=c23, but the older gcc was
using -std=c17. The new c23 breaks GMP, so let's add
a patch from upstream (GMP project) to fix it.

this has been done to both coreboot trees.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 22:16:09 +01:00
Leah Rowe 80007223c8 lib.sh: Provide printf for mktarball
Just to let the user know lbmk hasn't died.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 19:51:15 +01:00
Leah Rowe a16c483e5f Merge pull request 'coreboot: fam15h: Add patches to fix build with GCC 15 as host compiler' (#318) from alpernebbi/lbmk:coreboot-fam15h-gcc15 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/318
2025-04-29 17:13:45 +00:00
Alper Nebi Yasak 685685ab0e coreboot: fam15h: Add patches to fix build with GCC 15 as host compiler
Building the fam15h tree results in one of the same nonstring errors
we also had when building the default tree. Copy the relevant patch from
the default tree, while dropping a hunk that we don't need in this old
version.

Another build error is about bool being a reserved keyword now:

  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7140:13: error: 'bool' cannot be used here
   7140 | static void bool(struct compile_state *state, struct triple *def)
        |             ^~~~
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7140:13: note: 'bool' is a keyword with '-std=c23' onwards
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7140:18: error: expected identifier or '(' before 'struct'
   7140 | static void bool(struct compile_state *state, struct triple *def)
        |                  ^~~~~~
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c: In function 'mkcond_expr':
  .../lbmk/src/coreboot/fam15h/util/romcc/romcc.c:7708:19: error: expected ')' before ',' token
   7708 |         bool(state, test);
        |                   ^
        |                   )
  [...]

Fix that by adding a patch that renames the function to bool_().

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 19:54:12 +03:00
Leah Rowe 02110f2bc1 Merge pull request 'coreboot: Add patch to fix build with GCC 15 as host compiler' (#317) from alpernebbi/lbmk:coreboot-gcc15-nonstring into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/317
2025-04-29 16:31:07 +00:00
Alper Nebi Yasak 5ad1de3931 coreboot: Add patch to fix build with GCC 15 as host compiler
Building coreboot host tools with GCC 15 results in build errors:

  In file included from .../lbmk/src/coreboot/default/util/cbfstool/console/console.h:7,
                   from .../lbmk/src/coreboot/default/src/commonlib/fsp_relocate.c:3:
  .../lbmk/src/coreboot/default/src/commonlib/include/commonlib/loglevel.h:170:26: error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (6 chars into 5 available) [-Werror=unterminated-string-initialization]
    170 |         [BIOS_EMERG]   = "EMERG",
        |                          ^~~~~~~
  .../lbmk/src/coreboot/default/src/commonlib/include/commonlib/loglevel.h:171:26: error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (6 chars into 5 available) [-Werror=unterminated-string-initialization]
    171 |         [BIOS_ALERT]   = "ALERT",
        |                          ^~~~~~~
  [...]
  ../cbfstool/common.c: In function 'bintohex':
  ../cbfstool/common.c:195:43: error: initializer-string for array of 'char' truncates NUL terminator but destination lacks 'nonstring' attribute (17 chars into 16 available) [-Werror=unterminated-string-initialization]
    195 |         static const char translate[16] = "0123456789abcdef";
        |                                           ^~~~~~~~~~~~~~~~~~

Add a patch that marks the latter with the "nonstring" attribute, and
disable the warning for the former because I couldn't figure out how to
add that attribute there.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 17:45:46 +03:00
Leah Rowe 9e7bceb7fa Merge pull request 'seabios: Fix malloc_fn function pointer in romfile patch' (#313) from alpernebbi/lbmk:seabios-romfile-malloc-fptr into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/313
2025-04-29 13:55:18 +00:00
Leah Rowe 686e136f15 Merge pull request 'dependencies/debian: Fix libusb package name' (#315) from alpernebbi/lbmk:debian-libusb-dependency into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/315
2025-04-29 13:55:06 +00:00
Alper Nebi Yasak 6f120f0158 dependencies/debian: Fix libusb package name
The Debian package for libusb is "libusb-1.0-0". Fix the typo in the
list which is missing the suffix. While we're here, also fix a line
continuation.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 16:46:24 +03:00
Alper Nebi Yasak 35c853f8b3 seabios: Fix malloc_fn function pointer in romfile patch
One of our SeaBIOS patches causes build errors with GCC 15:

  src/romfile.c: In function 'romfile_loadfile_g':
  src/romfile.c:65:18: error: too many arguments to function 'malloc_fn'; expected 0, have 1
     65 |     char *data = malloc_fn(filesize+add_len);
        |                  ^~~~~~~~~ ~~~~~~~~~~~~~~~~
  src/romfile.c: In function 'romfile_loadfile':
  src/romfile.c:88:50: error: passing argument 3 of 'romfile_loadfile_g' from incompatible pointer type [-Wincompatible-pointer-types]
     88 |     char *data = romfile_loadfile_g(name, psize, &malloc_tmphigh, 1);
        |                                                  ^~~~~~~~~~~~~~~
        |                                                  |
        |                                                  void * (*)(u32) {aka void * (*)(unsigned int)}
  src/romfile.c:55:28: note: expected 'void * (*)(void)' but argument is of type 'void * (*)(u32)' {aka 'void * (*)(unsigned int)'}
     55 |                    void *(*malloc_fn)(), int add_len)
        |                    ~~~~~~~~^~~~~~~~~~~~
  In file included from src/romfile.c:8:
  src/malloc.h:42:21: note: 'malloc_tmphigh' declared here
     42 | static inline void *malloc_tmphigh(u32 size) {
        |                     ^~~~~~~~~~~~~~
  make: *** [Makefile:142: out/src/romfile.o] Error 1
  make: *** Waiting for unfinished jobs....
  src/optionroms.c: In function 'vgarom_setup':
  src/optionroms.c:468:60: error: passing argument 3 of 'romfile_loadfile_g' from incompatible pointer type [-Wincompatible-pointer-types]
    468 |     void *mxm_sis = romfile_loadfile_g("mxm-30-sis", NULL, &malloc_low, 0);
        |                                                            ^~~~~~~~~~~
        |                                                            |
        |                                                            void * (*)(u32) {aka void * (*)(unsigned int)}
  In file included from src/optionroms.c:18:
  src/romfile.h:17:34: note: expected 'void * (*)(void)' but argument is of type 'void * (*)(u32)' {aka 'void * (*)(unsigned int)'}
     17 |                          void *(*malloc_fn)(), int add_len);
        |                          ~~~~~~~~^~~~~~~~~~~~
  In file included from src/optionroms.c:16:
  src/malloc.h:30:21: note: 'malloc_low' declared here
     30 | static inline void *malloc_low(u32 size) {
        |                     ^~~~~~~~~~
  make: *** [Makefile:141: out/src/optionroms.o] Error 1
  make: Leaving directory '/tmp/lbmk/src/seabios/default'

This is because the function pointer defined as `void *(*malloc_fn)()`
refers to a function that takes no arguments, unlike `malloc_tmphigh`
which takes an unsigned int. Add the missing argument type.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 16:37:14 +03:00
Leah Rowe d8b0e74998 init.sh: fix yet another double quote for dotfiles
i missed this one, in another recent revision

double-quote because of the dot, for bash users

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 14:11:56 +01:00
Leah Rowe 780844112a Merge pull request 'Update U-Boot to v2025.10' (#305) from alpernebbi/lbmk:uboot-v2025.04 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/305
2025-04-29 12:50:55 +00:00
Alper Nebi Yasak 1265927ca3 u-boot: gru: Disable INIT_SP_RELATIVE
Recently, gru boards were migrated to use common stack addresses with
U-Boot commit 5e7cd8a11995 ("rockchip: Use common bss and stack
addresses on RK3399") and commit 49f8131e5594 ("rockchip: rk3399-gru:
Use TPL with common bss and stack addresses"). This is done with the
ROCKCHIP_COMMON_STACK_ADDR config.

With POSITION_INDEPENDENT, INIT_SP_RELATIVE defaults to enabled as well.
However, ROCKCHIP_COMMON_STACK_ADDR selects HAS_CUSTOM_SYS_INIT_SP_ADDR,
which depends on INIT_SP_RELATIVE being disabled. So this results in a
configuration warning:

  WARNING: unmet direct dependencies detected for HAS_CUSTOM_SYS_INIT_SP_ADDR
    Depends on [n]: ARM [=y] && ARCH_KIRKWOOD [=n] || ARC [=n] || ARM [=y] && !INIT_SP_RELATIVE [=y] || MIPS [=n] || PPC [=n] || RISCV [=n]
    Selected by [y]:
    - ROCKCHIP_COMMON_STACK_ADDR [=y] && ARM [=y] && ARCH_ROCKCHIP [=y] && SPL_SHARES_INIT_SP_ADDR [=y]

I'm not sure if adhering to the Rockchip values means we can't be
position-independent. Disabling INIT_SP_RELATIVE still appears to keep
my kevin board working, so let's do that for now.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:31:11 +03:00
Alper Nebi Yasak 5bea1fade9 u-boot: arm64: Expand our modified defconfigs to full configs
Run `./mk -l u-boot` to regenerate full configs from our new defconfigs.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:31:01 +03:00
Alper Nebi Yasak fd56d8ada1 u-boot: arm64: Merge our modifications into new defconfigs
Apply our preserved changes to the new U-Boot defconfigs. Upstream
rearranged memory layouts for Rockchip boards to a unified layout, which
got rid of CUSTOM_SYS_INIT_SP_ADDR and HAS_CUSTOM_SYS_INIT_SP_ADDR, and
will need a change to a related INIT_SP_RELATIVE later.

Normalize the positions of each line in the config by regenerating the
defconfig by `./mk -l u-boot` and then `./mk -s u-boot`, so that the
diff looks all green when we actually expand it to the full config.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:28:08 +03:00
Alper Nebi Yasak ed9ddd7415 u-boot: arm64: Add new upstream defconfigs
Copy over the new upstream defconfigs from the refreshed U-Boot trees,
so we can fold our modifications into them. Manually done, but like:

    do_defconfig() {
        ours="$1"
        theirs="$2"
        tree="$3"

        cp src/u-boot/${tree}/configs/${theirs}_defconfig \
           config/u-boot/${ours}/config/default
    }

    do_defconfig  amd64coreboot   coreboot64        x86_64
    do_defconfig  i386coreboot    coreboot          x86
    do_defconfig  gru_bob         chromebook_bob    default
    do_defconfig  gru_kevin       chromebook_kevin  default
    do_defconfig  qemu_arm_12mb   qemu_arm64        default

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:27:32 +03:00
Alper Nebi Yasak b1fa44858c u-boot: arm64: Rebase to v2025.04
Set the U-Boot revision to the commit hash for v2025.04, and rebase the
patches for the default U-Boot tree to accommodate for upstream changes:

 - The SPL/TPL/VPL phases are being unified under the xPL name, so
   there's a config rename.
 - Some test macros were renamed, for the video-related patches.
 - Add some missing hunks for video damage series.
 - Upstream Makefile adds another argument to the binman call.
 - The SWIG related patch is merged upstream, drop it.

I'm not sure if src/u-boot/* directories are regenerated on new builds,
so it may be necessary to remove them manually after applying this.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:26:58 +03:00
Alper Nebi Yasak 976fc6890a u-boot: arm64: Save our modifications to the upstream defconfigs
Run diffconfig from Linux to track our modifications to the old upstream
defconfigs, so we can apply them to the new ones. Restore the original
defconfigs to highlight our changes here, and upstream changes in the
next commit. Done manually, but something like:

  do_diff() {
      ours="$1"
      theirs="$2"
      tree="$3"

      diffconfig \
          src/u-boot/${tree}/configs/${theirs}_defconfig \
          config/u-boot/${ours}/config/default \
          >config/u-boot/${ours}/config/diffconfig

      cp src/u-boot/${tree}/configs/${theirs}_defconfig \
          config/u-boot/${ours}/config/default
  }

  do_diff amd64coreboot    coreboot64        x86_64
  do_diff i386coreboot     coreboot          x86
  do_diff gru_bob          chromebook_bob    default
  do_diff gru_kevin        chromebook_kevin  default
  do_diff qemu_arm64_12mb  qemu_arm64        default

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:26:22 +03:00
Alper Nebi Yasak 418570a617 u-boot: arm64: Turn configs into defconfigs
Run `./mk -s u-boot` to convert our configs into defconfigs, so we can
keep our changes to the old upstream defconfigs and re-apply them to the
new upstream defconfigs.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-29 15:26:12 +03:00
Leah Rowe 093a86d9c0 init.sh: don't use eval to read version files
it's not necessary, and was the cause of a recent issue,
which i mitigated, but why mitigate it?

prevent bugs. don't use eval unless absolutely necessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 12:01:13 +01:00
Leah Rowe 3045079947 init.sh: use backslash for dotfiles in eval
see:

commit f0c629dcc6
Author: Leah Rowe <leah@libreboot.org>
Date:   Sat Apr 12 13:51:49 2025 +0100

    lib.sh: write version/versiondate to dotfiles

and this bug report:

https://codeberg.org/libreboot/lbmk/issues/284

The report indicates that the above commit broke bash,
when sh (on the user's system) is bash.

I know sometimes when using bash, I need to use the
back slash when dealing with dots, e.g. when grepping
something.

Also double quote references to dotfiles, e.g. when
directing the output of printf.

I never noticed the issue myself, since I use dash.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 11:53:32 +01:00
Leah Rowe da108d1c04 mk: Don't run mkhelpers if mode is set
If the mode string is empty, then it's a build command.

See commit:

commit b1ea416575
Author: Leah Rowe <leah@libreboot.org>
Date:   Wed Apr 23 03:54:08 2025 +0100

    mk: remove mkhelp() and use x_() instead

This commit removed the following check:

If mode isn't set, run an mkhelper, otherwise don't.

Because this simplification removed that behaviour,
running e.g. "./mk -m coreboot x200_8mb" would result
in the mkcorebootbin function being executed, which is
normally putting the coreboot rom together.

Since it wasn't built in this case, an error is thrown.
This change therefore restores the previous behaviour,
fixing the bug.

First reported in this error report:
https://codeberg.org/libreboot/lbmk/issues/306

This commit fixes the issue.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-29 11:25:39 +01:00
Leah Rowe 71a58a38ab mk: condense main() again
i prefer it this way. this reverses the change that
i made a few revisions ago

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 23:07:25 +01:00
Leah Rowe f3882b9bf2 init.sh: make git name/email error more useful
instruct the user what to do in these conditions

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 23:02:04 +01:00
Leah Rowe 9cebda333d init.sh: move git name/mail check to xbmk_git_init
the command -v check has been removed, since this function
already calls git immediately, which would accomplish the
same thing since that causes an error if git isn't there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:54:43 +01:00
Leah Rowe ea081adc4c init.sh: tidy up the git name/email check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:51:56 +01:00
Leah Rowe 3292bded69 mk: make main() more readable
now that main is so small, some of the condensed
lines can be loosened up.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:46:30 +01:00
Leah Rowe 97a5e3d15e mk: move git check to init.sh xbmk_set_version
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:44:11 +01:00
Leah Rowe 11cd952060 init.sh: tidy up xbmk_init()
more version-related code moved to xbmk_set_version

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:41:05 +01:00
Leah Rowe f6c5c8d396 mk: move git_init to init.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:35:45 +01:00
Leah Rowe ec1c92238c init.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:23:37 +01:00
Leah Rowe e009f09e7f init.sh: clean up setvars
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:11:52 +01:00
Leah Rowe 9ec7215340 init.sh setvars: make err a printf for eval
setvars is always invoked with eval, so make the error
condition a message for eval, to ensure that it is reliably
handled, in case of error condition.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:07:52 +01:00
Leah Rowe 18ad654a1f init.sh: merge xbmk_child_init with xbmk_init
the for loop at the end of xbmk_init does essentially
the same thing. adapt accordingly, and merge.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 22:02:26 +01:00
Leah Rowe 1526820247 init.sh: split xbmk_child_init into functions
one function, for one task. skeleton functions for
performing multiple tasks. that is the basic coding
style guideline for lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 21:47:28 +01:00
Leah Rowe 0280cd4c0e init.sh: move parent fork to new function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 21:28:13 +01:00
Leah Rowe a0e1d42ff7 init.sh: Provide more complete error info
On initialisation of the child instance, ./mk is
executed, but an error from it won't reveal what
command was actually executed.

This change makes that the case, since x_ does
print the command that caused an error.

This is useful for debugging. However, we don't
want x_ to cause a real exit, because we still
need to handle the lock file from the parent
instance.

Therefore, the first child instance is executed
inside a subshell, and xbmk_rval is set if that
subshell returns non-zero.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 21:18:59 +01:00
Leah Rowe a8f0623efb update uefitool to rev a072527, 26 Apr 2025
This fixes a problem, in that CMake 4.0 dropped compatibility
with CMake version 3.5; UEFIExtract/CMakeLists.txt had the line:

CMAKE_MINIMUM_REQUIRED(VERSION 3.1.0 FATAL_ERROR)

This is lower than 3.5.

The new version has this:

CMAKE_MINIMUM_REQUIRED(VERSION 3.22)

Which is higher than 3.5, in terms of version number.

This brings in the following upstream changes:

* a072527 Convert other uses of 0xABCD back to ABCDh
* a19aead Revert "Update hexadecimal numbers output format from ABCDh to 0xABCD" due to breaking downstream tools
* 7752279 Improve region access settings info for Intel v2 descriptor
* 6f6debb Add volume header info on NumBlocks and Length used to calcualte alternative size of it
* f64ba09 Minor fix for embedded QHexView on Windows
* 2b23bbd Implement Apple developer signing for macOS builds
* 9cc9518 Update hexadecimal numbers output format from ABCDh to 0xABCD
* 73d07cd Add Kaitai-based parser for Dell DVAR store
* c8b7151 Fix minor bug while presenting the EOF elemement of AppleSysF store
* 892111a Add new fields into Intel Microcode header
* 7cea8ee Remove outdated definition of FLASH_PARAMETERS
* c38ed92 Add missing header comments to goto*dialog.h
* 22bb757 Remove PATH_MAX from realpath
* d61d759 Make sure to wrap all uses of kaitai::kstream into try-catch blocks
* 7ef3719 Add initial support for Insyde H2O FlashDeviceMap rev4
* 97a85f9 Add Microsoft LZMA section GUID
* a077743 Bump version numbers
* 07742a5 Update GUID database
* a12be6b Address review comments
* 9719b0c Update copyright and authors in About UEFITool window
* fbf6afd Expand Type column of the report to fit new FlashDeviceMap store and entry types
* 3cb5dc0 Add SLIC pubkey and marker parsers
* fd0faea Add Phoenix CMDB parser
* 01e2e08 Add FFS volume parser for non-AMI NVRAM areas
* 4e2a8f6 Add Intel uCode parser
* 58366f4 Add Insyde Flash Device Map parser
* b98edf6 Add Phoenix EVSA parser
* f989fdf Add Phoenix FlashMap parser
* 4e600eb Add Apple SysF/Diag parser
* 2d6eaa9 Add EDK2 FTW parser
* ca7d4ca Add Insyde FDC parser
* 34904bd Add KaitaiStruct parsing of Phoenix VSS2
* 489b85f Rewrite VSS and VSS2 NVRAM variable parsers in KaitaiStruct
* 2661b8f Remove manual NVRAM parsing, add EDK2 VSS parser written in KaitaiStruct
* d91115f Also sign UEFIFind and UEFIExtract for macOS
* 0fae05c Add adhoc signature to UEFITool on macOS
* 5e6a1c7 Fix CFBundleIdentifier in UEFITool Info.plist
* 8d7e01c Make sure to initialize counterUncData
* b1ad055 Bump version numbers
* 7dd9014 Update GUID database
* 4e3fa58 Update QHexView, build it as a library for Qt6 builds
* 369f101 Enable building ffsparser_fuzzer during CI/CD, improve readUnaligned to silence Clang UBSAN
* ff42cec UEFIExtract: add support for extracting uncompressedData for tree items that have it
* c94f78a Add missing common/LZMA/SDK/C/7zWindows.h
* b5756f9 Revert old patch from common/LZMA/SDK/C/CpuArch.c
* 65fb4a8 Update LZMA SDK to 24.09
* e66bc7d Apply a small patch to common/zlib/gzguts.h to fix a build issue in macOS
* dcf21fa Update built-in zlib to 1.3.1
* 0af36bd Fix an issue with kaitai_regenerate.sh creating backup files on modern macOS
* fd76e89 Update README.md
* 427d8ec Update README.md
* a824260 Add MX77L12850F
* a777f1f Update main.yml
* 5f23377 Update main.yml
* 932120c Use x64 macos-13 runner for FreeBSD in main.yml
* a8c008c Update macos-12 to macos-latest in main.yml
* 6b853f8 Fix SonarCube Scan action version
* 66565a5 Try using new SonarCube scan action
* 371448d Enable long file paths for UEFIFind
* b0cd7fe Update upload-artifacts action to v4
* 4b868bb Remove CodeQL and PVS-Studio from main.yml
* 214b356 Add AMIC A25LQ64 to internal JEDEC ID database
* 0030ea9 Fix findPattern logic when pattern is at the end of the data
* 3441255 fix: add qt version limit to setDesktopFileName
* 941ee6c Set desktop file name to fix the missing icon when running under Wayland
* c550853 Defined ACCESSPERMS for musl
* bf93a5e Bump version numbers
* d03a8f2 Fixing FreeBSD action
* 0a88da1 Update guids.csv
* 6f9a4c0 Fix off-by-one error in parsing IFWI partition table
* e0b1e02 Update main.yml
* 161c697 Update main.yml
* 573452e Update main.yml
* 166c797 add Micron XM25RH128C
* 0e11189 fix a few misspellings
* daf5851 Update README.md
* 1cba371 Update guids.csv
* 4992474 Fix CPD Extension offset (reverts 29915ca)
* 29915ca Fix CPD Manifest's partition offset

The ACCESSPERMS patch has been removed, because upstream
already dealt with this. Libreboot had made the same fix
independently, without realising that upstream also did.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 20:33:12 +01:00
Leah Rowe c698972130 rename include/vendor.sh to inject.sh
this matches cbmk, where inject.sh is the file name

this will make future cherry-picks of lbmk->cbmk easier

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:58:29 +01:00
Leah Rowe 24e488aae5 lib.sh: move _ua to the xbmkget function
don't declare it globally, because it's only used here

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:30:38 +01:00
Leah Rowe 6779d3f991 move variables out of init.sh to others
move them where they are used, or if they are used
in many places, move them to lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:28:49 +01:00
Leah Rowe 848159fa0e lib.sh: rename vendor_checksum
rename it to bad_checksum, so that its use makes more sense

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:21:22 +01:00
Leah Rowe 1de77c6558 lib.sh: move singletree() to git.sh
it is primarily used there, and then in mk,
but only after git.sh is sourced.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:19:36 +01:00
Leah Rowe 703fe44431 lib.sh: move cbfs() to rom.sh
it is only ever used there, so move it there

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:16:40 +01:00
Leah Rowe b57952e90d re-split include/init.sh to lib.sh
move non-init functions to lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:10:01 +01:00
Leah Rowe 8ecb62c662 rename include/lib.sh to init.sh
this is in prep for the next change, where non-init
functions will be moved to another file, again named
include/lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 19:04:03 +01:00
Leah Rowe ce4381169f lib.sh: introduce more top-down function order
a lot of init code was handled outside of any function. the
coding style used in the rest of the build system has now
been introduced, with xbmk_init being the main function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 18:35:41 +01:00
Leah Rowe 15b64cfebe mk/git.sh: remove tree_depend variable
this was used alongside the xgcc linking, so that coreboot
trees could specify that another tree was to be downloaded.

since this variable will no longer be used, it should be
removed, to avoid dead code bloat.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 12:02:55 +01:00
Leah Rowe 9b8179c0e5 git.sh: remove unused xgcc linking feature
the "xtree" variable is used by projects such as u-boot,
to export a CROSS_COMPILE variable specifying prefix for
gnu compilers, and for building the named coreboot tree.
for example, xtree can be "default", which is then the
coreboot tree downloaded, for use of crossgcc.

however, it is also used to symlink identical versions
of crossgcc between coreboot trees. this latter feature
was only needed for fam15h boards which were previously
split between two mostly identical coreboot trees, that
were later merged into a single tree, and this feature
is therefore no longer used.

remove this dead code, to reduce bloat in the build system.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 11:55:51 +01:00
Leah Rowe 4624c6e536 mk: remove unused variables (ser/xp)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 11:44:33 +01:00
Leah Rowe aba5b3a353 mk: simplify main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 11:30:32 +01:00
Leah Rowe 0ab7c6ff9c lib.sh: use realpath to get sys python on venv
In the previous revision, I make hardcoded use of
/usr/local/bin and /usr/bin as search locations, instead
of relying on PATH, when the user has a python venv, because
in those cases, we cannot rely on PATH so we use a python
command to detect the venv and then force use of the
normal system path for python.

However, there's no guarantee that the real Python will
indeed live at these locations. For example, some distros
like Nix or Guix will use many locations for different
versions of a given package, and it's for the birds as to
what given package version the user might be running.

Therefore, this patch retains that current hardcoded
assumption of /usr/local/bin and /usr/bin but *only* as
a fallback solution, instead checking realpath first.

The "realpath" command isn't technically POSIX standard,
but in practise it is available on GNU coreutils, Busybox,
and the various BSD userlands.

I could perhaps *import* a realpath utility, and use that,
but this should be fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 06:43:49 +01:00
Leah Rowe 8edea026c5 lib.sh: Force use of System Python to prevent hang
If the user has a virtual environment, the current logic
will cause lbmk to hang. A useful workaround is to force
use of the direct path to the system binary of python.

This works by detecting a virtual environment first, and
deferring to the old behaviour if no venv is found. If one
is found, then it will not rely on PATH, but instead only
search the standard locations /usr/local/bin and /usr/bin.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-26 05:25:28 +01:00
Leah Rowe b1b964fa5c lib.sh: further condense the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:35:18 +01:00
Leah Rowe 9543a325ac lib.sh: further simplify the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:31:40 +01:00
Leah Rowe 9baabed718 lib.sh: condense the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:27:03 +01:00
Leah Rowe 0c5c5ffc87 lib.sh: simplify mk()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:12:53 +01:00
Leah Rowe 83022b6ba8 lib.sh: simplify cbfs()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:11:20 +01:00
Leah Rowe 13ad839691 lib.sh: simplify the python check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 04:04:03 +01:00
Leah Rowe b1ea416575 mk: remove mkhelp() and use x_() instead
x_ and mkhelp pretty much do the same thing

in fact, there is no functional difference

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 03:54:08 +01:00
Leah Rowe 4cf64e59ed mk: simplify handling of trees()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-23 03:49:22 +01:00
Leah Rowe d0581914c7 coreboot/hp8300cmt: purge xhci_overcurrent_mapping
This prevents a build error, as the variable is no longer
used at all by coreboot (EHCI mapping is used as reference
instead).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 10:25:08 +01:00
Leah Rowe cb52fc4ba8 Fix VBT path on HP Elite desktops
Also: hp8300cmt_16mb did not specify a data.vbt path, even
though it is indeed available in the coreboot tree. This
has been corrected.

The previous lack of VBT on hp8300cmt_16mb wasn't really a
big problem, since coreboot handles initialisation anyway,
and it's basically optional on Linux. Coreboot doesn't parse
VBT at all.

This patch should fix build errors, that were caused on the
recent revision update, where several of the HP desktops
have now been turned into variants.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 07:51:49 +01:00
Leah Rowe 2bee87cfc2 lib.sh: add missing copyright year
alper made a fix to this file a few hours ago, but
forgot to update the copyright header

i'm doing it for alper, as a courtesy

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 04:01:31 +01:00
Leah Rowe 4b7ab403c6 ifd/q45t_am: unlock regions by default
i used ifdtool --unlock to do this

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 03:25:51 +01:00
Leah Rowe 564155277e coreboot/g43t_am3: use ifd-based setup
no-ME setup. with a gbe file. we previously made this
a descriptorless setup.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 03:24:38 +01:00
Leah Rowe 0ddd196375 coreboot/q45t_am3: use ifd-based setup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 02:44:33 +01:00
Leah Rowe 3b2d933842 coreboot/default: add missing submodules
due to a rule in .gitignore, these were ignored, because it
ignores .tar.xz entries in git status

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 01:59:05 +01:00
Leah Rowe a10d81399c NEW MAINBOARD: Acer Q45T-AM (G43T-AM3 variant)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 00:16:08 +01:00
Leah Rowe d114e0a765 mk: don't print confirmation of git pkg.cfg
otherwise, the "list" commands include such text,
where they should not.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 00:09:27 +01:00
Leah Rowe f59c24f12a coreboot/g43t_am3: fix data.vbt path
this board became a variant, in the new coreboot revision that
lbmk recently updated to. fix the data.vbt path to prevent error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-22 00:06:29 +01:00
Leah Rowe 21020fa319 add missing config/data/coreboot/0
this is a file containing one byte, of value zero

i meant to add it in previous commits, for the resizing
and shrinking of tarballs when inserting or deleting
vendor files

used by include/vendor.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-21 21:24:53 +01:00
Leah Rowe 2b4629d790 Merge pull request 'lib.sh: Fix python3 detection when 'python' is python2' (#290) from alpernebbi/lbmk:python3-detection-fix into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/290
2025-04-21 14:52:28 +00:00
Alper Nebi Yasak a18d287a81 lib.sh: Fix python3 detection when 'python' is python2
Properly set $pyver to "3" when we detect we can use python3. In the
following version checks, use the $python we detected instead of a
'python' from PATH because the latter might be a python2 while still
co-existing with a python3.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2025-04-21 17:45:25 +03:00
Leah Rowe c7569a6714 coreboot/next: merge with coreboot/default
I also cherry-picked a patch from Heads, that fixes build
issues caused by the hacks in the T480 port; several changes
made by Mate are now ifdef'd based on whether a KabyLake
ThinkPad is specified in defconfig.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-21 06:38:30 +01:00
Leah Rowe 762c7ff43e coreboot/default: Update, c247f62749b (8 Feb 2025)
This is currently the latest revision of coreboot.

Other coreboot trees to follow. The "next" tree will
also be merged with coreboot/default, in a follow-up
commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-21 03:26:54 +01:00
Leah Rowe 86e7aa80c5 Update the GRUB revisions
A number of regressions were caused by the recent CVE fixes,
many of which have since been fixed upstream. This includes
several ext4 file system bugs, which caused some systems not
to boot properly, when dealing with very large initramfs files.

No additional patching has been made. This will be tested, and
then used to provide a revision update for Libreboot 20241206.

After this, there are several additional OOT patches that will
be merged, for the next *testing release* of Libreboot.

Update to this revision, for all GRUB trees:
a4da71dafeea519b034beb159dfe80c486c2107c

This brings in the following changes from upstream:
* a4da71daf util/grub-install: Include raid5rec module for RAID 4 as well
* 223fcf808 loader/ia64/efi/linux: Reset grub_errno on failure to allocate
* 6504a8d4b lib/datetime: Specify license in emu module
* 8fef533cf configure: Add -mno-relax on riscv*
* 1fe094855 docs: Document the long options of tpm2_key_protect_init
* 6252eb97c INSTALL: Document the packages needed for TPM2 key protector tests
* 9d4b382aa docs: Update NV index mode of TPM2 key protector
* 2043b6899 tests/tpm2_key_protector_test: Add more NV index mode tests
* 9f66a4719 tests/tpm2_key_protector_test: Reset "ret" on fail
* b7d89e667 tests/tpm2_key_protector_test: Simplify the NV index mode test
* 5934bf51c util/grub-protect: Support NV index mode
* cd9cb944d tpm2_key_protector: Support NV index handles
* fa69deac5 tpm2_key_protector: Unseal key from a buffer
* 75c480885 tss2: Add TPM 2.0 NV index commands
* 041164d00 tss2: Fix the missing authCommand
* 46c9f3a8d tpm2_key_protector: Add tpm2_dump_pcr command
* 617dab9e4 tpm2_key_protector: Dump PCRs on policy fail
* 204a6ddfb loader/i386/linux: Update linux_kernel_params to match upstream
* 6b64f297e loader/xnu: Fix memory leak
* f94d257e8 fs/btrfs: Fix memory leaks
* 81146fb62 loader/i386/linux: Fix resource leak
* 1d0059447 lib/reloacator: Fix memory leaks
* f3f1fcecd disk/ldm: Fix memory leaks
* aae2ea619 fs/ntfs: Fix NULL pointer dereference and possible infinite loop
* 3b25e494d net/drivers/ieee1275/ofnet: Add missing grub_malloc()
* fee6081ec kern/ieee1275/init: Increase MIN_RMA size for CAS negotiation on PowerPC machines
* b66c6f918 fs/zfs: Fix a number of memory leaks in ZFS code
* 1d59f39b5 tests/util/grub-shell: Remove the work directory on successful run and debug is not on
* e0116f3bd tests/grub_cmd_cryptomount: Remove temporary directories if successful and debug is not on
* e6e2b73db tests/grub_cmd_cryptomount: Default TMPDIR to /tmp
* 32b02bb92 tests/grub_cmd_cryptomount: Cleanup the cryptsetup script unless debug is enabled
* c188ca5d5 tests: Cleanup generated files on expected failure in grub_cmd_cryptomount
* 50320c093 tests/util/grub-shell-luks-tester: Add missing line to create RET variable in cleanup
* bb6d3199b tests/util/grub-shell-luks-tester: Find cryptodisk by UUID
* 3fd163e45 tests/util/grub-shell: Default qemuopts to envvar $GRUB_QEMU_OPTS
* ff7f55307 disk/lvm: Add informational messages in error cases of ignored features
* a16b4304a disk/lvm: Add support for cachevol LV
* 9a37d6114 disk/lvm: Add support for integrity LV
* 6c14b87d6 lvm: Match all LVM segments before validation
* d34b9120e disk/lvm: Remove unused cache_pool
* 90848a1f7 disk/lvm: Make cache_lv more generic as ignored_feature_lv
* 488ac8bda commands/ls: Add directory header for dir args
* 096bf59e4 commands/ls: Print full paths for file args
* 90288fc48 commands/ls: Output path for single file arguments given with path
* 6337d84af commands/ls: Show modification time for file paths
* cbfb031b1 commands/ls: Merge print_files_long() and print_files() into print_file()
* 112d2069c commands/ls: Return proper GRUB_ERR_* for functions returning type grub_err_t
* da9740cd5 commands/acpi: Use options enum to index command options
* 1acf11fe4 docs: Capture additional commands restricted by lockdown
* 6a168afd3 docs: Document restricted filesystems in lockdown
* be0ae9583 loader/i386/bsd: Fix type passed for the kernel
* ee27f07a6 kern/partition: Unbreak support for nested partitions
* cb639acea lib/tss2/tss2_structs.h: Fix clang build - remove duplicate typedef
* 696e35b7f include/grub/mm.h: Remove duplicate inclusion of grub/err.h
* 187338f1a script/execute: Don't let trailing blank lines determine the return code
* ff173a1c0 gitignore: Ignore generated files from libtasn
* fbcc38891 util/grub.d/30_os-prober.in: Conditionally show or hide chain and efi menu entries
* 56ccc5ed5 util/grub.d/30_os-prober.in: Fix GRUB_OS_PROBER_SKIP_LIST for non-EFI
* 01f064064 docs: Do not reference non-existent --dumb option
* 3f440b5a5 docs: Replace @lbracechar{} and @rbracechar{} with @{ and @}
* f20988738 fs/xfs: Fix grub_xfs_iterate_dir() return value in case of failure
* 1ed2628b5 fs/xfs: Add new superblock features added in Linux 6.12/6.13
* 348cd416a fs/ext2: Rework out-of-bounds read for inline and external extents
* c730eddd2 disk/ahci: Remove conditional operator for endtime
* f0a08324d term/ns8250-spcr: Return if redirection is disabled
* 7161e2437 commands/file: Fix NULL dereference in the knetbsd tests
* 11b9c2dd0 gdb_helper: Typo hueristic
* 224aefd05 kern/efi/mm: Reset grub_mm_add_region_fn after ExitBootServices() call
* 531750f7b i386/tsc: The GRUB menu gets stuck due to unserialized rdtsc
* f2a1f66e7 kern/i386/tsc_pmtimer: The GRUB menu gets stuck due to failed calibration
* 13f005ed8 loader/i386/linux: Fix cleanup if kernel doesn't support 64-bit addressing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-20 05:43:53 +01:00
Leah Rowe 8d57bf6009 Revert "git.sh: minor cleanup"
This reverts commit e63d8dd20d.
2025-04-18 02:25:16 +01:00
Leah Rowe a2898771f6 lib.sh: perform root check even earlier
initialising variables, setting PWD, setting version,
this is all unnecessary before the root check, because
the dependencies commands use none of these.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 02:17:53 +01:00
Leah Rowe 779f600342 lib.sh: tidy up opening logic (put it together)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 02:10:49 +01:00
Leah Rowe bac4be99c2 lib.sh: do root check before python check
we don't need python before the root check

principle of least privilege

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 02:02:10 +01:00
Leah Rowe e63d8dd20d git.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 01:52:44 +01:00
Leah Rowe 11078508a2 lib.sh: simplify mktarball()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 01:33:45 +01:00
Leah Rowe 087bbedc5f vendor.sh: tidy up vendor_download()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:35:48 +01:00
Leah Rowe e11fd52d95 mk: tidy up check_gnu_path()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:27:33 +01:00
Leah Rowe 3442f4278e mk: simplify check_project_hashes()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:23:32 +01:00
Leah Rowe 6b6a0fa607 lib.sh: fix missing s/TMPDIR/xbmktmp
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-18 00:17:11 +01:00
Leah Rowe e07a2adb13 lbmk: don't handle TMPDIR directly
lbmk creates TMPDIR as /tmp/xbmk_*, but it's theoretically
possible that something could re-export it by mistake.

this change retains the same initialisation, but further
use is now via a new variable "xbmktmp", that stores the
value of TMPDIR upon lbmk's initialisation of it.

this reduces the chance of such a bug in the future, as
described above, so it is a preemptive/preventative fix.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 23:43:22 +01:00
Leah Rowe 9d3b52cd1d rom.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 23:31:26 +01:00
Leah Rowe b4402c5425 vendor.sh: yet even more code cleanup
code equals bugs. code that doesn't exist can't
have bugs, so it is superior by definition.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 23:04:14 +01:00
Leah Rowe fe5bdc7633 vendor.sh: even more cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 22:09:05 +01:00
Leah Rowe fcedb17a9a vendor.sh: more cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:38:20 +01:00
Leah Rowe 4e2b59ed3f vendor.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:20:14 +01:00
Leah Rowe a3acf4c3f9 vendor.sh: simplify process_release_roms
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:11:55 +01:00
Leah Rowe 30213a9688 vendor.sh: remove unnecessary check
the next part checks whether the file is below 512k,
so there's no point checking if it's below 2, because
the lowest a file size can be is zero, and expr will
produce a result of -1 if decrementing from zero.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 18:04:51 +01:00
Leah Rowe 38df7275f1 git.sh: remove unnecessary comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 17:14:11 +01:00
Leah Rowe f5891fb699 git.sh: remove link_crossgcc()
merge it with git_prep

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 17:10:19 +01:00
Leah Rowe a685654b90 git.sh: remove move_repo()
merge it with git_prep, since it's only a small
function and only called from there. the merged
code still makes sense and its purpose is still
quite clear on casual reading.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 16:54:59 +01:00
Leah Rowe e4aa62f79a git.sh: remove prep_submodule()
merge it with git_prep, since it's only a tiny
function and only called from there. the for
loop moved to the if block still makes sense
on casual reading.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 16:45:00 +01:00
Leah Rowe 2839feb9e4 git.sh: make git_prep command clearer
the "u" argument can actually be any thing. git_prep
handles git submodules only for single-tree projects,
under any candition, or on multi-tree projects if
the number of arguments to git_prep is above four.

"u" is the 5th argument, meant to enable submodule
downloads. it really doesn't matter what this string
says, so let's just make it as clear as possible.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 16:32:21 +01:00
Leah Rowe 410fa702c9 mrc.sh: Make proper use of variable inside printf
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 05:06:21 +01:00
Leah Rowe 075902c3ea simplify a few file checks
the combination of x_ with the "e" function enables
for much simpler file-check error handling, which is
a unique innovation of lbmk as it pertains to sh.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 04:49:17 +01:00
Leah Rowe b2255425eb rom.sh: remove unnecessary check
the cbfs function will call cbfstool, which will perform
the same check, and the same error condition would cause
the same exit behaviour in lbmk. the error message would
also provide output that is just as useful for debugging.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 04:22:25 +01:00
Leah Rowe 39640d76a7 lbmk: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-17 04:22:03 +01:00
Leah Rowe c8dc701f3e lib.sh mktarball: stricter tar error handling
There was no error handling, *at all*, on the actual tar
command, due to the lack of set -o pipefail, which we cannot
rely on in sh.

The x_ wrapper can be used in this case, as a mitigation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-16 00:57:54 +01:00
Leah Rowe 58a53d7046 vendor.sh: don't err on bruteforce me extract
it wouldn't exit with error status anyway, since i'm
setting +e here, but if that accidentally changed in
the future, i still wouldn't want this to exit.

the bruteforce me extraction naturally throws a lot of
errors, hence +e, because of how the extraction works,
but the result is checked at the end of the process,
to compensate. hence +e, because otherwise this brute
force extraction would never work.

therefore, this is an extremely theoretical bug fix, the
most quintessential of preemptive bug fixes, to the point
that it is actually rather pedantic.

The ":" in "|| :" will likely *never* be executed, but it
handles the theoretical case where the subshell exits with
non-zero status and +e is set; subshells aren't meant to
behave this way anyway, but who knows what cursed sh
implementation the user is on?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 17:58:59 +01:00
Leah Rowe 958fa34832 mk check_project_hashes: handle error on sha512sum
We can't do set -o pipefail in POSIX sh, which we're using,
but the build system has x_ which wraps around a command
and executes it, exiting with non-zero status if it does.

This fact enables lbmk to have functionality that is actually
superior to pipefail, since you can more easily control
specifically which parts error.

For example:

foo | bar | foo2 | bar2 | $err "error"

ERROR exits with non-zero status, but foo2, bar and foo
would not exit on error, only bar2 would. In *bash*, which
we avoid, set -o pipefail would make all of them exit on
error, but what if you wanted "bar" to not exit?

With lbmk, you could do, in the above example, and with the
above question asked ("what if you wanted bar not to exit"):

x_ foo | bar | x_ foo2 | bar2 > file | $err "error"

of course, you could also do, if not outputting to "file":

x_ foo | bar | x_ foo2 | x_ bar2

NOTE: in lbmk, $err is a variable containing the name of
a function that does something (whatever you want) and
then exits with non-zero status.

This entire explanation is beyond the scope of simply
providing (and explaining) this fix, but I also wanted to
use this commit as an example of the power of lbmk with
regards to POSIX shell scripting.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 17:08:25 +01:00
Leah Rowe 8b4b069e3f vendor.sh: remove unnecessary xchanged="y"
in these if clauses, what follows afterward is exactly
the same: set xchanged and return.

Therefore, these lines are redundant and they can be
removed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 15:53:36 +01:00
Leah Rowe 166dbb04c9 vendor.sh: set need_files="n" if skipping patch
This change finally ensures that no insertions will be
attempted, on the basis that readkconfig failed; this
covers the instance whereby vcfg was set, but no scanned
items were indicated e.g. Intel ME files not specified.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 15:49:10 +01:00
Leah Rowe e90657cc73 vendor.sh: Don't handle vendor files if not needed
This should speed up automated tests. Otherwise, it goes
through all the extra checks that aren't needed, for each
individual type of vendor file, and also errors out when
handling pico serprog images; during automated testing,
on the bin directory, you might try on every tarball, one
of which is the pico tarball and this patch makes lbmk skip
that one too.

In general, we must not perform unnecessary tasks. Doing so
may even cause other bugs that we couldn't easily detect.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 14:09:31 +01:00
Leah Rowe 2e10a45fa3 Revert "lib.sh: use eval for the command in x_"
This reverts commit 3bfdecdc75.

The commit that this reverses, caused sch5545 ec firmware
downloads to fail, due to globbing.
2025-04-13 05:15:13 +01:00
Leah Rowe 738d4bb6b6 lib.sh: fix bad eval writing resized file
x_ cannot be used, where output is redirectod to a file;
only the conventional piping can be used.

same as the last change. this and the other fix were caught
during testing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 04:02:34 +01:00
Leah Rowe eb9e5d2d5d lib.sh: fix bad eval writing version/versiondate
x_ cannot be used, where output is redirected to a file;
only the convention piping can be used, for errors.

relying on x_ in these cases will cause unpredictable bugs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 03:57:04 +01:00
Leah Rowe 3bfdecdc75 lib.sh: use eval for the command in x_
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 02:31:25 +01:00
Leah Rowe 4fa3bb9e5b mk: use eval to run mkhelp commands
directly quoting it and running it quoted means
that the shell way try to execute it as a file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-13 02:25:01 +01:00
Leah Rowe 9b3635718a mk: tidy up the switch/case block in main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:43:28 +01:00
Leah Rowe 0c381028ab mk: tidier error handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 023f9cf049 lib.sh: tidy up the error handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe cb3253befb rom.sh: tidy up error handling
same as the last change

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 7af46721bc vendor.sh: tidy up error handling
x_ can be used nowadays on any function, because it
properly handles globbing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 04ebb3b91a vendor.sh: tidy up decat_fspfd()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 0c87fdf96a git.sh: clean up fetch_project()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 9eb8856b3c mk: Remove unnecessary argument checks on trees()
These checks are no longer necessary, because these
checks are already properly handled in main().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 22:32:51 +01:00
Leah Rowe 52f3d54116 vendor.sh: properly call err_ in fail_inject
i can't call $err (variable), because it's set
to fail_inject. fix this infinite loop, which
was an oversight in the previous commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 20:19:48 +01:00
Leah Rowe c4c6692b76 remove xbmk_parent, handle forking in lib.sh
I was using a complicated method of knowing whether
the current instance was parent or a child, to know
whether the lock file and TMPDIR needed to be purged.

It was quite error-prone too. Instead, I'm now handling
it directly from within the if statement that previously
initialised xbmk_parent=y, forking ./mk from there.

The forked instance would not trigger that if clause
again, since then TMPDIR is created, thus avoiding
recursion.

This is an improvement because it doesn't rely on how
the parent handles exit statuses, and it ensures that
the lock/tmp files are never accidentally deleted.

Even if a given program/script that lbmk runs would
export TMPDIR, it doesn't matter because lbmk doesn't,
so it would be unaffected.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 20:03:40 +01:00
Leah Rowe fd5431db05 lib.sh: define x_ right after err_
because the top-down function order isn't as reliable
in lib.sh, since this is what first runs, included
in every other script

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:40:51 +01:00
Leah Rowe 972681a127 mk: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:38:14 +01:00
Leah Rowe b41cd39b68 lib.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:35:30 +01:00
Leah Rowe 4993950264 mrc.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:32:18 +01:00
Leah Rowe c158d82298 rom.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:29:35 +01:00
Leah Rowe cb36248c8c vendor.sh: tidy up check_release()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:10:49 +01:00
Leah Rowe 409cab39c5 vendor.sh: tidy up vendor_inject()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:08:30 +01:00
Leah Rowe 12b1623e47 vendor.sh: tidy up readcfg()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:05:12 +01:00
Leah Rowe 0d85f061e2 vendor.sh: tidy up patch_release_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 17:02:07 +01:00
Leah Rowe 61f2014102 vendor.sh: tidy up process_release_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:57:29 +01:00
Leah Rowe 5901f36e49 vendor.sh: tidy up patch_rom()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:53:34 +01:00
Leah Rowe 082930ce0e vendor.sh: tidy up inject()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:50:54 +01:00
Leah Rowe e1f91f3037 vendor.sh: tidy up modify_mac_addresses()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 16:43:59 +01:00
Leah Rowe 3181ac5012 script/trees: merge with mk and delete script/
script/ no longer exists. this means that the
only executable script in lbmk is now mk.

script/trees was never called directly; instead,
we used ./update trees in the past, then just ./mk.

this is part of a larger audit to simplify lbmk,
in preparation for the next Libreboot release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 14:46:09 +01:00
Leah Rowe 3d03dd1a50 mk: remove the legacy "roms" command
we don't need it. the documentation only tells you
now to run ./mk -b coreboot target1 target2 etc

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 14:24:10 +01:00
Leah Rowe f0c629dcc6 lib.sh: write version/versiondate to dotfiles
write to .version and .versiondate, instead
of version and versiondate.

this will hide them to avoid visual clutter while
analysing files within lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:51:49 +01:00
Leah Rowe 23b942c83e lib.sh: hardcode projectname/projectsite
remove the corresponding files, containing these strings

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:44:05 +01:00
Leah Rowe a03bb793ae remove update/vendor symlinks
these are obsolete commands for backward compatibility,
but they are being removed before the next release.

the documentation has for some now only referenced use
of the ./mk commands, making lbmk live up to its name!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:37:21 +01:00
Leah Rowe d7f80ebe71 move build to mk
i'm removing all the backward-compatibility in the
build system, so that only the ./mk command is available

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:32:34 +01:00
Leah Rowe 57d58527fd trees: unify the execution of mkhelper commands
provide it in a new function: mkhelp()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:20:16 +01:00
Leah Rowe e5262da4be trees: tidy up configure_project()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 13:07:27 +01:00
Leah Rowe 5179827839 build: make coreboot building an else in "roms"
Otherwise, the current return prevents set -u -e
after the case/switch block, which is a problem if
set +u +e was done at any point before the return.

Remove the return in the roms) section of the case/switch
block, and make the building of coreboot images part of
an else clause.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 12:58:28 +01:00
Leah Rowe c189257888 trees: don't build dependencies if dry=":"
build_depend is already blanked anyway, but it can't
hurt to have an extra check here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:28:14 +01:00
Leah Rowe 115a66fddd trees: unified handling of flags
this way, the error message will never be incorrect,
which i had to fix in a recent patch.

now, the same string is used for error messages and getopt.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:18:15 +01:00
Leah Rowe 3ea633cc79 trees: simplified handling of badhash/do_make
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:15:53 +01:00
Leah Rowe 9be40e94a2 trees: don't set mode on ./mk -b
mode is already initialised as an empty string

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:15:53 +01:00
Leah Rowe 67ad7c2635 trees: don't set mod on ./mk -d
mode is already initialised as an empty string

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 02:15:53 +01:00
Leah Rowe 2444894841 trees: don't initialise mode to "all"
this is not necessary. the fetch mode is still handled,
as before, and no make commands will run in this case.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 01:45:36 +01:00
Leah Rowe 97c50a39a6 trees: clean up some comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 01:45:10 +01:00
Leah Rowe cfb14fd8dd vendor.sh: simplified readkconfig()
So much bloat

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-12 01:13:05 +01:00
Leah Rowe 5b697b93a2 lib.sh: double-quote pwd to prevent globbing
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 20:11:51 +01:00
Leah Rowe 5a0a24f555 lbmk: unified PWD handling (work directory)
instead of running pwd all the time, run it once in lib.sh,
and export PWD.

for lbmk-specific use of PWD, use xbmkpwd, which contains
the value of PWD as was set by the pwd utility in lib.sh.

many parts of lbmk rely on pwd, and it *must* be correct.
this change adds basic error handling, since pwd can in
fact return errors in some cases.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 20:04:53 +01:00
Leah Rowe a25a29cfbb lib.sh: initialise PATH if it's unset
it's incorrect for PATH not to be set, but some users
may foolishly blank it out before running lbmk.

prevent such issues, by initialising it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 19:31:26 +01:00
Leah Rowe 1022abf699 move XBMKPATH to include/lib.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 19:22:23 +01:00
Leah Rowe 0764c969a2 lbmk: use pwd util, not PWD environmental variable
PWD could be anything, if the user manually exported
it before running lbmk.

always run pwd instead, to get the real string.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 17:52:18 +01:00
Leah Rowe f98b9b0110 clean up a few semicolons in the build system
several code lines were condensed together, which
make them less readable. make the code more readable
by having separate commands on separate lines.

i previously did this during my manic build system
audits of 2023 and 2024; condensing lines like this
is overly pedantic and serves no real purpose.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 17:15:00 +01:00
Leah Rowe 8ccb61cc71 trees: err if first argument is not a flag
E.g. ./mk -f coreboot is valid

./mk coreboot -f is not valid

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:24:51 +01:00
Leah Rowe 947c3e1a17 trees: err if no argument given
We were already covering this from the main build
script, but it's good to also check it here.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:24:19 +01:00
Leah Rowe edbbde0b12 trees: set dry=":" on ./mk -f
We don't want any build commands to run, when
the -f flag is used.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:11:24 +01:00
Leah Rowe 33bb0ecf76 trees: clean up initialisation of the dry variable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 14:10:42 +01:00
Leah Rowe c7636ff1df trees: initialise mode to "all", not ""
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 13:39:55 +01:00
Leah Rowe d0bd12631a trees: don't abuse the mode variable on -f
The "mode" variable is used as a suffix for make commands,
for example ./mk -m sets mode to "menuconfig", which means
you want to run "make menuconfig".

When fetching sources (./mk -f), I was setting mode to "fetch",
and putting checks in code to avoid use of make when mode was
set to "fetch".

The behaviour now is identical, except that a new variable
called "do_make" is set to "n" when doing ./mk -f, otherwise
set to "y", and this is checked instead. This should make
the meaning of the code somewhat clearer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-11 04:47:04 +01:00
Leah Rowe c4cd876c60 trees: Add missing flag to error output
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-09 09:38:59 +01:00
Leah Rowe 5ebcae5235 lbmk: minor code formatting cleanup
some lines were needlessly condensed, and less readable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-06 23:17:33 +01:00
Leah Rowe 70cef71dba grub/xhci: Remove unused patch
I was importing a patch for the z790 boards, but
Libreboot doesn't support this board yet, and the
patch was a hack that may affect other boards.

When I do later merge that board, and I find that the
hack is needed, I'll simply make another grub tree
within lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-04 13:57:09 +01:00
Leah Rowe 3f14a470a2 remove _fsp targets (keep _vfsp)
_fsp is obsolete. people should use _vfsp

_fsp was kept for a short while, for backward compatibility,
but nobody really uses it now and it just causes confusion

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-04-01 08:45:41 +01:00
Leah Rowe d7312260e7 util/nvmutil: remove excessive comments
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-25 13:29:16 +00:00
Leah Rowe e348ea0381 Bump GRUB revision to add 73 security patches
You can find information about these patches here:
https://lists.gnu.org/archive/html/grub-devel/2025-02/msg00024.html

GRUB has been on a crusade as of late, to proactively audit
and fix many security vulnerabilities. This lbmk change brings
in a comprehensive series of patches that fix bugs ranging from
possible buffer overflows, use-after frees, null derefs and so on.

These changes are critical, so a revision release *will* be issued,
for the Libreboot 20241206 release series.

This change imports the following 73 patches which
are present on the upstream GRUB repository (commit IDs
matched to upstream):

* 4dc616657 loader/i386/bsd: Use safe math to avoid underflow
* 490a6ab71 loader/i386/linux: Cast left shift to grub_uint32_t
* a8d6b0633 kern/misc: Add sanity check after grub_strtoul() call
* 8e6e87e79 kern/partition: Add sanity check after grub_strtoul() call
* 5b36a5210 normal/menu: Use safe math to avoid an integer overflow
* 9907d9c27 bus/usb/ehci: Define GRUB_EHCI_TOGGLE as grub_uint32_t
* f8795cde2 misc: Ensure consistent overflow error messages
* 66733f7c7 osdep/unix/getroot: Fix potential underflow
* d13b6e8eb script/execute: Fix potential underflow and NULL dereference
* e3c578a56 fs/sfs: Check if allocated memory is NULL
* 1c06ec900 net: Check if returned pointer for allocated memory is NULL
* dee2c14fd net: Prevent overflows when allocating memory for arrays
* 4beeff8a3 net: Use safe math macros to prevent overflows
* dd6a4c8d1 fs/zfs: Add missing NULL check after grub_strdup() call
* 13065f69d fs/zfs: Check if returned pointer for allocated memory is NULL
* 7f38e32c7 fs/zfs: Prevent overflows when allocating memory for arrays
* 88e491a0f fs/zfs: Use safe math macros to prevent overflows
* cde9f7f33 fs: Prevent overflows when assigning returned values from read_number()
* 84bc0a9a6 fs: Prevent overflows when allocating memory for arrays
* 6608163b0 fs: Use safe math macros to prevent overflows
* fbaddcca5 disk/ieee1275/ofdisk: Call grub_ieee1275_close() when grub_malloc() fails
* 33bd6b5ac disk: Check if returned pointer for allocated memory is NULL
* d8151f983 disk: Prevent overflows when allocating memory for arrays
* c407724da disk: Use safe math macros to prevent overflows
* c4bc55da2 fs: Disable many filesystems under lockdown
* 26db66050 fs/bfs: Disable under lockdown
* 5f31164ae commands/hexdump: Disable memory reading in lockdown mode
* 340e4d058 commands/memrw: Disable memory reading in lockdown mode
* 34824806a commands/minicmd: Block the dump command in lockdown mode
* c68b7d236 commands/test: Stack overflow due to unlimited recursion depth
* dad8f5029 commands/read: Fix an integer overflow when supplying more than 2^31 characters
* b970a5ed9 gettext: Integer overflow leads to heap OOB write
* 09bd6eb58 gettext: Integer overflow leads to heap OOB write or read
* 7580addfc gettext: Remove variables hooks on module unload
* 9c1619773 normal: Remove variables hooks on module unload
* 2123c5bca commands/pgp: Unregister the "check_signatures" hooks on module unload
* 0bf56bce4 commands/ls: Fix NULL dereference
* 05be856a8 commands/extcmd: Missing check for failed allocation
* 98ad84328 kern/dl: Check for the SHF_INFO_LINK flag in grub_dl_relocate_symbols()
* d72208423 kern/dl: Use correct segment in grub_dl_set_mem_attrs()
* 500e5fdd8 kern/dl: Fix for an integer overflow in grub_dl_ref()
* 2c34af908 video/readers/jpeg: Do not permit duplicate SOF0 markers in JPEG
* 0707accab net/tftp: Fix stack buffer overflow in tftp_open()
* 5eef88152 net: Fix OOB write in grub_net_search_config_file()
* aa8b4d7fa net: Remove variables hooks when interface is unregisted
* a1dd8e59d net: Unregister net_default_ip and net_default_mac variables hooks on unload
* d8a937cca script/execute: Limit the recursion depth
* 8a7103fdd kern/partition: Limit recursion in part_iterate()
* 18212f064 kern/disk: Limit recursion depth
* 67f70f70a disk/loopback: Reference tracking for the loopback
* 13febd78d disk/cryptodisk: Require authentication after TPM unlock for CLI access
* 16f196874 kern/file: Implement filesystem reference counting
* a79106872 kern/file: Ensure file->data is set
* d1d6b7ea5 fs/xfs: Ensuring failing to mount sets a grub_errno
* 6ccc77b59 fs/xfs: Fix out-of-bounds read
* 067b6d225 fs/ntfs: Implement attribute verification
* 048777bc2 fs/ntfs: Use a helper function to access attributes
* 237a71184 fs/ntfs: Track the end of the MFT attribute buffer
* aff263187 fs/ntfs: Fix out-of-bounds read
* 7e2f750f0 fs/ext2: Fix out-of-bounds read for inline extents
* edd995a26 fs/jfs: Inconsistent signed/unsigned types usage in return values
* bd999310f fs/jfs: Use full 40 bits offset and address for a data extent
* ab09fd053 fs/jfs: Fix OOB read caused by invalid dir slot index
* 66175696f fs/jfs: Fix OOB read in jfs_getent()
* 1443833a9 fs/iso9660: Fix invalid free
* 965db5970 fs/iso9660: Set a grub_errno if mount fails
* f7c070a2e fs/hfsplus: Set a grub_errno if mount fails
* 563436258 fs/f2fs: Set a grub_errno if mount fails
* 0087bc690 fs/tar: Integer overflow leads to heap OOB write
* 2c8ac08c9 fs/tar: Initialize name in grub_cpio_find_file()
* 417547c10 fs/hfs: Fix stack OOB write with grub_strcpy()
* c1a291b01 fs/ufs: Fix a heap OOB write
* ea703528a misc: Implement grub_strlcpy()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-19 21:26:23 +00:00
Leah Rowe 4b228c11f9 Merge pull request 'Update pico-serprog revision' (#271) from Riku_V/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/271
2025-02-12 21:20:17 +00:00
Riku Viitanen a8359e30b2 Update pico-serprog revision
Most importantly this should fix issues with rp2350 boards
not synchronizing properly.

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2025-02-12 22:19:11 +02:00
Leah Rowe d2cb954933 util/nvmutil: Fix bad error messages on R/W
The messages didn't really make sense.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-10 20:27:48 +00:00
Leah Rowe e1e515bd22 util/nvmutil: hardened pledge on help output
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-02-07 12:31:46 +00:00
Leah Rowe ada057a865 Merge pull request 'Simplify the README' (#269) from runxiyu/lbmk:readme-simplification into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/269
2025-02-02 10:32:39 +00:00
runxiyu 9ced146b47 README.md: Use newlines instead of bulleted list for docs/support links
I think newlines look better here. The indent that bullet-pointed lists
have, does not seem natural at the start of the document.

Signed-off-by: runxiyu <me@runxiyu.org>
2025-02-02 07:56:24 +00:00
Runxi Yu 266122592c README.md: Use the EFF's page on Right to Repair 2025-02-02 15:19:26 +08:00
Runxi Yu e36aa8c5a5 README.md: Vastly simplify it 2025-02-01 00:18:31 +08:00
Runxi Yu c17f4381ce README.md: Mention SeaBIOS and U-Boot instead of Tianocore as payloads
SeaBIOS has been supported for a long time and seems to be the
"recommended" payload nowadays (though usually with GRUB too). I haven't
seen Tianocore / EDK II been mentioned in a while. U-Boot support was
added as of Libreboot 20241206-rev8.

Signed-off-by: Runxi Yu <me@runxiyu.org>
2025-02-01 00:08:44 +08:00
Leah Rowe 47eb049cb4 Merge pull request 'deps/arch: genisoimage belongs to cdrtools' (#267) from runxiyu/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/267
2025-01-31 08:45:01 +00:00
Runxi Yu fa9a0df245 deps/arch: genisoimage belongs to cdrtools
genisoimage is not a an AUR package as suggested by aur_notice. It is
available in the "cdrtools" package in the repositories.

References: https://archlinux.org/packages/extra/x86_64/cdrtools/
Signed-off-by: Runxi Yu <me@runxiyu.org>
2025-01-31 16:38:20 +08:00
Leah Rowe a98490573b util/nvmutil: only set mac_updated at the end
after setting the checksum too

this is functionally no different, but setting it
at the start didn't sit right with me.

it's more logically correct to set it at the end,
in case any error did not result in an exit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:45:57 +00:00
Leah Rowe 6b9cf09ca2 restore old x230 gbe file
i accidentally committed one where i'd changed
the mac address, on a previous revision to nvmutil

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:17:07 +00:00
Leah Rowe 8a43535513 util/nvmutil: Fix bad comparison
We're checking if errno is ENOTDIR, not setting it;
the previous code would always return true, and then
set errno 0, which in the context of this code was
actually OK, so this patch makes no functional difference
in practise.

However, I'm a stickler for technical correctness. I caught
this when trying to compile with clang, because clang is
quite pedantic about checking for exactly this type of bug.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:10:52 +00:00
Leah Rowe a65a0c2f96 util/nvmutil: allow ./nvm gbe MAC
previously, if the user ran:

./nvm GBE [MAC address]

it would error, treating the MAC as a command

now if only 3 arguments are provided, and the
3rd argument ins't a valid command, it's treated
as a MAC address and validated accordingly.

this should make nvmutil easier to use, because
I imagine a lot of users forget to use setmac

there's no reason we should be so pedantic. we
should allow it to be used flexibly like this

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 04:07:54 +00:00
Leah Rowe 96356ce94f util/nvmutil: move "e" to swap()
we only use it there, so we should only define it
there. it's used to detect host CPU endianness.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 03:47:20 +00:00
Leah Rowe b1d8975959 util/nvmutil: Only read up to 4KB on larger gbe
On the 16KB and 128KB files, we still only need to
operate on 4KB at the start of each block, where the
block size is larger than 4KB.

The reason we deal with the entire 4KB block is because
the nvm words (in the 128 byte section) can define an
extended nvm area anywhere after 128 bytes, within the
128 byte block.

We could systematically read where that is being handled,
and handle it; we could then allocate less memory, and
read/write fewer bytes, but many block devices like SSDs
and flash drives have at least a 4KB erase block anyway,
so it's kinda pointless. saving memory would be nice, but
I don't really want to bloat the code.

This is a nice easy optimisation, to avoid wasting an
additional 8KB of memory when handling 16KB files, and
additional 120KB if handling 128KB files, since nf is
what determines how much memory will be allocated.

the alternative would be to use an mmap, and then we
could reasonably handle the idea above for only writing,
surgically, what we need: nvm words and extended nvm
words.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-29 03:41:55 +00:00
Leah Rowe 6821659bcb util/nvmutil: fix minor mistake (line break)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 18:46:36 +00:00
Leah Rowe 3bb7520f6d util/nvmutil: do setmac if only filename given
./nvm gbe.bin

with this patch, the above example does the same as:

./nvm gbe.bin setmac

now you can simply specify the gbe file, and it will
randomise the mac address within it, and update the
nvm checksum word.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 18:40:44 +00:00
Leah Rowe d94b274fd9 vendor.sh: don't error if grep -v fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 06:57:30 +00:00
Leah Rowe 6ebdd3c72b vendor.sh: Don't show gbe filename on inject
it's a temporary file, so printing it may confuse
the user. hide it from the output.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 06:49:45 +00:00
Leah Rowe a08748a9ed util/nvmutil: don't say write not needed if errno
otherwise, the output is confusing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:54:06 +00:00
Leah Rowe 6841a351eb util/nvmutil: print dump *after* modification
this way, we still get an error exit for example
when trying to invalidate an already invalid
checksum; this error exit was disabled by the
last revisions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:50:34 +00:00
Leah Rowe da0a6c216c util/nvmutil: verbosely print the written MAC
This is for user friendliness. Otherwise, many users
might try to dump afterward if they specified a random
MAC address.

This saves the user from having to re-run with the dump
command, thus saving time for the user.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:37:02 +00:00
Leah Rowe db5879c6b5 util/nvmutil: minor cleanup in cmd_dump
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:29:14 +00:00
Leah Rowe bd7215d1eb util/nvmutil: show nvm words written on writeGbe
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:26:59 +00:00
Leah Rowe c70117c79c util/nvmutil: clean up readonly check on writeGbe
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:18:38 +00:00
Leah Rowe cf5a63e65c util/nvmutil: Remove useless gbeFileChanged var
We don't need it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:13:20 +00:00
Leah Rowe 83601aa524 util/nvmutil: reset errno if any MAC updated
instead of setting errno in the for loop, set a variable
declaring that the mac was updated, and reset errno based
on that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:08:17 +00:00
Leah Rowe 3e86bf5ce2 util/nvmutil: reset errno when writing a MAC
if checksum verification passed, then we should reset
in case we're operating on a given part and the last
one checked was bad.

a catch-all reset is already performed in writeGbe,
but it's good to do it here too.

in practise, if the 2nd part (part 1) is what failed,
errno still wouldn't be reset.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:05:59 +00:00
Leah Rowe bcf53cc2cc util/nvmutil: show total number of bytes read
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 05:02:54 +00:00
Leah Rowe c91cc329cf util/nvmutil: rename tbw/bw to tnw/nw
to match nr in the readGbe function

number of bytes written, and total number
of bytes written.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:59:17 +00:00
Leah Rowe 9060710833 util/nvmutil: err if bytes read lower than nf
same as the last change. just covering edge cases.

we will likely never trigger this error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:57:32 +00:00
Leah Rowe c72f699d36 util/nvmutil: err if fewer bytes written
it will probably never happen, and this is technically
not an error condition of pread/pwrite, but we need it
to read and write that exact number of bytes, as per nf

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:55:05 +00:00
Leah Rowe d666f67ebe util/nvmutil: Show bytes written in writeGbe
This will be useful for future debugging, and future
work on optimisations.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:47:49 +00:00
Leah Rowe b2d6393ed5 util/nvmutil swap(): ensure that no overflow occurs
it wouldn't occur, on the current logic, but i wasn't
comfortable having the starting point (on little endian)
being higher than the checked endpoint, in case of
possible integer overflow as a result of future
modifications.

this is therefore a pre-emptive bug fix, because it doesn't
yet fix a bug, but it prevents a bug from being introduced.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:09:48 +00:00
Leah Rowe 063fef14d3 util/nvmutil: make swap() a bit clearer
don't sizecode. show the individual steps clearly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:09:09 +00:00
Leah Rowe fd1bbdc96c util/nvmutil: make 0x3f checksum position a define
for code clarity

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:06:12 +00:00
Leah Rowe 5ddf7f251d util/nvmutil: make 128 (nvm area) a define
for code clarity

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 04:03:34 +00:00
Leah Rowe 8850acc7da util/nvmutil swap(): Only handle the nvm area
The 128-byte nvm area is all that we need to handle,
since that is the only thing we actually work on in
nvmutil, based on checksum verification; the latter
implies that bytes must be in the correct order.

The swap() function previously worked on the entire
block, e.g. 4KB on 8KB files, 8KB on 16KB files and
64KB on 128KB files, and it did this twice, so it would
have operated on anywhere between 8KB to 128KB of data.

It now only operates on 256 bytes at a maximum, or 128
bytes if only handling one block. This is a significant
performance optimisation, on big endian host CPUs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-27 03:56:13 +00:00
Leah Rowe 49506a8832 util/nvmutil: move write checks to writeGbe
doing it in main() is messy. better do it from the
actual function. now the logic in main is clearer.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 08:52:26 +00:00
Leah Rowe 948377b0e7 util/nvmutil: make cmd_swap its own function again
previous audits sizecoded nvmutil.c, reducing the sloccount,
but this resulted in unreadable code.

move the swap logic (swap parts) back to its own function,
for clarity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 08:48:51 +00:00
Leah Rowe 6e134c9f4b util/nvmutil: minor cleanup
SIZE_64KB no longer needed, and the malloc error
is needlessly verbose

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 08:03:27 +00:00
Leah Rowe 98e105ac4f util/nvmutil: allocate less memory for setchecksum
also cmd_brick

where the checksum is being corrected or bricked, we
only need to handle the 128-byte nvm area on one of
the parts

similarly, we only need to allocate half the gbe file
size when doing a copy command.

256 bytes still allocated for setmac (see previous
commit), because we verify both checksums and set both
parts if possible.

with this, nvmutil is now much more memory-efficient.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 07:25:26 +00:00
Leah Rowe 52e8ea57f7 util/nvmutil: Further reduce memory usage
Allocate memory based on nf instead of partsize.

nf is the number of bytes actually read from each
part of the file.

Now if the user is running setmac for example,
256 bytes of memory will be allocated regardless
of gbe file size, whereas it would have previously
allocated 8KB, 16KB or 128KB depending on the file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 07:05:06 +00:00
Leah Rowe 7a7d356824 util/nvmutil: Remove unnecessary buf16 variable
We can just point to gbe[] directly, in the word macro.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 06:26:53 +00:00
Leah Rowe cdf23975bc util/nvmutil: Only allocate needed memory for file
We were allocating 128KB even if we only needed 8KB, for
example. It's not a lot of memory, but the principle of
the matter is that we must respect the user by not wasting
their memory.

The design of nvmutil is that it will never overflow, because
operations are mapped in memory to the exact size of the gbe
file, which can be 8KB, 16KB or 128KB, and this is enforced.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-26 06:09:04 +00:00
Leah Rowe ed45da9cae util/nvmutil: Remove unnecessary buffer
The buf variable is only used once, and only so
that we can get a pointer. We can point to buf16
instead, for the same result.

The gbe pointer (size_t) is later converter to
a char * when writing back to the file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-25 06:23:22 +00:00
Leah Rowe ec3148dc3b util/nvmutil: Show specific error for bad cmd argc
For example, if the brick command is used without specifying
a part number. Instead of saying "Invalid argument", show a
much more useful error message to help the user adapt.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 18:14:25 +00:00
Leah Rowe 073420d305 util/nvmutil: cleaner argument handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 18:10:17 +00:00
Leah Rowe a6c18734e7 util/nvmutil: extreme pledge/unveil hardening
call pledge *much* earlier, and and lock everything down
much sooner. the point of pledge/unveil is precisely that
your program must operate under the most restrictive set
of conditions possible, and still function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 17:58:42 +00:00
Leah Rowe deb307eaf6 util/nvmutil: more minor cleanup
just some line breaks

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 17:03:31 +00:00
Leah Rowe c14eccaf15 util/nvmutil: more granular MAC parsing errors
tell the user exactly what they got wrong, instead
of simply printing "bad mac address", which is not
very helpful to the user

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 16:58:51 +00:00
Leah Rowe 88fb9cc90e util/nvmutil: more cleanup
spread out a few lines, so that they are more
readable, and more thoroughly comment some parts.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 16:45:08 +00:00
Leah Rowe 5aaf27f80c remove errant comment in nvmutil
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 13:34:07 +00:00
Leah Rowe c829b45c17 util/nvmutil: support 16kb and 128kb gbe files
See:
https://edc.intel.com/content/www/us/en/design/ipla/software-development-platforms/client/platforms/alder-lake-mobile-p/intel-600-series-chipset-family-on-package-platform-controller-hub-pch-datash/spi0-for-flash/

The rules described there are universal, and replicated elsewhere
for many other platforms. The rules are simply:

* Flash descriptor is one block size, e.g. 4KB
* GbE is two block sizes, so if IfD is 4KB, GbE is 8KB

Intel defines 16KB and 128KB GbE files in specs, pertaining to
8KB and 64KB block sizes respectively.

The minimum size is 4KB blocksize, for 8KB GbE files which
we already supported. On larger block sizes, the same 4KB
parts are observed: a single 4KB IfD area at the start of
the block, and:

4KB GbE part at the start of the GbE region, and:
4KB GbE part at the start of GbE region plus block size

The empty space inbetween is padding, and we ignore it,
except when running swap/copy commands.

The nvmutil code has been modified, to create a 128KB buffer in
memory instead of 8KB, for loading GbE files.

Partsize is set to GbE file size divided by 2, and only the
area of memory we need to use is mapped; for example, if
we're loading a 8KB GbE file into memory, we only touch
the first 8KB part of the buffer, or first 16KB for 128KB
files.

In practise, we almost never see GbE files with sizes higher
than 8KB, but *we have seen it*, *AND NOW IT'S SUPPORTED!"

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 13:13:28 +00:00
Leah Rowe a98ca5bf65 util/nvmutil: Prevent unveil allowing dir access
We were checking directories *after* calling unveil, which
means that the sandboxing was incomplete; we only want files
to be accessed, not directories.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 12:18:45 +00:00
Leah Rowe 68c32034a0 typo: nvme should say nvm in nvmutil.c
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 11:37:26 +00:00
Leah Rowe c944c2bbac util/nvmutil: General code cleanup
A lot of size-coding was performed in prior audits, to
make the sloccount lower on nvmutil, but this resulted in
code that wasn't very human readable.

I've reversed some of it and added comments, for clarity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-24 11:33:30 +00:00
Leah Rowe 8c65e64e39 snip
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-18 05:06:34 +00:00
Leah Rowe f666652fe1 snip
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-18 01:43:02 +00:00
Leah Rowe 64d3c7b515 grub/xhci: Add xHCI non-root-hub fixes from Nitrokey
See:
https://github.com/Nitrokey/nethsm-grub/commits/nethsm-z790?since=2025-01-13&until=2025-01-13

And more generally, see branch:
https://github.com/Nitrokey/nethsm-grub/commits/nethsm-z790

This brings in a few minor fixes, and also a not-so-minor fix:
Add TT (transaction translation) handling for non-SuperSpeed
devices in xhci.c

More generally, this patchset will improve non-root hub support
in the xHCI code. There is also a patch to work around a quirk
on the MSI Z790-P mainboard, which I'm planning to add to Libreboot
at a later date.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-14 20:34:16 +00:00
Leah Rowe 7bf0d4c2ed add gnults-devel to fedora 41 dependencies
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-12 23:59:44 +00:00
Leah Rowe 66d084e7f7 grub.cfg: scan luks *inside lvm*
the user might have boot their kernel inside luks
inside lvm for some dumb reason

it's theoretically possible that the user would be
so silly indeed

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-12 13:45:00 +00:00
Leah Rowe 5a3b0dab96 grub.cfg: Scan *every* LVM device
We were scanning a hardcoded set up LVM volumes, so in practise,
LVM boot didn't really work. We did this because scanning for
asterisk is slow on some machines. However, since LVM is the last
one, and since most users don't boot directly from LVM, it wasn't
that much of an issue in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-12 13:19:48 +00:00
Leah Rowe 3c9f4be76f Libreboot 20241206, 8th revision
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 22:47:14 +00:00
Leah Rowe d4cc94d6b4 rom.sh: don't run mkpicotool on dry builds
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 18:15:22 +00:00
Leah Rowe de6d2f556f pico-sdk: Import picotool as a dependency
We were previously not handling picotool at all, and
pico-sdk would download picotool itself, at build time.

This means that the source archive, if created, would
not contain picotool. While not strictly required, for
complete corresponding source, since it's a toolchain
and not the actual pico-serprog firmware, it is my policy
that releases must include full corresponding source code,
when it is feasible to do so.

I must say, I intensely dislike cmake, with such burning
passion; I am thoroughly displeased by how hacky this is,
but it works and now nothing is in my way for a Libreboot
20241206 rev8 release!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 17:26:51 +00:00
Leah Rowe 4210ee68ea lib.sh: Much safer python version check
See:
https://docs.python.org/3/library/sys.html#sys.version_info

The sys.version_info tuple is a more reliable way to
get the version. Our previous logic assumed that Python
would always output "Python versionnumber", but this may
not always be how it works. We've seen this for example
where Debian modifies some GNU toolchains to include Debian
something in the output.

Python has a standard method built in for outputting exact
the information we need. In my system, what I got was this:

(3, 11, 2, 'final', 0)

That output was from running this command:

python -c 'import sys; print(sys.version_info[:])'

This is much more robust, so use this instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 03:54:38 +00:00
Leah Rowe 8c7ba6131c coreboot/next uprev: Fix T480 backlight keys
Backlight controls already worked on the T480/T480s, if you
used software-based controls e.g. set a hotkey for
xbacklight, but the actual Fn buttons on the keyboard did
not function at all; this patch fixes that issue

This also fixes LEDs on T480, on warm reboot, which are
otherwise off. It sets them back to the state they were
at on cold boot.

Both fixes are from Mate Kukri in the new T480 patchset.
In addition to these fixes, Mate made several code quality
improvements as part of efforts to upstream this code into
coreboot's main branch.

Updated coreboot T480 patchset to patchset 25. This change
will be reflected next in a modification to the Libreboot
documentation.

I had to make several other fixes on top of this; see diff.
A debug option was being enabled relating to stack overflow
detection, which we ought to avoid to mitigate over-zealous
build errors and stack corruption at boot; an errant option
for an EC we don't use was also being enabled, by some code
in coreboot relating to a Dasharo board; both issues have
been mitigated in this lbmk patch, by patching the upstream
coreboot build system in this patch.

As part of this change, the coreboot/next tree within lbmk
has been updated. Existing patches have been rebased.

This brings in the following changes from upstream, relative
to the previous revision used on coreboot/next:

* 2f1e4e5e85 mb/hp/snb_ivb_desktops/z220*: Remove leftover old usb configurations
* 9e859154ea mb/hp/snb_ivb_desktops: Remove unused includes
* 70b33cb38d ec/google/chromeec/acpi: Add support for generic LPC memory range
* f2ad73b5d1 mb/google/rauru: Raise little core CPU frequency from 700MHz to 2.4GHz
* 044017b4cd mb/google/rauru: Initialize PMICs in romstage
* 397c3e3c52 mb/google/fatcat/var/fatcat: Add touchpad wake source
* e18f0f53cb mb/google/fatcat/var/fatcat: Change touchpad interrupt to edge trigger
* a8b4ee246d mb/google/nissa/var/rull: Configure Acoustic noise mitigation
* c09fd09edf tree: Use "true", "false" for has_power_resource
* 1e64875265 mb/google/fatcat: Remove unused <stdio.h>
* f316ab6796 mb/google/fatcat/var/francka: Fix early pad configuration for TPM
* 6ca2c3c415 soc/mediatek/mt8196: Fix indentation in Makefile.mk
* 94c1307fdb soc/mediatek/mt8196: Add dynamic power-saving for peripheral clocks
* 67b140a949 tree: Use "true", "false" for fine_grained_control
* 97923aebe1 mb/prodrive/atlas: Add initial support for options
* 1a16146795 Fix up CFR's open issues
* 7e8d8cdea2 mb/google/rauru: Initialize SPM
* 3153432b83 soc/intel/alderlake: Add function to force disable memory channels
* 8ea2b0ab46 mb/google/fatcat/var/francka: Use RAM ID 2 for MT62F2G32D4DS-020 WT:F
* 5f600a8ee9 mb/google/fatcat: Limit Power Limit when battery is missing
* 5213646241 ec/google/chromeec: Add function to detect barrel charger
* 5ef70e5f22 ec/google/chromeec: Add API to check if battery is critically low
* 42fd35b486 ec/google/chromeec: Add API to check if charger is present
* 56370d0283 ec/google/chromeec: Add API to check if a USB PD charger is attached
* 001e7a0b45 soc/mediatek/mt8196: Add MT6685 Clock IC driver
* 5852841ca7 soc/intel/meteorlake: Use ASPM helpers from Alder Lake
* b04f057efd mb/google/rex/var/kanix: Add Synaptics touchpad
* af0c2e7a2e mb/prodrive/atlas: Remove the workaround for CLKREQ pins
* 13316c644b mb/google/fatcat/var/fatcat: Modify interrupt GPIO for LPSS I2C touchpad
* 825e9173b4 soc/mediatek: Distinguish pmic_init_setting function name
* d65ff8492c soc/intel/xeon_sp/spr/acpi: Fix regression
* 291778a1bd mb/google/corsola: Add new board variant Wyrdeer
* 745dcc861d mb/google/corsola: Refactor mipi_panel_power_on function
* 79f60c6b22 mb/google/nissa/var/telith: Disable stylus function
* d7934bdd53 Doc/soc/amd/family15h: Fix URLs to AMD documents
* 3cb7db4075 soc/mediatek/mt8196: Add PMIC MT6316 driver
* 60bce10750 drivers/mipi: Add support for KD_KD110N11_51IE panel
* d4c80054a4 soc/mediatek/mt8189: Enable timer compensation v2.5
* 403846f177 soc/mediatek/mt8196: Define MFGPLL_*_BASE using MFGSYS_BASE
* b3edaa7b10 mb/google/rauru: Implement SKU ID
* b470b48718 mb/google/rauru: Add support for getting storage id
* 24a5048948 mb/google/nissa/var/pujjo: Add new supported memory part
* c6e27c5fbf mb/google/nissa/var/rull: Add G2 touchscreen to devicetree
* 639def1d84 mb/google/fatcat/var/fatcat: Enable FPS
* acb8c870b2 mb/google/fatcat: Suppress unnecessary extra space in device trees
* d79ba5565d mb/google/nissa/var/telith: Modify PLD for typeC and typeA
* 620d2fab06 soc/mediatek/mt8189: Replace SPDX identifiers to GPL-2.0-only OR MIT
* d90b1322ab commonlib: Refactor CSE sync eventLog
* 4ef6c13b38 mb/google/brya: Adjust EC memory map range to support indexed IO
* 1e90bbadfa ec/google/chromeec: Add indexed IO support
* a8ab708584 mb/google/nissa/var/quandiso2: Create a quandiso2 variant
* 78f610a0ae util/docker/doc.coreboot.org: Allow git to work in envs owned by root
* 38ee22f6da util/docker/doc.coreboot.org: Use Alpine minor instead of point releases
* 0196c3b6a4 util/docker/doc.coreboot.org: Get rid of bash workarounds
* 897b46693b util/docker/doc.coreboot.org: Don't create volumes
* a0c45cbf1f 3rdparty/fsp: Update submodule to upstream master
* aa562d2881 soc/mediatek/mt8189: Add GPIO driver
* 40a863cd60 soc/mediatek/mt8189: Initialize watchdog
* 1380ed0cd2 soc/mediatek: Add support for MediaTek firmware support package
* 4f92943c89 soc/mediatek/common: Rename GPT_MHZ to TIMER_MHZ for readability
* 5a73692e0c soc/mediatek/mt8196: Add SPM loader
* 306660c2de util/crossgcc: Update CMake from 3.30.2 to 3.31.3
* f3adc74e44 mb/google/fatcat: Keep GSPIx interface default PCI
* 809e704101 soc/intel/pantherlake: Rename GSPI2 to GSPI0A
* 222ef676f9 soc/intel/pantherlake: Add ACPI name for GSPI2
* 1fda7027c0 util/crossgcc: Update ACPICA from 20230628 to 20241212
* e35175bb38 Update vboot submodule to upstream main
* 9eb4c5aff8 util/ifdtool: Fix memory leaks
* 87ae3573b5 mb/starlabs/starlite_adl: Configure GPIO interrupt for Virtual Button
* eaf87422b1 ec/starlabs/merlin: Add Intel Virtual Button Driver for Tablet Mode
* a1532790b9 docs: Add 24.12 release notes
* 8c0df740c7 mb/google/nissa/var/gothrax: Add probe and GPIO config for HDMI and  touchpanel
* f6fcff5511 docs/security/vboot: Update supported boards
* 0dba17da0c mb/google/brya/uldrenite: Add WWAN RW350R-GL power on sequence
* 2c4af7cd29 mb/topton/adl: Enable TPM2 (Intel fTPM/PTT)
* c11558d4c7 mb/asus/p8z77-m: Drop GPIO by I/O
* 4f1a1adef6 mb/topton/adl: Disable mapped SATA port
* 81cbe11361 mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM
* 9578c67c77 mb/google/brox: Include CSE reset in mainboard reset expectation
* 5af5e66686 util/cbfstool: eliminate late sign of life event
* 0797c40d52 src/soc/intel/cmn/blk/cse: Log cse sync information
* 9a15a1ed21 soc/intel: Log CSE Sync Early Sign of Life event from a better place
* c812c78618 mb/trulo/var/uldrenite: Support USB_OC on the A0 port
* ee1a766f05 mb/trulo/var/uldrenite: Set GPP_B5 and B6 to ISH function
* 87c9d93a62 mb/google/skywalker: Add MediaTek MT8189 reference board
* 6bd51ce42a soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC
* ea646c0514 mb/google/rauru: Add pwrsel init in romstage
* c3265da005 soc/mediatek/mt8196: Add pwrsel driver
* 30d8e1880a ec/google/chromeec: Publish LPC GMR address range via CREC _CRS
* bb85775d92 soc/intel/cmn/acpi: Add ACPI method to get LGMR address
* 84347d0b45 payloads/Linuxboot: Fix u-root build
* 7bcec7a2ef payloads/LinuxBoot: Build x86_64 with host toolchain
* e3150e819d util/crossgcc: Add libstdcxx target
* 61385c4976 soc/mediatek/common: Move SPM_SYSTEM_BASE_OFFSET to soc folders
* 6625dee027 soc/mediatek/common: Use array to represent spm_sw_rsv registers
* cd8d6861f6 soc/mediatek/common: Move some functions to spm_v1.c
* 91fe658714 drivers/option: Add forms in cbtables
* 4d4776f320 mb/emulation/qemu-sbsa: Configure flash region for MMU
* dfef1895f2 mainboard: Add MiTAC Computing Whitestone-2 (LGA-4677)
* caf8f9f60f mb/google/brya/var/uldrenite: Enable PMC, HECI and SRAM devices
* b668c756bf mb/trulo/var/uldrenite: Configure audio (max9360a, rt5682)
* 941f994809 mb/trulo/var/uldrenite: Configure Network
* 600e7810fb mb/trulo/var/uldrenite: Configure USB ports and mapping
* 0261cbe8e9 mb/trulo/var/uldrenite: Configure serial_io and I2C
* 113205bcd1 mb/trulo/var/uldrenite: Enable eMMC and DLL tuning parameters
* 0dd227f9c1 mb/trulo/var/uldrenite: Enable DPTF, S0ix and configure FIVR setting
* 0ce153c8df mb/google/nissa/var/rull: For probe, change unprovisioned to unknown
* b57308f437 mb/google/rauru: Add SD card configurations
* e969a3df87 soc/mediatek/mt8196: Add SD card configurations
* 8be835ce3c soc/mediatek/mt8196: Add tracker driver
* 78560f9958 soc/mediatek/mt8196: Add MMinfra driver support
* 0b252ef8b4 util/mtkheader: Add GFH header for mt8189 bootblock code
* 540eb5ba73 cpu/qemu: Enable IDT_IN_EVERY_STAGE
* f9d6fd4e0f soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE
* c3dee9eaba cpu/intel/car/romstage: Fix false-positive stack corruption
* b659fb5cea mb/ocp/tiogapass: Wait for BMC
* 7c0556244d drivers/wifi: Update Drive Strength BRI Rsp Table revision
* 70bdd2e1fa cpu/x86/topology: Simplify CPU topology initialization
* 3a2ffba231 soc/intel/xeon_sp: Introduce early_pch_init
* 48ed4b0f85 soc/intel/xeon_sp/lbg: Add support to hide HDA
* a857c81122 arch/x86: Disable DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
* 45dabe846d mb/google/brox: Apply ISH_FW_VERSION in Kconfig
* e0b1a0dbec vc/intel/fsp/mtl: Update MTL fsp header files from 3471_91 to 4122_21
* c20fd2fc3f 3rdparty/fsp: Update submodule to upstream master
* e5b5fc345a soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
* 673075f102 util/cbfstool: Add eventLog support for ELOG_TYPE_FW_CSE_SYNC
* 3235b7c6d5 commonlib: Add ELOG_TYPE_FW_CSE_SYNC eventLog type
* 4a0c49e671 soc/intel/pantherlake: Keep image clock configuration enable
* 51cc2bacb6 soc/intel/pantherlake: Disable stack overflow debug options
* eeb6f67eec Docs: Convert bare URLs into hyperlinks
* 2609519704 mb/google/rauru: Implement regulator interface
* 8c6426c1b4 soc/mediatek/mt8196: Add PMIC MT6373 driver
* bda5b83661 mb/google/brya/var/uldrenite: update gpio settings
* afb11d05b9 mb/google/trulo/var/uldrenite: Add memory config
* 46df9e1d38 mb/google/brya/var/marasov: Enable GPP_F9 GPIO for early panel power-on
* 04d33b90ec mb/google/fatcat: config GPP_F23 as ISH gpio pin
* 16ab83b34a soc/mediatek/mt8196: Initialize SSPM
* b793209b80 mb/google/brox/var/jubilant: Disable Tccold Handshake
* 2f1e67bbc7 mb/google/nissa/var/glassway: Modify touch screen ILIT2901 sequence
* a1c50f233d soc/mediatek/mt8196: Add PMIC MT6363 ADC driver
* 8910b6ba7d soc/mediatek/mt8196: Add PMIC MT6363 driver
* c215889442 soc/mediatek/mt8196: Add PMIF and PMIC driver support
* 27fa0595de soc/mediatek/mt8196: Add mtcmos init support
* 61a00269a2 mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1]
* 38b59164ca ec/google/chromeec: Define ACPI_NOTIFY_CROS_EC_MKBP constant
* 50c9747d87 drivers/usb/intel_bluetooth: Add GBTR Method
* 0bb4a220a8 soc/intel/common/cnvi: Fix GBTE path in comment
* d33244c3af drivers/usb/intel_bluetooth: Relocate BTRK to \_SB.PCI0
* 04b9627e07 drivers/usb/intel_bluetooth: Fix GBTE to return Local0
* c3f9dd3af3 drivers/usb/intel_bluetooth: Change the Power Resource to S0
* 1cf8d84f3b mb/google/nissa/var/rull: Add 6W and 15W DPTF parameters
* 62a9d670bf mb/google/brya/var/uldrenite: Add HDA verb tables
* 56278eeed8 mb/google/rex/var/kanix: Enable/Disable PCIE WLAN based on fw_config
* 6d3346068b intel/common/block: Program the right power_limits_config entry
* 35bf4bc59c commonlib: Add generic word-at-a-time optimization to ipchksum()
* e987ba45d6 soc/mediatek/mt8196: Add booker driver
* aa3cfd5c69 haswell NRI: Post-process selected timings
* 4a4ad2b1e6 haswell NRI: Initialise MPLL
* 41c2e1685e soc/intel/xeon_sp: Add PCU PCI drivers
* 8721757aca soc/intel/xeon_sp/skx: Configure IOAPICs
* e9c546b153 arch/x86: Rename breakpoint removal function
* 0351872731 arch/x86: Add breakpoint to stack canary
* 572da7c524 acpi/acpigen: generate Create*Field() from name string directly
* 2e9aebf63f mb/google/fatcat: Enable Intel DPTF support and configure policies
* a8ff286185 mb/google/fatcat: Enable Bayhub Level 2 errata
* 230e646d98 mb/google/fatcat: Remove redundant GPIOs for x1 slot
* fbacae625a soc/intel/ptl: Enable UFS functionality by adding IRQ programming
* b67e001a85 soc/intel/pantherlake: Fix UFS ACPI _ADR calculation
* 2496943b5c mb/google/brox/var/jubilant: Set PCIe root port 5 speed to Gen2
* dfdb210e26 soc/intel/common/block: Fixup itss_get_on_chip_dev_pirq
* 223dabef56 soc/intel/common/block: Add const qualifier for input of pirq ops
* afc49fa013 soc/intel/xeon_sp: Remove lpc_lockdown_config
* 1a4ab38035 soc/mediatek/mt8196: Rename SCP to SPM base variables
* 3189afbdee soc/intel/common: Drop locking function fast_spi_set_vcl
* 01bf34cb28 soc/intel/xeon_sp: Support _PRT reporting for domain
* 1399dd8086 soc/intel/xeon_sp: Skip not pre-routed devices in _PRT reporting
* a5362f6d73 soc/mediatek/mt8196: Enable ARM Trusted Firmware integration
* 42a696090f Update arm-trusted-firmware submodule to upstream master
* 861413b295 mb/google/nissa/var/riven: Set PCIe root port 4 speed to Gen2
* d5a11293ff soc/intel/alderlake: Add support for PCIe speed setting
* 5b447d00f5 soc/intel/pantherlake: Fix UFS ACPI inclusion in southbridge.asl
* 1c51c3e57f device/pci_ids: Add Pantherlake-H GT2 (DID2)
* 15109603c6 mainboard/ocp/tiogapass: Enable TPM
* 94d200c394 soc/intel/xeon_sp/cpx: Add missing FADT fields
* 534585d7bd soc/intel/xeon_sp/skx: Drop ACPI_FADT_8042
* 98ca450a53 soc/intel/xeon_sp: Use generate_p_state_entries
* 28c03b501e mb/ocp/tiogapass: Implement mainboard_dimm_slot_exists
* 74ee80d207 soc/intel/xeon_sp/cpx: Fix register lock
* e1a0e6b738 soc/intel/xeon_sp/skx: Fix CPU init
* b04ecb2a5f arch/x86: Enable support for IOAPIC devices
* a7437ca340 soc/intel/common/block/cse: allow CSE telemetry on non-lite CSE SKU
* 0d284bfc36 soc/intel/mtl/acpi/gpio.asl: fix missing gpio.h include
* aeb5ccd129 ec/dasharo/ec: add Dasharo features
* 820c7e06d2 soc/mediatek/mt8196: Set DRAMC_PARAM_HEADER_VERSION to 4
* d8104af174 mb/google/rex/var/kanix: Disable FP_MCU based on fw_config
* 075a13b775 mb/google/fatcat: Update Soundwire codec address based on devicetree
* 2411942a05 drivers/soundwire/alc711: Add common Kconfig for ALC7xx soundwire codecs
* 534f81d165 mb/google/fatcat: Update flash layout
* 1b175a64e3 soc/intel/ptl: Populate SMBIOS Type 4 with unique serial number
* 4b574281f0 soc/intel/cmn/pmc: Retrieve SoC QDF information via PMC IPC
* 4ce5304879 soc/intel/xeon_sp: Advertise DIMMs on skylake_sp as well
* 5613f0e6be soc/intel/xeon_sp: Fix debug print
* 0d827a5810 soc/intel/xeon_sp: Drop SOC_INTEL_MMAPVTD_ONLY_FOR_DPR
* d3aa108acf drivers/ipmi/ocp: Add missing include
* 37e9c22089 libpayload: configs: Add new config.featuretest to broaden CI
* bcced7caea commonlib/device_tree: Make END token part of struct_size
* 8ad1ee9b0a util/intelp2m: Print the current project version
* 1b9c312273 intelp2m/patform/sunrise: Add unit tests
* 2394795279 intelp2m/patform/lewisburg: Add unit tests
* bce3363412 intelp2m/patform/apollolake: Add unit tests
* 6abf66c8f3 util/intelp2m/parser/template: Add unit test
* 6b43e4ba33 MAINTAINERS: Add Yuchi and Vasiliy for Intel Atom Snow Ridge SoC
* 5cedebf874 soc/intel/xeon_xp: Remove 1 bytes losing in lower DRAM
* cd30d94ae5 mb/google/brya/var/uldrenite: Generate RAM ID and SPD file
* cda1e7e553 mb/google/nissa: Create pujjogatwin variant
* c0ccace4d5 .checkpatch.conf: Set max line length to 96
* 6f2a8ee8cc soc/mediatek/mt8196: Require DRAM blob to exist
* 850cf7d07a Update blobs submodule to upstream main
* 75424efdc4 soc/amd/common/psp/psp_def.h: increase P2C_BUFFER_MAXSIZE
* 179945291c soc/amd/common/psp/rpmc: fix printk format string
* 9b308f4d54 soc/amd/common/psp/psp_smi: report errors in 'handle_psp_command'
* 5613f209c7 soc/amd/common/psp_smi_flash: implement SPI flash RPMC command handling
* b1f954bc6c soc/amd/common/block/psp/psp_smi_flash.h: fix struct element types
* ce01117aa5 drivers/spi: add RPMC support
* 78270ef3f1 Documentation/tutorial/managing_local_additions.md: Add symlink info
* 0a7c3ed514 soc/mediatek/mt8195: Fix SCP register address
* 4c8547704f mb/google/rauru: Add 2nd source TAS2563 amps to support beep
* ac83b48cba soc/mediatek/mt8196: Add audio base address definition
* c661933a24 soc/mediatek/common: Add read16/write16 support for PMIF
* c107755701 vc/intel/fsp: Update PTL FSP headers from 2382_01 to 2431.00
* a417acdfbc mb/google/fatcat: Remove unnecessary prototype
* d095f1ea45 soc/amd/glinda: Update MCA banks
* 8df4eefd44 soc/mediatek/mt8196: Reserve DRAM buffers for HW TX TRACKING
* 5c766bc150 mb/purism/librem_cnl: Add ramtop to cmos.layout for librem_mini
* 2007792b08 mb/purism/librem_l1um_v2/ramstage.c: Use DEV_PTR macro
* 7f54139a81 Docs/mb/starlabs/labtop_cml.md: Fix footnote syntax

Signed-off-by: Leah Rowe <leah@libreboot.org>

wip2

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-06 03:11:05 +00:00
Leah Rowe 411fb697df set up python in PATH, ensuring that it is python3
we already check the python version, and set a variable
for it, so that we can reliably use python3, even if
python in PATH doesn't correspond to python3. for
example if a system has python as python2 and python3
as python3

well, we use that when running deguard for example, but
various upstream projects that we use may need python,
and all of them use python3, not 2

so, re-use the python variable set up by lbmk, and
set it up in PATH accordingly. this now makes the note
about python3 obsolete, on docs/build.md in lbwww.git

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 21:48:45 +00:00
Leah Rowe e8336bcc3c vendor.sh: Proper semantics on prefix file names
They may not actually always be binary blobs, at least not
software. I started referring to these as "vendor files" some
time ago, for this reason.

With this terminology, it applies properly to any sort of file
from the vendor. For example, it may be that in the future, we
start inserting the MFS section of an an Intel ME image, into
the Intel ME.

We already do that with deguard for example (set MFS config),
on MEv11 based setup. That is a vendor *file*, and though it
may still actually be a binary blob, it's not software, but
configuration.

The term "blob" normally means compiled software, in most people's
minds, but the term blob is technically accurate for any blob,
not just software; however, we have to keep people's perception
in mind.

Whereas, "vendor file" is also understood by most people to
include code supplied by the vendor.

We haven't done any releases yet with this ROM image file name
prefix, so it's perfectly OK to handle it now, without handling
the old one for backwards compatibility.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 08:56:23 +00:00
Leah Rowe 63f4578263 vendor.sh: Confirm if need_files=n
Users running setmac on an X200 tarball for example, will
now see it being modified, if they didn't specify
setmac keep, so they might think vendor files are being
inserted, which they are not.

Therefore, a confirmation is provided at the end of the output.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 08:20:53 +00:00
Leah Rowe 13b06ae130 vendor.sh: Allow restoring the default GbE file
./mk inject libreboot-YYYYMMDD_board.tar.xz setmac restore

This does the same thing as a normal setmac command, except
that it does not alter the MAC address; it is also not the
same as "keep", which skips *writing* the GbE region in-ROM.

The *restore* argument writes the default, unmodified GbE file
kept by lbmk, unmodified because nvmutil is skipped when the
user specifies this argument.

This option is useful for debugging purposes, because it can
be used to verify whether anything else is being wrongly
modified by the script; the "nuke" command can be executed
afterward, and the hash file inspected versus release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 08:13:28 +00:00
Leah Rowe ab8feff92e vendor.sh: set random MAC address *by default*
MAC addresses are generic, inside Libreboot images where
an Intel GbE region is specified.

We commonly get users flashing multiple systems for their
own use, and sometimes they complain that they networking
broke, because they don't know that the MAC address is
identical on each machine.

This still doesn't work around the case where the same machine
is used, e.g. multiple T440p thinkpads, but if they have one
of each model, it can work nicely, because we do in fact
change it for various platforms.

This change will also reduce the number of people at conferences
in the future, where there are multiple Libreboot users, having
MAC address conflicts.

Changing the MAC address is a good practise, so we enforce good
practise. The user can still retain the old behaviour by
using this command:

./mk inject libreboot-YYYYMMDD_boardname.tar.xz setmac keep

The "keep" argument clears new_mac, which will then skip
changing the MAC address. They can also still set an arbitrary
MAC address as an argument for setmac, e.g.:

./mk inject libreboot-YYYYMMDD_boardname.tar.xz setmac 00:de:ad:c0:ff:ee

This change will be covered in the documentation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 07:48:50 +00:00
Leah Rowe 0ceaa01d45 vendor.sh: add clarification to nogbe warning
if the user ran this on an x60 tarball, the no-gbe
warning seems confusing since that one has intel gbe,
but pre-ifd, so no gbe region in the flash; on pre-ifd
systems e.g. ich7 southbridge, the mac address was baked
into a separate gbe nvm on mask rom, inaccessible to users

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-05 07:31:14 +00:00
Leah Rowe 4d5caf1dcf vendor.sh: check that the vcfg file exists
setcfg already checks it, but it's good to check anyway

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 19:32:39 +00:00
Leah Rowe fc4ee88e16 vendor.sh: error out if nuking failed
We already have code to handle this, but it's possible
that I might break it in the future, due to the complex
logic of this script.

So, I've implemented this catch-all check at the end of
the process. It still relies on the actual setting of
the variables, upon which this check is based, to be set
correctly.

This condition will most certainly never be met, unless
I break some other part of the code in the future. That
is precisely what this overly pedantic check is for.

Example scenarios:

I forget to set xchanged=y, on a new modification.

I set has_hashes erroneously.

The variables are re-used between runs, and not properly
reset; at present, a given run of ./mk inject only
operates on a single target, but this latter fact could
change in the future.

need_files is set erroneously; vendorfiles detected as
being required, when they aren't.

These are just a few examples. As such, this is a preventative
bug fix, because it's preventing a bug.

The main reason I want this i n here is because I need to ensure
that vendor files are properly deleted, for a given release.
If I accidentally includes ones that I'm not supposed to,
inside ROM images, that could be a big problem.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 19:24:53 +00:00
Leah Rowe 8819a93d89 add line break, part 3
forgot a line break, three times in a rowe

you got a problem with that?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:33:18 +00:00
Leah Rowe 8ce1a00f51 add line break, part 2
because printf

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:32:13 +00:00
Leah Rowe bc2c14e76a add line break
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:30:23 +00:00
Leah Rowe c762850311 vendor.sh: prevent double-nuke
where the nuke command is used, we need the files to be
there; if they're not, it will try to nuke them, which will result
in an error in most cases, but there may be some cases where that
isn't true, for instance if only the Intel ME is needed; it'll be
writing zeroes over zeroes.

we want to only allow technically correct behaviour, because
technically correct is the best kind of correct.

it is theoretically possible that a double-nuke might affect
certain behaviours unpredictably. for example, if vendor.sh
later integrates another tool that works whereby the same command
inserts or nukes depending on a certain condition, but with the
same command, and where that command would return zero in both
cases.

this is a preventative bug fix, because it fixes an issue that
does not yet actually occur in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:26:22 +00:00
Leah Rowe 68299ad05c vendor.sh: much more verbose errors/confirmation
the user must be well-informed as to the next step, which
this script directly influences

guide the user accordingly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 16:15:43 +00:00
Leah Rowe b8e6d12f3d add libx86 to arch dependencies
needed to compile the "int" tool defined
under config/git/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 14:21:24 +00:00
Leah Rowe cf8ad497b4 vendor.sh: Remove unnecessary return
The message at the end that states a file was
not modified, is not currently printed when vendor
files are not needed, and setmac is not used.

This patch fixes that, so the user now sees a
confirmation of such change, or lack thereof.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 02:36:50 +00:00
Leah Rowe c858099b35 vendor.sh: Download utils even if vcfg unset
This is because the user may have specified setmac.

I tried without this change, on a fresh lbmk, setting
the MAC address on an X200 tarball, and it produced an
error that ifdtool was unavailable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 02:33:32 +00:00
Leah Rowe ce16856a24 vendor.sh: Allow setmac if vendorfiles not needed
Observe the following prior patch:

commit 818f3d630c
Author: Leah Rowe <leah@libreboot.org>
Date:   Fri Jan 3 17:06:14 2025 +0000

    vendor.sh: Don't error if vcfg is unset

Now:

This patch made vendor inject more robust, and speeds
up the processing of images where no vendor files are
needed, but it broke setmac on such tar archives.

This new patch works around it. For example, I was
able to run ./mk inject on an X200 tarball to change
the MAC address; no vendorfiles are inserted, because
it's not needed.

The further check for whether a board uses Intel GbE
still protects against accidental modification.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 02:23:07 +00:00
Leah Rowe 4b51787d07 add less to arch dependencies
probably not actually needed, but it annoys me that it doesn't
come installed by default, and it's needed for certain git
operations

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-04 00:59:33 +00:00
Leah Rowe 8bd028ec15 lib.sh: Set python after dependencies
otherwise, the user can't install python, which is
in the dependencies. an irony!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 20:53:05 +00:00
Leah Rowe 44b6df7c24 update my copyright years on modified scripts
there are some lbmk scripts that i modified, starting
this year. update the headers.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 18:09:03 +00:00
Leah Rowe 818f3d630c vendor.sh: Don't error if vcfg is unset
It should return 1 instead, in readcfg(), because this
is not an error condition; vcfg not being set means
that the board doesn't use vendor files, which is
perfectly normal and should not yield an error.

This fixes a build error under certain conditions,
found during release-build testing.

This bug was exposed when I fixed double quoting issues
as per shellcheck tests.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 17:08:05 +00:00
Leah Rowe 432a1a5bca lib.sh: Fix unescaped quotes in chkvars()
This should be the proper fix now

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 16:00:11 +00:00
Leah Rowe a73b0fd910 Revert "fix more unescaped quotes in eval"
This reverts commit ec6bcc1fba.
2025-01-03 15:56:41 +00:00
Leah Rowe ec6bcc1fba fix more unescaped quotes in eval
it should fix more build errors that might have appeared
in the aforementioned revision, mentioned in the previous
commit message

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 15:43:27 +00:00
Leah Rowe 5284f20b98 fix ./mk dependencies build issue
the bug was actually caused by chkvars

add an escape for the quotes and bam. fixed.

without this, i got the following e.g.

For command: ./mk dependencies debian

Output:

./mk: 1: [: apt-get: unexpected operator
ERROR ./mk: pkg_add unset

Someone reported a similar issue with the Arch one,
which is also now fixed. This regression was caused
by the previous commit:

commit 0cf58c2273
Author: Leah Rowe <leah@libreboot.org>
Date:   Thu Jan 2 23:52:45 2025 +0000

    fix lbmk shellcheck errors

I forgot to escape the double quotes in an eval.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 14:35:31 +00:00
Leah Rowe d825f9a968 rom.sh: Remove errant GRUB modules check
This check is a good idea, but not viable here,
because the modules naturally aren't set in all
circumstances, so it just causes a build error.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 09:34:42 +00:00
Leah Rowe 4149f3dc81 submodule/grub: use codeberg for 1st gnulib mirror
the gnu.org mirror is always slow for some reason, but only
for gnulib. it may only be for me, because routing in other
countries/networks may differ.

when i'm freshly cloning lbmk modules, gnulib is always really
slow, like 300KB/s (bytes, not bits)

i have 1gbps internet and wish to not have 2005-era speeds,
thank you kindly!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 09:19:59 +00:00
Leah Rowe 0305975e70 util/nvmutil: Update AUTHORS and COPYING files
Mention Riku's copyright in the COPYING file, and update
my years in that file. Add Riku to the AUTHORS file.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:24:09 +00:00
Leah Rowe 20b192e13b util/nvmutil: Describe nvmutil in help output
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:15:18 +00:00
Leah Rowe d1ca21628c util/nvmutil: Remove the correct binary on uninstall
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:13:01 +00:00
Leah Rowe e63fe256df util/spkmodem-recv: More correct Makefile
Set up the DESTDIR variable properly. Otherwise,
this is just style changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:09:55 +00:00
Leah Rowe efd50ee548 util/nvmutil: Honour the INSTALL variable
Don't assume "install" is the correct command.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:08:38 +00:00
Leah Rowe 8008838abb util/nvmutil: Don't clean when doing uninstall
The user might wish to uninstall, but not remove the
build that they just did.

The user can still do make clean if they wish.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:06:12 +00:00
Leah Rowe 982f257f58 util/nvmutil: Proper DESTDIR/PREFIX handling
DESTDIR is the root directory where it goes, which
is normally an empty string; PREFIX is where the
bin directory is located, relative to DESTDIR

Default to /usr/local for PREFIX, not /usr, because
/usr/bin is for system utilities.

nvmutil is a local utility.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 02:03:44 +00:00
Leah Rowe 3f85ae5f85 util/nvmutil: Set CC and CFLAGS only if unset
We don't want to clobber anything that the user set themselves.

Instead, we should respect the user's choice.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:48:52 +00:00
Leah Rowe 2c7b9fb941 util/nvmutil: Capitalise BABA
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:45:55 +00:00
Leah Rowe 57f9906f6d util/nvmutil: Add uninstall to Makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:41:46 +00:00
Leah Rowe 4defe2c608 util/nvmutil: Add distclean to Makefile
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:39:46 +00:00
Leah Rowe 033e4cd9d5 util/nvmutil: Make the GbE checksum a define
This makes the code easier to understand.

All 2-byte words, stored in little endian order within
the 128-byte GbE NVM area, must add up to 0xBABA.

If it doesn't, then software is supposed to reject that
GbE config. The nvmutil software works on that basis.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 01:36:44 +00:00
Leah Rowe 874317c4e5 util/nvmutil: nicer hexdump display
make it look like hexdump -C, where individual bytes are
spaced, and there is an additional space after 8 bytes,
per row.

i won't bother with a character display, since that is
meaningless on gbe nvm words.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 00:36:17 +00:00
Leah Rowe a338e585ee util/nvmutil: show the correct hexdump order
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-03 00:26:32 +00:00
Leah Rowe b032e483ef lib.sh mktarball: cleaner if statement
i also removed that printf, because the path it prints is
actually wrong sometimes; in the recent re-write of vendor.sh,
it prints the correct path instead

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 23:58:37 +00:00
Leah Rowe 0cf58c2273 fix lbmk shellcheck errors
There was also a condition in run_make_command that is now
an OR, where it was an AND, on script/trees, to fix the use
of mixed (and erroneous) OR/AND operators.

I'm planning a much more invasive audit than this. These are
light fixes, intended for Libreboot 20241206 rev8.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 23:52:45 +00:00
Leah Rowe 8276560cc9 lib.sh and rom.sh: update my header
i made modifications to them in 2025, so
update them to 2025

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 18:33:55 +00:00
Leah Rowe 08e86d2218 vendor.sh inject: reset err upon return
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 10:17:39 +00:00
Leah Rowe 41275d699c vendor.sh: MUCH, MUCH, MUCH safer ./mk inject
Don't extract to bin/release/

Modify the tarball instead. Previously, the tarball would
not be modified, but a lot of users thought the tarball was
being modified and ignored bin/release/, where the injected
images were actually being saved to.

Don't copy the tarball either. Just modify it in-place.

Don't allow single-rom injection either; only allow the
tarball-based method.

The command syntax has changed, but:
./mk inject tarball.tar.xz

This is the same. What has changed is nuke, and MAC address
modification. Observe:

./mk inject tarball.tar.xz nuke
./mk inject tarball.tar.xz setmac
./mk inject tarball.tar.xz setmac ??:??:??:??:??:??
./mk inject tarball.tar.xz setmac 00:1f:16:??:22:aa

These are just a few examples. The MAC address syntax is
the same as used for nvmutil, which means you can set it
randomly. Also:

./mk inject tarball.tar.xz setmac

You can use the *setmac* command *repeatedly*, even if
you've already injected a given archive. It'll just
update the archive, but skip injecting other files
that were already injected.

If you use setmac without a MAC address, it will randomise
the MAC address. This is therefore very similar to the
command structure used in nvmutil.

The code for injection is generally more robust, with
stronger error checks. This design change was done, so
that the user doesn't accidentally brick their machine.

The non-injected images have a prefix in the file name
saying "DO_NOT_FLASH", and those non-injected images are
padded by 1 byte. That way, the user knows not to flash it
and if they try, flashprog will throw an error.

The prefix and padding is removed on injection. Old images
without the padding/prefix can still be injected, via
tarballs; this new code is backwards-compatible with tarballs
from older Libreboot releases.

A common thing I see sometimes is a user will say they have
a black screen or something, and I say: did you insert vendor
files? And they say yes. And they did. But they extracted and
flashed from the tarball, which wasn't injected, because
they didn't release about bin/release/

No amount of RTFM is justified. The previous design flaw
is a bug. We must always observe user safety first, no matter
what, so that has now been done.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-02 08:46:36 +00:00
Leah Rowe ed7293494e util/nvmutil: Obey the 79-character per line limit
Must not exceed 79 lines. Some variables and functions have
been renamed, and there has been some minor re-factoring.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 21:10:56 +00:00
Leah Rowe 637b5e36fd util/nvmutil: Tidy up copyright header
I don't like using SPDX for actual copyright declarations.

I only want it to be used for the license identifier.

Also:

I made a *single* change to nvmutil.c in 2024, which means
that I have copyright in all years since and including 2022;
the file said 2022, 2023, 2025, but it's actually 2022-2025.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 20:56:54 +00:00
Leah Rowe cd28db883e vendor.sh: fix comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 18:30:57 +00:00
Leah Rowe 57971ceb22 util/nvmutil: Fix another straggler
I don't like using strings this way, it looks unclean.

Once again, use good old fashioned if/else.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-01-01 14:49:24 +00:00
Leah Rowe 15b37b2a1a util/nvmutil: Tidy up pledge calls
I wasn't too happy using shorthand for strings like that.

Tidy it up and use good old fashioned if/else.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 21:14:24 +00:00
Leah Rowe e8799310db hp820g2: fix vendorfile inject and set release=y
I believed that the compressed nature of refcode was the only
non-reproducible thing, but turns out you also need to run
rmodtool on the refcode to make the binary relocatable in
cbfs. This is based on my reading of the coreboot Makefile.

With this change, I can now provide release binaries for
the HP EliteBook 820 G2.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 14:46:13 +00:00
Leah Rowe f9ab082ec1 fedora41/dependencies: add libuuid-devel
it seems to be required for uuid/uuid.h

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:57:00 +00:00
Leah Rowe 661591f9f0 add uuid-devel to fedora41 dependencies
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:27:11 +00:00
Leah Rowe 1a46c04738 support ./mk dependencies fedora reinstall
dnf reinstall package

or

dnf install package

for reinstall, do this:

./mk dependencies fedora41 re

this is an example command

the 4th argument prefixes "install" in dnf install

a bit hacky but it should work

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:25:27 +00:00
Leah Rowe d58d63569f fix missing semicolon in grub nvme patch
i  forgot this when rebasing on the recent uprev

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 04:22:11 +00:00
Leah Rowe 95ea3293df bump seabios to rev 1602647f1 (7 November 2024)
This brings in a *single* change from SeaBIOS, because there
has only been one change in the main branch, and it's a bug fix.

The change from upstream is as follows:

commit 1602647f1be24fe63d11138d802e735c8e674e63
Author: Daniel Khodabakhsh <d.khodabakhsh@gmail.com>
Date:   Thu Nov 7 18:46:16 2024 -0800

    boot: Force display of the boot menu when boot-menu-wait is a negative number

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 03:31:37 +00:00
Leah Rowe 6d7e6c361b Bump GRUB revision to 6811f6f09 (26 November 2024)
Although this is for a stable release revision, namely
Libreboot 20241206 revision 8, I've carefully audited the
upstream changes and they all seem fine.

Several important bug fixes have been imported with this change.
Most interestly, GRUB has also added support for TPM2 Key
Protectors; we don't use this feature yet, and probably won't
for the time being, since TPM is largely security threatre for
our purposes anyway. There's no harm including all upstream
revisions, up to those ones, since those modules are not yet
added in lbmk.

Most notably, there are several file system fixes, and minor fixes
to the graphics terminal of GRUB. Minor fixes only, in terms of
what Libreboot actually uses at present.

The full list of imported changes are as follows, relative to the
previous GRUB revision, which was b53ec06a1 from 17 June 2024:

* 6811f6f09 tpm2_key_protector: Enable build for powerpc_ieee1275
* ff14b89bd ieee1275/tcg2: Add TCG2 driver for ieee1275 PowerPC firmware
* 72092a864 ieee1275/tcg2: Refactor grub_ieee1275_tpm_init()
* 8c0b5f200 ieee1275/ibmvpm: Move TPM initialization functions to own file
* 7344b3c7c ieee1275: Consolidate repeated definitions of IEEE1275_IHANDLE_INVALID
* 29d1bd2a9 term/ieee1275/serial: Cast 0 to proper type
* 99ee68a01 tss2: Adjust bit fields for big endian targets
* 3770a6905 docs: Document TPM2 key protector
* f898440cc tests: Add tpm2_key_protector_test
* 76a2bcb99 tpm2_key_protector: Add grub-emu support
* 135e0bc88 diskfilter: Look up cryptodisk devices first
* b35480b48 cryptodisk: Wipe out the cached keys from protectors
* 6abf8af3c cryptodisk: Fallback to passphrase
* fba3a474e tpm2_key_protector: Implement NV index
* 550ada7d6 tpm2_key_protector: Support authorized policy
* 5f6a2fd51 util/grub-protect: Add new tool
* ad0c52784 cryptodisk: Support key protectors
* 48e230c31 key_protector: Add TPM2 Key Protector
* 35c9904df tss2: Add TPM2 Software Stack (TSS2) support
* 63a78f4b4 tss2: Add TPM2 types and Marshal/Unmarshal functions
* 2ad159d9b tss2: Add TPM2 buffer handling functions
* 5d260302d key_protector: Add key protectors framework
* 3d60732f9 libtasn1: Add the documentation
* 99cda6788 asn1_test: Test module for libtasn1
* 504058e82 libtasn1: Compile into asn1 module
* 8a0fedef2 asn1_test: Enable the testcase only when GRUB_LONG_MAX is larger than GRUB_INT_MAX
* 66cf4cb14 asn1_test: Use the grub-specific functions and types
* 0d0913fc6 asn1_test: Print the error messages with grub_printf()
* 2e93a8e4b asn1_test: Remove "verbose" and the unnecessary printf()
* b7568e335 asn1_test: Return either 0 or 1 to reflect the results
* d60a04bae asn1_test: Rename the main functions to the test names
* 54e0e19a2 asn1_test: Include asn1_test.h only
* 0ad1d4ba8 libtasn1: Fix the potential buffer overrun
* 4160ca983 libtasn1: Use grub_divmod64() for division
* 8f56e5e5c libtasn1: Adjust the header paths in libtasn1.h
* d86df91cb libtasn1: Replace strcat() with _asn1_str_cat()
* 32fdfe600 libtasn1: Replace strcat() with strcpy() in _asn1_str_cat()
* fa498af7b libtasn1: Disable code not needed in GRUB
* 9a26abbc3 libtasn1: Import libtasn1-4.19.0
* c85c2b9f5 posix_wrap: Tweaks in preparation for libtasn1
* 4f6c46091 kern/fs: Honour file->read_hook() in grub_fs_blocklist_read()
* 792132c72 docs: Fix incorrect and potentially confusing language and minor formatting
* 1763d83f5 docs: Correct GRUB config file name for network boot
* 097fd9d9a docs: Correct chainloader UEFI secure boot info
* f48e6af11 docs: Correct PXE environment variables descriptions
* dd743ba42 loader/multiboot: Do not add modules before successful download
* 9a9082b50 grub-mkimage: Add SBAT metadata into ELF note for PowerPC targets
* f97d4618a grub-mkimage: Create new ELF note for SBAT
* f26b39860 commands/legacycfg: Avoid closing file twice
* 337cb2486 nx: Rename GRUB_DL_ALIGN to DL_ALIGN
* 31de991de kern/acpi: Fix out of bounds access in grub_acpi_xsdt_find_table()
* f5bb766e6 nx: Set the NX compatible flag for the GRUB EFI images
* 94649c026 nx: Set page permissions for loaded modules
* 09ca66673 nx: Add memory attribute get/set API
* 9fb80dd57 modules: Load module sections at page-aligned addresses
* 6e2fe134e modules: Don't allocate space for non-allocable sections
* 2b79d550f modules: Strip .llvm_addrsig sections and similar
* 246c82cda modules: Make .module_license read-only
* 616adeb80 i386/memory: Rename PAGE_SIZE to GRUB_PAGE_SIZE and make it global
* 95a7bfef5 i386/memory: Rename PAGE_SHIFT to GRUB_PAGE_SHIFT
* 1b1061409 i386/msr: Extract and improve MSR support detection code
* 929fafdf5 i386/msr: Rename grub_msr_read() and grub_msr_write()
* d96cfd7bf i386/msr: Merge rdmsr.h and wrmsr.h into msr.h
* 86ec48882 commands/tpm: Skip loopback image measurement
* 3808b1a9b net/drivers/efi/efinet: Skip virtual VLAN devices during card enumeration
* e5f047be0 efi/console: Properly clear leftover artifacts from the screen
* c5ae124e1 kern/riscv/efi/init: Use time register in grub_efi_get_time_ms()
* 9c34d56c2 loader/efi/linux: Reset freed pointer
* 92bed41bf loader/efi/linux: Reuse len variable
* 33cb8aecd lib/x86_64/relocator_asm: Use .quad instead of .long
* 77cd623de lib/x86_64/relocator_asm: Fix comment in code
* 95145eea5 loader/efi/linux: Update comment
* d333e8bb3 util/grub-mkimagexx: Explicitly move modules to __bss_start for MIPS targets
* 34b7f3721 include/grub/offsets.h: Set mod_align to 4 on MIPS
* ed0651673 gentpl: Put boot/mips/startup_raw.S into beginning of the image
* 648f2d16c configure: Add -mno-gpopt option for mips and mipsel targets
* f0710d2d8 lib/xzembed/xz_dec_bcj: Silence warning when no BCJ is available
* e61157bbd fs/erofs: Replace 64-bit modulo with bitwise operations
* 5313fa839 configure: Look for .otf fonts
* 33b94f2a9 loader/efi/chainloader: Do not print device path of chainloaded file
* ab1e6fc04 docs: Document all GRUB modules
* 9537f4403 commands/bli: Fix crash in get_part_uuid()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 03:13:58 +00:00
Leah Rowe 09a01477df t480/3050micro: force power off post power failure
The T480 has no option table, because it lacks nvram, so the
default option applies, which seems to be power on after power
failure. This is undesirable on a laptop.

It's triggered simply when your laptop battery runs out, and
once triggered, it couldn't be configured at all.

Hard-code this. The documentation will be updated later on
after this patch is pushed, telling those users who want
to change this behaviour how to modify/remove the patch,
if they wish to to do so, because some people may actually
want to run a server on the OptiPlex 3050 Micro (or if they're
crazy like I am, they will host libreboot.org on a ThinkPad).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 01:54:02 +00:00
Leah Rowe d344cd95ea flashprog: Disable -Werror
We haven't seen any build errors, but it seems flashprog
sets -Werror on CFLAGS. If you provide WARNERROR=no as
a make argument, it avoids -Werror entirely.

This is a preventative fix, for over-zealous compilers.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 00:12:21 +00:00
Leah Rowe dc95e912bf bump flashprog to revision eb2c041 (14 Nov 2024)
This brings in several important bug fixes from upstream.

With this, the following upstream changes have been imported:

* eb2c041 cli_wp: Fix bail-out when multiple chips are detected
* e05e334 cli_common: Rename local `optarg' variable
* efad610 manibuilder: Include NetBSD (anita tags) in `native' target
* 09289fb manibuilder: Replace unmaintained DEFAULT_TAGS list
* 1457cc6 manibuilder: Stop build testing oldest, EOL targets
* 1faffa5 manibuilder: Fix Ubuntu Noble Numbat (24.04) for amd64
* 61dbe36 udev rules: Use `uaccess' tag instead of `plugdev' group
* 63d30a2 install: Install binary into bin/, not sbin/
* 6ce26a7 flashchips: add Winbond W25R512NW / W74M51NW
* 612519b ichspi: Add Intel Arrow Lake support
* d5a61ef ichspi: Add Intel Lunar Lake support
* 5e0d9b0 ichspi: Add Intel Meteor Lake SoC
* 0ef2eb8 ichspi: Add Intel Snow Ridge SoC
* 42daab1 ichspi: Properly add Emmitsburg PCH
* af26008 ich_descriptors_tool: Add missing options for EHL & C620
* 82fe123 ich_descriptors: Hard code number of masters for newer gens
* 157b818 ich_descriptors: Guard MCH strap handling by chipset version
* db878fb ich_descriptors: Drop chipset detection based on `freq_read`
* b3cc2c6 ich_descriptors: Unify pretty printing of PCH100+ masters
* 8e4151d chipset_enable: Remove hidden-spidev workaround for Elkhart Lake
* 6d72efa chipset_enable: Remove hidden-spidev workaround for all 14nm PCHs
* 092a699 chipset_enable: Remove hidden-spidev workaround for TGP+
* 5bbd324 chipset_enable: Add missing PCI ID for Intel PCH H410
* a088475 chipset_enable: Factor PCH100 hidden-spidev workaround out
* 5eb7a58 Drop 1s delay before automatic verification
* 7427569 libflashprog: Run programmer_shutdown() on failed setup
* 5a9d6ea chipset_enable: Fix memory leaks introduced with AMD SPI100
* e149fbe Only try to check erase opcodes for SPI25 chips
* 07ebc68 Avoid NULL deref in check_block_eraser()
* 2405310 chipset_enable: Mark Intel QM87 as DEP
* 9897063 flashchips: Allow volatile register writes for W25Q128.V
* c972aed flashchips: Configure WP for MX25L25635F/45G
* 8f7122c cli: Add new write-protect CLI
* eed122d layout: Implement flashprog_layout_get_region_range()
* 1f693db cli: Add new `config' CLI for status/config registers
* 85c2cf8 cli: Implement "command" option parser
* 24c0977 cli: Add print function for generic CLI options
* b82aadc cli: Move some declarations into `cli.h`
* a705043 cli: Add a new CLI wrapper
* d39c7d6 cli: Extract basic CLI init into cli_common
* df6ce9f cli: Extract log argument parsing into cli_common
* 0da839b cli: Extract layout argument processing
* d91822a cli: Extract layout argument parsing into cli_common
* e7899a9 cli: Move all long-option keys into cli.h
* 34e783a cli: Extract flash argument parsing into cli_common
* e68b08b cli_classic: Rewrite programmer argument parsing
* 6898f5b spi25_statusreg: Prefer volatile status register writes
* 55e7884 Introduce FLASHPROG_FLAG_NON_VOLATILE_WRSR
* fbba454 Install udev rules
* 768cfc4 flashchips: Add GigaDevice GD25LR512ME

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-31 00:03:12 +00:00
Leah Rowe 27c8c1c16b replace liblz4-tool with lz4 and liblz4-dev
In Debian dependencies files. These are available in
Debian Stable, but liblz4-tool is a transitional
package referring to lz4; liblz4-tool transition
package is unavailable in Debian sid, so remove it
from the dependencies files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 22:31:24 +00:00
Leah Rowe d3a732a64d lib.sh dependencies: support --reinstall argument
./mk dependencies debian --reinstall

Add --reinstall and it'll do:

apt-get install --reinstall

This can be useful when updating from a stable release
to a testing release. The variable, "reinstall" can be
configured for other distros, but it's currently only
configured for Debian-based distros.

Also, it can be anything. For example, you could add -y;
however, a 4th argument will not be accepted. For example,
you cannot do:

./mk dependencies debian --reinstall -y

If you do this, it'll only see --reinstall; similarly, if
you did this command:

./mk dependencies debian -y --reinstall

then -y would be passed, but not --reinstall. This is an
intentional design decision, in case you accidentally pasted
or subshelled something that outputted something undesirable,
to prevent possible abuse.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 21:53:55 +00:00
Leah Rowe 466ada423d move xbmkpath to XBMK_CACHE/
When doing ./mk release, the build system would create
symlinks inside xbmkpath/ relative to the current work tree,
which will differ from what's in PATH.

Since XBMK_CACHE is already set globally, from the main work
tree and the release-build work tree, that means we can know
reliably that PATH is always correct if we put xbmkpath/
inside XBMK_CACHE.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 21:25:55 +00:00
Leah Rowe b0a2384032 Revert "Remove legacy update/vendor commands"
This reverts commit 7813205146.

I'm doing changes for 20241206 rev8. It was a mistake to
remove these; they will be removed again, after rev8.

The documentation standardised on ./mk a while ago now, and
it's almost time to remove these commands. However, anyone
using the old commands ought to be able to, up to and including
any revision of the Libreboot 20241206 release.

It is my intention that these legacy commands finally be
removed for the next testing release, as part of a much wider
build system audit that I'm doing between now and then.

(Libreboot Build System Audit 7 is underway, and several of
these early audit7 changes are going on 20241206 rev8; after
that, I will create a branch named 20241206_branch off of rev8,
and anything in master from then on will contain much wilder
changes, with more conservative changes in 20241206_branch)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 21:06:05 +00:00
Leah Rowe 3d7dd4aa9f Fix U-Boot build issue with Swig 4.3.0
Tested on Debian Sid, as of 30 December 2024, which uses
Swig 4.3.0. Context here:

commit a63456b9191fae2fe49f4b121e025792022e3950
Author: Markus Volk <f_l_k@t-online.de>
Date:   Wed Oct 30 06:07:16 2024 +0100

    scripts/dtc/pylibfdt/libfdt.i_shipped: Use SWIG_AppendOutput

This patch from U-Boot upstream has been backported to the
release revision used by Libreboot. Swig has, since 4.3.0,
changed the language-specific AppendOutput functions, but
the helper macro SWIG_AppendOutput is identical; therefore,
upstream switched to this function.

The benefit of this fix is that since the newly used macro
is also the same on older Swig versions, and behaves the same,
this shouldn't fix building on older Swig versions. For reference,
the initial Libreboot 20241206 release, and revisions of it before
revision 8, was built on Debian 12 which uses Swig 4.1.0.

The rev8 release will still be compiled on Debian 12, but with
this change, it should also compile on Debian Sid, and bleeding
edge distros like Arch Linux.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 20:24:46 +00:00
Leah Rowe 0c81074746 use command -v instead of which
which is a non-standard command, whereas command is part of posix

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 19:23:27 +00:00
Leah Rowe 6c7e3ce2d6 trees: remove unnecessary subshell
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 18:38:42 +00:00
Leah Rowe ad137eae89 trees: only symlink host gcc/gnat to build xgcc
In general, we don't want to mess with the hostcc, unless
we have to. To avoid other breakage, clear what we did
after crossgcc has compiled.

This is a follow-up to the previous patches, matching gcc
to gnat versions and vice versa, when compiling crossgcc.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 18:36:46 +00:00
Leah Rowe cfb6de94c3 trees: correction on check_gnu_path
i intend for this function to work generically,
matching gnat to gcc or gcc to gnat, but there was
a hangover from the previous code where it specifically
assumed we were matching gnat

this bug manifested when i tested with gnat being v13
and gcc being v14 in path, where gcc-13 was also
available in path.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 17:59:19 +00:00
Leah Rowe ec2f071666 trees: match gcc/gnat versions both ways
on debian trixie/sid after updating from stable,
sometimes gcc 13 and gnat 13 are both available, but
gcc resolves to gcc-14 and gnat-14 isn't available.

even when gnat-14 and gcc-14 are available, gnat will
still either resolve to gnat-13, or nothing at all.

in cases where gnat-14 is unavailable, but gcc and gnat 13
are both available, we should match gcc to gnat.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 15:29:41 +00:00
Leah Rowe f64b599627 Merge path.sh into script/trees
The code is simple enough now that I'm happy for it
to just be part of the main script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 14:14:19 +00:00
Leah Rowe 295463d281 path.sh: Further cleanup
Remove all symlinks each time, to ensure that no
stragglers are left behind, since they are being
re-generated each time anyway.

The code for determining version numbers has now
been unified under gnu_setver()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 14:11:45 +00:00
Leah Rowe 5b24e0a5a9 path.sh: More thorough gcc/gnat version check
We were checking the shorthand version number, but
the precise version numbers need to match.

Also: when we searched $PATH/gnat-$gccver, we assumed
that the full version would then match, without checking
it, so now it is checked precisely.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 13:36:34 +00:00
Leah Rowe 7849a07588 path.sh: minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 13:18:57 +00:00
Leah Rowe 17168a87db path.sh: remove unnecessary shebang
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 02:24:23 +00:00
Leah Rowe e565df94fd Fix globbing issue in lbmk
When doing e.g. $@ we should use double quotes to prevent globbing.

Thanks go to XRevan86 for pointing this out.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 01:02:22 +00:00
Leah Rowe c80cc0a00b remove auto-confirm on distro dependencies
because if it says yes to everything, and the package
manager would otherwise ask whether you want to give
it your first born son, you are therefore agreeing to it.

so remove -y for safety

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 00:29:04 +00:00
Leah Rowe 01fc65a0a9 Mitigate Debian Trixie/Sid GCC/GNAT version mismatch
When I tested Debian Trixie, and Debian Sid, I saw that
GCC in PATH pointed to gcc-14, but gnat in path pointed
to GNAT-13, even if you manually install gnat-14.

GNAT 14 was marked experimental, but GCC 14 was marked
for use, in the apt repositories.

So this patch doesn't address the mismatch when doing e.g.
apt-get install gcc gnat

I will address the actual package dependency in a follow-up
patch, on the Debian dependencies config.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-30 00:21:02 +00:00
Leah Rowe 424b0c7103 t480/3050micro: disable hyperthreading
Hyperthreading is a risk factor for spectre/meltdown
and other attacks.

Disabling it is a best practise. Those who need it
can always turn this option back on. Otherwise, disabling
it by default is a simply courtesy to the average user,
in the interest of security.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-29 02:10:03 +00:00
Leah Rowe 603105f3b4 t480/t480s: Disable TPM2 to mitigate SeaBIOS lag
SeaBIOS was lagging a lot, on startup and when executing
almost any payload, especially when doing anything in the
ESC menu.

I set the debug level to *21*, and thoroughly analysed the
logs. I found entries such as this:

Checking for bootsplash
WARNING - Timeout at wait_reg8:81!
TCGBIOS: Return value from sending TPM2_CC_StirRandom = 0x00000000
WARNING - Timeout at wait_reg8:81!
TCGBIOS: Return value from sending TPM2_CC_GetRandom = 0x00000000
WARNING - Timeout at wait_reg8:81!
TCGBIOS: Return value from sending TPM2_CC_HierarchyChangeAuth = 0x00000000
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc16e
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc1c5
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc211
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc25d
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc2a9
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc2f5
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc341
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc38d
WARNING - Timeout at wait_reg8:81!
TCGBIOS: LASA = 0x7a9fc000, next entry = 0x7a9fc3d9
Searching bootorder for: HALT
Mapping hd drive 0x000f49e0 to 0

I'm not quite certain what the problem is, but disabling TPM2
made the problem go away; SeaBIOS is snappy again.

TPM is security threatre anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-29 01:20:33 +00:00
Leah Rowe 754bd1e6ca rom.sh: Name pico directory serprog_pico
Previously serprog_rp2040, but we now also support
the RP2530 boards.

Therefore, serprog_pico is a nice generic name. The
directory on release archives will now be serprog_pico
instead of serprog_rp2040; it will contain serprog images
for both RP2040 and RP2530 devices.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-28 16:46:59 +00:00
Leah Rowe db22308eba add 2024 to Riku's copyright header on rom.sh
he forgot to do this in the recently merged pico2
support. i'm doing it for him as a matter of courtesy.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-28 13:24:01 +00:00
Leah Rowe 4fa5f696db Merge pull request 'rp2530' (#258) from Riku_V/lbmk:rp2530 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/258
2024-12-28 12:26:39 +00:00
Riku Viitanen a5e0360992 pico-sdk: update to 2.1.0
this brings support for a new microcontroller platform rp2530.

total number of pico boards supported now: 97

TEST: built them all

Tested-by: Riku Viitanen <riku.viitanen@protonmail.com>
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2024-12-28 04:02:08 +02:00
Riku Viitanen e2f8cc7f3e pico-serprog: enable building for multiple pico chips
rp2040 and rp2530 platforms can't share a cmake build directory. we
could just delete the build directory after every compilation, but that
would be really wasteful (every tool would need to be recomiled every
time. instead create new build directories as new plaforms are found
and symlink them to the point where the build directory used to be.

to find out which platform we're compiling for, we crudely parse the
board headers file.

there surely would be better ways to do this, but this hack works
with all the boards in pico-sdk 2.1.0.

Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
2024-12-28 03:53:25 +02:00
Leah Rowe ccc2b4d589 add spdx headers to dependencies configs
these used to be separate scripts under gpl 3+, so it makes
sense to clarify the licensing situation

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-27 14:01:07 +00:00
Leah Rowe a3969701e6 dependencies/debian: fix debian sid
change python3-distutils to python3-distutils-extra

the latter is still available in debian sid, but not
the former. however, installing this should still
provide the additional files required.

with this, the debian script is now compatible with
both debian sid and debian stable(bookworm, presently).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-27 13:58:29 +00:00
Leah Rowe 8f370cb60d add spdx headers to various config files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-27 02:24:38 +00:00
Leah Rowe d591ea4c5d git.sh: don't initialise livepull globally
set this variable in the tmpclone function. otherwise,
certain submodules might always download every time,
when handling multiple projects.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-26 23:47:48 +00:00
Leah Rowe b5da9feba3 vendor.sh: Print useful message on ./mk inject
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-26 22:25:07 +00:00
Leah Rowe 12c6259cb2 vendor.sh: Handle FSP insertion post-release
The Libreboot 20241206 release provided FSP pre-assembled
and inserted into the ROM images; the only file inserted
by vendor.sh was the Intel ME.

Direct distribution of an unmodified FSP image is permitted
by Intel, provided that the license notice is given among
other requirements. Due to how coreboot works, it must split
up the FSP into subcomponents, and adjust certain pointers
within the -M component (for raminit).

Such build-time modifications are perfectly fine in a coreboot
context, where it is expected that you are building from source.
The end result is simply what you use.

In a distribution such as Libreboot, where we provide pre-built
images, this becomes problematic. It's a technicality of the
license, and it seems that Intel themselves probably intended
for Libreboot to use the FSP this way anyway, since it is they
who seem to be the author of SplitFspBin.py, which is the
utility that coreboot uses for splitting up the FSP image.

Due to the technicality of the licensing, the FSP shall now
be scrubbed from releases, and re-inserted.

Coreboot was inserting the -S component with LZ4 compression,
which is bad news for ./mk inject beacuse the act of compression
is currently not reproducible. Therefore, coreboot has been
modified not to compress this section, and the inject command
doesn't compress it either. This means that the S file is using
about 180KB in flash, instead of about 140KB. This is totally OK.

The _fsp targets are retained, but set to release=n, because these
targets *still* don't scrub fsp.bin; if released, they would
include fsp files, so they've been set to release=n. These can
be used on older Libreboot release archives, for compatibility.

The new ROM images released for the affected machines are:

t480_vfsp_16mb
t480s_vfsp_16mb
dell3050micro_vfsp_16mb

Note the use of _vfsp instead of _fsp. These images are released,
unlike _fsp, and they lack fspm/fsps in the image. FSP S/M must
be inserted using ./mk inject.

This has been tested and confirmed to boot just fine.
The 20241206 images will be re-compiled and re-uploaded with this
and other recent changes, to make Libreboot 20241206 rev8.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-26 22:05:16 +00:00
Leah Rowe 7813205146 Remove legacy update/vendor commands
We only use ./mk now.

./build still exists for now. This will be removed
in a future revision, when the trees script is removed
and merged with the main script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-25 09:10:57 +00:00
Leah Rowe 07037561bd lbmk: remove use of deprecated ./vendor command
use ./mk instead, because in a future change to lbmk,
only ./mk will be used and the other commands will
be removed.

with this change, the ./vendor, ./build and ./update
commands are no longer used. these commands still work,
for backwards compatibility, but they are deprecated.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 16:58:23 +00:00
Leah Rowe 5d1f182306 vendor.sh: Safer exit when vendorfiles not needed
When vendor files were not needed on a given board,
the script would directly exit. This is bad, because
the inject functions are called directly from the main
script, which means the parent instance of lbmk.

This means that the lock file and temporary files were
not being removed on exit. On a subsequent run, this
would cause the error stating that a lock file is present,
which would cause further error, making the user believe
something is broken in lbmk.

Modify the behaviour accordingly; exits are now returns,
and these are handled in the calling functions, in such
a way that a proper exit occurs, whereby temporary files
and the lock file are deleted.

For context, please read the main "build" script where
it calls vendor_inject and vendor_download. At the end
of that script, it calls tmp_cleanup, which removes the
TMPDIR that was created, and the lock file. In lbmk,
the TMPDIR is not /tmp, but rather a subdirectory
under /tmp, so that further calls to mktemp create
everything under one single temporary directory, which
lbmk automatically removes on exit.

Therefore, this patch also avoids leaving temporary files
laying around on the disk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 14:09:29 +00:00
Leah Rowe a18175a5df data/deguard: Remove unused patch
The appdir.patch file was used on the older deguard
version, prior to Mate Kukri's rewrite. This patch is
no longer required, and no longer used, so it can be
removed safely from lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 12:40:53 +00:00
Leah Rowe ee8f53b96f lib.sh: Safer exit from ./mk dependencies
The exit was dependent upon install_packages returning
zero status, which it always would in practise, due to
its design, but this exit must always be observed, so
the code has been modified to honour this design.

A direct exit violates lbmk's design in most instances,
where a temporary directory and lock file has already
been created; at this stage, no such act was performed,
so a direct exit is perfectly acceptable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-24 12:39:05 +00:00
Leah Rowe a8b35c88cf remove geteltorito and mtools from lbmk
we needed these for extracting intel vga roms from
lenovoo updates, for t480, very briefly. about an hour
after i pushed that patch, mate kukri fixed libgfxinit
and then i removed the vgarom integration because it
wasn't needed anymore.

however, i forgot to remove geteltorito/mtools from
dependencies. some distros like fedora were problematic
about it.

the best thing about bugs is when you don't have to fix them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-22 23:13:43 +00:00
Leah Rowe 1dd32ea548 rom.sh: support grub-first setups
in this setup, seabios is never the default payload, grub is,
but only if grub is enabled.

set this in target.cfg:

payload_grubsea="y"

if payload_grub isn't enabled, this is auto-set to n

ditto if initmode=normal

NOTE: if flashing libgfx setups, you should make sure
that you're not booting with a graphics card, only intel
graphics. this setting will intentionally not be documented,
because it's not recommended, but is being implemented for
testing purposes (and i implemented it for some guy who i
think is cool). i'll probably also use this myself, since
i already do grub-only setups on all my own machines.

seagrub is the default on x86 because of past instabilities
with grub. to mitigate in case of future issues, since seabios
is always stable, we reduce the chance of bricks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-18 07:15:18 +00:00
Leah Rowe f7801ef477 vendor.sh: delete old tb.bin first, just in case
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-18 03:49:58 +00:00
Leah Rowe 02cbf8a729 vendor.sh: make TBFW pad size configurable
we encountered 1MB flash so far, but we may encounter other
sizes on other machines when added to libreboot later on

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-18 03:42:45 +00:00
Leah Rowe 9884e5ed1b T480/T480S: Support fetching ThunderBolt firmware
Though not used in coreboot builds, and not injected into the
builds in any way, these files are now created seperately when
handling T480/T480s vendor files:

vendorfiles/t480/tb.bin
vendorfiles/t480s/tb.bin

These are created by extracting Lenovo's ThunderBolt firmware
from update files. The updated firmware fixes a bug; older firmware
enabled debug commands that wrote logs to the TB controller's
own flash IC, and it'd get full up with logs, bricking the controller.
If you've already been screwed by this, you must flash externally,
using a padded firmware from Lenovo's updates.

Lenovo's own updater requires creating a boot CD or booting
Windows. This patch in lbmk auto-downloads just the firmware,
and you can flash it externally.

You could simply do this as a matter of course, when installing
Libreboot. You are recommended to update the Lenovo UEFI/EC firmwares
first, before installing Libreboot; please look at the Libreboot
documentation to know exactly which versions.

Then dump the ThunderBolt firmware first, to be sure, and then you
can flash these files. Flashing these updates will prevent the bug
described here:

https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480-type-20l5-20l6/20l5/solutions/ht508988

You can download Lenovo's installers for various ThinkPad models
there, including T480s/T480s. It is these downloads that this lbmk
patch uses, to extract those files directly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-18 02:28:29 +00:00
Leah Rowe 36b42dd1c1 also de-rainbow the u-boot menu
boring is good

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-17 13:02:37 +00:00
Leah Rowe eafc82028a Revert "use rainbow deer on the grub background"
libreboot has a lot of users worldwide, some of whom live in
countries that punish being gay; if they look at libreboot or
boot it and it has the pride colours on it, it could actually
get them in trouble.

this fact occured to me, and i've decided therefore to revert
back to the boring plain logo.

though, perhaps we could actually properly design a new logo?
a new, modern logo, and a nicer website.

we'll see!

This reverts commit 401efb24b2.
2024-12-17 12:32:17 +00:00
Leah Rowe 44969c73bd rom.sh: insert grub background in cbfs not memdisk
for some reason, when the background is in memdisk, inserting
it into cbfs afterward doesn't override, despite this
being the behaviour in grub.cfg

put it in cbfs explicitly, and skip inserting into memdisk

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-17 01:02:03 +00:00
Leah Rowe 401efb24b2 use rainbow deer on the grub background
same as on u-boot recently

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-17 00:57:05 +00:00
Leah Rowe dc27cb9178 add some scripts to .gitignore
f/m are scripts i'm gradually working on. easy flash scripts
for lbmk. no promises when/if i push them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-13 06:28:05 +00:00
Leah Rowe 3b6b283eab disable 3050micro nvme hotplug
see patch for rationale. this should prevent instability caused
when the nvme randomly replugs under linux. sometimes e.g. nvme0n1
becomes nvme0n2 while the system is running.

in my case, that caused my raid1 to become unsynced every few days.
this issue was fixed on t480 by disabling pcie hotplug for its nvme
device, so the same fix has been applied for dell optiplex 3050 micro.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-11 01:11:08 +00:00
Leah Rowe c202392189 fix t480 spd size (512, not 256)
this was done with the following command:

./mk -u coreboot t480s_fsp_16mb t480_fsp_16mb

it was set to 256 but should be 512. the SPD is what
contains configuration data for raminit, which training
code uses so that the timings will be correct. if the SPD
size is wrong, the machine won't boot

in practise, lbmk always runs "make oldconfig" on
a coreboot config, before building it, so this was
already being corrected automatically at build time.

however, if that fact ever changes in the future, this
wrong configuration would cause the machines not to boot.

therefore, this can be considered a preventative or perhaps
pre-emptive bug fix.

this fix does not need to be applied to the 20241206 release,
because of the behaviour described above. the final ROM images
do have the spd size set correctly to 512, because of this
design feature in lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-10 23:48:41 +00:00
Leah Rowe da527459b6 add tarballs and signatures to gitignore
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-08 21:31:06 +00:00
Leah Rowe b910424b5d fix another very stupid mistake
the last revision disabled building arm64 images!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-08 18:24:57 +00:00
Leah Rowe e3b77b132e fix the stupidest bug ever
no context given, but every rom needs to be re-built.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-08 18:04:51 +00:00
Leah Rowe e80261dd54 Revert "vendor.sh: avoid unnecessary directory copy"
Nope. It was correct before. fml

This reverts commit 2d96fe2a1d.
2024-12-06 10:34:36 +00:00
Leah Rowe ec581bde47 Libreboot 20241206 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-06 10:06:38 +00:00
Leah Rowe 2d96fe2a1d vendor.sh: avoid unnecessary directory copy
the previous commit changed an mv to a cp. what it hacked
was actually a relic of the vgarom download patch that i
did for t480, before mate got native video init working.

this patch is the better fix. i double checked to be sure,
and nothing was using the files at the copied location.
the _extracted directory under cache gets deleted later on,
so it's perfectly acceptable to keep.

the other alternative would have been to simply change
the path in the sch5545 function to appdir, instead of
the cache dir, but who really cares?

this patch removes bloat from lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-06 01:53:44 +00:00
Leah Rowe 2dc7c5fa72 vendor.sh: fix minor release bug
I should have copied the extract directory, in cases
where it appears as filename_extracted/ under cache/,
but I was moving it instead.

Both locations (cache/file/*_extracted/
and vendorfiles/appdir/) get deleted, on every run of
the vendor script, per target, so this is OK.

The only sin is additional use of disk space, for
archives that are mostly very small and get immediately
deleted anyway.

This one lbmk bug, minor though it may be, prevented
the Libreboot 20241205 release, which (since it's now
the 6th of December) will become Libreboot 20241206
instead - and that gives me time to contemplate whether
I want to do one more change that I had planned for the 5th!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-06 01:24:35 +00:00
Leah Rowe 56b35bd9d8 Libreboot 20241205 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-05 23:45:01 +00:00
Leah Rowe 07983c1d88 Revert "Revert "disable u-boot on thinkpad t480""
Nope! Bootflow menu is cursed on this machine.

Too many issues in U-Boot on this machine. I did however
boot a Debian installer after it booted, using bootflow.

The installed system wouldn't boot with bootflow, but I could
then boot it with "bootefi bootmgr".

I'll rig up a uart on the T480 when I get round to it and
start investigating U-Boot bugs on this board.

I don't want people flashing something that doesn't work.
GRUB and SeaBIOS work, so ship those, and don't ship U-Boot.

This reverts commit 19ec440a6f.
2024-12-05 13:01:31 +00:00
Leah Rowe 19ec440a6f Revert "disable u-boot on thinkpad t480"
u-boot does work after a few reboots. it just boot loops.

let it run. it should be able to boot from nvme. sata still needs
some work (sata only works in grub, on this machine)

This reverts commit cd9baca5d6.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-05 09:55:06 +00:00
Leah Rowe 99513c3bf6 add patch from mkukri fixing t480 sata
nvme worked but not sata. with this, t480 users with sata
ssds should be able to boot linux nicely

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-05 09:33:51 +00:00
Leah Rowe cd9baca5d6 disable u-boot on thinkpad t480
it just bootloops and doesn't seem reliable at the moment

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-05 09:29:59 +00:00
Leah Rowe 8065b9842b remove the purple patch on arm64 u-boot
it's green there. different colour scheme apparently.

still works on x86. alper said his kevin chromebook was green!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-04 22:17:34 +00:00
Leah Rowe 5cc91d8e40 Merge pull request 'u-boot: Use bootflow menu by default for ARM64 boards' (#254) from alpernebbi/lbmk:u-boot-arm64-bootflow-menu into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/254
2024-12-04 20:16:01 +00:00
Leah Rowe bef2890233 i made u-boot purple
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-04 20:14:59 +00:00
Alper Nebi Yasak f26752fd85 u-boot: Use bootflow menu by default for ARM64 boards
The bootflow menu is already the default boot command on x86. Switch
arm64 boards to that as well, so instead of booting the first thing we
find, we can easily choose what to boot.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-12-04 22:51:45 +03:00
Leah Rowe 965f9bd033 Add bootflow/branding patches to arm64 U-Boot too
U-Boot on ARM64 also enables the bootflow menu.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-04 18:57:24 +00:00
Leah Rowe 44e6a0c090 Add libreboot branding/version to U-Boot bootflow
Show it in the bootflow menu

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-04 18:51:45 +00:00
Leah Rowe c038b653ac Add auto-boot timeout for U-Boot's bootflow menu
Otherwise, you have to press enter to boot your distro.

With this, a timeout is created. After a number of seconds,
which can be reconfigured, the first option selected will be booted,
when generating a bootflow menu.

The timeout is disabled when you navigate the menu; it only
kicks in if you don't input anything on the keyboard.

More information about how this works is in the U-Boot patches,
within this patch. I've set the timeout to 8 seconds.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-04 07:23:51 +00:00
Leah Rowe 7a6e47c24f 8-sec auto-boot timeout for U-Boot's bootflow menu
Otherwise, you have to press enter to boot, which is unacceptable
for headless operation.

Pressing anything other than enter an an option, such as the arrow
keys, will disable the timeout.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-03 21:40:15 +00:00
Leah Rowe 90850eb859 fix board name for coreboot/dell7010sff
i'd copied the t1650 config and reselected the board lazily.

this fixes the issue:

https://codeberg.org/libreboot/lbmk/issues/242

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-03 15:33:27 +00:00
Leah Rowe 8314fbc67e add /dump/ to .gitignore
this is used for factoryy bios dumps, in cases where
boards require extraction of ME and so on,
instead of downloading online.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-03 15:15:24 +00:00
Leah Rowe efebfa992b Revert "trees: Allow using a custom clean command"
This reverts commit 5b4c9158e5.
2024-12-02 21:22:36 +00:00
Leah Rowe 5b4c9158e5 trees: Allow using a custom clean command
On coreboot for example, as Mate has told me, if you're
making Kconfig changes and re-compiling, sometimes the
actual image that you build might still have the old one
in it, due to how coreboot's build system works.

To mitigate this, you can just always run distclean before
doing the build, but lbmk was doing just clean.

In practise, we did not find any issues, but this change should
be harmless, and might prevent such issues in the future. It's
even possible that we might have already encountered this before
and not realised, and we were just lucky that no noticeable issues
were caused.

It's *also* possible that the reverse is true: an issue that
was previously covered up, then that issue will now be exposed.
However, if that turns out to be true, then that is good because
we are exposing said bugs and then we will know to fix them!

Anyway, the variable in target.cfg is:

cleancmd="whatever_you_want"

e.g.

cleancmd="distclean"

You may also specify this in global mkhelper.cfg files, per
project; I've already done this for SeaBIOS, coreboot
and U-Boot, since all of these use Kconfig files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 20:41:05 +00:00
Leah Rowe b95a411a36 Add SPD support for onboard ThinkPad T480S RAM
Patchset 20 from:

https://review.coreboot.org/c/coreboot/+/83274/18..20

Updated to that. A bunch of changes I made locally have been
copied here, thus removed from lbmk.

The previous setup in lbmk was to have only the DIMM slot work,
on the ThinkPad T480S, without setting up SPD for the onboard RAM>

Mate Kukri reverse engineered the scheme by which the SPDs are
chosen at boot, based on the wiring of the board. This should
just about match the way Lenovo did it in their firmware.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 16:32:15 +00:00
Leah Rowe 046529abd9 Disable m2 caddy hotplug on T480S
This fixes an error where nvme disappears and gets renamed
on s3 resume. Mate Kukri told me to test that and it worked.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 11:29:19 +00:00
Leah Rowe 9dc3c86ae3 vendor.sh: Remove T480 VGA ROM download handling
Libreboot's binary blob reduction policy is crystal clear:

If a blob can be avoided, it must be avoided.

The ThinkPad T480 was using Intel's VGA ROM for graphics
initialisation very briefly, before Mate fixed libgfxinit.

Since libgfxinit is fixed, the Intel VGA ROM is obsolete,
so we should not be handling this at all.

Similarly, the Nvidia ROM handling has been removed, because
Mate is hard-disabling that in the coreboot code anyway, since
the Nvidia dGPU didn't work when tested anyway.

Even if it did, Libreboot's blob policy makes it clear
that Intel graphics with native init from coreboot is to
be the preferred option.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 06:12:59 +00:00
Leah Rowe 33efe45b14 Enable legacy 8254 timer on ThinkPad T480
I also enabled this on T480S, because otherwise SeaBIOS hung.

Enabling it shouldn't cause any harm on the T480, though Mate
did say that his machine seemed to work with my setup.

However, I believe that was when I gave him the ones that lbmk
built with the VGA ROM. Now it builds with libgfxinit, because
Mate was able to fix libgfxinit on this machine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 06:09:03 +00:00
Leah Rowe cde9594aab libgfxinit on Thinkpad T480
was previously using the VGA ROM.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 06:05:41 +00:00
Leah Rowe c1b7326972 NEW MAINBOARD: ThinkPad T480S
Added t480s delta to deguard, for MFS config.

Updated coreboot/next to latest t480 patch set,
which includes t480s. This porting was done by
Mate Kukri.

also includes experimental t480s support

Also added a data.vbt file (not in the gerrit patch)
for the T480s.

I had to turn on 8254 legacy timer on t480s, otherwise
SeaBIOS would hang. Same issue I saw on OptiPlex 3050 Micro.

Minor issue:

On S3 resume, nvme0n1 for example got renamed to nvme0n2.
This caused a crash if running Linux from the nvme. I confirmed
this via live USB distro. So this port will need some tweaking
before it can be considered stable.

Also uses libgfxinit, which Mate recently fixed. I'm
going to enable libgfxinit on regular T480 next.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-02 05:57:34 +00:00
Leah Rowe 264928c6cd NEW MAINBOARD: ThinkPad T480
This uses the excellent deguard utility, written by
the excellent Mate Kukri.

A few bugs but it mostly works. Documentation to come
shortly, in lbwww.git.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-01 23:51:20 +00:00
Leah Rowe 597b45fdbd Merge pull request 'Update U-Boot to v2024.10' (#253) from alpernebbi/lbmk:uboot-v2024.10 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/253
2024-12-01 17:03:08 +00:00
Leah Rowe 28d8dc93a5 vendor.sh: Use the new deguard for 3050micro
I'm adding ThinkPad T480 support next, which requires
the new revision of deguard. Mate Kukri changed the way
deguard is used, in a rewrite of the project, so lbmk
has to change too.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-12-01 01:44:45 +00:00
Alper Nebi Yasak 3dd77b33a7 u-boot: Enable USB with a preboot command
We need to initialize the USB subsystem before we can use USB devices
like keyboards and external disks, by running `usb start`. Use the
PREBOOT config option to run the necessary command before U-Boot tries
to automatically boot anything. It's already enabled for boards other
than gru_kevin and gru_bob, so just update those two configs.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-11-30 22:31:16 +03:00
Alper Nebi Yasak ba772eb6ac u-boot: Update ARM64 boards to v2024.10
Set default U-Boot revision to v2024.10 and rebase patches on top of
that. The video subsystem now has switched to using the 'cyclic'
mechanism, so the code around one of the video patches changed a bit.

x86 boards were already switched to v2024.10. Update U-Boot for the
remaining ARM64 boards as usual:

- Turn old configs into defconfigs (./update trees -s u-boot)
- Save the diff from old upstream defconfig (diffconfig $theirs $ours)
- Update U-Boot revision, rebase patches, and clean old trees
- Prepare new U-Boot tree (./update trees -f u-boot)
- Review the diffconfigs to see if any options were renamed upstream
- Copy over the new upstream defconfigs and apply earlier diff
- Turn new defconfigs into configs (./update trees -l u-boot)

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-11-30 22:24:29 +03:00
Leah Rowe 7f6e47d27c trees: reset PATH per-target
Otherwise, if PATH was set before, it will be re-used
again in the next pass. We previously unset CROSS_COMPILE
to avoid using the wrong cross-compiler when switching to
another target within a multi-tree project such as U-Boot.

Well, PATH was also being set, to use coreboot xgcc first.
This is fine, but the next target may not use the same one.

This patch solves a similar problem to the following patch
which was mentioned above:

commit 637c0a1521
Author: Leah Rowe <leah@libreboot.org>
Date:   Tue Nov 19 02:52:28 2024 +0000

    trees: unset CROSS_COMPILE per target

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-29 00:39:35 +00:00
Leah Rowe f4b6aeea28 rom.sh: Add U-Boot before SeaBIOS and GRUB (x86)
Since U-Boot must be inserted at a specific offset, it's
theoretically possible that other files might overlap, but
cbfstool will work around wherever U-Boot was inserted if
it was inserted first; we don't use specific offsets for
the other files.

This is technically a preventative bug fix, but it fixes
a bug that would probably never occur in practise.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-27 02:41:39 +00:00
Leah Rowe 7014b303f9 rom.sh: Remove unnecessary shebang
This is not a main script, and should not be treated as such;
it must never be directly executed by the user.

This script was only ever used inside other scripts, so the
shebang didn't seem to do much at all, but it shouldn't be
there anyway.

Remove it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-26 23:28:42 +00:00
Leah Rowe a3accd39a0 Merge pull request 'config/deps/fedora41: Add openssl-devel-engine to dependency list' (#251) from mkukri/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/251
2024-11-24 15:17:48 +00:00
Mate Kukri 98c5e43628 config/deps/fedora41: Add openssl-devel-engine to dependency list
openssl-devel was split up in Fedora 41, and this package is required to build libreboot
on Fedora 41.

This was reported by "tweezers" on #libreboot.

Signed-off-by: Mate Kukri <km@mkukri.xyz>
2024-11-24 11:59:46 +00:00
Leah Rowe ef7db20546 e6400nvidia: Disable U-Boot
This uses the "normal" config. Previous changes prevent
U-Boot images being built for this anyway, but it does
yield a warning message.

Remove the warning at the source.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-21 18:35:59 +00:00
Leah Rowe eea9fc4097 rom.sh: unset displaymode on normal initmode
Otherwise, you get "normal_normal" in the image name.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-21 18:34:08 +00:00
Leah Rowe f312e6026f rom.sh: Don't build U-Boot on normal initmode
The "normal" mode in lbmk is where no built-in GPU exists,
or no libgfxinit is used, and SeaBIOS is the first payload,
and SeaBIOS executes VGA ROMs (can't know if it'll start
in VESA or text mode).

U-Boot needs a VESA framebuffer or native coreboot
framebuffer to work correctly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-21 18:24:50 +00:00
Leah Rowe 587d588fe4 rom.sh: Don't build txtmode U-Boot images
U-Boot needs a VESA framebuffer or native coreboot
framebuffer to work properly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-21 18:07:33 +00:00
Leah Rowe 7d1fd1cc6a rom.sh: Support SeaUBoot for 64-bit x86 U-Boot
Same concept as SeaGRUB, but for U-Boot. SeaBIOS starts, but
has a bootorder file loading U-Boot first, from flash.

You can interrupt it with the ESC menu, to boot something else
in SeaBIOS, including GRUB.

With this, we can effectively provide extremely user-friendly
UEFI-first setups in Libreboot.

Take that, edk2!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-21 12:29:05 +00:00
Leah Rowe 02e66ae01a U-Boot x86: Avoid clearing the VESA display
This is a patch from Simon Glass. U-Boot clears the display
when it starts up, but was asking the VESA driver to do the
same, needlessly; this patch avoids the latter.

A further patch is also included, which provides a better
message when jumping into long mode on the SPL (64-bit) target,
dumping it on the serial console instead of using printf.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 15:44:35 +00:00
Leah Rowe 32dced8cd8 disable U-Boot for now on HP EliteBook 8560w
dGPU only, and starts in text mode.

will have to test with vesa framebuffer later on.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 13:24:14 +00:00
Leah Rowe a68b468964 enable serial debug on HP EliteBook 8460p
there's a uart on the docking station

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 12:07:18 +00:00
Leah Rowe b79bd736e7 enable serial debug on hp elite 8200 sff
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 12:05:37 +00:00
Leah Rowe b109617752 enable the serial console on thinkpad x60
it has one on the docking station

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 11:31:37 +00:00
Leah Rowe 0c7fb21a06 enable the serial console on thinkpad t60
it has one on the docking station

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 11:29:53 +00:00
Leah Rowe eb14a176bc Only boot 32-bit u-boot from grub, 64 from seabios
For some reason, 32-bit U-Boot only works when executed from
GRUB, but not SeaBIOS; 64-bit U-Boot only works from SeaBIOS!

This will have to be investigated. Standalone U-Boot, where
U-Boot is the primary payload, has not yet been tested in
Libreboot, and will not be provided for some time due to
stability concerns. More testing is needed!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-20 01:19:27 +00:00
Leah Rowe 279e69172f make the u-boot grub menuentry more useful
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 23:26:28 +00:00
Leah Rowe fdbdf0449b Re-enable U-Boot x86 on real mainboards
The previous stability issues were resolved, thanks to
the previous revision which added a fix courtesy Simon Glass.

This reverts commit eba73c778a.
2024-11-19 22:48:21 +00:00
Leah Rowe b549d1e5f3 u-boot x86 serial/ns16550: disable UART as needed
U-Boot was hanging on hardware, but not Qemu. This is because on
the machines tested, namely the X200 and E6230 laptops supported
in Libreboot, the UART was disabled from coreboot.

This U-Boot patch from Simon Glass works around the issue by
silently disabling the UART when it isn't there. Instead,
output is sent to the display and U-Boot no longer hangs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 22:46:29 +00:00
Leah Rowe eba73c778a Disable U-Boot x86 except on Qemu
It's really buggy on hardware. Disable for now.

I've contacted Simon Glass on IRC, asking about hardware.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 16:22:14 +00:00
Leah Rowe 4bc6ca545e fix U-Boot hotkey mention in grub.cfg
it's u, not b, for the U-Boot hotkey

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 10:56:54 +00:00
Leah Rowe 6d629a8496 Update x86 U-Boot to v2024.10 (was v2024.07)
It's a new experimental payload in Libreboot, so we may aswell
start with the very latest release of U-Boot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 09:52:40 +00:00
Leah Rowe 709bbebdcf grub.cfg: mark U-Boot as experimental in the menu
it's important that we maintain realistic expectations.
x86 u-boot is not yet fully stable, so mark it as such.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 04:55:46 +00:00
Leah Rowe 637c0a1521 trees: unset CROSS_COMPILE per target
When building a coreboot image, if they enable the
x86 U-Boot payloads, sometimes what happens is you
have CROSS_COMPILE set, for i386-elf, but then it's
still set to that when later building 64-bit U-Boot,
which needs x86_64-elf.

We currently rely on hostcc to build U-Boot.

To mitigate this, unset CROSS_COMPILE in the main
loop of the trees script, for building project targets.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 02:52:28 +00:00
Leah Rowe f13819386b Enable x86 U-Boot payload on every x86 board
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 02:28:18 +00:00
Leah Rowe 747b6514ea Add U-Boot x86_64 payload
Currently seems to stall when booted from the GRUB
payload, but works when booted from the SeaBIOS menu.

I also tested it as a standalone payload and it seems
to boot. Will test on hardware next, and start adding
it to more mainboards.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-19 02:04:50 +00:00
Leah Rowe 3bf3ef557e add arm-none-eabi-gcc-cs-c++ to fedora dependency
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-09 15:36:36 +00:00
Leah Rowe 2deab8572d clean up the coreboot submodules
also bring the coreboot/next modules in line with
the recent merge that did away with coreboot/dell7

the submodules for coreboot/haswell were still there,
and have now been deleted; the haswell tree was used
for the NRI patches, which were moved to /default some
time ago

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-07 00:26:59 +00:00
Leah Rowe 9abddb82b9 Bump coreboot/next and merge coreboot/dell7
coreboot/dell7 is now part of coreboot/next, which in turn
has been updated, to accomodate 3050 micro patchset 18:

https://review.coreboot.org/c/coreboot/+/82053/18

It incorporates my Verb/VBT patches, which are therefore
no longer included separately.

Mate has fixed the USB config; see diff for details.
The configuration of USB ports was wrong, before.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-06 22:32:45 +00:00
Leah Rowe 8c4cacba27 data/coreboot: add missing variable
payload_uboot_i386 must be defined here, or the
build will fail for coreboot targets

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-05 19:33:49 +00:00
Leah Rowe cdd8cb9086 coreboot/default: remove unnecessary module
The fsp module is unnecessary on coreboot/default, and
therefore constitutes a waste of disk space.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-04 05:44:39 +00:00
Leah Rowe c0017c7357 Experimental U-Boot payload (32-bit dtb, U-Boot)
NOTE: Support added for xarch target x86_64-elf,
but U-Boot failed to build with this error:

OBJCOPY lib/efi_loader/helloworld.efi
x86_64-elf-objcopy: lib/efi_loader/helloworld_efi.so: invalid bfd target
make[2]: *** [scripts/Makefile.lib:476: lib/efi_loader/helloworld.efi] Error 1

Since I'm building U-Boot for x86_64 *on* an x86-64
host, and since that is currently the recommended type
of machine to use for lbmk development, and since the
other x86 payloads currently don't cross compile anyway,
this is an acceptable compromise for now. This is because
at present, I'm not making U-Boot the primary payload on x86,
instead preferring to chain it from GRUB and SeaBIOS.

The target.cfg file for x86 u-boot shows xarch/xtree commented.
Uncomment these to compile on crossgcc instead of hostcc.

I mention 64-bit because I initially did this first, but decided
to do 32-bit first. I'll work on the 64-bit one next (SPL).

It's only enabled in QEMU for now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-03 09:22:52 +00:00
Leah Rowe 14b4838d49 coreboot/default: Re-base all patches
There were a lot of unnecessary patches, such as the VRAM
patches; as Nicholas Chin has explained to me, the drivers
for these machines will just allocate what RAM they want
anyway, so in a lot of cases the extra allocated Video RAM
simply reduces the total amount of memory for other uses.

In general, we have a lot of patches that have existed for
years. A much more aggressive sweep will be done in the next
major audit, especially when the revisions are updated again.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-11-01 15:59:30 +00:00
Leah Rowe 67c92889a8 NEW MAINBOARD: Dell OptiPlex 780 USFF
Thanks go to Nicholas Chin and Lorenzo Aloe for working on
and testing this code. Based on the 780 MT port.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-31 05:30:10 +00:00
Leah Rowe 38006cb2bc coreboot/dell3050micro: enable coffeelake CPUs
pin mod needed (soldering) but according to mate, you
can use some coffeelake CPUs on these machines, despite
them being intel 7th gen. this includes 8-core chips.

this patch enables the software configuration in coreboot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-31 02:38:01 +00:00
Leah Rowe 97054498e9 NEW MAINBOARD: Dell OptiPlex 780 MT
Thanks go to Lorenzo Aloe and Nicholas Chin for working on
and testing this code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-28 05:03:17 +00:00
Leah Rowe f3170fb06e coreboot/dell7: add missing ifdtool nuke patch
This is for blanking the ME region on release builds.

This is required for lbmk when doing Libreboot releases,
on images that use an Intel ME region.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-28 01:16:25 +00:00
Leah Rowe 19795bf980 re-update seabios to latest revision
I reset it temporarily back to 1.16.3 when testing the
SeaBIOS hanging bug on 3050 micro, but the revision had
no effect; the bug was caused by a bad coreboot config

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 20:06:16 +00:00
Leah Rowe 9bdec645a3 3050micro: Re-enable SeaGRUB
Remove what is now unnecessary bloat, for ensuring that
GRUB is the primary payload; SeaGRUB is the only preference,
as per lbmk design.

The SeaBIOS hanging issue was fixed, so SeaGRUB is OK now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 19:32:36 +00:00
Leah Rowe 6c78942290 Merge pull request 'config/coreboot/default: Update MEC5035 patches' (#244) from nic3-14159/lbmk:mec5035-updates into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/244
2024-10-27 18:44:41 +00:00
Leah Rowe 237fa1e3c1 3050micro: don't set static option table
Again, I'm adapting the config to be as close to the
coreboot one as possible. I compiled directly from coreboot
earlier, and got SeaBIOS to work on my 3050.

I'm matching the setup as closely as possible. Once it works,
I can use that in a Libreboot release but then debug why the
old config wasn't working.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 18:35:29 +00:00
Leah Rowe d1743d1f64 3050micro: Use alt century byte +legacy 8254 timer
I'm eliminating as many differences as possible between lbmk's
setup, and the setup that is default when simply building from
the gerrit patch, directly in coreboot, by just picking the
mainboard; in this way, coreboot picks SeaBIOS as payload. I
already changed the SeaBIOS configs, in the previous patch.

Upon testing, this seems to have fixed the SeaBIOS hanging. I
need to have both of these options selected, or SeaBIOS hangs
just after it says "Press ESC" for the boot menu.

With this config change, SeaBIOS does not hang; instead, it shows
the list of devices as normal, and boots your machine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 18:34:43 +00:00
Leah Rowe c56f698713 Use SeaBIOS 1.16.3 and enable debugging
This diff matches the setup currently used in coreboot.

I'm eliminating as many differences as possible, while
I test the SeaBIOS hanging issue on Dell Optiplex 3050 Micro.

The actual SeaBIOS configs have also been modified, to match
the coreboot config.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 16:07:56 +00:00
Nicholas Chin b257662e55 config/coreboot/default: Update MEC5035 patches
- Update the MEC5035 S3 patches to the versions that were sent upstream
  to prevent conflicts with subsequent patches for that EC.
- Update the patch that enables the S3 SMI handler in mainboard code so
  that all Latitudes use the handler.
- Add a new patch that tells the EC to route power button events to the
  host so that the OS can decide what to do. Without it, the EC powers
  off the system without letting the OS cleanly shut down.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-10-26 20:55:18 -06:00
Leah Rowe d8ac9d53b6 Switch Dell 3050 Micro to newer coreboot revision
Specifically, use the same revision that Mate used in patchset 15.

This will ensure that any issues are *not* caused by the coreboot
revision; this is being done, because the old coreboot revision was
from July, but patchset 15 from Mate is based on a September revision
of coreboot.

I've been eliminating as many variables as possible, trying to fix
SeaBIOS payload on this machine, because it hangs in Libreboot, but
not when building from gerrit directly, which means the coreboot
revision may be a factor (since I'm using his patches on an older
revision so upstream might have made some changes since then that
the port relies on).

For this, a new coreboot tree is used, called "dell7", referring to
the fact that Kabylake is Intel's 7th generation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-27 01:15:24 +00:00
Leah Rowe 99a88ebfa2 Update dell 3050 patch to patch 15 (pwm fix)
Use patchset 15 instead of 14:
config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch

Rebase the verb patch; patchset 15 modified the Makefile:
config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch

We were using patchset 14 for the 3050 micro:
https://review.coreboot.org/c/coreboot/+/82053/14

Now we use patchset 15:
https://review.coreboot.org/c/coreboot/+/82053/15

Without this patch, the fans are always on a low setting, on
the Dell OptiPlex 3050 Micro, even under stress conditions. With
this patch, the fans change speed according to CPU temperature.

I had to rebase my verb patch, because Mate modified the Makefile
to add his sch5555 handler, on the same line where I add hda_verb.

Mate tells me he will merge my verb and vbt patches into a further
patchset later on. For now, I've simply rebased these patches on
top of Mate's newer work; I've told him he can use them in his port.

I'm probably going to now issue a new revision ROM image for
Libreboot 20241008, so that users can get this fix sooner.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-26 06:26:25 +01:00
Leah Rowe 3f63c6d12f rom.sh: remove unnecessary logic from copyps1bios
the .git directory never exists anyway, when doing a release,
so the purpose this is intended is defeated by lbmk's design.

individual headers say "pcsx-redux team" as copyright anyway,
and the code for generating that COPYING file, with MIT license
and correct years (matching the entire source code for the
open bios) remains correct.

a mitigation instead of this patch might be to maintain a hardcoded
list of authors, and manually update it over time, but this is not
required. however, it may be good practise for upstream to maintain
such a file. perhaps i should contact them?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-20 00:13:35 +01:00
Leah Rowe 56495c61e6 use redundant mirrors for recent utils imports
i mirrored riku's utils int, mxmdump and gpio-scripts
to the codeberg and disroot libreboot sites.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:48:32 +01:00
Leah Rowe 38d37a340f remove end slashes on repos in config/git/
Due to quirks in how caching works in lbmk, this may be
error-prone. I'll properly address it in the next audit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:37:05 +01:00
Leah Rowe 6eb2e98c0f import Riku's int tool
Riku used this for debugging, when adding the MXM support
to the HP EliteBook 8560w port. It will be useful for other
work that I have planned, so I'm archiving this too!

Riku has a lot of useful code, that I meant to import ages ago.
Once I'm done importing these in lbmk, I'll add backup repos.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:33:48 +01:00
Leah Rowe 441d21dc13 import Riku's gpio-scripts
Based on hell's code, but parses inteltool logs.

This will be useful for ports that I have planned, so
I'd like this to be included with Libreboot releases.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:30:51 +01:00
Leah Rowe e8957b0833 import Riku's mxmdump utility
Used to dump MXM config for a given mainboard. We used this
for the HP EliteBook 8560w.

I meant to import this via config/git/ ages ago.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:28:18 +01:00
Leah Rowe 91a26ec361 bump seabios
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-17 23:22:44 +01:00
Leah Rowe 34f851742e vendor.sh: Don't use x_ for image MAC address mod
The path might contain spaces and such, which breaks when
using the x_ prefix.

Call err instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-16 15:48:43 +01:00
Leah Rowe c7a3a607f3 bump flashprog revision to d128a0a
This brings in the following important fix:

commit d128a0ae87086b37c0e5d7a8d934bcdee173402f
Author: Nicholas Chin <nic.c3.14@gmail.com>
Date:   Fri Sep 27 22:57:22 2024 -0600

    flashchips: Remove unsupported erase blocks for Winbond W25X{16,32,64}

    This family of chips does not support the 0x52 (32 KiB block erase) and
    0x60 (chip erase) opcodes according to their datasheet.

The full list of changes this brings in is as follows:

* d128a0a flashchips: Remove unsupported erase blocks for Winbond W25X{16,32,64}
* c6a924a Don't mention writing when erasing only (-E)
* dac4239 ch347_spi: Add 'spimode' parameter
* 56d236b chipset_enable: Add some newer AMD code names
* 3b9f152 chipset_enable: Probe AMD SPIBAR first and bail on ff
* 522160f meson: Add ft4222_spi

Nicholas Chin's patch fixes a bug on GM45 ThinkPads, where WX25
ICs (Winbond) could be read, but writes would fail in certain
cases because flashchips.c provided incorrect block erase commands.

This is unrelated to the --workaround-mx patch, for Macronix ICs.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-14 16:26:01 +01:00
Leah Rowe 3b92b7b723 vendor.sh: Handle error status on RUNME.sh
The deguard utility is executed within a subshell, and
the subshell does not handle error status. This patch
fixes that, so that the main shell also exits non-zero.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-14 01:15:44 +01:00
Leah Rowe 147e034341 dependencies/fedora40: add python3-devel
I was build-testing gru_bob on an arm64 host, and got a
build error when compiling U-Boot.

Python.h missing - installing python3-devel fixes it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-13 06:31:36 +01:00
Leah Rowe c1ff438c90 Libreboot 20241008 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-08 19:50:44 +01:00
Leah Rowe 6b40616a40 build: actually build pcsx-redux bios on release
I added support earlier, on rom.sh, but the main build script
specifically defines which projects are to be compiled. I've
modified it so that pcsx-redux (just the BIOS part) will also
be compiled.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-08 16:16:30 +01:00
Leah Rowe d845791d6f rom.sh: support making pcsx-redux bios release
I also checked the copyright declarations in the
directory src/mips/openbios where the PCSX-Redux BIOS
is, gleaning all the copyright years: 2019-2024 at this
time.

The years will be updated as and when PCSX-Redux is
updated in lbmk. Their BIOS is under MIT so I made lbmk
generate an appropriate COPYING file alongside the binary,
containing:

Copyright (c) 2019-2024 PCSX-Redux authors

Along with the actual text of the MIT license. With all
of this, the PCSX-Redux BIOS can now be included in
Libreboot releases.

No actual tarball is created. The release script in lbmk
simply copies the bin/ directory to ../roms

I'm leaving the PCSX-Redux BIOS release uncompressed,
because, and this will sound patronising because that is
my precise intention: Windows users don't know how to do
anything. If I provide a tarball to Windows users, they
won't know what to do. Libreboot releases always go on rsync
mirrors, which also have HTTP servers with indexing enabled,
for browsing release files.

I mention Windows users, because most people who use the PCSX
Redux BIOS will probably use it on a PlayStation emulator, and
most emulator users are on Windows. I can't really be bothered
to provide it as a .zip archive, and it's only 512kb, so just
provide it uncompressed in Libreboot releases!

Releases were already possible under this scheme, so this
patch really just adds the COPYING file. It's simply a courtesy
to the PCSX-Redux developers, providing proper credit to them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-08 13:27:08 +01:00
Leah Rowe 09a8f2ea83 coreboot/dell3050micro: Add data.vbt file
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-07 00:32:31 +01:00
Leah Rowe 217aa1735a Add verb patch for Dell OptiPlex 3050 Micro
Thanks go to Nicholas Chin for helping me with this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-06 22:37:19 +01:00
Leah Rowe f4de640e45 rom.sh: disable seabios-as-primary if grub is main
on 3050micro, we disable seabios as a primary payload,
making grub a pribary payload instead.

the way it worked, the roms were still named seagrub
and the seabios rom would be compiled, but with the wrong
path, so seabios wouldn't be executed; seabios would hang
anyway, on this board.

instead, engineer it in such a way as to disable seabios_
images on this board. also, rename seagrub_ to grub_.

i normally only permit seagrub, and not grub, but i make an
exception for 3050micro because we know grub works, but seabios
currently hangs on this board (which means no bsd).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-06 10:31:36 +01:00
Leah Rowe c99dced5b1 dell3050micro: make GRUB the primary payload
SeaBIOS is known to hang on this board. It is being investigated.

Add two variable options for target.cfg files:

* seabiosname
* grubname

This string defines where it would be located in CBFS.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-06 09:22:21 +01:00
Leah Rowe ed8178e83b disable dram clear on dell 3050 micro
otherwise it takes ages to boot

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-05 19:04:57 +01:00
Leah Rowe d2939231ac 3050micro: disable TPM to mitagate seabios hanging
SeaBIOS hangs without this. Thanks go to Mate Kukri who
suggested this workaround.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-05 03:59:14 +01:00
Leah Rowe 809e1d97ab fix 3050 config (./mk -u coreboot)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-05 03:57:06 +01:00
Leah Rowe 44473d6832 git.sh: fix error with cache re-download
in some cases, on a fresh clone, the cached repo already
exists but lbmk tries to download it again. work around
this by checking that the directory exists; it's in the
main if statement, so that the "else" still applies. as
a result, the fallback to a live repo would un-fall back
to doing git-pull if the cached directory exists exists.

if it doesn't seem to make sense, it's because it doesn't.
this whole function needs to be rewritten better.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-05 03:52:50 +01:00
Leah Rowe c3ef0a8639 Add config for Dell OptiPlex 3050 Micro
This is using Mate Kukri's port, which was added in
previous lbmk revisions. I've added an IFD that sets
the HAP bit, and unlocks regions as standard.

vcfg is set to 3050micro, which defines downloading
of the MEv11 image and it will run deguard automatically.

I made a small adjustment to vendor.sh, because the hotpatch
logic for deguard uses -C in git, and when doing that, the
specified directory path is relative to that Git repository;
the .patch path has been adjusted accordingly.

Also add 3rdparty/fsp to coreboot/default modules.

This board requires the ifdtool option: -p sklkbl

The -p option tells flashrom what quirks are present in a
given IFD. We don't normally need this on other Libreboot
targets that we currently support. The -p option was needed
for creating this modified IFD, and it is therefore needed in
the inject script. Therefore, an "IFD_platform" option is
specified in a given board's target.cfg file. If this is set,
another variable is set that makes -p be used.

In this case, 3050's target.cfg says:

IFD_platform="sklkbl"

This option enables quirks for skylake/kabylake descriptors,
as required when using ifdtool.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-05 03:32:06 +01:00
Leah Rowe 23e64192ed Add Dell OptiPlex 7010/9010 SFF support
Pretty much just copied the T1650 directory in config/,
then changed the board to 9010 SFF in menuconfig.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-10-04 22:24:57 +01:00
Leah Rowe 02e76d09c1 add swig to fedora dependencies
needed when compiling u-boot

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-30 09:35:46 +01:00
Leah Rowe a42fe72c93 Merge pull request 'config/coreboot: Add Dell Latitude E4300' (#236) from nic3-14159/lbmk:e4300 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/236
2024-09-30 03:11:04 +00:00
Nicholas Chin e0e9c6ab3e config/coreboot: Add Dell Latitude E4300
Add patches to convert the E6400 port into a GM45 Latitude variant and
add the E4300 as another variant, and create a config for the E4300.
Tested on my E6400 and E4300.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-09-27 20:39:27 -06:00
Leah Rowe ff9c250a3e Add Sony PlayStation support to Libreboot
I also added a "cleanargs" argument, similar to the makeargs
argument, to work around a build error.

This builds the PCSX-Redux PS1 BIOS. They reverse engineered
the Sony PS1 BIOS and wrote a free one under MIT license.

Run this:

./mk -b pcsx-redux

The file will appear: bin/playstation/openbios.bin

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-26 00:35:18 +01:00
Leah Rowe 2b0fe39acb config/git: Import pcsx-redux
We don't need the entire emulator, but we will be using
a specific part: src/mips/openbios

third_party/uC-sdk submodule is included, because it
contains the necessary header files when building open bios.

I will be adding Sony Playstation support to Libreboot,
alongside a new emulator project to be announced soon.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-25 23:21:15 +01:00
Leah Rowe c723ce56d2 coreboot/default: Import mkukri's 3050 micro port
Dell OptiPlex 3050 Micro

I ran ./mk -u coreboot, to update existing configs
after merging. Actualy IFD and coreboot configs will
be done in the next revision. I've already added logic
for handling deguard, in preparation for this.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-24 20:31:12 +01:00
Leah Rowe e7c0109f5d Add deguard logic for Dell OptiPlex 3050 Micro
Copy the downloaded deguard source code into appdir,
and patch it to run as part of lbmk, instead of
standalone. The archived one in src/ is not directly
used; instead, the hotpatched version is used.

This is because the standalone version already has
download logic for the .zip file, but we already
cache that file in cache/ and use that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-24 16:53:48 +01:00
Leah Rowe 0266a48913 Add Mate Kukri's deguard utility
This program disables the Intel Boot Guard on Dell
OptiPlex 3050 Micro, via Intel ME modification.

Using this hack, you can run unsigned code on the ME.
Mate disabled BootGuard this way.

This will be used to add Dell OptiPlex 3050 Micro
support in Libreboot.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-09-24 13:41:01 +01:00
Leah Rowe 242b79aa25 Revert "vendor.sh: print extract errors to /dev/null"
This reverts commit 72fa467cb7.
2024-09-05 19:46:37 +01:00
Leah Rowe 72fa467cb7 vendor.sh: print extract errors to /dev/null
the output isn't really super critical, because it pertains
to files that would just result in a coreboot build error
if they didn't extract, which would still allow me to know
if a given extract function failed.

however, the extract function shows a lot of error output
because it literally bruteforces various extract methods,
when dealing with vendor files.

mitigate this by just printing the errors to /dev/null. this
will prevent users from erroneously thinking that lbmk is
operating under error condition, when it isn't. we do sometimes
get questions about it on irc.

fewer questions on irc is better.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-31 01:17:57 +01:00
Leah Rowe 66755f73ca Merge pull request 'Add remaining SNB/IVB Latitude ports' (#217) from nic3-14159/lbmk:latitude-ports into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/217
2024-08-14 13:34:52 +00:00
Nicholas Chin 4702e568c3 config/coreboot: Fix INTEL_GMA_VBT_FILE in Latitude configs
Commit 3ee4cc9dde (fix typo in dell
latitude coreboot coreboot config) fixed a typo from ${VARIANT_DIR) to
$(CONFIG_VARIANT_DIR). While this does work, since CONFIG_VARIANT_DIR is
a valid variable, it is not technically correct, as the default VBT path
set by coreboot's Kconfig files uses $(VARIANT_DIR), which is the same
as CONFIG_VARIANT_DIR, but with quotes stripped out.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-13 22:28:05 -06:00
Nicholas Chin 73484d98ac config/coreboot: Add config for Dell Latitude E6230
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-13 21:55:09 -06:00
Nicholas Chin f51a9dee95 config/coreboot: Add config for Dell Latitude E6330
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-13 21:55:09 -06:00
Nicholas Chin 0240be1833 config/coreboot: Add config for Dell Latitude E6320
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-13 21:55:08 -06:00
Nicholas Chin 875e9cb255 config/coreboot: Add config for Dell Latitude E6220
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-08-13 21:55:08 -06:00
Leah Rowe 3f9d575ceb coreboot/x4x: fix build error
see relevant patch added in the diff

set the clock on x4x boards to 96MHz like on GM45

fixes the following build error on x4x boards:

hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config"
make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-12 02:23:12 +01:00
Leah Rowe 8ca56f96c1 coreboot/default: fix build issue with DDR2 fix
some of my DDR2 checks were unnecessary, as nicholas pointed
out on irc, because they were in places that only ran if
DDR2 memory was used anyway.

in another, valid place, I was checking the wrong variable for
knowing what memory type is used.

this patch fixes build errors in lbmk:

src/northbridge/intel/gm45/raminit.c: In function 'dram_program_timings':
src/northbridge/intel/gm45/raminit.c:1120:29: error: 'sysinfo' undeclared (first use in this function); did you mean 'sysinfo_t'?
 1120 |                         if (sysinfo->spd_type == DDR2)
      |                             ^~~~~~~
      |                             sysinfo_t
src/northbridge/intel/gm45/raminit.c:1120:29: note: each undeclared identifier is reported only once for each function it appears in
src/northbridge/intel/gm45/raminit.c: In function 'ddr2_odt_setup':
src/northbridge/intel/gm45/raminit.c:1291:21: error: 'sysinfo' undeclared (first use in this function); did you mean 'sysinfo_t'?
 1291 |                 if (sysinfo->spd_type == DDR2) {
      |                     ^~~~~~~
      |                     sysinfo_t
make: *** [Makefile:423: build/romstage/northbridge/intel/gm45/raminit.o] Error 1

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-11 23:09:25 +01:00
Leah Rowe 3ee4cc9dde fix typo in dell latitude coreboot coreboot config
these configs were otherwise correct, but i typo'd a variable
in them when manually rebasing the old configs, after switching
to nicholas's new ports implemented as variants, where the old
ones in lbmk were individual board ports for those same boards.

Signed-off-by: Leah Rowe <info@minifree.org>
2024-08-11 22:06:19 +01:00
Leah Rowe 7ab22503ab vendor.sh: use readkconfig on inject too
same as the last change. we must avoid use of make variables,
in sh specifically, when handling these configuration files.

Signed-off-by: Leah Rowe <info@minifree.org>
2024-08-11 22:06:18 +01:00
Leah Rowe d66f6e0d5b vendor.sh: don't load entire coreboot configs
instead, only grep for the entries required, such
as Intel ME paths.

some variables in coreboot configs use $(), which
is used in *make*, on the coreboot build system, and
there refers to variables.

here, we are sourcing them from sh, which treats this
as a mini subshell to run a command; for example
CONFIG_FOO would be executed, which is bad.

The current logic still theoretically has this problem,
with this patch, but the entries we scan from the configs
do not currently have variable names in the strings.

So: filter out just what we need, into a temporary config,
when scanning for vendor files in coreboot configs, and
use the temporary config.

This fixes a build error when compiling for e5520_6mb.

Signed-off-by: Leah Rowe <info@minifree.org>
2024-08-11 21:22:26 +01:00
Leah Rowe aae8cabe73 lib.sh: more verbose error in x_
part of the command was cut off in the output

Signed-off-by: Leah Rowe <info@minifree.org>
2024-08-11 21:22:23 +01:00
Leah Rowe 3a5a179379 flashprog: bump to 639d563 (2024-08-02)
The workaround-mx patch was rebased on one section in spi.c,
because that part in upstream added QPI support; in the newly
rebase mx patch, the workaround_mx behaviour is only
honoured if QPI (Quad SPI) is not in use.

Quad SPI is not used in practise, on the machines where this
workaround is intended (GM45 ThinkPads with Macronix chips).

This imports the following upstream changes:

* 639d563 README: Update flashprog.org URLs
* cbbd601 README: Update dependency list and Linux package names
* 79451f1 README: Rename "Packaging" -> "Source Packaging"
* 5b4695c README: Dial laptop warning down a little
* 7224085 udev rules: Add some more IDs
* 448457a ch347_spi: Add CH347F ID and loop over the entries
* e39549b ch347_spi: Search for compatible USB interface
* dfd0647 ich_descriptors: Refactor component density handling
* b2ad9fd ich_descriptors: Make use of SPI_ENGINE_PCH100 marker
* 140e22f chipset_enable: Make use of SPI_ENGINE_PCH100 marker
* 869f0e7 ichspi: Use `swseq_data' on ICH7 paths too
* eeee91b ichspi: Replace all switch/case on `ich_generation'
* ecba1d8 ichspi: Drop redundant bail-out cases in ich_set_bbar()
* e8babf4 ichspi: Use a single check to enable hwseq for PCH100+
* fda324b ichspi: Introduce SPI_ENGINE_PCH100 marker
* a1f6476 ichspi: Split ICH7 init out
* 3f75d44 ich_descriptors: Remove `Dual Output Fast Read' for newer gens
* 2862011 spi25: Try to set volatile quad-enable (QE) automatically
* 4ac536b spi25_statusreg: Allow to write (non-)volatile bits specifically
* b1d2bae dediprog: Fix and enable 4BA modes for SF600Plus-G2
* d0afeef dediprog: Disable 4BA modes for SF100 w/ protocol v2
* 1b1deda Implement QPI support
* a1b7f35 dediprog: Implement multi-i/o reads
* 008a44f dediprog: Split read/write command preparation by protocol
* 4760b6e spi25: Implement multi-i/o reads
* 0c9af0a spi25: Check quad-enable (QE) bit
* 930d421 spi25: Introduce generic spi_prepare_io()/spi_finish_io()
* 8d0f465 spi25: Extract 4BA preparations into new `spi25_prepare.c`
* 044c9dc Add FT4222H support
* fc7c13c linux_gpio2_spi: Implement multi i/o
* 5fc3154 bitbang_spi: Implement multi-i/o
* d16a911 bitbang_spi: Move API into its own header file
* 226bb87 flashchips: Add missing QE-bit definitions
* 4fa39c5 flashchips: Fill multi-i/o gaps in MX25U family
* 5f50999 flashchips: Fill multi-i/o gaps in MX25R family
* 46552c8 flashchips: Fill multi-i/o gaps in MX25L family
* 96786d0 flashchips: Fill quad-i/o gaps in XM25Q family
* a26a3c6 flashchips: Fill dual-i/o gaps in W25X family
* 2133f59 flashchips: Fill quad-i/o gaps in W25Q family
* 68573af flashchips: Split GD25Q127C and GD25Q128C
* 4da971f flashchips: Fill quad-i/o gaps in GD25*Q families
* f7e2d97 spi: Allow to define a quad-enable (QE) configuration bit
* 1412d9f spi: Rework FEATURE_QPI
* d518563 spi: Prepare for multi i/o and dummy bytes
* bd72a47 spi25_statusreg: support reading/writing configuration register
* 3d728e7 spi25_statusreg.c: support reading security register
* a358b14 flashchips: Split W25Q64.W -> W25Q64DW | W25Q64FW/W25Q64JW...Q
* 3127db1 manibuilder: Drop legacy flashrom tag collections
* 619d9c0 manibuilder: Use `test_build.sh'
* 6560bba manibuilder/almalinux: Install `diffutils' for new `test_build.sh'
* c7b549e test_build.sh: Compare output for -L of Make and Meson builds
* 72b30a0 test_build.sh: Don't try to run cross-compiled programs
* 3d2f212 test_build.sh: Allow to override Make and Meson commands
* 4eb9748 test_build.sh: Run tests for both Make and Meson builds
* 8279457 manibuilder: Add Alpine Linux 3.18 & 3.19 images
* 15e9b10 manibuilder/alpine: Install libjaylink-dev when available
* b8b3593 manibuilder: Add images for Fedora 38..40
* 7b05f09 manibuilder: Add images for Ubuntu 24.04 "Noble Numbat"
* 5e8b339 manibuilder/anita: Add NetBSD 10.0 i386 & amd64 images
* 61da8c7 manibuilder/anita: Export library path for libusb
* 39152af manibuilder: Set sourcearcade.org as default source
* 20073e7 Properly clear erase-block selection when bigger block is chosen
* 3824c8d ichspi: Allow all opcodes when the "opmenu" isn't locked
* 0d4354e flashchips: Add W25Q32JV-.M

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-11 18:18:21 +01:00
Leah Rowe c3f6dd03cc seabios/default: bump to ec0bc256 (2024-06-24)
This brings in a single change:

commit ec0bc256ae0ea08a32d3e854e329cfbc141f07ad
Author: Gerd Hoffmann <kraxel@redhat.com>
Date:   Mon Jun 24 10:44:09 2024 +0200

    limit address space used for pci devices, part two

This increases compatibility with i686 hosts, when allocating
memory for pci devices.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-11 16:43:22 +01:00
Leah Rowe 5b353a2290 grub/*: Bump to rev b53ec06a1 (2024-06-17)
Of note: upstream has made several improvements to memory
management, and several fixes to file systems.

User-friendly change to LUKS: if the passphrase input failed,
the user is prompted again for the correct passphrase, instead
of GRUB just failing. Similar to cryptsetup luksOpen behaviour
under Linux.

This pulls in the following changes from upstream (gnu.org):

* b53ec06a1 util/grub-mkrescue: Check existence of option arguments
* ab9fe8030 loader/efi/fdt: Add fdtdump command to access device tree
* 0cfec355d osdep/devmapper/getroot: Unmark 2 strings for translation
* f171122f0 loader/emu/linux: Fix determination of program name
* 828717833 disk/cryptodisk: Fix translatable message
* 9a2134a70 tests: Add test for ZFS zstd
* f96df6fe9 fs/zfs/zfs: Add support for zstd compression
* 55d35d628 kern/efi/mm: Detect calls to grub_efi_drop_alloc() with wrong page counts
* 61f1d0a61 kern/efi/mm: Change grub_efi_allocate_pages_real() to call semantically correct free function
* dc0a3a27d kern/efi/mm: Change grub_efi_mm_add_regions() to keep track of map allocation size
* b990df0be tests/util/grub-fs-tester: Fix EROFS label tests in grub-fs-tester
* d41c64811 tests: Switch to requiring exfatprogs from exfat-utils
* c1ee4da6a tests/util/grub-shell-luks-tester: Fix detached header test getting wrong header path
* c22e052fe tests/util/grub-shell: Add flexibility in QEMU firmware handling
* d2fc9dfcd tests/util/grub-shell: Use pflash instead of -bios to load UEFI firmware
* 88a7e64c2 tests/util/grub-shell: Print gdbinfo if on EFI platform
* b8d29f114 configure: Add Debian/Ubuntu DejaVu font path
* 13b315c0a term/ns8250-spcr: Add one more 16550 debug type
* 8abec8e15 loader/i386/multiboot_mbi: Fix handling of errors in broken aout-kludge
* d35ff2251 net/drivers/ieee1275/ofnet: Remove 200 ms timeout in get_card_packet() to reduce input latency
* 86df79275 commands/efi/tpm: Re-enable measurements on confidential computing platforms
* 0b4d01794 util/grub-mkpasswd-pbkdf2: Simplify the main function implementation
* fa36f6376 kern/ieee1275/init: Add IEEE 1275 Radix support for KVM on Power
* c464f1ec3 fs/zfs/zfs: Mark vdev_zaps_v2 and head_errlog as supported
* 2ffc14ba9 types: Add missing casts in compile-time byteswaps
* c6ac49120 font: Add Fedora-specific font paths
* 5e8989e4e fs/bfs: Fix improper grub_free() on non-existing files
* c806e4dc8 io/gzio: Properly init a table
* 243682baa io/gzio: Abort early when get_byte() reads nothing
* bb65d81fe cli_lock: Add build option to block command line interface
* 56e58828c fs/erofs: Add tests for EROFS in grub-fs-tester
* 9d603061a fs/erofs: Add support for the EROFS
* 1ba39de62 safemath: Add ALIGN_UP_OVF() which checks for an overflow
* d291449ba docs: Fix spelling mistakes
* 6cc2e4481 util/grub.d/00_header.in: Quote background image pathname in output
* f456add5f disk/lvm: GRUB fails to detect LVM volumes due to an incorrect computation of mda_end
* 386b59ddb disk/cryptodisk: Allow user to retry failed passphrase
* 99b4c0c38 disk/mdraid1x_linux: Prevent infinite recursion
* b272ed230 efi: Fix stack protector issues
* 6744840b1 build: Track explicit module dependencies in Makefile.core.def

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-11 16:13:31 +01:00
Leah Rowe 80c3f9395d coreboot/fam15h: only use this, for amd boards
it is identical to fam15h_rdimm, with _udimm now removed;
the latter had a patch that added certain behaviour only
intended for rdimm, but the patch in question breaks various
configurations.

raminit has always been unreliable on these boards. i'd rather
simplify it all, in lbmk. i'll probably update this to the dasharo
tree later on, specificalyl for kgpe-d16

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-10 18:24:31 +01:00
Leah Rowe 0f7c0aa1c5 coreboot/default: re-merge coreboot/i945
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-10 17:53:10 +01:00
Leah Rowe 877f5d6aeb coreboot/default: merge coreboot/haswell
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-10 14:48:01 +01:00
Leah Rowe a15347ef1e coreboot/dell: merge into coreboot/default
The libgfxinit patch and other patches e.g. DDR2 fix, are
now provided in coreboot/default. The Latitude E6400 is now
using the newer coreboot revision from late July 2024.

Some other configs had to change because of this, relating to
the new way that Nicholas handles timing on LVDS displays
with the E6400 port; a default 96MHz clock is still used for
pixel reference clock, overridden with a value of 100MHz on
other GM45 machines, where 96MHz was previously hardcoded.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-09 20:55:42 +01:00
Leah Rowe dbe24b039d coreboot/default: Update to 97bc693ab (2024-07-29)
Several patches are now merged upstream and no longer needed
in lbmk, such as the HP EliteBook 8560w patch, and related
patches. Some patches were changed, for example the Dell Latitude
ivb/snb laptops are now variants in coreboot, instead of being
individual ports; now they re-use the same base code.

This this, the corresponding files under config/submodules
have changed, for things like 3rdparty submodules e.g. libgfxinit,
and tarballs e.g. crossgcc.

This is long overdue, and will enable more boards to be added.
This newer revision will be used in the next release, and some
follow-up patches will merge these trees into default:

* coreboot/haswell
* coreboot/dell

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-08-09 20:50:37 +01:00
Leah Rowe 1b55fc790c fix hp8200sff_4mb ifd file (pd region)
see bug report:

https://codeberg.org/libreboot/lbmk/issues/228

The layout specified incorrect boundaries for the pd region.
With this change, it should flash and boot reliably.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-28 18:24:12 +01:00
Leah Rowe 490a94d7bc uefitool: Only define ACCESSPERMS on *nix
I re-read the modified code, and it has defines in place
for building on Windows; I was defining ACCESSPERMS
universally, but it should only be defined for non-Windows
systems, which the context in this code means Linux/BSD.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-28 16:38:48 +01:00
Leah Rowe a78eaac883 uefitool: Add patch working around musl libc issue
musl libc is very conservative in what it implements,
preferring a very "pure" libc implementation. this means
that it lacks many of the niceties found in others like
the GNU C Library; the latter implements many BSD libc
extensions, for example.

ACCESSPERMS is a #define in BSD libc that does:
S_IRWXU | S_IRWXG | S_IRWXO

Essentially, it provides a bitwise OR providing chmod 0777,
which can be used as shorthand in calls to functions such
as mkdir() available in all libc implementations.

In the case of uefitool, this define is indeed used on mkdir.
Conditionally re-define ACCESSPERMS, if undefined, so that musl
libc can be used when building uefitool.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-28 16:09:35 +01:00
Leah Rowe 59894ed555 lib.sh: new function mk() to handle trees in bulk
single-tree projects cannot be handled in bulk, e.g.
./mk -f project1 project2 project3

that is still the case, from the shell, but internally
it is now possible:
mk -f project1 project2 project3

mk() is a function that simply handles the given flag,
and all projects specified.

it does not handle cases without argument, for example
you cannot do:
mk -f

arguments must be provided. it can be used internally,
to simplify cases where multiple single-tree projects
must be handled, but *also* allows multi-tree projects
to be specified, without being able to actually handle
trees within that multi-tree project; so for example,
you can only specify coreboot, and then it would run
on every coreboot tree.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-28 13:35:31 +01:00
Leah Rowe 7fa6052de0 general code cleanup in the build system
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-26 15:49:49 +01:00
Leah Rowe 3bd290f6a6 rom.sh: don't dry-run mkcoreboottar
same as the last change. make the main function a wrapper
that dry-runs the real function.

if the "dry" variable is blank, it executes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 23:46:53 +01:00
Leah Rowe a91751a86b rom.sh: don't run mkcorebootbin on trees -d
don't let it execute during dry builds

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 23:39:36 +01:00
Leah Rowe 38b65af5b5 support ./mk in place of ./update trees
it's a shortcut command. a new symlink.

./update trees -b flashprog

can instead do:

./mk -b flashprog

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 23:36:04 +01:00
Leah Rowe f5ba40200f trees: initialise badhash no n, not empty string
this is another alternative to the previous fix. this one
is therefore now a pre-emptive fix, in case other code is
written in the future that makes use of badhash.

the badhash variable in a y/n variable, so initialise to n.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 19:40:46 +01:00
Leah Rowe faefcdf3df rom.sh: fix buggy deletion of cbutils
when badhash=y, the utils should be deleted, but
the check is deleting if badhash isn't n. if the
hash check isn't being performed, then this will
always be the case and the utils are always deleted.

make it positively delete the file only if badhash=y,
not when it isn't n. while this may not sound very
different, it will prevent the utils being deleted and
re-build endlessly in other cases, like when building
release archives and running the inject --nuke mode
on every image that gets built.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 19:34:19 +01:00
Leah Rowe 40dd0a7cf3 rom.sh: also add grub to seabios images
we want multiple seagrub images made, with different
keymaps, but we only want one non-seagrub image.

however, we also want grub in the non-seagrub image.
it just means that seabios is primarily what the user
wants, and they might occasionally use grub, whereas
the seagrub images are for people who primarily want
grub but may occasionally access the seabios menu.

right now, the seabios images really only contain seabios,
but there's no harm in adding grub to them.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 18:47:38 +01:00
Leah Rowe d070eb1fef rom.sh: copy tmprom to TMPDIR for modification
don't rely on build/coreboot.rom staying in place,
because sometimes it can get purged under certain
conditions, due to idiosyncrasies in the coreboot
build system, even when we don't explicitly clean it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 18:40:42 +01:00
Leah Rowe f85cb69ce0 rom.sh: re-add seabios-only roms and grub keymaps
this time, only handle multiple keymaps on seagrub
images. for images where seabios is first but does
not immediately load grub, whether grub is still
available in flash, just do one image (US Qwerty)

this still results in fewer images per target than
Libreboot 20240612, but should prevent most users
from being annoyed. i got a few people asking
repeatedly, and i hadn't documented yet how to add
keymap.gkb or how to remove bootorder, to get a
different keymap or disable seagrub respectively.

i anticipate that i'll get such questions a lot, even
if i do document it, so i'm reversing that decision.

it doesn't result in much extra code. the new design
in lbmk makes this sort of thing much simpler.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 09:30:47 +01:00
Leah Rowe 490e0186a2 emphasis on readme that lbmk isn't a coreboot fork
i actually only made this change so that the revision changes,
so that the release directory changes when doing:
./update release

this is to test whether such location change affects the build
time when using ccache.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-22 02:00:26 +01:00
Leah Rowe ba4278e0c6 include/rom.sh: use ccache when building coreboot
ccache now required, in build dependencies

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-21 07:39:47 +01:00
Leah Rowe 31f1e4dadf vendor.sh: don't use XBMK_CACHE for appdir
the me_extract function prefixes it with PWD in
some cases, but we can't predict where appdir
will point to.

the "app" directory is not intended to be a cache
anyway, so it doesn't make sense to put it in
the cache directory.

it's essentially scratch memory.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-19 00:48:09 +01:00
Leah Rowe 2b50b3ea9a put cachedir in environmental variable
XBMK_CACHE is now used, instead of hardcoding cache/

this is exported initialised to cache/, if unset.
this means you can set your own directory, and it means
./update release will use the same directory.

this means bandwidth wastage is further avoided.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-19 00:37:11 +01:00
Leah Rowe 0e0b12a630 git.sh: warn when a cached clone fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-18 23:23:50 +01:00
Leah Rowe 9b1b955767 git.sh: fix typo in git command
the || : condition should be used, whereas i just
wrote : by mistake. this was done in a previous change.

fix it now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-18 23:11:45 +01:00
Leah Rowe 82bdf27072 git.sh: fix lack of error exits on fault
a previous change made it more redundant, falling back
on old behaviour (direct downloading, not cached), but
the way it's done means that the function never returns
an error condition in practise.

this patch fixes it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-18 23:09:59 +01:00
Leah Rowe 64283a1fb1 build: remove tmp/ on release archives
i overlooked this before. remove it. the directory
happened to be empty when i tested archives, but it's
still not a good thing that we have it. remove it!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-18 14:13:11 +01:00
Leah Rowe bf85246c4c trees: hardcode makeargs for xgcc
if coreboot itself is being handled, crossgcc has the
correct makeargs, setting the number of build threads.

however, other projects can specify "xtree" pointing to
a given coreboot tree, and build crossgcc for it.

one workaround may be to use trees -d coreboot TREE,
but then extra code would have to be written to make
it avoid other things like building cbfstool, which is
not required for just building crossgcc.

the cleanest way to do it is to simply hardcode it. the
value is set exactly the same as regular coreboot makeargs.

this fixes a bug, where some builds of crossgcc are made
on a single thread, rather than using XBMK_THREADS. this
patch forces it to always use CPUS=$XBMK_THREADS

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 23:25:44 +01:00
Leah Rowe c6e6d96ce1 allow using coreboot's build system to add payload
lbmk must still define payloads, but specific configs
may use coreboot's build system instead.

you might use this to add your own config with, say,
tianocore payload, using coreboot.git to build it,
rather than using lbmk's choice of payloads.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 19:06:53 +01:00
Leah Rowe 78cdc56ae1 trees: remove unnecessary command
we no longer need to remove cache/ per project, because
it's removed in bulk at the end, in the main build script,
when generating release archives.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 18:55:18 +01:00
Leah Rowe e699037890 build: remove cache/ on making releases
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 18:52:58 +01:00
Leah Rowe 79f50b3791 unify caching of files into cache/
hash/ becomes cache/hash/

repo/ becomes cache/repo/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 18:39:42 +01:00
Leah Rowe a9f9de885c unified cache file handling for vendorfile/subfile
lib.sh download() is used by subfile handling in git.sh,
e.g. crossgcc tarballs, and also the vendor scripts.

vendor files are cached, but not subfiles for repos.

cache both, under cache/file/, saved with the name equal
to the checksum, so: cache/file/CHECKSUM

also move vendorfiles/app/ to cache/app/ in this change.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 18:15:52 +01:00
Leah Rowe ef867eccca git.sh: remove previous tmprepo if args>5
if doing a retry, the directory may still exist, which
would make git clone yield an error response; the existing
directory will have been the one that failed to reset, so
let's delete it.

the one deleted is not the cache (repo/PROJECT/), thus
otherwise maintaining current behaviour.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 17:28:27 +01:00
Leah Rowe 4d5385a14d git.sh: try direct clone if cached git fails
normally, a project is cached at repo/PROJECT/, and
cloned from there to the final destination.

errors lead to a calling of $err, but this will result
in a return if done from inside a subshell, of non-zero
value, so use this to re-try with a 6th argument when
calling tmpclone().

in most cases, this fallback will never kick in, but
it will kick in resetting or patching the cached clone
fails; specifically, we are interested in the reset part.

a given project name may change repositories in lbmk at
a given time. if this happens, and the old one is cached,
the overall result of this patch is that lbmk will fall
back to the old behaviour, where git urls are tried
directly, without caching.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 17:09:34 +01:00
Leah Rowe 0cd52fc7fd git.sh: re-try git pull three times
mitigate jittery internet connections

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 16:55:05 +01:00
Leah Rowe 0b9cd77fe7 trees: auto-delete+auto-rebuild if project changes
actual source code is not scanned, but config directories are
scanned. simply get the checksum of each file under config/
pertaining to a given project/tree, and also for the given
target. coreboot utilities are also handled.

if it changes, in any way, delete and re-build automatically.

such deletions should probably still be done manually, as part
of understanding the build system, but this change should make
the build system much easier to use during development.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 16:34:34 +01:00
Leah Rowe 4438368c0c trees: also remove single-tree repo/p/
single-tree repos were not previously cached, but now
they are and they have to be handled.

this, as also alluded to in the previous commit, is done
when preparing release archives (XBMK_RELEASE=y)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 13:27:50 +01:00
Leah Rowe 570e3abb24 trees: remove repo/p, not src/p/p
repo/p/ does not have its revision reset, so it
changes unpredictably, and it's not used in builds.

this used to be src/p/p/ - the context here is multi-tree
projects, in source archives.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 13:24:21 +01:00
Leah Rowe 583502027e git.sh: don't download to src/project/project/
re-use repo/project/

this means that single- and multi-tree projects now
have a unified cached git repo location, as per the
new rules, thus saving on disk space usage.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 13:20:51 +01:00
Leah Rowe 9f09728aca git.sh: cache git downloads to repo/
do it based on the URL, e.g. https://review.coreboot.org/coreboot
becomes repo/coreboot

the downside is if you have two projects with repo urls specifying
the same string at the end, but this isn't the case at the moment
and likely won't be the case, but it's a theoretical issue.

this saves on bandwidth when downloading identical submodule repos
between multiple trees within the same multi-tree project

for example, coreboot 3rdparty/vboot is no longer downloaded more
than once, instead cloned locally on subsequent downloads.

if repo/DIR exists, git-pull is attempted, but errors do not result
in a non-zero exit, by design.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-17 13:01:12 +01:00
Leah Rowe f367afabc1 remove util/autoport
upstream has merged all of the changes that it contained,
so we don't need this anymore. we'll have the newer upstream
changes on the next general revision updates for coreboot,
within config/coreboot/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-16 03:57:08 +01:00
Leah Rowe 373c2eb23d trees: move dependency building to new function
configure_project is a bit big. move the dependencies
build logic to a new function.

it may be desirable in future to make the way that
function works the way all build commands are done.

for example:

./update trees -b coreboot x230_12mb

would become:

./update trees -b coreboot/x230_12mb

this would enable to mix and match multi/single tree
projects. for now, leave things as they are.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-13 23:07:45 +01:00
Leah Rowe 12c3956f59 Merge pull request 'Update U-Boot to v2024.07' (#225) from alpernebbi/lbmk:uboot-v2024.07 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/225
2024-07-11 22:03:18 +00:00
Alper Nebi Yasak 708fc14c60 u-boot: Fix display initialization on gru boards
U-Boot has migrated to using upstream device-tree files for gru boards,
but the clock driver doesn't yet support setting rates for a certain
clock that upstream uses for the eDP display. It happens to work without
it, so for now remove the clock setting until the driver is fixed.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-07-11 23:16:42 +03:00
Alper Nebi Yasak 0cc7736b40 u-boot: Avoid breaking build for U-Boot-only binman images
Commit 46e01c0e1d ("u-boot: Avoid building U-Boot-only binman images")
added a patch that prevents an error while building U-Boot, due to some
U-Boot images needing a copy of BL31 that we are not passing in.

Removing build instructions for these images isn't really necessary,
when we can instead tell the build tool that it shouldn't exit with an
error. It checks a BINMAN_ALLOW_MISSING environment variable for this,
but just unconditionally replace the check with the argument.

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-07-11 22:40:33 +03:00
Alper Nebi Yasak 2ecec55af7 u-boot: Update to v2024.07
Set default U-Boot revision to v2024.07 and rebase patches on top of
that. One patch that fixes drawing box characters (UTF-8 to CP437) had
an alternative merged, another hack we have to fix regulator issues is
no longer neccessary as the issue is fixed, and my QEMU patches were
merged upstream, so drop these patches. One patch we have to disable
binman images can be replaced by a simpler alternative so drop it too.

Upstream kconfig status is still unstable, so updating configs with
`make oldconfig` would miss important upstream changes, since they rely
on carrying defaults via upstream defconfigs. Update the configs as
such, like before:

- Turn old configs into defconfigs (./update trees -s u-boot)
- Save the diff from old upstream defconfig (diffconfig $theirs $ours)
- Update U-Boot revision, rebase patches, and clean old trees
- Prepare new U-Boot tree (./update trees -f u-boot)
- Review the diffconfigs to see if any options were renamed upstream
- Copy over the new upstream defconfigs and apply earlier diff
- Turn new defconfigs into configs (./update trees -l u-boot)

Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
2024-07-11 22:29:58 +03:00
Leah Rowe 090cf7ad54 trees: fix bad comparison in configure_project()
we used to set cmd only to these values:
build_project
build_targets

however, now we set them to:
build_project
build_targets $@

the latter cannot be measured reliably, but
we were checking whether cmd equalled:
build_targets

now we instead check that it does not equal:
build_project

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-11 01:14:28 +01:00
Leah Rowe e37779c11d trees: don't continue if no argument given
main() used to be the only function executed from
outside of main(), in this script, but now we source
a config file and then run the build afterward.

when a flag is provided without OPTARG, this means
that we are continuing such action erroneously. to
mitigate this, return 1 in that instance, and handle
it in the line that calls main(), making it exit with
zero status (success).

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-11 00:28:32 +01:00
Leah Rowe 3263eeb6b6 trees: general code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 23:11:23 +01:00
Leah Rowe 17f3e61a0e trees: merge build_targets() with handle_targets()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 21:43:13 +01:00
Leah Rowe c0a4df688c trees: use wrapper for dry-running make commands
instead of using lots of if/else conditions, do that once
and set a variable, dry, to :

if not doing a dry run, the variable is empty. prefix this
variable in places where you don't want a certain action to
be performed, on dry runs.

more specifically, : does *nothing* and always returns with
zero status (success).

this results in cleaner code, and a small sloccount reduction.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 21:00:16 +01:00
Leah Rowe 459db1cc2e trees: remove project-specific hacks
move the coreboot-specific includes into mkhelper.cfg
for that project.

on some projects, we need variables from mkhelper.cfg
to be global, so I was including serprog and coreboot
mkhelper.cfg files in this script.

instead, set a new variable "mkhelpercfg" pointing to
the config file. if it doesn't exist, create and then
point to a temporary (empty) mkhelper.cfg file.

the rom.sh include has been moved to coreboot mkhelper.cfg

The only remaining project-specific logic, in this trees
script, is now the coreboot crossgcc handling, but this
needs to be there as it's also used to build U-Boot.

The way this now works, certain includes are done twice.
For example, include/rom.sh will be included once globally,
outside of main(), and then again in configure_project().

This means that certain functions will be defined twice.
I'm uncertain if shell has anything equivalent to an ifdef
guard as in C, but we actually want this here anyway, and
it shouldn't cause any problems. It's a bit of a hack, but
otherwise results in much cleaner code.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 13:41:15 +01:00
Leah Rowe e9f66ec4a8 remove executable permission on include/
files under include/ should never be executed directly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 02:14:25 +01:00
Leah Rowe 91994b7852 rom.sh: actually say if a cbutil exists
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 02:04:25 +01:00
Leah Rowe 97b777715b rom.sh: avoid re-building cbutils if built
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 01:37:27 +01:00
Leah Rowe 494b94799e rom.sh: only before cbutils before coreboot
otherwise, due to the idiosyncratic nature of the coreboot
build system, the coreboot.rom gets wiped out.

cbutils is still handled by premake. ensure that payloads are
only inserted just after running the coreboot make command.

fixes a build issues introduced on 9020sff, previously unhandled.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 01:24:05 +01:00
Leah Rowe 469cc64f99 trees: fix bad comparison
pro-tip: don't do this at 3AM

do massive changes like this, no later than 1AM.

the intent anyway is for -d to cause no build dependencies
to be handled, but the current logic says to only handle
them if -d is set! fix it by removing the ! part

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-10 01:11:14 +01:00
Leah Rowe 5a1d2401c2 minor cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-09 03:09:49 +01:00
Leah Rowe 9646172145 trees: support -d (dry run) for custom build logic
-d does the same as -b, except for actually building
anything! in effect, it does the same as -f (fetch)
except that the resulting variable assignments will
not be recursive (as with -f).

if -d is passed, configuration is still loaded, defconfig
files are still cycled through, and more importantly:

helper functions are still processed.

the grub, serprog and coreboot helper functions have
been modified to return early (zero status) if -d is
passed.

this behaviour will be used to integrate vendor.sh
logic in with the trees script, for cases where the
user wants to only handle vendor files. e.g.:

./update trees -b coreboot x230_12mb

this would download the files as usual, build coreboot,
with those files, and then build the payloads. but:

./update trees -d coreboot x230_12mb

this would download the files, NOT build coreboot, and
NOT build the payloads.

this change increases the sloccount a bit, but i'm relying
on the fact that the vendor.sh script already re-implements
config handling wastefully; the plan is to only use trees.

for now, simply stub the same ./vendor download command.

there is one additional benefit to doing it this way:

this method is *per-kconfig* rather than per-target.
this way, one kconfig might specify a given vendor file
that is not specified in the other. although the stub
still simply handles this per target, it's done in premake,
which means that the given .config file has been copied.

this means that when i properly re-integrate the logic
into script/trees, i'll be able to go for it per-kconfig.

the utils command has been removed, e.g.
./update trees -b coreboot utils default

the equivalent is now:
./update trees -d coreboot default

this would technically download vendor files, but here
we are specifying a target for which no kconfigs exist;
a check is also in place, to avoid running the vendor file
download logic if tree==target

the overall effect of this change is that the trees script
no longer contains any project-specific logic, except for
the crossgcc build logic.

it does include some config/data mkhelper files at the top,
for serprog and coreboot, so that those variables defined in
those files can be global, but another solution to mitigate
that will also be implemented in a future commit.

the purpose of this and other revisions (in the final push
to complete lbmk audit 6 / cbmk audit 2) is to generalise as
much logic as possible, removing various ugly hacks.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-09 02:55:20 +01:00
Leah Rowe e850c06bd2 rom.sh: only make rom tarball if release=y
Signed-off-by: Leah Rowe <info@minifree.org>
2024-07-08 02:22:22 +01:00
Leah Rowe 2f3cc5d379 rom.sh: new file, to replace script/roms
stub it from the trees script. the way it works now,
there is less code in the build system.

./build roms

this is no longer a thing

./build roms serprog

this is also no longer a thing. instead, do:

./update trees -b coreboot targetnamehere

./update trees -b pico-serprog

./update trees -b stm32-vserprog

the old commands still works, which causes the new
commands to run

coreboot roms now appear in elf/, not bin/, as before,
but those images now contain payloads.

NOTE: to contradict the above: ./build roms is no
longer a thing, in that it's now deprecated, but
backward compatibility is present for now. it will
be removed in a future release.

./build roms list also still works! it will do:
./update trees -b coreboot list

also:
./update trees -b grub list
this is now possible too

if a target "list" is provided, for multi-tree sources,
the targets are shown.

there is another difference: seagrub roms are now seagrub_,
instead of seabios_withgrub.

seabios-only roms are no longer provided, where grub is also
enabled; only seagrub is used. the user can easily remove
the bootorder file, if they want seabios to not try grub first.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-07 21:25:07 +01:00
Leah Rowe 889afe1689 roms: remove unnecessary trees checks
we no longer need to call trees -b for payloads, because
build_depend is set in coreboot target.cfg files

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-06 11:34:27 +01:00
Leah Rowe c241a3ef48 coreboot: set build_depend on target.cfg files
set a default one in mkhelper.cfg

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-06 11:34:27 +01:00
Leah Rowe 6d4fb200ac trees: rename load_target_config()
rename it to configure_project, because the function now
also handles building (a little bit), not just mere loading
of configuration files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-06 11:34:27 +01:00
Leah Rowe 87df6ae369 trees: support build dependencies, not just fetch
We already have this to an extent, e.g. the xtree variable.

The xtree variable could probably be removed, in favour of
this, and used for the same purpose.

It works like this, for example:

build_depend="coreboot/default grub/xhci seabios u-boot/gru_bob flashprog"

the "/" denotes a tree, if it's a multi-tree project. However, specifying
the entire multi-tree project without slash is possible, for example:

build_depend="coreboot"

this would specify that all coreboot trees must be built.

This functionality will be used in follow-up commits, centralising
script/trees into mk on the main directory, repacing "build".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-06 11:34:19 +01:00
Leah Rowe 23ca49bee8 GRUB: only load xhci from grub.cfg
don't put it in the install modules.

this works around a hanging issue on haswell thinkpads.

when any usb device is inserted, GRUB will sometimes
hang if started from the SeaBIOS payload, *while* the
USB device is plugged in.

plugging in the USB device after GRUB starts worked.
it will have to be investigated more at a later date,
but this simply configuration change works.

the xhci module is already loaded explicitly, in grub.cfg

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-06 02:04:14 +01:00
Leah Rowe 065453b72e trees: just do makeargs on coreboot, not cbmakearg
stick the makeargs in mkhelper

i previously did cbmakeargs because the old revisions
had to define makeargs per-target otherwise. mkhelper
was done specifically to solve that problem.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-05 18:17:23 +01:00
Leah Rowe 2ab1d99490 trees: fix bad rm -Rf command (-Rf, not Rf)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-01 13:03:04 +01:00
Leah Rowe d6ff009e20 roms: fix bad comparison in configure_target()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-01 03:34:09 +01:00
Leah Rowe 3ee045f9ad GRUB: use mkhelper.cfg for common variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-07-01 03:32:35 +01:00
Leah Rowe 3ef84af9fd trees: allow global config on multi-tree projects
config/data/PROJECT/mkhelper.cfg can be provided, for
configuration, and it is loaded *before* target.cfg

there are certain instances where we repeat a lot of
config per tree, in multi-tree projects.

for example, we have the exact same config per grub
tree, besides tree name and revision number, for things
like autoconf arguments.

this last problem will be addressed, in a follow-up
patch, and then expanded upon for other projects.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 22:22:15 +01:00
Leah Rowe 2b49714a6a trees: handle all projects if project undefined
e.g. ./update trees -f

if passed, this command would download every tree

similarly, the -c option can be used in this way. this
solves a longstanding issue: on the current, much more
efficient design, it was not possible to systematically
clean every project.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 21:33:30 +01:00
Leah Rowe b7f12ade03 vendor.sh: remove mkdirs()
merge it into the only calling function

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 19:22:58 +01:00
Leah Rowe 0018600d6e git.sh: simpler for loop in git_am_patches()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 18:23:15 +01:00
Leah Rowe 5882056a27 git.sh: merge for loops in git_am_patches()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 18:16:34 +01:00
Leah Rowe 67421a21fd trees and git.sh: tidy up global variables
some of the variables only initialised in git.sh are
also used in the trees script, which is technically ok
because git.sh is included from the trees script, but
it makes more sense to declare them in the latter.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 18:10:22 +01:00
Leah Rowe 55dbd72aaf git.sh: simplified initialisation of "loc"
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 17:56:32 +01:00
Leah Rowe 0cb84a8dd1 trees: simplified distclean directory check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 17:13:49 +01:00
Leah Rowe 5ba0433b5f git.sh: condense fetch_targets() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 17:04:24 +01:00
Leah Rowe 4772186b19 git.sh: short git_prep command in fetch_targets()
loc is already set, and will correspond to the same
path, so we can quite conveniently use it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 17:02:44 +01:00
Leah Rowe c62dbdbe82 trees: only do bare multi-tree clone on git
i forgot to add the check for CHANGELOG

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 16:23:32 +01:00
Leah Rowe 89a81a2910 trees: simplified multi-tree bare repo clone
the git_prep function already creates the given
directory where source code goes, so we don't
need to do it from the trees script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 16:16:07 +01:00
Leah Rowe 017fd8259e git.sh: merge prepare_new_tree with fetch_targets
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 15:49:35 +01:00
Leah Rowe f937a1142d trees run_make_command: simpler distclean handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 15:46:03 +01:00
Leah Rowe 88f741db92 trees: condense copy_elf() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 15:39:41 +01:00
Leah Rowe d5928c9ba8 trees: add return to handle_defconfig()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 14:39:20 +01:00
Leah Rowe 1a7c8acb0e trees: rename check_config to check_defconfig
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 14:13:52 +01:00
Leah Rowe ba7b3a3b21 trees: remove variable "config_name"
it's only ever used once, so just use the value that
it's set to, without declaring the variable itself

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 14:10:49 +01:00
Leah Rowe 030f1afd8e trees: rename variable "config" to defconfig
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 14:08:22 +01:00
Leah Rowe 7394960619 git.sh: remove duplicate "xtree" variable
it's already defined inside the trees script

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 14:00:19 +01:00
Leah Rowe 0c4ad24b05 trees: remove unnecessary commonts
behaviour described there is obvious just
from analysing the while loop condition

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 13:46:31 +01:00
Leah Rowe eacc41e82a trees: condense run_make_command() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 13:42:42 +01:00
Leah Rowe 5639481419 trees: condense handle_makefile() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 13:30:35 +01:00
Leah Rowe 1ec9fc3368 trees: mv load_project_config load_target_config
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 01:07:59 +01:00
Leah Rowe 789631ccb8 trees, multi: download bare project *before* trees
when downloading multi-tree projects, the rev can be reset
to HEAD instead of the actual rev for a given target. this
occurs when the bare repo (e.g. src/coreboot/coreboot) does
not exist and has to be downloaded first.

bare repository downloading does not rely on target.cfg, in
this context, only pkg.cfg, but it uses the same variable
names (e.g. "rev").

instead of using a separate variable name, thus increasing
code complexity (which is the exact opposite of what i want
to do), do the bare repository download first.

this means that the git.sh script is much cleaner now, for
multi-tree projects, in that it *only* copies the bare repo
then runs git_prep; in that context, the bare repo is cloned
directly by calling the relevant function from script/trees,
which is the same behaviour as when cloning single-tree
project sources.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 00:40:30 +01:00
Leah Rowe a5e724e51e trees: unified multi-tree configuration handling
the same function that loads configurations for single-tree
projects has been merged with the function for multi-tree
configs in git.sh, and that functionality has been removed
from git.sh; now it is all unified in the trees script.

as the saying goes: write one program to do one thing well.

the purpose of git.sh is to download source code, but not
to handle configuration files; the latter is meant to be
handled by the trees script, which then calls into git.sh
before running the build logic for that given project.

additionally: the "seen" files are no longer handled, at all.
the logic there was added ages ago, because at the time, i was
considering whether to separate configuration into a new
repository, so that users could more easily make their own
configuration, so it was a guard against misconfiguration.
however, that decision was canceled and we're always very
careful not to introduce a loop; if a loop does occur, the
worst that can possibly happen is you waste some CPU cycles.

Instead, print (on standard output) what config file is being
used, so the operator can see when an infinite loop occurs.

ALSO:

remove _setcfgarg in load_project_config()

it was used to skip when a target.cfg file didn't exist,
specifically on single-tree projects, but this is now
handled using -f instead, on the while loop inside that
function, so _setcfgarg is now a redundant variable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-30 00:02:03 +01:00
Leah Rowe cfc9f62ffe trees: unified handling of source downloads
run it from load_project_config()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 22:25:54 +01:00
Leah Rowe 7bf2835207 git.sh: rename Fetch_project_trees fetch_targets
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 19:59:16 +01:00
Leah Rowe e0c244f37b git.sh: rename fetch_project_repo to fetch_project
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 19:58:03 +01:00
Leah Rowe 02f7417952 trees: better skip-clean string in handle_src_tree
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 19:47:25 +01:00
Leah Rowe f7ec42d379 trees: add return to check_coreboot_utils()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 19:46:07 +01:00
Leah Rowe 8d02adfbb5 trees: simplify "utilmode" variable initialisation
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 19:44:47 +01:00
Leah Rowe d1b7882c5a vendor.sh readcfg: split the -b coreboot command
just add a line break to make the code more readable

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 18:55:41 +01:00
Leah Rowe fbe36b01ac trees mkpayload_grub: remove unnecessary check
these variables are initialised empty, then populated
by reading a configuration file.

it may be that in some cases, we want these variables
to be empty. besides that, the "setcfg" command before
it will throw an error if the module file is missing,
and it is assumed that the variables would be set there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 18:39:25 +01:00
Leah Rowe 088a79918b vendor.sh: remove unnecessary check
the next command is a copy, which would give us the error
if the file doesn't exist, and an appropriate message

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 03:47:57 +01:00
Leah Rowe 8c5f78d3d3 vendor.sh: condense inject() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 03:27:31 +01:00
Leah Rowe 42925ce79f vendor.sh extract_kbc1126: use quote on file check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 03:09:03 +01:00
Leah Rowe ddcc74777e vendor.sh extract_kbc1126ec: simplify build check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 03:06:58 +01:00
Leah Rowe 7a12cd7704 vendor.sh: simplify e6400 vga rom file check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:25:22 +01:00
Leah Rowe 163bcfcdfd vendor.sh: simplify variable checks for e6400vga
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:23:02 +01:00
Leah Rowe cbac2087cc vendor.sh: condense fetch() a bit more
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:21:00 +01:00
Leah Rowe 675d2c0376 vendor.sh: remove unnecessary check
this is over-engineering, because we do not allow just
about any path to be provided; it's not provided as an
argument in a command, for example.

this is dictated by a configuration file, which we control.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:14:00 +01:00
Leah Rowe 5e46b9f434 vendor.sh: simplify kbc1126 util handling
we don't need to check whether the binary exists, because
make already does that for us.

we still need to check that the directory exists, because
older versions of coreboot did not include kbc1126, and we
do still use older coreboot revisions on some boards.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:12:40 +01:00
Leah Rowe 7086b68685 vendor.sh: simplify bootstrap() utils handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 02:07:16 +01:00
Leah Rowe 6a05487ef3 vendor.sh: simplified initialisation of _7ztest
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:57:03 +01:00
Leah Rowe 972e61070b vendor.sh: condense detect_board() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:47:14 +01:00
Leah Rowe bf5acedb12 vendor.sh: condense patch_rom() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:41:48 +01:00
Leah Rowe 8b8cf070d3 vendor.sh: add return to end of bootstrap()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:27:42 +01:00
Leah Rowe d85b9de2d9 vendor.sh: rename getcfg() to readkconfig()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:26:31 +01:00
Leah Rowe 53b69f673c vendor.sh: merge cfgutils() into readcfg()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:24:13 +01:00
Leah Rowe 55677d8217 vendor.sh: remove build_dependencies_inject()
merge it into vendor_inject()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:22:28 +01:00
Leah Rowe c764198619 vendor.sh: simplify initialisation of variables
also unify handling of cbutils

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 01:19:29 +01:00
Leah Rowe d63da943c1 vendor.sh inject: skip serprog targets
this is to prevent a fault condition during automated testing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 00:33:31 +01:00
Leah Rowe c6df9666af vendor.sh: don't inject /dev/null
if injection is attempted, verification comes next,
and verification fails.

this happens for kcma/kgpe amd boards, where pike2008
fake roms are inserted by inserting the correct pci
ids using /dev/null as a source. an empty pike2008 rom
prevents seabios from loading the real pci rom, and this
is done because the real one hangs SeaBIOS.

a similar fix was made for ./vendor download, but
overlooked for ./vendor inject. this patch fixes that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-29 00:23:26 +01:00
Leah Rowe f7ab70f60e vendor.sh: simplify inject()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 23:53:29 +01:00
Leah Rowe ee5bab2c9a vendor.sh: clean up GbE handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 23:33:31 +01:00
Leah Rowe f2d53eb842 vendor.sh: condense fetch() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 23:10:22 +01:00
Leah Rowe 85c2eb0f7c vendor.sh: general code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 22:49:59 +01:00
Leah Rowe a8f272536d lib.sh: stricter check in chkvars()
testing +x is all well and good, but the variable string
may be empty, even if set. some of the checks in the build
system are relying on the latter, so handle it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 22:32:03 +01:00
Leah Rowe fa5af956c4 vendor.sh: simplified modify_gbe handling
we don't need the "modifygbe" variable. we only need to
know that new_mac was set.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 22:31:09 +01:00
Leah Rowe 155ce49b17 vendor.sh: simplify modify_gbe()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 21:43:23 +01:00
Leah Rowe 08bce7ad3b vendor.sh: minor code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 21:31:40 +01:00
Leah Rowe 636b86237f vendor.sh: re-add modify_gbe()
i accidentally deleted it in an earlier code purge

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 16:24:07 +01:00
Leah Rowe 2eb0163cc7 Revert "vendor.sh: remove unnecessary check"
This reverts commit 8196ce6ddf.
2024-06-28 15:24:42 +01:00
Leah Rowe 3f37c3788b tidy up some setvars lists
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 15:02:11 +01:00
Leah Rowe ed3cce84bc roms: explicitly shift by 1 on the "all" target
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:57:07 +01:00
Leah Rowe 359d00bd56 roms: add return value for the list command
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:56:30 +01:00
Leah Rowe 3f540e7565 roms: build u-boot *before* checking ubootelf
the current check is flawed, because if u-boot doesn't
exist, but a given build would be the file verified by
the first check, the check would still fail even after
then building u-boot.

building it first will make this check pass, under such
a condition.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:52:08 +01:00
Leah Rowe afc0030682 remove more unnecessary checks on trees commands
the trees script already performs these checks

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:51:32 +01:00
Leah Rowe 35c487106a vendor.sh: remove unnecessary checks
again: the trees script already checks binaries,
and already checks sources. if they exist, the
relevant action is skipped entirely.

we don't need to check it in vendor.sh, because the
trees script already performs the same check.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:45:20 +01:00
Leah Rowe ce03786f69 vendor.sh: remove unnecessary command
we don't need to download the entire coreboot tree here,
because the next command after it builds utils from that
tree, using the trees script which would then go and
download that tree anyway; this is part of the design.

if a given elf binary exists, it won't be re-built, but
the missing sources will still be downloaded automatically.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:18:01 +01:00
Leah Rowe e01b5c9744 vendor.sh: remove unnecesessary cbutils check
the trees script already does this same check, so don't
do it in here. defer to the trees script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:16:17 +01:00
Leah Rowe 8196ce6ddf vendor.sh: remove unnecessary check
mktemp will never return empty output, and the next
command after it is an mkdir, which would throw an
error anyway, if the string is empty.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 14:15:28 +01:00
Leah Rowe 8f50131e1e vendor.sh: condense check_board() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:59:26 +01:00
Leah Rowe d12a686015 vendor fetch(): condense variable initialisation
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:50:35 +01:00
Leah Rowe 708e306e5f vendor.sh: remove unnecessary cbfstool check
the trees script already performs this check

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:49:44 +01:00
Leah Rowe 75951c4690 vendor.sh: simplified cbfstoolref check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:49:08 +01:00
Leah Rowe d36c07847d lib.sh: keep versiondate check to 80 characters
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:44:13 +01:00
Leah Rowe 40d3bb19be lib.sh: condense for loop
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:42:19 +01:00
Leah Rowe 5725e3c4ee lib.sh: condense err_() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:41:22 +01:00
Leah Rowe e3546f77b8 lib.sh: add a return to the end of chkvars()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:40:50 +01:00
Leah Rowe d0f68a0fbf vendor.sh: rename release to vrelease
also remove inject_vendorfiles() and merge it
into vendor_download()

the "release" variable is included in some target.cfg
files, which we put in config/coreboot/ and handle
here, so they could conflict with the release variable
used in vendor.sh, used for a different purpose. therefore,
rename it to "vrelease".

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:38:43 +01:00
Leah Rowe 473f277845 vendor.sh: unified reading of board configs
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:33:50 +01:00
Leah Rowe a2f4eba581 vendor.sh: simplify variable check in getcfg()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:24:47 +01:00
Leah Rowe 4afcbcb641 vendor.sh: remove unnecessary cbdir check
we don't need to check this, because the trees script
already checks it. avoid unnecessary work.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-28 13:22:37 +01:00
Leah Rowe fd037722ad remove use of _xm variable in the build system
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 22:18:01 +01:00
Leah Rowe 136787185d trees: don't hardcode use of mkpayload_grub
instead, make it a helper function, defined in target.cfg

this means that we can also do the same with other projects
in the future, and it is expected that we will have to.

these helper functions are used in cases where we want
additional actions to be performed.

actually, the helper could be anything. for example, you
could write:

mkhelper="./build foo bar"

and it would do that (at the point of execution, PWD
is the root directory of the build system)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:51:48 +01:00
Leah Rowe c59fbb3651 trees: simplify single/multi handling in main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:43:35 +01:00
Leah Rowe 902b98d1ac trees: rename build_projects to build_project
the script used to support building multiple single-tree
projects, but this behaviour was buggy and unused, so it
was removed.

rename the build_projects variable accordingly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:41:23 +01:00
Leah Rowe e1e04aa80d trees: err if target.cfg not given if multi-tree
it was always by design that an error should occur, if a
target.cfg file does not exist on multi-tree projects,
but we previously did not support target.cfg files on
single-tree projects.

single-tree target.cfg support was later added, and it was
done by making target.cfg optional there, but i accidentally
made it optional on multi-tree projects.

in practise, all multi-tree projects included target.cfg,
but this was not being enforced in code.

this patch should fix the issue.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:38:49 +01:00
Leah Rowe 93ff80d96d trees: set btype if target.cfg doesn't exist
set it to "auto", because otherwise it'll be unset,
which means that kconfig type is assumed.

the build system is designed in such a way that multi-tree
is assumed, if the target build system uses kconfig files.

target.cfg is optional on single-tree but not multi-tree,
so it's ok to set something here.

basically, kconfig-type projects will never be single-tree.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:33:30 +01:00
Leah Rowe 732c5908df lib.sh: remove unused cbdir variable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:12:30 +01:00
Leah Rowe 119cebc4d8 roms: remove unnecessary assignment to cbdir
cbdir isn't used in this script

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 16:10:09 +01:00
Leah Rowe 7a15ba18cb trees: avoid kconfig make commands generically
don't hardcode the check based on whether the current
project is grub. instead, define "btype" in target.cfg

if unset, we assume kconfig and permit kconfig commands
e.g. make menuconfig, make silentoldconfig, etc

this is to avoid the deadliest of sins:
project-specific hacks

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 15:55:56 +01:00
Leah Rowe eb9c1872b6 git.sh: remove unnecessary check
the trees script itself will check that the directory
exists, and exit with zero status if it does, without
doing anything else other than the return.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 14:52:28 +01:00
Leah Rowe 9aec992ff2 lib.sh: move git_err() to build
it's only used in the main build script, so move it there.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 14:32:20 +01:00
Leah Rowe 6fc7cd3c17 lib.sh: condense singletree() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 14:06:41 +01:00
Leah Rowe 35d09e426a lib.sh: add a return to the end of check_defconfig
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 14:06:08 +01:00
Leah Rowe 144b3c93a4 trees: condense elfcheck() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 14:05:19 +01:00
Leah Rowe 7b8c2bd412 lib.sh: condense e() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 03:41:30 +01:00
Leah Rowe ffdecb0ce1 trees: shorten the final confirmation message
must stay below 80 characters per line

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 03:36:32 +01:00
Leah Rowe ed6acfee84 lib.sh: make elf/coreboot* a dot directory
we don't want the user to flash coreboot from elf/, because
those images do not contain payloads. the user must flash from
bin/

ample warning is given, at build time, but the warning is written
in english. therefore, some people may not understand it, because
they may not even speak english.

hide the coreboot elf/ directory, to mitigate this possibility.
in most cases, this will probably prevent the average user from
flashing those images, since they likely won't see it.

the "DO NOT FLASH" warning is still included in that directory
name, while creating it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 03:23:31 +01:00
Leah Rowe 44fb987363 build: don't rm TMPDIR if it's /tmp
we override TMPDIR, setting it to /tmp/xbmk*C

if it's just set to tmp, that means we didn't set it properly,
which is a bug.

this patch protects against deletion of /tmp under such a
fault condition, if it were ever to occur in the future.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 03:20:18 +01:00
Leah Rowe fac74cd60a lib.sh: simplified TMPDIR handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 03:18:23 +01:00
Leah Rowe 671893a802 lib.sh: condense setcfg() if/else logic
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:52:46 +01:00
Leah Rowe 19bc5845a6 trees: remove redundant space in printf
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:45:11 +01:00
Leah Rowe 9154ba5b85 trees: explicitly err if OPTARG is not set
we currently rely on -e to make this happen

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:44:01 +01:00
Leah Rowe f383b1ad70 trees: only permit one single-tree project
the current logic for handling multiple single-tree projects
is quite error-prone, and uses recursion.

since we don't actually use it this way, remove that feature.

the most correct way to do it is with a for loop.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:42:59 +01:00
Leah Rowe a64e2db589 trees: call err if multiple flags are provided
this script is designed to only run a single flag.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:33:45 +01:00
Leah Rowe 0e97e98fe1 trees: explicitly set mode for -b
doing nothing means that if a flag is passed, and then
another flag overriding it, the resulting action will
not be correct; only one flag should be provided anyway,
but some users may feel a bit more adventurous.

mitigate it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:31:54 +01:00
Leah Rowe 7f7b640d3a roms: re-add compression of coreboot images
i accidentally removed this feature, during prior cleanup.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-27 02:05:29 +01:00
Leah Rowe 1ab9189cbd roms: build coreboot *after* checking variables
otherwise, release=n is ignored and an image is built in
the elf/ directory, even if it's still skipped for bin/

avoid doing unnecessary work per-release by checking the
variables before building coreboot via script/trees

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 09:54:22 +01:00
Leah Rowe 2b4c6ee5ca lib.sh: introduce mandatory check of projectname
error out if it's not set. ditto projectsite.

that way, if the files are accidentally deleted, or not
added in a derivative of the build system, you'll know.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 00:24:59 +01:00
Leah Rowe c79fb125eb lib.sh: condense setvars() a bit
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 00:22:42 +01:00
Leah Rowe 1387dc0ae2 simplified lock message
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 00:20:06 +01:00
Leah Rowe 20ac7ec67b lib.sh: simplify reading of version files
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 00:18:12 +01:00
Leah Rowe 4e48fa808e lib.sh: simplify use of environment variables
don't have a separate variable for them.

just export them directly and use them directly.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-25 00:12:18 +01:00
Leah Rowe b4fb251008 roms main(): confirm what serprog images are built
just like we do for coreboot images, do it for serprog.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 18:39:53 +01:00
Leah Rowe 5e2308ce05 roms: remove unused variable name
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 18:35:32 +01:00
Leah Rowe 2960abd008 roms: remove redundant printf
we don't need this message here, because the final confirmation
at the end of main() says which targets were built. saying what
individual rom images were built is just needless bloat,
especially with the new simplified lbmk design; we no longer
provide lots of rom images with different keymaps, because we
now expect the user to insert a gkb file themselves with cbfstool.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 18:32:18 +01:00
Leah Rowe c661eca6b9 roms: optimise u-boot elf check
because we use crossgcc here, blindly running trees -f
means needlessly re-running buildgcc, which then checks
for gcc binaries, even though we already know that the
u-boot binary exists. skip this check if u-boot exists.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 18:30:48 +01:00
Leah Rowe 8af9f904c4 roms: simplify build_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 18:24:50 +01:00
Leah Rowe c9f26dbc94 roms: make the bin/elf message more polite
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 17:42:58 +01:00
Leah Rowe 9484eda5a7 roms: re-add final confirmation of targets
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 17:41:43 +01:00
Leah Rowe 2b7df7ab2c roms: rename functions for extra clarity
the names of these functions do not match their true
intent. fix that by renaming them appropriately.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 17:35:44 +01:00
Leah Rowe 6753222d0e roms: build coreboot early to avoid duplicate work
we're building it per coreboot configuration file, rather
than per-target; the latter is more appropriate, and saves
on compilation time.

do it per-target.cfg, not per coreboot configuration.

this works because the trees script compiles all images
per target, for each given coreboot configuration within
that target, e.g. libgfxinit _corebootfb and _txtmode.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 17:28:25 +01:00
Leah Rowe 19e7c1eabb trees: try xgcc build twice if first attempt fails
sometimes buildgcc just fails for like no reason. we had this
the other day and another fix was made to the trees script, to
mitigate; the user ran it again and buildgcc worked just fine.

run it twice, and then call err only if the second one fails.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-24 14:23:56 +01:00
Leah Rowe 6468bdb3aa trees: don't check if xgcc is already built
just run the make crossgcc command anyway.
coreboot's own build system checks itself, and much
more reliably, but the check is more thorough and a bit
slower.

in rare cases, lbmk may come into build issues with xgcc,
and if you run the build again, it will always fail every
time because the checks is based on whether the xgcc
directory exists, rather than checking each
individual crossgcc binary.

checking every binary is also possible, but as i said,
the coreboot build system already does that, so let's defer
to coreboot's own handling of it.

remove the directory check. this will slow down the build
process a little bit, but should improve reliability under
fault conditions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-23 17:24:28 +01:00
Leah Rowe d5baaff0ec lib.sh: fix error running ./build dependencies
the e() and setvars() functions need to be declared before
the dependencies function.

also: after calling install_packages, it was doing a return
when it should have done an exit.

this is all fixed now. i apologise to anyone who previously
ran into trouble with this!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-23 12:34:26 +01:00
Leah Rowe 0158a08111 roms: general code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-23 01:10:11 +01:00
Leah Rowe e67cd17164 roms: only support SeaBIOS/SeaGRUB on x86
Never, ever build images where GRUB is the primary payload.

These options have been removed from target.cfg handling:

* seabios_withgrub
* grub_withseabios

The "payload_grub" variable now does the same thing as
the old "seabios_withgrub" variable, if set.

The "grubonly" configuration is retained, and enabled by
default when SeaGRUB is enabled (non-grubonly also available).

Due to lbmk issue #216, it is no longer Libreboot policy to
make GRUB the primary payload on any board. GRUB's sheer size
and complexity, plus the large number of memory corruption issues
similar to it that *have* been fixed over the years, tells me
that GRUB is a liability when it is the primary payload.

SeaBIOS is a much safer payload to run as primary, on x86, due
to its smaller size and much more conservative development; it
is simply far less likely to break.

If GRUB breaks in the future, the user's machine is not
bricked. This is because SeaBIOS is the default payload.

Since I no longer wish to ever provide GRUB as a primary
payload, supporting it in lbmk adds needless bloat that
will later probably break anyway due to lack of testing,
so let's just assume SeaGRUB in all cases where the user
wants to use a GRUB payload.

You can mitigate potential security issues with SeaBIOS
by disabling option ROM execution, which can be done at
runtime by inserting integers into CBFS. The SeaBIOS
documentation says how to do this.

Libreboot's GRUB hardening guide still says how to add
a bootorder file in CBFS, making SeaBIOS only load GRUB
from CBFS, and nothing else. This, combined with the
disablement of option ROM execution (if using Intel
graphics), pretty much provides the same security benefits
as GRUB-as-primary, for example when setting a GRUB password
and GPG checks, with encrypted /boot as in the hardening guide.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-22 22:57:39 +01:00
Leah Rowe 71137b12b4 roms: remove support for "grubonly" seabios
due to lbmk issue #216, it is now unwise to use grub as the
primary payload on any machine; the sheer complexity of grub
and the number of memory corruption bugs that have been fixed
due to auditing over the years, means more such bugs exist.

we now provide seabios as the primary payload on all x86 ports,
but provide a "grubfirst" configuration where a bootorder file
in seabios can be added via cbfs, which tells seabios to load
grub from cbfs first, while still allowing use of the boot select
menu by pressing esc in seabios.

well, the "grubonly" option also disables the seabios esc menu,
so that *only* grub runs. there is no point in using this unless
you want to harden your setup, for example if you want to set up
encrypted /boot and boot that from grub, and have a grub password
disallowing unauthorised bootup of your machine.

see grub hardening guide;
https://libreboot.org/docs/linux/grub_hardening.html

at least as of today, 22 June 2024, that page already says
how to manually disable the seabios menu in the same way, if that
is the setup you want. alternatively, a user may be wily
enough to edit target.cfg for their board and compile a rom
that only has the grub payload in it, if that is what the user
wishes to do.

regardless, the default configurations provided by lbmk must never
be unsafe, norc should the build system support such unsafe
settings;

yes, grub as primary payload is technically still supported in
lbmk. actually, at the time of this revision, i have half a mind
to remove that functionality altogether, so that only seabios is
allowed as primary payload, when compiling a rom image that also
has grub, chainloading grub from the seabios menu instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-22 21:44:49 +01:00
Leah Rowe d4d5d2902c use backticks on eval commands, not subshells
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-22 13:46:20 +01:00
Leah Rowe c1527b6114 lib.sh: remove badcmd()
it's bloat. telling the user to rtfm is something that
we already do on irc; they will still ask how to do
everything, and ignore the message from badcmd(), or
they will automatically know to rtfm.

i'm on a massive purge, removing bloat from lbmk as
part of Libreboot Build System Audit 6.

all bloat must go.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-22 13:46:20 +01:00
Leah Rowe fc7ae3e590 lib.sh: more unified config handling
replace it with logic that simply uses "." to load
files directly. for this, "vcfg" is added as a variable
in coreboot target.cfg files, referring to a directory
in config/vendor/ containing a file named pkg.cfg, and
this file then contains the same variables as the
erstwhile config/vendor/sources

config/git files are now directories, also containing
pkg.cfg files each with the same variables as before,
such as repository link and commit hash

this change results in a noticeable reduction in code
complexity within the build system.

unified reading of config files: new function setcfg()
added to lib.sh

setcfg checks if a config exists. if a 2nd argument is
passed, it is used as a return value for eval, otherwise
a string calling err is passed. setcfg output is passed
through eval, to set strings based on config; eval must
be used, so that the variables are set within the same
scope, otherwise they'd be set within setcfg which could
lead to some whacky results.

there's still a bit more more to do, but this single change
results in a substantial reduction in code complexity.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-22 13:44:27 +01:00
Leah Rowe ad1602569e trees: more robust check to avoid "make fetch"
do not use shorthand here. the test was failing to
produce the desired result under some circumstances,
for example when i did "./update release" i got this:

make: Entering directory '/home/lbdev/lbmk/release/20240612-62-ga6b1a6bd/libreboot-20240612-62-ga6b1a6bd_src/src/stm32-vserprog'
make: *** No rule to make target 'fetch'.  Stop.
make: Leaving directory '/home/lbdev/lbmk/release/20240612-62-ga6b1a6bd/libreboot-20240612-62-ga6b1a6bd_src/src/stm32-vserprog'
ERROR script/trees: !mk src/stm32-vserprog fetch
ERROR ./update: excmd: script/trees -f
ERROR script/roms: Unhandled non-zero exit: ./update
ERROR ./build: excmd: script/roms serprog
ERROR ./update: build_release release/20240612-62-ga6b1a6bd: stm32
ERROR ./update: can't build rom images

in the above circumstance, run_make_command was executed,
which is not the desired behaviour; rather, fetch_project_trees
or fetch_project_repo should be called, and then the script
should immediately exit. it should also exit, without downloading
anything, if a changelog file exists as in release archives.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-21 03:10:46 +01:00
Leah Rowe a6b1a6bddb roms: fix lack of backslash on multi-line command
Signed-off-by: Leah Rowe <info@minifree.org>
2024-06-20 22:39:28 +01:00
Leah Rowe 8c4a918500 vendor.sh: more cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 04:04:42 +01:00
Leah Rowe 4711296841 Revert "roms: remove build_payloads() and split it up"
This reverts commit 3610667e3d.

The output of some functions in the roms script are used as
an argument in cp and mv commands, also cbfstool. I overlooked
this fact in a previous code optimisation.

Revert it. The change only reduced sloccount by a few lines
anyway.
2024-06-20 02:58:59 +01:00
Leah Rowe 5a4fc97c63 vendor.sh: correction (s/scancfg/scan_config)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 02:07:35 +01:00
Leah Rowe d65e4fac1d git.sh: revert modification to for loop
i tried to be clever with this one, but it just made
the script exit with an error.

revert back to the old check (check whether one of
either repo or repo backup is set)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 01:42:10 +01:00
Leah Rowe bc61c39ec8 vendor.sh: minor code cleanup
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 01:23:37 +01:00
Leah Rowe 808458ced5 minor code cleanup in the build system
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 01:15:06 +01:00
Leah Rowe 4ab99d546e git.sh: general code cleanup in fetch_submodule()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 00:57:10 +01:00
Leah Rowe cd1d847898 git.sh: reduced indentation on repo/file check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 00:51:04 +01:00
Leah Rowe 4f6dda1366 git.sh: simplified repo/backup check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 00:46:51 +01:00
Leah Rowe 185d76f57e roms: merge mkserprog() into main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-20 00:46:43 +01:00
Leah Rowe 893e88bc81 roms: don't insert timeout.cfg
this is bloat, because it's something the user can already
do at runtime configuration anyway.

set it to a reasonable default of 8 seconds instead of 5,
and don't honour the timeout variable in target.cfg.

this will be documented in the next release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 14:32:42 +01:00
Leah Rowe abfc799fd5 correction
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 14:20:09 +01:00
Leah Rowe a0da8fdef1 roms: reduce indentation in build_grub_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 14:11:54 +01:00
Leah Rowe 383433d4f6 roms: re-introduce accidentally disabled check
i disabled a check in the script, while testing a prior
modification. re-introoduce the check, which is put there
to yield an error condition if no targets were compiled.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 01:29:26 +01:00
Leah Rowe 3610667e3d roms: remove build_payloads() and split it up
payloads are compiled before coreboot, but it doesn't matter
to the build speed whether this is done first.

reduce the lines of code by checking payload builds *while*
adding them to the coreboot images. this means that coreboot
is now compiled first, before the payloads.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 00:42:01 +01:00
Leah Rowe 29a7123c0c roms: group some commands that are similar
this makes the build_payloads() function nicer to read

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 00:06:36 +01:00
Leah Rowe 2d6946775e roms: remove mt86bin variable
it's only meaningfully used once, so just hardcode
the string, which is not set dynamically anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-19 00:03:16 +01:00
Leah Rowe 920e5ba2d9 roms: merge build_uboot_payload to build_payloads
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 23:56:39 +01:00
Leah Rowe a96c4b59fd roms: simplify payload_uboot y/n check
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 23:49:28 +01:00
Leah Rowe 28682b1a4b roms: simplify the check for serprog srcdir
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 02:15:25 +01:00
Leah Rowe b61dd4c258 roms: simplify the loop for building serprog roms
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 02:09:26 +01:00
Leah Rowe 6df17860e2 roms: shorten variable serprog_boards_dir
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 02:00:47 +01:00
Leah Rowe ea5b5b0720 roms: simplified serprog image copy
use eval to avoid having two mv commands

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 01:50:40 +01:00
Leah Rowe ea9bdfce4b roms: rename picosrc variable to rp2040src
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 01:44:25 +01:00
Leah Rowe 1a4f97ffd1 roms: remove useless confirmation in mkserprogfw
the user knows where to look. replace it with a single
declaration.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 01:22:48 +01:00
Leah Rowe 1881d34dbc roms: merge serprog build into one function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-18 01:20:40 +01:00
Leah Rowe f7e28964ac roms: remind the user about gkb files
nowadays, we don't insert GRUB keymaps automatically, for
sake of efficiency; without one, the default is US QWERTY.

a user will only want one keymap in particular, so this
is more efficient. in practise, they're either building
from source anyway, or using the inject scripts which
compile cbfstool anyway, so the user will already have
cbfstool.

also output this message from the inject script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-17 15:50:22 +01:00
Leah Rowe f928ac5c70 roms: rename x variable to it in for loop
there are two for loops that use x as a variable anme,
and an idiosyncrasy of certain sh implementations is
that these become global;

the result in this case was that when you finish building
every target in "./build roms", it would print "libgfxinit"
repeatedly, comma separated, instead of a comma-separated
list of the targets that were built.

work around it by renaming the variable in one of the loops.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-17 01:05:28 +01:00
Leah Rowe 58a451865b roms: don't use x_ to call cproms()
cproms() never returns non-zero, so it doesn't make
sense to use x_ here

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 17:56:41 +01:00
Leah Rowe bc853fbb89 roms build_uboot_roms(): move rom, don't copy
that way, we don't have to delete the temporary file.
just move it entirely.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 17:50:42 +01:00
Leah Rowe 12b26f207f roms cproms(): allow other commands besides cp
e.g. the operator might specify mv instead

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 17:50:13 +01:00
Leah Rowe e67628c6a5 unify coreboot elfdir (DO_NOT_FLASH)
use a common string when setting this path

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 17:46:58 +01:00
Leah Rowe 8b58c1eac6 roms: merge mkUbootRom() into build_uboot_roms()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 17:42:34 +01:00
Leah Rowe c3f0a109c3 roms: simplify mkSeabiosRom()
remove variables that are not meaningfully used

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 12:54:07 +01:00
Leah Rowe c8944f1ca8 roms: simplify mkUbootRom()
remove variables that are not meaningfully used

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 12:51:47 +01:00
Leah Rowe 92aa83a236 roms: simplify build_roms()
cbcfg is already a global variable, so there's no reason
to set it again at the start of this function.

remove the check for whether the given coreboot config
exists, to the calling function instead of build_roms().

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 12:46:03 +01:00
Leah Rowe d3e7886450 roms: remove unnecessary check
uboot_config is later only used if payload_uboot is set

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 12:42:57 +01:00
Leah Rowe ef411c596a build: remove unused variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 12:38:47 +01:00
Leah Rowe 6dc0515583 roms: further clean up build_grub_roms()
the tmpcfg variable will be useful elsewhere, for
the same kind of change as before.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 01:11:46 +01:00
Leah Rowe 0e9b36c581 roms: simplify timeout/scandisk insertion
we don't need to call mktemp everytime.
just use a staticly named file in tmpdir
and keep overwriting it.

these files are only small, and they get deleted
when the build system exits later on.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 01:08:40 +01:00
Leah Rowe 3a7b3660f9 roms: simplify seagrub check in build_grub_roms
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 01:05:28 +01:00
Leah Rowe 4b764d26fd roms: simplify mkserprog()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 00:53:21 +01:00
Leah Rowe 167e7447a5 roms: simplify the serprog build functions
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 00:48:36 +01:00
Leah Rowe 7bc9fcc342 script/roms: fix serprog build commands
forgot to shift

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-16 00:40:57 +01:00
Leah Rowe 0dfe3aed91 roms: simplified ubootelf check
we check it twice, which we don't need to do.

we only need to check it once!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:58:27 +01:00
Leah Rowe a9166898d2 roms: simplify grubonly check in configure_target
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:43:02 +01:00
Leah Rowe 90017cdc56 roms: simplify seagrub check in configure_target
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:38:19 +01:00
Leah Rowe 817004e151 roms: don't use x_ to call build_grub_roms
build_grub_roms never returns a non-zero value

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:31:26 +01:00
Leah Rowe 0812d53212 trees: simplify copy_elf()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:15:27 +01:00
Leah Rowe 331c4097ff trees: remove unnecessary check in copy_elf
we don't need to check whether this variable is set,
because checking an empty path will also cause the
same return in the next line.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:15:27 +01:00
Leah Rowe 340eea0b1c grub: insert background in memdisk instead
the background is only a few kb. the whole rationale
before was to limit the space used in memdisk, but this
decision was made when the background was much bigger;
it has since been optimised greatly, and the grub modules
were heavily reduce, so it should be safe.

grub's memdisk breaks when you add too much data to it.
as part of simplifying the rest of lbmk, this change removes
some more bloat from the rest of lbmk. handling this in the
memdisk is much simpler than handling it with cbfstool.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:15:27 +01:00
Leah Rowe ed9c90e59d roms: unify all add-payload commands
add a generic function that can insert payloads with lzma
compression, or raw files without compression

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 23:15:25 +01:00
Leah Rowe 26451775d5 roms: don't add grub keymaps at all
if not inserted, the default keymap is usqwerty.

don't waste ssd write cycles copying so many images,
or cpu time compressing so many. the user can simply
add a keymap.gkb file to cbfs and it will work fine.

this will be documented in the next release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-15 18:35:20 +01:00
Leah Rowe af8296ce6b roms: merge handle_coreboot_target into main()
rely on return status per each of the three main rom
functions, to then update the "targets" variable.

use this as the basis to determine which targets were
built, during final confirmation when the script exits.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 16:34:05 +01:00
Leah Rowe d1c0c34642 roms: simplify target check (whether roms built)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 16:26:49 +01:00
Leah Rowe f626b25db3 roms: simplify main() again
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 14:51:30 +01:00
Leah Rowe eb9a688ee3 roms: remove redundant check on grub_scan_disk
the current validation check is extremely over-engineered,
because the user override is no longer available and we're
always very careful in how we modify target.cfg per board.

remove the redundant code. trust that target.cfg is correct.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 14:51:30 +01:00
Leah Rowe a4328cb11f roms: remove dangerous runtime p/s/d options
p = payload

s = grub_scan_disk

d = displaymode

setting the payload is no longer safe, due to issue 216
and similar issues that might pop up in the future; it's
best left only to target.cfg, per board, so that we know
what config is safe/tested. don't let the user override it.

scandisk isn't safe to override because the given machine
may not have the type of device that the user specifies

displaymode is actually ok to set, because it simply whitelists
what configs pre-existing to actually use, but it's bloat

basically, the rule is this:

don't make it easy for the user to brick their hardware.
make it harder instead.

a user wily enough to go modifying their payload will probably
have read docs/maintain/ anyway and knows how to edit target.cfg
if they want another board configuration.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 14:51:27 +01:00
Leah Rowe 167e1a0fbe unified checks for variable initialisation
new function chkvars() does the job

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 13:37:03 +01:00
Leah Rowe 98724d701b lib.sh: remove the items() function
it's pretty much just doing the same thing as ls -1

remove it!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 13:19:25 +01:00
Leah Rowe baea03c672 roms: simplify main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-14 09:11:07 +01:00
Leah Rowe c8889b8d2c Libreboot 20240612 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-12 08:43:33 +01:00
Leah Rowe 67c95fc72d coreboot nasm: use coreboot mirror as backup
don't use the macports mirror, because it's not certain
whether those tarballs will always be there. use the
coreboot one as a backup instead, and nasm.us as main

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-12 07:50:05 +01:00
Leah Rowe 79d5d83412 haswell: add Mate's patch fixing IGD port list
fixes DP++ and adds a DP that wasn't even there before,
on all currently supported variants of these machines

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-12 07:39:14 +01:00
Leah Rowe 61a8f4b05e haswell: add Nico's patch for IGD PCI IDs
the patch fixes IGD on certain xeon processors

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-12 07:36:43 +01:00
Leah Rowe 0b37653ab9 grub: only enable nvme if needed on a board
remove nvme support from the "default" grub tree

now there are three trees:

* default: no xhci or nvme patches
* nvme: contains nvme support
* xhci: contains xhci and nvme support

this is in case a bug like lbmk issue #216 ever occurs
again, as referenced before during lbmk audit 5

there is no indication that the nvme patch causes any
issues, but after previous experience i want to be sure

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-12 00:58:22 +01:00
Leah Rowe 1952db5554 fix nasm download path for coreboot/fam15h
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-11 10:44:49 +01:00
Leah Rowe 2ee186aee3 minor code cleanup in the build system
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 18:48:58 +01:00
Leah Rowe c5441bb9f5 re-add ability to use cbfs grub.cfg as default
i removed this before, when making grub multi-tree,
because the design i used in an earlier version of
the patch actually added the grub.elf generation
to grub source itself, but then i decided to hack
around the grub build system from lbmk/cbmk instead

re-add this functionality, so that users can easily
insert their own custom grub.cfg into cbfs without
needing to re-build their image.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 16:06:07 +01:00
Leah Rowe d33556c6ae trees: exit with error if project undefined
i was originally looser about this, because i also wanted
the trees script to generically run "make" from any
directory, but this behaviour was error-prone and it is
no longer used in the build system.

disable it, in the interest of stability.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 15:58:09 +01:00
Leah Rowe 1799a33663 build: also make a lock file during release build
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 15:52:35 +01:00
Leah Rowe 78426a97e5 lib.sh: more useful lock message
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 15:44:20 +01:00
Leah Rowe e80c4b73ce create a lock file during builds
prevent duplicate main instances of the build
system from running

the lock file is deleted when the parent process
exits, alongside the tmpdir deletion

the build system must only ever be run ot one
instance at a time, per work directory

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 15:37:13 +01:00
Leah Rowe a0710ef9ca git.sh: hide e() output on for loop
this for loop is a hack to make sure that all the
sources get nuked (using nuke.list files).

hide the messages so that they do not appear when
running just any command in the trees script.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 15:27:03 +01:00
Leah Rowe 86eb566b13 lib.sh: fix regression
i was being a bit too clever about some optimisations

revert this change. otherwise, nothing will download
or build

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 15:23:50 +01:00
Leah Rowe fbcdf33f93 git.sh: download xtree *before*, not after
downloading it after means that if an error occurs
when downloading the xtree project, the main project
will still be there and nothing will mandate the
downloading of the xtree project. whereas, if we
grab the xtree project first, then the main project
won't get saved to src/

this makes the build system a bit more resilient under
fault conditions, but otherwise doesn't change behaviour.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 11:55:30 +01:00
Leah Rowe 6a3d8a9600 git.sh: fix deletion path in nuke()
i accidentally forgot to include src/ in the prefix

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 11:43:47 +01:00
Leah Rowe 3478b28821 lib.sh: less confusing error in download()
don't say "file missing", because it may be present!

instead, say that the download failed. this covers both
contexts: internet failed and thus no file present, or
the file is present but checksum verification failed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 11:07:07 +01:00
Leah Rowe f3f5b99cec lib.sh: hide stderr on download()
on the initial check, the output is confusing because
it will say "checksum verification failed" if the
file doesn't already exist, but then goes to download.

only say checksum failed if a download occured, and the
check failed, otherwise report nothing except that the
file already exists.

this will not reduce the ability to debug issues later
on, and it will reduce the amount of confusion for users.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 11:04:25 +01:00
Leah Rowe 3440e1f651 lib.sh: simplify download()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 11:04:08 +01:00
Leah Rowe 75b39dbeb1 lib.sh: fix redundancy in download()
it was only downloading the main url, even when
it should use the backup.

fix it by actually using the for loop variable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 10:58:19 +01:00
Leah Rowe 26df6e7ab2 lib.sh: simplify singletree()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 10:55:33 +01:00
Leah Rowe 9cdf419295 git.sh: further simplify nuke()
it's a very compact nuke

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 10:49:58 +01:00
Leah Rowe 1cede024d6 git.sh: simplify link_crossgcc()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 10:48:28 +01:00
Leah Rowe 77e482aae6 git.sh: simplify nuke()
do not over-engineer such a trivial thing.

seriously. all we're doing is nuking some files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 10:42:10 +01:00
Leah Rowe 42e979509b Merge pull request 'Add dependency scripts for Fedora 40 and Ubuntu 24.04' (#220) from fuel-pcbox/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/220
2024-06-09 06:42:26 +00:00
Leah Rowe a0eb79dfd8 add crossgcc tarballs to config/submodules/
support redundant downloads, and enable inclusion of these
tarballs inside release archives, for offline builds.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-09 06:55:25 +01:00
Leah Rowe b0d1ad32fa git.sh: support downloading *files* as submodules
when we download coreboot, we currently don't have a way to
download crossgcc tarballs, so we rely on coreboot to do it,
which means running the coreboot build system to do it; which
means we don't get them in release archives, unless we add
very hacky logic (which did exist and was removed).

the problem with coreboot's build system is that it does not
define backup links for each given tarball, instead relying
on gnu.org exclusively, which seems OK at first because the
gnu.org links actually return an HTTP 302 response leading
to a random mirror, HOWEVER:

the gnu.org 302 redirect often fails, and the download fails,
causing an error. a mitigation for this has been to patch the
coreboot build system to download directly from a single mirror
that is reliable (in our case mirrorservice.org).

while this mitigation mostly works, it's not redundant; the
kent mirror is occasionally down too, and again we still have
the problem of not being able to cleanly provide crossgcc
tarballs inside release archives.

do it in config/submodules, like so:

module.list shall say the relative path of a given file,
once downloaded, relative to the given source tree.

module.cfg shall be re-used, in the same way as for git
submodules, but:

subfile="url"
subfile_bkup="backup url"

do this, instead of:

subrepo="url"
subrepo_bkup="backup url"

example entries in module.list:

util/crossgcc/tarballs/binutils-2.41.tar.xz
util/crossgcc/tarballs/gcc-13.2.0.tar.xz
util/crossgcc/tarballs/gmp-6.3.0.tar.xz
util/crossgcc/tarballs/mpc-1.3.1.tar.gz
util/crossgcc/tarballs/mpfr-4.2.1.tar.xz
util/crossgcc/tarballs/nasm-2.16.01.tar.bz2
util/crossgcc/tarballs/R06_28_23.tar.gz

the "subrev" variable (in module.cfg) has been renamed
to "subhash", so that this makes sense, and that name is
common to both subfile/subrepo.

the download logic from the vendor scripts has been re-used
for this purpose, and it verifies files using sha512sum.
therefore:

when specifying subrepo(git submodule), subhash will still
be a sha1 checksum, but:

when specifying subfile(file, e.g. tarball), subhash will
be a sha512 checksum

the logic for both (subrepo and subfile) is unified, and
has this rule:

subrepo* and subfile* must never *both* be declared.

the actual configuration of coreboot crossgcc tarballs
will be done in a follow-up commit. this commit simply
modifies the code to accomodate this.

over time, this feature could be used for many other files
within source trees, and could perhaps be expanded to allow
extracting source tarballs in leiu of git repositories, but
the latter is not yet required and thus not implemented.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-08 05:44:53 +01:00
Leah Rowe 1a44fcfacf git.sh: remove unnecessary line break
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-08 02:17:23 +01:00
Leah Rowe 74ae84afba vendor.sh: add a return at the end of mkdirs
i don't like that it's not there, because of the quirks
in sh behaviour. put it there to put my mind at ease.

otherwise, this doesn't change any behaviour.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-08 01:59:46 +01:00
Leah Rowe c202dc612e vendor.sh: move download logic to lib.sh
in future revisions, i will make tarballs become subfiles,
to complement submodules. e.g. crossgcc tarballs in coreboot

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-08 01:55:15 +01:00
Leah Rowe 08d0a1d5d8 lib.sh: shorten a string in e()
line exceeds 80 characters

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-08 01:22:21 +01:00
Leah Rowe 9b00b30a4f move uefiextract to elf/uefitool/
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 21:30:43 +01:00
fuel-pcbox 046007b466 Add dependency scripts for Fedora 40 and Ubuntu 24.04 2024-06-07 13:02:40 -05:00
Leah Rowe 05d301bdee git.sh: fix submodule path
i accidentally cloned to tmpdir rather than tmpgit

oops!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 16:54:05 +01:00
Leah Rowe 7e15859be6 git.sh: simplify prep_submodules()
copying the module list into tmpdir/ no longer makes sense,
because it was only done before when we supported either
running the list from "git submodule update", or module.list.

since we only support handling of module.list, we can
greatly simplify this function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 16:28:01 +01:00
Leah Rowe acd3608bb1 git.sh: unified handling of git clone/reset/am
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 16:19:43 +01:00
Leah Rowe 668bcbf69c trees: simplified copy_elf() handling
don't create elfdir, create dest_dir, which is elfdir
plus the location within it

only create dest_dir within copy_elf, which is only
called if actually compiling the code

this avoids creating empty elf directories, and it
generally cleans up all handling, unifying the
handling of directories into a single function,
namely copy_elf() which already exists

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 15:04:24 +01:00
Leah Rowe 3eef7f37f2 git.sh: simplify submodule handling
there were stragglers remaining, from when we used to
actually run "git submodule update", but this was removed.

clean up the submodule functions and merge them together.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 14:40:59 +01:00
Leah Rowe 4b1b1f5098 git.sh: provide feedback for repository downloads
otherwise, it's not clear to the operator what's happening

i'm normally against such verbose feedback, because it's bloat,
but this minimal amount of feedback will make the build system
more pleasant to use, especially during testing.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 14:25:01 +01:00
Leah Rowe d43247683b git.sh: download "depend" projects *before*
don't do it after, because that means the main project
is saved under src/ before we know whether the subrepo
was downloaded.

the "depend" variable (in config/git/) is no longer used
for projects that go in subdirectories of a parent; now,
we use config/submodules/ for this type of dependency.

download the "depend" projects (as per config/git/) first.
this way, if they fail, the main one will fail, but if
they succeed and main fails, you can just run the main
download again and it won't fail.

this fixes a bug where, depending on how you download a
set of projects and depending on the order which you do so,
a given project can become un-downloadable on current design,
because git will complain that a directory already exists.

this fix is done not only in code (by this commit), but
by prior configuration changes.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 14:16:58 +01:00
Leah Rowe a4549e935e git.sh: reduced indentation in fetch_submodule
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 12:58:28 +01:00
Leah Rowe 11c47ba7dd git.sh: reduced indentation in prep_submodules
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 12:55:30 +01:00
Leah Rowe 9c1ea8f93a git.sh: *never* run git submodule update
only use config/submodules/ which the build system then
uses to run git clones manually, replicating the submodules
feature. we must never use a project's own gitmodules feature,
because we can't easily control it. better to let it break first,
and then figure out what modules to add manually, so that we
have only what we need for each project.

it's done this way, because git's own submodules feature
doesn't have very good error checking in general, nor
does it have good redundancy.

with the current design, we can declare backup repositories
for each submodule.

we replicate it precisely. for example:

3rdparty/vboot

this is a coreboot submodule, and we handle that in the
coreboot trees.

however, our current design also allows you to do this even
if the upstream repository does not contain a .gitmodules file

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 12:52:52 +01:00
Leah Rowe 137321ebc0 lib.sh: rename variable for clarity
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 12:50:16 +01:00
Leah Rowe 7bfb1d621f trees: don't check empty path in copy_elf()
it could lead to some whackiness later on

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 12:04:28 +01:00
Leah Rowe 0b7566cb78 trees: fix build issue caused by bad elf check
we're not checking for bad elfs, but the check itself was bad

due to a quirk in how sh works. really, really obscure bug.

fixed now!

if the given directory didn't actually exist, or there were no
files in it, it'd be searching for the file named "*"

which is obviously wrong

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 11:29:36 +01:00
Leah Rowe 7aa9f22409 trees: fix listfile check in copy_elf()
don't check that the variable is empty

check that the file itself exists or not

this should fix the recent build issues

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 10:35:38 +01:00
Leah Rowe 06c78e1321 trees: don't say check elf/ if build.list missing
(on single tree projects. this complements the last patch)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 10:32:39 +01:00
Leah Rowe dea41f138a trees: don't do elfcheck if build.list missing
otherwise, some checks are done too soon, and nothing
gets built.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 10:31:01 +01:00
Leah Rowe 3bd562a265 define mdfiles/images in config/submodules/docs/
again: the "depend" variable must never be used for subprojects
that point to a subdirectory of the main project, because there's
no clean way of handling this in case of error conditions.

make it a submodule under config/submodules/. this is for the
documentation, including static site generator documentation,
and image files (photos).

as of this revision, there are now only those "depend" projects
defined in config/git/, where the destination directory of the
subject is not a subdirectory of the main project, so:

in a subsequest revision, i will mitigate an existing bug whereby
failure of the dependency project leaves the main one still
intact, breaking builds; this revision enables that to be done.

from now on, subproject-to-subdirectory-of-main-project will
be avoided in config/git/; config/submodules/ will be used.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 01:01:44 +01:00
Leah Rowe bff7562819 libopencm3 to config/submodules/ on stm32-vserprog
same as the previous patch, we must no longer use "define"
variables in config/git/ when the path is a subdirectory of
a given project, because it means that the download can only
happen after the main one, and currently if that fails, the
download of the main repo would remain intact, breaking future
builds in ways that we can't control - to be clear, it could
be controlled, but with added code complexity in the build
system, so:

put it in config/submodules/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 00:47:06 +01:00
Leah Rowe d9b9f6db75 add tinyusb to config/submodule/ for pico-sdk
don't define it as a "depend" variable in config/git/,
because it means putting the files in a subdirectory of
an existing project was was already then downloaded, and
that means it can't be downloaded first; if the download
of it fails, the old download is left intact.

this bug isn't currently fixed in the build system, at all,
so this and other patches are being made to mitigate it.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 00:38:51 +01:00
Leah Rowe 099ee3f4a1 config/git: use "depend" for serprog dependencies
this brings the handling of serprog projects in sync
with canoeboot, which relies on the "depend" variable
to get the needed submodules, because cbmk does not
download submodules for these projects

lbmk does download submodules. i want it in sync with
cbmk for this, to make merging easier between both
projects, because i'm going to make a change on both
projects, whereby config/submodules/ is used exclusively

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-07 00:22:48 +01:00
Leah Rowe d0f99c2f98 trees: unified coreboot makeargs
in particular, the coreboot build system may auto-download
submodules when building cbfstool; vboot for instance.

we do not want such unpredictable behaviour, so now we
use UPDATED_SUBMODULES=1 when building coreboot utilities.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 22:21:59 +01:00
Leah Rowe a7889c5af8 trees: use multiple threads to build cbutils
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 22:20:09 +01:00
Leah Rowe d41658f17e move handle_coreboot_utils to script/trees
it doesn't really make sense placed in lib.sh,
because it's only called from script/trees

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 22:17:16 +01:00
Leah Rowe c0822ac458 put coreboot utils in elf/, not cbutils/
one directory per util, under elf/

e.g. elf/cbfstool/

further split by tree name, e.g.:

elf/cbfstool/default/
elf/cbfstool/foo/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 21:51:37 +01:00
Leah Rowe d1ba085153 fix build issue building coreboot utils
just run make directly. the trees script isn't really
designed to directly build directories, so don't.

nothing wrong with good old fashioned make -C

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 21:33:22 +01:00
Leah Rowe 7e49fe4b9b trees: skip single-tree build if a build exists
this replicates the same behaviour as multi-tree builds,
checking for files inside the relevant elf/ directory

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 09:20:45 +01:00
Leah Rowe 1277427478 use correct memtest86plus path in script/roms
the previous change makes memtest.bin get cached in elf/
but the path was being prefixed with src/ by script/roms

do away with the prefix

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 09:11:39 +01:00
Leah Rowe 8511615e1f put memtest86plus builds in elf/memtest86plus/
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 09:05:16 +01:00
Leah Rowe 176b936da2 put flashprog builds in elf/flashprog/
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 09:05:00 +01:00
Leah Rowe 48cbb30db1 trees: also print "DONE! check elf/dir" on single
e.g. ./update trees -b flashprog

tell the user to check elf/flashprog

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 08:53:29 +01:00
Leah Rowe 315fed5f48 trees: handle build-test on multi-tree projects
for example, now flashprog binaries could be placed
in the elf/ directory, under elf/flashprog/

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 03:13:52 +01:00
Leah Rowe b8112af953 git.sh: use singletree() to decide submodules
now it no longer hardcodes a check for whether the
project name is coreboot. this maintains the same
behaviour but will now work for other multi-tree
projects; in practise, the other multi-tree projects
did not use .gitmodules files anyway, but some of
them used config/submodules/ in our build system.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 02:49:38 +01:00
Leah Rowe 78f7e429ec move cbcfgsdir variable to vendor.sh
it's only ever used here

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 02:45:09 +01:00
Leah Rowe 810ad480da move cfgsdir/datadir variables to lib.sh
it's also used from script/roms, in addition to trees

move these variables to a common file used everywhere

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 02:43:27 +01:00
Leah Rowe ba36f26d62 handle build.list from config/data/, not config/
certain code checks for build.list, to skip it, for
example in items()

we already use config/data/grub to store grub config data
that applied to all trees

create these directories too:

config/data/coreboot
config/data/u-boot
config/data/seabios

move the respective build.list files in here, and also
to config/data/grub

now multi-tree projects contain, per directory, just the
target.cfg file and the patches directory. this is much
cleaner, because some of the logic can be simplified more

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 02:35:36 +01:00
Leah Rowe bea089bbe4 don't use build.list to detect multi-tree projects
instead, check for the presence of target.cfg files
not in config/project/ but config/project/tree/

the way this check is done, it merely returns 1 if
config/project/*/target.cfg is detected, and returns
0 in all other cases, even if config/project/target.cfg
exists

that way, if the maintainer accidentally adds a
target.cfg in the main directory, the given multi-tree
project will not break

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-06 01:01:22 +01:00
Leah Rowe 6e1b8087c5 move id check to lib.sh too
doesn't really matter, it's just an extra layer to ensure
reliability, but "id" is pretty standard

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-05 11:26:08 +01:00
Leah Rowe 62c25ac7ab move root check to lib.sh (bugfix)
this avoids writing the version/versiondate files as root.

this complements the previous fix, that avoided writing those
same files when running the dependencies command.

initial setup of the build system requires root, to run the
dependencies script, but otherwise the build system prevents
running as root for everything else, so we must avoid writing
the version/versiondate files as root.

that same avoidance is necessary when checking whether running
other commands as root; ironically, this check then prevented
running the build system at all!

the bug should be fully fixed now. i found this quite by accident
the other day, when testing something else.

good thing this got fixed because the release!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-05 11:11:01 +01:00
Leah Rowe 75382a4126 bugfix: move dependencies handling to lib.sh
do it strategically, in just the right place so that the
version and versiondate files aren't written.

otherwise, version/versiondate are written as root and
the build system becomes unusable after that, unless you
reset the file ownerships from root. hardly user-friendly.

mitigate this bug.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-05 11:07:53 +01:00
Leah Rowe c6aff76931 bump untitled revision again
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-04 14:16:43 +01:00
Leah Rowe 414a605ab3 bump untitled revision in git config
it imports the same environmental variable fix because
i had the same buggy TMPDIR check there. i fixed that
upstream in untitled.

import the new untitled revision.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-04 14:05:11 +01:00
Leah Rowe 7d562679be lib.sh bugfix: check environmental variables right
A user had TMUX_TMPDIR set, which broke the TMPDIR check

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-04 13:57:32 +01:00
Leah Rowe 53dd4bc4dd lib.sh: more friendly output from e()
already of saying "found", say "already exists"

this means the output of these commands more user
friendly and intuitive:

./update trees -b grub default
./update trees -b coreboot i945

this is just an example. when an ELF file already
exists, the build is skipped even if src isn't downloaded.

this design is intentional, because it means that you can
use previous builds if you want to save time on another.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-03 11:07:07 +01:00
Leah Rowe c2793e7a5e badcmd: don't print "no context given"
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-03 08:26:04 +01:00
Leah Rowe 49ae4f91f9 badcmd: link directly to the maintenance manual
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-03 08:25:04 +01:00
Leah Rowe 00653aab1e better help text on invalid commands
adding help again is a bad idea. code should never
document itself; that's what documentation is for.

so, make the code do a better job telling the user
where to find documentation.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-03 00:17:36 +01:00
Leah Rowe afac9a06d2 build: print the project website address on help
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-02 23:34:10 +01:00
Leah Rowe 1e534e7dda add projectsite file: point to libreboot.org
this will be used in subsequent revisions

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-02 23:15:27 +01:00
Leah Rowe 429e91f908 make GRUB multi-tree and re-add xhci patches
Re-add xHCI only on haswell and broadwell machines, where
they are needed. Otherwise, keep the same GRUB code.

The xHCI patches were removed because they caused issues
on Sandybridge-based Dell Latitude laptops. See:
https://codeberg.org/libreboot/lbmk/issues/216

The issue was not reported elsewhere, including on the
Haswell/Broadwell hardware where they are needed, but the
build system could only build one version of GRUB.

The older machines do not need xHCI patches, because they
either do not have xHCI patches, or work (in GRUB) because
they're in EHCI mode when running the payload.

So, the problem is that we need the xHCI patches for GRUB
on Haswell/Broadwell hardware, but the patches break
Sandybridge hardware, and we only had the one build of GRUB.
To mitigate this problem, the build system now supports
building multiple revisions of GRUB, with different patches,
and each given coreboot target can say which GRUB tree to use
by setting this in target.cfg:

grubtree="xhci"

In the above example, the "xhci" tree would be used. Some
generic GRUB config has been moved to config/data/grub/
and config/grub/ now looks like config/coreboot/ - also,
the grub.cfg file (named "payload" in each tree) is copied
to the GRUB source tree as ".config", then added to GRUB's
memdisk in the same way, as grub.cfg.

Several other design changes had to be made because of this:

* grub.cfg in memdisk no longer automatically jumps to one
  in CBFS, but now shows a menuentry for it if available

* Certain commands in script/trees are disabled for GRUB,
  such as *config make commands.

* gnulib is now defined in config/submodule/grub/, instead
  of config/git/grub - and this mitigates an existing bug
  where downloading gnulib first would make grub no longer
  possible to download in lbmk.

The coreboot option CONFIG_FINALIZE_USB_ROUTE_XHCI has been
re-enabled on: Dell OptiPlex 9020 MT, Dell OptiPlex 9020 SFF,
Lenovo ThinkPad T440p and Lenovo ThinkPad W541 - now USB should
work again in GRUB.

The GRUB payload has been re-enabled on HP EliteBook 820 G2.

This change will enable per-board GRUB optimisation in the
future. For example, we hardcode what partitions and LVMs
GRUB scans because * is slow on ICH7-based machines, due
to GRUB's design. On other machines, * is reasonably fast,
for automatically enumerating the list of devices for boot.

Use of * (and other wildcards) could enable our GRUB payload
to automatically boot more distros, with minimal fuss. This
can be done at a later date, in subsequent revisions.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-02 19:58:50 +01:00
Leah Rowe 9daf7f05f1 u-boot on qemu: remove currently unused x86 target
it doesn't build, at present, but isn't used by any
coreboot targets, so the build issue does not come up
during release builds, but i did find it laying around
during my audits.

x86 qemu is on todo for libreboot, on all x86 boards,
but the current config is broken, so: remove it.

it's very much a requirement that anything in lbmk should
work.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-01 22:55:19 +01:00
Leah Rowe 6d59f1d0be grub.cfg: scan /boot/grub.cfg last
very unlikely to exist. in fact, should i remove it?

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-01 18:12:40 +01:00
Leah Rowe 2becc736d3 grub.cfg: scan grub2/ last
it's very unlikely that someone would use this
directory name nowadays, and i had half a mind
to remove it altogether

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-01 18:12:40 +01:00
Leah Rowe cfc5265f5b grub.cfg: search a reduced list of devs/partitions
in practise, the machines we support don't have
the option of including so many disks; 8 seems like
the most reasonable default. additionally, it's
unreasonable to expect *20 partitions*

this hardcoding is done to avoid using *, which is
slow in grub on some machines (the grub kernel always
re-enumerates the devices during every operation,
without caching any of it)

yet, the hardcoding is also slow; balance it a bit
better by searching fewer permutations, but not so few
that it would likely break a lot of setups

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-01 18:12:40 +01:00
Leah Rowe 42b5b58d36 grub.cfg: scan grub.cfg from ESP
we already supported syslinux but not grub

support grub by scanning for the most common paths,
based on the most popular distros

we don't hardcode this with * because it slows down
the boot, and in practise many distros still use the
same grub.cfg location as in BIOS systems (the EFI
one is often just a link to the BIOS one)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-01 18:12:40 +01:00
Leah Rowe b3d58f1edc grub.cfg: split up try_user_config
in the next revision, i will add ESP paths

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-01 18:12:40 +01:00
Leah Rowe 2ea5e61cfd grub.cfg: don't search for *_grub.cfg
this is a relic from the old days when we didn't
automated the grub.cfg logic as much. these days,
the grub.cfg logic is able to boot almost all distros
without any manual intervention or override.

removing these entries will speed up the boot in general

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-01 18:12:40 +01:00
Leah Rowe c742a89dad grub.cfg: remove unnecessary path for isolinux
the path "/boot/EFI" is unnecessary because the ESP
is always a FAT32 partition, so we don't need to
scan it as a subdirectory within a subdirectory.

the ESP is always mounted as its own partition,
FAT32, and EFI/ is always at the root of it

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-01 18:12:40 +01:00
Leah Rowe e0b2216f64 grub.cfg: don't scan EFI on btrfs subvols
the esp is always a fat32 partition so this makes no sensgrub.cfg: don't scan EFI on btrfs subvols

the esp is always a fat32 partition so this makes no sense

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-06-01 18:12:40 +01:00
Leah Rowe 38135f9e22 Merge pull request 'Fix building vboot on i686' (#218) from lukeshu/lbmk:lukeshu/i686 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/218
2024-06-01 17:07:23 +00:00
Leah Rowe a76dda9330 vendor.sh: remove unnecessary assignment
dl_fail is set to n and then immediately to y afterward

why?

clearly i was dehydrated

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-31 17:27:13 +01:00
Luke T. Shumaker 221206b4da Fix building vboot on i686 2024-05-30 17:40:37 -06:00
Leah Rowe 17a9d11da1 git.sh: do not remove .submodules
the reason for it is because sometimes the coreboot build
system auto-downloads submodules which we don't want.

however, we now pass UPDATED_SUBMODULES=1 in make, which
disables this behaviour in coreboot's build system.

therefore, remove this unnecessary logic.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-30 07:50:58 +01:00
Leah Rowe 13d4b6d3c7 delete u-boot test/lib/strlcat.c using nuke()
we don't need to do it in the release function

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-30 07:37:19 +01:00
Leah Rowe f6cbc501c1 import nuke() from cbmk cdce8ba70b
cbmk revision:
cdce8ba70b863ea3fe0ad7a4d7b27d0c5ca30421
as of date 30 May 2024

Canoeboot provides deblobbing, fully, on all sources, so
as to provide a GNU FSDG compliant coreboot distro.

Libreboot used to do this but now uses a more pragmatic
Binary Blob Reduction Policy, allowing better hardware
support in general. See:

https://libreboot.org/news/policy.html

Well! We sometimes still need to delete files in Libreboot,
but for other reasons. For example, the poorly licensed
strlcat.c file that we delete from U-Boot, in both projects.

I currently hardcode such deletions in lbmk. After this
revision, I will start using "nuke.list" files as in cbmk.

Simply patching the sources to exclude such files, in this
context, is not OK because then we are still including them
but as diffs. This is why the nuke() function exists.

Import Canoeboot's nuke technology.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-30 07:29:50 +01:00
Leah Rowe 7fbcb7be95 coreboot t440p/w541: enable nvme in grub_scan_disk
these laptops do not officially have nvme slots on them,
but there is an ngff wifi slot which is PCI-E x1, and you
can use a special adapter on it to run nvme ssds.

total throughput is retarded by the x1 PCI-E configuration,
but it's still faster than a sata ssd (nvmes are x4 PCI-E).

support it in grub_scan_disk on the off chance that some
users may make use of this. it should work just fine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-29 23:42:48 +01:00
Leah Rowe 47f582d463 ./vendor download: skip if blob path is /dev/null
We use a path of /dev/null pointing to a ROM for
Fam15h AMD boards, to add fake PIKE2008 images.

This is to mitigate a hang in SeaBIOS, but now with
recent changes, this causes the command below to
download coreboot, when it should just exit saying
no vendor files needed. Prevent accidentally wasted
bandwidth. The command was:

./vendor download kcma_d8_rdimm_16mb

This now correctly does the following:
$ ./vendor download kcma_d8_rdimm_16mb
Vendor files not needed for: kcma_d8_rdimm_16mb

The joys of programming a build system in sh!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-29 03:25:33 +01:00
Leah Rowe e7cb10d68b do not allow dashes in coreboot target names
Command: ./vendor download kcma-d8-rdimm_16mb

Output was:

include/lib.sh: line 115: kcma-d8-rdimm=config/vendor: No such file or directory

That will have to be audited later on, but the recent
more stringent error checking in vendor.sh triggered
this previously untriggered error message. The error
was in fact already occuring before, silently.

Anyway, mitigate by renaming all coreboot targets so
that they do not contain hyphens in the name. This
should avoid triggering errors in that eval command,
on line 115 in lib.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-29 03:15:25 +01:00
Leah Rowe e9b9e825f1 ./vendor download: more fine-tuned error control
By default, the build system does set -u -e

Some errors are unavoidable and have to be handled, so
we have to set +u +e (turn off error handling in sh),
when downloading vendor files, but only certain parts of
vendor.sh trigger errors (which cause an exit).

Replace the current bazooka approach with a more fine
grained approach, turning error handling back on again
when it is safe to do so.

In the parts of the code where it is disabled, the code
is written very, very carefully, with errors still handled
manually, but more careful auditing is required.

This change has been tested and makes the command much
safer to run. In security (or any bug auditing), it is
the principle of least privilege that holds true.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-29 02:07:38 +01:00
Leah Rowe 0dd0dfaf3d vendor.sh: don't error on main targets
e.g. coreboot/default contains no config directory, so
the old logic would be trying to do:

.

which is obviously invalid

now for example:

$ ./vendor download default
Vendor files not needed for: default

and it will exit with zero status

the only thing that should ever return non-zero status
is when you define a target that does not exist, config
or no.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-29 00:48:18 +01:00
Leah Rowe a4bd49ded6 roms: allow user override of grub_scan_disk
this effectively lets you change the boot order. example:

./build roms -s "nvme ata" t1650_12mb

the above example would set:
grub_scan_disk="nvme ata"

another example:

./build roms -s nvme t1650_12mb

this would set:
grub_scan_disk="nvme"

this overrides what's set in target.cfg for the given
target. useful for quick reconfiguration if building
from source

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-28 23:47:13 +01:00
Leah Rowe b00800a7cc grub.cfg: actually support setting boot order
replace variables ahcidev/atadev/nvmedev with a single
one named bootdev

the for loop goes through grub_scan_disk, so now it is
effectively a bootorder configuration

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-28 23:19:23 +01:00
Leah Rowe 4488745cb6 trees: use CPUS=x on regular coreboot make
i already do this on crossgcc, but overlooked it on regular
builds where i just use -j, but coreboot's build system
makes use of the CPUS= option in make

use XBMK_THREADS for this

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-28 19:57:35 +01:00
Leah Rowe 7d50e09fea update gitignore
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-28 06:43:16 +01:00
Leah Rowe b78f62c78b roms: fix bad eval when comparing options
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-28 01:23:43 +01:00
Leah Rowe b11e4c9f3e grub.cfg: add spdx header
it has always been gpl 3 or later, but it helps to have
the license declaration within the file

there's a copying file anyway. put spdx in the config

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-27 22:41:34 +01:00
Leah Rowe 3998a3ba48 re-configure grub_scan_disk on various targets
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-27 21:33:53 +01:00
Leah Rowe 1c4d649848 remove grub_scan_disk in all target.cfg files
A subsequest revision will set them again as needed,
per coreboot target.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-27 20:41:11 +01:00
Leah Rowe e1883f1d5a grub.cfg: use grub_scan_disk to set boot order
Previously, grub_scan_disk could set ata, ahci or "both",
which would make both be tried (ahci first). This worked
when we only dealt with ata and ahci devices, but now we
support nvme devices so the logic is inherently flawed.

Instead, use grub_scan_disk to store the boot order, e.g.:

grub_scan_disk="ahci nvme ata"

grub_scan_disk="nvme ata"

In the first example, it would make GRUB scan ahci first,
then nvme and then ata.

In the secontd example, it would make GRUB scan nvme first,
and then ata.

If "both" is set, or anything other than ahci/ata/nvme,
grub_scan_disk is now changed to "nvme ahci ata".

Actual grub_scan_disk entries in target.cfg files will now
be modified, to match each machine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-27 20:36:58 +01:00
Leah Rowe c94cecd837 GRUB: remove XHCI patches for now (will re-add)
Fixes this bug:
https://codeberg.org/libreboot/lbmk/issues/216

Well, fix is the wrong word. We want xHCI ideally.

Mate is working on it as I write this. I've also:

* Disabled CONFIG_FINALIZE_USB_ROUTE_XHCI on Haswell
  boards (coreboot)
* Disabled the GRUB payload on HP 820 G2 for now

We will need to re-add the xHCI patches once fixed.
If Mate/we can't fix it, I'll contact Patrick
Rudolph who originally wrote the xHCI patches.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-27 17:11:33 +01:00
Leah Rowe ff2997d6ec minor correction
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-27 15:05:33 +01:00
Leah Rowe d855408a58 roms: make grubfirst if seabios_withgrub=y
rather than if seabios_grubonly=y

if grubonly=y, still make the grubonly rom

this complements the previous commit

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-27 14:42:16 +01:00
Leah Rowe ec761c88f2 coreboot: only run GRUB as a secondary payload
See:
https://codeberg.org/libreboot/lbmk/issues/216

Almost all users will be OK running GRUB, but a
minority of users have experienced a fatal error
pertaining to grub_free() or grub_realloc() (as
my investigation of GRUB sources reveal when grepping
the error reported in the link above).

We don't yet know what the bug is, only that the
error occurs, leading to an effective brick if the
user has GRUB as their primary payload.

So far, it has only been reported on some Intel
SandyBridge-based Dell Latitudes in Libreboot, but
we can't be too sure.

The user reported that memtest86+ passes just fine,
and SeaBIOS works; BIOS GRUB also works, which means
that the bug is likely only in an area of GRUB that
runs specifically on the coreboot payload, so it's
probably a driver in GRUB when running on the metal
rather than BIOS/UEFI.

The build system supports a configuration whereby
SeaBIOS is the primary payload, but GRUB is available
in the SeaBIOS boot select menu, and an additional
configuration is available where GRUB is what SeaBIOS
executes first (while still providing boot select);
both of these are now the *only* configurations
available, on all x86 targets except QEMU.

The QEMU target is fine because if the bug occurs there,
you can just close QEMU and try a different image.

Even after this bug is later identified and fixed,
the GRUB source code is vastly over-engineered and there
are likely many more such bugs. SeaBIOS is a reliable
payload; the code is small and robust. Remember always:

Code

equals

bugs

Therefore, this configuration change is likely going
to be permanent. This will apply in the next release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-27 14:24:26 +01:00
Leah Rowe 64c64bcf10 flashprog: bump to 5b4fdd1 from 2 May 2024
I've rebased the workaround-mx patch as follows. See:

commit 9a11cbf21a5078bcdb8db7584c44a9ee17020db4
Author: Nico Huber <nico.h@gmx.de>
Date:   Fri Jan 13 01:19:07 2023 +0100

    Let the flash context directly point to the used master

This change, now upstream in flashprog, made me have to do this in
the patch. I changed this:

flash->mst->spi.command(flash, sizeof(cmd), sizeof(buf), cmd, buf);

to this:

flash->mst.spi->command(flash, sizeof(cmd), sizeof(buf), cmd, buf);

It should work fine. This update imports the following upstream
patches from flashprog:

* 5b4fdd1 z60_flashprog.rules: Add udev rule for CH347
* 72c9e40 meson: Check for CPU families with known raw mem access
* 3458220 platform/meson: Port pciutils/pci.h workaround to Meson
* f279762 platform/meson: Check for libi386 on NetBSD
* 14da5f7 README: Convert to Markdown
* 8ddea57 README: Document branching and release policy
* 2522456 util/list_yet_unsupported_chips.sh: Fix path
* cbf9c11 spi: Don't cross 16MiB boundaries with long writes
* 823a704 dediprog: Skip warning on first attempt to read device string
* e8463c8 dediprog: Revise prefix check for given programmer id
* 38af1a1 dediprog: Revise id matching
* 4661e7c amd_spi100: Use flashprog_read_chunked() for progress reporting
* cdcfda2 read_memmapped: Use flashprog_read_chunked() for progress reporting
* 7679b5c spi25: Replace spi_read_chunked() with more abstract version
* ca1c7fd spi25: Normalize parameters of spi_nbyte_read()
* e36e3dc dediprog: Use default_spi_write_256
* 522a86d linux_spi: Use default_spi_read()/_write_256()
* 806509b cli_classic: Turn progress reporting into a progress bar
* 842d678 libflashrom: Return progress state to the library user
* aa714dd flashprog.c: Let select_erase_functions() return byte count
* 2eed4cf serprog: Add SPI Mode and CS Mode commands
* 821a085 dediprog: Implement id reading for SF600 and later
* 274e655 dediprog: Read device string early
* 0057822 dediprog: Add protocol detection for SF700 & SF600Plus-G2
* fb176d2 dediprog: Use more general 4BA write mode for newer protocols
* 0ab5c3d dediprog: Split device type and version parsing
* bdef5c2 dediprog: Use unsigned conversions to parse device string
* 5262e29 dediprog: Try to request 32B device string (instead of 16B)
* e76e21f dediprog: Get rid of some unnecessary hex constants
* 5a09d1e udelay: Lower the sleep vs delay threshold
* 03ad4a4 linux_mtd: Provide no-op delay implementation
* 211c6ec serprog: Refine flushing before synchronization
* 383b7fe serprog: Test synchronicity before trying to synchronize
* d7318ea serprog: Move synchronicity test into separate function
* 9a11cbf Let the flash context directly point to the used master
* aabb3e0 writeprotect: Hook wp functions into the chip driver
* 89569d6 memory_mapped: Reduce `decode_sizes` to a single `max_rom_decode`
* 929d2e1 internal: Pass programmer context down into chipset enables
* 7c717c3 internal: Pass programmer context down into board enables
* e3a2688 Pass programmer context to programmer->init()
* 2b66ad9 Start implementing struct flashprog_programmer
* 4517e92 memory_bus: Drop stale `size == 0` workaround and FIXME
* b197402 memory_bus: Split register mapping into own function
* 0e76d99 memory_bus: Move (un)map_flash_region into par master
* 9eec407 Perform default mapping only for respective chips
* 56b53dd wbsio_spi: Request memory mapping locally
* 5596190 it87spi: Request memory mapping locally
* 46449b4 spi25: Drop stale `bus == SPI` guards
* ab6b18f spi25: Move 4BA preparations into spi_prepare_4ba() hook
* 901fb95 Add prepare/finish_access() hooks for chip drivers
* a96aaa3 dediprog: Support long writes of 16MiB and more
* 1338936 Consider 4BA support when filtering erase functions
* 8d36db6 flashprog.8: Fix up serprog example
* d2ac303 flashprog.8: document new serprog cs parameter
* d1b9153 chipset_enable.c: Add Genoa to mendocino entry

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-26 20:30:45 +01:00
Leah Rowe 914852dd40 rename include/option.sh to include/lib.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-26 12:10:27 +01:00
Leah Rowe dc7b72f3f4 roms: rename bstr variable
i forgot to do this in the recent cleanup. it is now
initialised as a variable named "x"

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-26 09:22:39 +01:00
Leah Rowe 5c14e8e1bc general code cleanup in the build system
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-26 07:22:44 +01:00
Leah Rowe 48c2cef800 build: simplify git_init()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-25 16:56:44 +01:00
Leah Rowe db06bbdb6e build: do root check before git check
otherwise, git could be initialised as root.

running as root is not allowed.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-25 16:34:48 +01:00
Leah Rowe 8d199a31d1 build: simplify git checks
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-25 16:34:07 +01:00
Leah Rowe 8da2559b35 option.sh: fix bad check for version/versiondate
i was checking whether it's a directory, whereas i should
have been checking whether it's a file. this is a workaround
put in place in case someone downloaded a tarball from codeberg
which is pre-generated per commit. in this situation, the
version and versiondate files do not exist, but the design
of the build system requires that they do exist.

the existing check is correct except for this bug, so fix
the bug. check that they are files, not directories

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-25 14:37:40 +01:00
Leah Rowe d32968c731 trees: reset makeargs per target/project
it wasn't being reset before. when coreboot is being
built, i add to makeargs every time. if multiple targets
are being built, the make command would end up looking
something like:

make -C src/coreboot/default UPDATED_SUBMODULES=1 \
    UPDATED_SUBMODULES=1

(the parameter would be printed twice)

of course, this doesn't check whether that parameter is
added already in target.cfg for a given target, but that's
ok because i won't add that one in target.cfg

i baked it into the code, only when handling coreboot,
because that was easier than either putting it in makeargs
for every coreboot target.cfg, or again modifying the code to
handle that; the current solution is the cleanest.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-25 14:32:06 +01:00
Leah Rowe 7bab0cf9ed trees: also use UPDATED_SUBMODULES=1 on crossgcc
i overlooked this in the previous revision

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-25 00:37:26 +01:00
Leah Rowe 0a50eaf227 trees: add UPDATED_SUBMODULES to coreboot make
we do not want submodules to be downloaded after the fact.

we only handle this on ./update trees -f coreboot

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-25 00:22:34 +01:00
Leah Rowe ff0840bdf8 trees: write -C on the make command first not last
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-25 00:18:40 +01:00
Leah Rowe b91ee72762 config: add backup coreboot submodule repositories
this is using the same functionality that was added a few
commits ago, to override the use of "git submodule update"

each coreboot submodule has two repositories defined, with
the second one kicking in if the mail one fails upon cloning.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-24 23:42:05 +01:00
Leah Rowe 4a3ebe84a8 coreboot/default: remove chromeec from module.list
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-24 21:44:27 +01:00
Leah Rowe 9c5890e9f2 git.sh: break if a submodule clone succeeds
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-24 21:43:10 +01:00
Leah Rowe fdb08143e4 coreboot: only download the necessary submodules
whitelist what modules are downloaded, by adding
module.list files in the corresponding directories
under config/submodule/, per each coreboot tree.

this is making use of functionality added in the
previous commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-24 19:30:43 +01:00
Leah Rowe 1cb255e8be git.sh: allow finer control of git submodules
in each submodule configuration directory, a module.cfg
file can now be provided. in it, the user can specify
two repository links (main and backup) and a revision, like
so:

subrepo="repo link goes here"
subrepo_bkup="backup repo link goes here"
subrev="git revision id goes here"

additionally:

in the *main* project directory for the submodules,
a module.list file can be provided. example entries:

3rdparty/vboot
3rdparty/libgfxinit

if the module.list file is provided, only those submodules
will be downloaded. this can be combined with the module.cfg
files, if you wish, but it's optional. you can mix and match.

example locations:

multi-tree project:
config/submodule/coreboot/default/module.list
config/submodule/coreboot/default/vboot/module.cfg
single-tree project:
config/submodule/flashprog/module.list
config/submodule/flashprog/foo/module.cfg

*no* configuration files have been provided, in this commit,
which means that the current behaviour is maintained.

follow-up commits will absolutely configure the submodules.
this is being done to reduce the number of modules downloaded,
because we don't use most of the coreboot submodules that are
downloaded, thus wasting bandwidth and the releases are also
much bigger than necessary.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-24 18:58:48 +01:00
Leah Rowe 5d87eea77c build: hide git-init output
following on from the previous commit, if you run
something like "./build roms list" when running for
the first time from a codeberg tarball, the output
of the git commands will be included in the output

hide this output

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-24 15:00:46 +01:00
Leah Rowe b8ec7d5640 option.sh: generate version file if .git not found
a user was getting error "version unset" when using the
tarball generated from codeberg. it's recommended to use
the git repository properly, or a release archive.

mitigate this so that the build succeeds anyway.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-24 14:53:45 +01:00
Leah Rowe 87c361f3df update/trees: remove unused variable
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-23 00:01:20 +01:00
Leah Rowe da42727209 git.sh: move repo copying to a new function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 23:11:12 +01:00
Leah Rowe 093c4a367d git.sh: move link_crossgcc to end of file
link_crossgcc is called after git_am_patches, so
put it after ward

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 23:08:13 +01:00
Leah Rowe 73a2d99102 git.sh: move xgcc linking to a new function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 18:50:42 +01:00
Leah Rowe d774987697 git.sh: skip submodules if .gitmodules missing
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 18:03:48 +01:00
Leah Rowe c3e1aa343a git.sh: merge patch_submodules in prep_submodules
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 18:01:39 +01:00
Leah Rowe a41633306a git.sh: split submodule handling to new function
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 17:59:42 +01:00
Leah Rowe aa4faf0815 git.sh: remove errant line break
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 16:03:28 +01:00
Leah Rowe 0014269604 git.sh: remove another meaningless check
again, the directory in question is simply used
in a for loop using asterisk (git_am_patches) and
the for loop simply won't iterate if either the
directory doesn't exist or it contains no items.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 15:57:47 +01:00
Leah Rowe fc3b0ba8bf git.sh: shorter variable names
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 15:56:35 +01:00
Leah Rowe dae10dd482 git.sh: remove meaningless check
in the function that immediately follows, it
starts two for loops that check every item in
that directory, using the asterisk wildcard.

if the directory does not exist, then the for
loop will simply break on first pass.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 15:53:37 +01:00
Leah Rowe c148fa53df git.sh: remove variable not meaningfully used
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 15:53:15 +01:00
Leah Rowe 079afb5bd3 add CHANGELOG to .gitignore
we want ./update release to work in release archives.

under the current logic, CHANGELOG would be cloned into
release/, thus breaking ./update trees -f

fix it by adding the file to .gitignore

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-22 02:15:39 +01:00
Leah Rowe 0d8781ef4e Merge pull request 'Fix E6400 display reference clock patches' (#214) from nic3-14159/lbmk:fix-e6400-igpu-ref-clock into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/214
2024-05-22 01:06:59 +00:00
Nicholas Chin 9f50e36228 Fix E6400 display reference clock patches
The ones I submitted before seem to have been outdated ones
that don't actually build properly.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-21 18:58:28 -06:00
Leah Rowe e5a5935d8d fix building coreboot images on i686 hosts
firstly, memtest86+ is currently not cross compiled and
relies on 64-bit headers (x86_64 only). a 32-bit distro
is unlikely to be able to build 64-bit binaries.

secondly: vboot throws a build error due to -Werror when
building on 32-bit hosts. we rely on vboot code to build
cbfstool, so turn off -Werror on vboot

that's all. 32-bit hosts are not recommended; it is assumed
that you are building on an x86_64 host. work will go into
the build system at a later date to make it more portable,
by cross compiling everything, but this should fix 32-bit
for now.

there are some x60/t60 users who still want to build roms,
so let's allow them that possibility.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-21 23:40:25 +01:00
Leah Rowe a2ac4d1398 Merge pull request 'Also try unlocking encrypted volume on NVMe' (#213) from mkukri/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/213
2024-05-21 19:09:37 +00:00
Mate Kukri 77ebd05010 Also try unlocking encrypted volume on NVMe 2024-05-21 19:47:14 +01:00
Leah Rowe 287d05555f Merge pull request 'Add NVMe support to GRUB2 payload' (#212) from mkukri/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/212
2024-05-21 17:13:28 +00:00
Leah Rowe 47d77c9429 Merge pull request 'Fix E6400 display issue with 1440 x 900 panel' (#211) from nic3-14159/lbmk:fix-e6400-igpu-ref-clock into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/211
2024-05-21 17:13:17 +00:00
Leah Rowe 0beecd1b03 Merge pull request 'Add pt qwerty keymap to lbmk' (#210) from samuraikid/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/210
2024-05-21 17:13:07 +00:00
Leah Rowe 835e5ad0e8 git.sh: fix invalid command in git_prep()
"./update project trees" is a leftover from the
old build system design, prior to audits.

this particular call is for when xtree is defined,
which means that a given tree must rely on the given
coreboot tree defined by xtree. the "xtree" tree is
downloaded, so that its crossgcc builds can be re-used
to save time when building targets across many trees.

this is because trees often use identical crossgcc builds.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-21 18:09:41 +01:00
Mate Kukri abe6717c33 Add NVMe support to GRUB2 payload
Tested on OptiPlex 3050 (via injecting grub2.elf into WIP coreboot
port).
2024-05-20 20:48:44 +01:00
Nicholas Chin 8629873a60 Fix E6400 display issue with 1440 x 900 panel
The E6400 uses a 100 MHz reference clock on DPLL_REF_SSCLK, whereas
libgfxinit assumed that the reference was always 96 MHz. The frequency
difference caused by a 100 MHz reference with PLL config values
calculated assuming a 96 MHz reference were not significant enough to
cause noticable issues with the more common 1280 x 800 panels, but are
enough to matter for the 1440 x 900 panels which use a higher pixel
clock. This only affected the pre-OS graphics environment provided by
libgfxinit, as Linux drivers would determine the reference clock
frequency based on data in the VBT.

Fix this by making the reference clock frequency in libgfxinit
configurable for GM45 based on a new coreboot Kconfig, which is set to
100 MHz for the E6400.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-20 10:46:25 -06:00
Leah Rowe 1e54db2989 git.sh: allow patching submodules
for single-tree project (e.g. flashprog):
config/submodule/PROJECT/MODNAME/patches

for multi-tree project (e.g. coreboot):
config/submodule/PROJECT/TREE/MODNAME/patches

MODNAME is e.g.:
3rdparty/vboot directory in coreboot: would become vboot
(the submodule codepath is filtered to up to the final slash)

another example:
submodire src dir 3rdparty/foo/bar
MODNAME would be "bar"

Add whatever patches you like to a given submodule.

An example patch is included in this commit.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-20 00:10:27 +01:00
Leah Rowe 00e00a18d0 git.sh: don't delete .git if src/project/project
otherwise, "./update release" will epicly fail

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-19 23:04:37 +01:00
Leah Rowe 245b4eb21d build/roms: skip target if config/ dir missing
fixes a regression when running ./build roms all

now it should work again

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-19 22:43:52 +01:00
Leah Rowe aadccc591b more minor cleanup in the build system
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-19 08:14:57 +01:00
Leah Rowe 5b8928c7c9 git.sh: remove fetch_from_upstream()
the function is very small and only called once,
from fetch_project_trees()

merge it into fetch_project_trees()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-19 07:50:24 +01:00
Leah Rowe 71baf65351 option.sh: don't return 1 in mkrom_tarball
one of the calling functions relies on the return value
to be always 0, so these error conditions in mkrom_tarball
have been altered to cause an *exit* (non-zero) instead.

in practise, the commands in question were printf commands
run after tho directory they output to had been created,
so write access would probably not be an issue.

nonetheless, technically correct is the best kind of correct.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-19 06:51:20 +01:00
Leah Rowe 1fe9c4b899 option.sh: mktar_release to mkrom_tarball
that's all it's used for, to compress the rom images

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-19 06:45:38 +01:00
Leah Rowe cc7ed6926b build/roms: rename moverom to copyrom
it copies, it doesn't move, so name it right

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-19 06:43:37 +01:00
Leah Rowe b40118ae59 minor code cleanup in the build system
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-19 06:30:32 +01:00
samuraikid 8d723d1498 Add pt qwerty keymap to lbmk
Signed-off-by: samuraikid <samuraikid@noreply.codeberg.org>
2024-05-18 22:05:27 +00:00
Leah Rowe 998f30ad4d build/roms: simplify serprog list command
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-18 22:17:12 +01:00
Leah Rowe 21a7efaa95 build/roms: simplified config payload checks
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-18 22:13:20 +01:00
Leah Rowe 5b5dccd630 vendor.sh: further simplify config handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-18 19:51:40 +01:00
Leah Rowe 8418ea9ab2 vendor.sh: greatly simplified config handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-18 19:45:52 +01:00
Leah Rowe 53b394f583 vendor.sh: move config checks to detect_firmware
they will later be removed, as part of unification against
other files that perform the same tasks

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-18 19:28:15 +01:00
Leah Rowe bb7255c34b vendor.sh: print an error upon ill-defined target
previously, it was attempting to load the configs and silently
failing. we must provide feedback to the user.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-18 11:25:28 +01:00
Leah Rowe 3f73f3d0b4 vendor.sh: remove redundant check
we literally do this check twice, in immediate succession.

avoid wasted i/o

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-18 11:20:56 +01:00
Leah Rowe 32923f5608 vendor.sh: simplify defconfig check
re-use check_defconfig from option.sh

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-18 11:14:39 +01:00
Leah Rowe f8e3ca3b22 git.sh: Remove .git if XBMK_RELEASE=y
The build system already deletes .git in all source
directories for each given release, but does so at
the very end; it still does, but now it is deleted
one by one per project, to save space during very
large builds (release sizes vary wildly, depending
on how many trees exist for coreboot basically).

If you're building entirely in tmpfs (as I do), this
could be a problem if you have lots of .git/ directories.

This change reduces disk usage, or in the above example,
memory usage when running the build system from tmpfs.

This complements another recent change, where ROM images
are compressed per target during release builds, rather
than all at the very end of the process. It is part of a
series of optimisations, to reduce the memory and disk
usage of the build system, and to reduce I/O wastage
in general.

This change will not be the last of such changes!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-18 04:53:31 +01:00
Leah Rowe dd851caac9 build: remove initcmd() and simplify main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-16 11:34:53 +01:00
Leah Rowe 4ea843a490 build: initialise git first (before commands)
when running the inject logic, we should still initialise
the git repository because these commands make use of the
coreboot build system which requires git.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-16 11:29:57 +01:00
Leah Rowe 5702f5a4dc build: remove excmd() and simplify main()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-16 11:23:22 +01:00
Leah Rowe b76a70c3f9 build: don't make script_path a global variable
this allows a mild cleanup of the code (reduction by 1 line)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-16 11:11:59 +01:00
Leah Rowe 839ef680cd lbmk: allow easier sync with cbmk
an equivalent change has been made in cbmk.

certain lbmk-specific variable names have been made
generic, with certain functions and other variables
moved around.

i maintain sync between libreboot and canoeboot, where
both projects can have the same behaviours, and most of
the merge conflicts have to do with variable names
containing "LBMK", "lbmk", "cbmk" or "CBMK", or
indeed "canoeboot" and "libreboot"

LBMK/lbmk/CBMK/cbmk variables between canoeboot and
libreboot now contain the string XBMK/xbmk

it should now be *much* easier to merge build system
changes between lbmk and cbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-16 03:56:52 +01:00
Leah Rowe 885fcebd81 remove help commands (user should read docs)
i always say, code should never document itself.

that's what documentation is for. the releases
contain documentation under docs/ but the git
repository does not; for that, use the website.

(in practise, lbmk usually needs internet anyway)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 04:30:42 +01:00
Leah Rowe c6ba0a0e9b option.sh: delete check_git()
it's only used from main() in the main build script,
and it's very small, as is main()

therefore, move the logic into main()

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 04:03:16 +01:00
Leah Rowe 313c4c01e0 build: define "xp" in the global variables
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 03:55:44 +01:00
Leah Rowe 350857fff3 build: simplify for loop in fetch_trees()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 03:53:26 +01:00
Leah Rowe 8e05399d91 build: simplified downloads in fetch_trees()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 03:39:28 +01:00
Leah Rowe 914ff1ad12 ./build release: don't do u-boot-only archives
it's a pointless feature, initially added just to one-up
gnuboot and only intended for canoeboot, to provide u-boot
tarballs with deblobbing. this was done, because the parabola
build system has certain limitations so the idea is to provide
them with tarballs. but why? they can just fix their build system...

delete this bloat from lbmk. we only need to provide full sources,
and rom images.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 03:19:32 +01:00
Leah Rowe 5c3fb9a4f8 build: use utc+0 when initialising git repo dates
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 03:10:43 +01:00
Leah Rowe e281966f22 remove check_project() (always set variables)
in lbmk, we call check_project() to set variables
such as projectname, version, version date

this is unnecessary, because all main scripts use
this functionality anyway

do it by default

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 03:04:41 +01:00
Leah Rowe ee2bf0d25a build: simplify deletions in fetch_trees()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 02:56:58 +01:00
Leah Rowe 39df62301d build: delete mkversion() (just print relname)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 02:49:30 +01:00
Leah Rowe a40a61292d build/roms: clean up tarball handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 02:36:24 +01:00
Leah Rowe e5ffb2afe6 rm src/u-boot/*/test/lib/strlcat.c in u-boot
i accidentally removed this in a previous commit

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 02:33:35 +01:00
Leah Rowe c149cbb884 build: remove mkrom_images
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 01:41:19 +01:00
Leah Rowe 4135ce5e27 build: use same tarball name on uboot-only release
it's a rarely used feature, not currently used by the
libreboot project itself

remove unnecessary bloat

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 01:32:15 +01:00
Leah Rowe 189b70ddcb build/roms: create full release tarball name
set relname from option.sh under check_project()

now the release logic simply has to move a directory

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 01:27:45 +01:00
Leah Rowe 36d45474c0 option.sh: don't bother checking for GNU tar
releases aren't reproducible anyway. we were
using options available in gnu tar for this.

it will be revisited at a later date. however, the next
time this is done, we will use another method because
there are in fact portable ways to create tarballs
reproducibly, documented on reproducible-builds.org

to be revisited, at a later date. for now, remove bloat.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 00:48:08 +01:00
Leah Rowe f0b604fc95 option.sh: remove insert_version_files()
it's only called once, from this file, within a small
function, and the function itself is very small.

remove, and put the contents of the function in the
calling function.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 00:45:01 +01:00
Leah Rowe 267c13cca7 cleanup: remove mkvdir
this function is not needed, because it's only called
once and it's very small.

furthermore: insert_version_files does ntot need to be called here,
because they same files are generated immediately afterward when
running that version of lbmk.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 00:42:44 +01:00
Leah Rowe 08c9f94a1a unified sha512sum creation for tarballs
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-15 00:37:12 +01:00
Leah Rowe 1ce7e33976 move rom tarball creation to script/roms
export LBMK_RELEASE="y"

if this is done, the tarball is created instead
of a directory, and the rom images are nuked using
./vendor inject with the nuke option, inserting the
correct version files; the rom directory is deleted

now the release script logic simple renames existing
tarballs. the benefit of this change is fewer lines of
code, and now lbmk doesn't use an insane amount of disk
space when building a *lot* of release images (the
uncompressed directories are deleted after each build)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-14 23:44:28 +01:00
Leah Rowe 190495d2e5 disable x301 for next release (for now)
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-12 04:15:01 +01:00
Leah Rowe 03fae0cf88 mrc.sh: remove redundant function extract_ref()
extract_ref() is no longer used

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-11 22:48:51 +01:00
Leah Rowe f66ceef6f2 print two line breaks before confirming release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-11 22:14:04 +01:00
Leah Rowe cc33974150 remove haswell mrc blob (libre raminit stable now)
broadwell mrc is retained, because it's needed on 820 g2

it's no longer needed on haswell, because nri is stable. nri
is short for "native ram initialisation", and libreboot provides
this for: thinkpad t440p, thinkpad w541, dell optiplex 9020 mt,
and dell optiplex 9020 sff

remove, in line with libreboot's binary blob reduction policy

previous revisions, prior to the recent release, stated that
it would be retained for compatibility, but it's really not
right to retain it, because doing so violates libreboot's policy

the recent release excluded mrc-based rom images for haswell
machines, providing only those rom images that use the libre
raminit, while retaining support for mrc in the build system, so
that users could still run the lbmk inject script on older release
roms that use mrc

again: libreboot's binary blob reduction policy is very clear:

https://libreboot.org/news/policy.html

it is a policy that can be summarised, thus:

if a blob can be avoided, it must be avoided.

therefore, we will avoid the Haswell MRC raminit blob

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-11 19:12:11 +01:00
Leah Rowe 05fbd39298 remove all status checks. only handle release.
the release variable is all we need, turning a target on
or off for a given release.

the status checks were prone to bugs, and unnecessary; it
also broke certain benchmark scripts.

it's better to keep the lbmk logic simpler. board status
will be moved to the documentation instead.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-11 18:53:12 +01:00
Leah Rowe 8ba0fd834d git.sh: remove errant comment
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-11 07:01:39 +01:00
Leah Rowe d7ce26dc23 move script/*/* to script/
there are only two scripts under script/ now, and there
probably won't be many more. lbmk's design has simplified
to such a degree that the two-level directory structure is
no longer necessary.

the existing command structure has not changed. for example:

./build roms list
./update trees -f coreboot default

these will still work, but the symlinks to "build" are now
strictly for backwards compatibility; they may be removed
at a later date, but i'll keep the current design for now.

this also leads to a quirk, for example:

./build roms all
./update roms all

these now do the exact same thing, whereas "./update roms all"
would have previously been an invalid command.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-11 06:26:52 +01:00
Leah Rowe 029291e549 merge script/vendor/* into include/vendor.sh
stub it from the main build script

the commands remain identical:
./vendor download arguments_here
./vendor inject arguments_here

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-11 05:57:49 +01:00
Leah Rowe c8fb24bb7b build: print usage for special commands
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-11 05:19:48 +01:00
Leah Rowe 5f63b594fa merge script/update/release into build
the main script isn't that big, and since the main
purpose of lbmk is geared toward the releases, it
makes sense to reduce the number of scripts by
merging into the main one

the way this works, "./update release" still works
afterward

so, the way lbmk is used shall remain unchanged

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-11 04:15:30 +01:00
Leah Rowe e1ea5dd0fd bump seabios to e5f2e4c69643bc3cd385306a9e5d29e11578148c
changes upstream, relative to the previous revision:

* e5f2e4c6 pciinit: don't misalign large BARs
* 731c88d5 stdvgaio: Only read/write one color palette entry at a time
* c5a361c0 stdvga: Add stdvga_set_vertical_size() helper function
* 22c91412 stdvga: Rename stdvga_get_vde() to stdvga_get_vertical_size()
* 549463db stdvga: Rename stdvga_set_scan_lines() to stdvga_set_character_height()
* c67914ac stdvga: Rename stdvga_set_text_block_specifier() to stdvga_set_font_location()
* aa94925d stdvga: Rework stdvga palette index paging interface functions
* 8de51a5a stdvga: Rename stdvga_toggle_intensity() to stdvga_set_palette_blinking()
* 96c7781f stdvga: Add comments to interface functions in stdvga.c
* 2996819f stdvga: Rename CGA palette functions
* 91368088 stdvgamodes: Improve naming of dac palette tables
* 70f43981 stdvgamodes: No need to store pelmask in vga_modes[]
* 1588fd14 vgasrc: Rename vgahw_get_linesize() to vgahw_minimum_linelength()
* d73e18bb vgasrc: Use curmode_g instead of vmode_g when mode is the current video mode
* 192e23b7 vbe: implement function 09h (get/set palette data)
* 3722c21d vgasrc: round up save/restore size
* 5d87ff25 vbe: Add VBE 2.0+ OemData field to struct vbe_info
* 163fd9f0 fix smbios blob length overflow
* 82faf1d5 Add LBA 64bit support for reads beyond 2TB.
* 3f082f38 Add AHCI Power ON + ICC_ACTIVE into port setup code
* 3ae88886 esp-scsi: terminate DMA transfer when ESP data transfer completes
* a6ed6b70 limit address space used for pci devices.

Signed-off-by: Leah Rowe <info@minifree.org>
2024-05-10 05:52:12 +01:00
Leah Rowe 052414c0ca build: further prevent non-lbmk-work-directory
this is a follow-up to the previous commit

again, there's no posix way to check the path to the
file at argument 0, because readlink (utility) isn't
defined in posix (the C function is defined, but not
the utility included on many unices)

check whether "build" (file) exists, and whether it
is a symlink; if the latter, then we are definitely
not in the lbmk work directory!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-09 14:48:14 +01:00
Leah Rowe fb8d0c86c4 build: exit if not running from lbmk directory
there's no portable(posix) way to check when running
from a symlink to lbmk in the current work directory

for example:

ln -s lbmk/build lbmktest
./lbmktest roms list

this would pass the new test, and first try to
include option.sh. in practise, the user probably  doesn't
happen to have include/option.sh in their current path

i can use readlink here, but again not portable

the current check will suffice. it also works when
the symlink is called from $PATH

e.g. /usr/bin/lbmktest exists and you do:
lbmktest roms list

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-09 14:31:43 +01:00
Leah Rowe 38aaaecf6b build/roms: print serprog help
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-09 13:56:35 +01:00
Leah Rowe e3cb3a4072 merge script/build/serprog with script/build/roms
previous command:

./build serprog

now it is:

./build roms serprog

after that, it's the same arguments e.g.

./build roms serprog stm32
./build roms serprog rp2040

further cleanup to commence

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-09 13:52:49 +01:00
Leah Rowe 297af7e6d3 build/roms: remove unnecessary command
there is no need to return 0 at the end of a function.

sh does that anyway

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-09 13:03:35 +01:00
Leah Rowe 5e4009b539 merge include/err.sh with include/option.sh
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-06 22:54:55 +01:00
Leah Rowe 58400fc4a5 err.sh: correct copyright info
i replaced 2022, 2023 with 2022, 2024 when updating
the years, as per modifications, but the 2023 copyright
doesn't become invalidated

change it to 2022-2024 instead, which is correct

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-06 16:13:13 +01:00
Leah Rowe aa5937edd5 build/roms: don't rely on x in handle_target
x is part of the for loop in main() and may or not
still be available from handle_target, depending on
your implementation of sh, but this should not be assumed

do it properly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-05 05:28:06 +01:00
Leah Rowe 580a555948 build/roms: don't use exit status from skip_board
the printf could potentially return non-zero, which might
make the script not skip a given target

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-05 05:18:12 +01:00
Leah Rowe 2fcbff68fc build/roms: split up main()
it's starting to get a big big, so break it up

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-05 05:16:51 +01:00
Leah Rowe d13d930804 build/roms: allow searching status by mismatch
for example:

./build roms list stable

this lists all images that are marked "stable"

now:

./build roms list _stable

this lists all images that are *not* marked stable

this will help me keep track during development

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-05 04:41:51 +01:00
Leah Rowe ae9e73890f Libreboot 20240504 release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-04 06:25:42 +01:00
Leah Rowe d3aeb2c79f config/git: importer newer documentation
I'm on a schedule here and don't have time to do the
release changelog before actually compiling the release.
I'm pushing the release changelog / news announcement
*while the release is building*. Therefore, the actual
release archive will contain Libreboot documentation, but
from the lbwww revision just before the release announcement.

(a changelog file is still generated from Git, and included
in releases)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-04 06:22:56 +01:00
Leah Rowe 5bf25eac05 coreboot: update latitude release status
working s3 means i'm happy to mark it as being stable.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-04 04:58:40 +01:00
Leah Rowe 7a955a4c72 d510mo and d945gclf: disable for release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-04 04:54:09 +01:00
Leah Rowe 7e799e1f16 nb/haswell: lock policy regs when disabling IOMMU
Angel Pons told me I should do it. See comments here:
https://review.coreboot.org/c/coreboot/+/81016

I see no harm in complying with the request. I'll merge
this into the main patch at a later date and try to
get this upstreamed.

Just a reminder: on Optiplex 9020 variants, Xorg locks up
under Linux when tested with a graphics card; disabling
IOMMU works around the issue. Intel graphics work just fine
with IOMMU turned on. Libreboot disables IOMMU by default,
on the 9020, so that users can install graphics cards easily.

I'm pretty sure this is the correct way to do it. The machine
still seems to boot, in this configuration.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-04 04:32:35 +01:00
Leah Rowe d9c0346a00 build/roms: more useful status warnings
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-04 01:15:33 +01:00
Leah Rowe 985870297d deprecate MRC 9020MT/SFF (NRI 9020 is default now)
NRI is libre raminit

MRC is binary blob raminit

the libre raminit is stable enough now that it's default

the MRC-based targets will be removed in a future release

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-04 01:15:26 +01:00
Leah Rowe d839bfa1ed mark 9020 sff/mt stable for release
i initially decided to say unstable, but the default
configuration is reliable; the only caveat is that if
you enable IOMMU, you must only be using intel graphics.

this is already documented in warn.txt files, and on
the website, so it's more than ok to call this stable.

i use one of these myself as my daily driver and it's
rock solid. i haven't had any problems with it. i also
sell these to people with libreboot. no problems.

mark it as stable, ready for a full release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-04 01:15:17 +01:00
Leah Rowe a9bc6b254b mark lenovo x301 as stable for release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-04 01:15:08 +01:00
Leah Rowe 6e61052a55 Merge pull request 'coreboot/default: Add patches to fix S3 on SNB/IVB Latitudes' (#208) from nic3-14159/lbmk:latitude-fix-s3 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/208
2024-05-04 00:13:23 +00:00
Nicholas Chin 67ddd3f2f6 coreboot/default: Add patches to fix S3 on SNB/IVB Latitudes
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-03 18:02:44 -06:00
Leah Rowe 780e03fe1e remove x220edp/x230edp (keep regular x220/x230)
nitrocaster boards are hard to find nowadays and i'm not
comfortable supporting the knockoff chinese gear; quality
varies greatly, and i can't know how reliable they are.

nitrocaster has been out of business so it's just not
viable to support this mod anymore. in fact, keeping the
eDP-based targets is a liability to libreboot.

regular x220/x230 (non-eDP-modded) are retained. the eDP
modkit from nitrocaster let you use eDP screens instead
of lvds, on thinkpad x220 and x230, letting you use
higher resolution screens.

older lbmk revs can still be used, if you happen to come
across one of these boards. i only recommend using the
official nitrocaster board, if youcan find one unused.

ymmv with the chinese gear. better just use an unmodded
x230 or get a different machine.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-03 23:46:27 +01:00
Leah Rowe b379186a5c update hp machines to status=stable for release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-03 23:46:25 +01:00
Leah Rowe 6e7b5c0b24 Enable WiFi on HP EliteBook 8560w (GPIO config)
angel pons said how to fix it. more info in the patch.

works perfectly. i still see that scancode in dmesg and i guess
i have to assign it to some function that sets software rfkill

hw rfkill is no longer set. it's unblocked, and i can use wifi.

just in time for the libreboot release.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-03 23:45:59 +01:00
Leah Rowe 9961779643 Merge pull request 'Implemented failsafe options at boot and inside menus for enabling/disabling serial, spkmodem and gfxterm' (#203) from livio/lbmk:failsafe into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/203
2024-05-03 13:59:20 +00:00
Leah Rowe 2d207c547c coreboot/x301: set release=n (will re-test)
was reported broken on canoeboot 0.1, which uses 2021
coreboot. we use much newer coreboot now in libreboot, but
still, better be cautious. set to release=n.

i'll set status and remove release=n if it works on testing

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-03 14:27:50 +01:00
Leah Rowe 64ae2ddd33 update/release: purge test/lib/strlcat.c in u-boot
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-03 14:02:02 +01:00
Leah Rowe 748b207215 mark x4x boards ready for release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-03 13:57:35 +01:00
Leah Rowe 9caff26332 err.sh: update copyright info
i added a few changes during this year so far, 2024

update the copyright years

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-03 07:14:15 +01:00
Leah Rowe 7db2ae0bd2 update/release: say when an archive is being made
without this change, the user might think lbmk crashed

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-03 07:11:43 +01:00
Leah Rowe cd9685d12d Merge pull request 'dell-flash-unlock: Remove dependency on GNU Make' (#207) from nic3-14159/lbmk:dell-flash-unlock-updates into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/207
2024-05-02 04:04:04 +00:00
Nicholas Chin a5cb63764b dell-flash-unlock: Remove dependency on GNU Make
Use shell scripting in the recipe instead of GNU make's
conditional syntax. This allows the Makefile to work with
the default implementations of make on the BSDs.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-01 21:51:59 -06:00
Leah Rowe 4bf3da31c9 Merge pull request 'Fixed QEMU x86 target's SMBIOS informations' (#205) from livio/lbmk:qemux86_fix into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/205
2024-05-02 02:35:24 +00:00
Leah Rowe a18cd7f11b Merge pull request 'Fixed boot selection menu' (#204) from livio/lbmk:livio_290424 into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/204
2024-05-02 02:34:55 +00:00
Leah Rowe 05c3f4938a Merge pull request 'dell-flash-unlock-updates' (#206) from nic3-14159/lbmk:dell-flash-unlock-updates into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/206
2024-05-02 02:33:52 +00:00
Nicholas Chin 61f66a46ea dell-flash-unlock: Update README for BSD
Add FreeBSD to the README as it is now supported. Make a note about
using gmake instead of make as the makefile currently uses GNU
extensions to determine build flags based on the OS.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-01 20:20:24 -06:00
Nicholas Chin 5e2e761142 dell_flash_unlock: Add support for FreeBSD
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-01 20:11:14 -06:00
Nicholas Chin 61dbaf9463 dell_flash_unlock: Set iopl level back to 0 when done
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-01 20:10:43 -06:00
Nicholas Chin 355dffb708 dell_flash_unlock: Fix ec_set_fdo() signature
Set argument list as void.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-05-01 20:09:50 -06:00
livio 707d7ce7d0 Fixed QEMU x86 target's SMBIOS informations 2024-05-01 11:20:46 +02:00
livio d654a3e5ed Fixed QEMU x86 target's SMBIOS informations 2024-05-01 11:17:59 +02:00
livio b4d27d0cc6 Fixed boot selection menu 2024-05-01 11:06:27 +02:00
Leah Rowe 5c3d81fff9 correct dell latitude status for release
it should be marked unstable, though these machines
are basically reliable; they have certain missing features
and quirky behaviour so it's important not to over-sell it

mark it as unstable, on all of the dell latitudes

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-01 06:29:09 +01:00
Leah Rowe 6dfd8c7070 update release status for HP machines
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-01 06:12:50 +01:00
Leah Rowe 50f6943ccd set gru bob/kevin stable for release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-01 05:59:31 +01:00
Leah Rowe df5e321648 set dell latitudes stable for release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-01 05:56:42 +01:00
Leah Rowe 7e7c3c235d mark i945 machines as stable for release
the previous issue was tested, and can no longer be reproduced

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-05-01 00:37:03 +01:00
livio 3e86b3ab73 Implemented failsafe options at boot and inside menus for enabling/disabling serial, spkmodem and gfxterm 2024-04-29 14:39:47 +02:00
Leah Rowe 310378c9e5 build/roms: simplified list handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-29 00:28:14 +01:00
Nicholas Chin 6fe2482fdf dell-flash-unlock: Remove unnecessary includes for NetBSD
The pio.h header, although present on NetBSD, is not necessary, as it
only declares x86 port IO inx()/outx() functions which are not actually
implemented.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-04-28 15:16:19 -06:00
Nicholas Chin b737a24c90 dell-flash-unlock: Remove memory clobber from inline assembly
The x86 port IO instructions do not access memory so it is not
needed in the clobber list.

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-04-28 14:55:47 -06:00
Leah Rowe 5003e02bb2 build/roms: if release, allow all non-broken roms
this includes untested roms

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 20:47:59 +01:00
Leah Rowe dbe259ef65 build/roms: always display warnings
(even if status=stable)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 20:42:37 +01:00
Leah Rowe 0e2c56be41 build/roms: reduce indentation in skip_board()
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 20:40:41 +01:00
Leah Rowe 91927760db build/roms: simplified status handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 20:33:38 +01:00
Leah Rowe 230f68fd8f build/roms: simplified seagrub handling
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 20:21:35 +01:00
Leah Rowe 515185a7f5 build/roms: support SeaGRUB *with menu enabled*
This is useful on desktops, where you want GRUB to
automatically start, but you still want access to the
GRUB menu, in the case where you rely on SeaBIOS to
execute the VGA ROM inside your graphics card.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 19:56:25 +01:00
Leah Rowe a88a8281df update/trees: simplified defconfig copying
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 19:28:02 +01:00
Leah Rowe 55204dc444 option.sh: don't use nproc (not portable)
export LBMK_THREADS=x

where x is an integer. this is already supported for
setting the number of build threads, but if not set
it uses nproc.

openbsd doesn't have nproc. default to 1 thread.

now you MUST set threads. e.g. in linux do:

export LBMK_THREADS=$(nproc)

preliminary work is being done to make lbmk run
on openbsd!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 17:31:16 +01:00
Leah Rowe 71f8e6530a eDP configs (x230/x220): don't release
set to release="n" for now until the eDP targets
are fixed.

the regular non-eDP targets are stable, and will be
released.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 17:24:41 +01:00
Leah Rowe a5c7cc1a0b fix target.cfg files on dell latitudes
some latitudes still used the old style for variables
in target.cfg, specifically arch="x86_64" - lbmk used to
then check that on a big if/else and translate it to the
correct target name for crossgcc, e.g. i386-elf, arm-eabi

now it just puts the arch directly, in a new variable:
xarch

change arch="x86_64" to xarch="i386-elf" in these files.
also remove a few obsolete variables. should build now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 03:27:54 +01:00
Leah Rowe d923d31451 use mirrorservice.org for iasl downloads
github is unreliable. i host these files myself.

coreboot uses intel.com again now in the latest revisions, and
intel broke it before. i'm going to start backing up the acpica
releases onto my rsync server from now on, and keep patching
coreboot to use my files.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-28 02:02:15 +01:00
Leah Rowe 714d4b3ed3 update/release: disable status checking
just to ensure that nothing goes wrong. we don't rely on
the status variable for releases, because there is another
variable, release, that target.cfg files declare, e.g.

release="n"
release="y"

you can just omit the variable, because it defaults to y, so
you only need declare it when it needs to be "n"

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-27 22:42:12 +01:00
Leah Rowe e614f90638 build/roms: tell the user how to ignore status
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-27 18:50:49 +01:00
Leah Rowe f22305fbf5 update macbook21/x60/t60 status
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-27 17:01:38 +01:00
Leah Rowe 6c4f07b350 allow disabling status checks during builds
export LBMK_STATUS=n

if not set, the status checks and confirmation dialogs
persist. if set to y they persist.

if you set it to n, all checks are disabled, so e.g.:

./build roms all

this would once again build all targets, regardless
of status. this is if you want the old behaviour.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-27 16:46:31 +01:00
Leah Rowe ad7e3966b9 update 9020 sff/mt release status
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-27 15:45:49 +01:00
Leah Rowe 3ace925e91 update more board statuses before release
what's left to properly test are pineview/x4x/i945 and
some of the ivy/sandy elitebooks/hp workstations

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-27 15:26:18 +01:00
Leah Rowe e761922542 Set status=unstable on dell latitudes
also warn about issues, in a warn.txt file for each.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-27 15:08:16 +01:00
Leah Rowe 1fd9ba9ae0 declare ivy/sandy thinkpads stable for release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-27 14:51:59 +01:00
Leah Rowe 5218bfb0c8 declare gm45 thinkpads stable for release
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-27 14:49:14 +01:00
Leah Rowe b99ebe0551 kcma-d8/kgpe-d16: mark as tested(unstable)
raminit has never been fully reliable on this board, and so
this board has never been stable. so, now that lbmk specifies
such status per board, mark these boards as such.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-27 06:08:07 +01:00
Leah Rowe e5cc3e557a Merge pull request 'dell-flash-unlock: add NetBSD support' (#194) from linear/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/194
2024-04-26 22:57:47 +00:00
Leah Rowe c0b4ba2eea build/roms: update help, pertaining to status
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-26 23:32:10 +01:00
Leah Rowe d88783b734 build/roms: let "list" specify status types
for example:

./build roms list

this will list every now, still. same behaviour. now see:

./build roms list stable

this will list all stable roms

./build roms list untested

this lists untested roms. but wait!

./build roms list untested broken unstable

./build roms list broken unstable

yes. it works this way. now you can use lbmk to easily
see what rom status are, during maintenance.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-26 21:49:27 +01:00
Leah Rowe b6014a65ac erroneous return
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-26 21:10:06 +01:00
Leah Rowe ce7fd754a3 build/roms: report status when building images
export LBMK_VERSION_TYPE=x
x can be: stable, unstable

in target.cfg files, specify:
status=x
x can be: stable, unstable, broken, untested
if unset, lbmk defaults to "unknown"

if LBMK_VERSION_TYPE is set, no confirmation is asked
if the given target matches what's set (but what's set
in that environmental variable can only be stable or
unstable)

if LBMK_RELEASE="y", no confirmation is asked, unless
the target is something other than stable/unstable

"unstable" means it works, but has a few non-breaking
bugs, e.g. broken s3 on dell e6400

whereas, if raminit regularly fails or it is so absolutely
unreliable as to be unusable, then the board should be
declared "broken"

untested means: it has not been tested

With this change, it should now be easier to track whether
a given board is tested, in preparation for releases. When
working on trees/boards, status can be set for targets.

Also: in the board directory, you can add a "warn.txt" file
which will display a message. For example, if a board has a
particular quirk to watch out for, write that there. The message
will be printed during the build process, to stdout.

If status is anything *other* than stable, or it is unstable
but LBMK_VERSION_TYPE is not set to "unstable", and not building
a release, a confirmation is passed.

If the board is not specified as stable or unstable, during
a release build, the build is skipped and the ROM is not
provided in that release; this is in *addition* to
release="n" or release="y" that can be set in target.cfg,
which will skip the release build for that target if "n"

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-26 20:36:42 +01:00
Leah Rowe a2f4235358 i945: switch boards to 20230625 coreboot revision
On T60 with Libreboot 20231106 and the GRUB payload, a user
reported this error in GRUB when a battery was connected:

"alloc magic is broken at 0x7b1aedf0: 0"

This error disappears when a battery is not connected, or
when using Libreboot 20230625. The issue has persisted
through to LIbreboot 20240225 and after, and I believe the
issue will be somewhere in coreboot, not in GRUB itself.

For now, switch i945 laptops (X60, T60, Macbook2,1) back to
the February 2023 coreboot revision used in Libreboot 20230625.

A bisect can be done before the next Libreboot release, ETA
May 2024, if time permits. Otherwise, this revert should solve
the problem for now, at least so far as Libreboot is concerned.

The following coreboot patches have been backported:

    commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94
    Author: Bill Xie <persmule@hardenedlinux.org>
    Date:   Sat Oct 7 01:32:51 2023 +0800

        drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume

    Further patches from upstream:

    commit 432e92688eca0e85cbaebca3232f65936b305a98
    Author: Bill Xie <persmule@hardenedlinux.org>
    Date:   Fri Nov 3 12:34:01 2023 +0800

        drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum

These patches fixed S3 on GM45 machines, though it will be useful on
the i945 machines aswell.

The reason I'm doing it this way it is because I don't have a battery
for my X60 or T60, and my T60 isn't in a very good state either,
so I can't reproduce the error myself yet.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-26 09:55:55 +01:00
Leah Rowe 64177dbb8e exports variables from err.sh, not build
LC_COLLATE and LBMK_RELEASE are important variables. we want
to make sure that these are seen by everything.

since err.sh is included from all scripts, doing it there will
accomplish just that.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-26 08:20:19 +01:00
Leah Rowe a5082de43c GRUB: bump to today's latest revision
GRUB has not pushed many patches to master since the recent 2.12
release, but there are a number of interesting fixes.

libreboot is doing a release soon. bump to latest grub revision.

Some of the new patches in GRUB are interesting:

XFS fixes:

"fs/xfs: Handle non-continuous data blocks in directory extents"
68dd65cfdaad08b1f8ec01b84949b0bf88bc0d8c
Fixes: https://bugzilla.redhat.com/show_bug.cgi?id=2254370
Apparently, XFS could not boot in some reports, though this was
likely with BIOS or UEFI GRUB; no such reports were made to libreboot

"gfxmenu/view: Resolve false grub_errno disrupting boot process"
39c927df66c7ca62d97905d1385054ac9ce67209

"util/grub-fstest: Add a new command zfs-bootfs"
28c4405208cfb6e2cea737f6cbaf17e631bac6cd

The gnulib revision does not need to be updated at this time.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-26 05:12:04 +01:00
Leah Rowe ddfe71a366 9020 sff/mt: actually enable the TPM (by default)
i added mkukri's patch but didn't enable it. this was intentional.

this patch enables tpm by default, on all 9020 sff/mt targets.

most users probably won't need it, but enabling it won't hurt.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-26 05:10:12 +01:00
Leah Rowe 2d7debd33c 9020 sff/mt: add tpm enable patch from mate kukri
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-25 20:18:01 +01:00
Leah Rowe 08859bb4a5 lbmk: export TMPDIR from err.sh, not build
lbmk sets TMPDIR to /tmp, and then creates a tmpdir, then
exports *that* as the value of TMPDIR. this unified TMPDIR
location then contains all subsequent files and directories,
when any script or program makes use of /tmp, via mktemp. at
least, that's the theory!

in practise, because it was only being properly exported from
the main build scripts, subscripts that are then called were
not exporting it, at least that is my assumption because in
some cases, i found that the coreboot build system was leaving
errant files behind outside of our own TMPDIR, and that build
system did not seem to be setting TMPDIR itself; more debugging
is needed.

anyway: use the exact same logic, but do it from err.sh. since
err.sh is included from every lbmk script, that means it will
always be exported when running every single part of lbmk. this
should reduce the chance that mktemp creates files and directories
outside of our custom TMPDIR location.

this is because in lbmk, we mitigate unhandled tmpdirs/files by
unifying it in the manner described, then deleting the entire
TMPDIR on exit from the main lbmk parent process (the main
script that the user called from, which is always the "build"
file).

in lbmk, effort is made to clean up temporary files properly,
without relying on this catch-all, but we can't rely on that.
the catch-all should also be as robust as possible.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-25 19:08:53 +01:00
Leah Rowe f5f2c58a0e build/roms: add missing deletion of tmp file
the temporary rom per build was not being deleted after
finishing the current target. this adds up in /tmp during
large builds, when building for many targets. fix this!

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-25 19:03:43 +01:00
Leah Rowe 02e4c0b28e hp820g2: allow building, but don't do release ROMs
at present, the inject scripts compress refcode in a way
that is not reproducible, so there's no way to verify
that the firmware is correct, via checksum verification,
when injecting vendor code on release images

the lack of reproducibility in recompression will have to be
addressed, but the issue is that lbmk does not provide its own
sources for compression utilities, instead opting to use the
system's own compression utility

so the solution might be for lbmk not to use the host's utility,
and compile its own, or insert the refcode uncompressed. for now,
simply disable the hp 820 g2 target in libreboot releases

this uses the same logic recently implemented for excluding
mrc-based haswell images in libreboot releases

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-25 12:47:46 +01:00
Leah Rowe ed0678ae2e haswell: only provide NRI-based ROMs in releases
release="n" is set in target.cfg on haswell build targets
that use mrc.bin

script/update/release exports LBMK_RELEASE="y"

script/build/roms skips building a given target if release="n"
in target.cfg *and* LBMK_RELEASE="y"

you could also do the export yourself before running ./build roms,
for example:

export LBMK_RELEASE="y"
./build roms all

This would skip these ROM images. The native haswell raminit is
now stable enough in my testing, that I wish to delete the MRC-based
targets. This is in line with Libreboot's Binary Blob Reduction Policy,
which states: if a blob can be avoided, it should be avoided.

The problem is that users often run the inject script in *lbmk* from
Git, instead of from the src release archive. I forsee some users
running this on modern lbmk with older release images. If the mrc-based
target isn't there, the user may use an NRI-based target name, and
think it works; they will insert without MRC. I foresaw this ages
ago, which is why Caleb and I ensured that the script checks hashes,
and hashes are included in releases.

Therefore: for the time being, keep the MRC-based configs in lbmk
but do not include images for them in releases. This can be done
indefinitely, but I'll probably remove those configs entirely at
some point.

On the following boards, Libreboot now will *only* provide NRI-based
ROM images for the following machines:

* Dell OptiPlex 9020 SFF
* Dell OptiPlex 9020 MT
* Lenovo ThinkPad T440p
* Lenovo ThinkPad W541/W540

I now recommend exclusive use of NRI-based images, on Haswell
hardware. It's stable enough in my testing, and now supports S3.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-24 05:27:27 +01:00
Leah Rowe f5035e327a 9020 sff/mt: fix bad gpio read on hwm patch
sff happened to work, but mt would not boot with the patch,
because it called die() on unknown chassis type, and the gpio
happened to have a bad value in the old patch, because it wasn't
reading the right gpio.

i tested the fix on the old patch, but then decided to use
mate's new patch because instead of calling die(), it simply
boots with fan control disabled (max fan speed in that case),
if this happens again.

mt and sff have both been tested with this new version of the
patch. both of them boot, and they both have proper fan control.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-21 21:55:57 +01:00
Leah Rowe 523f1df9bf w541 libremrc: disable tseg stage cache
a hangover from earlier days, but i still disable it. i forgot
to do so on this config, when updating the nri code. do it now.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-21 03:16:43 +01:00
Leah Rowe c557e9e0e1 haswell nri: set 8MB CBFS on thinkpads (fix S3)
hell added a patch fixing S3 on haswell NRI, but it seems
you still need to set 8MB CBFS size as with the MRC

tested on a t440p. S3 now works on haswell NRI.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-21 01:52:29 +01:00
Leah Rowe ac7ce93005 add 9020sff/mt configs using haswell NRI
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-20 22:54:34 +01:00
Leah Rowe 9e3b217cfd update coreboot/haswell (NRI)
the t440p/w541 configs were re-done from scratch, because
the coreboot revisions are nearly two years apart.

i also added corebootfb configs.

hell updated their patchset. this patchset uses the following patch:

https://review.coreboot.org/c/coreboot/+/81948/1

it uses this, along with parent patches in the haswell nri patch series

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-20 22:12:04 +01:00
Leah Rowe 6da91df6b9 add mate's patch for 9020 sff/mt fan controls
see:

https://review.coreboot.org/c/coreboot/+/81529

what i've merged is patchset 4. i had to rebase it slightly,
because the libreboot version has the iommu toggle on cmos
configs, which are files that mate's patch also changes,
leading to merge conflict.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-07 04:17:36 +01:00
Leah Rowe 831954899c enable grub payload on libremrc w541/t440p
the grub payload was previously disabled, because the libre
mrc code sets up xhci rather than ehci, and grub did not have
xhci support (not natively).

libreboot now has xhci support in the grub payload, so enable
grub on these configurations.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-06 16:00:57 +01:00
Leah Rowe e9c591a554 add t440p/w541 configs using broadwell mrc
broadwell mrc enables both igpu and dgpu to be enabled
at any given time. if the onboard (intel) gpu is set as
primary, the logic to disable it is not executed within
coreboot; instead, the igpu is used for vga decode.

on some t440p/w541 thinkpads, both an intel and nvidia
gpu are present. in this setup, the intel gpu must be
used for vga, and all output, but rendering can be
offloaded to the nvidia gpu (nvidia optimus).

optimus would never work on haswell mrc.bin, because it
always disables the igpu when a dgpu is present, so a hack
exists in coreboot that hides the dgpu from mrc, so that the
igpu remains enabled. broadwell mrc doesn't do this, so the
option to hide PEG devices has been disabled in these
configs.

the broadwell mrc has better peg device handling, and can
support 16gb modules on broadwell hardware; it may well
support these modules on haswell hardware too, though ddr3
sodimms are very hard to find (and expensive). (and currently
untested, with this patch)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-06 02:09:04 +01:00
Leah Rowe 4134a883d0 add 9020 sff/mt targets that use broadwell mrc
broadwell mrc has better peg handling and can support 16gb
modules on broadwell machines - the blob can be used on haswell
machines too, instead of haswell mrc, and it might support 16gb
modules on these machines (not yet tested, but using broadwell
mrc does at least boot as reliably as haswell mrc anyway)

one little quirk with haswell mrc is that it actually handles
vga decode, disabling the igpu entirely, when a dgpu is used.
the broadwell mrc enables both GPUs and does not handle vga
decoding, so we must handle this the usual way; my patch for
this was merged upstream and i'm also adding it to libreboot,
which currently uses an older coreboot revision. this is needed
for dgpu to work. see patch:

0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch

broadwell mrc may also make dealing with nvidia optimus setups
more reliable, on laptops that have nvidia GPUs, but this patch
does not add bmrc configs for t440p/w541

NOTE: on t440p/w541 laptops with nvidia graphics, the video output
is wired to intel but rendering can be offloaded to nvidia. in this
setup, we want vga decode to be done on intel, so i've set these
configs to enable CONFIG_ONBOARD_VGA_IS_PRIMARY (set it to y)

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-06 01:28:10 +01:00
Leah Rowe f7283fa10d grub xhci support
see:

https://github.com/9elements/grub/commits/xhci-module-upstreaming-squash_v4/

grub only supports xhci on bios/uefi targets, but not coreboot.
some newer machines don't have ps/2 controllers, and boot in a
way where ehci isn't available at startup; the controller can't
be used by ehci code, there must be xhci support.

the code is from Patrick Rudolph working on behalf of 9elements.
the code was also sent here for review:

https://lists.gnu.org/archive/html/grub-devel/2020-12/msg00111.html

however, upstream never merged these patches. libreboot will have
to maintain these from now on. the patches have been rebased for
use with grub 2.12.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-04-05 23:44:06 +01:00
Leah Rowe 5cb17795c6 fix sata slots on dell 9020 sff and mt
3rd sata slot (of 3) broken on 9020 sff, and the 3rd and 4th (of 4)
slots are broken on 9020 mt

this patch fixes them on both, so that all ports work properly

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-03-30 06:06:09 +00:00
Leah Rowe 332778973c allow users to specify number of build threads
lbmk otherwise uses nproc to set the number of build threads,
in these places:

* generic make commands in script/update/trees
* crossgcc make command in script/update/trees

the -T0 option is also used in script/update/release, when running
tar.

with this change, you can do:

export LBMK_THREADS=x

where x is the number of threads. when you then run
lbmk, your chosen number of threads will override
the default. this may be useful on a host that does
not have a lot of memory.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-03-27 07:38:16 +00:00
Leah Rowe 6ebab10caa safer, simpler error handling in lbmk
in shell scripts, a function named the same as a program included in
the $PATH will override that program. for example, you could make a
function called ls() and this would override the standand "ls".

in lbmk, a part of it was first trying to run the "fail" command,
deferring to "err", because some scripts call fail() which does
some minor cleanup before calling err.

in most cases, fail() is not defined, and it's possible that the user
could have a program called "fail" in their $PATH, the behaviour of
which we could not determine, and it could have disastrous effects.

lbmk error handling has been re-engineered in such a way that the
err function is defined in a variable, which defaults to err_ which
calls err_, so defined under include/err.sh.

in functions that require cleanup prior to error handling, a fail()
function is still defined, and err is overridden, thus:

err="fail"

this change has made xx_() obsolete, so now only x_ is used. the x_
function is a wrapper that can be used to run a command and exit with
non-zero status (from lbmk) if the command fails. the xx_ command
did the same thing, but called fail() which would have called err();
now everything is $err

example:

	rm -f "$filename" || err "could not delete file"

this would now be:

	rm -f "$filename" || $err "could not delete file"

overriding of err= must be done *after* including err.sh. for
example:

err="fail"
. "include/err.sh"

^ this is wrong. instead, one must do:

. "include/err.sh"
err="fail"

this is because err is set as a global variable under err.sh

the new error handling is much cleaner, and safer. it also reduces
the chance of mistakes such as: calling err when you meant to
call fail. this is because the standard way is now to call $err,
so you set err="fail" at the top of the script and all is well.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-03-27 01:50:31 +00:00
Leah Rowe 6b11f1b055 Merge pull request 'config: Add Dell Latitude E5420' (#191) from nic3-14159/lbmk:latitude-ports into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/191
2024-03-19 00:06:51 +00:00
Leah Rowe 457a7037d8 Merge pull request 'util: Import autoport with Haswell patches' (#195) from nic3-14159/lbmk:autoport-fork into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/195
2024-03-18 23:59:32 +00:00
Nicholas Chin 8cba237086 util: Import autoport with Haswell patches
This is a copy of coreboot's autoport utility, with a patch applied to
support Haswell/Lynx Point platforms. That patch is currently in review
on coreboot's Gerrit.

https://review.coreboot.org/c/coreboot/+/30890

Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-03-18 10:45:05 -06:00
linear cannon e119ffa54d dell-flash-unlock: add NetBSD support 2024-03-16 01:33:10 -04:00
Leah Rowe c578fe56c3 Merge pull request 'Use proper autolink' (#192) from eo/lbmk:master into master
Reviewed-on: https://codeberg.org/libreboot/lbmk/pulls/192
2024-03-12 21:17:31 +00:00
Leo Heitmann Ruiz 98caceb1ce Use proper autolink 2024-03-05 20:33:17 +00:00
Nicholas Chin 036bf2c69a config: Add Dell Latitude E5420
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
2024-03-04 18:28:58 -07:00
Leah Rowe 665840b2b9 coreboot/dell9020*_12mb: Disable IOMMU by default
Needed to make graphics cards work. Turn it on if you're using
only the Intel GPU.

With IOMMU *enabled*, graphics cards do not work reliably at all.
The cause still needs to be investigated, but the symptoms are
graphical corruption on the screen, and Xorg usually crashes.
In some cases (on some cards), TTYs can still be used; the payload
can still be used reliably, on a graphics card, but Xorg fails to
work properly.

This could be a bug in Linux drivers, instead of anything that
coreboot does (not yet tested in factory BIOS).

Leaving it off by default will ensure reliable operation on all
setups, whether an iGPU or dGPU is used.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-03-02 23:13:43 +00:00
Leah Rowe 944cafa230 coreboot/haswell: make IOMMU a runtime option
It is now possible to disable the IOMMU on Haswell
boards, by doing this on your ROM image:

./nvramtool -C libreboot.rom -w iommu=Disable

To enable it again, do this:

./nvramtool -C libreboot.rom -w iommu=Enable

If not specified, the default behaviour is *on*.
A follow-up patch will turn IOMMU *off* by default,
on Dell OptiPlex 9020 SFF/MT, by setting it as such
in cmos.default. This is to make graphics cards work
properly to work around a bug when it's turned on.

Leaving the IOMMU enabled is recommended, if it works.
It works in most cases, including on 9020 SFF/MT when
using the Intel GPU without a graphics card inserted.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-03-02 23:12:54 +00:00
Leah Rowe db074b785c enable serial console on fam15h boards
Signed-off-by: Leah Rowe <leah@libreboot.org>
2024-02-27 18:52:31 +00:00
1176 changed files with 97226 additions and 38724 deletions
+17 -1
View File
@@ -1,8 +1,9 @@
*~
*.o
/cache/
/lbmk.err.log
/repo/
/docs/
/cbutils/
/pciroms/
/util/dell-flash-unlock/dell_flash_unlock
/TODO
@@ -23,9 +24,24 @@
/push
/version
/versiondate
/.version
/.versiondate
/vendorfiles/
*me.bin
*sch5545ec.bin
/mrc/
/util/nvmutil/nvm
/src/
/CHANGELOG
/todo.txt
/lock
/hash/
/dump/
/qrun*.sh
*.tar.*
/m
/f
/r
/e
/xbmkpath/
/xbmkwd/
+39 -105
View File
@@ -1,123 +1,57 @@
Libreboot
=========
Find libreboot documentation at <https://libreboot.org/>
Documentation: [libreboot.org](https://libreboot.org)\
Support: [\#libreboot](https://web.libera.chat/#libreboot) on
[Libera](https://libera.chat/) IRC
The `libreboot` project provides
[libre](https://libreboot.org/freedom-status.html) *boot
firmware* that initializes the hardware (e.g. memory controller, CPU,
peripherals) on specific Intel/AMD x86 and ARM targets, which
then starts a bootloader for your operating system. Linux/BSD are
well-supported. It replaces proprietary BIOS/UEFI firmware. Help is available
via [\#libreboot IRC](https://web.libera.chat/#libreboot)
on [Libera](https://libera.chat/) IRC.
Libreboot provides
[libre](https://libreboot.org/freedom-status.html)
boot firmware on
[supported motherboards](https://libreboot.org/docs/install/#which-systems-are-supported-by-libreboot). It replaces proprietary vendor BIOS/UEFI implementations, by
* Using coreboot to initialize the hardware (e.g. memory controller, CPU, etc.) while
minimizing unwanted functionality (e.g. backdoors such as the Intel Management Engine)
* ... which runs a payload such as SeaBIOS, GRUB, or U-Boot
* ... which loads your operating system's boot loader (BSD and Linux-based
[systems](systems) are supported).
Why use Libreboot?
==================
Why use Libreboot, and what is coreboot?
----------------------------------------
Why should you use *libreboot*?
----------------------------
A lot of users who use libre operating systems still use proprietary boot
firmware, which often contain backdoors and bugs, hampering
[user freedom](https://writefreesoftware.org) and
[right to repair](https://www.eff.org/issues/right-to-repair).
Libreboot gives you freedoms that you otherwise can't get with most other
boot firmware. It's extremely powerful and configurable for many use cases.
[coreboot](https://coreboot.org) provides libre boot firmware by initializing
the hardware then running a payload. However, coreboot is notoriously difficult
to configure and install for most non-technical users, requiring detailed
technical knowledge of hardware.
You have rights. The right to privacy, freedom of thought, freedom of speech
and the right to read. In this context, Libreboot gives you these rights.
Your freedom matters.
[Right to repair](https://vid.puffyan.us/watch?v=Npd_xDuNi9k) matters.
Many people use proprietary (non-libre)
boot firmware, even if they use [a libre OS](https://www.openbsd.org/).
Proprietary firmware often contains backdoors (more info on the FAQ), and it
and can be buggy. The libreboot project was founded in December 2013,
with the express purpose of making coreboot firmware accessible for
non-technical users.
Libreboot solves this by being **a coreboot distribution** (in the same way
that Alpine Linux is a Linux distribution). It provides a fully automated build
system that downloads and compiles pre-configured ROM images for supported
motherboards, so end-users could easily fetch images to flash onto their
devices.
The `libreboot` project uses [coreboot](https://www.coreboot.org/) for [hardware
initialisation](https://doc.coreboot.org/getting_started/architecture.html).
Coreboot is notoriously difficult to install for most non-technical users; it
handles only basic initialization and jumps to a separate
[payload](https://doc.coreboot.org/payloads.html) program (e.g.
[GRUB](https://www.gnu.org/software/grub/),
[Tianocore](https://www.tianocore.org/)), which must also be configured.
*The libreboot software solves this problem*; it is a *coreboot distribution* with
an automated build system (named *lbmk*) that builds complete *ROM images*, for
more robust installation. Documentation is provided.
Libreboot also produces documentation aimed at non-technical users and
excellent user support via IRC.
How does Libreboot differ from coreboot?
========================================
In the same way that *Debian* is a GNU+Linux distribution, `libreboot` is
a *coreboot distribution*. If you want to build a ROM image from scratch, you
otherwise have to perform expert-level configuration of coreboot, GRUB and
whatever other software you need, to prepare the ROM image. With *libreboot*,
you can literally download from Git or a source archive, and run `make`, and it
will build entire ROM images. An automated build system, named `lbmk`
(Libreboot MaKe), builds these ROM images automatically, without any user input
or intervention required. Configuration has already been performed in advance.
If you were to build regular coreboot, without using libreboot's automated
build system, it would require a lot more intervention and decent technical
knowledge to produce a working configuration.
Regular binary releases of `libreboot` provide these
ROM images pre-compiled, and you can simply install them, with no special
knowledge or skill except the ability to follow installation instructions
and run commands BSD/Linux.
Project goals
=============
- *Support as much hardware as possible!* Libreboot aims to eventually
have *maintainers* for every board supported by coreboot, at every
point in time.
- *Make coreboot easy to use*. Coreboot is notoriously difficult
to install, due to an overall lack of user-focused documentation
and support. Most people will simply give up before attempting to
install coreboot. Libreboot's automated build system and user-friendly
installation instructions solves this problem.
Libreboot attempts to bridge this divide by providing a build system
automating much of the coreboot image creation and customization.
Secondly, the project produces documentation aimed at non-technical users.
Thirdly, the project attempts to provide excellent user support via IRC.
Libreboot already comes with a payload (GRUB), flashprog and other
needed parts. Everything is fully integrated, in a way where most of
the complicated steps that are otherwise required, are instead done
for the user in advance.
You can download ROM images for your libreboot system and install
them without having to build anything from source. If, however, you are
interested in building your own image, the build system makes it relatively
easy to do so.
Not a coreboot fork!
--------------------
Libreboot is not a fork of coreboot. Every so often, the project
re-bases on the latest version of coreboot, with the number of custom
patches in use minimized. Tested, *stable* (static) releases are then provided
in Libreboot, based on specific coreboot revisions.
How to help
===========
Contribute
----------
You can check bugs listed on
the [bug tracker](https://codeberg.org/libreboot/lbmk/issues).
If you spot a bug and have a fix, the website has instructions for how to send
patches, and you can also report it. Also, this entire website is
written in Markdown and hosted in a [separate
repository](https://codeberg.org/libreboot/lbwww) where you can send patches.
You may use Codeberg pull requests to send patches with bug fixes or other
improvements. This repository hosts the code for the main build system.
The website lives in [a separate repository](https://codeberg.org/libreboot/lbwww).
Any and all development discussion and user support are all done on the IRC
channel. More information is on https://libreboot.org/contact.html.
Development is also done on the IRC channel.
LICENSE FOR THIS README
=======================
License for this README
-----------------------
It's just a README file. This README file is released under the terms of the
Creative Commons Zero license, version 1.0 of the license, which you can
read here:
It's just a README file. It is released under
[Creative Commons Zero, version 1.0](https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt).
<https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt>
-150
View File
@@ -1,150 +0,0 @@
#!/usr/bin/env sh
# SPDX-License-Identifier: GPL-3.0-or-later
# SPDX-FileCopyrightText: 2014,2015,2020,2021,2023 Leah Rowe <leah@libreboot.org>
# SPDX-FileCopyrightText: 2015 Patrick "P. J." McDermott <pj@pehjota.net>
# SPDX-FileCopyrightText: 2015, 2016 Klemens Nanni <contact@autoboot.org>
# SPDX-FileCopyrightText: 2022, Caleb La Grange <thonkpeasant@protonmail.com>
set -u -e
export LC_COLLATE=C
export LC_ALL=C
. "include/err.sh"
. "include/option.sh"
eval "$(setvars "" option aur_notice tmpdir)"
tmpdir_was_set="y"
set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n"
if [ "${tmpdir_was_set}" = "y" ]; then
[ "${TMPDIR%_*}" = "/tmp/lbmk" ] || tmpdir_was_set="n"
fi
if [ "${tmpdir_was_set}" = "n" ]; then
export TMPDIR="/tmp"
tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)"
export TMPDIR="${tmpdir}"
else
export TMPDIR="${TMPDIR}"
tmpdir="${TMPDIR}"
fi
linkpath="${0}"
linkname="${linkpath##*/}"
buildpath="./script/${linkname}"
main()
{
xx_ id -u 1>/dev/null 2>/dev/null
[ $# -lt 1 ] && fail "Too few arguments. Try: ${0} help"
[ "$1" = "dependencies" ] && xx_ install_packages $@ && lbmk_exit 0
for cmd in initcmd check_git check_project git_init excmd; do
eval "${cmd} \$@"
done
lbmk_exit 0
}
initcmd()
{
[ "$(id -u)" != "0" ] || fail "this command as root is not permitted"
check_project
case "${1}" in
help) usage ${0} ;;
list) items "${buildpath}" ;;
version) mkversion ;;
*)
option="${1}"
return 0 ;;
esac
lbmk_exit 0
}
install_packages()
{
if [ $# -lt 2 ]; then
printf "You must specify a distro, namely:\n" 1>&2
printf "Look at files under config/dependencies/\n" 1>&2
printf "Example: ./build dependencies debian\n" 1>&2
fail "install_packages: target not specified"
fi
[ -f "config/dependencies/${2}" ] || fail "Unsupported target"
. "config/dependencies/${2}"
xx_ ${pkg_add} ${pkglist}
[ -z "${aur_notice}" ] && return 0
printf "You must install AUR packages: %s\n" "$aur_notice" 1>&2
}
# release archives contain .gitignore, but not .git.
# lbmk can be run from lbmk.git, or an archive.
git_init()
{
[ -L ".git" ] && fail "Reference .git is a symlink"
[ -e ".git" ] && return 0
eval "$(setvars "$(date -Rd @${versiondate})" cdate _nogit)"
git init || fail "${PWD}: cannot initialise Git repository"
git add -A . || fail "${PWD}: cannot add files to Git repository"
git commit -m "${projectname} ${version}" --date "${cdate}" \
--author="lbmk <lbmk@libreboot.org>" || \
fail "$PWD: can't commit ${projectname}/${version}, date $cdate"
git tag -a "${version}" -m "${projectname} ${version}" || \
fail "${PWD}: cannot git-tag ${projectname}/${version}"
}
excmd()
{
lbmkcmd="${buildpath}/${option}"
[ -f "${lbmkcmd}" ] || fail "Invalid command. Run: ${linkpath} help"
shift 1; "$lbmkcmd" $@ || fail "excmd: ${lbmkcmd} ${@}"
}
usage()
{
progname=${0}
cat <<- EOF
$(mkversion)
USAGE: ${progname} <OPTION>
possible values for 'OPTION':
$(items "${buildpath}")
To know what ${projectname} version you're on, type:
${progname} version
Refer to ${projectname} documentation for more info.
EOF
}
mkversion()
{
printf "revision: %s %s\n" "$projectname" "$version"
printf "revision date: %s\n" "$(date -Rud @${versiondate})"
}
lbmk_exit()
{
tmp_cleanup || err "lbmk_exit: can't rm tmpdir upon exit $1: $tmpdir"
exit $1
}
fail()
{
tmp_cleanup || printf "WARNING: can't rm tmpdir: %s\n" "$tmpdir" 1>&2
err "${1}"
}
tmp_cleanup()
{
[ "${tmpdir_was_set}" = "n" ] || return 0
rm -Rf "${tmpdir}" || return 1
}
main $@
@@ -1,56 +0,0 @@
From f22f408956bf02609a96b7d72fb3321da159bfc6 Mon Sep 17 00:00:00 2001
From: Nico Huber <nico.huber@secunet.com>
Date: Tue, 22 Jun 2021 13:49:44 +0000
Subject: [PATCH 1/1] cbfstool: Make use of spurious null-termination
The null-termination of `filetypes` was added after the code was
written, obviously resulting in NULL dereferences. As some more
code has grown around the termination, it's hard to revert the
regression, so let's update the code that still used the array
length.
This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
which actually did fix something, but only one path while it broke
two others. We should be careful with fixes, they can always break
something else. Especially when a dumb tool triggered the patching
it seems likely that fewer people looked into related code.
Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
---
util/cbfstool/common.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
index e2ed38ffc4..539d0baccf 100644
--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
@@ -168,10 +168,10 @@ void print_supported_architectures(void)
void print_supported_filetypes(void)
{
- int i, number = ARRAY_SIZE(filetypes);
+ int i;
- for (i=0; i<number; i++) {
- printf(" %s%c", filetypes[i].name, (i==(number-1))?'\n':',');
+ for (i=0; filetypes[i].name; i++) {
+ printf(" %s%c", filetypes[i].name, filetypes[i + 1].name ? ',' : '\n');
if ((i%8) == 7)
printf("\n");
}
@@ -180,7 +180,7 @@ void print_supported_filetypes(void)
uint64_t intfiletype(const char *name)
{
size_t i;
- for (i = 0; i < (sizeof(filetypes) / sizeof(struct typedesc_t)); i++)
+ for (i = 0; filetypes[i].name; i++)
if (strcmp(filetypes[i].name, name) == 0)
return filetypes[i].type;
return -1;
--
2.39.2
-2
View File
@@ -1,2 +0,0 @@
tree="coreboot413"
rev="5c186c6777c9438ff4681929c9c25c98dee28bef"
@@ -6,22 +6,23 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
@@ -37,7 +38,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@@ -55,10 +55,11 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@@ -67,23 +68,30 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@@ -93,6 +101,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@@ -103,7 +112,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
CONFIG_MAINBOARD_VERSION="1.0"
@@ -119,22 +130,26 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
# CONFIG_CONSOLE_POST is not set
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -150,8 +165,6 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -159,7 +172,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@@ -178,6 +193,7 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -193,6 +209,14 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@@ -200,17 +224,16 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_EC_GPE_SCI=0x50
CONFIG_HEAP_SIZE=0x100000
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -249,7 +272,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x80000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -258,18 +283,21 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# CONFIG_TOP_SWAP_REDUNDANCY is not set
#
# CPU
@@ -293,6 +321,7 @@ CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -347,6 +376,7 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -359,7 +389,6 @@ CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -370,6 +399,10 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@@ -386,12 +419,14 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -410,15 +445,18 @@ CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
CONFIG_DRAM_SUPPORT_DDR3=y
CONFIG_DRAM_SUPPORT_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -436,6 +474,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -457,6 +496,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@@ -509,7 +550,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console
@@ -584,7 +624,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@@ -598,9 +637,17 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
+4 -2
View File
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="y"
payload_memtest="y"
release="n"
build_depend="seabios/default memtest86plus"
@@ -6,22 +6,23 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
@@ -37,7 +38,6 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@@ -55,10 +55,11 @@ CONFIG_NO_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@@ -67,23 +68,30 @@ CONFIG_NO_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@@ -93,6 +101,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@@ -103,7 +112,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
CONFIG_MAINBOARD_VERSION="1.0"
@@ -119,22 +130,26 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
# CONFIG_CONSOLE_POST is not set
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -150,8 +165,6 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -159,7 +172,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@@ -178,6 +193,7 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -193,6 +209,14 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@@ -200,17 +224,16 @@ CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_EC_GPE_SCI=0x50
CONFIG_HEAP_SIZE=0x100000
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -249,7 +272,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x80000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -258,18 +283,21 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# CONFIG_TOP_SWAP_REDUNDANCY is not set
#
# CPU
@@ -293,6 +321,7 @@ CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -347,6 +376,7 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -359,7 +389,6 @@ CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -370,6 +399,10 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@@ -386,12 +419,14 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -410,15 +445,18 @@ CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
CONFIG_DRAM_SUPPORT_DDR3=y
CONFIG_DRAM_SUPPORT_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -436,6 +474,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -457,6 +496,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@@ -509,7 +550,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console
@@ -584,7 +624,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@@ -598,9 +637,17 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
+4 -1
View File
@@ -1,5 +1,8 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
payload_seabios_withgrub="y"
payload_grub="y"
payload_memtest="y"
release="n"
@@ -6,22 +6,23 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
@@ -37,7 +38,6 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@@ -55,10 +55,11 @@ CONFIG_TSEG_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@@ -67,23 +68,30 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@@ -93,6 +101,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@@ -103,7 +112,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
CONFIG_MAINBOARD_VERSION="1.0"
@@ -119,23 +130,27 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
# CONFIG_CONSOLE_POST is not set
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -151,8 +166,6 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -160,7 +173,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@@ -179,6 +194,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -194,6 +210,14 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@@ -201,15 +225,14 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
CONFIG_EC_GPE_SCI=0x50
CONFIG_HEAP_SIZE=0x100000
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
CONFIG_COREBOOT_ROMSIZE_KB_512=y
@@ -248,7 +271,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -257,18 +282,21 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# CONFIG_TOP_SWAP_REDUNDANCY is not set
#
# CPU
@@ -292,6 +320,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -346,6 +375,7 @@ CONFIG_SUPERIO_SMSC_LPC47M15X=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -358,7 +388,6 @@ CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -369,6 +398,10 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@@ -385,12 +418,14 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -406,14 +441,17 @@ CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_USE_DDR2=y
CONFIG_DRAM_SUPPORT_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -431,6 +469,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -451,6 +490,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@@ -503,7 +544,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console
@@ -582,7 +622,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@@ -597,9 +636,17 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
+4 -3
View File
@@ -1,6 +1,7 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="y"
payload_memtest="n"
release="n"
build_depend="seabios/default"
@@ -6,22 +6,23 @@
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
@@ -37,7 +38,6 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
@@ -55,10 +55,11 @@ CONFIG_TSEG_STAGE_CACHE=y
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
@@ -67,23 +68,30 @@ CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
@@ -93,6 +101,7 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
@@ -103,7 +112,9 @@ CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
CONFIG_MAINBOARD_VERSION="1.0"
@@ -119,23 +130,27 @@ CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
# CONFIG_CONSOLE_POST is not set
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -151,8 +166,6 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -160,7 +173,9 @@ CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
@@ -179,6 +194,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -194,6 +210,14 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
#
# Ptlrvp
#
# CONFIG_BOARD_INTEL_PTLRVP is not set
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
@@ -201,15 +225,14 @@ CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
CONFIG_EC_GPE_SCI=0x50
CONFIG_HEAP_SIZE=0x100000
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -248,7 +271,9 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_CPU_PT_ROM_MAP_GB=4
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -257,18 +282,21 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
# CONFIG_TOP_SWAP_REDUNDANCY is not set
#
# CPU
@@ -292,6 +320,7 @@ CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -346,6 +375,7 @@ CONFIG_SUPERIO_SMSC_LPC47M15X=y
#
# Embedded Controllers
#
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -358,7 +388,6 @@ CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
@@ -369,6 +398,10 @@ CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
@@ -385,12 +418,14 @@ CONFIG_NO_EARLY_GFX_INIT=y
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -406,14 +441,17 @@ CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_USE_DDR2=y
CONFIG_DRAM_SUPPORT_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -431,6 +469,7 @@ CONFIG_SPI_FLASH_ISSI=y
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -451,6 +490,8 @@ CONFIG_DRIVERS_MC146818=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
@@ -503,7 +544,6 @@ CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_HEAP_SIZE=0x100000
#
# Console
@@ -582,7 +622,6 @@ CONFIG_PAYLOAD_NONE=y
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
@@ -597,9 +636,17 @@ CONFIG_HAVE_DEBUG_SMBUS=y
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
+5 -3
View File
@@ -1,6 +1,8 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="y"
payload_memtest="n"
payload_grub="y"
release="n"
build_depend="seabios/default grub/default"
+18
View File
@@ -0,0 +1,18 @@
3rdparty/fsp/EagleStreamFspBinPkg
3rdparty/fsp/MeteorLakeFspBinPkg
3rdparty/fsp/IceLakeFspBinPkg
3rdparty/fsp/AmberLakeFspBinPkg
3rdparty/fsp/DenvertonNSFspBinPkg
3rdparty/fsp/TigerLakeFspBinPkg
3rdparty/fsp/CedarIslandFspBinPkg
3rdparty/fsp/ElkhartLakeFspBinPkg
3rdparty/fsp/CometLakeFspBinPkg
3rdparty/fsp/WhitleyFspBinPkg
3rdparty/fsp/ArrowLakeFspBinPkg
3rdparty/fsp/IdavilleFspBinPkg
3rdparty/fsp/BraswellFspBinPkg
3rdparty/fsp/CoffeeLakeFspBinPkg
3rdparty/fsp/RaptorLakeFspBinPkg
3rdparty/fsp/ApolloLakeFspBinPkg
3rdparty/fsp/SkylakeFspBinPkg
3rdparty/vboot/tests
@@ -1,7 +1,7 @@
From 50a52cea2b43e6e407b456c082e908c7d29e090b Mon Sep 17 00:00:00 2001
From 4e350ac1b7d5f27ae0887bb016d748b0987ad14d Mon Sep 17 00:00:00 2001
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
Date: Wed, 27 Oct 2021 13:36:01 +0200
Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
Subject: [PATCH 01/41] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +
@@ -10,10 +10,10 @@ Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
3 files changed, 20 insertions(+)
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
index 5f5ffde588..27377b737c 100644
index 330d8efae2..cf10343554 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select I945_LVDS
@@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644
end
end
--
2.39.2
2.47.3
@@ -1,23 +0,0 @@
From 1195c954a3b6822e5e843067251c0c80c9520eab Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@retroboot.org>
Date: Fri, 19 Mar 2021 05:54:58 +0000
Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of
8MiB
---
src/mainboard/apple/macbook21/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
index cf1bc4566e..dc0df3b6d6 100644
--- a/src/mainboard/apple/macbook21/cmos.default
+++ b/src/mainboard/apple/macbook21/cmos.default
@@ -5,4 +5,4 @@ boot_devices=''
boot_default=0x40
cmos_defaults_loaded=Yes
lpt=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2
@@ -1,7 +1,7 @@
From 80ebbfef42454ea0911e5fc3858103d905987ed8 Mon Sep 17 00:00:00 2001
From 0322228c25be7d95e7dbcc905dec81960905152b Mon Sep 17 00:00:00 2001
From: persmule <persmule@gmail.com>
Date: Sun, 31 Oct 2021 23:33:26 +0000
Subject: [PATCH 09/30] lenovo/t400: Enable all SATA ports
Subject: [PATCH 02/41] lenovo/t400: Enable all SATA ports
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -15,7 +15,7 @@ This patch unmasked all SATA ports found within t400s with factory firmware.
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index 259c3e1b21..3d007533a4 100644
index 9e056772e9..9361f330d2 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
@@ -30,5 +30,5 @@ index 259c3e1b21..3d007533a4 100644
register "sata_traffic_monitor" = "0"
--
2.39.2
2.47.3
@@ -1,7 +1,7 @@
From 47afbe8b94edd1ff58c1daf0bda020e6afac35f4 Mon Sep 17 00:00:00 2001
From 4714f4388bf90fc7ff3d25dd62feec07de5f4c7e Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 3 Jan 2022 19:06:22 +0000
Subject: [PATCH 11/30] lenovo/x230: set me_state=Disabled in cmos.default
Subject: [PATCH 03/41] lenovo/x230: set me_state=Disabled in cmos.default
I only recently found out about this. It's possible to use me_cleaner to
do the same thing, but some people might just flash coreboot and not do
@@ -23,16 +23,15 @@ Date: Thu Nov 21 21:47:31 2019 +0300
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 2e315d4521..3585cbd58b 100644
index 732e214b32..8454f0eac0 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -15,5 +15,5 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
gfx_uma_size=224M
--
2.39.2
2.47.3
@@ -1,23 +0,0 @@
From ca4cd66f411247395a323e5ea1abf09e83057827 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Sun, 3 Jan 2021 03:34:01 +0000
Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default
(previously it was 8MiB)
---
src/mainboard/lenovo/x60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
index 5c3576d1f3..88170a1aab 100644
--- a/src/mainboard/lenovo/x60/cmos.default
+++ b/src/mainboard/lenovo/x60/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2
@@ -1,22 +0,0 @@
From eca0f4a3a4d6907e92b948547a362ca0ac3fc382 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Mon, 22 Feb 2021 22:16:59 +0000
Subject: [PATCH 04/30] lenovo/t60: make 64MiB VRAM the default in cmos.default
---
src/mainboard/lenovo/t60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
index af865f16da..7f03157df7 100644
--- a/src/mainboard/lenovo/t60/cmos.default
+++ b/src/mainboard/lenovo/t60/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2
@@ -1,7 +1,7 @@
From 531ef34ece796f38cb8a13a54856e46e79842e29 Mon Sep 17 00:00:00 2001
From 0d8c12b68060ebfe4df4cf0d7cb1abd4c2b2243b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 2 Mar 2022 21:50:01 +0000
Subject: [PATCH 12/30] set me_state=Disabled on all cmos.default files!
Subject: [PATCH 04/41] set me_state=Disabled on all cmos.default files!
yeah. why the hell isn't this the default
@@ -20,103 +20,105 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
10 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
index 681c40e78b..57cdcf9162 100644
index be08e0a342..b8970efa46 100644
--- a/src/mainboard/lenovo/l520/cmos.default
+++ b/src/mainboard/lenovo/l520/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
@@ -16,4 +16,4 @@ sticky_fn=Disable
trackpoint=Enable
backlight=Both
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
index 8244071b8a..c011867916 100644
index 6fd26c5fe3..27a62d07b3 100644
--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
@@ -16,4 +16,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
index 8244071b8a..c011867916 100644
index 6fd26c5fe3..27a62d07b3 100644
--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
@@ -16,4 +16,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
index 26795fe5cf..55e1e6c04e 100644
index c896eadec1..6d1e172056 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
hybrid_graphics_mode=Integrated Only
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
index 52dbf70377..b16800ca9e 100644
index 286fb0ae8c..5a05c73721 100644
--- a/src/mainboard/lenovo/t430s/cmos.default
+++ b/src/mainboard/lenovo/t430s/cmos.default
@@ -16,4 +16,4 @@ backlight=Both
@@ -18,4 +18,4 @@ backlight=Both
enable_dual_graphics=Disable
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
index cf79b391e2..b66f7034dc 100644
index 4857f92f67..ab1be1a678 100644
--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
index cf79b391e2..b66f7034dc 100644
index 4857f92f67..ab1be1a678 100644
--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
@@ -17,4 +17,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
index 6d1d57a795..52f303dfdb 100644
index ef706c1303..b318ab9772 100644
--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
@@ -13,4 +13,4 @@ usb_always_on=Disable
@@ -15,4 +15,4 @@ usb_always_on=Disable
fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
index 62715bc6ba..129b5fd121 100644
index d61046df6b..8c793fd1c3 100644
--- a/src/mainboard/protectli/vault_cml/cmos.default
+++ b/src/mainboard/protectli/vault_cml/cmos.default
@@ -1,3 +1,3 @@
@@ -2,4 +2,4 @@
boot_option=Fallback
debug_level=Debug
-me_state=Enable
+me_state=Disabled
diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
index 62715bc6ba..129b5fd121 100644
index d61046df6b..8c793fd1c3 100644
--- a/src/mainboard/system76/tgl-u/cmos.default
+++ b/src/mainboard/system76/tgl-u/cmos.default
@@ -1,3 +1,3 @@
@@ -2,4 +2,4 @@
boot_option=Fallback
debug_level=Debug
-me_state=Enable
+me_state=Disabled
--
2.39.2
2.47.3
@@ -1,23 +0,0 @@
From 2eae87815675aebd472b6042777fe51279be4550 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:10:33 +0100
Subject: [PATCH 05/30] lenovo/t400: set VRAM to 256MiB VRAM by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/t400/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
index a326e315b1..b907a3e2df 100644
--- a/src/mainboard/lenovo/t400/cmos.default
+++ b/src/mainboard/lenovo/t400/cmos.default
@@ -13,4 +13,4 @@ power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
hybrid_graphics_mode=Integrated Only
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.2
@@ -1,7 +1,7 @@
From 158b79e6057e071d039619f617c112d31fb13f64 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
From a3bc9753261ebd534df6c6752169b3edbb588a97 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
Subject: [PATCH 15/30] util/ifdtool: add --nuke flag (all 0xFF on region)
Subject: [PATCH 05/41] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
@@ -16,22 +16,22 @@ Rebased since the last revision update in lbmk.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
1 file changed, 81 insertions(+), 31 deletions(-)
util/ifdtool/ifdtool.c | 116 +++++++++++++++++++++++++++++------------
1 file changed, 84 insertions(+), 32 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 191b3216de..38132b4a28 100644
index 75238c73b2..ea8dfc788d 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
@@ -2240,6 +2240,7 @@ static void print_usage(const char *name)
" tgl - Tiger Lake\n"
" wbg - Wellsburg\n"
" -S | --setpchstrap Write a PCH strap\n"
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
" -T | --topswapsize Set the Top Swap Block Size PCH strap value\n"
" Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n"
@@ -2251,6 +2252,60 @@ static void print_usage(const char *name)
"\n");
}
@@ -92,23 +92,23 @@ index 191b3216de..38132b4a28 100644
int main(int argc, char *argv[])
{
int opt, option_index = 0;
@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
@@ -2258,6 +2313,7 @@ int main(int argc, char *argv[])
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
+ int mode_nuke = 0;
int mode_gpr0_disable = 0;
char *region_type_string = NULL, *region_fname = NULL;
const char *layout_fname = NULL;
@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
{"validate", 0, NULL, 't'},
int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
int mode_settopswapsize = 0;
char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL;
@@ -2294,6 +2350,7 @@ int main(int argc, char *argv[])
{"setpchstrap", 1, NULL, 'S'},
{"newvalue", 1, NULL, 'V'},
{"topswapsize", 1, NULL, 'T'},
+ {"nuke", 1, NULL, 'N'},
{0, 0, 0, 0}
};
@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
@@ -2343,35 +2400,8 @@ int main(int argc, char *argv[])
region_fname++;
// Descriptor, BIOS, ME, GbE, Platform
// valid type?
@@ -141,15 +141,16 @@ index 191b3216de..38132b4a28 100644
- else if (!strcasecmp("PTT", region_type_string))
- region_type = 15;
- if (region_type == -1) {
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
fprintf(stderr, "No such region type: '%s'\n\n",
region_type_string);
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
case 't':
mode_validate = 1;
@@ -2552,7 +2582,23 @@ int main(int argc, char *argv[])
mode_settopswapsize = 1;
top_swap_size_arg = optarg;
break;
- case 'v':
+ case 'N':
+ region_type_string = strdup(optarg);
+ if (!region_type_string) {
@@ -166,38 +167,41 @@ index 191b3216de..38132b4a28 100644
+ }
+ mode_nuke = 1;
+ break;
case 'v':
+ Case 'v':
print_version();
exit(EXIT_SUCCESS);
@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
break;
@@ -2571,7 +2617,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 |
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
- mode_gpr0_disable) > 1) {
+ mode_gpr0_disable + mode_nuke) > 1) {
- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
+ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
+ mode_nuke) > 1) {
fprintf(stderr, "You may not specify more than one mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
@@ -2580,7 +2627,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 +
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
- mode_validate + mode_gpr0_disable) == 0) {
+ mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
+ mode_nuke) == 0) {
fprintf(stderr, "You need to specify a mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
@@ -2746,6 +2794,10 @@ int main(int argc, char *argv[])
write_image(new_filename, image, size);
}
+ if (mode_nuke) {
+ nuke(new_filename, image, size, region_type);
+ }
+ if (mode_nuke) {
+ nuke(new_filename, image, size, region_type);
+ }
+
if (mode_altmedisable) {
struct fpsba *fpsba = find_fpsba(image, size);
struct fmsba *fmsba = find_fmsba(image, size);
--
2.39.2
2.47.3
@@ -1,23 +0,0 @@
From f6b4913a5eca619b745d5ccea9af022a54fb185b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:11:59 +0100
Subject: [PATCH 06/30] lenovo/x200: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/x200/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
index bb4323836e..458b3f19c5 100644
--- a/src/mainboard/lenovo/x200/cmos.default
+++ b/src/mainboard/lenovo/x200/cmos.default
@@ -12,4 +12,4 @@ sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.2
@@ -1,20 +1,20 @@
From 2b899f40ce5d728faa7c1da23c3348435b7ac9cb Mon Sep 17 00:00:00 2001
From c3f93c58ddeb1e44daf76db9d67e33bcd2c54a62 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
Subject: [PATCH 18/30] mb/dell/e6400: Enable 01.0 device in devicetree for
Subject: [PATCH 06/41] mb/dell/e6400: Enable 01.0 device in devicetree for
dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6400/devicetree.cb | 2 +-
src/mainboard/dell/gm45_latitude/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
index bb954cbd7b..e9f3915d17 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
+++ b/src/mainboard/dell/e6400/devicetree.cb
@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
diff --git a/src/mainboard/dell/gm45_latitude/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
index 5919803be2..76dae87153 100644
--- a/src/mainboard/dell/gm45_latitude/devicetree.cb
+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
@@ -18,7 +18,7 @@ chip northbridge/intel/gm45
ops gm45_pci_domain_ops
device pci 00.0 on end # host bridge
@@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644
device pci 02.1 on end # Display
device pci 03.0 on end # ME
--
2.39.2
2.47.3
@@ -1,7 +1,7 @@
From 2ccd3e71730004c3ffbed178087cb778c170079e Mon Sep 17 00:00:00 2001
From 9c0234bac4d37670da6831e3ff9545a0c6119237 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 19/30] Remove warning for coreboot images built without a
Subject: [PATCH 07/41] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
@@ -13,10 +13,10 @@ up. This has caused confusion and concern so just patch it out.
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
index a2336aa876..4f1692a873 100644
index 5f988dac1b..516133880f 100644
--- a/payloads/Makefile.mk
+++ b/payloads/Makefile.mk
@@ -49,16 +49,5 @@ distclean-payloads:
@@ -50,16 +50,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
@@ -35,5 +35,5 @@ index a2336aa876..4f1692a873 100644
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
2.39.2
2.47.3
@@ -1,23 +0,0 @@
From a3a0969075163be413f968b03671aa5d8662672a Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:18:26 +0100
Subject: [PATCH 07/30] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
index 8372032119..bedad54d2a 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
-gfx_uma_size=64M
+gfx_uma_size=256M
--
2.39.2
@@ -1,7 +1,7 @@
From 70262a5f4bf801814d68f8778ea89b5cd8ef8f9a Mon Sep 17 00:00:00 2001
From 495eab54f7c2224a0ad3da3dc79905182eca6eee Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Thu, 22 Jun 2023 16:44:27 +0300
Subject: [PATCH 21/30] HACK: Disable coreboot related BL31 features
Subject: [PATCH 08/41] HACK: Disable coreboot related BL31 features
I don't know why, but removing this BL31 make argument lets gru-kevin
power off properly when shut down from Linux. Needs investigation.
@@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation.
1 file changed, 3 deletions(-)
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
index 538d254ace..18e451d63c 100644
index 279d31fb47..3d436179fe 100644
--- a/src/arch/arm64/Makefile.mk
+++ b/src/arch/arm64/Makefile.mk
@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
@@ -162,9 +162,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
# Always enable crash reporting, even on a release build
BL31_MAKEARGS += CRASH_REPORTING=1
@@ -24,5 +24,5 @@ index 538d254ace..18e451d63c 100644
BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
--
2.39.2
2.47.3
@@ -1,23 +0,0 @@
From 223ac17617b3a0c08925abbbe42d0d003e144a28 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:21:39 +0100
Subject: [PATCH 08/30] acer/g43t-am3: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/acer/g43t-am3/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
index 706f5dd551..e8b45ea22c 100644
--- a/src/mainboard/acer/g43t-am3/cmos.default
+++ b/src/mainboard/acer/g43t-am3/cmos.default
@@ -3,4 +3,4 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=64M
+gfx_uma_size=256M
--
2.39.2
@@ -1,7 +1,7 @@
From a9ab864aee1be7a03926443ddc94e4c5012719ba Mon Sep 17 00:00:00 2001
From bf464f17367c0dfa7f2c667d699800f3c6e60040 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 11:41:41 +0000
Subject: [PATCH 24/30] dell/e6430: use ME Soft Temporary Disable
Subject: [PATCH 09/41] dell/e6430: use ME Soft Temporary Disable
i overlooked this. it's set on other boards.
@@ -12,13 +12,13 @@ disablement, to absolutely ensure Intel ME is not alive
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6430/cmos.default | 2 +-
src/mainboard/dell/snb_ivb_latitude/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default
index 2a5b30f2b7..279415dfd1 100644
--- a/src/mainboard/dell/e6430/cmos.default
+++ b/src/mainboard/dell/e6430/cmos.default
--- a/src/mainboard/dell/snb_ivb_latitude/cmos.default
+++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default
@@ -6,4 +6,4 @@ bluetooth=Enable
wwan=Enable
wlan=Enable
@@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644
-me_state=Normal
+me_state=Disabled
--
2.39.2
2.47.3
@@ -1,22 +0,0 @@
From 318a97c284f8d5030100476a32516ddc9e51603d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 20 Dec 2021 01:29:31 +0000
Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
default
---
src/mainboard/lenovo/x230/cmos.default | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 7314066c2b..2e315d4521 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
me_state=Normal
+gfx_uma_size=224M
--
2.39.2
@@ -1,7 +1,7 @@
From 4e0b62e6f0977cf922b1947955538ddca63bb954 Mon Sep 17 00:00:00 2001
From 5c27543224963e7fa17ad18dea27d186685e9f13 Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Sat, 23 Dec 2023 19:02:10 +0200
Subject: [PATCH 30/30] mb/hp: Add Compaq Elite 8300 CMT port
Subject: [PATCH 10/41] mb/hp: Add Compaq Elite 8300 CMT port
Based on autoport and Z220 SuperIO code.
@@ -32,7 +32,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
---
.../hp/compaq_elite_8300_cmt/Kconfig | 39 ++++
.../hp/compaq_elite_8300_cmt/Kconfig.name | 2 +
.../hp/compaq_elite_8300_cmt/Makefile.inc | 7 +
.../hp/compaq_elite_8300_cmt/Makefile.mk | 7 +
.../hp/compaq_elite_8300_cmt/acpi/ec.asl | 1 +
.../compaq_elite_8300_cmt/acpi/platform.asl | 10 +
.../hp/compaq_elite_8300_cmt/acpi/superio.asl | 29 +++
@@ -41,17 +41,17 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
.../hp/compaq_elite_8300_cmt/cmos.default | 7 +
.../hp/compaq_elite_8300_cmt/cmos.layout | 74 +++++++
.../hp/compaq_elite_8300_cmt/data.vbt | Bin 0 -> 3902 bytes
.../hp/compaq_elite_8300_cmt/devicetree.cb | 161 +++++++++++++++
.../hp/compaq_elite_8300_cmt/devicetree.cb | 177 ++++++++++++++++
.../hp/compaq_elite_8300_cmt/dsdt.asl | 26 +++
.../hp/compaq_elite_8300_cmt/early_init.c | 31 +++
.../hp/compaq_elite_8300_cmt/early_init.c | 14 ++
.../compaq_elite_8300_cmt/gma-mainboard.ads | 17 ++
src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++
.../hp/compaq_elite_8300_cmt/hda_verb.c | 33 +++
.../hp/compaq_elite_8300_cmt/mainboard.c | 16 ++
18 files changed, 661 insertions(+)
18 files changed, 660 insertions(+)
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
@@ -121,11 +121,11 @@ index 0000000000..bd399b1e76
@@ -0,0 +1,2 @@
+config BOARD_HP_COMPAQ_ELITE_8300_CMT
+ bool "Compaq Elite 8300 CMT"
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
new file mode 100644
index 0000000000..fb492d3583
--- /dev/null
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
@@ -353,10 +353,10 @@ HcmV?d00001
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
new file mode 100644
index 0000000000..f4efabd792
index 0000000000..3d21739b72
--- /dev/null
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
@@ -0,0 +1,161 @@
@@ -0,0 +1,177 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/sandybridge
@@ -386,6 +386,22 @@ index 0000000000..f4efabd792
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+ register "usb_port_config" = "{
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 }
+ }"
+
+ device ref xhci on end # USB 3.0 Controller
+ device ref mei1 off end # Management Engine Interface 1
@@ -405,7 +421,7 @@ index 0000000000..f4efabd792
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 on end
+ device ref pcie_rp5 on end
+ device ref pcie_rp5 on end
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 on end
+ device ref pcie_rp8 on end
+
@@ -552,10 +568,10 @@ index 0000000000..e8e2b3a3e5
+}
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
new file mode 100644
index 0000000000..99b7891c70
index 0000000000..8d10c6317c
--- /dev/null
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
@@ -0,0 +1,31 @@
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
@@ -565,23 +581,6 @@ index 0000000000..99b7891c70
+
+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 0, 0 },
+ { 1, 0, 0 },
+ { 1, 0, 1 },
+ { 1, 0, 1 },
+ { 1, 0, 2 },
+ { 1, 0, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 0, 4 },
+ { 1, 0, 4 },
+ { 1, 0, 6 },
+ { 1, 0, 5 },
+ { 1, 0, 5 },
+ { 1, 0, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ if (CONFIG(CONSOLE_SERIAL))
@@ -869,5 +868,5 @@ index 0000000000..8dbd95ef96
+ .enable_dev = mainboard_enable,
+};
--
2.39.2
2.47.3
@@ -0,0 +1,292 @@
From 062b28da685d1c9f7cbe8333e98257a83ce4ca82 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 2 Mar 2024 22:51:09 +0000
Subject: [PATCH 11/41] nb/intel/haswell: make IOMMU a runtime option
When I tested graphics cards on a coreboot port for Dell
OptiPlex 9020 SFF, I could not use a graphics card unless
I set iommu=off on the Linux cmdline.
Coreboot's current behaviour is to check whether the CPU
has vt-d support and, if it does, initialise the IOMMU.
This patch maintains the current behaviour by default, but
allows the user to turn *off* the IOMMU, even if vt-d is
supported by the host CPU.
If iommu=Disable is specified, the check will not be
performed, and the IOMMU will be left disabled. This option
has been added to all current Haswell boards, though it is
recommended to leave the IOMMU turned on in most setups.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/asrock/b85m_pro4/cmos.default | 1 +
src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++
src/mainboard/asrock/h81m-hds/cmos.default | 1 +
src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++
src/mainboard/dell/optiplex_9020/cmos.default | 1 +
src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++
src/mainboard/google/beltino/cmos.layout | 5 +++++
src/mainboard/google/slippy/cmos.layout | 5 +++++
src/mainboard/intel/baskingridge/cmos.layout | 4 ++++
src/mainboard/lenovo/haswell/cmos.default | 1 +
src/mainboard/lenovo/haswell/cmos.layout | 3 +++
src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++
src/northbridge/intel/haswell/early_init.c | 5 +++++
14 files changed, 48 insertions(+)
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default
index 01bf20ad16..dfc8b80fb0 100644
--- a/src/mainboard/asrock/b85m_pro4/cmos.default
+++ b/src/mainboard/asrock/b85m_pro4/cmos.default
@@ -4,3 +4,4 @@ boot_option=Fallback
debug_level=Debug
nmi=Enable
power_on_after_fail=Disable
+iommu=Enable
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout
index efdc333fc2..c9883ea71d 100644
--- a/src/mainboard/asrock/b85m_pro4/cmos.layout
+++ b/src/mainboard/asrock/b85m_pro4/cmos.layout
@@ -11,6 +11,7 @@
395 4 e 4 debug_level
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
+ 412 1 e 6 iommu
984 16 h 0 check_sum
# -----------------------------------------------------------------
@@ -38,6 +39,8 @@
5 0 Disable
5 1 Enable
5 2 Keep
+ 6 0 Disable
+ 6 1 Enable
# -----------------------------------------------------------------
# -----------------------------------------------------------------
diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default
index 01bf20ad16..dfc8b80fb0 100644
--- a/src/mainboard/asrock/h81m-hds/cmos.default
+++ b/src/mainboard/asrock/h81m-hds/cmos.default
@@ -4,3 +4,4 @@ boot_option=Fallback
debug_level=Debug
nmi=Enable
power_on_after_fail=Disable
+iommu=Enable
diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout
index c9ba76c78f..95ee3d36fb 100644
--- a/src/mainboard/asrock/h81m-hds/cmos.layout
+++ b/src/mainboard/asrock/h81m-hds/cmos.layout
@@ -21,6 +21,9 @@ entries
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
+# enable or disable iommu
+412 1 e 6 iommu
+
# coreboot config options: check sums
984 16 h 0 check_sum
@@ -52,6 +55,9 @@ enumerations
5 1 Enable
5 2 Keep
+6 0 Disable
+6 1 Enable
+
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
index 6c4a2a1be7..8000eea8c0 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
@@ -4,3 +4,4 @@ debug_level=Debug
nmi=Disable
power_on_after_fail=Disable
fan_full_speed=Disable
+iommu=Enable
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
index d10ad95b23..4a1496a878 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
@@ -21,6 +21,9 @@ entries
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
+# turn iommu on or off
+411 1 e 6 iommu
+
# coreboot config options: EC
412 1 e 1 fan_full_speed
@@ -55,6 +58,9 @@ enumerations
5 1 Enable
5 2 Keep
+6 0 Disable
+6 1 Enable
+
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout
index 78d44c1415..c143979ae1 100644
--- a/src/mainboard/google/beltino/cmos.layout
+++ b/src/mainboard/google/beltino/cmos.layout
@@ -19,6 +19,9 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+# enable or disable iommu
+412 1 e 8 iommu
+
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
@@ -47,6 +50,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 Disable
+8 1 Enable
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout
index 78d44c1415..c143979ae1 100644
--- a/src/mainboard/google/slippy/cmos.layout
+++ b/src/mainboard/google/slippy/cmos.layout
@@ -19,6 +19,9 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+# enable or disable iommu
+412 1 e 8 iommu
+
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
@@ -47,6 +50,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 Disable
+8 1 Enable
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout
index 78d44c1415..f2c602f541 100644
--- a/src/mainboard/intel/baskingridge/cmos.layout
+++ b/src/mainboard/intel/baskingridge/cmos.layout
@@ -19,6 +19,8 @@ entries
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
+412 1 e 8 iommu
+
# coreboot config options: bootloader
#Used by ChromeOS:
416 128 r 0 vbnv
@@ -47,6 +49,8 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 Disable
+8 1 Enable
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default
index 08db97c5a9..cc6b363cd9 100644
--- a/src/mainboard/lenovo/haswell/cmos.default
+++ b/src/mainboard/lenovo/haswell/cmos.default
@@ -14,3 +14,4 @@ trackpoint=Enable
backlight=Keyboard
enable_dual_graphics=Disable
usb_always_on=Disable
+iommu=Enable
diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout
index 27915d3ab7..59df76b64c 100644
--- a/src/mainboard/lenovo/haswell/cmos.layout
+++ b/src/mainboard/lenovo/haswell/cmos.layout
@@ -23,6 +23,7 @@ entries
# coreboot config options: EC
411 1 e 8 first_battery
+413 1 e 14 iommu
415 1 e 1 wlan
416 1 e 1 trackpoint
417 1 e 1 fn_ctrl_swap
@@ -72,6 +73,8 @@ enumerations
13 0 Disable
13 1 AC and battery
13 2 AC only
+14 0 Disable
+14 1 Enable
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default
index 7ce38fb5d7..6049e7938a 100644
--- a/src/mainboard/supermicro/x10slm-f/cmos.default
+++ b/src/mainboard/supermicro/x10slm-f/cmos.default
@@ -5,3 +5,4 @@ debug_level=Debug
nmi=Enable
power_on_after_fail=Keep
hide_ast2400=Disable
+iommu=Enable
diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout
index 38ba87aa45..24d39e97ee 100644
--- a/src/mainboard/supermicro/x10slm-f/cmos.layout
+++ b/src/mainboard/supermicro/x10slm-f/cmos.layout
@@ -21,6 +21,9 @@ entries
408 1 e 1 nmi
409 2 e 5 power_on_after_fail
+# enable or disable iommu
+412 1 e 6 iommu
+
# coreboot config options: mainboard
416 1 e 1 hide_ast2400
@@ -55,6 +58,9 @@ enumerations
5 1 Enable
5 2 Keep
+6 0 Disable
+6 1 Enable
+
# -----------------------------------------------------------------
checksums
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index e47deb5da6..1a7e0b1076 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -5,6 +5,7 @@
#include <device/mmio.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
+#include <option.h>
#include "haswell.h"
@@ -157,6 +158,10 @@ static void haswell_setup_misc(void)
static void haswell_setup_iommu(void)
{
const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
+ u8 enable_iommu = get_uint_option("iommu", 1);
+
+ if (!enable_iommu)
+ return;
if (capid0_a & VTD_DISABLE)
return;
--
2.47.3
@@ -0,0 +1,29 @@
From 5bd5bc755af744b51e0577970dc6f5214bd0cfee Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 2 Mar 2024 23:00:09 +0000
Subject: [PATCH 12/41] dell/optiplex_9020: Disable IOMMU by default
Needed to make graphics cards work. Turning it on is
recommended if only using iGPU, otherwise leave it off
by default. The IOMMU is extremely buggy when a graphics
card is used. Leaving it off by default will ensure that
the default ROM images in Libreboot will work on any setup.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/dell/optiplex_9020/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
index 8000eea8c0..0700f971ee 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
@@ -4,4 +4,4 @@ debug_level=Debug
nmi=Disable
power_on_after_fail=Disable
fan_full_speed=Disable
-iommu=Enable
+iommu=Disable
--
2.47.3
@@ -1,198 +0,0 @@
From 7b9003f98c7c685b2fe56781f3b0916018037b72 Mon Sep 17 00:00:00 2001
From: Alexander Couzens <lynxis@fe80.eu>
Date: Sat, 19 Mar 2022 13:42:33 +0000
Subject: [PATCH 13/30] lenovo/x230: introduce FHD variant
There is a modification for the x230 which uses the 2nd DP from the dock
as the integrated panel's connection, which allows using a custom eDP
panel instead of the stock LVDS display.
There are several adapter boards present on the market and all of them
uses the same method of enabling the custom eDP panel.
To make this work with coreboot, the internal LVDS connector should be
disabled in libgfxinit. The VBT has been modified as well, which allows
brightness controls to work out of the box.
The modifications done to the VBT are:
- Remove the LVDS port entry.
- Move the DP-3 (which is the 2nd DP on the dock) entry to the first
position on the list.
- Set the DP-3 as internally connected.
This has been reported to work with the following panels:
- LP125WF2-SPB4 (1920*1080, 12.5")
- LQ125T1JW02 (2560*1440, 12.5")
- LQ133M1JW21 (1920*1080, 13.3")
- LTN133HL10-201 (1920*1080, 13.3")
- B133HAN04.6 (1920*1080, 13.3")
- B133QAN02.0 (2560*1600, 13.3")
Other eDP panels not on this list should work as well.
Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
---
src/mainboard/lenovo/x230/Kconfig | 15 ++++++++-----
src/mainboard/lenovo/x230/Kconfig.name | 3 +++
src/mainboard/lenovo/x230/Makefile.mk | 5 +++++
.../lenovo/x230/variants/x230_edp/data.vbt | Bin 0 -> 4281 bytes
.../x230/variants/x230_edp/gma-mainboard.ads | 21 ++++++++++++++++++
5 files changed, 38 insertions(+), 6 deletions(-)
create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
index 279095629b..acfd0ed561 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S
+if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
select H8_HAS_BAT_THRESHOLDS_IMPL
select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S
select NO_UART_ON_SUPERIO
- select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+ select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15
select DRIVERS_RICOH_RCE822
select MEMORY_MAPPED_TPM
- select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+ select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
select MAINBOARD_HAS_LIBGFXINIT
select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
select INTEL_GMA_HAVE_VBT
@@ -47,17 +47,20 @@ config MAINBOARD_DIR
default "lenovo/x230"
config VARIANT_DIR
- default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+ default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
default "x230s" if BOARD_LENOVO_X230S
config MAINBOARD_PART_NUMBER
- default "ThinkPad X230" if BOARD_LENOVO_X230
+ default "ThinkPad X230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230_EDP
default "ThinkPad X230t" if BOARD_LENOVO_X230T
default "ThinkPad X230s" if BOARD_LENOVO_X230S
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+config INTEL_GMA_VBT_FILE
+ default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
+
config USBDEBUG_HCD_INDEX
int
default 2
@@ -79,4 +82,4 @@ config PS2M_EISAID
config THINKPADEC_HKEY_EISAID
default "LEN0068"
-endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S
+endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name
index 1a01436879..e7290a12dd 100644
--- a/src/mainboard/lenovo/x230/Kconfig.name
+++ b/src/mainboard/lenovo/x230/Kconfig.name
@@ -6,3 +6,6 @@ config BOARD_LENOVO_X230T
config BOARD_LENOVO_X230S
bool "ThinkPad X230s"
+
+config BOARD_LENOVO_X230_EDP
+ bool "ThinkPad X230 eDP Mod (2K/FHD)"
diff --git a/src/mainboard/lenovo/x230/Makefile.mk b/src/mainboard/lenovo/x230/Makefile.mk
index 8e801f145d..6e6f9f90b9 100644
--- a/src/mainboard/lenovo/x230/Makefile.mk
+++ b/src/mainboard/lenovo/x230/Makefile.mk
@@ -5,4 +5,9 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/early_init.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+
+ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y)
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads
+else
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+endif
diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt b/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
GIT binary patch
literal 4281
zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^
zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT
zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}(
z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg
zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW>
zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn
zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L
zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy;
z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY
zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH
z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
literal 0
HcmV?d00001
diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
new file mode 100644
index 0000000000..f7cf0bc264
--- /dev/null
+++ b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
@@ -0,0 +1,21 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
--
2.39.2
@@ -0,0 +1,51 @@
From 78da1e003a69a4cc6bd5e71e4bc43a4844d05f16 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 6 Apr 2024 01:22:47 +0100
Subject: [PATCH 13/41] nb/haswell: Fully disable iGPU when dGPU is used
My earlier patch disabled decode *and* disabled the iGPU itself, but
a subsequent revision disabled only VGA decode. Upon revisiting, I
found that, actually, yes, you also need to disable the iGPU entirely.
Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU.
With this patch, the iGPU is completely disabled when you install a
graphics card, but the iGPU is available to use when no graphics card
is present.
For more context, see:
Author: Leah Rowe <info@minifree.org>
Date: Fri Feb 23 13:33:31 2024 +0000
nb/haswell: Disable iGPU when dGPU is used
And look at the Gerrit comments:
https://review.coreboot.org/c/coreboot/+/80717/
So, my original submission on change 80717 was actually correct.
This patch fixes the issue. I tested on iGPU and dGPU, with both
broadwell and haswell mrc.bin.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/northbridge/intel/haswell/gma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index f7fad3183d..1b188e92e1 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -466,6 +466,9 @@ static void gma_func0_disable(struct device *dev)
{
/* Disable VGA decode */
pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
+
+ /* Required or else the graphics card doesn't work */
+ dev->enabled = 0;
}
static struct device_operations gma_func0_ops = {
--
2.47.3
@@ -0,0 +1,147 @@
From 0a982ec4b606b6c236f71478350b69f532f30719 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 11:03:32 -0600
Subject: [PATCH 14/41] ec/dell/mec5035: Add S3 suspend SMI handler
This is necessary for S3 resume to work on SNB and newer Dell Latitude
laptops. If a command isn't sent, the EC cuts power to the DIMMs,
preventing the system from resuming. These commands were found using an
FPGA to log all LPC bus transactions between the host and the EC and
then narrowing down which ones were actually necessary.
Interestingly, the command IDs appear to be identical to those in
ec/google/wilco, the EC used on Dell Latitude Chromebooks, and that EC
implements a similar S3 SMI handler as the one implemented in this
commit. The Wilco EC Kconfig does suggest that its firmware is a
modified version of Dell's usual Latitude EC firmware, so the
similarities seem to be intentional.
These similarities also identified a command to enable or disable wake
sources like the power button and lid switch, and this was added to the
SMI handler to disable lid wake as the system does not yet resume
properly from a like wake with coreboot.
Tested on the Latitude E6430 (Ivy Bridge) and the Precision M6800
(Haswell, not yet pushed).
Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/Makefile.mk | 1 +
src/ec/dell/mec5035/mec5035.c | 13 +++++++++++++
src/ec/dell/mec5035/mec5035.h | 22 ++++++++++++++++++++++
src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++
4 files changed, 53 insertions(+)
create mode 100644 src/ec/dell/mec5035/smihandler.c
diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk
index 4ebdd811f9..be557e4599 100644
--- a/src/ec/dell/mec5035/Makefile.mk
+++ b/src/ec/dell/mec5035/Makefile.mk
@@ -5,5 +5,6 @@ ifeq ($(CONFIG_EC_DELL_MEC5035),y)
bootblock-y += mec5035.c
romstage-y += mec5035.c
ramstage-y += mec5035.c
+smm-y += mec5035.c smihandler.c
endif
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index 17ac2c1dab..c5067c16f6 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -100,6 +100,19 @@ static void mec5035_power_button_route(enum ec_power_button_route target)
write_mailbox_regs(&buf, 2, 1);
ec_command(CMD_POWER_BUTTON_TO_HOST);
}
+void mec5035_change_wake(u8 source, enum ec_wake_change change)
+{
+ u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
+ write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS);
+ ec_command(CMD_ACPI_WAKEUP_CHANGE);
+}
+
+void mec5035_sleep_enable(void)
+{
+ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
+ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
+ ec_command(CMD_SLEEP_ENABLE);
+}
void mec5035_early_init(void)
{
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index 5fdf56631b..5cd907bf71 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -4,6 +4,7 @@
#define _EC_DELL_MEC5035_H_
#include <stdint.h>
+#include <types.h>
#define NUM_REGISTERS 32
@@ -11,6 +12,8 @@ enum mec5035_cmd {
CMD_MOUSE_TP = 0x1a,
CMD_RADIO_CTRL = 0x2b,
CMD_POWER_BUTTON_TO_HOST = 0x3e,
+ CMD_ACPI_WAKEUP_CHANGE = 0x4a,
+ CMD_SLEEP_ENABLE = 0x64,
CMD_CPU_OK = 0xc2,
};
@@ -39,9 +42,28 @@ enum ec_power_button_route {
HOST
};
+#define ACPI_WAKEUP_NUM_ARGS 4
+enum ec_wake_change {
+ WAKE_OFF = 0,
+ WAKE_ON
+};
+
+/* Copied from ec/google/wilco/commands.h. Not sure if these all apply */
+enum ec_acpi_wake_events {
+ EC_ACPI_WAKE_PWRB = BIT(0), /* Wake up by power button */
+ EC_ACPI_WAKE_LID = BIT(1), /* Wake up by lid switch */
+ EC_ACPI_WAKE_RTC = BIT(5), /* Wake up by RTC */
+};
+
+#define SLEEP_EN_NUM_ARGS 2
+
u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
void mec5035_cpu_ok(void);
void mec5035_early_init(void);
void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
+void mec5035_change_wake(u8 source, enum ec_wake_change change);
+void mec5035_sleep_enable(void);
+
+void mec5035_smi_sleep(int slp_type);
#endif /* _EC_DELL_MEC5035_H_ */
diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c
new file mode 100644
index 0000000000..958733bf97
--- /dev/null
+++ b/src/ec/dell/mec5035/smihandler.c
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <console/console.h>
+#include <ec/acpi/ec.h>
+#include "mec5035.h"
+
+void mec5035_smi_sleep(int slp_type)
+{
+ switch (slp_type) {
+ case ACPI_S3:
+ /* System does not yet resume properly if woken by lid */
+ mec5035_change_wake(EC_ACPI_WAKE_LID, WAKE_OFF);
+ mec5035_sleep_enable();
+ break;
+ }
+}
--
2.47.3
@@ -1,25 +0,0 @@
From 9959fe252cceca7005b63e3313f7f95114f1f93c Mon Sep 17 00:00:00 2001
From: Alexei Sorokin <sor.alexei@meowr.ru>
Date: Sun, 27 Nov 2022 18:36:26 +0300
Subject: [PATCH 14/30] lenovo/x230: fix the data.vbt path for the EDP variant
---
src/mainboard/lenovo/x230/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
index acfd0ed561..34108c3c04 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -59,7 +59,7 @@ config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config INTEL_GMA_VBT_FILE
- default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
+ default "src/mainboard/\$(MAINBOARDDIR)/variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
config USBDEBUG_HCD_INDEX
int
--
2.39.2
@@ -0,0 +1,55 @@
From 9ca5c919339049518e842980041f528d48d79124 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Sat, 4 May 2024 02:00:53 +0100
Subject: [PATCH 15/41] nb/haswell: lock policy regs when disabling IOMMU
Angel Pons told me I should do it. See comments here:
https://review.coreboot.org/c/coreboot/+/81016
I see no harm in complying with the request. I'll merge
this into the main patch at a later date and try to
get this upstreamed.
Just a reminder: on Optiplex 9020 variants, Xorg locks up
under Linux when tested with a graphics card; disabling
IOMMU works around the issue. Intel graphics work just fine
with IOMMU turned on. Libreboot disables IOMMU by default,
on the 9020, so that users can install graphics cards easily.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/northbridge/intel/haswell/early_init.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
index 1a7e0b1076..e9506ee830 100644
--- a/src/northbridge/intel/haswell/early_init.c
+++ b/src/northbridge/intel/haswell/early_init.c
@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void)
const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
u8 enable_iommu = get_uint_option("iommu", 1);
- if (!enable_iommu)
- return;
-
if (capid0_a & VTD_DISABLE)
return;
- /* Setup BARs: zeroize top 32 bits; set enable bit */
- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
+ if (enable_iommu) {
+ /* Setup BARs: zeroize top 32 bits; set enable bit */
+ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
+ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
+ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
+ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
+ }
/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
u32 reg32;
--
2.47.3
@@ -1,47 +0,0 @@
From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
Enabling PECI without microcode updates loaded causes the CPUID feature set
to become corrupted. And one consequence is broken SpeedStep. At least, that's
my understanding looking at Intel Errata. This revert is not a fix, because
upstream is correct (upstream assumes microcode updates). We will simply
maintain this revert patch in Libreboot, from now on.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 315e7c36fc..1423fd72bc 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
}
-#define IA32_PECI_CTL 0x5a0
-
static void configure_misc(const int eist, const int tm2, const int emttm)
{
msr_t msr;
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
}
-
- /* Enable PECI
- WARNING: due to Erratum AW67 described in Intel document #318733
- the microcode must be updated before this MSR is written to. */
- msr = rdmsr(IA32_PECI_CTL);
- msr.lo |= 1;
- wrmsr(IA32_PECI_CTL, msr);
}
#define PIC_SENS_CFG 0x1aa
--
2.39.2
@@ -1,7 +1,7 @@
From f26df5dff7be4b0c9d8dced1cf6ed07472a174c7 Mon Sep 17 00:00:00 2001
From e74c4ee6a62ef9f91a8efb257658f627498b91fa Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 10 May 2021 22:40:59 +0200
Subject: [PATCH 8/9] nb/intel/gm45: Make DDR2 raminit work
Subject: [PATCH 16/41] nb/intel/gm45: Make DDR2 raminit work
List of changes:
- Update some timing and ODT values
@@ -20,10 +20,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
3 files changed, 106 insertions(+), 13 deletions(-)
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index d929533d92..997f8a0e5a 100644
index f68bfdee7a..b76117bc3a 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
int raminit_read_vco_index(void);
u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
@@ -31,9 +31,9 @@ index d929533d92..997f8a0e5a 100644
+void raminit_rcomp_calibration(int ddr_type, stepping_t stepping);
void raminit_reset_readwrite_pointers(void);
void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume);
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index b7e013959a..df8f46fbbc 100644
index def9e1e331..7b091cc567 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping,
@@ -70,7 +70,7 @@ index b7e013959a..df8f46fbbc 100644
}
mchbar_write32(CxODT_HIGH(ch), reg);
@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume)
raminit_write_training(timings->mem_clock, dimms, s3resume);
}
@@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
}
--
2.39.2
2.47.3
@@ -1,173 +0,0 @@
From 8a94f38398b8fa554fa4ae53ecb88a372df634fd Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
Subject: [PATCH 17/30] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
While this fix is *technically correct*, the one in
coreboot, it breaks rebooting as tested on several
GM45 ThinkPads e.g. X200, T400, when microcode
updates are not applied.
Since November 2022, Libreboot includes microcode
updates by default, but it tells users how to remove
it from the ROM (with cbfstool) if they wish.
Well, with Libreboot 20221214, 20230319 and 20230413,
mitigations present in Libreboot 20220710 (which did
not have microcode updates) do not exist.
This patch, along with the other patch to remove PECI
support (which breaks speedstep when microcode updates
are not applied) have now been re-added to Libreboot.
It is still best to use microcode updates by default.
These patches in coreboot are not critically urgent,
and you can use the machines with or without them,
regardless of ucode.
I'll probably re-write this and the other patch at
some point, applying the change conditionally upon
whether or not microcode is applied.
Pragmatism is a good thing. I recommend it.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
5 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 1423fd72bc..d1f98ca43a 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -8,6 +8,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
#define MSR_BBL_CR_CTL3 0x11e
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states(quad);
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index bc53214310..72f40f6762 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
smm_initialize();
}
-#define SMRR_SUPPORTED (1 << 11)
-
static void per_cpu_smm_trigger(void)
{
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
- set_feature_ctrl_vmx();
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
- /* We don't care if the lock is already setting
- as our smm relocation handler is able to handle
- setups where SMRR is not enabled here. */
- if (ia32_ft_ctrl.lo & (1 << 0)) {
- /* IA32_FEATURE_CONTROL locked. If we set it again we
- get an illegal instruction. */
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
- } else {
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
- printk(BIOS_INFO,
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
- }
- } else {
- set_vmx_and_lock();
- }
-
/* Relocate the SMM handler. */
smm_relocate();
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 05f5f327cc..0450c2ad83 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 5bd1c32815..f3bb08cde3 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 535fb8fae7..f7b05facd2 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
--
2.39.2
@@ -0,0 +1,240 @@
From da433a5d9a7d1d7856b55761b8392864343de5a8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Tue, 6 Aug 2024 00:50:24 +0100
Subject: [PATCH 17/41] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
We add this patch:
commit commit_id_here
Author: Angel Pons <th3fanbus@gmail.com>
Date: Mon May 10 22:40:59 2021 +0200
nb/intel/gm45: Make DDR2 raminit work
This patch was original applied, in lbmk, only on coreboot/dell,
separately from coreboot/default, which was wasteful because it
meant having an entire coreboot tree just for a single board. We
did this, because the DDR2 RCOMP fix happened to break DDR3 init
on other boards.
What *this* new patch does on top of Angel's patch, is make sure
that their changes only apply to DDR2, while DDR3 behaviour remains
unchanged. This means that the Dell Latitude E6400 can be supported
in the main coreboot tree, within lbmk.
Essentially, this patch restores the old behaviour, prior to applying
Angel's patch, only when DDR3 memory is used.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/northbridge/intel/gm45/raminit.c | 161 +++++++++---------
.../intel/gm45/raminit_rcomp_calibration.c | 9 +-
2 files changed, 88 insertions(+), 82 deletions(-)
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index 7b091cc567..478898564a 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
reg = (reg & ~(0xf << 10)) | (2 << 10);
else
reg = (reg & ~(0xf << 10)) | (3 << 10);
- reg = (reg & ~(0x7 << 5)) | (2 << 5);
+ if (spd_type == DDR2)
+ reg = (reg & ~(0x7 << 5)) | (2 << 5);
+ else
+ reg = (reg & ~(0x7 << 5)) | (3 << 5);
} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume)
raminit_write_training(timings->mem_clock, dimms, s3resume);
}
- /*
- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
- * after receiver enable calibration, otherwise raminit sometimes
- * completes with non-working memory.
- */
- mchbar_write32(0x0530, 0x06060005);
- mchbar_write32(0x0680, 0x06060606);
- mchbar_write32(0x0684, 0x08070606);
- mchbar_write32(0x0688, 0x0e0e0c0a);
- mchbar_write32(0x068c, 0x0e0e0e0e);
- mchbar_write32(0x0698, 0x06060606);
- mchbar_write32(0x069c, 0x08070606);
- mchbar_write32(0x06a0, 0x0c0c0b0a);
- mchbar_write32(0x06a4, 0x0c0c0c0c);
-
- mchbar_write32(0x06c0, 0x02020202);
- mchbar_write32(0x06c4, 0x03020202);
- mchbar_write32(0x06c8, 0x04040403);
- mchbar_write32(0x06cc, 0x04040404);
- mchbar_write32(0x06d8, 0x02020202);
- mchbar_write32(0x06dc, 0x03020202);
- mchbar_write32(0x06e0, 0x04040403);
- mchbar_write32(0x06e4, 0x04040404);
-
- mchbar_write32(0x0700, 0x02020202);
- mchbar_write32(0x0704, 0x03020202);
- mchbar_write32(0x0708, 0x04040403);
- mchbar_write32(0x070c, 0x04040404);
- mchbar_write32(0x0718, 0x02020202);
- mchbar_write32(0x071c, 0x03020202);
- mchbar_write32(0x0720, 0x04040403);
- mchbar_write32(0x0724, 0x04040404);
-
- mchbar_write32(0x0740, 0x02020202);
- mchbar_write32(0x0744, 0x03020202);
- mchbar_write32(0x0748, 0x04040403);
- mchbar_write32(0x074c, 0x04040404);
- mchbar_write32(0x0758, 0x02020202);
- mchbar_write32(0x075c, 0x03020202);
- mchbar_write32(0x0760, 0x04040403);
- mchbar_write32(0x0764, 0x04040404);
-
- mchbar_write32(0x0780, 0x06060606);
- mchbar_write32(0x0784, 0x09070606);
- mchbar_write32(0x0788, 0x0e0e0c0b);
- mchbar_write32(0x078c, 0x0e0e0e0e);
- mchbar_write32(0x0798, 0x06060606);
- mchbar_write32(0x079c, 0x09070606);
- mchbar_write32(0x07a0, 0x0d0d0c0b);
- mchbar_write32(0x07a4, 0x0d0d0d0d);
-
- mchbar_write32(0x07c0, 0x06060606);
- mchbar_write32(0x07c4, 0x09070606);
- mchbar_write32(0x07c8, 0x0e0e0c0b);
- mchbar_write32(0x07cc, 0x0e0e0e0e);
- mchbar_write32(0x07d8, 0x06060606);
- mchbar_write32(0x07dc, 0x09070606);
- mchbar_write32(0x07e0, 0x0d0d0c0b);
- mchbar_write32(0x07e4, 0x0d0d0d0d);
-
- mchbar_write32(0x0840, 0x06060606);
- mchbar_write32(0x0844, 0x08070606);
- mchbar_write32(0x0848, 0x0e0e0c0a);
- mchbar_write32(0x084c, 0x0e0e0e0e);
- mchbar_write32(0x0858, 0x06060606);
- mchbar_write32(0x085c, 0x08070606);
- mchbar_write32(0x0860, 0x0c0c0b0a);
- mchbar_write32(0x0864, 0x0c0c0c0c);
-
- mchbar_write32(0x0880, 0x02020202);
- mchbar_write32(0x0884, 0x03020202);
- mchbar_write32(0x0888, 0x04040403);
- mchbar_write32(0x088c, 0x04040404);
- mchbar_write32(0x0898, 0x02020202);
- mchbar_write32(0x089c, 0x03020202);
- mchbar_write32(0x08a0, 0x04040403);
- mchbar_write32(0x08a4, 0x04040404);
+ if (sysinfo->spd_type == DDR2) {
+ /*
+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
+ * after receiver enable calibration, otherwise raminit sometimes
+ * completes with non-working memory.
+ */
+ mchbar_write32(0x0530, 0x06060005);
+ mchbar_write32(0x0680, 0x06060606);
+ mchbar_write32(0x0684, 0x08070606);
+ mchbar_write32(0x0688, 0x0e0e0c0a);
+ mchbar_write32(0x068c, 0x0e0e0e0e);
+ mchbar_write32(0x0698, 0x06060606);
+ mchbar_write32(0x069c, 0x08070606);
+ mchbar_write32(0x06a0, 0x0c0c0b0a);
+ mchbar_write32(0x06a4, 0x0c0c0c0c);
+
+ mchbar_write32(0x06c0, 0x02020202);
+ mchbar_write32(0x06c4, 0x03020202);
+ mchbar_write32(0x06c8, 0x04040403);
+ mchbar_write32(0x06cc, 0x04040404);
+ mchbar_write32(0x06d8, 0x02020202);
+ mchbar_write32(0x06dc, 0x03020202);
+ mchbar_write32(0x06e0, 0x04040403);
+ mchbar_write32(0x06e4, 0x04040404);
+
+ mchbar_write32(0x0700, 0x02020202);
+ mchbar_write32(0x0704, 0x03020202);
+ mchbar_write32(0x0708, 0x04040403);
+ mchbar_write32(0x070c, 0x04040404);
+ mchbar_write32(0x0718, 0x02020202);
+ mchbar_write32(0x071c, 0x03020202);
+ mchbar_write32(0x0720, 0x04040403);
+ mchbar_write32(0x0724, 0x04040404);
+
+ mchbar_write32(0x0740, 0x02020202);
+ mchbar_write32(0x0744, 0x03020202);
+ mchbar_write32(0x0748, 0x04040403);
+ mchbar_write32(0x074c, 0x04040404);
+ mchbar_write32(0x0758, 0x02020202);
+ mchbar_write32(0x075c, 0x03020202);
+ mchbar_write32(0x0760, 0x04040403);
+ mchbar_write32(0x0764, 0x04040404);
+
+ mchbar_write32(0x0780, 0x06060606);
+ mchbar_write32(0x0784, 0x09070606);
+ mchbar_write32(0x0788, 0x0e0e0c0b);
+ mchbar_write32(0x078c, 0x0e0e0e0e);
+ mchbar_write32(0x0798, 0x06060606);
+ mchbar_write32(0x079c, 0x09070606);
+ mchbar_write32(0x07a0, 0x0d0d0c0b);
+ mchbar_write32(0x07a4, 0x0d0d0d0d);
+
+ mchbar_write32(0x07c0, 0x06060606);
+ mchbar_write32(0x07c4, 0x09070606);
+ mchbar_write32(0x07c8, 0x0e0e0c0b);
+ mchbar_write32(0x07cc, 0x0e0e0e0e);
+ mchbar_write32(0x07d8, 0x06060606);
+ mchbar_write32(0x07dc, 0x09070606);
+ mchbar_write32(0x07e0, 0x0d0d0c0b);
+ mchbar_write32(0x07e4, 0x0d0d0d0d);
+
+ mchbar_write32(0x0840, 0x06060606);
+ mchbar_write32(0x0844, 0x08070606);
+ mchbar_write32(0x0848, 0x0e0e0c0a);
+ mchbar_write32(0x084c, 0x0e0e0e0e);
+ mchbar_write32(0x0858, 0x06060606);
+ mchbar_write32(0x085c, 0x08070606);
+ mchbar_write32(0x0860, 0x0c0c0b0a);
+ mchbar_write32(0x0864, 0x0c0c0c0c);
+
+ mchbar_write32(0x0880, 0x02020202);
+ mchbar_write32(0x0884, 0x03020202);
+ mchbar_write32(0x0888, 0x04040403);
+ mchbar_write32(0x088c, 0x04040404);
+ mchbar_write32(0x0898, 0x02020202);
+ mchbar_write32(0x089c, 0x03020202);
+ mchbar_write32(0x08a0, 0x04040403);
+ mchbar_write32(0x08a4, 0x04040404);
+ }
igd_compute_ggc(sysinfo);
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
index b74765fd9c..5d4505e063 100644
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
reg = mchbar_read32(0x518);
lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
- if (i == 1) {
+ if ((i == 1) && (ddr_type == DDR2)) {
magic_comp[0] = (reg >> 8) & 0x3f;
magic_comp[1] = (reg >> 0) & 0x3f;
}
@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
}
mchbar += 0x0040;
}
-
- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
+ if (ddr_type == DDR2) {
+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
+ }
}
--
2.47.3
@@ -0,0 +1,51 @@
From b4443cfe4b63a49b8170bdfb6dacbc8d52110eff Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 20 May 2024 10:24:16 -0600
Subject: [PATCH 18/41] mb/dell/e6400: Use 100 MHz reference clock for display
The E6400 uses a 100 MHz reference clock for spread spectrum support on
LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
the more common 1280 x 800 display panels, the numerical error was not
large enough to cause noticable issues, but the actual pixel clock
frequency derived from a 100 MHz reference using PLL configs calculated
assuming a 96 MHz reference was not close enough for 1440 x 900 panels,
which require a much higher pixel clock. This resulted in a garbled
display in the pre-OS graphics environment provided by libgfxinit.
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/gm45_latitude/Kconfig | 2 ++
src/northbridge/intel/gm45/Kconfig | 4 ++++
2 files changed, 6 insertions(+)
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
index edc79b0d43..5020744990 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
@@ -22,6 +22,8 @@ config BOARD_DELL_E6400
select BOARD_DELL_GM45_LATITUDE_COMMON
if BOARD_DELL_GM45_LATITUDE_COMMON
+config INTEL_GMA_DPLL_REF_FREQ
+ default 100000000
config MAINBOARD_DIR
default "dell/gm45_latitude"
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index a776217475..35e89b0c88 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
if NORTHBRIDGE_INTEL_GM45
+config INTEL_GMA_DPLL_REF_FREQ
+ int
+ default 96000000
+
config VBOOT
select VBOOT_STARTS_IN_BOOTBLOCK
--
2.47.3
@@ -0,0 +1,52 @@
From d3d97fccab40cfe50eac92796bb7f16bd245b189 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Mon, 12 Aug 2024 02:15:24 +0100
Subject: [PATCH 19/41] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
set it to 96MHz. fixes the following build error when
building for x4x boards e.g. gigabyte ga-g41m-es2l:
hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config"
make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1
this error was introduced when merging coreboot/dell
into coreboot/default in lbmk. nicholas chin's fix in lbmk
was as follows:
commit 8629873a6043067affc137be275b7aa69cb1f10c
Author: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon May 20 10:46:25 2024 -0600
Fix E6400 display issue with 1440 x 900 panel
this currently corresponds to the patch in lbmk,
as of 12 august 2024:
0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
The assumption prior to Nicholas's fix was 96MHz, so set
it accordingly on x4x northbridge.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/northbridge/intel/x4x/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 6fa4551957..646af3510b 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
if NORTHBRIDGE_INTEL_X4X
+config INTEL_GMA_DPLL_REF_FREQ
+ int
+ default 96000000
+
config CBFS_SIZE
default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
--
2.47.3
@@ -1,826 +0,0 @@
From a49df0307455d6d8b7a9efb9f4639b72be1b64d4 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 19 Aug 2023 16:19:10 -0600
Subject: [PATCH 20/30] mb/dell: Add Latitude E6430 (Ivy Bridge)
Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. This
is based on the autoport output with some manual tweaks. The flash is
8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. It
can also be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
Working:
- Libgfxinit
- USB EHCI debug (left side usb port is HCD index 2, middle port on the
right side is HCD index 1)
- Keyboard
- Touchpad/trackpoint
- ExpressCard
- Audio
- Ethernet
- SD card reader
- mPCIe WiFi
- SeaBIOS 1.16.2
- edk2 (MrChromebox' fork, uefipayload_202306)
- Internal flashing using dell-flash-unlock
Not working:
- S3 suspend: Possibly EC related
- Physical wireless switch - this triggers an SMI handler in the vendor
firmware which sends commands to the EC to enable/disable wireless
devices
- Battery reporting - needs ACPI code for the EC
- Brightness hotkeys - probably EC related
Unknown/untested:
- Dock
- eSATA
- TPM
- dGPU on non-UMA model
- Bluetooth module (not included on my system)
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6430/Kconfig | 44 +++++
src/mainboard/dell/e6430/Kconfig.name | 2 +
src/mainboard/dell/e6430/Makefile.inc | 6 +
src/mainboard/dell/e6430/acpi/ec.asl | 9 +
src/mainboard/dell/e6430/acpi/platform.asl | 12 ++
src/mainboard/dell/e6430/acpi/superio.asl | 3 +
src/mainboard/dell/e6430/acpi_tables.c | 16 ++
src/mainboard/dell/e6430/board_info.txt | 6 +
src/mainboard/dell/e6430/cmos.default | 9 +
src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++
src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e6430/devicetree.cb | 70 ++++++++
src/mainboard/dell/e6430/dsdt.asl | 30 ++++
src/mainboard/dell/e6430/early_init.c | 32 ++++
src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++
src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++
src/mainboard/dell/e6430/hda_verb.c | 33 ++++
src/mainboard/dell/e6430/mainboard.c | 21 +++
18 files changed, 593 insertions(+)
create mode 100644 src/mainboard/dell/e6430/Kconfig
create mode 100644 src/mainboard/dell/e6430/Kconfig.name
create mode 100644 src/mainboard/dell/e6430/Makefile.inc
create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl
create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl
create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl
create mode 100644 src/mainboard/dell/e6430/acpi_tables.c
create mode 100644 src/mainboard/dell/e6430/board_info.txt
create mode 100644 src/mainboard/dell/e6430/cmos.default
create mode 100644 src/mainboard/dell/e6430/cmos.layout
create mode 100644 src/mainboard/dell/e6430/data.vbt
create mode 100644 src/mainboard/dell/e6430/devicetree.cb
create mode 100644 src/mainboard/dell/e6430/dsdt.asl
create mode 100644 src/mainboard/dell/e6430/early_init.c
create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e6430/gpio.c
create mode 100644 src/mainboard/dell/e6430/hda_verb.c
create mode 100644 src/mainboard/dell/e6430/mainboard.c
diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
new file mode 100644
index 0000000000..e4c799803e
--- /dev/null
+++ b/src/mainboard/dell/e6430/Kconfig
@@ -0,0 +1,44 @@
+if BOARD_DELL_LATITUDE_E6430
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e6430"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E6430"
+
+config PS2K_EISAID
+ default "PNP0303"
+
+config PS2M_EISAID
+ default "PNP0F13"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0166"
+
+endif
diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
new file mode 100644
index 0000000000..f866b03585
--- /dev/null
+++ b/src/mainboard/dell/e6430/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6430
+ bool "Latitude E6430"
diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e6430/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt
new file mode 100644
index 0000000000..4601a4aaba
--- /dev/null
+++ b/src/mainboard/dell/e6430/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
new file mode 100644
index 0000000000..2a5b30f2b7
--- /dev/null
+++ b/src/mainboard/dell/e6430/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Normal
diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e6430/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d
GIT binary patch
literal 6144
zcmeHKU2Gdw7XHRFw#VZc+nI!tq)j-qG$b@>#vu)%WW~fb!7ZV6LkJc^+qlG~(WXgp
zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;)
zjkMh#DR=zcpL5Use9xJ4?#x^=mKdcQb|t!Zj3v6R-<{Yod<{*&!ppI%xUMXT9lLMX
zn;IM)+?yEQoxF~o#5x>}{dfwPkR;RSiC=!jj_JAlRQpJWpd}$VY+XtFX9|?cO&y#m
z<SE`uGt*OdcG7S%MVsQ5GkI`wn)VeYZ#ytIou8d0Yb)J)AUAzmo)Vpuq&7;?RQ_;&
zie?W??w`vSW@&DQ`Yr3=;cjcIHNi^L`QOvN$?05SGCy0nZ&#9>IdrG<AJm@gpdQPz
zx_Yd5oSZFFa;9)-D-BLf(TLc`ERE!6^M%9tiLHiaXuwHXRU|<2BX~C?>4zSq6a*B6
zRA?%66|w}s0z*YuMNq*73a(KQQ8A>TT}4_&3_e5hDZs@lHpaYN60rOh%jBQN+*9zu
zIASsRL<3j>pYk93g@PXvaUZbpk)yEWDA4C2Ai!cNXi4M~3gjt#<|(LxR49-{<^K|T
zqL5SnLUq0r*kw>Q!0PGk>)$?LCsIS{ox_=t(Xs5!w-o>M=erl0apv_Z`-(^w_5@pz
z)}lBfx8o(*hgal&<dh}67_jhVpb;fTbFdMn7Q<$~Ll)yIMvJN<r<#~$+{1W;@r<hB
z1mh&*ZN|rpFBo4lzGDPK8tNG98Jij1j4K&Q#`TPw7&*r87<Vw{8Gm6s$astqxC3WO
zz9NE-Ek(&|>)aMG1rKzf_^2m;)RTu!i#rBrUK{pWM_5BuDg}f1vGgAMqNM&t?7(IQ
zcDa=Dn9^Q5?6k6+@y4UvvL3SDxKs*_^RS1n^H*!{fYZz^rPBX<FZ?DhF0v6`u90ic
zA-5^lMeh7u!RIful;@oGY=u>mV(=eO(Cd-pvqPqVBRYz~7nA{nO7|Kv{w^;?LXb8F
zZpK}KE=2zd4)ya^Le2qLGkt7<&s%Z6*Z`k>QW26OPC!Y8WP|wUI8Rlea-W3+oBO=P
z7W#bDD=HM*SuTlWaHmLu%9{LBg+7xrp>y^-%p_)+nfZB&dFmKmF?B(+QtAm&-^!?J
zr{Qq~n%$Y;KvfME{x@gVUB~vz&MBs@*k&z6fZ?Ic-b`*fKea1&Fkj=~!ZaqDU=O0r
zYCPKK+S_PdhGTnR+18<YSJL`a_aBz`G`HE=V`WMDYTMfPLXT~qEK3^O(Kj!<{?_~E
z{ct?ZJ!#R&H|_;QGyr;2JDTu4Urkt)#LW}e65l@e>g0GR_nHOE`gieuP-A>69j*W0
z><PPSE2YwgK714^F4A&KOda3ou4=7C($dQbCP^XH=U4QVf8#_di>h~9>kwTD6>nL4
zBSLUr+fHA!LgjQi9)hfgsV8iv!rHDd&4tY)VQn!?C&K1ZSo<JM{|K9!t~KbiT{nky
zZA_;>>gEHwc1)*Nb@P2)`%EVorfFy!3`!X0sG<GVpasKx*wBs}^oC)6VrYLeNR61y
z5$%!)?TnbWM6~@8x-Vir9?_nP(0dVcIij74P%LV0jB1@x<FeCA(YGuW>p0XopwxoS
z0g?6TPW!DC<JKR&l%Knmp5z$x;*#X7@7xT>ql9>N1GN_$T-UVr&HErC5juykd~Sxy
zq!PK|<^jJ^DuQ9)7p<sFLXlH${*3wEJ(L;FsEd;DgJ^{x0*)Wd^<xJzFfF2O*!)Bc
zXtuum#xVj7H8Tulu*qs$*N1J-3WmV*15LsWQhjX<ZR^LFq0OSkUSwZ$8NS&h7|>t`
z7FKz(x)t4R_RHf7I)6EA!d)M`R($wttvJgMee=p9zrFL_EL#DYA0wUzD?Ryj%h>lB
ztg|e-5!;@t?uT+rR=1)e9yp?8gwNW88`Zyt!8rx=+B{i(4~DY`_-WO>sGeD;nsGcs
z7h1ZN6srJX#Uke;d$JhpccQxNhw2Qz?Zw91`@8IHm-n!7{19~*_}LvecV2YZ7%!rJ
zJQk}HtK2>CvB*WQ@u9a$Eq*zF2M=FM=@c`>dwDQ;<8EgZ-}dvt6=k(8Kqfa=nDJJ{
z`Qth}G~%sFr{ZEKZb_%aySrD?sV%fJw`vFfda&ho1a>X)H^I}D_0A<|*{8kwEBU8>
qS<b6g={WLAp3+&R^8(yo-t$_!=7BX2ta)I~18W{w^T5By1OEis_@J`@
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
new file mode 100644
index 0000000000..054b01c5ac
--- /dev/null
+++ b/src/mainboard/dell/e6430/devicetree.cb
@@ -0,0 +1,70 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x0534 inherit
+
+ device ref host_bridge on end
+ device ref peg10 off end
+ device ref igd on end
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x005c0921"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end
+ device ref mei1 on end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt on end
+ device ref gbe on end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end # WWAN Slot
+ device ref pcie_rp2 on end # SLAN Slot
+ device ref pcie_rp3 on end # ExpressCard
+ device ref pcie_rp4 on end # E-Module (optical bay)
+ device ref pcie_rp5 on end # Extra Half Mini PCIe slot
+ device ref pcie_rp6 on end # SD/MMC Card Reader
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e6430/dsdt.asl b/src/mainboard/dell/e6430/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e6430/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
new file mode 100644
index 0000000000..d882c3d78b
--- /dev/null
+++ b/src/mainboard/dell/e6430/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 2, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
new file mode 100644
index 0000000000..1310830c8e
--- /dev/null
+++ b/src/mainboard/dell/e6430/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, --mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c
new file mode 100644
index 0000000000..777570765a
--- /dev/null
+++ b/src/mainboard/dell/e6430/gpio.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c
new file mode 100644
index 0000000000..56ada95c58
--- /dev/null
+++ b/src/mainboard/dell/e6430/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x10280534, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280534),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e6430/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.39.2
@@ -0,0 +1,332 @@
From c2a05f102ca378d8e23f0485d680845584efa290 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Sep 2024 19:51:25 -0600
Subject: [PATCH 20/41] mb/dell/gm45_latitudes: Add E4300 variant
Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/gm45_latitude/Kconfig | 5 +
src/mainboard/dell/gm45_latitude/Kconfig.name | 3 +
.../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes
.../variants/e4300/gma-mainboard.ads | 17 +++
.../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++
.../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++
.../variants/e4300/overridetree.cb | 10 ++
7 files changed, 210 insertions(+)
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
index 5020744990..d27d5728a8 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
config BOARD_DELL_E6400
select BOARD_DELL_GM45_LATITUDE_COMMON
+config BOARD_DELL_E4300
+ select BOARD_DELL_GM45_LATITUDE_COMMON
+
if BOARD_DELL_GM45_LATITUDE_COMMON
config INTEL_GMA_DPLL_REF_FREQ
default 100000000
@@ -30,12 +33,14 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "Latitude E6400" if BOARD_DELL_E6400
+ default "Latitude E4300" if BOARD_DELL_E4300
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config VARIANT_DIR
default "e6400" if BOARD_DELL_E6400
+ default "e4300" if BOARD_DELL_E4300
config USBDEBUG_HCD_INDEX
default 1
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
index aefe777109..4dc95f46be 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig.name
+++ b/src/mainboard/dell/gm45_latitude/Kconfig.name
@@ -1,4 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
+config BOARD_DELL_E4300
+ bool "Latitude E4300"
+
config BOARD_DELL_E6400
bool "Latitude E6400"
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3
GIT binary patch
literal 3881
zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+
zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5a<biIGGii6#d8gP4#QmGpeGyBx))(i;53
zx0(69nR)Nco0&Inc1d4HFVD7b?CrX@org342aOf$sh&<9U7NP<Sl8a$zN4diQ+5M?
z9rN*fa`GZDAW257d6jcVwtw%wp<VsFPss9IbIT6VyT7@GKQuhTyNCDm-+uql-l6R9
zaA9y{CEr#U=-)Ruz;_Pq?H?H$9GyPr&Fjey7akuO+O>Nhx3i7B*>RjEs#<v0-hG36
zcy@TCu#&g$*~7O8nNhxFaCC5F|KPw%gBc7st!SzQND;)Ih9pfkBd$T$U~A~qu#ltO
zMczfDhAs`eH4JHpsJLH4lZIP4`dyfi4M|pkg+SayZ(n(7kunGFvl<qe=w81$=+A#a
zN=hgb2&njUcPLB!=P$(o-$={^mxQGIHvtVGBS4IU%YyNVhd3krw*m^es@B12UftTZ
zHsf}zTi<zK_vS6VeYx!qdQTpH>PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC
zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpD<v6uK&w=s5=N^P
zn1nKYZrHyr#A-t5vRX$dPN$Pl=yivfA{67CP>h$)OQqAIh6jOwCxuw)qvS0N+Nk!?
zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E
z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u
z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L<DD#SV;6@`cGC4?jgJ8YLq>~qi^
z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I<Q#e&+8Yy!=BeKi&0@sfte<K0&
zMgsgs0(vE~6cP&098SWEom4ZZF%<l!OeEuw4n?=)Y_tg#&wy^{e@5{s`F9qRm`5m;
zi_|4iQq@4&R8mD)tJIvCw3$`@-B9JV=`1}s_;B_rjtcVXpQ!o`MAJ$M5w65C7t<Ku
z%xfIo$p$+0N}Qe(C7MY#!0SQ1({^-qFj5ylEHjhwn>8}OhGtOw#1e$Fn9w<r1Zp}l
zPz$#mOP$ow*1(UHvmCGVz;T^IRnSxa*6jz+_oSD)xmT|Cbl&YcJ5M&d?&+&NDI2Y0
zO0ai&>sUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6
z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e%
zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D
z!+P0Z#|`^S!}`Hs7Yw^5X*DKUOVaL7TBAv}d|dV9^O8rYn%=4o&5GjdSWeb`yeyf7
zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG*
zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg
zI{c?gKNv~R$<jgIlQvzm9GD`y{Dh<T(H)!WlUUWvtFvzDqaVV>&eHj<So5w}UG%+7
zt=J~1YHpT3TjRY{XlrmCz6QBZ$WqGr>8!uus22Br_GkCD$Q)pf!<P$30Ez;o=qDzr
z7@f;LJ+ZPlo=?}4PvMm&OKLGLZ0h1&n7U8@9GP~;8!wz(OqQ<s6e;@8hfYU0ht*9>
zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K<j&AXad#XeO8mgw(v
z_Gj1VBJZIpZ<>`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692<oYlGx5_cte6LX
JE5(FU=`RLB=-&VU
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
new file mode 100644
index 0000000000..89b81b3d69
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP2, -- dock DP
+ Analog, -- mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
new file mode 100644
index 0000000000..b50f8da0b5
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_NATIVE,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_NATIVE,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
new file mode 100644
index 0000000000..a9948a93dd
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x111d76b2, /* IDT 92HD71B7X */
+ 0x1028024d, /* Subsystem ID */
+ 13, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+
+ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
+ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
+ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
+ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
+ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
+ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
+ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
+ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
+};
+
+const u32 pc_beep_verbs[] = {
+ 0x00170500, /* power up codec */
+ 0x00d70500, /* power up speakers */
+ 0x00d70102, /* select mixer (input 0x2) for speakers */
+ 0x00d70740, /* enable speakers output */
+ 0x02770720, /* enable beep input */
+ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
+ 0x00d37000, /* unmute speakers */
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
new file mode 100644
index 0000000000..20dfa245fb
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/gm45
+ device domain 0 on
+ subsystemid 0x1028 0x024d inherit
+ chip southbridge/intel/i82801ix
+ device pci 1c.2 off end # PCIe Port #3
+ end
+ end
+end
--
2.47.3
@@ -0,0 +1,70 @@
From 2305cfb93110003613caa1dec8c5f574b5e400bd Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 3 May 2024 16:31:12 -0600
Subject: [PATCH 21/41] mb/dell: Add S3 SMI handler for Dell Latitudes
Integrate the previously added mec5035_smi_sleep() function into
mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
The E6400 does not require the EC command to sucessfully suspend and
resume from S3, though sending it does enable the breathing effect on
the power LED while in S3. Without it, all LEDs turn off during S3.
Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++
src/mainboard/dell/haswell_latitude/smihandler.c | 9 +++++++++
src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
3 files changed, 27 insertions(+)
create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c
create mode 100644 src/mainboard/dell/haswell_latitude/smihandler.c
create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
new file mode 100644
index 0000000000..00e55b51db
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_smi_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/haswell_latitude/smihandler.c b/src/mainboard/dell/haswell_latitude/smihandler.c
new file mode 100644
index 0000000000..00e55b51db
--- /dev/null
+++ b/src/mainboard/dell/haswell_latitude/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_smi_sleep(slp_typ);
+}
diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
new file mode 100644
index 0000000000..00e55b51db
--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ mec5035_smi_sleep(slp_typ);
+}
--
2.47.3
@@ -0,0 +1,31 @@
From aafddebf91f185d9c72fa1492af9128ee4803239 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Tue, 31 Dec 2024 14:42:24 +0000
Subject: [PATCH 22/41] Disable compression on refcode insertion
Compression is not reliably reproducible. In an lbmk release
context, this means we cannot rely on vendorfile insertion.
Therefore, use uncompressed refcode.
Signed-off-by: Leah Rowe <info@minifree.org>
---
Makefile.mk | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile.mk b/Makefile.mk
index 75787b32d4..3616f4fe68 100644
--- a/Makefile.mk
+++ b/Makefile.mk
@@ -1422,7 +1422,7 @@ endif
cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
$(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
$(CONFIG_CBFS_PREFIX)/refcode-type := stage
-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG)
+$(CONFIG_CBFS_PREFIX)/refcode-compression := none
cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
--
2.47.3
@@ -1,39 +0,0 @@
From 536a1dd349f590cbefccac7e7364cafcdaec9600 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 22 Oct 2023 15:02:25 +0100
Subject: [PATCH 22/30] don't use github for the acpica download
i have the tarball from a previous download, and i placed
it on libreboot rsync, which then got mirrored to princeton.
today, github's ssl cert was b0rking the hell out and i really
really wanted to finish a build, and didn't want to wait for
github to fix their httpd.
so i'm now hosting this specific acpica tarball on rsync.
this patch makes that URL be used, instead of the github one.
that's the 2nd time i've had to patch coreboot's acpica download!
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 23a5caf2bb..36565a906c 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2
@@ -1,142 +0,0 @@
From ad812d008d570c1655bff13a9026f39a9efdcbc9 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 31 Oct 2023 18:24:39 +0000
Subject: [PATCH 23/30] crank up vram allocation on more intel boards
these were added to libreboot, and it's a policy of
libreboot to max out the vram settings. this was
overlooked, in prior revisions and releases.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6400/cmos.default | 2 +-
src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
src/mainboard/hp/compaq_8200_elite_sff/cmos.default | 2 +-
src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
src/mainboard/hp/snb_ivb_laptops/cmos.default | 1 +
src/mainboard/lenovo/t420/cmos.default | 1 +
src/mainboard/lenovo/t420s/cmos.default | 1 +
src/mainboard/lenovo/t430/cmos.default | 1 +
src/mainboard/lenovo/t520/cmos.default | 1 +
src/mainboard/lenovo/t530/cmos.default | 1 +
src/mainboard/lenovo/x201/cmos.default | 1 +
src/mainboard/lenovo/x220/cmos.default | 1 +
12 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
index eeb6f47364..25dfa38cb5 100644
--- a/src/mainboard/dell/e6400/cmos.default
+++ b/src/mainboard/dell/e6400/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Disable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
index ccc7e64625..7c97b84baf 100644
--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
+++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
@@ -3,5 +3,5 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=128M
+gfx_uma_size=224M
fan_full_speed=Disable
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
index 6d27a79c66..4517ffc7c2 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
@@ -3,5 +3,5 @@ debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=224M
psu_fan_lvl=3
diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
index 6f3cec735e..9fc4db2990 100644
--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
@@ -3,4 +3,4 @@ debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=224M
diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
index ad822d5043..89418a4cfc 100644
--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
+++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
@@ -3,3 +3,4 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
index c011867916..83f590d39d 100644
--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
@@ -15,3 +15,4 @@ trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
index c011867916..83f590d39d 100644
--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
@@ -15,3 +15,4 @@ trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
index 55e1e6c04e..a72108f47e 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
usb_always_on=Disable
hybrid_graphics_mode=Integrated Only
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
index b66f7034dc..a73ea6e9ee 100644
--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
index b66f7034dc..a73ea6e9ee 100644
--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
index 2cf484fd5a..46294d91ca 100644
--- a/src/mainboard/lenovo/x201/cmos.default
+++ b/src/mainboard/lenovo/x201/cmos.default
@@ -15,3 +15,4 @@ power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
usb_always_on=Disable
+gfx_uma_size=128M
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
index 52f303dfdb..92a2026542 100644
--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
me_state=Disabled
+gfx_uma_size=224M
--
2.39.2
@@ -0,0 +1,187 @@
From 09febfb85eb176c8bf0e416412ed0b971dc2cefc Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 21 Apr 2025 02:58:47 +0100
Subject: [PATCH 23/41] nb/intel/*: Disable stack overflow debug options
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/northbridge/intel/e7505/Kconfig | 9 +++++++++
src/northbridge/intel/gm45/Kconfig | 9 +++++++++
src/northbridge/intel/haswell/Kconfig | 9 +++++++++
src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++
src/northbridge/intel/i945/Kconfig | 9 +++++++++
src/northbridge/intel/ironlake/Kconfig | 9 +++++++++
src/northbridge/intel/pineview/Kconfig | 9 +++++++++
src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++
src/northbridge/intel/x4x/Kconfig | 9 +++++++++
9 files changed, 85 insertions(+)
diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
index 039a7396f8..ddcb986f10 100644
--- a/src/northbridge/intel/e7505/Kconfig
+++ b/src/northbridge/intel/e7505/Kconfig
@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505
select NO_CBFS_MCACHE
select SMM_TSEG
select NEED_SMALL_2MB_PAGE_TABLES
+
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
index 35e89b0c88..c5456d0ddf 100644
--- a/src/northbridge/intel/gm45/Kconfig
+++ b/src/northbridge/intel/gm45/Kconfig
@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index c57f1ec380..0a5181b183 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL
if NORTHBRIDGE_INTEL_HASWELL
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
config USE_NATIVE_RAMINIT
bool "[NOT COMPLETE] Use native raminit"
default n
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
index dbb2d7436b..5e9418b6a9 100644
--- a/src/northbridge/intel/i440bx/Kconfig
+++ b/src/northbridge/intel/i440bx/Kconfig
@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM
If your board has 4 DIMM slots, you must use select this option, in
your Kconfig file of the board. On boards with 3 DIMM slots,
do _not_ select this option.
+
+if NORTHBRIDGE_INTEL_I440BX
+
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
+endif
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
index c4e17f90bf..b12f5be091 100644
--- a/src/northbridge/intel/i945/Kconfig
+++ b/src/northbridge/intel/i945/Kconfig
@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
index 39566a6e5f..f46acf6937 100644
--- a/src/northbridge/intel/ironlake/Kconfig
+++ b/src/northbridge/intel/ironlake/Kconfig
@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
index a05b866dad..50e3a7cdb9 100644
--- a/src/northbridge/intel/pineview/Kconfig
+++ b/src/northbridge/intel/pineview/Kconfig
@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE
config DOMAIN_RESOURCE_32BIT_LIMIT
default 0xfec00000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
index 9972a43da0..fe4ac5106c 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
+++ b/src/northbridge/intel/sandybridge/Kconfig
@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX
default 2 if IGD_DEFAULT_UMA_SIZE_96MB
default 3 if IGD_DEFAULT_UMA_SIZE_128MB
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 646af3510b..069fa0244d 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE
config FIXED_EPBAR_MMIO_BASE
default 0xfed19000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
endif
--
2.47.3
@@ -0,0 +1,708 @@
From 70f588b7cc66af2e427d9045d36ac2f5f4835dae Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Mon, 30 Sep 2024 20:44:38 -0400
Subject: [PATCH 24/41] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/optiplex_780/Kconfig | 40 ++++
src/mainboard/dell/optiplex_780/Kconfig.name | 4 +
src/mainboard/dell/optiplex_780/Makefile.mk | 10 +
src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 +
.../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++
.../dell/optiplex_780/acpi/superio.asl | 18 ++
.../dell/optiplex_780/board_info.txt | 6 +
src/mainboard/dell/optiplex_780/cmos.default | 8 +
src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++
src/mainboard/dell/optiplex_780/cstates.c | 8 +
src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++
src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++
.../dell/optiplex_780/gma-mainboard.ads | 16 ++
.../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes
.../optiplex_780/variants/780_mt/early_init.c | 12 ++
.../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++
.../optiplex_780/variants/780_mt/hda_verb.c | 26 +++
.../variants/780_mt/overridetree.cb | 10 +
18 files changed, 530 insertions(+)
create mode 100644 src/mainboard/dell/optiplex_780/Kconfig
create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name
create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk
create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl
create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl
create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt
create mode 100644 src/mainboard/dell/optiplex_780/cmos.default
create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout
create mode 100644 src/mainboard/dell/optiplex_780/cstates.c
create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb
create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl
create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
new file mode 100644
index 0000000000..2d06c75c9a
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/Kconfig
@@ -0,0 +1,40 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_DELL_OPTIPLEX_780_COMMON
+ def_bool n
+ select BOARD_ROMSIZE_KB_8192
+ select CPU_INTEL_SOCKET_LGA775
+ select DRIVERS_I2C_CK505
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_X4X
+ select PCIEXP_ASPM
+ select PCIEXP_CLK_PM
+ select SOUTHBRIDGE_INTEL_I82801JX
+
+config BOARD_DELL_OPTIPLEX_780_MT
+ select BOARD_DELL_OPTIPLEX_780_COMMON
+
+if BOARD_DELL_OPTIPLEX_780_COMMON
+
+config VGA_BIOS_ID
+ default "8086,2e22"
+
+config MAINBOARD_DIR
+ default "dell/optiplex_780"
+
+config MAINBOARD_PART_NUMBER
+ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
+
+config OVERRIDE_DEVICETREE
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config VARIANT_DIR
+ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
+
+endif # BOARD_DELL_OPTIPLEX_780_COMMON
diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
new file mode 100644
index 0000000000..db7f2e8fe3
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_DELL_OPTIPLEX_780_MT
+ bool "OptiPlex 780 MT"
diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk
new file mode 100644
index 0000000000..d462995d75
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/Makefile.mk
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += cstates.c
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
+
+bootblock-y += variants/$(VARIANT_DIR)/early_init.c
+romstage-y += variants/$(VARIANT_DIR)/early_init.c
+
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl
new file mode 100644
index 0000000000..479296cb76
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
+
+/* dummy */
diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
new file mode 100644
index 0000000000..b7588dcc41
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+/* This is board specific information:
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
+ */
+
+If (PICM) {
+ Return (Package() {
+ /* PCI slot */
+ Package() { 0x0001ffff, 0, 0, 0x14},
+ Package() { 0x0001ffff, 1, 0, 0x15},
+ Package() { 0x0001ffff, 2, 0, 0x16},
+ Package() { 0x0001ffff, 3, 0, 0x17},
+
+ Package() { 0x0002ffff, 0, 0, 0x15},
+ Package() { 0x0002ffff, 1, 0, 0x16},
+ Package() { 0x0002ffff, 2, 0, 0x17},
+ Package() { 0x0002ffff, 3, 0, 0x14},
+ })
+} Else {
+ Return (Package() {
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
+
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
+ })
+}
diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl
new file mode 100644
index 0000000000..9f3900b86c
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#undef SUPERIO_DEV
+#undef SUPERIO_PNP_BASE
+#undef IT8720F_SHOW_SP1
+#undef IT8720F_SHOW_SP2
+#undef IT8720F_SHOW_EC
+#undef IT8720F_SHOW_KBCK
+#undef IT8720F_SHOW_KBCM
+#undef IT8720F_SHOW_GPIO
+#undef IT8720F_SHOW_CIR
+#define SUPERIO_DEV SIO0
+#define SUPERIO_PNP_BASE 0x2e
+#define IT8720F_SHOW_EC 1
+#define IT8720F_SHOW_KBCK 1
+#define IT8720F_SHOW_KBCM 1
+#define IT8720F_SHOW_GPIO 1
+#include <superio/ite/it8720f/acpi/superio.asl>
diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt
new file mode 100644
index 0000000000..aaf657b583
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/board_info.txt
@@ -0,0 +1,6 @@
+Category: desktop
+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default
new file mode 100644
index 0000000000..23f0e55f3e
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/cmos.default
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+sata_mode=AHCI
+gfx_uma_size=64M
diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout
new file mode 100644
index 0000000000..9f5012adb4
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/cmos.layout
@@ -0,0 +1,72 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+# coreboot config options: southbridge
+408 1 e 10 sata_mode
+409 2 e 7 power_on_after_fail
+411 1 e 1 nmi
+
+# coreboot config options: cpu
+
+# coreboot config options: northbridge
+432 4 e 11 gfx_uma_size
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+10 0 AHCI
+10 1 Compatible
+11 1 4M
+11 2 8M
+11 3 16M
+11 4 32M
+11 5 48M
+11 6 64M
+11 7 128M
+11 8 256M
+11 9 96M
+11 10 160M
+11 11 224M
+11 12 352M
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c
new file mode 100644
index 0000000000..4adf0edc63
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/cstates.c
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpigen.h>
+
+int get_cst_entries(const acpi_cstate_t **entries)
+{
+ return 0;
+}
diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb
new file mode 100644
index 0000000000..95e3bd517c
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/devicetree.cb
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/x4x
+ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
+ device domain 0 on
+ ops x4x_pci_domain_ops # PCI domain
+ subsystemid 0x8086 0x0028 inherit
+ device pci 0.0 on end # Host Bridge
+ device pci 1.0 on end # PCIe x16 2.0 slot
+ device pci 2.0 on end # Integrated graphics controller
+ device pci 2.1 on end # Integrated graphics controller 2
+ device pci 3.0 off end # ME
+ device pci 3.1 off end # ME
+ chip southbridge/intel/i82801jx # ICH10
+ register "gpe0_en" = "0x40"
+
+ # Set AHCI mode.
+ register "sata_port_map" = "0x3f"
+ register "sata_clock_request" = "1"
+
+ # Enable PCIe ports 0,1 as slots.
+ register "pcie_slot_implemented" = "0x3"
+
+ device pci 19.0 on end # GBE
+ device pci 1a.0 on end # USB
+ device pci 1a.1 on end # USB
+ device pci 1a.2 on end # USB
+ device pci 1a.7 on end # USB
+ device pci 1b.0 on end # Audio
+ device pci 1c.0 off end # PCIe 1
+ device pci 1c.1 off end # PCIe 2
+ device pci 1c.2 off end # PCIe 3
+ device pci 1c.3 off end # PCIe 4
+ device pci 1c.4 off end # PCIe 5
+ device pci 1c.5 off end # PCIe 6
+ device pci 1d.0 on end # USB
+ device pci 1d.1 on end # USB
+ device pci 1d.2 on end # USB
+ device pci 1d.7 on end # USB
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on end # LPC bridge
+ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5)
+ device pci 1f.3 on # SMBus
+ chip drivers/i2c/ck505 # IDT CV194
+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff, 0xff,
+ 0xff, 0xff, 0xff }"
+ register "regs" = "{ 0x15, 0x82, 0xff, 0xff,
+ 0xff, 0x00, 0x00, 0x95,
+ 0x00, 0x65, 0x7d, 0x56,
+ 0x13, 0xc0, 0x00, 0x07,
+ 0x01, 0x0a, 0x64 }"
+ device i2c 69 on end
+ end
+ end
+ device pci 1f.4 off end
+ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode)
+ device pci 1f.6 off end # Thermal Subsystem
+ end
+ end
+end
diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl
new file mode 100644
index 0000000000..9ad70469de
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/dsdt.asl
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20090811 // OEM revision
+)
+{
+ #include <acpi/dsdt_top.asl>
+
+ OSYS = 2002
+ // global NVS and variables
+ #include <southbridge/intel/common/acpi/platform.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/x4x/acpi/x4x.asl>
+ #include <southbridge/intel/i82801jx/acpi/ich10.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
new file mode 100644
index 0000000000..bc81cf4a40
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
@@ -0,0 +1,16 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP2,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf
GIT binary patch
literal 1917
zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb
zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX
zznS;`v-5V=o<pVaS;}Q53%NpOI!8{cz{K0eVfK65_|*A}SF)Me%$4!N`H5-z90%~a
zvGog3fe5LjnM&o#3$<#k{6>{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E
znI_A1T57efS5MG<y}m-_+CrVKE#0VADDft%nb#Y<<ao9;Mf?!XvM)_$Xla>NN5_ut
zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh
z0Pae^5`gfb?<R!YN+PQ)U7<%H;73qF3iyQT71$?W2s|f{69_4sRY(x>7Q)c(LsP)8
zQy)2gw<F#IP`I}U>gG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa<Jq(M
zbA{r}Z0XY6<@U{Y-d!KWR>9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n
z>oEf8XCt;_Y-iYBWz#<re{?il1^f{S#nht`VW!62^5R*KQ6_?#8e&Qw=9%`og2x!s
z&J)wlZ=a<yoJkutfwu4%aVXlu?i^8v?R77IyGvKcD|M`CFG$6FUmK8q<|o>3T9EmJ
z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<<Gei4)FzWqGEt6P8D
zA9m}s>;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH`
zawsKv^FvHqm+<DDPT)%}_kZ8^eT88YGmG-#)X3=RRB|L^Uj_{yd%JeO<1HRZVz=Fz
z+aqUCWdF3_={#Q&&k)eF1i=WV`AbSlzo*bP?x?ir5BVVO`R34f89jWL{Z}or^BwmG
z-E;A_iWVUUWnWQl3L|~0xA@rHJRA-;7V)Y6B5=@E8R@?(?5{Eh23RefpSOGX_F{8A
z1PtU+iNng^h#C7J<vufJ9>c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E
xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO(<xf!`#Pk3F
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
new file mode 100644
index 0000000000..e2fa05cd8f
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <northbridge/intel/x4x/x4x.h>
+
+void mb_get_spd_map(u8 spd_map[4])
+{
+ // BTX form factor
+ spd_map[0] = 0x53;
+ spd_map[1] = 0x52;
+ spd_map[2] = 0x51;
+ spd_map[3] = 0x50;
+}
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
new file mode 100644
index 0000000000..9993f17c55
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_NATIVE,
+ .gpio8 = GPIO_MODE_NATIVE,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_NATIVE,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_NATIVE,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT,
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio56 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_NATIVE,
+ .gpio69 = GPIO_MODE_NATIVE,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
new file mode 100644
index 0000000000..4158bcf899
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x11d4194a, /* Analog Devices AD1984A */
+ 0xbfd40000, /* Subsystem ID */
+ 10, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+ AZALIA_PIN_CFG(0, 0x11, 0x032140f0),
+ AZALIA_PIN_CFG(0, 0x12, 0x21214010),
+ AZALIA_PIN_CFG(0, 0x13, 0x901701f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0),
+ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121),
+ AZALIA_PIN_CFG(0, 0x16, 0x9933012e),
+ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0),
+ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
new file mode 100644
index 0000000000..555b1c1f5c
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/x4x
+ device domain 0 on
+ chip southbridge/intel/i82801jx
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2
+ end
+ end
+end
--
2.47.3
@@ -0,0 +1,326 @@
From 463148c9773f3dd44f60c2cf2ac17900c3e68619 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 30 Oct 2024 20:55:25 -0600
Subject: [PATCH 25/41] mb/dell/optiplex_780: Add USFF variant
Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/optiplex_780/Kconfig | 5 +
src/mainboard/dell/optiplex_780/Kconfig.name | 3 +
.../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes
.../variants/780_usff/early_init.c | 9 +
.../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++
.../optiplex_780/variants/780_usff/hda_verb.c | 26 +++
.../variants/780_usff/overridetree.cb | 10 ++
7 files changed, 219 insertions(+)
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
index 2d06c75c9a..fc649e35d5 100644
--- a/src/mainboard/dell/optiplex_780/Kconfig
+++ b/src/mainboard/dell/optiplex_780/Kconfig
@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON
config BOARD_DELL_OPTIPLEX_780_MT
select BOARD_DELL_OPTIPLEX_780_COMMON
+config BOARD_DELL_OPTIPLEX_780_USFF
+ select BOARD_DELL_OPTIPLEX_780_COMMON
+
if BOARD_DELL_OPTIPLEX_780_COMMON
config VGA_BIOS_ID
@@ -30,11 +33,13 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
+ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config VARIANT_DIR
default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
+ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF
endif # BOARD_DELL_OPTIPLEX_780_COMMON
diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
index db7f2e8fe3..bc84c82a79 100644
--- a/src/mainboard/dell/optiplex_780/Kconfig.name
+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
@@ -2,3 +2,6 @@
config BOARD_DELL_OPTIPLEX_780_MT
bool "OptiPlex 780 MT"
+
+config BOARD_DELL_OPTIPLEX_780_USFF
+ bool "OptiPlex 780 USFF"
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7
GIT binary patch
literal 1917
zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@i<uQKf!)+gO;|
zveT#>P+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G
z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX
zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv
zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB
zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU<Iv53Rb6YTgMPOY8;~P1Yglh^6Fgt1^
zCTz|SVPcSpZ44F@&oNPUMO@&BE3y(57YP_Y!4SZhE?GXYa7k+b0(X|s7u3GDRf^1#
zOd2ZCCPO|I&sHEt;p8UshhHtYQ>7!7x2m<d`Gu2<r+Qc4|6pwd8&zFboH_W7XE7uU
zWW-@Cim&mdY2!O{JANR)OTJG2z>LBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T
z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`<pE+J?KFZ=&_JVP1YL=#z<-Q*24K4
zn+$YxrHNJJc`k?_8N=Kres26_#E8GLn2{jfW5P%ge`kL(Btkt=>xo)V)Ow=U6P12c
z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8
zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE
zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb
zV99s{>`r76L#Hr6XW6r|<iq#4Jr?XsxKyeJKEj7;e4SZ^1B12u&iV_9M0*Kem@fmn
z1C>>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq<Gj{q2D(
z>&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a=
T#w3FFBiyj<XAh$hb(enud`r7S
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
new file mode 100644
index 0000000000..2a55fc3a6e
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <northbridge/intel/x4x/x4x.h>
+
+void mb_get_spd_map(u8 spd_map[4])
+{
+ spd_map[0] = 0x50;
+ spd_map[2] = 0x52;
+}
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
new file mode 100644
index 0000000000..389f4077d7
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
@@ -0,0 +1,166 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_NATIVE,
+ .gpio8 = GPIO_MODE_NATIVE,
+ .gpio9 = GPIO_MODE_GPIO,
+ .gpio10 = GPIO_MODE_GPIO,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_NATIVE,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_NATIVE,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio9 = GPIO_DIR_OUTPUT,
+ .gpio10 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_OUTPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_OUTPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_INPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio9 = GPIO_LEVEL_HIGH,
+ .gpio18 = GPIO_LEVEL_HIGH,
+ .gpio20 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_NATIVE,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT,
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_OUTPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio35 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_HIGH,
+ .gpio56 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio72 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ },
+};
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
new file mode 100644
index 0000000000..c94e06b156
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x11d4194a, /* Analog Devices AD1984A */
+ 0x10280420, /* Subsystem ID */
+ 10, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+ AZALIA_PIN_CFG(0, 0x11, 0x02214040),
+ AZALIA_PIN_CFG(0, 0x12, 0x01014010),
+ AZALIA_PIN_CFG(0, 0x13, 0x991301f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x02a19020),
+ AZALIA_PIN_CFG(0, 0x15, 0x01813030),
+ AZALIA_PIN_CFG(0, 0x16, 0x413301f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0),
+ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0),
+ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
new file mode 100644
index 0000000000..555b1c1f5c
--- /dev/null
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/x4x
+ device domain 0 on
+ chip southbridge/intel/i82801jx
+ device pci 1c.0 on end # PCIe 1
+ device pci 1c.1 on end # PCIe 2
+ end
+ end
+end
--
2.47.3
@@ -1,36 +0,0 @@
From 936a8f113772c93d7501e7133159ab4e23436222 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 22:57:08 +0000
Subject: [PATCH 25/30] use mirrorservice.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 36565a906c..4d4ca06113 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
# to the jenkins build as well, or the builder won't download it.
# GCC toolchain archive locations
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2
@@ -1,792 +0,0 @@
From 973783a989cdcb7b77029e369156c81eefe8cc67 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 19 Aug 2023 16:19:10 -0600
Subject: [PATCH 26/30] mb/dell: Add Latitude E6530 (Ivy Bridge)
Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested. This
is based on the autoport output with some manual tweaks. The flash is
8MiB + 4MiB. It can be internally flashed by sending a command to the
EC, which causes the EC to pull the FDO pin low and the firmware to skip
setting up any chipset based write protections. [1] The EC is the SMSC
MEC5055, which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6530/Kconfig | 37 ++++
src/mainboard/dell/e6530/Kconfig.name | 2 +
src/mainboard/dell/e6530/Makefile.inc | 6 +
src/mainboard/dell/e6530/acpi/ec.asl | 9 +
src/mainboard/dell/e6530/acpi/platform.asl | 12 ++
src/mainboard/dell/e6530/acpi/superio.asl | 3 +
src/mainboard/dell/e6530/acpi_tables.c | 16 ++
src/mainboard/dell/e6530/board_info.txt | 6 +
src/mainboard/dell/e6530/cmos.default | 9 +
src/mainboard/dell/e6530/cmos.layout | 88 ++++++++++
src/mainboard/dell/e6530/data.vbt | Bin 0 -> 4280 bytes
src/mainboard/dell/e6530/devicetree.cb | 68 ++++++++
src/mainboard/dell/e6530/dsdt.asl | 30 ++++
src/mainboard/dell/e6530/early_init.c | 38 ++++
src/mainboard/dell/e6530/gma-mainboard.ads | 20 +++
src/mainboard/dell/e6530/gpio.c | 192 +++++++++++++++++++++
src/mainboard/dell/e6530/hda_verb.c | 33 ++++
src/mainboard/dell/e6530/mainboard.c | 21 +++
18 files changed, 590 insertions(+)
create mode 100644 src/mainboard/dell/e6530/Kconfig
create mode 100644 src/mainboard/dell/e6530/Kconfig.name
create mode 100644 src/mainboard/dell/e6530/Makefile.inc
create mode 100644 src/mainboard/dell/e6530/acpi/ec.asl
create mode 100644 src/mainboard/dell/e6530/acpi/platform.asl
create mode 100644 src/mainboard/dell/e6530/acpi/superio.asl
create mode 100644 src/mainboard/dell/e6530/acpi_tables.c
create mode 100644 src/mainboard/dell/e6530/board_info.txt
create mode 100644 src/mainboard/dell/e6530/cmos.default
create mode 100644 src/mainboard/dell/e6530/cmos.layout
create mode 100644 src/mainboard/dell/e6530/data.vbt
create mode 100644 src/mainboard/dell/e6530/devicetree.cb
create mode 100644 src/mainboard/dell/e6530/dsdt.asl
create mode 100644 src/mainboard/dell/e6530/early_init.c
create mode 100644 src/mainboard/dell/e6530/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e6530/gpio.c
create mode 100644 src/mainboard/dell/e6530/hda_verb.c
create mode 100644 src/mainboard/dell/e6530/mainboard.c
diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
new file mode 100644
index 0000000000..582adddbd4
--- /dev/null
+++ b/src/mainboard/dell/e6530/Kconfig
@@ -0,0 +1,37 @@
+if BOARD_DELL_LATITUDE_E6530
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+ default "dell/e6530"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E6530"
+
+config VGA_BIOS_ID
+ default "8086,0166"
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config USBDEBUG_HCD_INDEX
+ default 2
+endif
diff --git a/src/mainboard/dell/e6530/Kconfig.name b/src/mainboard/dell/e6530/Kconfig.name
new file mode 100644
index 0000000000..01ed76d107
--- /dev/null
+++ b/src/mainboard/dell/e6530/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6530
+ bool "Latitude E6530"
diff --git a/src/mainboard/dell/e6530/Makefile.inc b/src/mainboard/dell/e6530/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e6530/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6530/acpi/ec.asl b/src/mainboard/dell/e6530/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6530/acpi/platform.asl b/src/mainboard/dell/e6530/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6530/acpi/superio.asl b/src/mainboard/dell/e6530/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e6530/acpi_tables.c b/src/mainboard/dell/e6530/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e6530/board_info.txt b/src/mainboard/dell/e6530/board_info.txt
new file mode 100644
index 0000000000..4601a4aaba
--- /dev/null
+++ b/src/mainboard/dell/e6530/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/dell/e6530/cmos.default b/src/mainboard/dell/e6530/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e6530/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
new file mode 100644
index 0000000000..e85ea4c661
--- /dev/null
+++ b/src/mainboard/dell/e6530/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+415 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e6530/data.vbt b/src/mainboard/dell/e6530/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
GIT binary patch
literal 4280
zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV
zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU
zIJ+cPr4+cc-@WIad+wQY&YW{+c1J!nPPgn&^^N3Hy*D37jg0=7CSl@*=mXr>x75gi
zTMlK0$A=H4Mh~QKqCa92jz_;d3rtFqp(o-4gCnzxrJ2}Rw@^!haWp<ahv&+aDb5_3
zE0-vq=pkms7Ves!pD#^PA#PF^_wjBTO=oC(ayR{asyKURiBdh3?x76Ll#Z5WXklvl
z@M5XFK#OxUXqrdzedca+l4WK~_tG8Hv&HgsX`$Za3pnYy`CpW$@0?nsSh|}MrfK#j
z%y^t^lPNt{p5INwGcz<MWEN<wv`{J^Eluv$Rb2&6%ZgV5Bp(6~Lz2Eoz~@C!!B)bs
z1x-OrK~}*8L07Po(5+xZL6I<}phTEf5QRsVJYHa{f^AXPFaoSsnJ0feXUdB=CJ>Fv
zr&_=Q6YubieL}zoiJ0a+c+(bGwFN5g1pz;^rGP1sM+lHB@UAPM2&F=RB&yv@$caXF
ze~Io&3CQe=cMHr!e{yiokd?~p&F&k`jg99Ex7}WO=$8*Kx8wXv4eSa_CJqKVkyRr&
zCdcqs*@M5!gD84e@fW{|5B#mDGTH;JFw`h^stQcTjf@V3pNe8&f$=NG?-+klRGea*
zX1vOHi}4@EM~qJyfuM>e#%9J&Mjzt`j5OnB#;uGZ<1WTMj3vgSj3*esXZY{I`KqUa
zfbB~~a>piTMAVDNyHR<{<v-=}gXhE(15|emxueb8Kv%5>0{F7}8pool{7_h6u?7yg
zlyNm>-Eq_&WjW{0$9ZHq6x?~W8l2#1g0CyrtN#R-nbWG(?>iNG1zRiZgj;Lm_%rVe
zwZ6i{g#sR5xudpbj~5H9TNIQ3gMikIG@l(Z4IR@^2|Vu|LZteLF5@$KH5`Pr&3_vn
z^!Fn27&z6hSPR+*;D*&lm-)OE=ZgjK*(X&XdBq7RDUd7>|Lou?UMNg6lVCB;TPz{Z
zN4-~p*Rr=uq8OYdlAy38{}dt5%2}aUax{}zWzDRgmsn2|!)=Bp)U35;Ld3H+Ye=*_
z4S&0{5*TVI!OU-SWz$XUwrrnb%9?NHau^uhn>&;%&X#8O7mt)SIJr8D$u?NS=rUW6
zCmnxV&FgUDAWX}gZ+1AH&-C4Q=3sl5RX9=OWPfCtcRZi4tkX44YYfRH*@?H7T=Kz=
zG*i-wU2jbJMK%ChTMTXZFJEm~k;KCj*D60g=j!2ns8Q`g%jSRK^?=IwL^|I5-K2zH
z8*A0-mL%Q`R#xatM^u^E=IrX+2&bc;3rv!NipS^G*6zlIRAV(JJDU($OBHuptd&1(
zoNu>t*Q}|siS8#MYavR6j7&(~AEL#OaV(^+gy>YrSPiLfgy{2-p=xT2Mtd}4R8#XB
z-LDysYw8J&{-GJKYwEiif07x7u5QsOr5oeA`ZJxDb>p|XdQzvCb>nSaeP1UfY_x~f
z9bwuRHf|5Ahr{&iu<>+QeI`t=g^e>|^=z1;5o23K?TP5uo%2>aXQWCKr#dH;Qr0*j
z3LecKKarw5`Xblzd$&H4oP%y&l3egyUc<=<Azs)*u}X^*n$F~s2O<-paSF?q*HB+n
zqBfj5;J|x@hM`M(QD20jrkwi8`y3l;8qO;#l8A#CMI8Kg9E{ERsT>TGXaGC^5Cz)J
z4?eb?Kub*nWYdmhV-4?j<o}k#pt-{wK;b3U(B^+`s7-`HYOZOxv<+RG^LulAxKL|9
z3NH#9{Lg*7U1&gy<zHSG$;LMHby+V=ENlGFVLKjt%kkph7kP1M8|vebT=K5)*E>JW
zjd{Tu*o*CE*QO)}{_J>haU5zn+1QJ^eBg|d5n5-%|DwS@1+<Mtvat=iZ3BF??pZXh
zth4PnnWL*s%}k43fbe34>yaZ_2@Kj<UGt)`2G5>K>)nIBR-xB@+1PQ2*c$lV?Z13o
zbX%CHpm`!1Z4$d28~9k{rfu-0w@xg6{q!u2{)Dm_))4RK$?#7P*t7V+g_9d<V!MD`
zaj`t-?uy6zsjzp<-IdM6g(XhQX2iF<+p?Kmw6?a+f^VMex*PuetNfqf+4_FpD%8TW
eZvUbDHC^NLu5~gtzg|!EqSkX2ep9pg!tpEeo1jDh
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
new file mode 100644
index 0000000000..96eed178c5
--- /dev/null
+++ b/src/mainboard/dell/e6530/devicetree.cb
@@ -0,0 +1,68 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00000251"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x0535 inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 off end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x005c0921"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x007c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end # USB 3.0 Controller
+ device ref mei1 off end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+ device ref me_kt on end # Management Engine KT
+ device ref gbe on end # Intel Gigabit Ethernet
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda on end # High Definition Audio
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3
+ device ref pcie_rp4 on end # PCIe Port #4
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref ehci1 on end # USB2 EHCI #1
+ device ref pci_bridge off end # PCI bridge
+ device ref lpc on # LPC bridge
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end # SATA Controller 1
+ device ref smbus on end # SMBus
+ device ref sata2 off end # SATA Controller 2
+ device ref thermal off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/dell/e6530/dsdt.asl b/src/mainboard/dell/e6530/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e6530/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
new file mode 100644
index 0000000000..d57f48e7f1
--- /dev/null
+++ b/src/mainboard/dell/e6530/early_init.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 0, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 2, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ mec5035_early_init();
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/dell/e6530/gma-mainboard.ads b/src/mainboard/dell/e6530/gma-mainboard.ads
new file mode 100644
index 0000000000..1310830c8e
--- /dev/null
+++ b/src/mainboard/dell/e6530/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, --mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6530/gpio.c b/src/mainboard/dell/e6530/gpio.c
new file mode 100644
index 0000000000..777570765a
--- /dev/null
+++ b/src/mainboard/dell/e6530/gpio.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e6530/hda_verb.c b/src/mainboard/dell/e6530/hda_verb.c
new file mode 100644
index 0000000000..9de7e34311
--- /dev/null
+++ b/src/mainboard/dell/e6530/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x10280535, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280535),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6530/mainboard.c b/src/mainboard/dell/e6530/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e6530/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.39.2
@@ -0,0 +1,33 @@
From bf3c3df864cae045c82d1c032ced834a60239401 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 6 Jan 2025 01:53:53 +0000
Subject: [PATCH 26/41] src/intel/x4x: Disable stack overflow debug
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/northbridge/intel/x4x/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
index 069fa0244d..8c70344846 100644
--- a/src/northbridge/intel/x4x/Kconfig
+++ b/src/northbridge/intel/x4x/Kconfig
@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER
int
default 256
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
# This number must be equal or lower than what's reported in ACPI PCI _CRS
config DOMAIN_RESOURCE_32BIT_LIMIT
default 0xfec00000
--
2.47.3
@@ -0,0 +1,42 @@
From 0ad074869ec2a25508b1d6fc97c6ce61a9982fbd Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 22 Apr 2025 10:21:59 +0100
Subject: [PATCH 27/41] hp/8300cmt: remove xhci_overcurrent_mapping
No longer needed, as per the following commit:
commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1
Author: Keith Hui <buurin@gmail.com>
Date: Tue Dec 31 18:19:31 2024 -0500
sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping
Removing this from the devicetree also allows the
board to compile, otherwise an error is thrown:
build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping'
147 | .xhci_overcurrent_mapping = 0x00000c03,
| ^~~~~~~~~~~~~~~~~~~~~~~~
build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror]
147 | .xhci_overcurrent_mapping = 0x00000c03,
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
index 3d21739b72..3a0b6d5c59 100644
--- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
- register "xhci_overcurrent_mapping" = "0x00000c03"
register "xhci_switchable_ports" = "0x0000000f"
register "usb_port_config" = "{
{ 1, 0, 0 },
--
2.47.3
@@ -1,145 +0,0 @@
From 88652afd52b0a8e0fc8bb1656e59d8ae4796d847 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Thu, 25 Jan 2024 14:30:03 +0000
Subject: [PATCH 27/30] rebase dell/e6530 to newer coreboot code
i diffed nicholas's current e6430 patch, versus the old one,
prior to this revision update in lbmk, also cross referencing
the original e6430 and e6530 patches, diffing them, and the
result in this patch. most notably, spd data is now defined in
the devicetree, instead of early_init.c as per:
commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da
Author: Keith Hui <buurin@gmail.com>
Date: Sat Jul 22 12:49:05 2023 -0400
mb/*: Update SPD mapping for sandybridge boards
This should work fine. Will test after this builds.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/dell/e6530/Kconfig | 15 +++++++++++----
src/mainboard/dell/e6530/cmos.layout | 2 +-
src/mainboard/dell/e6530/devicetree.cb | 8 +++++---
src/mainboard/dell/e6530/early_init.c | 12 +++---------
4 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
index 582adddbd4..a104566890 100644
--- a/src/mainboard/dell/e6530/Kconfig
+++ b/src/mainboard/dell/e6530/Kconfig
@@ -20,18 +20,25 @@ config BOARD_SPECIFIC_OPTIONS
select SYSTEM_TYPE_LAPTOP
select USE_NATIVE_RAMINIT
+config DRAM_RESET_GATE_GPIO
+ default 60
+
config MAINBOARD_DIR
default "dell/e6530"
config MAINBOARD_PART_NUMBER
default "Latitude E6530"
-config VGA_BIOS_ID
- default "8086,0166"
+config PS2K_EISAID
+ default "PNP0303"
-config DRAM_RESET_GATE_GPIO
- default 60
+config PS2M_EISAID
+ default "PNP0F13"
config USBDEBUG_HCD_INDEX
default 2
+
+config VGA_BIOS_ID
+ default "8086,0166"
+
endif
diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
index e85ea4c661..1aa7e77bce 100644
--- a/src/mainboard/dell/e6530/cmos.layout
+++ b/src/mainboard/dell/e6530/cmos.layout
@@ -25,7 +25,7 @@ entries
# coreboot config options: EC
412 1 e 1 bluetooth
413 1 e 1 wwan
-415 1 e 1 wlan
+414 1 e 1 wlan
# coreboot config options: ME
424 1 e 14 me_state
diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
index 96eed178c5..37135bcf0f 100644
--- a/src/mainboard/dell/e6530/devicetree.cb
+++ b/src/mainboard/dell/e6530/devicetree.cb
@@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
register "gpu_panel_power_up_delay" = "400"
register "gpu_pch_backlight" = "0x13121312"
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
device domain 0x0 on
subsystemid 0x1028 0x0535 inherit
@@ -24,7 +26,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
register "gen1_dec" = "0x007c0681"
register "gen2_dec" = "0x005c0921"
register "gen3_dec" = "0x003c07e1"
- register "gen4_dec" = "0x007c0901"
+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
register "gpi0_routing" = "2"
register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
@@ -37,7 +39,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
register "xhci_switchable_ports" = "0x0000000f"
device ref xhci on end # USB 3.0 Controller
- device ref mei1 off end # Management Engine Interface 1
+ device ref mei1 on end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
device ref me_ide_r off end # Management Engine IDE-R
device ref me_kt on end # Management Engine KT
@@ -48,7 +50,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
device ref pcie_rp2 on end # PCIe Port #2
device ref pcie_rp3 on end # PCIe Port #3
device ref pcie_rp4 on end # PCIe Port #4
- device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp5 on end # PCIe Port #5
device ref pcie_rp6 on end # PCIe Port #6
device ref pcie_rp7 off end # PCIe Port #7
device ref pcie_rp8 off end # PCIe Port #8
diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
index d57f48e7f1..2b40f6963f 100644
--- a/src/mainboard/dell/e6530/early_init.c
+++ b/src/mainboard/dell/e6530/early_init.c
@@ -4,7 +4,6 @@
#include <bootblock_common.h>
#include <device/pci_ops.h>
#include <ec/dell/mec5035/mec5035.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
#include <southbridge/intel/bd82x6x/pch.h>
const struct southbridge_usb_port mainboard_usb_ports[] = {
@@ -26,13 +25,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
void bootblock_mainboard_early_init(void)
{
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
mec5035_early_init();
}
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
- read_spd(&spd[0], 0x50, id_only);
- read_spd(&spd[2], 0x52, id_only);
-}
--
2.39.2
@@ -0,0 +1,47 @@
From 4739f197ee3d4c95809ba48671bc5c409766b9c7 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Wed, 11 Dec 2024 01:06:01 +0000
Subject: [PATCH 28/41] dell/3050micro: disable nvme hotplug
in my testing, when running my 3050micro for a few days,
the nvme would sometimes randomly rename.
e.g. nvme0n1 renamed to nvme0n2
this might cause crashes in linux, if booting only from the
nvme. in my case, i was booting from mdraid (sata+nvme) and
every few days, the nvme would rename at least once, causing
my RAID to become unsynced. since i'm using RAID1, this was
OK and I could simply re-sync the array, but this is quite
precarious indeed. if you're using raid0, that will potentially
corrupt your RAID array indefinitely.
this same issue manifested on the T480/T480 thinkpads, and
S3 resume would break because of that, when booting from nvme,
because the nvme would be "unplugged" and appear to linux as a
new device (the one that you booted from).
the fix there was to disable hotplugging on that pci-e slot
for the nvme, so apply the same fix here for 3050 micro
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
.../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
index c5f1749b2c..ff48a8121a 100644
--- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
+++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
@@ -46,7 +46,7 @@ chip soc/intel/skylake
register "PcieRpAdvancedErrorReporting[20]" = "1"
register "PcieRpLtrEnable[20]" = "true"
register "PcieRpClkSrcNumber[20]" = "3"
- register "PcieRpHotPlug[20]" = "1"
+ register "PcieRpHotPlug[20]" = "0"
end
end
--
2.47.3
@@ -1,54 +0,0 @@
From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Thu, 25 Jan 2024 14:37:30 +0000
Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree
we neuter anyway. disabling it in devicetree will prevent linux
from ever trying to use it or load a driver for it, and thus
might prevent benign error messages from appearing in dmesg.
this change was suggested by nicholas when asked on irc.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/dell/e6430/devicetree.cb | 4 ++--
src/mainboard/dell/e6530/devicetree.cb | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
index 054b01c5ac..2b8574c984 100644
--- a/src/mainboard/dell/e6430/devicetree.cb
+++ b/src/mainboard/dell/e6430/devicetree.cb
@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
register "xhci_switchable_ports" = "0x0000000f"
device ref xhci on end
- device ref mei1 on end
+ device ref mei1 off end
device ref mei2 off end
device ref me_ide_r off end
- device ref me_kt on end
+ device ref me_kt off end
device ref gbe on end
device ref ehci2 on end
device ref hda on end
diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
index 37135bcf0f..010200bb6d 100644
--- a/src/mainboard/dell/e6530/devicetree.cb
+++ b/src/mainboard/dell/e6530/devicetree.cb
@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
register "xhci_switchable_ports" = "0x0000000f"
device ref xhci on end # USB 3.0 Controller
- device ref mei1 on end # Management Engine Interface 1
+ device ref mei1 off end # Management Engine Interface 1
device ref mei2 off end # Management Engine Interface 2
device ref me_ide_r off end # Management Engine IDE-R
- device ref me_kt on end # Management Engine KT
+ device ref me_kt off end # Management Engine KT
device ref gbe on end # Intel Gigabit Ethernet
device ref ehci2 on end # USB2 EHCI #2
device ref hda on end # High Definition Audio
--
2.39.2
@@ -0,0 +1,61 @@
From a6fdf61bb4779775fa330fc3f9b79be651c6854a Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 6 Jan 2025 01:36:23 +0000
Subject: [PATCH 29/41] src/intel/skylake: Disable stack overflow debug options
The option was appearing in T480/3050micro configs of lbmk,
after updating on the coreboot/next uprev for 20241206 rev8:
CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y
I did some digging. See coreboot commit:
commit 51cc2bacb6b07279b97e9934d079060475481fb6
Author: Subrata Banik <subratabanik@google.com>
Date: Fri Dec 13 13:07:28 2024 +0530
soc/intel/pantherlake: Disable stack overflow debug options
Well now:
I'm disabling this behaviour on Skylake, for the same
behaviour, because I want as few behaviour changes in general,
as possible, for the rev8 release.
According to Subrata's patch, which was for Pantherlake,
without this change, stack corruption can occur on verstage
and romstage early on. Please look at that coreboot patch,
referenced above, for clarity.
I see no harm in disabling this option for Skylake, since
the behaviour that it otherwise enables was not present
before.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/skylake/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 7c530f2c75..70c2a7643c 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -131,6 +131,15 @@ config DCACHE_RAM_SIZE
The size of the cache-as-ram region required during bootblock
and/or romstage.
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
config DCACHE_BSP_STACK_SIZE
hex
default 0x20400 if FSP_USES_CB_STACK
--
2.47.3
@@ -1,164 +0,0 @@
From f07ed32c36978327709a113967ec40e5ba8d828e Mon Sep 17 00:00:00 2001
From: risapav <risapav@gmail.com>
Date: Sun, 17 Dec 2023 16:54:07 +0100
Subject: [PATCH 29/30] x220_edp modification introduced, similar to x230_edp
---
src/mainboard/lenovo/x220/Kconfig | 13 ++++++-----
src/mainboard/lenovo/x220/Kconfig.name | 3 +++
src/mainboard/lenovo/x220/Makefile.mk | 6 +++++
.../lenovo/x220/variants/x220_edp/data.vbt | Bin 0 -> 4281 bytes
.../x220/variants/x220_edp/gma-mainboard.ads | 21 ++++++++++++++++++
5 files changed, 38 insertions(+), 5 deletions(-)
create mode 100644 src/mainboard/lenovo/x220/variants/x220_edp/data.vbt
create mode 100644 src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
index eeb55b4393..bc73a47df9 100644
--- a/src/mainboard/lenovo/x220/Kconfig
+++ b/src/mainboard/lenovo/x220/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
+if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 || BOARD_LENOVO_X220_EDP
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS
select DRIVERS_RICOH_RCE822
select EC_LENOVO_H8
select EC_LENOVO_PMH7
- select GFX_GMA_PANEL_1_ON_LVDS
+ select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
select H8_HAS_BAT_THRESHOLDS_IMPL
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
@@ -41,19 +41,22 @@ config MAINBOARD_DIR
default "lenovo/x220"
config VARIANT_DIR
- default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+ default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X220_EDP
default "x1" if BOARD_LENOVO_X1
config FMDFILE
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
config MAINBOARD_PART_NUMBER
- default "ThinkPad X220" if BOARD_LENOVO_X220
+ default "ThinkPad X220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220_EDP
default "ThinkPad X220i" if BOARD_LENOVO_X220I
default "ThinkPad X1" if BOARD_LENOVO_X1
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config INTEL_GMA_VBT_FILE
+ default "src/mainboard/\$(MAINBOARDDIR)/variants/x220_edp/data.vbt" if BOARD_LENOVO_X220_EDP
config USBDEBUG_HCD_INDEX
int
@@ -75,4 +78,4 @@ config PS2K_EISAID
config PS2M_EISAID
default "LEN0020"
-endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
+endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 || BOARD_LENOVO_X220_EDP
diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name
index 988ac4fb55..cd501954e0 100644
--- a/src/mainboard/lenovo/x220/Kconfig.name
+++ b/src/mainboard/lenovo/x220/Kconfig.name
@@ -6,3 +6,6 @@ config BOARD_LENOVO_X220I
config BOARD_LENOVO_X1
bool "ThinkPad X1"
+
+config BOARD_LENOVO_X220_EDP
+ bool "ThinkPad X220 eDP Mod (2K/FHD)"
diff --git a/src/mainboard/lenovo/x220/Makefile.mk b/src/mainboard/lenovo/x220/Makefile.mk
index b104bb52a9..052bf17a22 100644
--- a/src/mainboard/lenovo/x220/Makefile.mk
+++ b/src/mainboard/lenovo/x220/Makefile.mk
@@ -4,6 +4,12 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/romstage.c
+
+ifeq ($(CONFIG_BOARD_LENOVO_X220_EDP),y)
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x220_edp/gma-mainboard.ads
+else
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+endif
+
bootblock-y += early_init.c
romstage-y += early_init.c
diff --git a/src/mainboard/lenovo/x220/variants/x220_edp/data.vbt b/src/mainboard/lenovo/x220/variants/x220_edp/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
GIT binary patch
literal 4281
zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^
zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT
zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}(
z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg
zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW>
zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn
zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L
zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy;
z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY
zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH
z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
literal 0
HcmV?d00001
diff --git a/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads b/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
new file mode 100644
index 0000000000..f7cf0bc264
--- /dev/null
+++ b/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
@@ -0,0 +1,21 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
--
2.39.2
@@ -0,0 +1,36 @@
From 287a6d09ac6f5cdfc8255c2020e37441ddb870c7 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Thu, 26 Dec 2024 19:45:20 +0000
Subject: [PATCH 30/41] soc/intel/skylake: Don't compress FSP-S
Build systems like lbmk need to reproducibly insert
certain vendor files on release images.
Compression isn't always reproducible, and making it
so costs a lot more time than simply disabling compression.
With this change, the FSP-S module will now be inserted
without compression, which means that there will now be
about 40KB of extra space used in the flash.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/soc/intel/skylake/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 70c2a7643c..a2854923e7 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -14,7 +14,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
select DRAM_SUPPORT_DDR4
select DRIVERS_USB_ACPI
select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
- select FSP_COMPRESS_FSP_S_LZ4
+# select FSP_COMPRESS_FSP_S_LZ4
select FSP_M_XIP
select GENERIC_GPIO_LIB
select HAVE_FSP_GOP
--
2.47.3
@@ -0,0 +1,78 @@
From c0bb0e62f169e07ab11c434fbd79a6a26b4e7690 Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Wed, 18 Dec 2024 02:06:18 +0000
Subject: [PATCH 31/41] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
This is used by lbmk to know where a tb.bin file goes,
when extracting and padding TBT.bin from Lenovo ThunderBolt
firmware updates on T480/T480s and other machines, grabbing
Lenovo update files.
Not used in any builds, so it's not relevant for ./mk inject
However, the ThunderBolt firmware is now auto-downloaded on
T480/T480s. This is not inserted, because it doesn't go in
the main flash, but the resulting ROM image can be flashed
on the TB controller's separate flash chip.
Locations are as follows:
vendorfiles/t480s/tb.bin
vendorfiles/t480/tb.bin
This can be used for other affected ThinkPads when they're
added to Libreboot, but note that Lenovo provides different
TB firmware files for each machine.
Since I assume it's the same TB controller on all of those
machines, I have to wonder: what difference is there between
the various TBT.bin files provided by Lenovo, and how do they
differ in terms of actual flashed configuration?
We simply flash the padded TBT.bin when updating the firmware,
flashing externally. That's what this patch is for, so that
lbmk can auto-download them.
Signed-off-by: Leah Rowe <info@minifree.org>
---
src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index 2ffbaab85f..512b326381 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY
string
default MAINBOARD_PART_NUMBER
+config LENOVO_TBFW_BIN
+ string "Lenovo ThunderBolt firmware bin file"
+ default ""
+ help
+ ThunderBolt firmware for certain ThinkPad models e.g. T480.
+ Not used in the actual build. Libreboot's build system uses this
+ along with config/vendor/*/pkg.cfg entries defining a URL to the
+ Lenovo download link and hash. The resulting file when processed by
+ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device.
+ Earlier versions of this firmware had debug commands enabled that
+ sent logs to said flash IC, and it would quickly fill up, bricking
+ the ThunderBolt controller. With these updates, flashed externally,
+ you can fix the issue if present or otherwise prevent it. The benefit
+ here is that you then don't need to use Windows or a boot disk. You
+ can flash the TB firmware while flashing Libreboot firmware. Easy!
+ Look for these variables in lbmk:
+ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and
+ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file.
+ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting
+ the firmware, putting it at that desired location. In this way, lbmk
+ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb
+ and it appears at vendorfiles/t480/tb.bin fully padded and everything!
+
+ Just leave this blank if you don't care about this option. It's not
+ useful for every ThinkPad, only certain models.
+
endif # VENDOR_LENOVO
--
2.47.3
@@ -1,923 +0,0 @@
From 38a713eb071dd9c1b7d5092ce686537e5d9266f5 Mon Sep 17 00:00:00 2001
From: Mate Kukri <kukri.mate@gmail.com>
Date: Mon, 4 Dec 2023 21:34:18 +0000
Subject: [PATCH 1/1] mb/dell: Add OptiPlex 7020/9020 port
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
The OptiPlex 7020 and 9020 use physically identical motherboards.
Each model comes in the following form factors:
- 7020: SFF, MT
- 9020: USFF (not currently supported), SFF, MT
(7020 SFF) Boots Linux and Windows 10:
- Tested with an i3-4160 and i5-4460
- DRAM init works using the MRC (4G, 4G+4G)
- iGPU init works using libgfxinit (VGA, 2x DP)
- PCIe 16x: tested, ok
- PCIe 4x: tested, ok
- All USB2 and USB3 ports work
- SMSC SCH5555 Super I/O: serial works, PS/2 untested
- Audio: back and front output works, internal speaker works,
mic inputs untested
- Ethernet: tested, works
(9020 MT)
- Tested by Michael Büchler (thanks for the overridetree)
Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
---
src/mainboard/dell/optiplex_9020/Kconfig | 34 +++
src/mainboard/dell/optiplex_9020/Kconfig.name | 11 +
src/mainboard/dell/optiplex_9020/Makefile.inc | 5 +
src/mainboard/dell/optiplex_9020/acpi/ec.asl | 3 +
.../dell/optiplex_9020/acpi/platform.asl | 11 +
.../dell/optiplex_9020/acpi/superio.asl | 3 +
.../dell/optiplex_9020/board_info.txt | 8 +
src/mainboard/dell/optiplex_9020/bootblock.c | 116 ++++++++++
src/mainboard/dell/optiplex_9020/cmos.default | 4 +
src/mainboard/dell/optiplex_9020/cmos.layout | 58 +++++
src/mainboard/dell/optiplex_9020/data.vbt | Bin 0 -> 4409 bytes
.../dell/optiplex_9020/devicetree.cb | 80 +++++++
src/mainboard/dell/optiplex_9020/dsdt.asl | 25 ++
.../dell/optiplex_9020/gma-mainboard.ads | 18 ++
src/mainboard/dell/optiplex_9020/gpio.c | 217 ++++++++++++++++++
src/mainboard/dell/optiplex_9020/hda_verb.c | 27 +++
src/mainboard/dell/optiplex_9020/mainboard.c | 15 ++
.../dell/optiplex_9020/overridetree_mt.cb | 10 +
src/mainboard/dell/optiplex_9020/romstage.c | 53 +++++
19 files changed, 698 insertions(+)
create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig
create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig.name
create mode 100644 src/mainboard/dell/optiplex_9020/Makefile.inc
create mode 100644 src/mainboard/dell/optiplex_9020/acpi/ec.asl
create mode 100644 src/mainboard/dell/optiplex_9020/acpi/platform.asl
create mode 100644 src/mainboard/dell/optiplex_9020/acpi/superio.asl
create mode 100644 src/mainboard/dell/optiplex_9020/board_info.txt
create mode 100644 src/mainboard/dell/optiplex_9020/bootblock.c
create mode 100644 src/mainboard/dell/optiplex_9020/cmos.default
create mode 100644 src/mainboard/dell/optiplex_9020/cmos.layout
create mode 100644 src/mainboard/dell/optiplex_9020/data.vbt
create mode 100644 src/mainboard/dell/optiplex_9020/devicetree.cb
create mode 100644 src/mainboard/dell/optiplex_9020/dsdt.asl
create mode 100644 src/mainboard/dell/optiplex_9020/gma-mainboard.ads
create mode 100644 src/mainboard/dell/optiplex_9020/gpio.c
create mode 100644 src/mainboard/dell/optiplex_9020/hda_verb.c
create mode 100644 src/mainboard/dell/optiplex_9020/mainboard.c
create mode 100644 src/mainboard/dell/optiplex_9020/overridetree_mt.cb
create mode 100644 src/mainboard/dell/optiplex_9020/romstage.c
diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
new file mode 100644
index 0000000000..774a72f161
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/Kconfig
@@ -0,0 +1,34 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+if BOARD_DELL_OPTIPLEX_9020_SFF || BOARD_DELL_OPTIPLEX_9020_MT
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_CMOS_DEFAULT
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_HASWELL
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_LYNXPOINT
+ select SUPERIO_SMSC_SCH555x
+
+config CBFS_SIZE
+ default 0x600000
+
+config MAINBOARD_DIR
+ default "dell/optiplex_9020"
+
+config MAINBOARD_PART_NUMBER
+ default "OptiPlex 7020/9020 SFF" if BOARD_DELL_OPTIPLEX_9020_SFF
+ default "OptiPlex 7020/9020 MT" if BOARD_DELL_OPTIPLEX_9020_MT
+
+config OVERRIDE_DEVICETREE
+ default "overridetree_mt.cb" if BOARD_DELL_OPTIPLEX_9020_MT
+
+endif
diff --git a/src/mainboard/dell/optiplex_9020/Kconfig.name b/src/mainboard/dell/optiplex_9020/Kconfig.name
new file mode 100644
index 0000000000..c25c330a44
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/Kconfig.name
@@ -0,0 +1,11 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_DELL_OPTIPLEX_9020_SFF
+ bool "OptiPlex 7020/9020 SFF"
+ help
+ The 7020 SFF and 9020 SFF mainboards are physically identical.
+
+config BOARD_DELL_OPTIPLEX_9020_MT
+ bool "OptiPlex 7020/9020 MT"
+ help
+ The 7020 MT and 9020 MT mainboards are physically identical.
diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc
new file mode 100644
index 0000000000..6ca2f2afaa
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/Makefile.inc
@@ -0,0 +1,5 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+bootblock-y += bootblock.c
diff --git a/src/mainboard/dell/optiplex_9020/acpi/ec.asl b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/dell/optiplex_9020/acpi/platform.asl b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
new file mode 100644
index 0000000000..cda7682e3e
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ Return(Package() { 0, 0 })
+}
+
+Method(_PTS, 1)
+{
+
+}
diff --git a/src/mainboard/dell/optiplex_9020/acpi/superio.asl b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/dell/optiplex_9020/board_info.txt b/src/mainboard/dell/optiplex_9020/board_info.txt
new file mode 100644
index 0000000000..e30cf9c41f
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/board_info.txt
@@ -0,0 +1,8 @@
+Vendor name: Dell Inc.
+Board name: OptiPlex 7020/9020
+Release year: 2014
+Category: desktop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
new file mode 100644
index 0000000000..2837cf9cf1
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/bootblock.c
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <device/pnp_ops.h>
+#include <superio/smsc/sch555x/sch555x.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
+{
+ // Clear EC-to-Host mailbox
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
+
+ // Send address and value to the EC
+ sch555x_emi_write16(0, (addr1 * 2) | 0x101);
+ sch555x_emi_write32(4, val | (addr2 << 16));
+
+ // Wait for acknowledgement message from EC
+ outb(1, SCH555x_EMI_IOBASE);
+ size_t timeout = 0;
+ do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
+}
+
+struct ec_init_entry {
+ uint16_t addr;
+ uint8_t val;
+};
+
+static void ec_init(void)
+{
+ /*
+ * Tables from CORE_PEI
+ */
+
+ static const struct ec_init_entry init_table1[] = {
+ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10},
+ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10},
+ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12},
+ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12},
+ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10},
+ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11},
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i)
+ ec_write(2, init_table1[i].addr, init_table1[i].val);
+
+ static const struct ec_init_entry init_table2[] = {
+ {0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f},
+ {0x0083, 0xbb}, {0x0085, 0xd9}, {0x0086, 0x2c}, {0x008a, 0x34},
+ {0x008b, 0x60}, {0x0090, 0x5e}, {0x0091, 0x5e}, {0x0092, 0x86},
+ {0x0096, 0xa4}, {0x0097, 0xa4}, {0x0098, 0xa4}, {0x009b, 0xa4},
+ {0x00a0, 0x0a}, {0x00a1, 0x0a}, {0x00ae, 0x7c}, {0x00af, 0x7c},
+ {0x00b0, 0x9e}, {0x00b3, 0x7c}, {0x00b6, 0x08}, {0x00b7, 0x08},
+ {0x00ea, 0x64}, {0x00ef, 0xff}, {0x00f8, 0x15}, {0x00f9, 0x00},
+ {0x00f0, 0x30}, {0x00fd, 0x01}, {0x01a1, 0x00}, {0x01a2, 0x00},
+ {0x01b1, 0x08}, {0x01be, 0x90}, {0x0280, 0x24}, {0x0281, 0x13},
+ {0x0282, 0x03}, {0x0283, 0x0a}, {0x0284, 0x80}, {0x0285, 0x03},
+ {0x0288, 0x80}, {0x0289, 0x0c}, {0x028a, 0x03}, {0x028b, 0x0a},
+ {0x028c, 0x80}, {0x028d, 0x03}, {0x0040, 0x01},
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i)
+ ec_write(1, init_table2[i].addr, init_table2[i].val);
+
+ /*
+ * Table from PeiHwmInit
+ */
+
+ static const struct ec_init_entry hwm_init_table[] = {
+ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f},
+ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33},
+ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff},
+ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00},
+ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00},
+ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80},
+ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02},
+ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04},
+ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50},
+ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50},
+ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c},
+ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd},
+ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e},
+ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00},
+ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff},
+ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00},
+ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c},
+ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02},
+ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03},
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i)
+ ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val);
+}
+
+#define SCH555x_IOBASE 0x2e
+#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL)
+#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1)
+
+void mainboard_config_superio(void)
+{
+ // Super I/O early init will map Runtime and EMI registers
+ sch555x_early_init(GLOBAL_DEV);
+
+ // Changes LED color among a few other things (extracted from Dell's FW)
+ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS);
+ outb(0x00, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN);
+ outb(0x18, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN1);
+ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
+ outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
+
+ // Magic EC init
+ ec_init();
+
+ // Magic EC init is needed for UART1 initialization to work
+ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+}
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
new file mode 100644
index 0000000000..b159660aa8
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
@@ -0,0 +1,4 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
new file mode 100644
index 0000000000..c9ba76c78f
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
@@ -0,0 +1,58 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 3 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 4 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 5 power_on_after_fail
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+
+2 0 Enable
+2 1 Disable
+
+3 0 Fallback
+3 1 Normal
+
+4 0 Emergency
+4 1 Alert
+4 2 Critical
+4 3 Error
+4 4 Warning
+4 5 Notice
+4 6 Info
+4 7 Debug
+4 8 Spew
+
+5 0 Disable
+5 1 Enable
+5 2 Keep
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/dell/optiplex_9020/data.vbt b/src/mainboard/dell/optiplex_9020/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..1779f3b8d1018ba0aae480103b145bd7b6dd6187
GIT binary patch
literal 4409
zcmdT{T}&KR6h8B_yR)-1!!lr9XiE<T5h_au1f&hdSy<_UtKG6lH%+yR*`>u$pi5g@
zP3)>@YHE~+rqQIfO&U!#QHhDMkD3^5qG|e|_!FbV_|P=QG{y&G)b-q%VY>waTYnNg
zlQZY%p84*%_nv!argpGv03)IJ_Pe7|bSMP|Y$`oQ_r=uJyEVQm92yAi>WXgdz6a04
zD)5&6aRng7aW^T=MoU}o*#7ireSZT+;@h#UsjZ1Q4>q^r@OTD8dxst!AG;&CDL8Oo
z^uXRm#BdDb@opR+9u95~SuwW<QzMfTqeF)qF*csrKZ)H~hheKJ9Bag}aojteN>8Tu
zlb(JA9~v1O%8aBZS%1O)#VHqfy2mFDXGV7K*^l+z4cKBBMzF<bZbmC*>>kfdG+}6T
z6#H4sB=%D$nS<$6lPaq+z<VHx902D6&lA9LzqdfOh#}ETa^{d^Qa3IULMDVoxLYjf
zv_SO(uW~#!R!i{VA*TVEBzVEHO|WbbVKxbVzx(ZS+aUqD7$Jw01c2!TeBcCl0o=?F
z28TS8$Zmu%>jW^<CJybs=4~hTnz>lR#jfi;e=$Iyv50HHXlZTl*xYG$g?l1>(OCb$
zU}DG4>=REuHB||}y?K34mZfn9c;qU`2=#DU;Ndl)1MU?sz-wNFPrQEkmiQ;)T^<R}
zdUSY)_#@&kiGTFS@Cz|7$)FHd5Z4d~iSHopC5{t6K)joHAMs<vPZPgD{1Wk5;x~xj
zC4QgyW8%+<za@4bfZuX_7Ccs_S<aEAwgkTj&o@B!q~ky7_`O%{^_3mzbL0|(U(%J!
zc|7n(?qUFPIq6Q8fk_B7y<FHqia0WANkND?_5ev%QVGY-<-AEUTj=`t?()a1=55O5
z{_mRaBdE^OAe?=LY&@K6Vl9(-%92(Xz`HWb2jrieR~917`}6Ye2PkFGM<<PdozIAn
z^~{K!pyf`h0{p_snin|Dy#pS02chH`c=HRG@BbfDysjI9Dy8GmAziVGdEP8P1@20r
zBqq#pp3aSG?5Z($i{C%72adbj0IKXTPv?C2Liz8vth$FvMX=5WiS0s*j42Hu+7sIq
z8yZWG-Z!*2U8Hey1X2}XhM>*}9BsG30>%b-aT^$>F;QlFs?KdZG`Fp?&P=>G?}^-H
z8V}91nC5%)o<Kdc9}(=yRN9ZYz<R5Y#!XvQOq$z%Cn**6PyxTvRRPl+f_+_}SCoA<
za@Vv<hO&AVF3|ye$@4RJwCumBv5E4paIqMm<F?cxfHmzf>&;H%+*-esTyM8m72{dk
zN_}yhSK?iwVn0WBiCk!kp>joHDlbZb@-S0HiL0(nDpFM`l;n%Xd2HQIg5o*w(&Ie1
zXo(bBhcHASlm}+e6jDvD2&s06<%&>b5^ABIR?)PhL=q;MUUIqs5lZ+1pe5A$068bG
zYk1wEhT|Z7B_sHB-6yZ{VV6%I@W~JQaLT8j@X2R<_@Ph#!Y6;{LrKvq6}eWyK1JWD
z$ioUgr|72?`J93m6@5;TuPEqO_4TUUsA9jWr&M`N#p9~}sw&T@IIHTHRrx0s1Dd`;
zlUp_1q3NTVd{D!an*OFHpV#mkO~0ziziR4+t74X)<Fci+?Wnk=j6%hk;1x^$%=t;W
zN^Yg4Uc8pHADlgcLV{lz;Y<lab7BqFXUpvws%k&N(?Ss`Sx<+!GQ!KP+0;bGI<u<0
z4SuHz074M#Hw&c+7DDH;qgZ?(u>Ea)e<*`45Lgb&Bj~FK_ryRq5ZmCESNs5##`izi
zWl>%<LQf28jJj3r(DnvHaKF`A!KQ&LD-NM<^&lbC85n4V#QQeF4>b${%1!r_HHzg|
zb7P%(J~^e(e?Sd9{<%GhPj7S-3+AEyh&WB(;<TE@je=%!#d%nM6pIdgs~&vU<?vS!
ztaC^yZYGz`LA7!K7Z$M=S1RF53~x3RqnkZtSM@aQ$D;QIzd0M&*AX-mLFdJ1%|nTW
zKu4H+<*IHlA(@4;q~A}wijjptb-`A1OTqCOFSJ6vTQS-lW>Em~L_u66jOlR9ZUEZ|
zMhC-jAj9!85eeUR&5CZpNVwUt>909-|5kF?Ve@Y58TNJV5CLGmjb)HGdJ22pR+!su
z`@ntQ1&|Z3+xNb&p(?Li{yzJDS)dq4FZ3_c3(;&nw}2XNf@gau=U)2uzaL_df=2EH
PTo#&U0FLJAf1&;f?(g8r
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
new file mode 100644
index 0000000000..c0b17a15ff
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
@@ -0,0 +1,80 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/haswell
+ # This mainboard has VGA
+ register "gpu_ddi_e_connected" = "1"
+
+ chip cpu/intel/haswell
+ device cpu_cluster 0 on ops haswell_cpu_bus_ops end
+ end
+
+ device domain 0 on
+ ops haswell_pci_domain_ops
+
+ subsystemid 0x1028 0x05a5 inherit
+
+ device pci 00.0 on end # Host bridge
+ device pci 01.0 on end # PCIe graphics
+ device pci 02.0 on end # VGA controller
+ device pci 03.0 on end # Mini-HD audio
+
+ chip southbridge/intel/lynxpoint
+ register "gen1_dec" = "0x007c0a01"
+ register "gen2_dec" = "0x007c0901"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x001c0901"
+ register "sata_port_map" = "0x33"
+
+ device pci 14.0 on end # xHCI controller
+ device pci 16.0 on end # Management Engine interface 1
+ device pci 16.1 off end # Management Engine interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 on end # Management Engine KT
+ device pci 19.0 on # Intel Gigabit Ethernet
+ subsystemid 0x1028 0x05a4
+ end
+ device pci 1a.0 on end # EHCI controller #2
+ device pci 1b.0 on end # HD audio controller
+ device pci 1c.0 off end
+ device pci 1c.1 off end
+ device pci 1c.2 off end
+ device pci 1c.3 off end
+ device pci 1c.4 on end # PCIe 4x slot
+ device pci 1c.5 off end
+ device pci 1c.6 off end
+ device pci 1c.7 off end
+ device pci 1d.0 on end # EHCI controller #1
+ device pci 1f.0 on # LPC bridge
+ chip superio/smsc/sch555x
+ device pnp 2e.0 on # EMI
+ io 0x60 = 0xa00
+ end
+ device pnp 2e.1 on # 8042
+ io 0x60 = 0x60
+ irq 0x0f = 0
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.7 on # UART1
+ io 0x60 = 0x3f8
+ irq 0x0f = 2
+ irq 0x70 = 4
+ end
+ device pnp 2e.8 off end # UART2
+ device pnp 2e.c on # LPC interface
+ io 0x60 = 0x2e
+ end
+ device pnp 2e.a on # Runtime registers
+ io 0x60 = 0xa40
+ end
+ device pnp 2e.b off end # Floppy Controller
+ device pnp 2e.11 off end # Parallel Port
+ end
+ end
+ device pci 1f.2 on end # SATA controller 1
+ device pci 1f.3 on end # SMBus
+ device pci 1f.5 off end # SATA controller 2
+ device pci 1f.6 off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/dell/optiplex_9020/dsdt.asl b/src/mainboard/dell/optiplex_9020/dsdt.asl
new file mode 100644
index 0000000000..7ec1e9775a
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/dsdt.asl
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20181031 /* OEM Revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/haswell/acpi/hostbridge.asl>
+ #include <southbridge/intel/lynxpoint/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
new file mode 100644
index 0000000000..173f2f1d0d
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
@@ -0,0 +1,18 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/optiplex_9020/gpio.c b/src/mainboard/dell/optiplex_9020/gpio.c
new file mode 100644
index 0000000000..48b7707e2c
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/gpio.c
@@ -0,0 +1,217 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_GPIO,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_NATIVE,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_NATIVE,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_GPIO,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_GPIO,
+ .gpio26 = GPIO_MODE_GPIO,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_NATIVE,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio11 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_OUTPUT,
+ .gpio15 = GPIO_DIR_OUTPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_OUTPUT,
+ .gpio23 = GPIO_DIR_OUTPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio25 = GPIO_DIR_OUTPUT,
+ .gpio26 = GPIO_DIR_OUTPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio13 = GPIO_LEVEL_LOW,
+ .gpio15 = GPIO_LEVEL_HIGH,
+ .gpio22 = GPIO_LEVEL_HIGH,
+ .gpio23 = GPIO_LEVEL_HIGH,
+ .gpio25 = GPIO_LEVEL_HIGH,
+ .gpio26 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+ .gpio18 = GPIO_BLINK,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio8 = GPIO_INVERT,
+ .gpio9 = GPIO_INVERT,
+ .gpio11 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio26 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_GPIO,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_NATIVE,
+ .gpio37 = GPIO_MODE_NATIVE,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_GPIO,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio32 = GPIO_DIR_INPUT,
+ .gpio33 = GPIO_DIR_OUTPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio44 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio46 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_OUTPUT,
+ .gpio53 = GPIO_DIR_OUTPUT,
+ .gpio54 = GPIO_DIR_OUTPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio57 = GPIO_DIR_OUTPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio33 = GPIO_LEVEL_HIGH,
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_HIGH,
+ .gpio52 = GPIO_LEVEL_HIGH,
+ .gpio53 = GPIO_LEVEL_HIGH,
+ .gpio54 = GPIO_LEVEL_HIGH,
+ .gpio55 = GPIO_LEVEL_HIGH,
+ .gpio57 = GPIO_LEVEL_HIGH,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_GPIO,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_GPIO,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_GPIO,
+ .gpio73 = GPIO_MODE_GPIO,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio64 = GPIO_DIR_OUTPUT,
+ .gpio66 = GPIO_DIR_OUTPUT,
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio72 = GPIO_DIR_OUTPUT,
+ .gpio73 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+ .gpio64 = GPIO_LEVEL_HIGH,
+ .gpio66 = GPIO_LEVEL_HIGH,
+ .gpio72 = GPIO_LEVEL_HIGH,
+ .gpio74 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/optiplex_9020/hda_verb.c b/src/mainboard/dell/optiplex_9020/hda_verb.c
new file mode 100644
index 0000000000..df43ade3e6
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/hda_verb.c
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0280, /* Realtek ALC3220 */
+ 0x102805a5, /* Subsystem ID */
+ 13, /* Number of entries */
+ AZALIA_SUBVENDOR(0, 0x102805a5),
+ AZALIA_PIN_CFG(0, 0x12, 0x4008c000),
+ AZALIA_PIN_CFG(0, 0x13, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x15, 0x0221401f),
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x18, 0x01a13040),
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
+ AZALIA_PIN_CFG(0, 0x1a, 0x02a19030),
+ AZALIA_PIN_CFG(0, 0x1b, 0x01014020),
+ AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
new file mode 100644
index 0000000000..c834fea5d3
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+
+static void mainboard_enable(struct device *dev)
+{
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
new file mode 100644
index 0000000000..90205c2d68
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+chip northbridge/intel/haswell
+ device domain 0 on
+ chip southbridge/intel/lynxpoint
+ device pci 1c.1 on end # PCI (via XIO2001 bridge)
+ device pci 1c.2 on end # PCIe 1x slot
+ end
+ end
+end
diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c
new file mode 100644
index 0000000000..2b9cdaa5fd
--- /dev/null
+++ b/src/mainboard/dell/optiplex_9020/romstage.c
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+
+void mainboard_config_rcba(void)
+{
+ RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQC, PIRQD, PIRQA);
+ RCBA16(D29IR) = DIR_ROUTE(PIRQC, PIRQA, PIRQD, PIRQH);
+ RCBA16(D28IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
+ RCBA16(D27IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQG);
+ RCBA16(D26IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQF, PIRQA);
+ RCBA16(D25IR) = DIR_ROUTE(PIRQH, PIRQG, PIRQF, PIRQE);
+ RCBA16(D22IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQA);
+ RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
+}
+
+void mb_get_spd_map(struct spd_info *spdi)
+{
+ spdi->addresses[0] = 0x50;
+ spdi->addresses[1] = 0x51;
+ spdi->addresses[2] = 0x52;
+ spdi->addresses[3] = 0x53;
+}
+
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
+ /* Length, Enable, OCn#, Location */
+ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
+ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
+ {0x0040, 1, 1, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 2, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 3, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 3, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 0, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 0, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 4, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 4, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 5, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 5, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 6, USB_PORT_BACK_PANEL},
+ {0x0040, 1, 7, USB_PORT_BACK_PANEL},
+};
+
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
+ /* Enable, OCn# */
+ {1, 6},
+ {1, 7},
+ {0, USB_OC_PIN_SKIP},
+ {0, USB_OC_PIN_SKIP},
+ {1, 1},
+ {1, 2},
+};
--
2.39.2
@@ -0,0 +1,37 @@
From c25cf16fb0d278354c7e2c19f534a04e27ac46dd Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 21 Apr 2025 05:14:45 +0100
Subject: [PATCH 32/41] Conditional TBFW setting for kabylake thinkpads
Otherwise, other boards will define it, which
might trigger the vendor download script, and
lead to a non-zero exit.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/Kconfig | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
index 512b326381..b2c7763198 100644
--- a/src/mainboard/lenovo/Kconfig
+++ b/src/mainboard/lenovo/Kconfig
@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY
string
default MAINBOARD_PART_NUMBER
+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580
+
config LENOVO_TBFW_BIN
string "Lenovo ThunderBolt firmware bin file"
default ""
@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN
Just leave this blank if you don't care about this option. It's not
useful for every ThinkPad, only certain models.
+endif # BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580
+
endif # VENDOR_LENOVO
--
2.47.3
@@ -1,774 +0,0 @@
From 41002e64c92e90903fa591c4a8a1cc0108833743 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 26 Nov 2023 17:08:52 -0700
Subject: [PATCH] mb/dell: Add Latitude E6420 (Sandy Bridge)
Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6420/Kconfig | 38 ++++
src/mainboard/dell/e6420/Kconfig.name | 2 +
src/mainboard/dell/e6420/Makefile.inc | 6 +
src/mainboard/dell/e6420/acpi/ec.asl | 9 +
src/mainboard/dell/e6420/acpi/platform.asl | 12 ++
src/mainboard/dell/e6420/acpi/superio.asl | 3 +
src/mainboard/dell/e6420/acpi_tables.c | 16 ++
src/mainboard/dell/e6420/board_info.txt | 6 +
src/mainboard/dell/e6420/cmos.default | 9 +
src/mainboard/dell/e6420/cmos.layout | 88 ++++++++++
src/mainboard/dell/e6420/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e6420/devicetree.cb | 66 +++++++
src/mainboard/dell/e6420/dsdt.asl | 30 ++++
src/mainboard/dell/e6420/early_init.c | 32 ++++
src/mainboard/dell/e6420/gma-mainboard.ads | 20 +++
src/mainboard/dell/e6420/gpio.c | 191 +++++++++++++++++++++
src/mainboard/dell/e6420/hda_verb.c | 33 ++++
src/mainboard/dell/e6420/mainboard.c | 21 +++
18 files changed, 582 insertions(+)
create mode 100644 src/mainboard/dell/e6420/Kconfig
create mode 100644 src/mainboard/dell/e6420/Kconfig.name
create mode 100644 src/mainboard/dell/e6420/Makefile.inc
create mode 100644 src/mainboard/dell/e6420/acpi/ec.asl
create mode 100644 src/mainboard/dell/e6420/acpi/platform.asl
create mode 100644 src/mainboard/dell/e6420/acpi/superio.asl
create mode 100644 src/mainboard/dell/e6420/acpi_tables.c
create mode 100644 src/mainboard/dell/e6420/board_info.txt
create mode 100644 src/mainboard/dell/e6420/cmos.default
create mode 100644 src/mainboard/dell/e6420/cmos.layout
create mode 100644 src/mainboard/dell/e6420/data.vbt
create mode 100644 src/mainboard/dell/e6420/devicetree.cb
create mode 100644 src/mainboard/dell/e6420/dsdt.asl
create mode 100644 src/mainboard/dell/e6420/early_init.c
create mode 100644 src/mainboard/dell/e6420/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e6420/gpio.c
create mode 100644 src/mainboard/dell/e6420/hda_verb.c
create mode 100644 src/mainboard/dell/e6420/mainboard.c
diff --git a/src/mainboard/dell/e6420/Kconfig b/src/mainboard/dell/e6420/Kconfig
new file mode 100644
index 0000000000..cff62bf70c
--- /dev/null
+++ b/src/mainboard/dell/e6420/Kconfig
@@ -0,0 +1,38 @@
+if BOARD_DELL_LATITUDE_E6420
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_10240
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e6420"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E6420"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0126"
+
+endif # BOARD_DELL_LATITUDE_E6420
diff --git a/src/mainboard/dell/e6420/Kconfig.name b/src/mainboard/dell/e6420/Kconfig.name
new file mode 100644
index 0000000000..1722891e7b
--- /dev/null
+++ b/src/mainboard/dell/e6420/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6420
+ bool "Latitude E6420"
diff --git a/src/mainboard/dell/e6420/Makefile.inc b/src/mainboard/dell/e6420/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e6420/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6420/acpi/ec.asl b/src/mainboard/dell/e6420/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e6420/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6420/acpi/platform.asl b/src/mainboard/dell/e6420/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e6420/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6420/acpi/superio.asl b/src/mainboard/dell/e6420/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e6420/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e6420/acpi_tables.c b/src/mainboard/dell/e6420/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e6420/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e6420/board_info.txt b/src/mainboard/dell/e6420/board_info.txt
new file mode 100644
index 0000000000..34d5ad9e0b
--- /dev/null
+++ b/src/mainboard/dell/e6420/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/dell/e6420/cmos.default b/src/mainboard/dell/e6420/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e6420/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e6420/cmos.layout b/src/mainboard/dell/e6420/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e6420/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e6420/data.vbt b/src/mainboard/dell/e6420/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd
GIT binary patch
literal 6144
zcmeHKeQZ-z6hE);wSBvNZ|mO1=*HLC2BQN8uVX6{N9eY)75ORymb$R8!YYuAZEgeE
zKk|S@Fen*n41W-viAF;r%)~^EkpLz-B{2q##)LmGAtoY;7*Qhv_1yPbw$TC$2}G0K
z=6Ao&x#ym9?z!i_&TOh(kLzky2cN8MTpny#R<;VU4Rkn?rBIz(YL~BBw<%b&zGhSH
z$~AQ>@D0d=Xx6RE0BwSxspWdrW9y<FZGD@&x3_JL;p$p!;!BVdcKLkht0=-%(Jj&T
z_GkyztZ%>#t7^)^(T-R<7W?O6ZTI%A+j=`<Jw3Q%dk6N!da<_?7oyiU3)^<~_TiSk
zE$y+=RK3PGQ`gzmXYPRBx>C|f*UP9{h|4>ANrAe~?ymV*)83AaT#FuTjP=C2cg5P~
zt4w78r$t#300cWY_k)mevmAmFI3&oBfytoAAPQiYK$XEIgHwV@5-gJ-Q-*p8yfTDj
zaDz=1Y!X1B3`OpQ&Ik}bM|0xHn0gYNZw0rT=7AXS2in-q8K^?)0|el+Z6geW7i7MM
zv~!|>HqL-|Fk}EYOa@)R<X)VQ7c}d8R1b@RTn5rq(90|QRg0?wwZZz(6Dz}w>zg9Y
z8;!mD_V*XSjT33~$`o`s>zEGBq8AQ`HaH?y!Fh2QiX1v@aCo4LaENf&DZ_cE2A2qb
z5@cC}X)=S^1RvpXLWs~v*hqMau$!=t@B-mg!XV)|;eEm>!Z6`H;R4|&!d1d`f|S7^
zli+B98*!TfPE&6~NVM5j3v{N3OTjpnm_L@BPh(}esd(J!gj?~iJP?n|OZZOiTqlql
zg<NWR@g&-*W-E%A7|*1Z_`sVO$K&iAP+VIj9{<1hT%SXsK}IBk8!daftR`6-)EUiS
zvv*HR(#-ZwhA~7wcmxbe4%E?Y7P0y{1q|nqR1L29UR8v@#No^g5MH)7!>{%-$T|cR
zZx5|xm>Fl>;@$m};P{0WC>O~<Nl1`*PLgPN_hP2a^h+L$ls&SYrkDYr+&l*%%S?^Q
ziPSdtHE<LNEnr7cs=ihL-C>-p>*$9CpHRLgN|POkqD^UP4nw|4nf0bc8MOBk<;%js
zfpCAWNzqSPlz@X%j9CGrwZDKUl@K{g6pzqiIIARDQ)#@^RW&0pmNG;XZ?!SlHB?L#
zKRAMgq(R;aQd%@Gy38-LS@ix)fR**(P3B9wI=Uk^&cWmmwB<vf21<0#LBA!;qtAh(
zYe5g_T{+gw^mi8QzPPraBoH~8oCz%r=$nVi1A)`Y8IKqIdqm6MihqxtpFaTggaPxu
zQP07nf#&kPkPp}Cmk$F1g7q7QK;kz~80i&oDN}~wYbPUI6AtG5H+$T!@f5FzUhp21
z^XiPT3rb%B@sA9g!n88R7BOsLS|?+D3}0v3dyIX|@JFWo&e%<c#V)PV#g@7-=F*;V
zvAr&Q+ogTvVxPM3XP5Smi`f;Nt7uCU)}Y`HMcbpW=M_AuXlE35PQl+4O{7m66&I@7
zGL@}Sai^*sP}va`KTx$VRQ8REf2*1+lTFH0=UkNx+eN|1rVyipl)Du=h=@%w+iQZG
zT6@-PdW^oyFb44AG`HMZWEnP{&OQ+jC`N4emoS)x;EPN}uaSFOf-Mn8JRRO&LTWJc
zn6%=L94~PR)%Ua_HTZcfTXD<p{%8p|<N<;Efw$Zb4$}{m8@7c((~<7^thaau&@Wx#
zVGNL)lmH@{o=h*{muXGc!;nXrVgpp3;1V1stMj=4AtxyzX+?SoB~zN}!*r?9Qvs1P
zmV_(CTmt0sY&6=F=_M>E34GYvuh1uQF+BUdWyQC5SaEM1QvKlHBMs13C}n{0SwRxW
ziekMa&kvRFruRcKCevGy5)TxUBDlur@E{TtQ^NQ>nO+Cgl)&Ga(PxqVW?e3TLH-UY
zdL3T{z^xdd`$(STFUb8R*cKa}r>n{Wk+MXRH~o-hN}#9OF*>T#>rfhiRs(Wc-R^9@
z%F=<}dn(E}ADc03zJ>JvZe;_8f+WFLL4%qNYs`_aa`a$Pl5H;iO^Wt*cP3W(d=(g}
zZ%nKT1$|r-tAv8($u2-BI2Uiz#%OT&!Q3b~Ru2P2j;Gem!@wfPsTR%J>W{8z)oq^J
k^Qm&?O@bFkw4CTocwoW<6CRlGz=Q`TJTT#bN9KWl0rH4|j{pDw
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e6420/devicetree.cb b/src/mainboard/dell/e6420/devicetree.cb
new file mode 100644
index 0000000000..f9259f7175
--- /dev/null
+++ b/src/mainboard/dell/e6420/devicetree.cb
@@ -0,0 +1,66 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x0000054f"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x0493 inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 on end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x007c0901"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x001c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3b"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe on end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp2 on end
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 on end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e6420/dsdt.asl b/src/mainboard/dell/e6420/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e6420/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e6420/early_init.c b/src/mainboard/dell/e6420/early_init.c
new file mode 100644
index 0000000000..0682441ed6
--- /dev/null
+++ b/src/mainboard/dell/e6420/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 0, 6 },
+ { 1, 0, 7 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e6420/gma-mainboard.ads b/src/mainboard/dell/e6420/gma-mainboard.ads
new file mode 100644
index 0000000000..2a16f44360
--- /dev/null
+++ b/src/mainboard/dell/e6420/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, -- mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6420/gpio.c b/src/mainboard/dell/e6420/gpio.c
new file mode 100644
index 0000000000..943c743f48
--- /dev/null
+++ b/src/mainboard/dell/e6420/gpio.c
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+ .gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e6420/hda_verb.c b/src/mainboard/dell/e6420/hda_verb.c
new file mode 100644
index 0000000000..b3803b7c65
--- /dev/null
+++ b/src/mainboard/dell/e6420/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x10280493, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280493),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6420/mainboard.c b/src/mainboard/dell/e6420/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e6420/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.43.0
@@ -1,773 +0,0 @@
From 5e8bff81220d4d0f663feed443e4594b76e442bf Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 31 Jan 2024 22:07:25 -0700
Subject: [PATCH] mb/dell: Add Latitude E6520 (Sandy Bridge)
Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6520/Kconfig | 38 +++++
src/mainboard/dell/e6520/Kconfig.name | 2 +
src/mainboard/dell/e6520/Makefile.inc | 6 +
src/mainboard/dell/e6520/acpi/ec.asl | 9 +
src/mainboard/dell/e6520/acpi/platform.asl | 12 ++
src/mainboard/dell/e6520/acpi/superio.asl | 3 +
src/mainboard/dell/e6520/acpi_tables.c | 16 ++
src/mainboard/dell/e6520/board_info.txt | 6 +
src/mainboard/dell/e6520/cmos.default | 9 +
src/mainboard/dell/e6520/cmos.layout | 88 ++++++++++
src/mainboard/dell/e6520/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e6520/devicetree.cb | 66 +++++++
src/mainboard/dell/e6520/dsdt.asl | 30 ++++
src/mainboard/dell/e6520/early_init.c | 32 ++++
src/mainboard/dell/e6520/gma-mainboard.ads | 20 +++
src/mainboard/dell/e6520/gpio.c | 190 +++++++++++++++++++++
src/mainboard/dell/e6520/hda_verb.c | 33 ++++
src/mainboard/dell/e6520/mainboard.c | 21 +++
18 files changed, 581 insertions(+)
create mode 100644 src/mainboard/dell/e6520/Kconfig
create mode 100644 src/mainboard/dell/e6520/Kconfig.name
create mode 100644 src/mainboard/dell/e6520/Makefile.inc
create mode 100644 src/mainboard/dell/e6520/acpi/ec.asl
create mode 100644 src/mainboard/dell/e6520/acpi/platform.asl
create mode 100644 src/mainboard/dell/e6520/acpi/superio.asl
create mode 100644 src/mainboard/dell/e6520/acpi_tables.c
create mode 100644 src/mainboard/dell/e6520/board_info.txt
create mode 100644 src/mainboard/dell/e6520/cmos.default
create mode 100644 src/mainboard/dell/e6520/cmos.layout
create mode 100644 src/mainboard/dell/e6520/data.vbt
create mode 100644 src/mainboard/dell/e6520/devicetree.cb
create mode 100644 src/mainboard/dell/e6520/dsdt.asl
create mode 100644 src/mainboard/dell/e6520/early_init.c
create mode 100644 src/mainboard/dell/e6520/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e6520/gpio.c
create mode 100644 src/mainboard/dell/e6520/hda_verb.c
create mode 100644 src/mainboard/dell/e6520/mainboard.c
diff --git a/src/mainboard/dell/e6520/Kconfig b/src/mainboard/dell/e6520/Kconfig
new file mode 100644
index 0000000000..db9f25b4ac
--- /dev/null
+++ b/src/mainboard/dell/e6520/Kconfig
@@ -0,0 +1,38 @@
+if BOARD_DELL_LATITUDE_E6520
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_10240
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e6520"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E6520"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0116"
+
+endif # BOARD_DELL_LATITUDE_E6520
diff --git a/src/mainboard/dell/e6520/Kconfig.name b/src/mainboard/dell/e6520/Kconfig.name
new file mode 100644
index 0000000000..25968e80e5
--- /dev/null
+++ b/src/mainboard/dell/e6520/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6520
+ bool "Latitude E6520"
diff --git a/src/mainboard/dell/e6520/Makefile.inc b/src/mainboard/dell/e6520/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e6520/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6520/acpi/ec.asl b/src/mainboard/dell/e6520/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e6520/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6520/acpi/platform.asl b/src/mainboard/dell/e6520/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e6520/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6520/acpi/superio.asl b/src/mainboard/dell/e6520/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e6520/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e6520/acpi_tables.c b/src/mainboard/dell/e6520/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e6520/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e6520/board_info.txt b/src/mainboard/dell/e6520/board_info.txt
new file mode 100644
index 0000000000..34d5ad9e0b
--- /dev/null
+++ b/src/mainboard/dell/e6520/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/dell/e6520/cmos.default b/src/mainboard/dell/e6520/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e6520/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e6520/cmos.layout b/src/mainboard/dell/e6520/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e6520/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e6520/data.vbt b/src/mainboard/dell/e6520/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
GIT binary patch
literal 6144
zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN)
z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y
z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+
z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7
zcXx+--0R}IwzW3-+`f2k?^Av5V7MpRO-q(9rn_R1@Xlz2Ztdy`$Gf6^w6~|bKi!!7
z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ
z)4V8f0Gt`D`+>9Fr~tnJ76EJ`5D_F1cn-`0$RgN9unI6kfYkzIiO?W`ON4+34lv1_
zNdPDkq1cf$p8^EW;TS*O$CdzNo#1fbIG_Oi0T(ti0jwyt0le_p_HlvX^CFvr)>$b>
zO-z8^CSU`w=mIK7Q)@9fR;XUzrFu{T=rRyygIZBpU9+Or>+?4R9%~G?Y-|g)Z`Sti
z+do(U*Wb-xR~DzjS<75#=Us4sH^C9U2FCbND7L7u$>M|<;t=AnRfI9C0v8c~AVg7t
zIU<3D2oK^>L;%r(*o=4*u?Mja@dDyi#4zFn;(f#^#3*76aUSs#;tJv#La-6YLRdQB
zdcvfERkvH?k~GJlfM<HR476j(@nfm+47<!Ult@^ua5M3h6A}q=C0ognX9aX4mxq)U
zXOhm=DbLene?C%_16Q)2NRV@Yacz`D;{V>Ve-1?&ZXy}n)YwnVAgNlz#zX;=IX)-F
z)9LL3lbEdY5Co)LsK?vP)7s}G(5xduE!Y!#Wgh<IN3(3ey=-oWU(9aEJ_HzV53Jbq
zj5B5RjzLUt>_T&xi$uUA#0e}X3D~`J(bHz;DgTa@GrpW6=>eZwJeNYYo*GjF=``;(
zuoQ3|V5YoKd$j=KK{`uSX*DeU1oJg=+RT6)rLe6%2>Ci^!5ao=*gS}wFN=nUf`fTF
zM?Gb5ycWjM7I?MJ!2;w|LFg=UoLq-ytr2iemG)AsW}bI4X9PK}T5UKsQi7anu=tD6
zf|={kXkNeQBD>6bQ3taC8XJOJ^e40_ydyfr&a41L^1)jNrK<B_wV}+ZE`p;QK=rDz
zTw`SJ+e`Oc*icaF4INF51Xg*~ts@m)@9ETt(*@N7yy0)Ddce%i9{^k2kbd8=Wns~P
zWBD$~himxDharxF@f!ti^0$~9Zxt{tg`@Dbl_0Ki2Xp_MEw-<z6qgep;XYmR%Dl-F
z%3cBfcN;Avikpz-gmw_6mymu!Unk0YgnUfsk3{*6kQ;=S*p(_fS!JhDyYh^k?6uRk
z?8--W@~NHvY*+ra6SG9iC1s^V)<|@Rqzp*pd5NBslrs`JC(&Oeg~v}CnJ$x+)iP<8
z=`LA0Ad@39{XkZ}kjXbP{YzHtS!70*yy%LcnJ#cz4u%*Wq!^d*AVMZdr&l=#Qgik~
ze2l)cX+!kF9EaFhY;0^Uo_#VNC?7K2Tf=ZR1y5);b!mCGG?<cc#M0rtHKYeKi%BE?
z@Y6|P8fx#li}c`Uv24UGyZaM0To;Ep<_AWZA1t~bFgI)uf}&Eq=L_Cs89=>wnT0Vx
z-jp>o1ffJNommZ4?=TIPlePIw0hgQ706f*tBC`#pg>9&zRHe>J2%RxBTrOc6Adh9E
ziJr`?VQH!N!_GkoKaoq|+3$^Ae0#sUxXlmM1Huq~g<=Ls?ILv+nQcH%PQedGOlH=Q
z77rMcJlH4Mkc#U2(IDv>rsm1aHpsdL_RdT^i_ACcQUMIJcSus}*(?CIiy^#^=t=g1
z+*^Zbh30&^#_bKclSy9pL$<B~pK8m*sLpIdnHM@W$nA7Ea@Z`x27K?aNK<@lCW(2L
zb@kB3H8kKy4W3Hu)NN|kd!DL^o#iR9a{QYV-Wl&r&hmIFX{ezkIV<4zFiVUQ@K>ao
z00DnFy~Uek!JRwhVX!of0)$Sa*X^S~LMQH0<E(UUx}L=|;Kgw(r(4q=nD)T52c|tR
O?SW|zOncy=dEg(6JAK&z
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e6520/devicetree.cb b/src/mainboard/dell/e6520/devicetree.cb
new file mode 100644
index 0000000000..cfba8ef4e7
--- /dev/null
+++ b/src/mainboard/dell/e6520/devicetree.cb
@@ -0,0 +1,66 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x0494 inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 on end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x007c0901"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x001c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3b"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe on end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp2 on end
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 on end
+ device ref pcie_rp5 off end
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 off end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e6520/dsdt.asl b/src/mainboard/dell/e6520/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e6520/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e6520/early_init.c b/src/mainboard/dell/e6520/early_init.c
new file mode 100644
index 0000000000..2a37091df6
--- /dev/null
+++ b/src/mainboard/dell/e6520/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 0, 3 },
+ { 1, 0, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 0, 6 },
+ { 1, 0, 7 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e6520/gma-mainboard.ads b/src/mainboard/dell/e6520/gma-mainboard.ads
new file mode 100644
index 0000000000..2a16f44360
--- /dev/null
+++ b/src/mainboard/dell/e6520/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, -- mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6520/gpio.c b/src/mainboard/dell/e6520/gpio.c
new file mode 100644
index 0000000000..61f01816c4
--- /dev/null
+++ b/src/mainboard/dell/e6520/gpio.c
@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_NATIVE,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio49 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e6520/hda_verb.c b/src/mainboard/dell/e6520/hda_verb.c
new file mode 100644
index 0000000000..d33eb3b4c5
--- /dev/null
+++ b/src/mainboard/dell/e6520/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x10280494, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280494),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6520/mainboard.c b/src/mainboard/dell/e6520/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e6520/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.43.0
@@ -0,0 +1,30 @@
From 2c3a31547a14eb1b1145a5d153289b2eef6d71d8 Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Sat, 27 Sep 2025 23:30:46 +0300
Subject: [PATCH 33/41] soc/intel/alderlake: Disable
MRC_CACHE_USING_MRC_VERSION
There's some issue with building against the FSP headers in src/vendorcode.
Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing
from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force.
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
---
src/soc/intel/alderlake/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 97c2ecca70..a2074fe05a 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE
select INTEL_GMA_VERSION_2
select INTEL_TXT_LIB
select MP_SERVICES_PPI_V2
- select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO
select MRC_SETTINGS_PROTECT
select PARALLEL_MP_AP_WORK
select PLATFORM_USES_FSP2_2
--
2.47.3
@@ -0,0 +1,76 @@
From 8eeb1de057b19938f1221b85e00699c58de90069 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 28 Sep 2025 03:17:50 +0100
Subject: [PATCH 34/41] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks)
if you pass -k (keep fptr modules), don't use -r, don't
use -t, you can essentially just use me_cleaner to
extract a ME image without changing it. this is useful
when for example, you just want to set the HAP bit.
however, me_cleaner still performs a FPTR check.
on some newer ME versions, it's always invalid according
to me_cleaner, because for example it doesn't handle
ME16 very well yet.
this patch adds an option to override the FPTR check
either pass -p or --pass-fptr
NOTE: we probably won't use this on coreboot's me_cleaner,
which is the corna version. we only need it on the newer
me_cleaner versions for e.g. ME16, on certain setups.
still, it's best to have the patch here too, just in case.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/me_cleaner/me_cleaner.py | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py
index fae5e56732..228bac899f 100755
--- a/util/me_cleaner/me_cleaner.py
+++ b/util/me_cleaner/me_cleaner.py
@@ -246,8 +246,10 @@ def check_partition_signature(f, offset):
return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME
-def print_check_partition_signature(f, offset):
- if check_partition_signature(f, offset):
+def print_check_partition_signature(f, offset, pass_fptr):
+ if pass_fptr:
+ print("Skipping FPTR checks because the user told us to")
+ elif check_partition_signature(f, offset):
print("VALID")
else:
print("INVALID!!")
@@ -486,6 +488,8 @@ if __name__ == "__main__":
"--extract-me)", action="store_true")
parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR "
"modules, even when possible", action="store_true")
+ parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks"
+ "regardless of other operations", action="store_true")
bw_list.add_argument("-w", "--whitelist", metavar="whitelist",
help="Comma separated list of additional partitions "
"to keep in the final image. This can be used to "
@@ -871,12 +875,14 @@ if __name__ == "__main__":
print("Checking the FTPR RSA signature of the extracted ME "
"image... ", end="")
print_check_partition_signature(mef_copy,
- ftpr_offset + ftpr_mn2_offset)
+ ftpr_offset + ftpr_mn2_offset,
+ args.pass_fptr)
mef_copy.close()
if not me6_ignition:
print("Checking the FTPR RSA signature... ", end="")
- print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset)
+ print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset,
+ args.pass_fptr)
f.close()
--
2.47.3
@@ -1,780 +0,0 @@
From 86911e57c556389eed386bc23d5e87dd520afec9 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 31 Jan 2024 22:57:07 -0700
Subject: [PATCH] mb/dell: Add Latitude E5530 (Ivy Bridge)
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e5530/Kconfig | 37 ++++
src/mainboard/dell/e5530/Kconfig.name | 2 +
src/mainboard/dell/e5530/Makefile.inc | 6 +
src/mainboard/dell/e5530/acpi/ec.asl | 9 +
src/mainboard/dell/e5530/acpi/platform.asl | 12 ++
src/mainboard/dell/e5530/acpi/superio.asl | 3 +
src/mainboard/dell/e5530/acpi_tables.c | 16 ++
src/mainboard/dell/e5530/board_info.txt | 6 +
src/mainboard/dell/e5530/cmos.default | 9 +
src/mainboard/dell/e5530/cmos.layout | 88 ++++++++++
src/mainboard/dell/e5530/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e5530/devicetree.cb | 70 ++++++++
src/mainboard/dell/e5530/dsdt.asl | 30 ++++
src/mainboard/dell/e5530/early_init.c | 32 ++++
src/mainboard/dell/e5530/gma-mainboard.ads | 20 +++
src/mainboard/dell/e5530/gpio.c | 194 +++++++++++++++++++++
src/mainboard/dell/e5530/hda_verb.c | 33 ++++
src/mainboard/dell/e5530/mainboard.c | 21 +++
18 files changed, 588 insertions(+)
create mode 100644 src/mainboard/dell/e5530/Kconfig
create mode 100644 src/mainboard/dell/e5530/Kconfig.name
create mode 100644 src/mainboard/dell/e5530/Makefile.inc
create mode 100644 src/mainboard/dell/e5530/acpi/ec.asl
create mode 100644 src/mainboard/dell/e5530/acpi/platform.asl
create mode 100644 src/mainboard/dell/e5530/acpi/superio.asl
create mode 100644 src/mainboard/dell/e5530/acpi_tables.c
create mode 100644 src/mainboard/dell/e5530/board_info.txt
create mode 100644 src/mainboard/dell/e5530/cmos.default
create mode 100644 src/mainboard/dell/e5530/cmos.layout
create mode 100644 src/mainboard/dell/e5530/data.vbt
create mode 100644 src/mainboard/dell/e5530/devicetree.cb
create mode 100644 src/mainboard/dell/e5530/dsdt.asl
create mode 100644 src/mainboard/dell/e5530/early_init.c
create mode 100644 src/mainboard/dell/e5530/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e5530/gpio.c
create mode 100644 src/mainboard/dell/e5530/hda_verb.c
create mode 100644 src/mainboard/dell/e5530/mainboard.c
diff --git a/src/mainboard/dell/e5530/Kconfig b/src/mainboard/dell/e5530/Kconfig
new file mode 100644
index 0000000000..3faae4ee50
--- /dev/null
+++ b/src/mainboard/dell/e5530/Kconfig
@@ -0,0 +1,37 @@
+if BOARD_DELL_LATITUDE_E5530
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e5530"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E5530"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0166"
+
+endif # BOARD_DELL_LATITUDE_E5530
diff --git a/src/mainboard/dell/e5530/Kconfig.name b/src/mainboard/dell/e5530/Kconfig.name
new file mode 100644
index 0000000000..775963204a
--- /dev/null
+++ b/src/mainboard/dell/e5530/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E5530
+ bool "Latitude E5530"
diff --git a/src/mainboard/dell/e5530/Makefile.inc b/src/mainboard/dell/e5530/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e5530/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e5530/acpi/ec.asl b/src/mainboard/dell/e5530/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e5530/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e5530/acpi/platform.asl b/src/mainboard/dell/e5530/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e5530/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e5530/acpi/superio.asl b/src/mainboard/dell/e5530/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e5530/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e5530/acpi_tables.c b/src/mainboard/dell/e5530/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e5530/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e5530/board_info.txt b/src/mainboard/dell/e5530/board_info.txt
new file mode 100644
index 0000000000..4601a4aaba
--- /dev/null
+++ b/src/mainboard/dell/e5530/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/dell/e5530/cmos.default b/src/mainboard/dell/e5530/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e5530/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e5530/cmos.layout b/src/mainboard/dell/e5530/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e5530/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e5530/data.vbt b/src/mainboard/dell/e5530/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3
GIT binary patch
literal 6144
zcmeHKU2Gdg5dO}0w$JA~+qs02q)iz56C9e5vuQ#oL0l3O+%|395Q2peO{y4(2uX0t
zuMja1N)bPb1cE+5)fYsCK!89MFQAGChyWpk5PuR<K|G+sLmxmOR4}u5=Rg`mj70g7
zvgdDic6N4dW^QKhynd)>kS^cR)3#-(r*-?zo-O^C(kLvv8XM<+Y3tdt^YY!P?!oTe
zJ^ed-x6w0Lh5fN#jsv5TWE#mtd*_yky}9xDK(kOwLt+C7_AQAd#iwr=o0`gvQZ`{x
z6ZeT`x^^;8+a~jSa^o~PF@8J6N5;o#dhCwebaM;!_oisw1#O9K={qQM<@Oeu$lXeN
z#wJGcW4Y<2)-A{Bot(NoKX%>qdnw-AOi9bKT9Z~HL5|7PJDHz4kGlEx143q+26EH6
z{4KfB^9;?<fTOaiNPy%=@LovL&q<^d1Qdi+Xex9SvIM^ZLq%9cP{A1rE>#dw(WfA;
zBCR3@pCS1a;A|CZW1h7H*l#mW{%y{bf)9ofiz!EHzyiac@{RpMzz>O-<~{hx5tw%b
z3ZJWD4_g-`iF`tUJb}+Vfe;XI1T2Y4_Y!iVk<<T4ce(^PWKh<?N^a`t+}vgNr25iZ
z`!fTBL)ojYF5G?3y|eW=`9>MLB9et&!A7LDDE7&5ye#|hn%s#IWgagDEPNHHMUhb-
ztc9t?uz{bD#kh#kpsE;AO-wWHV?4olPStRPag^~k<737bjBgm<GlC%vRgBe)4U9I%
zg^XUtcE**A5ylOSn;A2V2N;hso?--U#>t|ufS}_`LGs2bcSKCVBh4s0>G7ZR_@NWx
zkph}GhP}~YR?roT!61GqzQ?gBsuv3jY}UXbmr|alv^VxUqbz5<`5=!hhpaa*7DK~4
zP4ad6dhH!>nYpc4{J&G-w{UiWo$zXnTz{tAq0|?c_`QJ7pKmCwIpe7Uix$P?9}v*1
z(aVR6OkMkQ6oM}*UC@j78!~>7=OZCVYXeu|u0SiI4}w$uw6&0P09LF%Hp}O&IA3gl
z4@ap0NfAe+q(ZVm{Bwe*Do~kbCc$Q!x7b3Sk9tLgVmsR<Q4H=9Nl;mmf2xpY<*d*-
z`yI_BR#`La=Oxxt#qgS`3pER^nh^CZ%*qlq2N9@uSAtz-C7AhduB_U|{>#oOrY`tq
z%|?L!zRd2-$V6^@$H<Mj3MXf#F<J+^8%<X2{tnmQTI*aK*ageBrm9^|<Ked3j_s;%
zva<(Dob)BOwdcj8Z67UhYUAjbk==Of9W#D7k!DJobLx$$fXD_wuZyD&Kk-$EIY~S`
zan1ANbFUW8hZ0pUw5)y??*}!;chdgq|0X5;s;m`@YdY{zs4z#z8e;13T6b4tC7gy$
zTwszEQhk0!U$`3=Qi)ZbY^*|bAyvF>@ml^iaX;uzoVB3JA(|h9tcNKXHdA43N0|18
z&3$2QE=)(l=6qQDAWT1oO-<KoblR+&{kk@!)1A8ch^`&b>2=+FU)Mg<35IDJ+8Tp;
z40F)Xt}$rVFdsLxLk7KRn4cKhmj<a3vp%A&kI>eLd38j)HbM_Y%!3i_aD?8An8za8
z@d(AD=Gv&%5;e{}p%i?_q(T*^IwzEx*Eu1wKHV9=lVUvjqv!B@cWER!2fe%`IqO?q
z!=Wf4kzGUaLX8`m#*P^uL?%M#6qc9Qu(YT|ZMb#7UzCc_(DkQYEG<G&Q*QkX`CS`I
z8cwQnl8A#CMH~W79L&{2*Jof_MD5t{bPTAszWUa20yPzD=*wW8)wHSu?avDhffu^!
zL>Q#%k_O0@^DN5S@MXi$D;acJ>#cTV-(U@Offv4ACp4hO4$Ll!WO)s3P4=t9vpWBC
zSckhlcD?xUuX=Gx96Dx{IsQ23r&;o1*+^Cp2RA3nd$A-RIHP2Q7uitC>c67FIR*5}
zB3a%B!?6K=TJ$W+SJv@*9Lms{mTvWmU4Zanj_Z*lSqOGISzYp?yawOqLhVhRt#-E6
zd)YW~h&meh-5prIE}Cr&7f?MMi&cqTt_^%Fa?>k(=`9jVoIf@}{g+WX#TpWuc+!2v
zPG^>A|NZ2GlGsKdGqN{7>Fr7+Hc_^3z}uBhC4?nzOQ*!QyVugGjkK_~$bvtfY`h79
z9rOI3;Mt}9)_G{zXTAPw`8T@6=Ut0r9R5;0#Zy|#8F;v4^UAmqft3iXL|`QXD-l?U
Jz~2*rUjdP?m;3+#
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e5530/devicetree.cb b/src/mainboard/dell/e5530/devicetree.cb
new file mode 100644
index 0000000000..2af748cf27
--- /dev/null
+++ b/src/mainboard/dell/e5530/devicetree.cb
@@ -0,0 +1,70 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00000000"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x03d003d0"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x053d inherit
+
+ device ref host_bridge on end
+ device ref peg10 off end
+ device ref igd on end
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x005c0921"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end
+ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe off end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end # WWAN Slot
+ device ref pcie_rp2 on end # SLAN Slot
+ device ref pcie_rp3 on end # ExpressCard
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 on end # Extra Half Mini PCIe slot
+ device ref pcie_rp6 on end # SD/MMC Card Reader
+ device ref pcie_rp7 on end # BCM5761 Ethernet
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e5530/dsdt.asl b/src/mainboard/dell/e5530/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e5530/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e5530/early_init.c b/src/mainboard/dell/e5530/early_init.c
new file mode 100644
index 0000000000..00fd5f6795
--- /dev/null
+++ b/src/mainboard/dell/e5530/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 0, 3 },
+ { 1, 2, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 0, 6 },
+ { 1, 1, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e5530/gma-mainboard.ads b/src/mainboard/dell/e5530/gma-mainboard.ads
new file mode 100644
index 0000000000..1310830c8e
--- /dev/null
+++ b/src/mainboard/dell/e5530/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, --mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e5530/gpio.c b/src/mainboard/dell/e5530/gpio.c
new file mode 100644
index 0000000000..0599f13921
--- /dev/null
+++ b/src/mainboard/dell/e5530/gpio.c
@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e5530/hda_verb.c b/src/mainboard/dell/e5530/hda_verb.c
new file mode 100644
index 0000000000..4c7c36ee05
--- /dev/null
+++ b/src/mainboard/dell/e5530/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x1028053d, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x1028053d),
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e5530/mainboard.c b/src/mainboard/dell/e5530/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e5530/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.43.0
@@ -1,41 +0,0 @@
From b2cf0657a2058118baf6f4ec96e356de3c9e493e Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Sun, 11 Feb 2024 19:02:20 +0200
Subject: [PATCH] hp8560w: Add MXM System Infomation Structure
Change-Id: I45b421f2d7baf8ca8dedbd3b1ab1e38392b6219b
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
---
src/mainboard/hp/snb_ivb_laptops/Makefile.mk | 6 ++++++
.../hp/snb_ivb_laptops/variants/8560w/mxm-30-sis | Bin 0 -> 129 bytes
2 files changed, 6 insertions(+)
create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
index c007bb68cd..7950abbc4e 100644
--- a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
+++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
@@ -9,3 +9,9 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb
# FIXME: Other variants with same size onboard RAM may exist.
SPD_SOURCES = hynix_4g
+
+ifeq ($(CONFIG_BOARD_HP_8560W),y)
+cbfs-files-y += mxm-30-sis
+mxm-30-sis-file := variants/$(VARIANT_DIR)/mxm-30-sis
+mxm-30-sis-type := raw
+endif
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
new file mode 100644
index 0000000000000000000000000000000000000000..7e4e245a50d8d5d36ddb22e3b1aed3fa87a2f57d
GIT binary patch
literal 129
zcmeZ`@Qr6?sAMn@-0}aX9Rou`%?mKiz;Fq|&xF!hw;=rNM_^h3Dy{$(SAdE$zF=lx
o@?l{RW{6;7W}LwIl$Vj2apDSgHUS2PJFE;0Kxqas5d=FN0HAs+0RR91
literal 0
HcmV?d00001
--
2.43.1
@@ -1,775 +0,0 @@
From 7c7ce2087e1ff5f0eedb65793254163d01be3056 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Wed, 7 Feb 2024 10:23:38 -0700
Subject: [PATCH] mb/dell: Add Latitude E5520 (Sandybridge)
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e5520/Kconfig | 37 ++++
src/mainboard/dell/e5520/Kconfig.name | 2 +
src/mainboard/dell/e5520/Makefile.inc | 5 +
src/mainboard/dell/e5520/acpi/ec.asl | 9 +
src/mainboard/dell/e5520/acpi/platform.asl | 12 ++
src/mainboard/dell/e5520/acpi/superio.asl | 3 +
src/mainboard/dell/e5520/acpi_tables.c | 16 ++
src/mainboard/dell/e5520/board_info.txt | 6 +
src/mainboard/dell/e5520/cmos.default | 9 +
src/mainboard/dell/e5520/cmos.layout | 88 ++++++++++
src/mainboard/dell/e5520/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e5520/devicetree.cb | 66 +++++++
src/mainboard/dell/e5520/dsdt.asl | 30 ++++
src/mainboard/dell/e5520/early_init.c | 32 ++++
src/mainboard/dell/e5520/gma-mainboard.ads | 20 +++
src/mainboard/dell/e5520/gpio.c | 195 +++++++++++++++++++++
src/mainboard/dell/e5520/hda_verb.c | 33 ++++
src/mainboard/dell/e5520/mainboard.c | 21 +++
18 files changed, 584 insertions(+)
create mode 100644 src/mainboard/dell/e5520/Kconfig
create mode 100644 src/mainboard/dell/e5520/Kconfig.name
create mode 100644 src/mainboard/dell/e5520/Makefile.inc
create mode 100644 src/mainboard/dell/e5520/acpi/ec.asl
create mode 100644 src/mainboard/dell/e5520/acpi/platform.asl
create mode 100644 src/mainboard/dell/e5520/acpi/superio.asl
create mode 100644 src/mainboard/dell/e5520/acpi_tables.c
create mode 100644 src/mainboard/dell/e5520/board_info.txt
create mode 100644 src/mainboard/dell/e5520/cmos.default
create mode 100644 src/mainboard/dell/e5520/cmos.layout
create mode 100644 src/mainboard/dell/e5520/data.vbt
create mode 100644 src/mainboard/dell/e5520/devicetree.cb
create mode 100644 src/mainboard/dell/e5520/dsdt.asl
create mode 100644 src/mainboard/dell/e5520/early_init.c
create mode 100644 src/mainboard/dell/e5520/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e5520/gpio.c
create mode 100644 src/mainboard/dell/e5520/hda_verb.c
create mode 100644 src/mainboard/dell/e5520/mainboard.c
diff --git a/src/mainboard/dell/e5520/Kconfig b/src/mainboard/dell/e5520/Kconfig
new file mode 100644
index 0000000000..213c54cf5c
--- /dev/null
+++ b/src/mainboard/dell/e5520/Kconfig
@@ -0,0 +1,37 @@
+if BOARD_DELL_LATITUDE_E5520
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_6144
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_BD82X6X
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config MAINBOARD_DIR
+ default "dell/e5520"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E5520"
+
+config USBDEBUG_HCD_INDEX
+ default 2
+
+config VGA_BIOS_ID
+ default "8086,0126"
+
+endif # BOARD_DELL_LATITUDE_E5520
diff --git a/src/mainboard/dell/e5520/Kconfig.name b/src/mainboard/dell/e5520/Kconfig.name
new file mode 100644
index 0000000000..c88913e8b3
--- /dev/null
+++ b/src/mainboard/dell/e5520/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E5520
+ bool "Latitude E5520"
diff --git a/src/mainboard/dell/e5520/Makefile.inc b/src/mainboard/dell/e5520/Makefile.inc
new file mode 100644
index 0000000000..18391d8b18
--- /dev/null
+++ b/src/mainboard/dell/e5520/Makefile.inc
@@ -0,0 +1,5 @@
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e5520/acpi/ec.asl b/src/mainboard/dell/e5520/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e5520/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e5520/acpi/platform.asl b/src/mainboard/dell/e5520/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e5520/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e5520/acpi/superio.asl b/src/mainboard/dell/e5520/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e5520/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e5520/acpi_tables.c b/src/mainboard/dell/e5520/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e5520/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e5520/board_info.txt b/src/mainboard/dell/e5520/board_info.txt
new file mode 100644
index 0000000000..34d5ad9e0b
--- /dev/null
+++ b/src/mainboard/dell/e5520/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2011
diff --git a/src/mainboard/dell/e5520/cmos.default b/src/mainboard/dell/e5520/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e5520/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e5520/cmos.layout b/src/mainboard/dell/e5520/cmos.layout
new file mode 100644
index 0000000000..1aa7e77bce
--- /dev/null
+++ b/src/mainboard/dell/e5520/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+414 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e5520/data.vbt b/src/mainboard/dell/e5520/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729
GIT binary patch
literal 6144
zcmeHKZ){Ul6hE);wSBvNZ|mL$bmQOM2BTvXUI!}^N9ejTij1vnu+)Wx6<c9(Y_%K6
zzOV-@f<ehpWB5RHBpMBgG7}RuMuM2=l*E{6G$wq&gqTQ3#E2RZsOP@dvW*rP7>Fjj
z&F`Lj?>YC}bI(2Z+}C+6zKyiGrosQXuW7A+&1%<rN+Y1ck(}dLrx)Ma#^x>lnvFGE
zeD#gB>*#Tq4&j^|7Xcz1r^pp*)g#T}u1Me3ct>Pgls5Qi3!6e2W0%`a-Ic|3efWuR
zXJ@#}wJyGMTXTcY<%@TBKh@(3hP$Gjv}E}rx-%9D_eLXhYe!c&-VyDg-Cdo1>Biji
zNNsnlFW#|jdoOj?mZ43m>cVO%UE9@*E7x|%V~c4`XD4l9GCi~@+7pfMibfX8L?!^I
zc~Rg1I5SxH1DAEZ0{jA41jrJBh#-l;b6^%g7QrThRe)&%tQH_!ggOD7A_PRRgGuI0
z0zi=n#rCB66d-sO$M~^6wgeb$2fH1|0R`v}xUiWCU`4SF;Dyh&j|mK&6WJWJ&Pq9I
zVgmFQfh+)vE}(KWwHA|Oh3fSkss|;2E(2i}s1?gRRV%8!K7U={vHD=s#+Fd)W^M1j
z{R4$??VSvEWpgT=vCM&1-U$bI6CB~IV3Z$$Vv7o!EDnev4j~R(MHsazZ~^fLLKGF4
zEfQFOa3dZ?1Q1P#&4?!vyAk^k&m&$z3?WV+-b0*1j37o4=MX<3E+eiYge(Ht2umAW
zOPDmU>UL{flI9u|@JtVvfp#o8ek?VfVV9YP5(%pnZX~{PKq4WoWGmV8t$=Ri@{zLQ
zNYYt4<$0Ry&qIoG;7s-t333)Nu8opN{NG!)&!I@eO(cVx8vBVEBvotJ7%yNl$7iQ_
zI=xk30+V$ff`F6<wRoF(TK%j9nsr#H23umU%)_7jNOl%*FPU567qbg;4gtp711nj2
z#+kHw`v4|5cA+`UMIvAl;slnH1nl0v=xH<al>1}ljxDE1dcda^&!do|r^eJkI?aC-
zEQMSfm?<w*Unzumkj_w5>VYL6W4=aCiy4rk%xq~5LV?bi|GL2$G7li<%c7yd;6T34
zQBN5huZ3~6`ChGkpb$Bg5ITb#2iK-qs|1`=sl6Dhn(Lj&8Agt?S{sTDmmtRj7Jm_1
zFnt{w&FdFkWS3bl>OeL?eO+*i{)9G!cSI-InGt|U0eEYmRCOHm7|I;#LO8ksRIeJ#
zGe+jTwPg4C4TYuN(9zULV3k+hI$YuPo=%N8oZ#u_4S!3Xelt6N0BmuC`hCNeg+&97
z6*!>)uHvr%2004GZv?!_-y&|TRmil=9D%Q`1aXBsnD^gov3*UZI34&1_vn(B=T4kZ
z_A>ClXVIBNaS^hd&^DrU6VgZMYeadMkdFxcktn|ra-Gl;n^I{bt86rCQ=YMry*B!$
zP5ID9KDE)GZOY#^VwPyRq^y+48j0?ZlzxdkC()CV@`*&wO7vGr;qjA3rb}gIwM-gi
zx>HsT$mEDj-<OpyWb%zn|B@A3Hkp<!FT5;hrt_SZiy?*wDaIu{h>%Ir=@rh7)SR;b
zAEWQGv_X1)wq0y5Ha0c~&psIsln<Hiu3;#Lf;%*eI<@?p8cfMJV(IYi8q$NA#iS8`
z_~|4t4b^wtMSAeFST^F8-Tm<zu8D&j^8=&I4;I}Im>aeSK~X8*^Z9SE44_`P#KIUL
zf6^N2f>5HCPWM3N+f0MyWOV^kz~!-wVc4MRXOY>4Jsxd1RyBKEMzNf{RKhesKFdbq
zJ(*d<l2Y#n?E?~iBA39P?~Pr2d#}5=#Sfl-VGzGUF$4U2KcqCIVlwkC(&7PQk_X!a
z8}3Jgq-&U*Co|h1>l)ZQGyW_x->i#;FvQ*=Nv&nG0N5@D@jjv_Q}K}6MP?1A6`JGe
zDwj9pN+x;T4>`I9e5x(uqdK#OGB31ikk@Xv=dxLb4fx(;ktX@rOb~M~?dYQQYiPia
z8r;jUQ?sd2@3||-cb2Eb%JFYfxHsONoaJ^eqoKN{<g9?-%`7oWz+aJS0tEc!^d@hD
z1-I{%hr!Y?0uVZpUbl__37xn@jkD6Z>3SATgBQlEoN7&ZV9Eni9+>jLln16fFy(=V
H=7E0zE^L4Z
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e5520/devicetree.cb b/src/mainboard/dell/e5520/devicetree.cb
new file mode 100644
index 0000000000..bef96ac14c
--- /dev/null
+++ b/src/mainboard/dell/e5520/devicetree.cb
@@ -0,0 +1,66 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00000218"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x049a inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 on end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x007c0901"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x001c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x3b"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+
+ device ref mei1 off end
+ device ref mei2 off end
+ device ref me_ide_r off end
+ device ref me_kt off end
+ device ref gbe off end
+ device ref ehci2 on end
+ device ref hda on end
+ device ref pcie_rp1 on end
+ device ref pcie_rp2 on end
+ device ref pcie_rp3 on end
+ device ref pcie_rp4 off end
+ device ref pcie_rp5 on end
+ device ref pcie_rp6 on end
+ device ref pcie_rp7 on end
+ device ref pcie_rp8 off end
+ device ref ehci1 on end
+ device ref pci_bridge off end
+ device ref lpc on
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end
+ device ref smbus on end
+ device ref sata2 off end
+ device ref thermal off end
+ end
+ end
+end
diff --git a/src/mainboard/dell/e5520/dsdt.asl b/src/mainboard/dell/e5520/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e5520/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e5520/early_init.c b/src/mainboard/dell/e5520/early_init.c
new file mode 100644
index 0000000000..7297921546
--- /dev/null
+++ b/src/mainboard/dell/e5520/early_init.c
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 1, 7 },
+ { 1, 1, 6 },
+ { 1, 1, 6 },
+ { 1, 1, 7 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+ | COMB_LPC_EN | COMA_LPC_EN);
+ mec5035_early_init();
+}
diff --git a/src/mainboard/dell/e5520/gma-mainboard.ads b/src/mainboard/dell/e5520/gma-mainboard.ads
new file mode 100644
index 0000000000..2a16f44360
--- /dev/null
+++ b/src/mainboard/dell/e5520/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, -- mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e5520/gpio.c b/src/mainboard/dell/e5520/gpio.c
new file mode 100644
index 0000000000..f76b93d9f0
--- /dev/null
+++ b/src/mainboard/dell/e5520/gpio.c
@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_NATIVE,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_GPIO,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_GPIO,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio12 = GPIO_DIR_OUTPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+ .gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio12 = GPIO_LEVEL_HIGH,
+ .gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_GPIO,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_NATIVE,
+ .gpio50 = GPIO_MODE_GPIO,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_GPIO,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_OUTPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio46 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio50 = GPIO_DIR_OUTPUT,
+ .gpio51 = GPIO_DIR_OUTPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio55 = GPIO_DIR_OUTPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_LOW,
+ .gpio37 = GPIO_LEVEL_LOW,
+ .gpio46 = GPIO_LEVEL_HIGH,
+ .gpio50 = GPIO_LEVEL_HIGH,
+ .gpio51 = GPIO_LEVEL_LOW,
+ .gpio55 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_NATIVE,
+ .gpio69 = GPIO_MODE_NATIVE,
+ .gpio70 = GPIO_MODE_NATIVE,
+ .gpio71 = GPIO_MODE_NATIVE,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_GPIO,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e5520/hda_verb.c b/src/mainboard/dell/e5520/hda_verb.c
new file mode 100644
index 0000000000..e2efee3646
--- /dev/null
+++ b/src/mainboard/dell/e5520/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
+ 0x1028049a, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x1028049a),
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e5520/mainboard.c b/src/mainboard/dell/e5520/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e5520/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.43.0
@@ -0,0 +1,35 @@
From be79f8b72a098dcd51639210935ba02d2f5ff808 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sat, 4 Oct 2025 21:57:43 +0100
Subject: [PATCH 35/41] soc/intel/alderlake: Don't compress FSP-S
Build systems like lbmk need to reproducibly insert
certain vendor files on release images.
Compression isn't always reproducible, and making it
so costs a lot more time than simply disabling compression.
With this change, FSP-S uses slightly more space inside
the flash, but it's not that much.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/alderlake/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index a2074fe05a..08137d2706 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE
select DRAM_SUPPORT_DDR5
select DRIVERS_USB_ACPI
select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
- select FSP_COMPRESS_FSP_S_LZ4
+# select FSP_COMPRESS_FSP_S_LZ4
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
select FSP_M_XIP
select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN
--
2.47.3
@@ -0,0 +1,33 @@
From 226df168b34467ca8555e953b6d793f273c0b82c Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sat, 4 Oct 2025 22:20:11 +0100
Subject: [PATCH 36/41] alderlake: don't require full fsp repo for fd path
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/alderlake/Kconfig | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 08137d2706..67e47c2e36 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -417,7 +417,14 @@ config FSP_HEADER_PATH
config FSP_FD_PATH
string
- depends on FSP_USE_REPO
+# dependency removed for lbmk purposes, so that the path is present
+# in the config regardless of whether it's used. this is for ./mk -d
+# on alderlake boards, which is used by lbmk to manually split fsp,
+# even though the result is identical to what coreboot produces, because
+# this enables lbmk to strip the fsp in release archives, and re-insert
+# for compliance reasons (due to technicalities in intel's licensing),
+# and to enable lbmk's advanced checksum verification of vendor files
+# depends on FSP_USE_REPO
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P
--
2.47.3
@@ -0,0 +1,46 @@
From 30366be45e5b7521b93475f68c7143bd683b25f3 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 6 Oct 2025 04:47:06 +0100
Subject: [PATCH 37/41] soc/alderlake: disable stack overflow debug option
same as on other boards. based on this commit:
commit 51cc2bacb6b07279b97e9934d079060475481fb6
Author: Subrata Banik <subratabanik@google.com>
Author: Subrata Banik <subratabanik@google.com>
Date: Fri Dec 13 13:07:28 2024 +0530
soc/intel/pantherlake: Disable stack overflow debug options
yeah, i've been replicating this change per platform.
we do alderlake now in libreboot, so let's set that here too.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/alderlake/Kconfig | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 67e47c2e36..e9c56fc6b9 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -331,6 +331,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ
int
default 19200000
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
+ bool
+ default n
+
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
+ bool
+ default n
+
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
int
default 133
--
2.47.3
@@ -0,0 +1,92 @@
From 90332fe96aca0de4d99d58d1593048c77e1bdecf Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 11 May 2025 15:41:22 -0600
Subject: [PATCH 38/41] ec/dell/mec5035: Add command to disable EC-initiated
thermal shutdown
If command 0xBF isn't sent, the EC shuts down the system without warning
as soon as the CPU temperature reaches about 87 degrees, without letting
the CPU thermal throttle to try and reduce the temperature. With vendor
firmware, the CPU is able to reach around 100 degrees before thermal
throttling.
This command was found by collecting EC commands by logging the LPC bus
while running with vendor firmware and then replaying observed commands
from coreboot. By systematically replaying subsets of commands in a
binary search pattern and then stress testing the system, the command to
disable the shutdown was isolated.
The exact meaning of the parameters for this command are unknown at this
time, but do seem to differ between different generations of these
laptops. Due to this, the commmand should be called by mainboard
specific code which passes the specific parameter value used.
The Google Wilco EC code, which runs on Latitude Chromebooks and shares
many commands with the standard Latitude ECs, suggests that command 0xBF
tells the EC about the processors CPUID. However, the values observed in
LPC bus logs do not seem to correspond with any CPUID values on the
non-Chromebook systems I tested.
Observed command parameter values (sent on mailbox registers 2-4):
- E6430 (Ivy Bridge): 0x07, 0x00, 0x00
- M6800 (Haswell): 0x14, 0x00, 0x00
Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++
src/ec/dell/mec5035/mec5035.h | 2 ++
2 files changed, 21 insertions(+)
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index c5067c16f6..b316fa4989 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -114,6 +114,25 @@ void mec5035_sleep_enable(void)
ec_command(CMD_SLEEP_ENABLE);
}
+void mec5035_cmd_bf(u8 i)
+{
+ /*
+ * If this command isn't sent, the EC shuts down the system as soon as
+ * the CPU temperature reaches about 87 degrees. It is unknown exactly
+ * what the parameters represent. The Google Wilco EC code, which runs
+ * on Latitude Chromebooks and shares some commands with the standard
+ * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but
+ * the values observed in LPC bus logs don't seem to match any CPUID
+ * values of the normal Latitudes this was tested with.
+ * Observed i values:
+ * - E6430 (Ivy Bridge): 0x7
+ * - M6800 (Haswell): 0x14
+ */
+ u8 buf[3] = {i, 0, 0};
+ write_mailbox_regs(buf, 2, 3);
+ ec_command(CMD_BF);
+}
+
void mec5035_early_init(void)
{
/* If this isn't sent the EC shuts down the system after about 15
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index 5cd907bf71..71d1a71075 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -14,6 +14,7 @@ enum mec5035_cmd {
CMD_POWER_BUTTON_TO_HOST = 0x3e,
CMD_ACPI_WAKEUP_CHANGE = 0x4a,
CMD_SLEEP_ENABLE = 0x64,
+ CMD_BF = 0xbf,
CMD_CPU_OK = 0xc2,
};
@@ -65,5 +66,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change);
void mec5035_sleep_enable(void);
void mec5035_smi_sleep(int slp_type);
+void mec5035_cmd_bf(u8 i);
#endif /* _EC_DELL_MEC5035_H_ */
--
2.47.3
@@ -0,0 +1,36 @@
From 68048f4afe369ece02143f9a4a7da2104ff2d10b Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 11 May 2025 16:28:23 -0600
Subject: [PATCH 39/41] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown
at 87 degrees
If command 0xBF isn't sent, the EC will shut down the system without
warning once the CPU reaches approximately 87 degrees, without the
system thermal throttling first. Call the newly added function from the
MEC5035 code to send this command and disable this behavior.
Tested on the Latitude E6430.
Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c
index ff83db095b..ef385a0a70 100644
--- a/src/mainboard/dell/snb_ivb_latitude/early_init.c
+++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c
@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void)
| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
| COMB_LPC_EN | COMA_LPC_EN);
mec5035_early_init();
+
+ /* Observed from LPC logs with vendor firmware. Seems to disable
+ * EC-initiated shutdown when the CPU reaches approximately 87 degrees.
+ * The exact meaning of the parameter is currently unknown. */
+ mec5035_cmd_bf(0x07);
}
--
2.47.3
@@ -0,0 +1,28 @@
From 6e084398d4e6847b0f64325dadd4cfee0b43d7ea Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sat, 20 Dec 2025 20:12:48 +0100
Subject: [PATCH 1/1] fix ifdtool build
not my mistake. someone messed up.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index ea8dfc788d..33f00436bc 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -2598,7 +2598,7 @@ int main(int argc, char *argv[])
}
mode_nuke = 1;
break;
- Case 'v':
+ case 'v':
print_version();
exit(EXIT_SUCCESS);
break;
--
2.47.3
@@ -0,0 +1,30 @@
From ca27517cb5752d078a3f8328ff6b220f652b0849 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sat, 20 Dec 2025 22:36:18 +0100
Subject: [PATCH 1/1] tests/Makefile.mk: use 3rdparty/cmocka by default
(tests)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
tests/Makefile.mk | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/tests/Makefile.mk b/tests/Makefile.mk
index f3f122dd38..33bb2a2d07 100644
--- a/tests/Makefile.mk
+++ b/tests/Makefile.mk
@@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage
endif
# Use system cmoka in default, or build from 3rdparty source code if requested
-USE_SYSTEM_CMOCKA ?= 1
+# PATCH NOTE: lbmk sets it to 0 by default. You can still override it to 1
+# if you wish; upstream sets this to 1 by default, but we do 0
+USE_SYSTEM_CMOCKA ?= 0
ifeq ($(USE_SYSTEM_CMOCKA),1)
ifeq ($(shell $(HOSTPKG_CONFIG) --exists cmocka || echo 1),1)
$(warning No system cmocka, build from 3rdparty instead...)
--
2.47.3
@@ -0,0 +1,51 @@
From 22076426d1de6d2e49b8728b3cf206bfcfc6742d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 23 Dec 2025 18:41:27 +0100
Subject: [PATCH 1/2] mb/dell/optiplex_780: use legacy HDA verb table
See:
commit 31fc5b06a6be62b30739d33eeabe6c2727679bb1
Author: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Thu Aug 7 08:31:24 2025 +0900
device: Introduce reworked azalia verb table
and:
commit 50a59d4464917503847eeeb2df4320c35cf2f6cc
Author: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Date: Mon Sep 15 16:25:21 2025 +0900
device: Add Kconfig to prepare for reworked verb table implementation
Without this change, lbmk gets the following error
when building for Dell OptiPlex 780:
i386-elf-ld.bfd: build/ramstage/device/azalia_device.o: in function `azalia_codecs_init':
/path/to/corebootclone/src/device/azalia_device.c:318:(.text.azalia_codecs_init+0xa): undefined reference to `mainboard_azalia_codecs'
This is a temporary fix. Upstream will require that the code
be fully adapted at a future date. Therefore, one could consider
the current functionality to be "deprecated".
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/optiplex_780/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
index fc649e35d5..172bb2fa87 100644
--- a/src/mainboard/dell/optiplex_780/Kconfig
+++ b/src/mainboard/dell/optiplex_780/Kconfig
@@ -2,6 +2,7 @@
config BOARD_DELL_OPTIPLEX_780_COMMON
def_bool n
+ select AZALIA_USE_LEGACY_VERB_TABLE
select BOARD_ROMSIZE_KB_8192
select CPU_INTEL_SOCKET_LGA775
select DRIVERS_I2C_CK505
--
2.47.3
@@ -0,0 +1,30 @@
From 6cea443cf12eb94b3eafcbba4ce6370b31f716cc Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 23 Dec 2025 18:46:45 +0100
Subject: [PATCH 2/2] hp8300cmt: use legacy verb table
same as for the 780 optiplex patch
coreboot is making some changes to the way verbs are
handled. for now, this change is being made to adapt.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/hp/compaq_elite_8300_cmt/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
index d2bfd35dc4..30be7fb3fe 100644
--- a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
@@ -2,6 +2,7 @@ if BOARD_HP_COMPAQ_ELITE_8300_CMT
config BOARD_SPECIFIC_OPTIONS
def_bool y
+ select AZALIA_USE_LEGACY_VERB_TABLE
select BOARD_ROMSIZE_KB_16384
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
--
2.47.3
@@ -0,0 +1,34 @@
From 3bb05d0486186400df8ed9ac66cfadcbff7a48a6 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 6 Jan 2026 21:42:21 +0000
Subject: [PATCH 1/1] topton x2e n150: use old fsp
i added the old fsp back, so that we didn't have to
mess around with vendor files in lbmk, because coreboot
upstream updated the fsp repo, which modified this
fsp file.
we know the old fsp worked. there's no point testing
the new one yet, unless someone can tell me about
real bugs that got fixed.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/soc/intel/alderlake/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index e9c56fc6b9..43cd6f8efe 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -438,6 +438,7 @@ config FSP_FD_PATH
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S
+ default "3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if BOARD_TOPTON_X2E_N150
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N
default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P
default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S
--
2.47.3
@@ -0,0 +1,31 @@
From 6c6b7a71bfb36f9639abe72066851de22aa4f1ca Mon Sep 17 00:00:00 2001
From: Ron Nazarov <ron@noisytoot.org>
Date: Sat, 14 Feb 2026 20:13:01 +0000
Subject: [PATCH] mb/supermicro/x11-lga1151-series: Disable ME HECI in
devicetree
Since we always use me_cleaner, this speeds up boot time by preventing
coreboot from wasting a few seconds waiting for HECI.
Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350
Signed-off-by: Ron Nazarov <ron@noisytoot.org>
---
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
index fbf896c6ae..aa09a41f2f 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
@@ -15,7 +15,7 @@ chip soc/intel/skylake
device ref sa_thermal on end
device ref south_xhci on end
device ref thermal on end
- device ref heci1 on end
+ device ref heci1 off end
device ref sata on
register "SataSalpSupport" = "1"
register "SataPortsEnable" = "{
--
2.52.0
+3 -1
View File
@@ -1,2 +1,4 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"
rev="fcd716d9a272461da1fdbaf1c048eb5a52c7896b"
@@ -1,203 +0,0 @@
From 4fbd327df271d613d4a56a36eafd88d9d642ec6b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
Subject: [PATCH 1/9] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
Example:
./ifdtool --nuke gbe coreboot.rom
./ifdtool --nuke bios coreboot.com
./ifdtool --nuke me coreboot.com
Rebased since the last revision update in lbmk.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
1 file changed, 81 insertions(+), 31 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 191b3216de..38132b4a28 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
" tgl - Tiger Lake\n"
" wbg - Wellsburg\n"
" -S | --setpchstrap Write a PCH strap\n"
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
"\n");
}
+static int
+get_region_type_string(const char *region_type_string)
+{
+ if (!strcasecmp("Descriptor", region_type_string))
+ return 0;
+ else if (!strcasecmp("BIOS", region_type_string))
+ return 1;
+ else if (!strcasecmp("ME", region_type_string))
+ return 2;
+ else if (!strcasecmp("GbE", region_type_string))
+ return 3;
+ else if (!strcasecmp("Platform Data", region_type_string))
+ return 4;
+ else if (!strcasecmp("Device Exp1", region_type_string))
+ return 5;
+ else if (!strcasecmp("Secondary BIOS", region_type_string))
+ return 6;
+ else if (!strcasecmp("Reserved", region_type_string))
+ return 7;
+ else if (!strcasecmp("EC", region_type_string))
+ return 8;
+ else if (!strcasecmp("Device Exp2", region_type_string))
+ return 9;
+ else if (!strcasecmp("IE", region_type_string))
+ return 10;
+ else if (!strcasecmp("10GbE_0", region_type_string))
+ return 11;
+ else if (!strcasecmp("10GbE_1", region_type_string))
+ return 12;
+ else if (!strcasecmp("PTT", region_type_string))
+ return 15;
+ return -1;
+}
+
+static void
+nuke(const char *filename, char *image, int size, int region_type)
+{
+ int i;
+ struct region region;
+ const struct frba *frba = find_frba(image, size);
+ if (!frba)
+ exit(EXIT_FAILURE);
+
+ region = get_region(frba, region_type);
+ if (region.size > 0) {
+ for (i = region.base; i <= region.limit; i++) {
+ if ((i + 1) > (size))
+ break;
+ image[i] = 0xFF;
+ }
+ write_image(filename, image, size);
+ }
+}
+
int main(int argc, char *argv[])
{
int opt, option_index = 0;
@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
+ int mode_nuke = 0;
int mode_gpr0_disable = 0;
char *region_type_string = NULL, *region_fname = NULL;
const char *layout_fname = NULL;
@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
{"validate", 0, NULL, 't'},
{"setpchstrap", 1, NULL, 'S'},
{"newvalue", 1, NULL, 'V'},
+ {"nuke", 1, NULL, 'N'},
{0, 0, 0, 0}
};
@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
region_fname++;
// Descriptor, BIOS, ME, GbE, Platform
// valid type?
- if (!strcasecmp("Descriptor", region_type_string))
- region_type = 0;
- else if (!strcasecmp("BIOS", region_type_string))
- region_type = 1;
- else if (!strcasecmp("ME", region_type_string))
- region_type = 2;
- else if (!strcasecmp("GbE", region_type_string))
- region_type = 3;
- else if (!strcasecmp("Platform Data", region_type_string))
- region_type = 4;
- else if (!strcasecmp("Device Exp1", region_type_string))
- region_type = 5;
- else if (!strcasecmp("Secondary BIOS", region_type_string))
- region_type = 6;
- else if (!strcasecmp("Reserved", region_type_string))
- region_type = 7;
- else if (!strcasecmp("EC", region_type_string))
- region_type = 8;
- else if (!strcasecmp("Device Exp2", region_type_string))
- region_type = 9;
- else if (!strcasecmp("IE", region_type_string))
- region_type = 10;
- else if (!strcasecmp("10GbE_0", region_type_string))
- region_type = 11;
- else if (!strcasecmp("10GbE_1", region_type_string))
- region_type = 12;
- else if (!strcasecmp("PTT", region_type_string))
- region_type = 15;
- if (region_type == -1) {
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
fprintf(stderr, "No such region type: '%s'\n\n",
region_type_string);
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
case 't':
mode_validate = 1;
break;
+ case 'N':
+ region_type_string = strdup(optarg);
+ if (!region_type_string) {
+ fprintf(stderr, "No region specified\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
+ fprintf(stderr, "No such region type: '%s'\n\n",
+ region_type_string);
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ mode_nuke = 1;
+ break;
case 'v':
print_version();
exit(EXIT_SUCCESS);
@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
- mode_gpr0_disable) > 1) {
+ mode_gpr0_disable + mode_nuke) > 1) {
fprintf(stderr, "You may not specify more than one mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
- mode_validate + mode_gpr0_disable) == 0) {
+ mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
fprintf(stderr, "You need to specify a mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
write_image(new_filename, image, size);
}
+ if (mode_nuke) {
+ nuke(new_filename, image, size, region_type);
+ }
+
if (mode_altmedisable) {
struct fpsba *fpsba = find_fpsba(image, size);
struct fmsba *fmsba = find_fmsba(image, size);
--
2.39.2
@@ -1,47 +0,0 @@
From 362e86f89b3980699e7e794df9b98018397fe2d8 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 2/9] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
Enabling PECI without microcode updates loaded causes the CPUID feature set
to become corrupted. And one consequence is broken SpeedStep. At least, that's
my understanding looking at Intel Errata. This revert is not a fix, because
upstream is correct (upstream assumes microcode updates). We will simply
maintain this revert patch in Libreboot, from now on.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 315e7c36fc..1423fd72bc 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
}
-#define IA32_PECI_CTL 0x5a0
-
static void configure_misc(const int eist, const int tm2, const int emttm)
{
msr_t msr;
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
}
-
- /* Enable PECI
- WARNING: due to Erratum AW67 described in Intel document #318733
- the microcode must be updated before this MSR is written to. */
- msr = rdmsr(IA32_PECI_CTL);
- msr.lo |= 1;
- wrmsr(IA32_PECI_CTL, msr);
}
#define PIC_SENS_CFG 0x1aa
--
2.39.2
@@ -1,173 +0,0 @@
From 883455573f07551eaf2b12ab80bedcd2b4904a17 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
Subject: [PATCH 3/9] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
While this fix is *technically correct*, the one in
coreboot, it breaks rebooting as tested on several
GM45 ThinkPads e.g. X200, T400, when microcode
updates are not applied.
Since November 2022, Libreboot includes microcode
updates by default, but it tells users how to remove
it from the ROM (with cbfstool) if they wish.
Well, with Libreboot 20221214, 20230319 and 20230413,
mitigations present in Libreboot 20220710 (which did
not have microcode updates) do not exist.
This patch, along with the other patch to remove PECI
support (which breaks speedstep when microcode updates
are not applied) have now been re-added to Libreboot.
It is still best to use microcode updates by default.
These patches in coreboot are not critically urgent,
and you can use the machines with or without them,
regardless of ucode.
I'll probably re-write this and the other patch at
some point, applying the change conditionally upon
whether or not microcode is applied.
Pragmatism is a good thing. I recommend it.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
5 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 1423fd72bc..d1f98ca43a 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -8,6 +8,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
#define MSR_BBL_CR_CTL3 0x11e
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states(quad);
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index bc53214310..72f40f6762 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
smm_initialize();
}
-#define SMRR_SUPPORTED (1 << 11)
-
static void per_cpu_smm_trigger(void)
{
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
- set_feature_ctrl_vmx();
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
- /* We don't care if the lock is already setting
- as our smm relocation handler is able to handle
- setups where SMRR is not enabled here. */
- if (ia32_ft_ctrl.lo & (1 << 0)) {
- /* IA32_FEATURE_CONTROL locked. If we set it again we
- get an illegal instruction. */
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
- } else {
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
- printk(BIOS_INFO,
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
- }
- } else {
- set_vmx_and_lock();
- }
-
/* Relocate the SMM handler. */
smm_relocate();
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 05f5f327cc..0450c2ad83 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 5bd1c32815..f3bb08cde3 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 535fb8fae7..f7b05facd2 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
--
2.39.2
@@ -1,28 +0,0 @@
From 458fe39e9cd2536cfa8671427e6f557396143339 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
Subject: [PATCH 4/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6400/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
index bb954cbd7b..e9f3915d17 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
+++ b/src/mainboard/dell/e6400/devicetree.cb
@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
ops gm45_pci_domain_ops
device pci 00.0 on end # host bridge
- device pci 01.0 off end
+ device pci 01.0 on end
device pci 02.0 on end # VGA
device pci 02.1 on end # Display
device pci 03.0 on end # ME
--
2.39.2
@@ -1,39 +0,0 @@
From de4eeaf6d44cb05c60c0b0d54b43cdb88686b998 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 5/9] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
roms without a payload resulting in a no boot situation, but in
libreboot lbmk handles the payload and thus this warning always comes
up. This has caused confusion and concern so just patch it out.
---
payloads/Makefile.mk | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
index a2336aa876..4f1692a873 100644
--- a/payloads/Makefile.mk
+++ b/payloads/Makefile.mk
@@ -49,16 +49,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
-show_notices:: warn_no_payload
-endif
-
-warn_no_payload:
- printf "\n\t** WARNING **\n"
- printf "coreboot has been built without a payload. Writing\n"
- printf "a coreboot image without a payload to your board's\n"
- printf "flash chip will result in a non-booting system. You\n"
- printf "can use cbfstool to add a payload to the image.\n\n"
-
.PHONY: force-payload coreinfo nvramcui
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
2.39.2
@@ -1,39 +0,0 @@
From 261454e47783b973b088e9dbea47bda02758dcb4 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 22 Oct 2023 15:02:25 +0100
Subject: [PATCH 6/9] don't use github for the acpica download
i have the tarball from a previous download, and i placed
it on libreboot rsync, which then got mirrored to princeton.
today, github's ssl cert was b0rking the hell out and i really
really wanted to finish a build, and didn't want to wait for
github to fix their httpd.
so i'm now hosting this specific acpica tarball on rsync.
this patch makes that URL be used, instead of the github one.
that's the 2nd time i've had to patch coreboot's acpica download!
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 23a5caf2bb..36565a906c 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2
@@ -1,36 +0,0 @@
From 622daa7c46de01530de60a7be32c8b9e48b356fd Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 22:57:08 +0000
Subject: [PATCH 7/9] use mirrorservice.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 36565a906c..4d4ca06113 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
# to the jenkins build as well, or the builder won't download it.
# GCC toolchain archive locations
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2
@@ -1,23 +0,0 @@
From f318da0563ecb2386ac368e04bad88a8aacbc83d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Nov 2023 16:33:11 +0000
Subject: [PATCH 9/9] dell/e6400: crank up vram to 256MB (max)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6400/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
index eeb6f47364..25dfa38cb5 100644
--- a/src/mainboard/dell/e6400/cmos.default
+++ b/src/mainboard/dell/e6400/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Disable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.2
-4
View File
@@ -1,4 +0,0 @@
tree="dell"
tree_depend="default"
xtree="default"
rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"
@@ -0,0 +1,829 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
# CONFIG_NO_STAGE_CACHE is not set
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/sklkbl_desktops"
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=512
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
CONFIG_CBFS_SIZE=0xEEE000
CONFIG_CONSOLE_SERIAL=y
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
CONFIG_MAX_CPUS=16
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_UART_FOR_CONSOLE=0
CONFIG_VARIANT_DIR="optiplex_3050"
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
# CONFIG_VGA_BIOS is not set
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_PCIEXP_CLK_PM=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
# CONFIG_CONSOLE_POST is not set
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USE_PM_ACPI_TIMER=y
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_BOARD_DELL_E4300 is not set
# CONFIG_BOARD_DELL_E6400 is not set
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
CONFIG_BOARD_DELL_OPTIPLEX_3050=y
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
# CONFIG_BOARD_DELL_XPS_8300 is not set
CONFIG_BOARD_DELL_SKLKBL_DESKTOPS_COMMON=y
CONFIG_DCACHE_RAM_BASE=0xfef00000
CONFIG_DCACHE_RAM_SIZE=0x40000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
CONFIG_USE_LEGACY_8254_TIMER=y
# CONFIG_DEBUG_SMI is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
CONFIG_HAVE_IFD_BIN=y
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
CONFIG_TTYS0_BAUD=115200
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
CONFIG_D3COLD_SUPPORT=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
CONFIG_DRIVERS_UART_8250IO=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=16384
CONFIG_ROM_SIZE=0x01000000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_SMM_RESERVED_SIZE=0x200000
CONFIG_SMM_MODULE_STACK_SIZE=0x800
CONFIG_ACPI_BERT_SIZE=0x0
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
CONFIG_CPU_PT_ROM_MAP_GB=512
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_IFD_CHIPSET="sklkbl"
CONFIG_IED_REGION_SIZE=0x400000
CONFIG_MAX_ROOT_PORTS=24
CONFIG_PCR_BASE_ADDRESS=0xfd000000
CONFIG_CPU_BCLK_MHZ=100
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
CONFIG_CPU_XTAL_HZ=24000000
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
# CONFIG_ENABLE_SATA_TEST_MODE is not set
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_FSP_PUBLISH_MBP_HOB=y
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
CONFIG_MAX_HECI_DEVICES=5
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_HAVE_PAM0_REGISTER=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
CONFIG_SOC_INTEL_KABYLAKE=y
CONFIG_SKYLAKE_SOC_PCH_H=y
CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FSP_T_LOCATION=0xfffe0000
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_SOC_INTEL_COMMON=y
#
# Intel SoC Common Code for IP blocks
#
CONFIG_SOC_INTEL_COMMON_BLOCK=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
# CONFIG_USE_COREBOOT_MP_INIT is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
CONFIG_INTEL_CAR_NEM_ENHANCED=y
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
CONFIG_HAVE_HYPERTHREADING=y
# CONFIG_FSP_HYPERTHREADING is not set
# CONFIG_INTEL_KEYLOCKER is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
CONFIG_SOC_INTEL_CSE_RW_FILE=""
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
CONFIG_SA_ENABLE_DPR=y
CONFIG_HAVE_CAPID_A_REGISTER=y
CONFIG_HAVE_BDSM_BGSM_REGISTER=y
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
#
# Intel SoC Common PCH Code
#
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
#
# Intel SoC Common coreboot stages and non-IP blocks
#
CONFIG_SOC_INTEL_COMMON_BASECODE=y
CONFIG_SOC_INTEL_COMMON_RESET=y
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
CONFIG_PAVP=y
# CONFIG_MMA is not set
CONFIG_SOC_INTEL_COMMON_NHLT=y
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
#
# CPU
#
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_PARALLEL_MP=y
CONFIG_PARALLEL_MP_AP_WORK=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
#
# Southbridge
#
# CONFIG_PCIEXP_HOTPLUG is not set
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_SMSC_SCH555x=y
#
# Embedded Controllers
#
#
# Intel Firmware
#
CONFIG_HAVE_ME_BIN=y
# CONFIG_STITCH_ME_BIN is not set
# CONFIG_CHECK_ME is not set
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
# CONFIG_USE_ME_CLEANER is not set
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
CONFIG_UNLOCK_FLASH_REGIONS=y
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_UDK_BASE=y
CONFIG_UDK_2017_BINDING=y
CONFIG_UDK_2013_VERSION=2013
CONFIG_UDK_2017_VERSION=2017
CONFIG_UDK_202005_VERSION=202005
CONFIG_UDK_202111_VERSION=202111
CONFIG_UDK_202302_VERSION=202302
CONFIG_UDK_202305_VERSION=202305
CONFIG_UDK_VERSION=2017
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_HAVE_FSP_GOP=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_RUN_FSP_GOP is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y
# CONFIG_BOOTSPLASH is not set
CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y
# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set
# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set
# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_DRAM_SUPPORT_DDR4=y
CONFIG_DRAM_SUPPORT_DDR3=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
CONFIG_CACHE_MRC_SETTINGS=y
CONFIG_MRC_SETTINGS_PROTECT=y
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
# CONFIG_FSP_USE_REPO is not set
# CONFIG_DISPLAY_HOBS is not set
# CONFIG_DISPLAY_UPD_DATA is not set
CONFIG_PLATFORM_USES_FSP2_0=y
CONFIG_PLATFORM_USES_FSP2_X86_32=y
CONFIG_HAVE_INTEL_FSP_REPO=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_S_CBFS="fsps.bin"
CONFIG_FSP_M_CBFS="fspm.bin"
# CONFIG_FSP_FULL_FD is not set
CONFIG_FSP_T_RESERVED_SIZE=0x0
CONFIG_FSP_M_XIP=y
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
CONFIG_FSP_VGA_MODE12_BPP=0x0
CONFIG_INTEL_GMA_ACPI=y
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="Skylake"
CONFIG_GFX_GMA_PCH="Sunrise_Point"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
CONFIG_USE_PC_CMOS_ALTCENTURY=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_USB_ACPI=y
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_FW_VER=10
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
# end of Memory initialization
# CONFIG_STM is not set
# CONFIG_INTEL_CBNT_SUPPORT is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_CUSTOM_MADT=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_ACPI_LPIT=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
#
# I/O mapped, 8250-compatible
#
CONFIG_TTYS0_BASE=0x3f8
#
# Serial port base address = 0x3f8
#
# CONFIG_CONSOLE_SERIAL_921600 is not set
# CONFIG_CONSOLE_SERIAL_460800 is not set
# CONFIG_CONSOLE_SERIAL_230400 is not set
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_CONSOLE_SERIAL_57600 is not set
# CONFIG_CONSOLE_SERIAL_38400 is not set
# CONFIG_CONSOLE_SERIAL_19200 is not set
# CONFIG_CONSOLE_SERIAL_9600 is not set
CONFIG_TTYS0_LCS=3
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_CB=y
# end of Console
CONFIG_ACPI_S1_NOT_SUPPORTED=y
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_ACPI_NHLT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# Vendorcode Debug Settings
#
#
# BLOB Debug Settings
#
# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
# CONFIG_DISPLAY_FSP_HEADER is not set
# CONFIG_VERIFY_HOBS is not set
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
#
# General Debug Settings
#
# CONFIG_GDB_STUB is not set
CONFIG_HAVE_DEBUG_GPIO=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
@@ -0,0 +1,822 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
# CONFIG_NO_STAGE_CACHE is not set
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/sklkbl_desktops"
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=512
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
CONFIG_CBFS_SIZE=0xEEE000
CONFIG_CONSOLE_SERIAL=y
CONFIG_MAX_CPUS=16
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_UART_FOR_CONSOLE=0
CONFIG_VARIANT_DIR="optiplex_3050"
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
# CONFIG_VGA_BIOS is not set
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_PCIEXP_CLK_PM=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
# CONFIG_CONSOLE_POST is not set
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USE_PM_ACPI_TIMER=y
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_BOARD_DELL_E4300 is not set
# CONFIG_BOARD_DELL_E6400 is not set
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
CONFIG_BOARD_DELL_OPTIPLEX_3050=y
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
# CONFIG_BOARD_DELL_XPS_8300 is not set
CONFIG_BOARD_DELL_SKLKBL_DESKTOPS_COMMON=y
CONFIG_DCACHE_RAM_BASE=0xfef00000
CONFIG_DCACHE_RAM_SIZE=0x40000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
CONFIG_USE_LEGACY_8254_TIMER=y
# CONFIG_DEBUG_SMI is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
CONFIG_HAVE_IFD_BIN=y
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
CONFIG_TTYS0_BAUD=115200
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
CONFIG_D3COLD_SUPPORT=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
CONFIG_DRIVERS_UART_8250IO=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=16384
CONFIG_ROM_SIZE=0x01000000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_SMM_RESERVED_SIZE=0x200000
CONFIG_SMM_MODULE_STACK_SIZE=0x800
CONFIG_ACPI_BERT_SIZE=0x0
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
CONFIG_CPU_PT_ROM_MAP_GB=512
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_IFD_CHIPSET="sklkbl"
CONFIG_IED_REGION_SIZE=0x400000
CONFIG_MAX_ROOT_PORTS=24
CONFIG_PCR_BASE_ADDRESS=0xfd000000
CONFIG_CPU_BCLK_MHZ=100
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
CONFIG_CPU_XTAL_HZ=24000000
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
# CONFIG_ENABLE_SATA_TEST_MODE is not set
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_FSP_PUBLISH_MBP_HOB=y
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
CONFIG_MAX_HECI_DEVICES=5
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_HAVE_PAM0_REGISTER=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
CONFIG_SOC_INTEL_KABYLAKE=y
CONFIG_SKYLAKE_SOC_PCH_H=y
CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FSP_T_LOCATION=0xfffe0000
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_SOC_INTEL_COMMON=y
#
# Intel SoC Common Code for IP blocks
#
CONFIG_SOC_INTEL_COMMON_BLOCK=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
# CONFIG_USE_COREBOOT_MP_INIT is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
CONFIG_INTEL_CAR_NEM_ENHANCED=y
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
CONFIG_HAVE_HYPERTHREADING=y
# CONFIG_FSP_HYPERTHREADING is not set
# CONFIG_INTEL_KEYLOCKER is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
CONFIG_SOC_INTEL_CSE_RW_FILE=""
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
CONFIG_SA_ENABLE_DPR=y
CONFIG_HAVE_CAPID_A_REGISTER=y
CONFIG_HAVE_BDSM_BGSM_REGISTER=y
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
#
# Intel SoC Common PCH Code
#
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
#
# Intel SoC Common coreboot stages and non-IP blocks
#
CONFIG_SOC_INTEL_COMMON_BASECODE=y
CONFIG_SOC_INTEL_COMMON_RESET=y
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
CONFIG_PAVP=y
# CONFIG_MMA is not set
CONFIG_SOC_INTEL_COMMON_NHLT=y
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
#
# CPU
#
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_PARALLEL_MP=y
CONFIG_PARALLEL_MP_AP_WORK=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
#
# Southbridge
#
# CONFIG_PCIEXP_HOTPLUG is not set
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_SMSC_SCH555x=y
#
# Embedded Controllers
#
#
# Intel Firmware
#
CONFIG_HAVE_ME_BIN=y
# CONFIG_STITCH_ME_BIN is not set
# CONFIG_CHECK_ME is not set
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
# CONFIG_USE_ME_CLEANER is not set
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
CONFIG_UNLOCK_FLASH_REGIONS=y
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_UDK_BASE=y
CONFIG_UDK_2017_BINDING=y
CONFIG_UDK_2013_VERSION=2013
CONFIG_UDK_2017_VERSION=2017
CONFIG_UDK_202005_VERSION=202005
CONFIG_UDK_202111_VERSION=202111
CONFIG_UDK_202302_VERSION=202302
CONFIG_UDK_202305_VERSION=202305
CONFIG_UDK_VERSION=2017
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_HAVE_FSP_GOP=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_RUN_FSP_GOP is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_DRAM_SUPPORT_DDR4=y
CONFIG_DRAM_SUPPORT_DDR3=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
CONFIG_CACHE_MRC_SETTINGS=y
CONFIG_MRC_SETTINGS_PROTECT=y
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
# CONFIG_FSP_USE_REPO is not set
# CONFIG_DISPLAY_HOBS is not set
# CONFIG_DISPLAY_UPD_DATA is not set
CONFIG_PLATFORM_USES_FSP2_0=y
CONFIG_PLATFORM_USES_FSP2_X86_32=y
CONFIG_HAVE_INTEL_FSP_REPO=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_S_CBFS="fsps.bin"
CONFIG_FSP_M_CBFS="fspm.bin"
# CONFIG_FSP_FULL_FD is not set
CONFIG_FSP_T_RESERVED_SIZE=0x0
CONFIG_FSP_M_XIP=y
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
CONFIG_FSP_VGA_MODE12_BPP=0x0
CONFIG_INTEL_GMA_ACPI=y
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="Skylake"
CONFIG_GFX_GMA_PCH="Sunrise_Point"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
CONFIG_USE_PC_CMOS_ALTCENTURY=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_USB_ACPI=y
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_FW_VER=10
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
# end of Memory initialization
# CONFIG_STM is not set
# CONFIG_INTEL_CBNT_SUPPORT is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_CUSTOM_MADT=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_ACPI_LPIT=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
#
# I/O mapped, 8250-compatible
#
CONFIG_TTYS0_BASE=0x3f8
#
# Serial port base address = 0x3f8
#
# CONFIG_CONSOLE_SERIAL_921600 is not set
# CONFIG_CONSOLE_SERIAL_460800 is not set
# CONFIG_CONSOLE_SERIAL_230400 is not set
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_CONSOLE_SERIAL_57600 is not set
# CONFIG_CONSOLE_SERIAL_38400 is not set
# CONFIG_CONSOLE_SERIAL_19200 is not set
# CONFIG_CONSOLE_SERIAL_9600 is not set
CONFIG_TTYS0_LCS=3
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_CB=y
# end of Console
CONFIG_ACPI_S1_NOT_SUPPORTED=y
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_ACPI_NHLT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# Vendorcode Debug Settings
#
#
# BLOB Debug Settings
#
# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
# CONFIG_DISPLAY_FSP_HEADER is not set
# CONFIG_VERIFY_HOBS is not set
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
#
# General Debug Settings
#
# CONFIG_GDB_STUB is not set
CONFIG_HAVE_DEBUG_GPIO=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
@@ -0,0 +1,13 @@
# SPDX-License-Identifier: GPL-3.0-or-later
tree="default"
xarch="i386-elf"
payload_seabios="y"
payload_grub="y"
payload_memtest="y"
grub_scan_disk="nvme ahci"
grubtree="xhci_nvme"
vcfg="3050micro"
build_depend="seabios/default grub/xhci_nvme memtest86plus u-boot/amd64coreboot"
IFD_platform="sklkbl"
payload_uboot="amd64"
@@ -0,0 +1,811 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_LTO is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
CONFIG_SEPARATE_ROMSTAGE=y
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
# CONFIG_NO_STAGE_CACHE is not set
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOOSTAR is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ARM is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_CWWK is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_ERYING is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_FRAMEWORK is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HARDKERNEL is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LATTEPANDA is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MITAC_COMPUTING is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_NOVACUSTOM is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAPTOR_CS is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_TOPTON is not set
# CONFIG_VENDOR_UP is not set
# CONFIG_VENDOR_VIA is not set
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/sklkbl_desktops"
CONFIG_VGA_BIOS_ID="8086,0406"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=512
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
CONFIG_CBFS_SIZE=0xEEE000
# CONFIG_CONSOLE_SERIAL is not set
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
CONFIG_MAX_CPUS=16
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_VARIANT_DIR="optiplex_3050"
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
# CONFIG_VGA_BIOS is not set
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_PCIEXP_CLK_PM=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
# CONFIG_FATAL_ASSERTS is not set
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
# CONFIG_CONSOLE_POST is not set
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
CONFIG_MAX_SOCKET=1
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USE_PM_ACPI_TIMER=y
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_BOARD_DELL_E4300 is not set
# CONFIG_BOARD_DELL_E6400 is not set
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
CONFIG_BOARD_DELL_OPTIPLEX_3050=y
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
# CONFIG_BOARD_DELL_XPS_8300 is not set
CONFIG_BOARD_DELL_SKLKBL_DESKTOPS_COMMON=y
CONFIG_DCACHE_RAM_BASE=0xfef00000
CONFIG_DCACHE_RAM_SIZE=0x40000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
CONFIG_USE_LEGACY_8254_TIMER=y
# CONFIG_DEBUG_SMI is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
CONFIG_HAVE_IFD_BIN=y
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
CONFIG_D3COLD_SUPPORT=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
CONFIG_DRIVERS_UART_8250IO=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x100000
# CONFIG_DRIVERS_EFI_FW_INFO is not set
CONFIG_BOARD_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=16384
CONFIG_ROM_SIZE=0x01000000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_SMM_RESERVED_SIZE=0x200000
CONFIG_SMM_MODULE_STACK_SIZE=0x800
CONFIG_ACPI_BERT_SIZE=0x0
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
CONFIG_CPU_PT_ROM_MAP_GB=512
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_IFD_CHIPSET="sklkbl"
CONFIG_IED_REGION_SIZE=0x400000
CONFIG_MAX_ROOT_PORTS=24
CONFIG_PCR_BASE_ADDRESS=0xfd000000
CONFIG_CPU_BCLK_MHZ=100
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
CONFIG_CPU_XTAL_HZ=24000000
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
# CONFIG_ENABLE_SATA_TEST_MODE is not set
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_FSP_PUBLISH_MBP_HOB=y
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
CONFIG_MAX_HECI_DEVICES=5
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_HAVE_PAM0_REGISTER=y
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
CONFIG_SOC_INTEL_KABYLAKE=y
CONFIG_SKYLAKE_SOC_PCH_H=y
CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
CONFIG_FSP_T_LOCATION=0xfffe0000
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
CONFIG_UART_BITBANG_TX_DELAY_MS=5
CONFIG_SOC_INTEL_COMMON=y
#
# Intel SoC Common Code for IP blocks
#
CONFIG_SOC_INTEL_COMMON_BLOCK=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
# CONFIG_USE_COREBOOT_MP_INIT is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
CONFIG_INTEL_CAR_NEM_ENHANCED=y
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
CONFIG_HAVE_HYPERTHREADING=y
# CONFIG_FSP_HYPERTHREADING is not set
# CONFIG_INTEL_KEYLOCKER is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
CONFIG_SOC_INTEL_CSE_RW_FILE=""
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
CONFIG_SA_ENABLE_DPR=y
CONFIG_HAVE_CAPID_A_REGISTER=y
CONFIG_HAVE_BDSM_BGSM_REGISTER=y
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
#
# Intel SoC Common PCH Code
#
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
#
# Intel SoC Common coreboot stages and non-IP blocks
#
CONFIG_SOC_INTEL_COMMON_BASECODE=y
CONFIG_SOC_INTEL_COMMON_RESET=y
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
CONFIG_PAVP=y
# CONFIG_MMA is not set
CONFIG_SOC_INTEL_COMMON_NHLT=y
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
#
# CPU
#
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_PARALLEL_MP=y
CONFIG_PARALLEL_MP_AP_WORK=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
#
# Southbridge
#
# CONFIG_PCIEXP_HOTPLUG is not set
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_SMSC_SCH555x=y
#
# Embedded Controllers
#
#
# Intel Firmware
#
CONFIG_HAVE_ME_BIN=y
# CONFIG_STITCH_ME_BIN is not set
# CONFIG_CHECK_ME is not set
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
# CONFIG_USE_ME_CLEANER is not set
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
CONFIG_UNLOCK_FLASH_REGIONS=y
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
CONFIG_UDK_BASE=y
CONFIG_UDK_2017_BINDING=y
CONFIG_UDK_2013_VERSION=2013
CONFIG_UDK_2017_VERSION=2017
CONFIG_UDK_202005_VERSION=202005
CONFIG_UDK_202111_VERSION=202111
CONFIG_UDK_202302_VERSION=202302
CONFIG_UDK_202305_VERSION=202305
CONFIG_UDK_VERSION=2017
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
CONFIG_DEFAULT_EBDA_SIZE=0x400
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_HAVE_FSP_GOP=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_RUN_FSP_GOP is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y
# CONFIG_BOOTSPLASH is not set
CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y
# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set
# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set
# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_DRAM_SUPPORT_DDR4=y
CONFIG_DRAM_SUPPORT_DDR3=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
# CONFIG_ELOG is not set
# CONFIG_DRIVERS_HWID_DMI is not set
CONFIG_CACHE_MRC_SETTINGS=y
CONFIG_MRC_SETTINGS_PROTECT=y
# CONFIG_DRIVERS_OPTION_CFR is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_DRIVERS_UART=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_DESIGNWARE=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
# CONFIG_FSP_USE_REPO is not set
# CONFIG_DISPLAY_HOBS is not set
# CONFIG_DISPLAY_UPD_DATA is not set
CONFIG_PLATFORM_USES_FSP2_0=y
CONFIG_PLATFORM_USES_FSP2_X86_32=y
CONFIG_HAVE_INTEL_FSP_REPO=y
CONFIG_ADD_FSP_BINARIES=y
CONFIG_FSP_S_CBFS="fsps.bin"
CONFIG_FSP_M_CBFS="fspm.bin"
# CONFIG_FSP_FULL_FD is not set
CONFIG_FSP_T_RESERVED_SIZE=0x0
CONFIG_FSP_M_XIP=y
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
CONFIG_FSP_VGA_MODE12_BPP=0x0
CONFIG_INTEL_GMA_ACPI=y
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="Skylake"
CONFIG_GFX_GMA_PCH="Sunrise_Point"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
CONFIG_USE_PC_CMOS_ALTCENTURY=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_USB_ACPI=y
CONFIG_DRIVERS_WIFI_GENERIC=y
CONFIG_DRIVERS_MTK_WIFI=y
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_FW_VER=10
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
# end of Memory initialization
# CONFIG_STM is not set
# CONFIG_INTEL_CBNT_SUPPORT is not set
# CONFIG_BOOTMEDIA_LOCK_NONE is not set
CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
CONFIG_BOOTMEDIA_LOCK_WHOLE_RO=y
# CONFIG_BOOTMEDIA_LOCK_WHOLE_NO_ACCESS is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_CUSTOM_MADT=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_ACPI_LPIT=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_NULL=y
# end of Console
CONFIG_ACPI_S1_NOT_SUPPORTED=y
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_ACPI_NHLT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# Vendorcode Debug Settings
#
#
# BLOB Debug Settings
#
# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
# CONFIG_DISPLAY_FSP_HEADER is not set
# CONFIG_VERIFY_HOBS is not set
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
#
# General Debug Settings
#
# CONFIG_GDB_STUB is not set
CONFIG_HAVE_DEBUG_GPIO=y
# CONFIG_DEBUG_GPIO is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
#
# Boot Logo Configuration
#
# CONFIG_BMP_LOGO is not set
# end of Boot Logo Configuration
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y

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