grub.cfg: bruteforce linux/initrd if no grub.cfg

this is probably not safe, and neither is the current fall back code which is being removed from master. i already finished it before testing, but after realising the above, so i'll just stash it in this branch for now. Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-07-11 14:02:52 +02:00 · 2023-12-18 06:44:09 +00:00
618 changed files with 15012 additions and 48049 deletions
@@ -2,6 +2,7 @@
 *.o
 /lbmk.err.log
 /docs/
+/cbutils/
 /pciroms/
 /util/dell-flash-unlock/dell_flash_unlock
 /TODO
@@ -28,6 +29,3 @@
 /mrc/
 /util/nvmutil/nvm
 /src/
-/CHANGELOG
-/todo.txt
-/lock
@@ -81,7 +81,7 @@ automating much of the coreboot image creation and customization.
 Secondly, the project produces documentation aimed at non-technical users.
 Thirdly, the project attempts to provide excellent user support via IRC.

-Libreboot already comes with a payload (GRUB), flashprog and other
+Libreboot already comes with a payload (GRUB), flashrom and other
 needed parts. Everything is fully integrated, in a way where most of
 the complicated steps that are otherwise required, are instead done
 for the user in advance.
@@ -111,7 +111,7 @@ written in Markdown and hosted in a [separate
 repository](https://codeberg.org/libreboot/lbwww) where you can send patches.

 Any and all development discussion and user support are all done on the IRC
-channel. More information is on <https://libreboot.org/contact.html>.
+channel. More information is on https://libreboot.org/contact.html.

 LICENSE FOR THIS README
 =======================
@@ -1,143 +1,164 @@
 #!/usr/bin/env sh
 # SPDX-License-Identifier: GPL-3.0-or-later
-# Copyright (c) 2014-2015,2020-2024 Leah Rowe <leah@libreboot.org>
-# Copyright (c) 2015 Patrick "P. J." McDermott <pj@pehjota.net>
-# Copyright (c) 2015-2016 Klemens Nanni <contact@autoboot.org>
-# Copyright (c) 2022 Caleb La Grange <thonkpeasant@protonmail.com>
+# SPDX-FileCopyrightText: 2014,2015,2020,2021,2023 Leah Rowe <leah@libreboot.org>
+# SPDX-FileCopyrightText: 2015 Patrick "P. J." McDermott <pj@pehjota.net>
+# SPDX-FileCopyrightText: 2015, 2016 Klemens Nanni <contact@autoboot.org>
+# SPDX-FileCopyrightText: 2022, Caleb La Grange <thonkpeasant@protonmail.com>

 set -u -e

-if [ "./${0##*/}" != "${0}" ] || [ ! -f "build" ] || [ -L "build" ]; then
-	printf "You must run this in the proper work directory.\n" 1>&2
-	exit 1
+export LC_COLLATE=C
+export LC_ALL=C
+
+. "include/err.sh"
+. "include/option.sh"
+
+eval "$(setvars "" option aur_notice tmpdir)"
+
+tmpdir_was_set="y"
+set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n"
+if [ "${tmpdir_was_set}" = "y" ]; then
+	tmpdir="${TMPDIR##*/}"
+	tmpdir="${TMPDIR%_*}"
+	if [ "${tmpdir}" = "lbmk" ]; then
+		tmpdir=""
+		tmpdir_was_set="n"
+	fi
 fi
-
-. "include/lib.sh"
-. "include/vendor.sh"
-. "include/mrc.sh"
-
-eval "$(setvars "" vdir src_dirname srcdir _xm mode xp)"
-err="fail"
+if [ "${tmpdir_was_set}" = "n" ]; then
+	export TMPDIR="/tmp"
+	tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)"
+	export TMPDIR="${tmpdir}"
+else
+	export TMPDIR="${TMPDIR}"
+fi
+tmpdir="${TMPDIR}"

 linkpath="${0}"
 linkname="${linkpath##*/}"
+buildpath="./script/${linkname}"

 main()
 {
-	[ $# -lt 1 ] && badcmd
-	spath="script/$1"
+	xx_ id -u 1>/dev/null 2>/dev/null
+	[ $# -lt 1 ] && fail "Too few arguments. Try: ${0} help"
+	if [ "${1}" = "dependencies" ]; then
+		xx_ install_packages $@
+		lbmk_exit 0
+	fi

-	for g in "which git" "git config --global user.name" \
-	    "git config --global user.email" "git_init"; do
-		eval "$g 1>/dev/null 2>/dev/null || git_err \"$g\""
-	done
+	initialise_command $@ && shift 1
+
+	check_git
+	check_project "fail"
+	git_init
+
+	execute_command $@
+	lbmk_exit 0
+}
+
+initialise_command()
+{
+	[ "$(id -u)" != "0" ] || fail "this command as root is not permitted"
+
+	check_project

 	case "${1}" in
-	version) printf "%s\nWebsite: %s\n" "$relname" "$projectsite" ;;
-	release) shift 1; mkrelease $@ ;;
-	inject) shift 1; vendor_inject $@ ;;
-	download) shift 1; vendor_download $@ ;;
-	*)
-		[ -f "$spath" ] || badcmd
-		shift 1; "$spath" $@ || $err "excmd: $spath $@" ;;
+	help)
+		usage ${0}
+		lbmk_exit 0 ;;
+	list)
+		items "${buildpath}"
+		lbmk_exit 0 ;;
+	version)
+		mkversion
+		lbmk_exit 0 ;;
 	esac
-	set -u -e # some commands disable them. turn them on!
+	option="${1}"
 }

+install_packages()
+{
+	if [ $# -lt 2 ]; then
+		printf "You must specify a distro, namely:\n" 1>&2
+		printf "Look at files under config/dependencies/\n" 1>&2
+		printf "Example: ./build dependencies debian\n" 1>&2
+		fail "install_packages: target not specified"
+	fi
+
+	[ -f "config/dependencies/${2}" ] || fail "Unsupported target"
+
+	. "config/dependencies/${2}"
+
+	xx_ ${pkg_add} ${pkglist}
+	[ -z "${aur_notice}" ] && return 0
+	printf "You must install AUR packages: %s\n" "${aur_notice}" 1>&2
+}
+
+# release archives contain .gitignore, but not .git.
+# lbmk can be run from lbmk.git, or an archive.
 git_init()
 {
-	[ -L ".git" ] && return 1
+	[ -L ".git" ] && fail "Reference .git is a symlink"
 	[ -e ".git" ] && return 0
-	eval "$(setvars "$(date -Rud @$versiondate)" cdate _nogit)"
+	eval "$(setvars "$(date -Rd @${versiondate})" cdate _nogit)"

-	git init || return 1
-	git add -A . || return 1
-	git commit -m "$projectname $version" --date "$cdate" \
-	    --author="xbmk <xbmk@example.com>" || return 1
-	git tag -a "$version" -m "$projectname $version" || return 1
+	git init || fail "${PWD}: cannot initialise Git repository"
+	git add -A . || fail "${PWD}: cannot add files to Git repository"
+	git commit -m "${projectname} ${version}" --date "${cdate}" \
+	    --author="lbmk <lbmk@libreboot.org>" || \
+	    fail "${PWD}: can't commit ${projectname}/${version}, date ${cdate}"
+	git tag -a "${version}" -m "${projectname} ${version}" || \
+	    fail "${PWD}: cannot git-tag ${projectname}/${version}"
 }

-mkrelease()
+execute_command()
 {
-	export XBMK_RELEASE="y"
-
-	vdir="release"
-	while getopts d:m: option; do
-		[ -z "$OPTARG" ] && badcmd "empty argument not allowed"
-		case "$option" in
-		d) vdir="$OPTARG" ;;
-		m) mode="$OPTARG" ;;
-		*) badcmd "invalid option '-$option'" ;;
-		esac
-	done
-
-	vdir="$vdir/$version"
-	src_dirname="${relname}_src"
-	srcdir="$vdir/$src_dirname"
-
-	[ -e "$vdir" ] && $err "already exists: \"$vdir\""
-	mkdir -p "$vdir" || $err "mkvdir: !mkdir -p \"$vdir\""
-	git clone . "$srcdir" || $err "mkdir: !gitclone \"$srcdir\""
-	touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
-
-	build_release
-
-	printf "\n\nDONE! Check release files under %s\n" "$vdir"
+	lbmkcmd="${buildpath}/${option}"
+	[ -f "${lbmkcmd}" ] || fail "Invalid command. Run: ${linkpath} help"
+	"${lbmkcmd}" $@ || fail "execute_command: ${lbmkcmd} ${@}"
 }

-build_release()
+usage()
 {
-	_xm="build_release $vdir"
-	(
-	cd "$srcdir" || $err "$_xm: !cd \"$srcdir\""
-	fetch_trees
-	x_ mv src/docs docs
-	) || $err "can't create release files"
+	progname=${0}
+	cat <<- EOF
+	$(mkversion)

-	git log --graph --pretty=format:'%Cred%h%Creset %s %Creset' \
-	    --abbrev-commit > "$srcdir/CHANGELOG" || $err "!gitlog $srcdir"
-	rm -f "$srcdir/lock" || $err "can't remove lock file in $srcdir"
+	USAGE:	${progname} <OPTION>

-	(
-	cd "${srcdir%/*}" || $err "$_xm: mktarball \"$srcdir\""
-	mktarball "${srcdir##*/}" "${srcdir##*/}.tar.xz" || $err "$_xm: mksrc"
-	) || $err "can't create src tarball"
-	[ "$mode" = "src" ] && return 0
+	possible values for 'OPTION':
+	$(items "${buildpath}")

-	touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
+	To know what ${projectname} version you're on, type:
+	${progname} version

-	(
-	cd "$srcdir" || $err "$_xm: 2 !cd \"$srcdir\""
-	./build roms all || $err "$_xm: roms-all"
-	./build roms serprog rp2040 || $err "$_xm: rp2040"
-	./build roms serprog stm32 || $err "$_xm: stm32"
-	x_ mv bin ../roms
-	) || $err "can't build rom images"
-
-	rm -Rf "$srcdir" || $err "!rm -Rf $srcdir"
+	Refer to ${projectname} documentation for more info.
+	EOF
 }

-fetch_trees()
+mkversion()
 {
-	for x in $(items config/git); do
-		./update trees -f "$x" || $err "$_xm: fetch $x"
-		singletree "$x" || x_ rm -Rf "src/$x/$x"
-	done
-	rmgit .
+	printf "revision: %s %s\n" "${projectname}" "${version}"
+	printf "revision date: %s\n" "$(date -Rud @${versiondate})"
+}
+
+lbmk_exit()
+{
+	tmp_cleanup || err "lbmk_exit: can't rm tmpdir upon exit $1: ${tmpdir}"
+	exit $1
 }

 fail()
 {
-	tmp_cleanup || printf "WARNING: can't rm tmpfiles: %s\n" "$tmpdir" 1>&2
-	err_ "${1}"
+	tmp_cleanup || printf "WARNING: can't rm tmpdir: %s\n" "${tmpdir}" 1>&2
+	err "${1}"
 }

 tmp_cleanup()
 {
-	[ "$tmpdir_was_set" = "n" ] || return 0
-	rm -Rf "$tmpdir" || return 1
-	rm -f lock || return 1
+	[ "${tmpdir_was_set}" = "n" ] || return 0
+	rm -Rf "${tmpdir}" || return 1
 }

 main $@
-tmp_cleanup || err_ "can't rm tmpdir upon non-zero exit: $tmpdir"
@@ -1,56 +0,0 @@
-From f22f408956bf02609a96b7d72fb3321da159bfc6 Mon Sep 17 00:00:00 2001
-From: Nico Huber <nico.huber@secunet.com>
-Date: Tue, 22 Jun 2021 13:49:44 +0000
-Subject: [PATCH 1/1] cbfstool: Make use of spurious null-termination
-
-The null-termination of `filetypes` was added after the code was
-written, obviously resulting in NULL dereferences. As some more
-code has grown around the termination, it's hard to revert the
-regression, so let's update the code that still used the array
-length.
-
-This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
-which actually did fix something, but only one path while it broke
-two others. We should be careful with fixes, they can always break
-something else. Especially when a dumb tool triggered the patching
-it seems likely that fewer people looked into related code.
-
-Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
-Signed-off-by: Nico Huber <nico.huber@secunet.com>
-Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-Reviewed-by: Julius Werner <jwerner@chromium.org>
---
- util/cbfstool/common.c | 8 ++++----
- 1 file changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
-index e2ed38ffc4..539d0baccf 100644
--- a/util/cbfstool/common.c
-+++ b/util/cbfstool/common.c
-@@ -168,10 +168,10 @@ void print_supported_architectures(void)
- 
- void print_supported_filetypes(void)
- {
-	int i, number = ARRAY_SIZE(filetypes);
-+	int i;
- 
-	for (i=0; i<number; i++) {
-		printf(" %s%c", filetypes[i].name, (i==(number-1))?'\n':',');
-+	for (i=0; filetypes[i].name; i++) {
-+		printf(" %s%c", filetypes[i].name, filetypes[i + 1].name ? ',' : '\n');
- 		if ((i%8) == 7)
- 			printf("\n");
- 	}
-@@ -180,7 +180,7 @@ void print_supported_filetypes(void)
- uint64_t intfiletype(const char *name)
- {
- 	size_t i;
-	for (i = 0; i < (sizeof(filetypes) / sizeof(struct typedesc_t)); i++)
-+	for (i = 0; filetypes[i].name; i++)
- 		if (strcmp(filetypes[i].name, name) == 0)
- 			return filetypes[i].type;
- 	return -1;
-- 
-2.39.2
-
@@ -1,2 +0,0 @@
-tree="coreboot413"
-rev="5c186c6777c9438ff4681929c9c25c98dee28bef"
@@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -130,8 +129,6 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=256
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -144,6 +141,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -191,7 +189,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_MINNOW3 is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
-# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
@@ -204,12 +201,15 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
 CONFIG_PCIEXP_HOTPLUG_BUSES=32
 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -223,7 +223,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=1024
@@ -249,7 +248,6 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -258,18 +256,17 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000

 #
 # CPU
@@ -358,8 +355,6 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -391,7 +386,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
+CONFIG_AZALIA_PLUGIN_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -402,6 +397,8 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -431,7 +428,6 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
@@ -446,10 +442,6 @@ CONFIG_DRIVERS_I2C_CK505=y
 CONFIG_INTEL_EDID=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
@@ -481,7 +473,6 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module

@@ -509,7 +500,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
@@ -573,10 +563,6 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set

-#
-# Vendorcode Debug Settings
-#
-
 #
 # BLOB Debug Settings
 #
@@ -1,5 +1,9 @@
 tree="default"
-xarch="i386-elf"
+romtype="normal"
+arch="x86_64"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
 payload_memtest="y"
-release="n"
+microcode_required="n"
+vendorfiles="n"
@@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -130,8 +129,6 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=256
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -144,6 +141,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -191,7 +189,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_MINNOW3 is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
-# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
@@ -204,12 +201,15 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
 CONFIG_PCIEXP_HOTPLUG_BUSES=32
 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -223,7 +223,6 @@ CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=16384
@@ -249,7 +248,6 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -258,18 +256,17 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000

 #
 # CPU
@@ -358,8 +355,6 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -391,7 +386,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
+CONFIG_AZALIA_PLUGIN_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -402,6 +397,8 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -431,7 +428,6 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
@@ -446,10 +442,6 @@ CONFIG_DRIVERS_I2C_CK505=y
 CONFIG_INTEL_EDID=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
@@ -481,7 +473,6 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module

@@ -509,7 +500,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
@@ -573,10 +563,6 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set

-#
-# Vendorcode Debug Settings
-#
-
 #
 # BLOB Debug Settings
 #
@@ -1,6 +1,8 @@
 tree="default"
-xarch="i386-elf"
+romtype="normal"
+arch="x86_64"
 payload_seabios="y"
 payload_seabios_withgrub="y"
 payload_memtest="y"
-release="n"
+microcode_required="n"
+vendorfiles="n"
@@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -131,8 +130,6 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -145,6 +142,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -192,7 +190,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_MINNOW3 is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
-# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
@@ -202,6 +199,8 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
@@ -209,6 +208,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -222,7 +222,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=512
@@ -248,7 +247,6 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -257,18 +255,17 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000

 #
 # CPU
@@ -357,8 +354,6 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -390,7 +385,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
+CONFIG_AZALIA_PLUGIN_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -398,6 +393,8 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
 # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -426,7 +423,6 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
@@ -440,10 +436,6 @@ CONFIG_HAVE_USBDEBUG=y
 CONFIG_INTEL_EDID=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
@@ -475,7 +467,6 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module

@@ -503,7 +494,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
@@ -571,10 +561,6 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set

-#
-# Vendorcode Debug Settings
-#
-
 #
 # BLOB Debug Settings
 #
@@ -1,4 +1,9 @@
 tree="default"
-xarch="i386-elf"
+romtype="normal"
+arch="x86_32"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
-release="n"
+payload_memtest="n"
+vendorfiles="n"
+microcode_required="n"
@@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -131,8 +130,6 @@ CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -145,6 +142,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -192,7 +190,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_MINNOW3 is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
-# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
@@ -202,6 +199,8 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
@@ -209,6 +208,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -222,7 +222,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=8192
@@ -248,7 +247,6 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -257,18 +255,17 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000

 #
 # CPU
@@ -357,8 +354,6 @@ CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -390,7 +385,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
+CONFIG_AZALIA_PLUGIN_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -398,6 +393,8 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
 # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -426,7 +423,6 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
@@ -440,10 +436,6 @@ CONFIG_HAVE_USBDEBUG=y
 CONFIG_INTEL_EDID=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
@@ -475,7 +467,6 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module

@@ -503,7 +494,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
@@ -571,10 +561,6 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set

-#
-# Vendorcode Debug Settings
-#
-
 #
 # BLOB Debug Settings
 #
@@ -1,5 +1,9 @@
 tree="default"
-xarch="i386-elf"
+romtype="normal"
+arch="x86_32"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
-payload_seabios_withgrub="y"
-release="n"
+payload_memtest="n"
+vendorfiles="n"
+microcode_required="n"
@@ -1,7 +1,7 @@
-From 1195c954a3b6822e5e843067251c0c80c9520eab Mon Sep 17 00:00:00 2001
+From e8f5f6c372152c7deddd3080954d0f4fdd39ae2b Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@retroboot.org>
 Date: Fri, 19 Mar 2021 05:54:58 +0000
-Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of
+Subject: [PATCH 01/22] apple/macbook21: Set default VRAM to 64MiB instead of
 8MiB

 ---
@@ -1,7 +1,7 @@
-From 50a52cea2b43e6e407b456c082e908c7d29e090b Mon Sep 17 00:00:00 2001
+From fdd756a8217548981a1eb62e504cc37371c9fd51 Mon Sep 17 00:00:00 2001
 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
 Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 02/22] add c3 and clockgen to apple/macbook21

 ---
 src/mainboard/apple/macbook21/Kconfig       |  1 +
@@ -1,7 +1,7 @@
-From ca4cd66f411247395a323e5ea1abf09e83057827 Mon Sep 17 00:00:00 2001
+From c8332a8bac4986afec6c639f55c5876f83e50b76 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@osboot.org>
 Date: Sun, 3 Jan 2021 03:34:01 +0000
-Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default
+Subject: [PATCH 03/22] lenovo/x60: 64MiB Video RAM changed to default
 (previously it was 8MiB)

 ---
@@ -1,7 +1,7 @@
-From eca0f4a3a4d6907e92b948547a362ca0ac3fc382 Mon Sep 17 00:00:00 2001
+From 2e3ad35c24a86cb3109f4e5139b9ffba931eb80b Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@osboot.org>
 Date: Mon, 22 Feb 2021 22:16:59 +0000
-Subject: [PATCH 04/30] lenovo/t60: make 64MiB VRAM the default in cmos.default
+Subject: [PATCH 04/22] lenovo/t60: make 64MiB VRAM the default in cmos.default

 ---
 src/mainboard/lenovo/t60/cmos.default | 2 +-
@@ -1,7 +1,7 @@
-From 2eae87815675aebd472b6042777fe51279be4550 Mon Sep 17 00:00:00 2001
+From 5fc03fbf8c7fa30588dab93c76b5532ce03b1610 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:10:33 +0100
-Subject: [PATCH 05/30] lenovo/t400: set VRAM to 256MiB VRAM by default
+Subject: [PATCH 05/22] lenovo/t400: set VRAM to 256MiB VRAM by default

 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -1,7 +1,7 @@
-From f6b4913a5eca619b745d5ccea9af022a54fb185b Mon Sep 17 00:00:00 2001
+From 93f607fed477b3e63b7929808937436ac2898b34 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:11:59 +0100
-Subject: [PATCH 06/30] lenovo/x200: set VRAM to 256MiB by default
+Subject: [PATCH 06/22] lenovo/x200: set VRAM to 256MiB by default

 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -1,7 +1,7 @@
-From a3a0969075163be413f968b03671aa5d8662672a Mon Sep 17 00:00:00 2001
+From 9faa780b2ac45bc1bf61aa252364ee3158c4cb10 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:18:26 +0100
-Subject: [PATCH 07/30] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
+Subject: [PATCH 07/22] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default

 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -1,7 +1,7 @@
-From 223ac17617b3a0c08925abbbe42d0d003e144a28 Mon Sep 17 00:00:00 2001
+From f1c59cd67446303a5cdf9107461247a63f894de3 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:21:39 +0100
-Subject: [PATCH 08/30] acer/g43t-am3: set VRAM to 256MiB by default
+Subject: [PATCH 08/22] acer/g43t-am3: set VRAM to 256MiB by default

 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -1,7 +1,7 @@
-From 80ebbfef42454ea0911e5fc3858103d905987ed8 Mon Sep 17 00:00:00 2001
+From 75858ba200a2a5835bca0af9b5f508a52ed978de Mon Sep 17 00:00:00 2001
 From: persmule <persmule@gmail.com>
 Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 09/30] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 09/22] lenovo/t400: Enable all SATA ports

 There are 2 SATA ports on the chassis of t400(s), but at least one dock for
 t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -1,7 +1,7 @@
-From 318a97c284f8d5030100476a32516ddc9e51603d Mon Sep 17 00:00:00 2001
+From 2c103a71a37eb4db9d33928b2371a682ca04e65f Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 20 Dec 2021 01:29:31 +0000
-Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
+Subject: [PATCH 10/22] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
 default

 ---
@@ -1,7 +1,7 @@
-From 47afbe8b94edd1ff58c1daf0bda020e6afac35f4 Mon Sep 17 00:00:00 2001
+From 040f15039fa59d70cd54b8fff5d947e155666aa1 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 11/30] lenovo/x230: set me_state=Disabled in cmos.default
+Subject: [PATCH 11/22] lenovo/x230: set me_state=Disabled in cmos.default

 I only recently found out about this. It's possible to use me_cleaner to
 do the same thing, but some people might just flash coreboot and not do
@@ -1,7 +1,7 @@
-From 531ef34ece796f38cb8a13a54856e46e79842e29 Mon Sep 17 00:00:00 2001
+From 81febff42c66bd53e44176f14b651339b503a9f3 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 12/30] set me_state=Disabled on all cmos.default files!
+Subject: [PATCH 12/22] set me_state=Disabled on all cmos.default files!

 yeah. why the hell isn't this the default

@@ -0,0 +1,198 @@
+From c73269315626678c191ea494338581abdc417f21 Mon Sep 17 00:00:00 2001
+From: Alexander Couzens <lynxis@fe80.eu>
+Date: Sat, 19 Mar 2022 13:42:33 +0000
+Subject: [PATCH 13/22] lenovo/x230: introduce FHD variant
+
+There is a modification for the x230 which uses the 2nd DP from the dock
+as the integrated panel's connection, which allows using a custom eDP
+panel instead of the stock LVDS display.
+
+There are several adapter boards present on the market and all of them
+uses the same method of enabling the custom eDP panel.
+
+To make this work with coreboot, the internal LVDS connector should be
+disabled in libgfxinit. The VBT has been modified as well, which allows
+brightness controls to work out of the box.
+
+The modifications done to the VBT are:
+- Remove the LVDS port entry.
+- Move the DP-3 (which is the 2nd DP on the dock) entry to the first
+  position on the list.
+- Set the DP-3 as internally connected.
+
+This has been reported to work with the following panels:
+- LP125WF2-SPB4 (1920*1080, 12.5")
+- LQ125T1JW02 (2560*1440, 12.5")
+- LQ133M1JW21 (1920*1080, 13.3")
+- LTN133HL10-201 (1920*1080, 13.3")
+- B133HAN04.6 (1920*1080, 13.3")
+- B133QAN02.0 (2560*1600, 13.3")
+
+Other eDP panels not on this list should work as well.
+
+Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0
+Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
+Signed-off-by: Felix Singer <felixsinger@posteo.net>
+---
+ src/mainboard/lenovo/x230/Kconfig             |  15 ++++++++-----
+ src/mainboard/lenovo/x230/Kconfig.name        |   3 +++
+ src/mainboard/lenovo/x230/Makefile.inc        |   5 +++++
+ .../lenovo/x230/variants/x230_edp/data.vbt    | Bin 0 -> 4281 bytes
+ .../x230/variants/x230_edp/gma-mainboard.ads  |  21 ++++++++++++++++++
+ 5 files changed, 38 insertions(+), 6 deletions(-)
+ create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
+ create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
+
+diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
+index 279095629b..acfd0ed561 100644
+--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
+@@ -1,4 +1,4 @@
+-if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S
+if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
+ 
+ config BOARD_SPECIFIC_OPTIONS
+ 	def_bool y
+@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select H8_HAS_BAT_THRESHOLDS_IMPL
+ 	select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S
+ 	select NO_UART_ON_SUPERIO
+-	select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+	select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
+ 	select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S
+ 	select HAVE_ACPI_TABLES
+ 	select HAVE_OPTION_TABLE
+@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select INTEL_INT15
+ 	select DRIVERS_RICOH_RCE822
+ 	select MEMORY_MAPPED_TPM
+-	select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+	select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
+ 	select MAINBOARD_HAS_LIBGFXINIT
+ 	select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+ 	select INTEL_GMA_HAVE_VBT
+@@ -47,17 +47,20 @@ config MAINBOARD_DIR
+ 	default "lenovo/x230"
+ 
+ config VARIANT_DIR
+-	default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+	default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
+ 	default "x230s" if BOARD_LENOVO_X230S
+ 
+ config MAINBOARD_PART_NUMBER
+-	default "ThinkPad X230" if BOARD_LENOVO_X230
+	default "ThinkPad X230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230_EDP
+ 	default "ThinkPad X230t" if BOARD_LENOVO_X230T
+ 	default "ThinkPad X230s" if BOARD_LENOVO_X230S
+ 
+ config OVERRIDE_DEVICETREE
+ 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+ 
+config INTEL_GMA_VBT_FILE
+	default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
+
+ config USBDEBUG_HCD_INDEX
+ 	int
+ 	default 2
+@@ -79,4 +82,4 @@ config PS2M_EISAID
+ config THINKPADEC_HKEY_EISAID
+ 	default "LEN0068"
+ 
+-endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ||  BOARD_LENOVO_X230S
+endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ||  BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
+diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name
+index 1a01436879..e7290a12dd 100644
+--- a/src/mainboard/lenovo/x230/Kconfig.name
+++ b/src/mainboard/lenovo/x230/Kconfig.name
+@@ -6,3 +6,6 @@ config BOARD_LENOVO_X230T
+ 
+ config BOARD_LENOVO_X230S
+ 	bool "ThinkPad X230s"
+
+config BOARD_LENOVO_X230_EDP
+	bool "ThinkPad X230 eDP Mod (2K/FHD)"
+diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc
+index 8e801f145d..6e6f9f90b9 100644
+--- a/src/mainboard/lenovo/x230/Makefile.inc
+++ b/src/mainboard/lenovo/x230/Makefile.inc
+@@ -5,4 +5,9 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
+ romstage-y += variants/$(VARIANT_DIR)/early_init.c
+ romstage-y += variants/$(VARIANT_DIR)/gpio.c
+ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+
+ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y)
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads
+else
+ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+endif
+diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt b/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
+GIT binary patch
+literal 4281
+zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^
+zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
+zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
+zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
+zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
+zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
+z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
+zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
+z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
+z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
+zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT
+zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
+z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}(
+z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg
+zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW>
+zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn
+zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L
+zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy;
+z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY
+zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
+zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
+zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
+z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
+zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
+zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
+zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
+z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
+zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
+zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH
+z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
+zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
+p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
+new file mode 100644
+index 0000000000..f7cf0bc264
+--- /dev/null
+++ b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
+@@ -0,0 +1,21 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
+-- 
+2.39.2
+
@@ -0,0 +1,25 @@
+From c32229e3f82c00abb2bee4d0f7ddf33d4c7a04dc Mon Sep 17 00:00:00 2001
+From: Alexei Sorokin <sor.alexei@meowr.ru>
+Date: Sun, 27 Nov 2022 18:36:26 +0300
+Subject: [PATCH 14/22] lenovo/x230: fix the data.vbt path for the EDP variant
+
+---
+ src/mainboard/lenovo/x230/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
+index acfd0ed561..34108c3c04 100644
+--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
+@@ -59,7 +59,7 @@ config OVERRIDE_DEVICETREE
+ 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+ 
+ config INTEL_GMA_VBT_FILE
+-	default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
+       default "src/mainboard/\$(MAINBOARDDIR)/variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
+ 
+ config USBDEBUG_HCD_INDEX
+ 	int
+-- 
+2.39.2
+
@@ -1,7 +1,7 @@
-From 158b79e6057e071d039619f617c112d31fb13f64 Mon Sep 17 00:00:00 2001
+From 38c76afbea4abfed2976bfbe10977e41f21665b0 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 15/30] util/ifdtool: add --nuke flag (all 0xFF on region)
+Subject: [PATCH 15/22] util/ifdtool: add --nuke flag (all 0xFF on region)

 When this option is used, the region's contents are overwritten
 with all ones (0xFF).
@@ -16,91 +16,91 @@ Rebased since the last revision update in lbmk.

 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
- util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
- 1 file changed, 81 insertions(+), 31 deletions(-)
+ util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
+ 1 file changed, 83 insertions(+), 31 deletions(-)

 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index 191b3216de..38132b4a28 100644
+index ddbc0fb91b..7af9235ae3 100644
 --- a/util/ifdtool/ifdtool.c
 +++ b/util/ifdtool/ifdtool.c
-@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
- 	       "                                         tgl    - Tiger Lake\n"
+@@ -1847,6 +1847,7 @@ static void print_usage(const char *name)
 	       "                                         wbg    - Wellsburg\n"
 	       "   -S | --setpchstrap                    Write a PCH strap\n"
-+	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
+	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
 	       "   -v | --version:                       print the version\n"
 	       "   -h | --help:                          print this help\n\n"
-@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
+ 	       "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
+@@ -1854,6 +1855,60 @@ static void print_usage(const char *name)
 	       "\n");
 }
 
 +static int
 +get_region_type_string(const char *region_type_string)
 +{
-+       if (!strcasecmp("Descriptor", region_type_string))
-+               return 0;
-+       else if (!strcasecmp("BIOS", region_type_string))
-+               return 1;
-+       else if (!strcasecmp("ME", region_type_string))
-+               return 2;
-+       else if (!strcasecmp("GbE", region_type_string))
-+               return 3;
-+       else if (!strcasecmp("Platform Data", region_type_string))
-+               return 4;
-+       else if (!strcasecmp("Device Exp1", region_type_string))
-+               return 5;
-+       else if (!strcasecmp("Secondary BIOS", region_type_string))
-+               return 6;
-+       else if (!strcasecmp("Reserved", region_type_string))
-+               return 7;
-+       else if (!strcasecmp("EC", region_type_string))
-+               return 8;
-+       else if (!strcasecmp("Device Exp2", region_type_string))
-+               return 9;
-+       else if (!strcasecmp("IE", region_type_string))
-+               return 10;
-+       else if (!strcasecmp("10GbE_0", region_type_string))
-+               return 11;
-+       else if (!strcasecmp("10GbE_1", region_type_string))
-+               return 12;
-+       else if (!strcasecmp("PTT", region_type_string))
-+               return 15;
-+       return -1;
+	if (!strcasecmp("Descriptor", region_type_string))
+		return 0;
+	else if (!strcasecmp("BIOS", region_type_string))
+		return 1;
+	else if (!strcasecmp("ME", region_type_string))
+		return 2;
+	else if (!strcasecmp("GbE", region_type_string))
+		return 3;
+	else if (!strcasecmp("Platform Data", region_type_string))
+		return 4;
+	else if (!strcasecmp("Device Exp1", region_type_string))
+		return 5;
+	else if (!strcasecmp("Secondary BIOS", region_type_string))
+		return 6;
+	else if (!strcasecmp("Reserved", region_type_string))
+		return 7;
+	else if (!strcasecmp("EC", region_type_string))
+		return 8;
+	else if (!strcasecmp("Device Exp2", region_type_string))
+		return 9;
+	else if (!strcasecmp("IE", region_type_string))
+		return 10;
+	else if (!strcasecmp("10GbE_0", region_type_string))
+		return 11;
+	else if (!strcasecmp("10GbE_1", region_type_string))
+		return 12;
+	else if (!strcasecmp("PTT", region_type_string))
+		return 15;
+	return -1;
 +}
 +
 +static void
 +nuke(const char *filename, char *image, int size, int region_type)
 +{
-+       int i;
-+       struct region region;
-+       const struct frba *frba = find_frba(image, size);
-+       if (!frba)
-+               exit(EXIT_FAILURE);
+	int i;
+	struct region region;
+	const struct frba *frba = find_frba(image, size);
+	if (!frba)
+		exit(EXIT_FAILURE);
 +
-+       region = get_region(frba, region_type);
-+       if (region.size > 0) {
-+               for (i = region.base; i <= region.limit; i++) {
-+                       if ((i + 1) > (size))
-+                               break;
-+                       image[i] = 0xFF;
-+               }
-+               write_image(filename, image, size);
-+       }
+	region = get_region(frba, region_type);
+	if (region.size > 0) {
+		for (i = region.base; i <= region.limit; i++) {
+			if ((i + 1) > (size))
+				break;
+			image[i] = 0xFF;
+		}
+		write_image(filename, image, size);
+	}
 +}
 +
 int main(int argc, char *argv[])
 {
 	int opt, option_index = 0;
-@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
+@@ -1861,6 +1916,7 @@ int main(int argc, char *argv[])
 	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
 	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
 +	int mode_nuke = 0;
- 	int mode_gpr0_disable = 0;
 	char *region_type_string = NULL, *region_fname = NULL;
 	const char *layout_fname = NULL;
-@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
+ 	char *new_filename = NULL;
+@@ -1892,6 +1948,7 @@ int main(int argc, char *argv[])
 		{"validate", 0, NULL, 't'},
 		{"setpchstrap", 1, NULL, 'S'},
 		{"newvalue", 1, NULL, 'V'},
@@ -108,7 +108,7 @@ index 191b3216de..38132b4a28 100644
 		{0, 0, 0, 0}
 	};
 
-@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
+@@ -1941,35 +1998,8 @@ int main(int argc, char *argv[])
 			region_fname++;
 			// Descriptor, BIOS, ME, GbE, Platform
 			// valid type?
@@ -141,12 +141,12 @@ index 191b3216de..38132b4a28 100644
 -			else if (!strcasecmp("PTT", region_type_string))
 -				region_type = 15;
 -			if (region_type == -1) {
-+                       if ((region_type =
-+                           get_region_type_string(region_type_string)) == -1) {
+			if ((region_type =
+			    get_region_type_string(region_type_string)) == -1) {
 				fprintf(stderr, "No such region type: '%s'\n\n",
 					region_type_string);
 				fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
-@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
+@@ -2135,6 +2165,22 @@ int main(int argc, char *argv[])
 		case 't':
 			mode_validate = 1;
 			break;
@@ -169,29 +169,31 @@ index 191b3216de..38132b4a28 100644
 		case 'v':
 			print_version();
 			exit(EXIT_SUCCESS);
-@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
+@@ -2150,7 +2196,8 @@ int main(int argc, char *argv[])
+ 
 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
 			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
- 			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
-			mode_gpr0_disable) > 1) {
-+			mode_gpr0_disable + mode_nuke) > 1) {
+-			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) {
+			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
+			mode_nuke) > 1) {
 		fprintf(stderr, "You may not specify more than one mode.\n\n");
 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
 		exit(EXIT_FAILURE);
-@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
+@@ -2158,7 +2205,8 @@ int main(int argc, char *argv[])
+ 
 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
 			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
- 			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
-			mode_validate + mode_gpr0_disable) == 0) {
-+			mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
+-			mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
+			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
+			mode_validate + mode_nuke) == 0) {
 		fprintf(stderr, "You need to specify a mode.\n\n");
 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
 		exit(EXIT_FAILURE);
-@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
+@@ -2262,6 +2310,10 @@ int main(int argc, char *argv[])
 		write_image(new_filename, image, size);
 	}
 
-+       if (mode_nuke) {
+	if (mode_nuke) {
 +               nuke(new_filename, image, size, region_type);
 +       }
 +
@@ -1,7 +1,7 @@
-From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001
+From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 1 Dec 2021 02:53:00 +0000
-Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert
+Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
 "cpu/intel/model_1067x: enable PECI"

 This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
@@ -1,7 +1,7 @@
-From 8a94f38398b8fa554fa4ae53ecb88a372df634fd Mon Sep 17 00:00:00 2001
+From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 17 Apr 2023 15:49:57 +0100
-Subject: [PATCH 17/30] GM45-type CPUs: don't enable alternative SMRR
+Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR

 This reverts the changes in coreboot revision:
 df7aecd92643d207feaf7fd840f8835097346644
@@ -1,7 +1,7 @@
-From 2b899f40ce5d728faa7c1da23c3348435b7ac9cb Mon Sep 17 00:00:00 2001
+From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 18/30] mb/dell/e6400: Enable 01.0 device in devicetree for
+Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for
 dGPU models

 Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
@@ -1,7 +1,7 @@
-From 2ccd3e71730004c3ffbed178087cb778c170079e Mon Sep 17 00:00:00 2001
+From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 19/30] Remove warning for coreboot images built without a
+Subject: [PATCH 19/22] Remove warning for coreboot images built without a
 payload

 I added this in upstream to prevent people from accidentally flashing
@@ -9,19 +9,19 @@ roms without a payload resulting in a no boot situation, but in
 libreboot lbmk handles the payload and thus this warning always comes
 up. This has caused confusion and concern so just patch it out.
 ---
- payloads/Makefile.mk | 13 +------------
+ payloads/Makefile.inc | 13 +------------
 1 file changed, 1 insertion(+), 12 deletions(-)

-diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
-index a2336aa876..4f1692a873 100644
--- a/payloads/Makefile.mk
-+++ b/payloads/Makefile.mk
+diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
+index e735443a76..4f1692a873 100644
+--- a/payloads/Makefile.inc
+++ b/payloads/Makefile.inc
@@ -49,16 +49,5 @@ distclean-payloads:
 print-repo-info-payloads:
 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
 
 -ifeq ($(CONFIG_PAYLOAD_NONE),y)
-show_notices:: warn_no_payload
+-files_added:: warn_no_payload
 -endif
 -
 -warn_no_payload:
@@ -0,0 +1,61 @@
+From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sun, 27 Aug 2023 17:36:36 -0600
+Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios
+
+These were determined by sniffing the LPC bus while toggling the
+hardware wireless switch on the Latitude E6400. To differentiate devices
+options in the vendor BIOS to change which radios the switch controlled
+were used.
+
+Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/ec/dell/mec5035/mec5035.c | 9 +++++++++
+ src/ec/dell/mec5035/mec5035.h | 8 ++++++++
+ 2 files changed, 17 insertions(+)
+
+diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
+index 8da11e5b1c..e0335a4635 100644
+--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
+@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting)
+ 	return buf[0];
+ }
+ 
+void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on)
+{
+	/* From LPC traces and userspace testing with other values,
+	   the second byte has to be 2 for an unknown reason. */
+	u8 buf[3] = {dev, 2, on};
+	write_mailbox_regs(buf, 2, 3);
+	ec_command(CMD_RADIO_EN);
+}
+
+ void mec5035_early_init(void)
+ {
+ 	/* If this isn't sent the EC shuts down the system after about 15
+diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
+index e7a05b64d4..16512e2cc2 100644
+--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
+@@ -16,8 +16,16 @@
+ 
+ #define CMD_CPU_OK	0xc2
+ 
+#define CMD_RADIO_EN	0x2b
+enum mec5035_radio_dev {
+	RADIO_WLAN = 0,
+	RADIO_WWAN = 1,
+	RADIO_WPAN = 2,
+};
+
+ u8 mec5035_mouse_touchpad(u8 setting);
+ void mec5035_cpu_ok(void);
+ void mec5035_early_init(void);
+void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on);
+ 
+ #endif /* _EC_DELL_MEC5035_H_ */
+-- 
+2.39.2
+
@@ -0,0 +1,37 @@
+From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sun, 27 Aug 2023 19:15:37 -0600
+Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API
+
+Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/ec/dell/mec5035/mec5035.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
+index e0335a4635..20a33cc0ad 100644
+--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
+@@ -4,6 +4,7 @@
+ #include <console/console.h>
+ #include <device/device.h>
+ #include <device/pnp.h>
+#include <option.h>
+ #include <pc80/keyboard.h>
+ #include <stdint.h>
+ #include "mec5035.h"
+@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev)
+ 	mec5035_mouse_touchpad(TP_PS2_MOUSE);
+ 
+ 	pc_keyboard_init(NO_AUX_DEVICE);
+
+	mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1));
+	mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1));
+	mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1));
+ }
+ 
+ static struct device_operations ops = {
+-- 
+2.39.2
+
@@ -1,14 +1,14 @@
-From a49df0307455d6d8b7a9efb9f4639b72be1b64d4 Mon Sep 17 00:00:00 2001
+From b37175381a32d9d308b5c1d67e11cdc57a24c820 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 19 Aug 2023 16:19:10 -0600
-Subject: [PATCH 20/30] mb/dell: Add Latitude E6430 (Ivy Bridge)
+Subject: [PATCH] mb/dell: Add Latitude E6430 (Ivy Bridge)

-Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. This
-is based on the autoport output with some manual tweaks. The flash is
-8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. It
-can also be internally flashed by sending a command to the EC, which
+Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested.
+This is based on the autoport output with some manual tweaks. The flash
+is 8MiB + 4MiB, and is fairly easily accessed by removing the keyboard.
+It can also be internally flashed by sending a command to the EC, which
 causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections [1]. The EC is the SMSC MEC5055,
+up any chipset based write protections. [1] The EC is the SMSC MEC5055,
 which seems to be compatible with the existing MEC5035 code.

 Working:
@@ -24,29 +24,27 @@ Working:
 - mPCIe WiFi
 - SeaBIOS 1.16.2
 - edk2 (MrChromebox' fork, uefipayload_202306)
- Internal flashing using dell-flash-unlock
+- Internal flashing

 Not working:
- S3 suspend: Possibly EC related
- Physical wireless switch - this triggers an SMI handler in the vendor
-  firmware which sends commands to the EC to enable/disable wireless
-  devices
- Battery reporting - needs ACPI code for the EC
- Brightness hotkeys - probably EC related
+- S3 suspend: It seems like the EC also controls the DRAM reset gate so
+  there may be a command that needs to be implemented for this
+- Physical Wireless switch
+- Battery reporting
+- Brightness hotkeys

 Unknown/untested:
 - Dock
 - eSATA
 - TPM
 - dGPU on non-UMA model
- Bluetooth module (not included on my system)

-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+[1] https://github.com/nic3-14159/e6400-flash-unlock

 Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
 ---
- src/mainboard/dell/e6430/Kconfig           |  44 +++++
+ src/mainboard/dell/e6430/Kconfig           |  37 ++++
 src/mainboard/dell/e6430/Kconfig.name      |   2 +
 src/mainboard/dell/e6430/Makefile.inc      |   6 +
 src/mainboard/dell/e6430/acpi/ec.asl       |   9 +
@@ -57,14 +55,14 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
 src/mainboard/dell/e6430/cmos.default      |   9 +
 src/mainboard/dell/e6430/cmos.layout       |  88 ++++++++++
 src/mainboard/dell/e6430/data.vbt          | Bin 0 -> 6144 bytes
- src/mainboard/dell/e6430/devicetree.cb     |  70 ++++++++
+ src/mainboard/dell/e6430/devicetree.cb     |  68 ++++++++
 src/mainboard/dell/e6430/dsdt.asl          |  30 ++++
- src/mainboard/dell/e6430/early_init.c      |  32 ++++
+ src/mainboard/dell/e6430/early_init.c      |  38 ++++
 src/mainboard/dell/e6430/gma-mainboard.ads |  20 +++
 src/mainboard/dell/e6430/gpio.c            | 192 +++++++++++++++++++++
 src/mainboard/dell/e6430/hda_verb.c        |  33 ++++
 src/mainboard/dell/e6430/mainboard.c       |  21 +++
- 18 files changed, 593 insertions(+)
+ 18 files changed, 590 insertions(+)
 create mode 100644 src/mainboard/dell/e6430/Kconfig
 create mode 100644 src/mainboard/dell/e6430/Kconfig.name
 create mode 100644 src/mainboard/dell/e6430/Makefile.inc
@@ -86,10 +84,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>

 diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
 new file mode 100644
-index 0000000000..e4c799803e
+index 0000000000..ea691aeb4e
 --- /dev/null
 +++ b/src/mainboard/dell/e6430/Kconfig
-@@ -0,0 +1,44 @@
+@@ -0,0 +1,37 @@
 +if BOARD_DELL_LATITUDE_E6430
 +
 +config BOARD_SPECIFIC_OPTIONS
@@ -112,27 +110,20 @@ index 0000000000..e4c799803e
 +	select SYSTEM_TYPE_LAPTOP
 +	select USE_NATIVE_RAMINIT
 +
-+config DRAM_RESET_GATE_GPIO
-+	default 60
-+
 +config MAINBOARD_DIR
 +	default "dell/e6430"
 +
 +config MAINBOARD_PART_NUMBER
 +	default "Latitude E6430"
 +
-+config PS2K_EISAID
-+	default "PNP0303"
-+
-+config PS2M_EISAID
-+	default "PNP0F13"
-+
-+config USBDEBUG_HCD_INDEX
-+	default 2
-+
 +config VGA_BIOS_ID
 +	default "8086,0166"
 +
+config DRAM_RESET_GATE_GPIO
+	default 60
+
+config USBDEBUG_HCD_INDEX
+	default 2
 +endif
 diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
 new file mode 100644
@@ -247,7 +238,7 @@ index 0000000000..2a5b30f2b7
 +me_state=Normal
 diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
 new file mode 100644
-index 0000000000..1aa7e77bce
+index 0000000000..e85ea4c661
 --- /dev/null
 +++ b/src/mainboard/dell/e6430/cmos.layout
@@ -0,0 +1,88 @@
@@ -278,7 +269,7 @@ index 0000000000..1aa7e77bce
 +# coreboot config options: EC
 +412	1	e	1	bluetooth
 +413	1	e	1	wwan
-+414	1	e	1	wlan
+415	1	e	1	wlan
 +
 +# coreboot config options: ME
 +424	1	e	14	me_state
@@ -383,10 +374,10 @@ HcmV?d00001

 diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
 new file mode 100644
-index 0000000000..054b01c5ac
+index 0000000000..56dd9e5fe2
 --- /dev/null
 +++ b/src/mainboard/dell/e6430/devicetree.cb
-@@ -0,0 +1,70 @@
+@@ -0,0 +1,68 @@
 +chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
 +	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
 +	register "gpu_cpu_backlight" = "0x00001312"
@@ -401,21 +392,19 @@ index 0000000000..054b01c5ac
 +	register "gpu_panel_power_up_delay" = "400"
 +	register "gpu_pch_backlight" = "0x13121312"
 +
-+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
-+
 +	device domain 0x0 on
 +		subsystemid 0x1028 0x0534 inherit
 +
-+		device ref host_bridge on end
-+		device ref peg10 off end
-+		device ref igd on end
+		device ref host_bridge on end # Host bridge
+		device ref peg10 off end # PEG
+		device ref igd on end # iGPU
 +
 +		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
 +			register "docking_supported" = "1"
 +			register "gen1_dec" = "0x007c0681"
 +			register "gen2_dec" = "0x005c0921"
 +			register "gen3_dec" = "0x003c07e1"
-+			register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
+			register "gen4_dec" = "0x007c0901"
 +			register "gpi0_routing" = "2"
 +			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
 +			register "pcie_port_coalesce" = "1"
@@ -427,33 +416,33 @@ index 0000000000..054b01c5ac
 +			register "xhci_overcurrent_mapping" = "0x00000c03"
 +			register "xhci_switchable_ports" = "0x0000000f"
 +
-+			device ref xhci		on end
-+			device ref mei1		on end
-+			device ref mei2		off end
-+			device ref me_ide_r	off end
-+			device ref me_kt	on end
-+			device ref gbe		on end
-+			device ref ehci2	on end
-+			device ref hda		on end
-+			device ref pcie_rp1	on end # WWAN Slot
-+			device ref pcie_rp2	on end # SLAN Slot
-+			device ref pcie_rp3	on end # ExpressCard
-+			device ref pcie_rp4	on end # E-Module (optical bay)
-+			device ref pcie_rp5	on end # Extra Half Mini PCIe slot
-+			device ref pcie_rp6	on end # SD/MMC Card Reader
-+			device ref pcie_rp7	off end
-+			device ref pcie_rp8	off end
-+			device ref ehci1	on end
-+			device ref pci_bridge	off end
-+			device ref lpc		on
+			device ref xhci		on end # USB 3.0 Controller
+			device ref mei1		on end # Management Engine Interface 1
+			device ref mei2		off end # Management Engine Interface 2
+			device ref me_ide_r	off end # Management Engine IDE-R
+			device ref me_kt	on end # Management Engine KT
+			device ref gbe		on end # Intel Gigabit Ethernet
+			device ref ehci2	on end # USB2 EHCI #2
+			device ref hda		on end # High Definition Audio
+			device ref pcie_rp1	on end # PCIe Port #1
+			device ref pcie_rp2	on end # PCIe Port #2
+			device ref pcie_rp3	on end # PCIe Port #3
+			device ref pcie_rp4	on end # PCIe Port #4
+			device ref pcie_rp5	off end # PCIe Port #5
+			device ref pcie_rp6	on end # PCIe Port #6
+			device ref pcie_rp7	off end # PCIe Port #7
+			device ref pcie_rp8	off end # PCIe Port #8
+			device ref ehci1	on end # USB2 EHCI #1
+			device ref pci_bridge	off end # PCI bridge
+			device ref lpc		on # LPC bridge
 +				chip ec/dell/mec5035
 +					device pnp ff.0 on end
 +				end
 +			end
-+			device ref sata1	on end
-+			device ref smbus	on end
-+			device ref sata2	off end
-+			device ref thermal	off end
+			device ref sata1	on end # SATA Controller 1
+			device ref smbus	on end # SMBus
+			device ref sata2	off end # SATA Controller 2
+			device ref thermal	off end # Thermal
 +		end
 +	end
 +end
@@ -495,16 +484,17 @@ index 0000000000..7d13c55b08
 +}
 diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
 new file mode 100644
-index 0000000000..d882c3d78b
+index 0000000000..7944157f59
 --- /dev/null
 +++ b/src/mainboard/dell/e6430/early_init.c
-@@ -0,0 +1,32 @@
+@@ -0,0 +1,38 @@
 +/* SPDX-License-Identifier: GPL-2.0-only */
 +
 +
 +#include <bootblock_common.h>
 +#include <device/pci_ops.h>
 +#include <ec/dell/mec5035/mec5035.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
 +#include <southbridge/intel/bd82x6x/pch.h>
 +
 +const struct southbridge_usb_port mainboard_usb_ports[] = {
@@ -526,11 +516,16 @@ index 0000000000..d882c3d78b
 +
 +void bootblock_mainboard_early_init(void)
 +{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
 +	mec5035_early_init();
 +}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}
 diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
 new file mode 100644
 index 0000000000..1310830c8e
@@ -822,5 +817,5 @@ index 0000000000..31e49802fc
 +	.enable_dev = mainboard_enable,
 +};
 -- 
-2.39.2
+2.42.0

@@ -1,19 +1,19 @@
-From 70262a5f4bf801814d68f8778ea89b5cd8ef8f9a Mon Sep 17 00:00:00 2001
+From 9f52555eac217623ad2edc72492f9ded6a5b538d Mon Sep 17 00:00:00 2001
 From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
 Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH 21/30] HACK: Disable coreboot related BL31 features
+Subject: [PATCH] HACK: Disable coreboot related BL31 features

 I don't know why, but removing this BL31 make argument lets gru-kevin
 power off properly when shut down from Linux. Needs investigation.
 ---
- src/arch/arm64/Makefile.mk | 3 ---
+ src/arch/arm64/Makefile.inc | 3 ---
 1 file changed, 3 deletions(-)

-diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
-index 538d254ace..18e451d63c 100644
--- a/src/arch/arm64/Makefile.mk
-+++ b/src/arch/arm64/Makefile.mk
-@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
+diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
+index 6b49743633c3..e1982d92cc5c 100644
+--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
+@@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
 # Always enable crash reporting, even on a release build
 BL31_MAKEARGS += CRASH_REPORTING=1
 
@@ -24,5 +24,5 @@ index 538d254ace..18e451d63c 100644
 BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
 
 -- 
-2.39.2
+2.40.1

@@ -1,7 +1,7 @@
-From 261454e47783b973b088e9dbea47bda02758dcb4 Mon Sep 17 00:00:00 2001
+From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 22 Oct 2023 15:02:25 +0100
-Subject: [PATCH 6/9] don't use github for the acpica download
+Subject: [PATCH 1/1] don't use github for the acpica download

 i have the tarball from a previous download, and i placed
 it on libreboot rsync, which then got mirrored to princeton.
@@ -22,7 +22,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
 1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 23a5caf2bb..36565a906c 100755
+index ebc9fcb49a..a857110b4b 100755
 --- a/util/crossgcc/buildgcc
 +++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
@@ -0,0 +1,341 @@
+From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 29 Oct 2023 01:18:50 +0000
+Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
+ value"
+
+This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
+
+NOTE:
+
+this is done instead of merging:
+https://review.coreboot.org/c/coreboot/+/78623
+
+which is still under review for now
+
+the patch i'm reverting is this one:
+https://review.coreboot.org/c/coreboot/+/78270
+
+this was actually only merged the day before i
+updated coreboot revs in lbmk to the 12 october rev,
+so there's no harm in quickly reverting this for now
+
+however, later on, we will rely on the other patch
+---
+ src/Kconfig                                   | 3 ++-
+ src/cpu/qemu-x86/Kconfig                      | 3 +++
+ src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
+ src/northbridge/amd/pi/Kconfig                | 4 ++++
+ src/soc/amd/picasso/Kconfig                   | 4 ++++
+ src/soc/amd/stoneyridge/Kconfig               | 4 ++++
+ src/soc/cavium/cn81xx/Kconfig                 | 3 +++
+ src/soc/intel/alderlake/Kconfig               | 5 +++++
+ src/soc/intel/apollolake/Kconfig              | 4 ++++
+ src/soc/intel/cannonlake/Kconfig              | 4 ++++
+ src/soc/intel/elkhartlake/Kconfig             | 4 ++++
+ src/soc/intel/jasperlake/Kconfig              | 4 ++++
+ src/soc/intel/meteorlake/Kconfig              | 5 +++++
+ src/soc/intel/skylake/Kconfig                 | 4 ++++
+ src/soc/intel/tigerlake/Kconfig               | 4 ++++
+ src/soc/intel/xeon_sp/Kconfig                 | 4 ++++
+ src/soc/intel/xeon_sp/cpx/Kconfig             | 4 ++++
+ src/soc/intel/xeon_sp/skx/Kconfig             | 4 ++++
+ src/soc/intel/xeon_sp/spr/Kconfig             | 4 ++++
+ src/soc/qualcomm/ipq40xx/Kconfig              | 4 ++++
+ 20 files changed, 77 insertions(+), 1 deletion(-)
+
+diff --git a/src/Kconfig b/src/Kconfig
+index ae8024089e..1549719dd0 100644
+--- a/src/Kconfig
+++ b/src/Kconfig
+@@ -751,7 +751,8 @@ config RTC
+ 
+ config HEAP_SIZE
+ 	hex
+-	default 0x100000
+	default 0x100000 if FLATTENED_DEVICE_TREE
+	default 0x4000
+ 
+ config STACK_SIZE
+ 	hex
+diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
+index 0fa999e1ac..f3e2c4cea9 100644
+--- a/src/cpu/qemu-x86/Kconfig
+++ b/src/cpu/qemu-x86/Kconfig
+@@ -35,4 +35,7 @@ config MAX_CPUS
+ 	default 32 if SMM_TSEG
+ 	default 4
+ 
+config HEAP_SIZE
+	default 0x8000
+
+ endif
+diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
+index 7bc3b0bcbb..7f9300f2a7 100644
+--- a/src/mainboard/sifive/hifive-unleashed/Kconfig
+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
+@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select FLATTENED_DEVICE_TREE
+ 	select SPI_SDCARD
+ 
+config HEAP_SIZE
+	default 0x10000
+
+ config MAINBOARD_DIR
+ 	default "sifive/hifive-unleashed"
+ 
+diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
+index 4ffe82a15f..4518db149b 100644
+--- a/src/northbridge/amd/pi/Kconfig
+++ b/src/northbridge/amd/pi/Kconfig
+@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
+ 	hex
+ 	default 0x200000
+ 
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+ endif # NORTHBRIDGE_AMD_PI
+diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
+index c33f287067..796fe4eb13 100644
+--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
+@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
+ 	bool
+ 	default n
+ 
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+ config SERIRQ_CONTINUOUS_MODE
+ 	bool
+ 	default n
+diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
+index 6ff135e6a8..9af7455bae 100644
+--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
+@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
+ 	bool
+ 	default n
+ 
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+ config EHCI_BAR
+ 	hex
+ 	default 0xfef00000
+diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
+index 77ca97202b..368581f8f1 100644
+--- a/src/soc/cavium/cn81xx/Kconfig
+++ b/src/soc/cavium/cn81xx/Kconfig
+@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
+ 	int
+ 	default 1
+ 
+config HEAP_SIZE
+	default 0x10000
+
+ config STACK_SIZE
+ 	default 0x2000
+ 
+diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
+index 4b960c1d22..82ec8f263e 100644
+--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
+@@ -215,6 +215,11 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000 if BMP_LOGO
+	default 0x10000
+
+ config GFX_GMA_DEFAULT_MMIO
+ 	default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
+ 
+diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
+index 78ec2987ce..bce935d800 100644
+--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
+@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
+ 	help
+ 	  Name of file to store in the IFWI region.
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 6
+diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
+index a42a3c365b..80237f9810 100644
+--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
+@@ -160,6 +160,10 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config NHLT_DMIC_1CH_16B
+ 	bool
+ 	depends on ACPI_NHLT
+diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
+index 3361c0ddb9..7f1c767379 100644
+--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
+@@ -104,6 +104,10 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x0
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 7
+diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
+index 3d84991e09..ff5def3263 100644
+--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
+@@ -106,6 +106,10 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 8
+diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
+index 590e8b80e1..48030a1911 100644
+--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
+@@ -197,6 +197,11 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000 if BMP_LOGO
+	default 0x10000
+
+ # Intel recommends reserving the PCIe TBT root port resources as below:
+ # - 42 buses
+ # - 194 MiB Non-prefetchable memory
+diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
+index e0df501460..d6a11363ee 100644
+--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
+@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
+ 	help
+ 	  If you set this option to n, will not use native SD controller.
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
+index c07a0d8365..0a4b7bfdb8 100644
+--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
+@@ -152,6 +152,10 @@ config IED_REGION_SIZE
+ config INTEL_TME
+ 	default n
+ 
+config HEAP_SIZE
+	hex
+	default 0x10000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 24 if SOC_INTEL_TIGERLAKE_PCH_H
+diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
+index e63bee5451..63ced01067 100644
+--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
+@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
+ config ECAM_MMCONF_BUS_NUMBER
+ 	default 256
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config HPET_MIN_TICKS
+ 	hex
+ 	default 0x80
+diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
+index ac166c3038..f54f7716b6 100644
+--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
+@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
+ 	hex
+ 	default 0x7C00
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config STACK_SIZE
+ 	hex
+ 	default 0x4000
+diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
+index 5d843878e1..c2c3d4e2e8 100644
+--- a/src/soc/intel/xeon_sp/skx/Kconfig
+++ b/src/soc/intel/xeon_sp/skx/Kconfig
+@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
+ 	hex
+ 	default 0x7C00
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
+index 43b87ade14..b1c4c783b7 100644
+--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
+@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
+ 	hex
+ 	default 0x8c00
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config STACK_SIZE
+ 	hex
+ 	default 0x4000
+diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
+index 0ce92731c0..0eabb00752 100644
+--- a/src/soc/qualcomm/ipq40xx/Kconfig
+++ b/src/soc/qualcomm/ipq40xx/Kconfig
+@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
+ 	help
+ 	  Path for utils to combine SBL_ELF and bootblock
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ endif
+-- 
+2.39.2
+
@@ -0,0 +1,77 @@
+From 27bf50138af0c5267581f8cc1f80676fb1836572 Mon Sep 17 00:00:00 2001
+From: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
+Date: Mon, 27 Mar 2017 22:05:16 +0200
+Subject: [PATCH 1/1] sb/intel/ibexpeak/setup_heci_uma.c: Add timeouts when
+ waiting for heci
+
+Since until now, the code running on the management engine is:
+- Signed by its manufacturer
+- Proprietary software, without corresponding source code
+It can desirable to run the least ammount possible of such
+code, which is what me_cleaner[1] enables.
+
+It does it by removing partitions of the management engine
+firmwares, however when doing so, the HECI interface might
+not be present anymore.
+
+So it is desirable not to have the RAM initialisation code
+wait forever for the HECI interface to appear.
+
+[1] https://github.com/corna/me_cleaner/
+
+MERGENOTE: Adapted from this patch:
+https://mail.coreboot.org/pipermail/coreboot/2017-March/083798.html
+Author on this version of the patch set to same author as in the
+linked one, with same date set, but the commit message is modified
+to match the new code path. Patch author Denis Carikli, but this
+versions of the patch was rebased from it by Leah Rowe on 29 Oct 2023.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/southbridge/intel/ibexpeak/setup_heci_uma.c | 14 ++++++++------
+ 1 file changed, 8 insertions(+), 6 deletions(-)
+
+diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
+index 572e5e7a76..3a68344d97 100644
+--- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c
+++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
+@@ -8,28 +8,30 @@
+ #include <southbridge/intel/ibexpeak/me.h>
+ #include <southbridge/intel/ibexpeak/pch.h>
+ #include <types.h>
+#include <delay.h>
+ 
+ #define HECIDEV PCI_DEV(0, 0x16, 0)
+ 
+-/* FIXME: add timeout.  */
+ static void wait_heci_ready(void)
+ {
+-	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8))	// = 0x8000000c
+-		;
+	int i = 1000*1000;
+ 
+	while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8)) /* = 0x8000000c */
+		udelay(1);
+ 	write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
+ }
+ 
+-/* FIXME: add timeout.  */
+ static void wait_heci_cb_avail(int len)
+ {
+	int i = 1000*1000;
+
+ 	union {
+ 		struct mei_csr csr;
+ 		u32 raw;
+ 	} csr;
+ 
+-	while (!(read32(DEFAULT_HECIBAR + 0xc) & 8))
+-		;
+	while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8))
+		udelay(1);
+ 
+ 	do {
+ 		csr.raw = read32(DEFAULT_HECIBAR + 0x4);
+-- 
+2.39.2
+
@@ -1,145 +0,0 @@
-From 88652afd52b0a8e0fc8bb1656e59d8ae4796d847 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Thu, 25 Jan 2024 14:30:03 +0000
-Subject: [PATCH 27/30] rebase dell/e6530 to newer coreboot code
-
-i diffed nicholas's current e6430 patch, versus the old one,
-prior to this revision update in lbmk, also cross referencing
-the original e6430 and e6530 patches, diffing them, and the
-result in this patch. most notably, spd data is now defined in
-the devicetree, instead of early_init.c as per:
-
-commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da
-Author: Keith Hui <buurin@gmail.com>
-Date:   Sat Jul 22 12:49:05 2023 -0400
-    mb/*: Update SPD mapping for sandybridge boards
-
-This should work fine. Will test after this builds.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- src/mainboard/dell/e6530/Kconfig       | 15 +++++++++++----
- src/mainboard/dell/e6530/cmos.layout   |  2 +-
- src/mainboard/dell/e6530/devicetree.cb |  8 +++++---
- src/mainboard/dell/e6530/early_init.c  | 12 +++---------
- 4 files changed, 20 insertions(+), 17 deletions(-)
-
-diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
-index 582adddbd4..a104566890 100644
--- a/src/mainboard/dell/e6530/Kconfig
-+++ b/src/mainboard/dell/e6530/Kconfig
-@@ -20,18 +20,25 @@ config BOARD_SPECIFIC_OPTIONS
- 	select SYSTEM_TYPE_LAPTOP
- 	select USE_NATIVE_RAMINIT
- 
-+config DRAM_RESET_GATE_GPIO
-+	default 60
-+
- config MAINBOARD_DIR
- 	default "dell/e6530"
- 
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E6530"
- 
-config VGA_BIOS_ID
-	default "8086,0166"
-+config PS2K_EISAID
-+	default "PNP0303"
- 
-config DRAM_RESET_GATE_GPIO
-	default 60
-+config PS2M_EISAID
-+	default "PNP0F13"
- 
- config USBDEBUG_HCD_INDEX
- 	default 2
-+
-+config VGA_BIOS_ID
-+	default "8086,0166"
-+
- endif
-diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
-index e85ea4c661..1aa7e77bce 100644
--- a/src/mainboard/dell/e6530/cmos.layout
-+++ b/src/mainboard/dell/e6530/cmos.layout
-@@ -25,7 +25,7 @@ entries
- # coreboot config options: EC
- 412	1	e	1	bluetooth
- 413	1	e	1	wwan
-415	1	e	1	wlan
-+414	1	e	1	wlan
- 
- # coreboot config options: ME
- 424	1	e	14	me_state
-diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
-index 96eed178c5..37135bcf0f 100644
--- a/src/mainboard/dell/e6530/devicetree.cb
-+++ b/src/mainboard/dell/e6530/devicetree.cb
-@@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- 	register "gpu_panel_power_up_delay" = "400"
- 	register "gpu_pch_backlight" = "0x13121312"
- 
-+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
-+
- 	device domain 0x0 on
- 		subsystemid 0x1028 0x0535 inherit
- 
-@@ -24,7 +26,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- 			register "gen1_dec" = "0x007c0681"
- 			register "gen2_dec" = "0x005c0921"
- 			register "gen3_dec" = "0x003c07e1"
-			register "gen4_dec" = "0x007c0901"
-+			register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
- 			register "gpi0_routing" = "2"
- 			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
- 			register "pcie_port_coalesce" = "1"
-@@ -37,7 +39,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- 			register "xhci_switchable_ports" = "0x0000000f"
- 
- 			device ref xhci		on end # USB 3.0 Controller
-			device ref mei1		off end # Management Engine Interface 1
-+			device ref mei1		on end # Management Engine Interface 1
- 			device ref mei2		off end # Management Engine Interface 2
- 			device ref me_ide_r	off end # Management Engine IDE-R
- 			device ref me_kt	on end # Management Engine KT
-@@ -48,7 +50,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- 			device ref pcie_rp2	on end # PCIe Port #2
- 			device ref pcie_rp3	on end # PCIe Port #3
- 			device ref pcie_rp4	on end # PCIe Port #4
-			device ref pcie_rp5	off end # PCIe Port #5
-+			device ref pcie_rp5	on end # PCIe Port #5
- 			device ref pcie_rp6	on end # PCIe Port #6
- 			device ref pcie_rp7	off end # PCIe Port #7
- 			device ref pcie_rp8	off end # PCIe Port #8
-diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
-index d57f48e7f1..2b40f6963f 100644
--- a/src/mainboard/dell/e6530/early_init.c
-+++ b/src/mainboard/dell/e6530/early_init.c
-@@ -4,7 +4,6 @@
- #include <bootblock_common.h>
- #include <device/pci_ops.h>
- #include <ec/dell/mec5035/mec5035.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
- #include <southbridge/intel/bd82x6x/pch.h>
- 
- const struct southbridge_usb_port mainboard_usb_ports[] = {
-@@ -26,13 +25,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
- 
- void bootblock_mainboard_early_init(void)
- {
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
- 	mec5035_early_init();
- }
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	read_spd(&spd[0], 0x50, id_only);
-	read_spd(&spd[2], 0x52, id_only);
-}
-- 
-2.39.2
-
@@ -1,54 +0,0 @@
-From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Thu, 25 Jan 2024 14:37:30 +0000
-Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree
-
-we neuter anyway. disabling it in devicetree will prevent linux
-from ever trying to use it or load a driver for it, and thus
-might prevent benign error messages from appearing in dmesg.
-
-this change was suggested by nicholas when asked on irc.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- src/mainboard/dell/e6430/devicetree.cb | 4 ++--
- src/mainboard/dell/e6530/devicetree.cb | 4 ++--
- 2 files changed, 4 insertions(+), 4 deletions(-)
-
-diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
-index 054b01c5ac..2b8574c984 100644
--- a/src/mainboard/dell/e6430/devicetree.cb
-+++ b/src/mainboard/dell/e6430/devicetree.cb
-@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- 			register "xhci_switchable_ports" = "0x0000000f"
- 
- 			device ref xhci		on end
-			device ref mei1		on end
-+			device ref mei1		off end
- 			device ref mei2		off end
- 			device ref me_ide_r	off end
-			device ref me_kt	on end
-+			device ref me_kt	off end
- 			device ref gbe		on end
- 			device ref ehci2	on end
- 			device ref hda		on end
-diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
-index 37135bcf0f..010200bb6d 100644
--- a/src/mainboard/dell/e6530/devicetree.cb
-+++ b/src/mainboard/dell/e6530/devicetree.cb
-@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
- 			register "xhci_switchable_ports" = "0x0000000f"
- 
- 			device ref xhci		on end # USB 3.0 Controller
-			device ref mei1		on end # Management Engine Interface 1
-+			device ref mei1		off end # Management Engine Interface 1
- 			device ref mei2		off end # Management Engine Interface 2
- 			device ref me_ide_r	off end # Management Engine IDE-R
-			device ref me_kt	on end # Management Engine KT
-+			device ref me_kt	off end # Management Engine KT
- 			device ref gbe		on end # Intel Gigabit Ethernet
- 			device ref ehci2	on end # USB2 EHCI #2
- 			device ref hda		on end # High Definition Audio
-- 
-2.39.2
-
@@ -1,7 +1,7 @@
-From ad812d008d570c1655bff13a9026f39a9efdcbc9 Mon Sep 17 00:00:00 2001
+From 0721e7e984bc83861bce3d47632b717848673749 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Tue, 31 Oct 2023 18:24:39 +0000
-Subject: [PATCH 23/30] crank up vram allocation on more intel boards
+Subject: [PATCH 1/1] crank up vram allocation on more intel boards

 these were added to libreboot, and it's a policy of
 libreboot to max out the vram settings. this was
@@ -1,873 +0,0 @@
-From 4e0b62e6f0977cf922b1947955538ddca63bb954 Mon Sep 17 00:00:00 2001
-From: Riku Viitanen <riku.viitanen@protonmail.com>
-Date: Sat, 23 Dec 2023 19:02:10 +0200
-Subject: [PATCH 30/30] mb/hp: Add Compaq Elite 8300 CMT port
-
-Based on autoport and Z220 SuperIO code.
-
-With SeaBIOS and Nouveau on Debian, only nomodeset works with GTX 780
-(must use proprietary driver instead).
-
-Tested by xilynx / spot_ on #libreboot:
- i3-3220, native raminit 2x2GB, M378B5773DH0-CH9 + MT8JTF25664AZ-1G6M1
- Celeron G1620, native raminit 1x4GB, MT8JTF51264AZ-1G6E1
- Booting Debian with Linux 6.1.0-16-amd64 via SeaBIOS
- All SATA ports
- Audio: internal speaker, headphone and microphone plugs
- Rebooting
- S3 suspend and wake
- libgfxinit: VGA, DisplayPort
- Ethernet
- Super I/O: fan speeds stay in control
- GPU in PEG slot
-
-Untested:
- EHCI debugging
- Other PCI/PCIe slots
- PS/2
- Serial, parallel ports
-
-Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363
-Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
---
- .../hp/compaq_elite_8300_cmt/Kconfig          |  39 ++++
- .../hp/compaq_elite_8300_cmt/Kconfig.name     |   2 +
- .../hp/compaq_elite_8300_cmt/Makefile.inc     |   7 +
- .../hp/compaq_elite_8300_cmt/acpi/ec.asl      |   1 +
- .../compaq_elite_8300_cmt/acpi/platform.asl   |  10 +
- .../hp/compaq_elite_8300_cmt/acpi/superio.asl |  29 +++
- .../hp/compaq_elite_8300_cmt/acpi_tables.c    |  12 ++
- .../hp/compaq_elite_8300_cmt/board_info.txt   |   5 +
- .../hp/compaq_elite_8300_cmt/cmos.default     |   7 +
- .../hp/compaq_elite_8300_cmt/cmos.layout      |  74 +++++++
- .../hp/compaq_elite_8300_cmt/data.vbt         | Bin 0 -> 3902 bytes
- .../hp/compaq_elite_8300_cmt/devicetree.cb    | 161 +++++++++++++++
- .../hp/compaq_elite_8300_cmt/dsdt.asl         |  26 +++
- .../hp/compaq_elite_8300_cmt/early_init.c     |  31 +++
- .../compaq_elite_8300_cmt/gma-mainboard.ads   |  17 ++
- src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++
- .../hp/compaq_elite_8300_cmt/hda_verb.c       |  33 +++
- .../hp/compaq_elite_8300_cmt/mainboard.c      |  16 ++
- 18 files changed, 661 insertions(+)
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.default
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/data.vbt
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/gpio.c
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c
-
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
-new file mode 100644
-index 0000000000..d2bfd35dc4
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
-@@ -0,0 +1,39 @@
-+if BOARD_HP_COMPAQ_ELITE_8300_CMT
-+
-+config BOARD_SPECIFIC_OPTIONS
-+	def_bool y
-+	select BOARD_ROMSIZE_KB_16384
-+	select HAVE_ACPI_RESUME
-+	select HAVE_ACPI_TABLES
-+	select HAVE_CMOS_DEFAULT
-+	select HAVE_OPTION_TABLE
-+	select INTEL_GMA_HAVE_VBT
-+	select INTEL_INT15
-+	select MAINBOARD_HAS_TPM1
-+	select MAINBOARD_HAS_LIBGFXINIT
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select MEMORY_MAPPED_TPM
-+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+	select SERIRQ_CONTINUOUS_MODE
-+	select SOUTHBRIDGE_INTEL_C216
-+	select SUPERIO_NUVOTON_NPCD378
-+	select USE_NATIVE_RAMINIT
-+
-+config CBFS_SIZE
-+	default 0x570000
-+
-+config MAINBOARD_DIR
-+	default "hp/compaq_elite_8300_cmt"
-+
-+config MAINBOARD_PART_NUMBER
-+	default "HP Compaq Elite 8300 CMT"
-+
-+config VGA_BIOS_ID
-+	default "8086,0152"
-+
-+config DRAM_RESET_GATE_GPIO
-+	default 60
-+
-+config USBDEBUG_HCD_INDEX # FIXME: check this
-+	default 2
-+endif
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
-new file mode 100644
-index 0000000000..bd399b1e76
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_HP_COMPAQ_ELITE_8300_CMT
-+	bool "Compaq Elite 8300 CMT"
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
-new file mode 100644
-index 0000000000..fb492d3583
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
-@@ -0,0 +1,7 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
-new file mode 100644
-index 0000000000..73fa78ef14
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
-@@ -0,0 +1 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
-new file mode 100644
-index 0000000000..aff432b6f4
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
-@@ -0,0 +1,10 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+	Return(Package() {0, 0})
-+}
-+
-+Method(_PTS, 1)
-+{
-+}
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
-new file mode 100644
-index 0000000000..54f8e3fe95
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
-@@ -0,0 +1,29 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */
-+
-+#include <superio/nuvoton/npcd378/acpi/superio.asl>
-+
-+Scope (\_GPE)
-+{
-+	Method (_L0D, 0, NotSerialized)
-+	{
-+		Notify (\_SB.PCI0.EHC1, 0x02)
-+		Notify (\_SB.PCI0.EHC2, 0x02)
-+		//FIXME: Add GBE device
-+		//Notify (\_SB.PCI0.GBE, 0x02)
-+	}
-+
-+	Method (_L09, 0, NotSerialized)
-+	{
-+		Notify (\_SB.PCI0.RP01, 0x02)
-+		Notify (\_SB.PCI0.RP02, 0x02)
-+		Notify (\_SB.PCI0.RP03, 0x02)
-+		Notify (\_SB.PCI0.RP04, 0x02)
-+		Notify (\_SB.PCI0.RP05, 0x02)
-+		Notify (\_SB.PCI0.RP06, 0x02)
-+		Notify (\_SB.PCI0.RP07, 0x02)
-+		Notify (\_SB.PCI0.RP08, 0x02)
-+		Notify (\_SB.PCI0.PEGP, 0x02)
-+	}
-+}
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c
-new file mode 100644
-index 0000000000..8f4f83b826
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi_gnvs.h>
-+#include <soc/nvs.h>
-+
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+	/* Temperature at which OS will shutdown */
-+	gnvs->tcrt = 100;
-+	/* Temperature at which OS will throttle CPU */
-+	gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt
-new file mode 100644
-index 0000000000..16c29e82d8
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt
-@@ -0,0 +1,5 @@
-+Category: desktop
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-+Release year: 2012
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default
-new file mode 100644
-index 0000000000..6d27a79c66
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default
-@@ -0,0 +1,7 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Enable
-+nmi=Enable
-+sata_mode=AHCI
-+gfx_uma_size=32M
-+psu_fan_lvl=3
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout
-new file mode 100644
-index 0000000000..1fc83b1a55
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout
-@@ -0,0 +1,74 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0	120	r	0	reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384	1	e	4	boot_option
-+388	4	h	0	reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395	4	e	6	debug_level
-+400	3	h	0	psu_fan_lvl
-+
-+# coreboot config options: southbridge
-+408	1	e	1	nmi
-+409	2	e	7	power_on_after_fail
-+
-+421	1	e	9	sata_mode
-+
-+# coreboot config options: northbridge
-+432	3	e	11	gfx_uma_size
-+
-+448	128	r	0	vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896	32	r	0	mrc_scrambler_seed
-+928	32	r	0	mrc_scrambler_seed_s3
-+960	16	r	0	mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984	16	h	0	check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID	value	text
-+1	0	Disable
-+1	1	Enable
-+2	0	Enable
-+2	1	Disable
-+4	0	Fallback
-+4	1	Normal
-+6	0	Emergency
-+6	1	Alert
-+6	2	Critical
-+6	3	Error
-+6	4	Warning
-+6	5	Notice
-+6	6	Info
-+6	7	Debug
-+6	8	Spew
-+7	0	Disable
-+7	1	Enable
-+7	2	Keep
-+9	0	AHCI
-+9	1	IDE
-+11	0	32M
-+11	1	64M
-+11	2	96M
-+11	3	128M
-+11	4	160M
-+11	5	192M
-+11	6	224M
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 415 984
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt b/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..ba627e152b65d779a80529d3811ec4d21c1b1e54
-GIT binary patch
-literal 3902
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-z<tLDc9kdaQ30aLnL^K;s2=dhMWTFo|nZ_7XjUmSPK!^{95W@p8ks#}tpO&8zIx!OQ
-zPQE$ko;~;Lz2}~D=XOmtlA-CLNM|A&X^#!0H)V!X1yJCH+Hrg@ZIQ%qdRr`<32%!e
-zhohV5IamQTwRf%o6o9FhLR}l4OH3XpP6S4SG(9$1II_L8yRfU+nK)!=G!;$I@QxkD
-ziDGH&K(Rp6*_Xmpr<F+L;O>b69XhyYd$H6<buRR#UELiUx+zsQbar)jhLo-lr6HwH
-z>Fo<WE0Nehba-<rkql=N!$Wj<l*SV2a5_D(Ig)&trbdV3iAW+d5R-_pl<3~6Bc<KD
-z#t+ayG>9yU(vE~()R;1j?k!Dq(D1|r9o2pI)6wGoV(Cz^&><0>;1cWR7zP*~YL5XE
-z{3`?=k6Yy2an&85Zl2-7jM~D`7^g}MH^6WOPE9askfBLVUBl5fj(Wi%F%Ax(<(|k=
-zUH4c9hXO|5?0UW22lb}G1;Fb@mzSZ8u5fTU59si@;V}EXTQ}(rl%Wn?F&a92X)&+>
-zPTj@>Ls7r4(ffK2={zn6t_hS-cTaC$zZ!`R#y2KYqnT`O>nqx^H{P7_!|gKQVi}A&
-z)G!L9*Z>@59dMlOh4owoes{Vd<dPwV$RfrOM_mMtBi==PggB45i1-TeHR314Rm63~
-z9|&+0AczJ;Ga`TpA^H)6h!kQgqJWr0I1j?@szU?Z5NsM_$vRVlmxGf*(9T-+vzFa+
-z!`K`kmJ}>$kl1)tt1cJZseb2!YSsO`J_8jQ^hAhROmRyl4au@8tDixs`{k^Dwd%=Z
-zH-yjQdy~%q^YKY<!Z~QsaFSLvP<_4(KebAii%moAUIzzXdbGph$OYv=h6VegT-HIX
-zhmBa>th;}v$r!Z-pnAN<1I)+#R``=|huU|*W1ew~tpBFsG0q;_jCFT6Ulxt*TNv8#
-z2{`>`$JM`Jd{F+EzpU7VIlvml?AFW1Xv$0tKyom(Ej2b-oERG0Q?%Jx8HYk6s9{*E
-z_)hegWIm-8PLF`1DpU2QrTKj4;VUElwQBD4f+hZ<s%)PPsp_Q#i!T5@)2taxv1ghG
-z<B&&<DI4jDn$!FOh>Zbggj@JDLYbjpK69X2PaAVr^Xn{6e+%<?63)ABGAHVvOwA0G
-zop-g`)B~42TA5y1<#p#*n`4^oSOPu_>i&oRk>LBlzUQG|c;s(9<VO#^<&i}~RuI}x
-z<RL<GguYJXG9hOOy+q_62>FFjhafiyq*<UbLCy*!FVMFH`LsYj73iEG|16MS1xiG@
-zNhE7UniS<%MKUhZlcHP^$pw+li}F>GTo<V<$!jFiA<>K^@07@tL{CZbd5K(<q}Cgp
-z=D5OWb(o)+1@4lFyO?u`hP=smQS!Cx@SCx8`ItCXGEp|?Se~I$OQ9>*L<3rb71Ew*
-zhn0l-*|a>v(n`=1+Du-&m2f&k|07qiv~u)9FuttfVcu_x;V>QXdsXjZ?db(%oNhK5
-zme#7yVBD-k)j4Zp4ohoWFJ0rv5wpCVNbYROUKoL9Ww31Rg%2ZHHV$2!ik&#T)={qH
-z{mrUEty8JFXPPS;w@^`Y*;z%PU#m>bK7$Oci}}Epjc<@x;b&~*!<k@Zeq?5~lKODv
-zA_EJ8u45$aFet6+Tz;mY_(sgz72qmZ5DkWZn3D#BWHRv7#wxD)p^~C26;X-mqrjL$
-z8S4>Op}BgEe0X$iI{Gx<zTS2<*M4^|Sg17^@EYY@zAl0)<Ta?zd%bn~D02?r)iu%P
-wm+F7xwtgQt<KA_UyAYqlTkT_cS089?Pr=)R7|a9^*a9j1U$>1p1;4R>1E3jwQUCw|
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-new file mode 100644
-index 0000000000..f4efabd792
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-@@ -0,0 +1,161 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+
-+chip northbridge/intel/sandybridge
-+	register "gfx.use_spread_spectrum_clock" = "0"
-+	register "gpu_dp_b_hotplug" = "0"
-+	register "gpu_dp_c_hotplug" = "0"
-+	register "gpu_dp_d_hotplug" = "0"
-+	# BTX mainboard: Reversed mapping
-+	register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}"
-+	device domain 0 on
-+		subsystemid 0x103c 0x3396 inherit
-+
-+		device ref host_bridge on end # Host bridge Host bridge
-+		device ref peg10 on end # PEG
-+		device ref igd on end # iGPU
-+
-+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-+			register "docking_supported" = "0"
-+			register "gen1_dec" = "0x00fc0a01"
-+			register "gen2_dec" = "0x00fc0801"
-+			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
-+			register "pcie_port_coalesce" = "1"
-+			register "sata_interface_speed_support" = "0x3"
-+			register "sata_port_map" = "0x1f"
-+			register "spi_lvscc" = "0x2005"
-+			register "spi_uvscc" = "0x2005"
-+			register "superspeed_capable_ports" = "0x0000000f"
-+			register "xhci_overcurrent_mapping" = "0x00000c03"
-+			register "xhci_switchable_ports" = "0x0000000f"
-+
-+			device ref xhci on   end # USB 3.0 Controller
-+			device ref mei1 off  end # Management Engine Interface 1
-+			device ref mei2 off  end
-+			device ref me_ide_r off end
-+			device ref me_kt off end
-+			device ref gbe on    end # Intel Gigabit Ethernet
-+			device ref ehci1 on  end # USB2 EHCI #1
-+			device ref ehci2 on  end # USB2 EHCI #2
-+			device ref hda on    end # High Definition Audio
-+			device ref sata1 on  end # SATA Controller 1
-+			device ref sata2 off end # SATA Controller 2
-+			device ref smbus on  end # SMBus
-+
-+			device ref pcie_rp1 on end
-+			device ref pcie_rp2 on end
-+			device ref pcie_rp3 on end
-+			device ref pcie_rp4 on end
-+			device ref pcie_rp5 on end
-+			device ref pcie_rp5 on end
-+			device ref pcie_rp7 on end
-+			device ref pcie_rp8 on end
-+
-+			device ref pci_bridge on  end
-+			device ref lpc on # LPC bridge
-+				chip superio/common # copied from Z220
-+					device pnp 2e.ff on # passes SIO base addr to SSDT gen
-+						chip superio/nuvoton/npcd378
-+							device pnp 2e.0 off end		# Floppy
-+							device pnp 2e.1 on		# Parallel port
-+								# global
-+
-+								# serialice: Vendor writes:
-+								irq 0x14 = 0x9c
-+								irq 0x1c = 0xa8
-+								irq 0x1d = 0x08
-+								irq 0x22 = 0x3f
-+								irq 0x1a = 0xb0
-+								# dumped from superiotool:
-+								irq 0x1b = 0x1e
-+								irq 0x27 = 0x08
-+								irq 0x2a = 0x20
-+								irq 0x2d = 0x01
-+								# parallel port
-+								io 0x60 = 0x378
-+								irq 0x70 = 0x07
-+								drq 0x74 = 0x01
-+							end
-+							device pnp 2e.2 off		# COM1
-+								io 0x60 = 0x2f8
-+								irq 0x70 = 3
-+							end
-+							device pnp 2e.3 on		# COM2, IR
-+								io 0x60 = 0x3f8
-+								irq 0x70 = 4
-+							end
-+							device pnp 2e.4 on		# LED control
-+								io 0x60 = 0x600
-+								# IOBASE[0h] = bit0 LED red / green
-+								# IOBASE[0h] = bit1-4 LED PWM duty cycle
-+								# IOBASE[1h] = bit6 SWCC
-+
-+								io 0x62 = 0x610
-+								# IOBASE [0h] = GPES
-+								# IOBASE [1h] = GPEE
-+								# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
-+								# IOBASE [8h:bh] = GPS
-+								# IOBASE [ch:fh] = GPE
-+							end
-+							device pnp 2e.5 on		# Mouse
-+								irq 0x70 = 0xc
-+							end
-+							device pnp 2e.6 on		# Keyboard
-+								io 0x60 = 0x0060
-+								io 0x62 = 0x0064
-+								irq 0x70 = 0x01
-+								# serialice: Vendor writes:
-+								drq 0xf0 = 0x40
-+							end
-+							device pnp 2e.7 on		#  WDT ?
-+								io 0x60 = 0x620
-+							end
-+							device pnp 2e.8 on		# HWM
-+								io 0x60 = 0x800
-+								# IOBASE[0h:feh] HWM page
-+								# IOBASE[ffh] bit0-bit3 page selector
-+
-+								drq 0xf0 = 0x20
-+								drq 0xf1 = 0x01
-+								drq 0xf2 = 0x40
-+								drq 0xf3 = 0x01
-+
-+								drq 0xf4 = 0x66
-+								drq 0xf5 = 0x67
-+								drq 0xf6 = 0x66
-+								drq 0xf7 = 0x01
-+							end
-+							device pnp 2e.f on		# GPIO OD ?
-+								drq 0xf1 = 0x97
-+								drq 0xf2 = 0x01
-+								drq 0xf5 = 0x08
-+								drq 0xfe = 0x80
-+							end
-+							device pnp 2e.15 on		# BUS ?
-+								io 0x60 = 0x0680
-+								io 0x62 = 0x0690
-+							end
-+							device pnp 2e.1c on		# Suspend Control ?
-+								io 0x60 = 0x640
-+								# writing to IOBASE[5h]
-+								#  0x0: Power off
-+								#  0x9: Power off and bricked until CMOS battery removed
-+							end
-+							device pnp 2e.1e on		# GPIO ?
-+								io 0x60 = 0x660
-+								drq 0xf4 = 0x01
-+								# skip the following, as it
-+								# looks like remapped registers
-+								#drq 0xf5 = 0x06
-+								#drq 0xf6 = 0x60
-+								#drq 0xfe = 0x03
-+							end
-+						end
-+					end
-+				end
-+				chip drivers/pc80/tpm
-+					device pnp 4e.0 on end          # TPM module
-+				end
-+			end
-+		end
-+	end
-+end
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl
-new file mode 100644
-index 0000000000..e8e2b3a3e5
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl
-@@ -0,0 +1,26 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi.h>
-+
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	ACPI_DSDT_REV_2,
-+	OEM_ID,
-+	ACPI_TABLE_CREATOR,
-+	0x20141018	/* OEM revision */
-+)
-+{
-+	#include <acpi/dsdt_top.asl>
-+	#include "acpi/platform.asl"
-+	#include <cpu/intel/common/acpi/cpu.asl>
-+	#include <southbridge/intel/common/acpi/platform.asl>
-+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-+	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+
-+	Device (\_SB.PCI0)
-+	{
-+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-+	}
-+}
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
-new file mode 100644
-index 0000000000..99b7891c70
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <superio/nuvoton/npcd378/npcd378.h>
-+#include <superio/nuvoton/common/nuvoton.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+	{ 1, 0, 0 },
-+	{ 1, 0, 0 },
-+	{ 1, 0, 1 },
-+	{ 1, 0, 1 },
-+	{ 1, 0, 2 },
-+	{ 1, 0, 2 },
-+	{ 1, 0, 3 },
-+	{ 1, 0, 3 },
-+	{ 1, 0, 4 },
-+	{ 1, 0, 4 },
-+	{ 1, 0, 6 },
-+	{ 1, 0, 5 },
-+	{ 1, 0, 5 },
-+	{ 1, 0, 6 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	if (CONFIG(CONSOLE_SERIAL))
-+		nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-+}
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads
-new file mode 100644
-index 0000000000..686f7d44db
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads
-@@ -0,0 +1,17 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (DP2,
-+      HDMI2,
-+      Analog,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c
-new file mode 100644
-index 0000000000..2ae852ae51
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c
-@@ -0,0 +1,191 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_GPIO,
-+	.gpio2 = GPIO_MODE_NATIVE,
-+	.gpio3 = GPIO_MODE_NATIVE,
-+	.gpio4 = GPIO_MODE_NATIVE,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_GPIO,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_NATIVE,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_NATIVE,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio1 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio11 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_OUTPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_OUTPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_OUTPUT,
-+	.gpio31 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio15 = GPIO_LEVEL_LOW,
-+	.gpio17 = GPIO_LEVEL_LOW,
-+	.gpio28 = GPIO_LEVEL_LOW,
-+	.gpio29 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio1 = GPIO_INVERT,
-+	.gpio6 = GPIO_INVERT,
-+	.gpio11 = GPIO_INVERT,
-+	.gpio13 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_GPIO,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_GPIO,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_GPIO,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_NATIVE,
-+	.gpio52 = GPIO_MODE_NATIVE,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_NATIVE,
-+	.gpio61 = GPIO_MODE_GPIO,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio32 = GPIO_DIR_INPUT,
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_INPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio43 = GPIO_DIR_INPUT,
-+	.gpio46 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio61 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_GPIO,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_OUTPUT,
-+	.gpio72 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+	.gpio71 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c
-new file mode 100644
-index 0000000000..a1eafcda68
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x10ec0221,	/* Codec Vendor / Device ID: Realtek */
-+	0x103c3396,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x103c3396),
-+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
-+	AZALIA_PIN_CFG(0, 0x14, 0x01014020),
-+	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
-+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
-+	AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f),
-+	AZALIA_PIN_CFG(0, 0x1b, 0x01813c30),
-+	AZALIA_PIN_CFG(0, 0x1d, 0x415901f0),
-+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
-+	AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
-+
-+	0x80862806,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x58560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x58560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c
-new file mode 100644
-index 0000000000..8dbd95ef96
--- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/device.h>
-+#include <drivers/intel/gma/int15.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
-+					GMA_INT15_PANEL_FIT_DEFAULT,
-+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+	.enable_dev = mainboard_enable,
-+};
-- 
-2.39.2
-
@@ -1,7 +1,7 @@
-From a9ab864aee1be7a03926443ddc94e4c5012719ba Mon Sep 17 00:00:00 2001
+From e712efdaf46a09a107c88a273d9b00effb4d977e Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 11:41:41 +0000
-Subject: [PATCH 24/30] dell/e6430: use ME Soft Temporary Disable
+Subject: [PATCH 1/1] dell/e6430: use ME Soft Temporary Disable

 i overlooked this. it's set on other boards.

@@ -1,923 +0,0 @@
-From 38a713eb071dd9c1b7d5092ce686537e5d9266f5 Mon Sep 17 00:00:00 2001
-From: Mate Kukri <kukri.mate@gmail.com>
-Date: Mon, 4 Dec 2023 21:34:18 +0000
-Subject: [PATCH 1/1] mb/dell: Add OptiPlex 7020/9020 port
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-The OptiPlex 7020 and 9020 use physically identical motherboards.
-
-Each model comes in the following form factors:
- 7020: SFF, MT
- 9020: USFF (not currently supported), SFF, MT
-
-(7020 SFF) Boots Linux and Windows 10:
- Tested with an i3-4160 and i5-4460
- DRAM init works using the MRC (4G, 4G+4G)
- iGPU init works using libgfxinit (VGA, 2x DP)
- PCIe 16x: tested, ok
- PCIe 4x: tested, ok
- All USB2 and USB3 ports work
- SMSC SCH5555 Super I/O: serial works, PS/2 untested
- Audio: back and front output works, internal speaker works,
-         mic inputs untested
- Ethernet: tested, works
-
-(9020 MT)
- Tested by Michael Büchler (thanks for the overridetree)
-
-Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a
-Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
---
- src/mainboard/dell/optiplex_9020/Kconfig      |  34 +++
- src/mainboard/dell/optiplex_9020/Kconfig.name |  11 +
- src/mainboard/dell/optiplex_9020/Makefile.inc |   5 +
- src/mainboard/dell/optiplex_9020/acpi/ec.asl  |   3 +
- .../dell/optiplex_9020/acpi/platform.asl      |  11 +
- .../dell/optiplex_9020/acpi/superio.asl       |   3 +
- .../dell/optiplex_9020/board_info.txt         |   8 +
- src/mainboard/dell/optiplex_9020/bootblock.c  | 116 ++++++++++
- src/mainboard/dell/optiplex_9020/cmos.default |   4 +
- src/mainboard/dell/optiplex_9020/cmos.layout  |  58 +++++
- src/mainboard/dell/optiplex_9020/data.vbt     | Bin 0 -> 4409 bytes
- .../dell/optiplex_9020/devicetree.cb          |  80 +++++++
- src/mainboard/dell/optiplex_9020/dsdt.asl     |  25 ++
- .../dell/optiplex_9020/gma-mainboard.ads      |  18 ++
- src/mainboard/dell/optiplex_9020/gpio.c       | 217 ++++++++++++++++++
- src/mainboard/dell/optiplex_9020/hda_verb.c   |  27 +++
- src/mainboard/dell/optiplex_9020/mainboard.c  |  15 ++
- .../dell/optiplex_9020/overridetree_mt.cb     |  10 +
- src/mainboard/dell/optiplex_9020/romstage.c   |  53 +++++
- 19 files changed, 698 insertions(+)
- create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig
- create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig.name
- create mode 100644 src/mainboard/dell/optiplex_9020/Makefile.inc
- create mode 100644 src/mainboard/dell/optiplex_9020/acpi/ec.asl
- create mode 100644 src/mainboard/dell/optiplex_9020/acpi/platform.asl
- create mode 100644 src/mainboard/dell/optiplex_9020/acpi/superio.asl
- create mode 100644 src/mainboard/dell/optiplex_9020/board_info.txt
- create mode 100644 src/mainboard/dell/optiplex_9020/bootblock.c
- create mode 100644 src/mainboard/dell/optiplex_9020/cmos.default
- create mode 100644 src/mainboard/dell/optiplex_9020/cmos.layout
- create mode 100644 src/mainboard/dell/optiplex_9020/data.vbt
- create mode 100644 src/mainboard/dell/optiplex_9020/devicetree.cb
- create mode 100644 src/mainboard/dell/optiplex_9020/dsdt.asl
- create mode 100644 src/mainboard/dell/optiplex_9020/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/optiplex_9020/gpio.c
- create mode 100644 src/mainboard/dell/optiplex_9020/hda_verb.c
- create mode 100644 src/mainboard/dell/optiplex_9020/mainboard.c
- create mode 100644 src/mainboard/dell/optiplex_9020/overridetree_mt.cb
- create mode 100644 src/mainboard/dell/optiplex_9020/romstage.c
-
-diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
-new file mode 100644
-index 0000000000..774a72f161
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/Kconfig
-@@ -0,0 +1,34 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+if BOARD_DELL_OPTIPLEX_9020_SFF || BOARD_DELL_OPTIPLEX_9020_MT
-+
-+config BOARD_SPECIFIC_OPTIONS
-+	def_bool y
-+	select BOARD_ROMSIZE_KB_12288
-+	select HAVE_ACPI_RESUME
-+	select HAVE_ACPI_TABLES
-+	select HAVE_OPTION_TABLE
-+	select HAVE_CMOS_DEFAULT
-+	select INTEL_GMA_HAVE_VBT
-+	select INTEL_INT15
-+	select MAINBOARD_HAS_LIBGFXINIT
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select NORTHBRIDGE_INTEL_HASWELL
-+	select SERIRQ_CONTINUOUS_MODE
-+	select SOUTHBRIDGE_INTEL_LYNXPOINT
-+	select SUPERIO_SMSC_SCH555x
-+
-+config CBFS_SIZE
-+	default 0x600000
-+
-+config MAINBOARD_DIR
-+	default "dell/optiplex_9020"
-+
-+config MAINBOARD_PART_NUMBER
-+	default "OptiPlex 7020/9020 SFF" if BOARD_DELL_OPTIPLEX_9020_SFF
-+	default "OptiPlex 7020/9020 MT" if BOARD_DELL_OPTIPLEX_9020_MT
-+
-+config OVERRIDE_DEVICETREE
-+	default "overridetree_mt.cb" if BOARD_DELL_OPTIPLEX_9020_MT
-+
-+endif
-diff --git a/src/mainboard/dell/optiplex_9020/Kconfig.name b/src/mainboard/dell/optiplex_9020/Kconfig.name
-new file mode 100644
-index 0000000000..c25c330a44
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/Kconfig.name
-@@ -0,0 +1,11 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+config BOARD_DELL_OPTIPLEX_9020_SFF
-+	bool "OptiPlex 7020/9020 SFF"
-+	help
-+	  The 7020 SFF and 9020 SFF mainboards are physically identical.
-+
-+config BOARD_DELL_OPTIPLEX_9020_MT
-+	bool "OptiPlex 7020/9020 MT"
-+	help
-+	  The 7020 MT and 9020 MT mainboards are physically identical.
-diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc
-new file mode 100644
-index 0000000000..6ca2f2afaa
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/Makefile.inc
-@@ -0,0 +1,5 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-+bootblock-y += bootblock.c
-diff --git a/src/mainboard/dell/optiplex_9020/acpi/ec.asl b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
-new file mode 100644
-index 0000000000..16990d45f4
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: CC-PDDC */
-+
-+/* Please update the license if adding licensable material. */
-diff --git a/src/mainboard/dell/optiplex_9020/acpi/platform.asl b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
-new file mode 100644
-index 0000000000..cda7682e3e
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
-@@ -0,0 +1,11 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+	Return(Package() { 0, 0 })
-+}
-+
-+Method(_PTS, 1)
-+{
-+
-+}
-diff --git a/src/mainboard/dell/optiplex_9020/acpi/superio.asl b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
-new file mode 100644
-index 0000000000..16990d45f4
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: CC-PDDC */
-+
-+/* Please update the license if adding licensable material. */
-diff --git a/src/mainboard/dell/optiplex_9020/board_info.txt b/src/mainboard/dell/optiplex_9020/board_info.txt
-new file mode 100644
-index 0000000000..e30cf9c41f
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/board_info.txt
-@@ -0,0 +1,8 @@
-+Vendor name: Dell Inc.
-+Board name: OptiPlex 7020/9020
-+Release year: 2014
-+Category: desktop
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
-new file mode 100644
-index 0000000000..2837cf9cf1
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/bootblock.c
-@@ -0,0 +1,116 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <arch/io.h>
-+#include <device/pnp_ops.h>
-+#include <superio/smsc/sch555x/sch555x.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
-+
-+static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
-+{
-+	// Clear EC-to-Host mailbox
-+	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
-+	outb(tmp, SCH555x_EMI_IOBASE + 1);
-+
-+	// Send address and value to the EC
-+	sch555x_emi_write16(0, (addr1 * 2) | 0x101);
-+	sch555x_emi_write32(4, val | (addr2 << 16));
-+
-+	// Wait for acknowledgement message from EC
-+	outb(1, SCH555x_EMI_IOBASE);
-+	size_t timeout = 0;
-+	do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
-+}
-+
-+struct ec_init_entry {
-+	uint16_t addr;
-+	uint8_t val;
-+};
-+
-+static void ec_init(void)
-+{
-+	/*
-+	 * Tables from CORE_PEI
-+	 */
-+
-+	static const struct ec_init_entry init_table1[] = {
-+		{0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10},
-+		{0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10},
-+		{0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12},
-+		{0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12},
-+		{0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10},
-+		{0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11},
-+	};
-+
-+	for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i)
-+		ec_write(2, init_table1[i].addr, init_table1[i].val);
-+
-+	static const struct ec_init_entry init_table2[] = {
-+		{0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f},
-+		{0x0083, 0xbb}, {0x0085, 0xd9}, {0x0086, 0x2c}, {0x008a, 0x34},
-+		{0x008b, 0x60}, {0x0090, 0x5e}, {0x0091, 0x5e}, {0x0092, 0x86},
-+		{0x0096, 0xa4}, {0x0097, 0xa4}, {0x0098, 0xa4}, {0x009b, 0xa4},
-+		{0x00a0, 0x0a}, {0x00a1, 0x0a}, {0x00ae, 0x7c}, {0x00af, 0x7c},
-+		{0x00b0, 0x9e}, {0x00b3, 0x7c}, {0x00b6, 0x08}, {0x00b7, 0x08},
-+		{0x00ea, 0x64}, {0x00ef, 0xff}, {0x00f8, 0x15}, {0x00f9, 0x00},
-+		{0x00f0, 0x30}, {0x00fd, 0x01}, {0x01a1, 0x00}, {0x01a2, 0x00},
-+		{0x01b1, 0x08}, {0x01be, 0x90}, {0x0280, 0x24}, {0x0281, 0x13},
-+		{0x0282, 0x03}, {0x0283, 0x0a}, {0x0284, 0x80}, {0x0285, 0x03},
-+		{0x0288, 0x80}, {0x0289, 0x0c}, {0x028a, 0x03}, {0x028b, 0x0a},
-+		{0x028c, 0x80}, {0x028d, 0x03}, {0x0040, 0x01},
-+	};
-+
-+	for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i)
-+		ec_write(1, init_table2[i].addr, init_table2[i].val);
-+
-+	/*
-+	 * Table from PeiHwmInit
-+	 */
-+
-+	static const struct ec_init_entry hwm_init_table[] = {
-+		{0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f},
-+		{0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33},
-+		{0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff},
-+		{0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00},
-+		{0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00},
-+		{0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80},
-+		{0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02},
-+		{0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04},
-+		{0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50},
-+		{0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50},
-+		{0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c},
-+		{0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd},
-+		{0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e},
-+		{0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00},
-+		{0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff},
-+		{0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00},
-+		{0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c},
-+		{0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02},
-+		{0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03},
-+	};
-+
-+	for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i)
-+		ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val);
-+}
-+
-+#define SCH555x_IOBASE	0x2e
-+#define GLOBAL_DEV	PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL)
-+#define SERIAL_DEV	PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1)
-+
-+void mainboard_config_superio(void)
-+{
-+	// Super I/O early init will map Runtime and EMI registers
-+	sch555x_early_init(GLOBAL_DEV);
-+
-+	// Changes LED color among a few other things (extracted from Dell's FW)
-+	outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS);
-+	outb(0x00, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN);
-+	outb(0x18, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN1);
-+	outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
-+	outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
-+
-+	// Magic EC init
-+	ec_init();
-+
-+	// Magic EC init is needed for UART1 initialization to work
-+	sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-+}
-diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
-new file mode 100644
-index 0000000000..b159660aa8
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/cmos.default
-@@ -0,0 +1,4 @@
-+boot_option=Fallback
-+debug_level=Debug
-+nmi=Disable
-+power_on_after_fail=Disable
-diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
-new file mode 100644
-index 0000000000..c9ba76c78f
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
-@@ -0,0 +1,58 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0	120	r	0	reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384	1	e	3	boot_option
-+388	4	h	0	reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395	4	e	4	debug_level
-+
-+#400	8	r	0	reserved for century byte
-+
-+# coreboot config options: southbridge
-+408	1	e	1	nmi
-+409	2	e	5	power_on_after_fail
-+
-+# coreboot config options: check sums
-+984	16	h	0	check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID	value	text
-+1	0	Disable
-+1	1	Enable
-+
-+2	0	Enable
-+2	1	Disable
-+
-+3	0	Fallback
-+3	1	Normal
-+
-+4	0	Emergency
-+4	1	Alert
-+4	2	Critical
-+4	3	Error
-+4	4	Warning
-+4	5	Notice
-+4	6	Info
-+4	7	Debug
-+4	8	Spew
-+
-+5	0	Disable
-+5	1	Enable
-+5	2	Keep
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 415 984
-diff --git a/src/mainboard/dell/optiplex_9020/data.vbt b/src/mainboard/dell/optiplex_9020/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..1779f3b8d1018ba0aae480103b145bd7b6dd6187
-GIT binary patch
-literal 4409
-zcmdT{T}&KR6h8B_yR)-1!!lr9XiE<T5h_au1f&hdSy<_UtKG6lH%+yR*`>u$pi5g@
-zP3)>@YHE~+rqQIfO&U!#QHhDMkD3^5qG|e|_!FbV_|P=QG{y&G)b-q%VY>waTYnNg
-zlQZY%p84*%_nv!argpGv03)IJ_Pe7|bSMP|Y$`oQ_r=uJyEVQm92yAi>WXgdz6a04
-zD)5&6aRng7aW^T=MoU}o*#7ireSZT+;@h#UsjZ1Q4>q^r@OTD8dxst!AG;&CDL8Oo
-z^uXRm#BdDb@opR+9u95~SuwW<QzMfTqeF)qF*csrKZ)H~hheKJ9Bag}aojteN>8Tu
-zlb(JA9~v1O%8aBZS%1O)#VHqfy2mFDXGV7K*^l+z4cKBBMzF<bZbmC*>>kfdG+}6T
-z6#H4sB=%D$nS<$6lPaq+z<VHx902D6&lA9LzqdfOh#}ETa^{d^Qa3IULMDVoxLYjf
-zv_SO(uW~#!R!i{VA*TVEBzVEHO|WbbVKxbVzx(ZS+aUqD7$Jw01c2!TeBcCl0o=?F
-z28TS8$Zmu%>jW^<CJybs=4~hTnz>lR#jfi;e=$Iyv50HHXlZTl*xYG$g?l1>(OCb$
-zU}DG4>=REuHB||}y?K34mZfn9c;qU`2=#DU;Ndl)1MU?sz-wNFPrQEkmiQ;)T^<R}
-zdUSY)_#@&kiGTFS@Cz|7$)FHd5Z4d~iSHopC5{t6K)joHAMs<vPZPgD{1Wk5;x~xj
-zC4QgyW8%+<za@4bfZuX_7Ccs_S<aEAwgkTj&o@B!q~ky7_`O%{^_3mzbL0|(U(%J!
-zc|7n(?qUFPIq6Q8fk_B7y<FHqia0WANkND?_5ev%QVGY-<-AEUTj=`t?()a1=55O5
-z{_mRaBdE^OAe?=LY&@K6Vl9(-%92(Xz`HWb2jrieR~917`}6Ye2PkFGM<<PdozIAn
-z^~{K!pyf`h0{p_snin|Dy#pS02chH`c=HRG@BbfDysjI9Dy8GmAziVGdEP8P1@20r
-zBqq#pp3aSG?5Z($i{C%72adbj0IKXTPv?C2Liz8vth$FvMX=5WiS0s*j42Hu+7sIq
-z8yZWG-Z!*2U8Hey1X2}XhM>*}9BsG30>%b-aT^$>F;QlFs?KdZG`Fp?&P=>G?}^-H
-z8V}91nC5%)o<Kdc9}(=yRN9ZYz<R5Y#!XvQOq$z%Cn**6PyxTvRRPl+f_+_}SCoA<
-za@Vv<hO&AVF3|ye$@4RJwCumBv5E4paIqMm<F?cxfHmzf>&;H%+*-esTyM8m72{dk
-zN_}yhSK?iwVn0WBiCk!kp>joHDlbZb@-S0HiL0(nDpFM`l;n%Xd2HQIg5o*w(&Ie1
-zXo(bBhcHASlm}+e6jDvD2&s06<%&>b5^ABIR?)PhL=q;MUUIqs5lZ+1pe5A$068bG
-zYk1wEhT|Z7B_sHB-6yZ{VV6%I@W~JQaLT8j@X2R<_@Ph#!Y6;{LrKvq6}eWyK1JWD
-z$ioUgr|72?`J93m6@5;TuPEqO_4TUUsA9jWr&M`N#p9~}sw&T@IIHTHRrx0s1Dd`;
-zlUp_1q3NTVd{D!an*OFHpV#mkO~0ziziR4+t74X)<Fci+?Wnk=j6%hk;1x^$%=t;W
-zN^Yg4Uc8pHADlgcLV{lz;Y<lab7BqFXUpvws%k&N(?Ss`Sx<+!GQ!KP+0;bGI<u<0
-z4SuHz074M#Hw&c+7DDH;qgZ?(u>Ea)e<*`45Lgb&Bj~FK_ryRq5ZmCESNs5##`izi
-zWl>%<LQf28jJj3r(DnvHaKF`A!KQ&LD-NM<^&lbC85n4V#QQeF4>b${%1!r_HHzg|
-zb7P%(J~^e(e?Sd9{<%GhPj7S-3+AEyh&WB(;<TE@je=%!#d%nM6pIdgs~&vU<?vS!
-ztaC^yZYGz`LA7!K7Z$M=S1RF53~x3RqnkZtSM@aQ$D;QIzd0M&*AX-mLFdJ1%|nTW
-zKu4H+<*IHlA(@4;q~A}wijjptb-`A1OTqCOFSJ6vTQS-lW>Em~L_u66jOlR9ZUEZ|
-zMhC-jAj9!85eeUR&5CZpNVwUt>909-|5kF?Ve@Y58TNJV5CLGmjb)HGdJ22pR+!su
-z`@ntQ1&|Z3+xNb&p(?Li{yzJDS)dq4FZ3_c3(;&nw}2XNf@gau=U)2uzaL_df=2EH
-PTo#&U0FLJAf1&;f?(g8r
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
-new file mode 100644
-index 0000000000..c0b17a15ff
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
-@@ -0,0 +1,80 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+chip northbridge/intel/haswell
-+	# This mainboard has VGA
-+	register "gpu_ddi_e_connected" = "1"
-+
-+	chip cpu/intel/haswell
-+		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
-+	end
-+
-+	device domain 0 on
-+		ops haswell_pci_domain_ops
-+
-+		subsystemid 0x1028 0x05a5 inherit
-+
-+		device pci 00.0 on  end					# Host bridge
-+		device pci 01.0 on  end					# PCIe graphics
-+		device pci 02.0 on  end					# VGA controller
-+		device pci 03.0 on  end					# Mini-HD audio
-+
-+		chip southbridge/intel/lynxpoint
-+			register "gen1_dec" = "0x007c0a01"
-+			register "gen2_dec" = "0x007c0901"
-+			register "gen3_dec" = "0x003c07e1"
-+			register "gen4_dec" = "0x001c0901"
-+			register "sata_port_map" = "0x33"
-+
-+			device pci 14.0 on  end				# xHCI controller
-+			device pci 16.0 on  end				# Management Engine interface 1
-+			device pci 16.1 off end				# Management Engine interface 2
-+			device pci 16.2 off end				# Management Engine IDE-R
-+			device pci 16.3 on  end				# Management Engine KT
-+			device pci 19.0 on      			# Intel Gigabit Ethernet
-+				subsystemid 0x1028 0x05a4
-+			end
-+			device pci 1a.0 on  end				# EHCI controller #2
-+			device pci 1b.0 on  end				# HD audio controller
-+			device pci 1c.0 off end
-+			device pci 1c.1 off end
-+			device pci 1c.2 off end
-+			device pci 1c.3 off end
-+			device pci 1c.4 on  end				# PCIe 4x slot
-+			device pci 1c.5 off end
-+			device pci 1c.6 off end
-+			device pci 1c.7 off end
-+			device pci 1d.0 on  end				# EHCI controller #1
-+			device pci 1f.0 on				# LPC bridge
-+				chip superio/smsc/sch555x
-+					device pnp 2e.0 on		# EMI
-+						io 0x60 = 0xa00
-+					end
-+					device pnp 2e.1 on		# 8042
-+						io 0x60 = 0x60
-+						irq 0x0f = 0
-+						irq 0x70 = 1
-+						irq 0x72 = 12
-+					end
-+					device pnp 2e.7 on		# UART1
-+						io 0x60 = 0x3f8
-+						irq 0x0f = 2
-+						irq 0x70 = 4
-+					end
-+					device pnp 2e.8 off end 	# UART2
-+					device pnp 2e.c on		# LPC interface
-+						io 0x60 = 0x2e
-+					end
-+					device pnp 2e.a on		# Runtime registers
-+						io 0x60 = 0xa40
-+					end
-+					device pnp 2e.b  off end	# Floppy Controller
-+					device pnp 2e.11 off end	# Parallel Port
-+				end
-+			end
-+			device pci 1f.2 on  end				# SATA controller 1
-+			device pci 1f.3 on  end				# SMBus
-+			device pci 1f.5 off end				# SATA controller 2
-+			device pci 1f.6 off end				# Thermal
-+		end
-+	end
-+end
-diff --git a/src/mainboard/dell/optiplex_9020/dsdt.asl b/src/mainboard/dell/optiplex_9020/dsdt.asl
-new file mode 100644
-index 0000000000..7ec1e9775a
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/dsdt.asl
-@@ -0,0 +1,25 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi.h>
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	ACPI_DSDT_REV_2,
-+	OEM_ID,
-+	ACPI_TABLE_CREATOR,
-+	0x20181031	/* OEM Revision */
-+)
-+{
-+	#include <acpi/dsdt_top.asl>
-+	#include "acpi/platform.asl"
-+	#include <southbridge/intel/common/acpi/platform.asl>
-+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
-+	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+	#include <cpu/intel/common/acpi/cpu.asl>
-+
-+	Device (\_SB.PCI0)
-+	{
-+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
-+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
-+	}
-+}
-diff --git a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
-new file mode 100644
-index 0000000000..173f2f1d0d
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
-@@ -0,0 +1,18 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (DP1,
-+      DP2,
-+      DP3,
-+      Analog,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/optiplex_9020/gpio.c b/src/mainboard/dell/optiplex_9020/gpio.c
-new file mode 100644
-index 0000000000..48b7707e2c
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/gpio.c
-@@ -0,0 +1,217 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_GPIO,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_GPIO,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_GPIO,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_NATIVE,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_NATIVE,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_NATIVE,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_GPIO,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_GPIO,
-+	.gpio26 = GPIO_MODE_GPIO,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_NATIVE,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio1 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio5 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio11 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_OUTPUT,
-+	.gpio15 = GPIO_DIR_OUTPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_OUTPUT,
-+	.gpio23 = GPIO_DIR_OUTPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio25 = GPIO_DIR_OUTPUT,
-+	.gpio26 = GPIO_DIR_OUTPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio31 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio13 = GPIO_LEVEL_LOW,
-+	.gpio15 = GPIO_LEVEL_HIGH,
-+	.gpio22 = GPIO_LEVEL_HIGH,
-+	.gpio23 = GPIO_LEVEL_HIGH,
-+	.gpio25 = GPIO_LEVEL_HIGH,
-+	.gpio26 = GPIO_LEVEL_HIGH,
-+	.gpio28 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+	.gpio18 = GPIO_BLINK,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio8 = GPIO_INVERT,
-+	.gpio9 = GPIO_INVERT,
-+	.gpio11 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+	.gpio26 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_GPIO,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_NATIVE,
-+	.gpio37 = GPIO_MODE_NATIVE,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_GPIO,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_GPIO,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_GPIO,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_GPIO,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_GPIO,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio32 = GPIO_DIR_INPUT,
-+	.gpio33 = GPIO_DIR_OUTPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio44 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio46 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio50 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_OUTPUT,
-+	.gpio52 = GPIO_DIR_OUTPUT,
-+	.gpio53 = GPIO_DIR_OUTPUT,
-+	.gpio54 = GPIO_DIR_OUTPUT,
-+	.gpio55 = GPIO_DIR_OUTPUT,
-+	.gpio57 = GPIO_DIR_OUTPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio33 = GPIO_LEVEL_HIGH,
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio50 = GPIO_LEVEL_HIGH,
-+	.gpio51 = GPIO_LEVEL_HIGH,
-+	.gpio52 = GPIO_LEVEL_HIGH,
-+	.gpio53 = GPIO_LEVEL_HIGH,
-+	.gpio54 = GPIO_LEVEL_HIGH,
-+	.gpio55 = GPIO_LEVEL_HIGH,
-+	.gpio57 = GPIO_LEVEL_HIGH,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_GPIO,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_GPIO,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_NATIVE,
-+	.gpio71 = GPIO_MODE_NATIVE,
-+	.gpio72 = GPIO_MODE_GPIO,
-+	.gpio73 = GPIO_MODE_GPIO,
-+	.gpio74 = GPIO_MODE_GPIO,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio64 = GPIO_DIR_OUTPUT,
-+	.gpio66 = GPIO_DIR_OUTPUT,
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio72 = GPIO_DIR_OUTPUT,
-+	.gpio73 = GPIO_DIR_INPUT,
-+	.gpio74 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+	.gpio64 = GPIO_LEVEL_HIGH,
-+	.gpio66 = GPIO_LEVEL_HIGH,
-+	.gpio72 = GPIO_LEVEL_HIGH,
-+	.gpio74 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 =	{
-+		.mode = &pch_gpio_set1_mode,
-+		.direction = &pch_gpio_set1_direction,
-+		.level = &pch_gpio_set1_level,
-+		.blink = &pch_gpio_set1_blink,
-+		.invert = &pch_gpio_set1_invert,
-+		.reset = &pch_gpio_set1_reset,
-+	},
-+	.set2 =	{
-+		.mode = &pch_gpio_set2_mode,
-+		.direction = &pch_gpio_set2_direction,
-+		.level = &pch_gpio_set2_level,
-+		.reset = &pch_gpio_set2_reset,
-+	},
-+	.set3 =	{
-+		.mode = &pch_gpio_set3_mode,
-+		.direction = &pch_gpio_set3_direction,
-+		.level = &pch_gpio_set3_level,
-+		.reset = &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/optiplex_9020/hda_verb.c b/src/mainboard/dell/optiplex_9020/hda_verb.c
-new file mode 100644
-index 0000000000..df43ade3e6
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/hda_verb.c
-@@ -0,0 +1,27 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <stdint.h>
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x10ec0280, /* Realtek ALC3220 */
-+	0x102805a5, /* Subsystem ID */
-+	13,	 /* Number of entries */
-+	AZALIA_SUBVENDOR(0, 0x102805a5),
-+	AZALIA_PIN_CFG(0, 0x12, 0x4008c000),
-+	AZALIA_PIN_CFG(0, 0x13, 0x411111f0),
-+	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x15, 0x0221401f),
-+	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
-+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
-+	AZALIA_PIN_CFG(0, 0x18, 0x01a13040),
-+	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
-+	AZALIA_PIN_CFG(0, 0x1a, 0x02a19030),
-+	AZALIA_PIN_CFG(0, 0x1b, 0x01014020),
-+	AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
-+	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
-+};
-+
-+const u32 pc_beep_verbs[] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
-new file mode 100644
-index 0000000000..c834fea5d3
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/device.h>
-+#include <drivers/intel/gma/int15.h>
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
-+					GMA_INT15_PANEL_FIT_DEFAULT,
-+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+	.enable_dev = mainboard_enable,
-+};
-diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
-new file mode 100644
-index 0000000000..90205c2d68
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
-@@ -0,0 +1,10 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+chip northbridge/intel/haswell
-+	device domain 0 on
-+		chip southbridge/intel/lynxpoint
-+			device pci 1c.1 on  end	# PCI (via XIO2001 bridge)
-+			device pci 1c.2 on  end	# PCIe 1x slot
-+		end
-+	end
-+end
-diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c
-new file mode 100644
-index 0000000000..2b9cdaa5fd
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/romstage.c
-@@ -0,0 +1,53 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/raminit.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
-+
-+void mainboard_config_rcba(void)
-+{
-+	RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQC, PIRQD, PIRQA);
-+	RCBA16(D29IR) = DIR_ROUTE(PIRQC, PIRQA, PIRQD, PIRQH);
-+	RCBA16(D28IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
-+	RCBA16(D27IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQG);
-+	RCBA16(D26IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQF, PIRQA);
-+	RCBA16(D25IR) = DIR_ROUTE(PIRQH, PIRQG, PIRQF, PIRQE);
-+	RCBA16(D22IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQA);
-+	RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
-+}
-+
-+void mb_get_spd_map(struct spd_info *spdi)
-+{
-+	spdi->addresses[0] = 0x50;
-+	spdi->addresses[1] = 0x51;
-+	spdi->addresses[2] = 0x52;
-+	spdi->addresses[3] = 0x53;
-+}
-+
-+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
-+	/* Length, Enable, OCn#, Location */
-+	{0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
-+	{0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
-+	{0x0040, 1, 1, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 2, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 3, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 3, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 0, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 0, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 4, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 4, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 5, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 5, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 6, USB_PORT_BACK_PANEL},
-+	{0x0040, 1, 7, USB_PORT_BACK_PANEL},
-+};
-+
-+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
-+	/* Enable, OCn# */
-+	{1, 6},
-+	{1, 7},
-+	{0, USB_OC_PIN_SKIP},
-+	{0, USB_OC_PIN_SKIP},
-+	{1, 1},
-+	{1, 2},
-+};
-- 
-2.39.2
-
@@ -1,774 +0,0 @@
-From 41002e64c92e90903fa591c4a8a1cc0108833743 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 26 Nov 2023 17:08:52 -0700
-Subject: [PATCH] mb/dell: Add Latitude E6420 (Sandy Bridge)
-
-Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/e6420/Kconfig           |  38 ++++
- src/mainboard/dell/e6420/Kconfig.name      |   2 +
- src/mainboard/dell/e6420/Makefile.inc      |   6 +
- src/mainboard/dell/e6420/acpi/ec.asl       |   9 +
- src/mainboard/dell/e6420/acpi/platform.asl |  12 ++
- src/mainboard/dell/e6420/acpi/superio.asl  |   3 +
- src/mainboard/dell/e6420/acpi_tables.c     |  16 ++
- src/mainboard/dell/e6420/board_info.txt    |   6 +
- src/mainboard/dell/e6420/cmos.default      |   9 +
- src/mainboard/dell/e6420/cmos.layout       |  88 ++++++++++
- src/mainboard/dell/e6420/data.vbt          | Bin 0 -> 6144 bytes
- src/mainboard/dell/e6420/devicetree.cb     |  66 +++++++
- src/mainboard/dell/e6420/dsdt.asl          |  30 ++++
- src/mainboard/dell/e6420/early_init.c      |  32 ++++
- src/mainboard/dell/e6420/gma-mainboard.ads |  20 +++
- src/mainboard/dell/e6420/gpio.c            | 191 +++++++++++++++++++++
- src/mainboard/dell/e6420/hda_verb.c        |  33 ++++
- src/mainboard/dell/e6420/mainboard.c       |  21 +++
- 18 files changed, 582 insertions(+)
- create mode 100644 src/mainboard/dell/e6420/Kconfig
- create mode 100644 src/mainboard/dell/e6420/Kconfig.name
- create mode 100644 src/mainboard/dell/e6420/Makefile.inc
- create mode 100644 src/mainboard/dell/e6420/acpi/ec.asl
- create mode 100644 src/mainboard/dell/e6420/acpi/platform.asl
- create mode 100644 src/mainboard/dell/e6420/acpi/superio.asl
- create mode 100644 src/mainboard/dell/e6420/acpi_tables.c
- create mode 100644 src/mainboard/dell/e6420/board_info.txt
- create mode 100644 src/mainboard/dell/e6420/cmos.default
- create mode 100644 src/mainboard/dell/e6420/cmos.layout
- create mode 100644 src/mainboard/dell/e6420/data.vbt
- create mode 100644 src/mainboard/dell/e6420/devicetree.cb
- create mode 100644 src/mainboard/dell/e6420/dsdt.asl
- create mode 100644 src/mainboard/dell/e6420/early_init.c
- create mode 100644 src/mainboard/dell/e6420/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/e6420/gpio.c
- create mode 100644 src/mainboard/dell/e6420/hda_verb.c
- create mode 100644 src/mainboard/dell/e6420/mainboard.c
-
-diff --git a/src/mainboard/dell/e6420/Kconfig b/src/mainboard/dell/e6420/Kconfig
-new file mode 100644
-index 0000000000..cff62bf70c
--- /dev/null
-+++ b/src/mainboard/dell/e6420/Kconfig
-@@ -0,0 +1,38 @@
-+if BOARD_DELL_LATITUDE_E6420
-+
-+config BOARD_SPECIFIC_OPTIONS
-+	def_bool y
-+	select BOARD_ROMSIZE_KB_10240
-+	select EC_ACPI
-+	select EC_DELL_MEC5035
-+	select GFX_GMA_PANEL_1_ON_LVDS
-+	select HAVE_ACPI_RESUME
-+	select HAVE_ACPI_TABLES
-+	select HAVE_CMOS_DEFAULT
-+	select HAVE_OPTION_TABLE
-+	select INTEL_GMA_HAVE_VBT
-+	select INTEL_INT15
-+	select MAINBOARD_HAS_LIBGFXINIT
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+	select SERIRQ_CONTINUOUS_MODE
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+	select SYSTEM_TYPE_LAPTOP
-+	select USE_NATIVE_RAMINIT
-+
-+config DRAM_RESET_GATE_GPIO
-+	default 60
-+
-+config MAINBOARD_DIR
-+	default "dell/e6420"
-+
-+config MAINBOARD_PART_NUMBER
-+	default "Latitude E6420"
-+
-+config USBDEBUG_HCD_INDEX
-+	default 2
-+
-+config VGA_BIOS_ID
-+	default "8086,0126"
-+
-+endif # BOARD_DELL_LATITUDE_E6420
-diff --git a/src/mainboard/dell/e6420/Kconfig.name b/src/mainboard/dell/e6420/Kconfig.name
-new file mode 100644
-index 0000000000..1722891e7b
--- /dev/null
-+++ b/src/mainboard/dell/e6420/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_DELL_LATITUDE_E6420
-+	bool "Latitude E6420"
-diff --git a/src/mainboard/dell/e6420/Makefile.inc b/src/mainboard/dell/e6420/Makefile.inc
-new file mode 100644
-index 0000000000..ba64e93eb8
--- /dev/null
-+++ b/src/mainboard/dell/e6420/Makefile.inc
-@@ -0,0 +1,6 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6420/acpi/ec.asl b/src/mainboard/dell/e6420/acpi/ec.asl
-new file mode 100644
-index 0000000000..0d429410a9
--- /dev/null
-+++ b/src/mainboard/dell/e6420/acpi/ec.asl
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Device(EC)
-+{
-+	Name (_HID, EISAID("PNP0C09"))
-+	Name (_UID, 0)
-+	Name (_GPE, 16)
-+/* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e6420/acpi/platform.asl b/src/mainboard/dell/e6420/acpi/platform.asl
-new file mode 100644
-index 0000000000..2d24bbd9b9
--- /dev/null
-+++ b/src/mainboard/dell/e6420/acpi/platform.asl
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+	/* FIXME: EC support  */
-+	Return(Package() {0, 0})
-+}
-+
-+Method(_PTS,1)
-+{
-+	/* FIXME: EC support  */
-+}
-diff --git a/src/mainboard/dell/e6420/acpi/superio.asl b/src/mainboard/dell/e6420/acpi/superio.asl
-new file mode 100644
-index 0000000000..55b1db5b11
--- /dev/null
-+++ b/src/mainboard/dell/e6420/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <drivers/pc80/pc/ps2_controller.asl>
-diff --git a/src/mainboard/dell/e6420/acpi_tables.c b/src/mainboard/dell/e6420/acpi_tables.c
-new file mode 100644
-index 0000000000..e2759659bf
--- /dev/null
-+++ b/src/mainboard/dell/e6420/acpi_tables.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi_gnvs.h>
-+#include <soc/nvs.h>
-+
-+/* FIXME: check this function.  */
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+	/* The lid is open by default. */
-+	gnvs->lids = 1;
-+
-+	/* Temperature at which OS will shutdown */
-+	gnvs->tcrt = 100;
-+	/* Temperature at which OS will throttle CPU */
-+	gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/dell/e6420/board_info.txt b/src/mainboard/dell/e6420/board_info.txt
-new file mode 100644
-index 0000000000..34d5ad9e0b
--- /dev/null
-+++ b/src/mainboard/dell/e6420/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: laptop
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-+Release year: 2011
-diff --git a/src/mainboard/dell/e6420/cmos.default b/src/mainboard/dell/e6420/cmos.default
-new file mode 100644
-index 0000000000..279415dfd1
--- /dev/null
-+++ b/src/mainboard/dell/e6420/cmos.default
-@@ -0,0 +1,9 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+bluetooth=Enable
-+wwan=Enable
-+wlan=Enable
-+sata_mode=AHCI
-+me_state=Disabled
-diff --git a/src/mainboard/dell/e6420/cmos.layout b/src/mainboard/dell/e6420/cmos.layout
-new file mode 100644
-index 0000000000..1aa7e77bce
--- /dev/null
-+++ b/src/mainboard/dell/e6420/cmos.layout
-@@ -0,0 +1,88 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0	120	r	0	reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384	1	e	4	boot_option
-+388	4	h	0	reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395	4	e	6	debug_level
-+
-+#400	8	r	0	reserved for century byte
-+
-+# coreboot config options: southbridge
-+408	1	e	1	nmi
-+409	2	e	7	power_on_after_fail
-+411     1       e       9       sata_mode
-+
-+# coreboot config options: EC
-+412	1	e	1	bluetooth
-+413	1	e	1	wwan
-+414	1	e	1	wlan
-+
-+# coreboot config options: ME
-+424	1	e	14	me_state
-+425	2	h	0	me_state_prev
-+
-+# coreboot config options: northbridge
-+432	3	e	11	gfx_uma_size
-+435	2	e	12	hybrid_graphics_mode
-+440	8	h	0	volume
-+
-+# VBOOT
-+448	128	r	0	vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896	32	r	0	mrc_scrambler_seed
-+928	32	r	0	mrc_scrambler_seed_s3
-+960	16	r	0	mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984	16	h	0	check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID	value	text
-+1	0	Disable
-+1	1	Enable
-+2	0	Enable
-+2	1	Disable
-+4	0	Fallback
-+4	1	Normal
-+6	0	Emergency
-+6	1	Alert
-+6	2	Critical
-+6	3	Error
-+6	4	Warning
-+6	5	Notice
-+6	6	Info
-+6	7	Debug
-+6	8	Spew
-+7	0	Disable
-+7	1	Enable
-+7	2	Keep
-+9	0	AHCI
-+9	1	Compatible
-+11	0	32M
-+11	1	64M
-+11	2	96M
-+11	3	128M
-+11	4	160M
-+11	5	192M
-+11	6	224M
-+14	0	Normal
-+14	1	Disabled
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 447 984
-diff --git a/src/mainboard/dell/e6420/data.vbt b/src/mainboard/dell/e6420/data.vbt
-new file mode 100644
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-zVGNL)lmH@{o=h*{muXGc!;nXrVgpp3;1V1stMj=4AtxyzX+?SoB~zN}!*r?9Qvs1P
-zmV_(CTmt0sY&6=F=_M>E34GYvuh1uQF+BUdWyQC5SaEM1QvKlHBMs13C}n{0SwRxW
-ziekMa&kvRFruRcKCevGy5)TxUBDlur@E{TtQ^NQ>nO+Cgl)&Ga(PxqVW?e3TLH-UY
-zdL3T{z^xdd`$(STFUb8R*cKa}r>n{Wk+MXRH~o-hN}#9OF*>T#>rfhiRs(Wc-R^9@
-z%F=<}dn(E}ADc03zJ>JvZe;_8f+WFLL4%qNYs`_aa`a$Pl5H;iO^Wt*cP3W(d=(g}
-zZ%nKT1$|r-tAv8($u2-BI2Uiz#%OT&!Q3b~Ru2P2j;Gem!@wfPsTR%J>W{8z)oq^J
-k^Qm&?O@bFkw4CTocwoW<6CRlGz=Q`TJTT#bN9KWl0rH4|j{pDw
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/e6420/devicetree.cb b/src/mainboard/dell/e6420/devicetree.cb
-new file mode 100644
-index 0000000000..f9259f7175
--- /dev/null
-+++ b/src/mainboard/dell/e6420/devicetree.cb
-@@ -0,0 +1,66 @@
-+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
-+	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
-+	register "gpu_cpu_backlight" = "0x0000054f"
-+	register "gpu_dp_b_hotplug" = "4"
-+	register "gpu_dp_c_hotplug" = "4"
-+	register "gpu_dp_d_hotplug" = "4"
-+	register "gpu_panel_port_select" = "0"
-+	register "gpu_panel_power_backlight_off_delay" = "2300"
-+	register "gpu_panel_power_backlight_on_delay" = "2300"
-+	register "gpu_panel_power_cycle_delay" = "6"
-+	register "gpu_panel_power_down_delay" = "400"
-+	register "gpu_panel_power_up_delay" = "400"
-+	register "gpu_pch_backlight" = "0x13121312"
-+
-+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
-+
-+	device domain 0x0 on
-+		subsystemid 0x1028 0x0493 inherit
-+
-+		device ref host_bridge on end # Host bridge
-+		device ref peg10 on end # PEG
-+		device ref igd on end # iGPU
-+
-+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-+			register "docking_supported" = "1"
-+			register "gen1_dec" = "0x007c0681"
-+			register "gen2_dec" = "0x007c0901"
-+			register "gen3_dec" = "0x003c07e1"
-+			register "gen4_dec" = "0x001c0901"
-+			register "gpi0_routing" = "2"
-+			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
-+			register "pcie_port_coalesce" = "1"
-+			register "sata_interface_speed_support" = "0x3"
-+			register "sata_port_map" = "0x3b"
-+			register "spi_lvscc" = "0x2005"
-+			register "spi_uvscc" = "0x2005"
-+
-+			device ref mei1		off end
-+			device ref mei2		off end
-+			device ref me_ide_r	off end
-+			device ref me_kt	off end
-+			device ref gbe		on end
-+			device ref ehci2	on end
-+			device ref hda		on end
-+			device ref pcie_rp1	on end
-+			device ref pcie_rp2	on end
-+			device ref pcie_rp3	on end
-+			device ref pcie_rp4	on end
-+			device ref pcie_rp5	off end
-+			device ref pcie_rp6	on end
-+			device ref pcie_rp7	off end
-+			device ref pcie_rp8	off end
-+			device ref ehci1	on end
-+			device ref pci_bridge	off end
-+			device ref lpc		on
-+				chip ec/dell/mec5035
-+					device pnp ff.0 on end
-+				end
-+			end
-+			device ref sata1 on end
-+			device ref smbus on end
-+			device ref sata2 off end
-+			device ref thermal off end
-+		end
-+	end
-+end
-diff --git a/src/mainboard/dell/e6420/dsdt.asl b/src/mainboard/dell/e6420/dsdt.asl
-new file mode 100644
-index 0000000000..7d13c55b08
--- /dev/null
-+++ b/src/mainboard/dell/e6420/dsdt.asl
-@@ -0,0 +1,30 @@
-+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <acpi/acpi.h>
-+
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	ACPI_DSDT_REV_2,
-+	OEM_ID,
-+	ACPI_TABLE_CREATOR,
-+	0x20141018	/* OEM revision */
-+)
-+{
-+	#include <acpi/dsdt_top.asl>
-+	#include "acpi/platform.asl"
-+	#include <cpu/intel/common/acpi/cpu.asl>
-+	#include <southbridge/intel/common/acpi/platform.asl>
-+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-+	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+
-+	Device (\_SB.PCI0)
-+	{
-+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-+	}
-+}
-diff --git a/src/mainboard/dell/e6420/early_init.c b/src/mainboard/dell/e6420/early_init.c
-new file mode 100644
-index 0000000000..0682441ed6
--- /dev/null
-+++ b/src/mainboard/dell/e6420/early_init.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+	{ 1, 1, 0 },
-+	{ 1, 1, 0 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 1 },
-+	{ 1, 0, 2 },
-+	{ 1, 1, 2 },
-+	{ 1, 1, 3 },
-+	{ 1, 1, 3 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 7 },
-+	{ 1, 1, 6 },
-+	{ 1, 0, 6 },
-+	{ 1, 0, 7 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/e6420/gma-mainboard.ads b/src/mainboard/dell/e6420/gma-mainboard.ads
-new file mode 100644
-index 0000000000..2a16f44360
--- /dev/null
-+++ b/src/mainboard/dell/e6420/gma-mainboard.ads
-@@ -0,0 +1,20 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (
-+      HDMI1, -- mainboard HDMI
-+      DP2, -- dock DP
-+      DP3, -- dock DP
-+      Analog, -- mainboard VGA
-+      LVDS,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/e6420/gpio.c b/src/mainboard/dell/e6420/gpio.c
-new file mode 100644
-index 0000000000..943c743f48
--- /dev/null
-+++ b/src/mainboard/dell/e6420/gpio.c
-@@ -0,0 +1,191 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_NATIVE,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_NATIVE,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+	.gpio31 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/e6420/hda_verb.c b/src/mainboard/dell/e6420/hda_verb.c
-new file mode 100644
-index 0000000000..b3803b7c65
--- /dev/null
-+++ b/src/mainboard/dell/e6420/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x10280493,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x10280493),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/e6420/mainboard.c b/src/mainboard/dell/e6420/mainboard.c
-new file mode 100644
-index 0000000000..31e49802fc
--- /dev/null
-+++ b/src/mainboard/dell/e6420/mainboard.c
-@@ -0,0 +1,21 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/device.h>
-+#include <drivers/intel/gma/int15.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+#include <ec/acpi/ec.h>
-+#include <console/console.h>
-+#include <pc80/keyboard.h>
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+
-+	/* FIXME: fix these values. */
-+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
-+					GMA_INT15_PANEL_FIT_DEFAULT,
-+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+	.enable_dev = mainboard_enable,
-+};
-- 
-2.43.0
-
@@ -1,7 +1,7 @@
-From 622daa7c46de01530de60a7be32c8b9e48b356fd Mon Sep 17 00:00:00 2001
+From 89c47fad6e97fc6a7113ebbdedfcc42ae2b6fc7f Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 22:57:08 +0000
-Subject: [PATCH 7/9] use mirrorservice.org for gcc downloads
+Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads

 the gnu.org 302 redirect often fails

@@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
 1 file changed, 5 insertions(+), 5 deletions(-)

 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 36565a906c..4d4ca06113 100755
+index 87f80ba7f6..b3aad5df7d 100755
 --- a/util/crossgcc/buildgcc
 +++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
@@ -1,773 +0,0 @@
-From 5e8bff81220d4d0f663feed443e4594b76e442bf Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Wed, 31 Jan 2024 22:07:25 -0700
-Subject: [PATCH] mb/dell: Add Latitude E6520 (Sandy Bridge)
-
-Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/e6520/Kconfig           |  38 +++++
- src/mainboard/dell/e6520/Kconfig.name      |   2 +
- src/mainboard/dell/e6520/Makefile.inc      |   6 +
- src/mainboard/dell/e6520/acpi/ec.asl       |   9 +
- src/mainboard/dell/e6520/acpi/platform.asl |  12 ++
- src/mainboard/dell/e6520/acpi/superio.asl  |   3 +
- src/mainboard/dell/e6520/acpi_tables.c     |  16 ++
- src/mainboard/dell/e6520/board_info.txt    |   6 +
- src/mainboard/dell/e6520/cmos.default      |   9 +
- src/mainboard/dell/e6520/cmos.layout       |  88 ++++++++++
- src/mainboard/dell/e6520/data.vbt          | Bin 0 -> 6144 bytes
- src/mainboard/dell/e6520/devicetree.cb     |  66 +++++++
- src/mainboard/dell/e6520/dsdt.asl          |  30 ++++
- src/mainboard/dell/e6520/early_init.c      |  32 ++++
- src/mainboard/dell/e6520/gma-mainboard.ads |  20 +++
- src/mainboard/dell/e6520/gpio.c            | 190 +++++++++++++++++++++
- src/mainboard/dell/e6520/hda_verb.c        |  33 ++++
- src/mainboard/dell/e6520/mainboard.c       |  21 +++
- 18 files changed, 581 insertions(+)
- create mode 100644 src/mainboard/dell/e6520/Kconfig
- create mode 100644 src/mainboard/dell/e6520/Kconfig.name
- create mode 100644 src/mainboard/dell/e6520/Makefile.inc
- create mode 100644 src/mainboard/dell/e6520/acpi/ec.asl
- create mode 100644 src/mainboard/dell/e6520/acpi/platform.asl
- create mode 100644 src/mainboard/dell/e6520/acpi/superio.asl
- create mode 100644 src/mainboard/dell/e6520/acpi_tables.c
- create mode 100644 src/mainboard/dell/e6520/board_info.txt
- create mode 100644 src/mainboard/dell/e6520/cmos.default
- create mode 100644 src/mainboard/dell/e6520/cmos.layout
- create mode 100644 src/mainboard/dell/e6520/data.vbt
- create mode 100644 src/mainboard/dell/e6520/devicetree.cb
- create mode 100644 src/mainboard/dell/e6520/dsdt.asl
- create mode 100644 src/mainboard/dell/e6520/early_init.c
- create mode 100644 src/mainboard/dell/e6520/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/e6520/gpio.c
- create mode 100644 src/mainboard/dell/e6520/hda_verb.c
- create mode 100644 src/mainboard/dell/e6520/mainboard.c
-
-diff --git a/src/mainboard/dell/e6520/Kconfig b/src/mainboard/dell/e6520/Kconfig
-new file mode 100644
-index 0000000000..db9f25b4ac
--- /dev/null
-+++ b/src/mainboard/dell/e6520/Kconfig
-@@ -0,0 +1,38 @@
-+if BOARD_DELL_LATITUDE_E6520
-+
-+config BOARD_SPECIFIC_OPTIONS
-+	def_bool y
-+	select BOARD_ROMSIZE_KB_10240
-+	select EC_ACPI
-+	select EC_DELL_MEC5035
-+	select GFX_GMA_PANEL_1_ON_LVDS
-+	select HAVE_ACPI_RESUME
-+	select HAVE_ACPI_TABLES
-+	select HAVE_CMOS_DEFAULT
-+	select HAVE_OPTION_TABLE
-+	select INTEL_GMA_HAVE_VBT
-+	select INTEL_INT15
-+	select MAINBOARD_HAS_LIBGFXINIT
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+	select SERIRQ_CONTINUOUS_MODE
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+	select SYSTEM_TYPE_LAPTOP
-+	select USE_NATIVE_RAMINIT
-+
-+config DRAM_RESET_GATE_GPIO
-+	default 60
-+
-+config MAINBOARD_DIR
-+	default "dell/e6520"
-+
-+config MAINBOARD_PART_NUMBER
-+	default "Latitude E6520"
-+
-+config USBDEBUG_HCD_INDEX
-+	default 2
-+
-+config VGA_BIOS_ID
-+	default "8086,0116"
-+
-+endif # BOARD_DELL_LATITUDE_E6520
-diff --git a/src/mainboard/dell/e6520/Kconfig.name b/src/mainboard/dell/e6520/Kconfig.name
-new file mode 100644
-index 0000000000..25968e80e5
--- /dev/null
-+++ b/src/mainboard/dell/e6520/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_DELL_LATITUDE_E6520
-+	bool "Latitude E6520"
-diff --git a/src/mainboard/dell/e6520/Makefile.inc b/src/mainboard/dell/e6520/Makefile.inc
-new file mode 100644
-index 0000000000..ba64e93eb8
--- /dev/null
-+++ b/src/mainboard/dell/e6520/Makefile.inc
-@@ -0,0 +1,6 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6520/acpi/ec.asl b/src/mainboard/dell/e6520/acpi/ec.asl
-new file mode 100644
-index 0000000000..0d429410a9
--- /dev/null
-+++ b/src/mainboard/dell/e6520/acpi/ec.asl
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Device(EC)
-+{
-+	Name (_HID, EISAID("PNP0C09"))
-+	Name (_UID, 0)
-+	Name (_GPE, 16)
-+/* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e6520/acpi/platform.asl b/src/mainboard/dell/e6520/acpi/platform.asl
-new file mode 100644
-index 0000000000..2d24bbd9b9
--- /dev/null
-+++ b/src/mainboard/dell/e6520/acpi/platform.asl
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+	/* FIXME: EC support  */
-+	Return(Package() {0, 0})
-+}
-+
-+Method(_PTS,1)
-+{
-+	/* FIXME: EC support  */
-+}
-diff --git a/src/mainboard/dell/e6520/acpi/superio.asl b/src/mainboard/dell/e6520/acpi/superio.asl
-new file mode 100644
-index 0000000000..55b1db5b11
--- /dev/null
-+++ b/src/mainboard/dell/e6520/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <drivers/pc80/pc/ps2_controller.asl>
-diff --git a/src/mainboard/dell/e6520/acpi_tables.c b/src/mainboard/dell/e6520/acpi_tables.c
-new file mode 100644
-index 0000000000..e2759659bf
--- /dev/null
-+++ b/src/mainboard/dell/e6520/acpi_tables.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi_gnvs.h>
-+#include <soc/nvs.h>
-+
-+/* FIXME: check this function.  */
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+	/* The lid is open by default. */
-+	gnvs->lids = 1;
-+
-+	/* Temperature at which OS will shutdown */
-+	gnvs->tcrt = 100;
-+	/* Temperature at which OS will throttle CPU */
-+	gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/dell/e6520/board_info.txt b/src/mainboard/dell/e6520/board_info.txt
-new file mode 100644
-index 0000000000..34d5ad9e0b
--- /dev/null
-+++ b/src/mainboard/dell/e6520/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: laptop
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-+Release year: 2011
-diff --git a/src/mainboard/dell/e6520/cmos.default b/src/mainboard/dell/e6520/cmos.default
-new file mode 100644
-index 0000000000..279415dfd1
--- /dev/null
-+++ b/src/mainboard/dell/e6520/cmos.default
-@@ -0,0 +1,9 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+bluetooth=Enable
-+wwan=Enable
-+wlan=Enable
-+sata_mode=AHCI
-+me_state=Disabled
-diff --git a/src/mainboard/dell/e6520/cmos.layout b/src/mainboard/dell/e6520/cmos.layout
-new file mode 100644
-index 0000000000..1aa7e77bce
--- /dev/null
-+++ b/src/mainboard/dell/e6520/cmos.layout
-@@ -0,0 +1,88 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0	120	r	0	reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384	1	e	4	boot_option
-+388	4	h	0	reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395	4	e	6	debug_level
-+
-+#400	8	r	0	reserved for century byte
-+
-+# coreboot config options: southbridge
-+408	1	e	1	nmi
-+409	2	e	7	power_on_after_fail
-+411     1       e       9       sata_mode
-+
-+# coreboot config options: EC
-+412	1	e	1	bluetooth
-+413	1	e	1	wwan
-+414	1	e	1	wlan
-+
-+# coreboot config options: ME
-+424	1	e	14	me_state
-+425	2	h	0	me_state_prev
-+
-+# coreboot config options: northbridge
-+432	3	e	11	gfx_uma_size
-+435	2	e	12	hybrid_graphics_mode
-+440	8	h	0	volume
-+
-+# VBOOT
-+448	128	r	0	vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896	32	r	0	mrc_scrambler_seed
-+928	32	r	0	mrc_scrambler_seed_s3
-+960	16	r	0	mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984	16	h	0	check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID	value	text
-+1	0	Disable
-+1	1	Enable
-+2	0	Enable
-+2	1	Disable
-+4	0	Fallback
-+4	1	Normal
-+6	0	Emergency
-+6	1	Alert
-+6	2	Critical
-+6	3	Error
-+6	4	Warning
-+6	5	Notice
-+6	6	Info
-+6	7	Debug
-+6	8	Spew
-+7	0	Disable
-+7	1	Enable
-+7	2	Keep
-+9	0	AHCI
-+9	1	Compatible
-+11	0	32M
-+11	1	64M
-+11	2	96M
-+11	3	128M
-+11	4	160M
-+11	5	192M
-+11	6	224M
-+14	0	Normal
-+14	1	Disabled
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 447 984
-diff --git a/src/mainboard/dell/e6520/data.vbt b/src/mainboard/dell/e6520/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
-GIT binary patch
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-
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-HcmV?d00001
-
-diff --git a/src/mainboard/dell/e6520/devicetree.cb b/src/mainboard/dell/e6520/devicetree.cb
-new file mode 100644
-index 0000000000..cfba8ef4e7
--- /dev/null
-+++ b/src/mainboard/dell/e6520/devicetree.cb
-@@ -0,0 +1,66 @@
-+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
-+	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
-+	register "gpu_cpu_backlight" = "0x00001312"
-+	register "gpu_dp_b_hotplug" = "4"
-+	register "gpu_dp_c_hotplug" = "4"
-+	register "gpu_dp_d_hotplug" = "4"
-+	register "gpu_panel_port_select" = "0"
-+	register "gpu_panel_power_backlight_off_delay" = "2300"
-+	register "gpu_panel_power_backlight_on_delay" = "2300"
-+	register "gpu_panel_power_cycle_delay" = "6"
-+	register "gpu_panel_power_down_delay" = "400"
-+	register "gpu_panel_power_up_delay" = "400"
-+	register "gpu_pch_backlight" = "0x13121312"
-+
-+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
-+
-+	device domain 0x0 on
-+		subsystemid 0x1028 0x0494 inherit
-+
-+		device ref host_bridge on end # Host bridge
-+		device ref peg10 on end # PEG
-+		device ref igd on end # iGPU
-+
-+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-+			register "docking_supported" = "1"
-+			register "gen1_dec" = "0x007c0681"
-+			register "gen2_dec" = "0x007c0901"
-+			register "gen3_dec" = "0x003c07e1"
-+			register "gen4_dec" = "0x001c0901"
-+			register "gpi0_routing" = "2"
-+			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
-+			register "pcie_port_coalesce" = "1"
-+			register "sata_interface_speed_support" = "0x3"
-+			register "sata_port_map" = "0x3b"
-+			register "spi_lvscc" = "0x2005"
-+			register "spi_uvscc" = "0x2005"
-+
-+			device ref mei1		off end
-+			device ref mei2		off end
-+			device ref me_ide_r	off end
-+			device ref me_kt	off end
-+			device ref gbe		on end
-+			device ref ehci2	on end
-+			device ref hda		on end
-+			device ref pcie_rp1	on end
-+			device ref pcie_rp2	on end
-+			device ref pcie_rp3	on end
-+			device ref pcie_rp4	on end
-+			device ref pcie_rp5	off end
-+			device ref pcie_rp6	on end
-+			device ref pcie_rp7	off end
-+			device ref pcie_rp8	off end
-+			device ref ehci1	on end
-+			device ref pci_bridge	off end
-+			device ref lpc		on
-+				chip ec/dell/mec5035
-+					device pnp ff.0 on end
-+				end
-+			end
-+			device ref sata1 on end
-+			device ref smbus on end
-+			device ref sata2 off end
-+			device ref thermal off end
-+		end
-+	end
-+end
-diff --git a/src/mainboard/dell/e6520/dsdt.asl b/src/mainboard/dell/e6520/dsdt.asl
-new file mode 100644
-index 0000000000..7d13c55b08
--- /dev/null
-+++ b/src/mainboard/dell/e6520/dsdt.asl
-@@ -0,0 +1,30 @@
-+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <acpi/acpi.h>
-+
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	ACPI_DSDT_REV_2,
-+	OEM_ID,
-+	ACPI_TABLE_CREATOR,
-+	0x20141018	/* OEM revision */
-+)
-+{
-+	#include <acpi/dsdt_top.asl>
-+	#include "acpi/platform.asl"
-+	#include <cpu/intel/common/acpi/cpu.asl>
-+	#include <southbridge/intel/common/acpi/platform.asl>
-+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-+	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+
-+	Device (\_SB.PCI0)
-+	{
-+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-+	}
-+}
-diff --git a/src/mainboard/dell/e6520/early_init.c b/src/mainboard/dell/e6520/early_init.c
-new file mode 100644
-index 0000000000..2a37091df6
--- /dev/null
-+++ b/src/mainboard/dell/e6520/early_init.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+	{ 1, 1, 0 },
-+	{ 1, 1, 0 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 1 },
-+	{ 1, 0, 2 },
-+	{ 1, 1, 2 },
-+	{ 1, 0, 3 },
-+	{ 1, 0, 3 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 7 },
-+	{ 1, 1, 6 },
-+	{ 1, 0, 6 },
-+	{ 1, 0, 7 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/e6520/gma-mainboard.ads b/src/mainboard/dell/e6520/gma-mainboard.ads
-new file mode 100644
-index 0000000000..2a16f44360
--- /dev/null
-+++ b/src/mainboard/dell/e6520/gma-mainboard.ads
-@@ -0,0 +1,20 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (
-+      HDMI1, -- mainboard HDMI
-+      DP2, -- dock DP
-+      DP3, -- dock DP
-+      Analog, -- mainboard VGA
-+      LVDS,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/e6520/gpio.c b/src/mainboard/dell/e6520/gpio.c
-new file mode 100644
-index 0000000000..61f01816c4
--- /dev/null
-+++ b/src/mainboard/dell/e6520/gpio.c
-@@ -0,0 +1,190 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_NATIVE,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_NATIVE,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/e6520/hda_verb.c b/src/mainboard/dell/e6520/hda_verb.c
-new file mode 100644
-index 0000000000..d33eb3b4c5
--- /dev/null
-+++ b/src/mainboard/dell/e6520/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x10280494,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x10280494),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/e6520/mainboard.c b/src/mainboard/dell/e6520/mainboard.c
-new file mode 100644
-index 0000000000..31e49802fc
--- /dev/null
-+++ b/src/mainboard/dell/e6520/mainboard.c
-@@ -0,0 +1,21 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/device.h>
-+#include <drivers/intel/gma/int15.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+#include <ec/acpi/ec.h>
-+#include <console/console.h>
-+#include <pc80/keyboard.h>
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+
-+	/* FIXME: fix these values. */
-+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
-+					GMA_INT15_PANEL_FIT_DEFAULT,
-+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+	.enable_dev = mainboard_enable,
-+};
-- 
-2.43.0
-
@@ -1,7 +1,7 @@
-From 973783a989cdcb7b77029e369156c81eefe8cc67 Mon Sep 17 00:00:00 2001
+From 823da59b0bdaeb20d5f22da65e736acaa70b301e Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 19 Aug 2023 16:19:10 -0600
-Subject: [PATCH 26/30] mb/dell: Add Latitude E6530 (Ivy Bridge)
+Subject: [PATCH] mb/dell: Add Latitude E6530 (Ivy Bridge)

 Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested.  This
 is based on the autoport output with some manual tweaks. The flash is
@@ -788,5 +788,5 @@ index 0000000000..31e49802fc
 +	.enable_dev = mainboard_enable,
 +};
 -- 
-2.39.2
+2.42.1

@@ -1,780 +0,0 @@
-From 86911e57c556389eed386bc23d5e87dd520afec9 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Wed, 31 Jan 2024 22:57:07 -0700
-Subject: [PATCH] mb/dell: Add Latitude E5530 (Ivy Bridge)
-
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/e5530/Kconfig           |  37 ++++
- src/mainboard/dell/e5530/Kconfig.name      |   2 +
- src/mainboard/dell/e5530/Makefile.inc      |   6 +
- src/mainboard/dell/e5530/acpi/ec.asl       |   9 +
- src/mainboard/dell/e5530/acpi/platform.asl |  12 ++
- src/mainboard/dell/e5530/acpi/superio.asl  |   3 +
- src/mainboard/dell/e5530/acpi_tables.c     |  16 ++
- src/mainboard/dell/e5530/board_info.txt    |   6 +
- src/mainboard/dell/e5530/cmos.default      |   9 +
- src/mainboard/dell/e5530/cmos.layout       |  88 ++++++++++
- src/mainboard/dell/e5530/data.vbt          | Bin 0 -> 6144 bytes
- src/mainboard/dell/e5530/devicetree.cb     |  70 ++++++++
- src/mainboard/dell/e5530/dsdt.asl          |  30 ++++
- src/mainboard/dell/e5530/early_init.c      |  32 ++++
- src/mainboard/dell/e5530/gma-mainboard.ads |  20 +++
- src/mainboard/dell/e5530/gpio.c            | 194 +++++++++++++++++++++
- src/mainboard/dell/e5530/hda_verb.c        |  33 ++++
- src/mainboard/dell/e5530/mainboard.c       |  21 +++
- 18 files changed, 588 insertions(+)
- create mode 100644 src/mainboard/dell/e5530/Kconfig
- create mode 100644 src/mainboard/dell/e5530/Kconfig.name
- create mode 100644 src/mainboard/dell/e5530/Makefile.inc
- create mode 100644 src/mainboard/dell/e5530/acpi/ec.asl
- create mode 100644 src/mainboard/dell/e5530/acpi/platform.asl
- create mode 100644 src/mainboard/dell/e5530/acpi/superio.asl
- create mode 100644 src/mainboard/dell/e5530/acpi_tables.c
- create mode 100644 src/mainboard/dell/e5530/board_info.txt
- create mode 100644 src/mainboard/dell/e5530/cmos.default
- create mode 100644 src/mainboard/dell/e5530/cmos.layout
- create mode 100644 src/mainboard/dell/e5530/data.vbt
- create mode 100644 src/mainboard/dell/e5530/devicetree.cb
- create mode 100644 src/mainboard/dell/e5530/dsdt.asl
- create mode 100644 src/mainboard/dell/e5530/early_init.c
- create mode 100644 src/mainboard/dell/e5530/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/e5530/gpio.c
- create mode 100644 src/mainboard/dell/e5530/hda_verb.c
- create mode 100644 src/mainboard/dell/e5530/mainboard.c
-
-diff --git a/src/mainboard/dell/e5530/Kconfig b/src/mainboard/dell/e5530/Kconfig
-new file mode 100644
-index 0000000000..3faae4ee50
--- /dev/null
-+++ b/src/mainboard/dell/e5530/Kconfig
-@@ -0,0 +1,37 @@
-+if BOARD_DELL_LATITUDE_E5530
-+
-+config BOARD_SPECIFIC_OPTIONS
-+	def_bool y
-+	select BOARD_ROMSIZE_KB_12288
-+	select EC_ACPI
-+	select EC_DELL_MEC5035
-+	select GFX_GMA_PANEL_1_ON_LVDS
-+	select HAVE_ACPI_RESUME
-+	select HAVE_ACPI_TABLES
-+	select HAVE_CMOS_DEFAULT
-+	select HAVE_OPTION_TABLE
-+	select INTEL_GMA_HAVE_VBT
-+	select INTEL_INT15
-+	select MAINBOARD_HAS_LIBGFXINIT
-+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+	select SERIRQ_CONTINUOUS_MODE
-+	select SOUTHBRIDGE_INTEL_C216
-+	select SYSTEM_TYPE_LAPTOP
-+	select USE_NATIVE_RAMINIT
-+
-+config DRAM_RESET_GATE_GPIO
-+	default 60
-+
-+config MAINBOARD_DIR
-+	default "dell/e5530"
-+
-+config MAINBOARD_PART_NUMBER
-+	default "Latitude E5530"
-+
-+config USBDEBUG_HCD_INDEX
-+	default 2
-+
-+config VGA_BIOS_ID
-+	default "8086,0166"
-+
-+endif # BOARD_DELL_LATITUDE_E5530
-diff --git a/src/mainboard/dell/e5530/Kconfig.name b/src/mainboard/dell/e5530/Kconfig.name
-new file mode 100644
-index 0000000000..775963204a
--- /dev/null
-+++ b/src/mainboard/dell/e5530/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_DELL_LATITUDE_E5530
-+	bool "Latitude E5530"
-diff --git a/src/mainboard/dell/e5530/Makefile.inc b/src/mainboard/dell/e5530/Makefile.inc
-new file mode 100644
-index 0000000000..ba64e93eb8
--- /dev/null
-+++ b/src/mainboard/dell/e5530/Makefile.inc
-@@ -0,0 +1,6 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e5530/acpi/ec.asl b/src/mainboard/dell/e5530/acpi/ec.asl
-new file mode 100644
-index 0000000000..0d429410a9
--- /dev/null
-+++ b/src/mainboard/dell/e5530/acpi/ec.asl
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Device(EC)
-+{
-+	Name (_HID, EISAID("PNP0C09"))
-+	Name (_UID, 0)
-+	Name (_GPE, 16)
-+/* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e5530/acpi/platform.asl b/src/mainboard/dell/e5530/acpi/platform.asl
-new file mode 100644
-index 0000000000..2d24bbd9b9
--- /dev/null
-+++ b/src/mainboard/dell/e5530/acpi/platform.asl
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+	/* FIXME: EC support  */
-+	Return(Package() {0, 0})
-+}
-+
-+Method(_PTS,1)
-+{
-+	/* FIXME: EC support  */
-+}
-diff --git a/src/mainboard/dell/e5530/acpi/superio.asl b/src/mainboard/dell/e5530/acpi/superio.asl
-new file mode 100644
-index 0000000000..55b1db5b11
--- /dev/null
-+++ b/src/mainboard/dell/e5530/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <drivers/pc80/pc/ps2_controller.asl>
-diff --git a/src/mainboard/dell/e5530/acpi_tables.c b/src/mainboard/dell/e5530/acpi_tables.c
-new file mode 100644
-index 0000000000..e2759659bf
--- /dev/null
-+++ b/src/mainboard/dell/e5530/acpi_tables.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi_gnvs.h>
-+#include <soc/nvs.h>
-+
-+/* FIXME: check this function.  */
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+	/* The lid is open by default. */
-+	gnvs->lids = 1;
-+
-+	/* Temperature at which OS will shutdown */
-+	gnvs->tcrt = 100;
-+	/* Temperature at which OS will throttle CPU */
-+	gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/dell/e5530/board_info.txt b/src/mainboard/dell/e5530/board_info.txt
-new file mode 100644
-index 0000000000..4601a4aaba
--- /dev/null
-+++ b/src/mainboard/dell/e5530/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: laptop
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-+Release year: 2012
-diff --git a/src/mainboard/dell/e5530/cmos.default b/src/mainboard/dell/e5530/cmos.default
-new file mode 100644
-index 0000000000..279415dfd1
--- /dev/null
-+++ b/src/mainboard/dell/e5530/cmos.default
-@@ -0,0 +1,9 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+bluetooth=Enable
-+wwan=Enable
-+wlan=Enable
-+sata_mode=AHCI
-+me_state=Disabled
-diff --git a/src/mainboard/dell/e5530/cmos.layout b/src/mainboard/dell/e5530/cmos.layout
-new file mode 100644
-index 0000000000..1aa7e77bce
--- /dev/null
-+++ b/src/mainboard/dell/e5530/cmos.layout
-@@ -0,0 +1,88 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0	120	r	0	reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384	1	e	4	boot_option
-+388	4	h	0	reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395	4	e	6	debug_level
-+
-+#400	8	r	0	reserved for century byte
-+
-+# coreboot config options: southbridge
-+408	1	e	1	nmi
-+409	2	e	7	power_on_after_fail
-+411     1       e       9       sata_mode
-+
-+# coreboot config options: EC
-+412	1	e	1	bluetooth
-+413	1	e	1	wwan
-+414	1	e	1	wlan
-+
-+# coreboot config options: ME
-+424	1	e	14	me_state
-+425	2	h	0	me_state_prev
-+
-+# coreboot config options: northbridge
-+432	3	e	11	gfx_uma_size
-+435	2	e	12	hybrid_graphics_mode
-+440	8	h	0	volume
-+
-+# VBOOT
-+448	128	r	0	vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896	32	r	0	mrc_scrambler_seed
-+928	32	r	0	mrc_scrambler_seed_s3
-+960	16	r	0	mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984	16	h	0	check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID	value	text
-+1	0	Disable
-+1	1	Enable
-+2	0	Enable
-+2	1	Disable
-+4	0	Fallback
-+4	1	Normal
-+6	0	Emergency
-+6	1	Alert
-+6	2	Critical
-+6	3	Error
-+6	4	Warning
-+6	5	Notice
-+6	6	Info
-+6	7	Debug
-+6	8	Spew
-+7	0	Disable
-+7	1	Enable
-+7	2	Keep
-+9	0	AHCI
-+9	1	Compatible
-+11	0	32M
-+11	1	64M
-+11	2	96M
-+11	3	128M
-+11	4	160M
-+11	5	192M
-+11	6	224M
-+14	0	Normal
-+14	1	Disabled
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 447 984
-diff --git a/src/mainboard/dell/e5530/data.vbt b/src/mainboard/dell/e5530/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3
-GIT binary patch
-literal 6144
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-zuMja1N)bPb1cE+5)fYsCK!89MFQAGChyWpk5PuR<K|G+sLmxmOR4}u5=Rg`mj70g7
-zvgdDic6N4dW^QKhynd)>kS^cR)3#-(r*-?zo-O^C(kLvv8XM<+Y3tdt^YY!P?!oTe
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-zB3a%B!?6K=TJ$W+SJv@*9Lms{mTvWmU4Zanj_Z*lSqOGISzYp?yawOqLhVhRt#-E6
-zd)YW~h&meh-5prIE}Cr&7f?MMi&cqTt_^%Fa?>k(=`9jVoIf@}{g+WX#TpWuc+!2v
-zPG^>A|NZ2GlGsKdGqN{7>Fr7+Hc_^3z}uBhC4?nzOQ*!QyVugGjkK_~$bvtfY`h79
-z9rOI3;Mt}9)_G{zXTAPw`8T@6=Ut0r9R5;0#Zy|#8F;v4^UAmqft3iXL|`QXD-l?U
-Jz~2*rUjdP?m;3+#
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/e5530/devicetree.cb b/src/mainboard/dell/e5530/devicetree.cb
-new file mode 100644
-index 0000000000..2af748cf27
--- /dev/null
-+++ b/src/mainboard/dell/e5530/devicetree.cb
-@@ -0,0 +1,70 @@
-+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
-+	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
-+	register "gpu_cpu_backlight" = "0x00000000"
-+	register "gpu_dp_b_hotplug" = "4"
-+	register "gpu_dp_c_hotplug" = "4"
-+	register "gpu_dp_d_hotplug" = "4"
-+	register "gpu_panel_port_select" = "0"
-+	register "gpu_panel_power_backlight_off_delay" = "2300"
-+	register "gpu_panel_power_backlight_on_delay" = "2300"
-+	register "gpu_panel_power_cycle_delay" = "6"
-+	register "gpu_panel_power_down_delay" = "400"
-+	register "gpu_panel_power_up_delay" = "400"
-+	register "gpu_pch_backlight" = "0x03d003d0"
-+
-+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
-+
-+	device domain 0x0 on
-+		subsystemid 0x1028 0x053d inherit
-+
-+		device ref host_bridge on end
-+		device ref peg10 off end
-+		device ref igd on end
-+
-+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-+			register "docking_supported" = "1"
-+			register "gen1_dec" = "0x007c0681"
-+			register "gen2_dec" = "0x005c0921"
-+			register "gen3_dec" = "0x003c07e1"
-+			register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
-+			register "gpi0_routing" = "2"
-+			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
-+			register "pcie_port_coalesce" = "1"
-+			register "sata_interface_speed_support" = "0x3"
-+			register "sata_port_map" = "0x33"
-+			register "spi_lvscc" = "0x2005"
-+			register "spi_uvscc" = "0x2005"
-+			register "superspeed_capable_ports" = "0x0000000f"
-+			register "xhci_overcurrent_mapping" = "0x00000c03"
-+			register "xhci_switchable_ports" = "0x0000000f"
-+
-+			device ref xhci		on end
-+			device ref mei1		off end
-+			device ref mei2		off end
-+			device ref me_ide_r	off end
-+			device ref me_kt	off end
-+			device ref gbe		off end
-+			device ref ehci2	on end
-+			device ref hda		on end
-+			device ref pcie_rp1	on end # WWAN Slot
-+			device ref pcie_rp2	on end # SLAN Slot
-+			device ref pcie_rp3	on end # ExpressCard
-+			device ref pcie_rp4	off end
-+			device ref pcie_rp5	on end # Extra Half Mini PCIe slot
-+			device ref pcie_rp6	on end # SD/MMC Card Reader
-+			device ref pcie_rp7	on end # BCM5761 Ethernet
-+			device ref pcie_rp8	off end
-+			device ref ehci1	on end
-+			device ref pci_bridge	off end
-+			device ref lpc		on
-+				chip ec/dell/mec5035
-+					device pnp ff.0 on end
-+				end
-+			end
-+			device ref sata1	on end
-+			device ref smbus	on end
-+			device ref sata2	off end
-+			device ref thermal	off end
-+		end
-+	end
-+end
-diff --git a/src/mainboard/dell/e5530/dsdt.asl b/src/mainboard/dell/e5530/dsdt.asl
-new file mode 100644
-index 0000000000..7d13c55b08
--- /dev/null
-+++ b/src/mainboard/dell/e5530/dsdt.asl
-@@ -0,0 +1,30 @@
-+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <acpi/acpi.h>
-+
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	ACPI_DSDT_REV_2,
-+	OEM_ID,
-+	ACPI_TABLE_CREATOR,
-+	0x20141018	/* OEM revision */
-+)
-+{
-+	#include <acpi/dsdt_top.asl>
-+	#include "acpi/platform.asl"
-+	#include <cpu/intel/common/acpi/cpu.asl>
-+	#include <southbridge/intel/common/acpi/platform.asl>
-+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-+	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+
-+	Device (\_SB.PCI0)
-+	{
-+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-+	}
-+}
-diff --git a/src/mainboard/dell/e5530/early_init.c b/src/mainboard/dell/e5530/early_init.c
-new file mode 100644
-index 0000000000..00fd5f6795
--- /dev/null
-+++ b/src/mainboard/dell/e5530/early_init.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+	{ 1, 1, 0 },
-+	{ 1, 1, 0 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 2 },
-+	{ 1, 1, 2 },
-+	{ 1, 1, 3 },
-+	{ 1, 0, 3 },
-+	{ 1, 2, 4 },
-+	{ 1, 1, 4 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 5 },
-+	{ 1, 0, 6 },
-+	{ 1, 1, 6 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/e5530/gma-mainboard.ads b/src/mainboard/dell/e5530/gma-mainboard.ads
-new file mode 100644
-index 0000000000..1310830c8e
--- /dev/null
-+++ b/src/mainboard/dell/e5530/gma-mainboard.ads
-@@ -0,0 +1,20 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (
-+      HDMI1, -- mainboard HDMI
-+      DP2, -- dock DP
-+      DP3, -- dock DP
-+      Analog, --mainboard VGA
-+      LVDS,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/e5530/gpio.c b/src/mainboard/dell/e5530/gpio.c
-new file mode 100644
-index 0000000000..0599f13921
--- /dev/null
-+++ b/src/mainboard/dell/e5530/gpio.c
-@@ -0,0 +1,194 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_GPIO,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_GPIO,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio1 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio12 = GPIO_DIR_OUTPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio12 = GPIO_LEVEL_HIGH,
-+	.gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+	.gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio13 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_GPIO,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_INPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio53 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_GPIO,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+	.gpio74 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/e5530/hda_verb.c b/src/mainboard/dell/e5530/hda_verb.c
-new file mode 100644
-index 0000000000..4c7c36ee05
--- /dev/null
-+++ b/src/mainboard/dell/e5530/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76df,	/* Codec Vendor / Device ID: IDT */
-+	0x1028053d,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x1028053d),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0),
-+
-+	0x80862806,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/e5530/mainboard.c b/src/mainboard/dell/e5530/mainboard.c
-new file mode 100644
-index 0000000000..31e49802fc
--- /dev/null
-+++ b/src/mainboard/dell/e5530/mainboard.c
-@@ -0,0 +1,21 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/device.h>
-+#include <drivers/intel/gma/int15.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+#include <ec/acpi/ec.h>
-+#include <console/console.h>
-+#include <pc80/keyboard.h>
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+
-+	/* FIXME: fix these values. */
-+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
-+					GMA_INT15_PANEL_FIT_DEFAULT,
-+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+	.enable_dev = mainboard_enable,
-+};
-- 
-2.43.0
-
@@ -0,0 +1,164 @@
+From 38b9e571e5b2a7116b06fb9d99bccd8b03450f9a Mon Sep 17 00:00:00 2001
+From: risapav <risapav@gmail.com>
+Date: Sun, 17 Dec 2023 16:54:07 +0100
+Subject: [PATCH] x220_edp modification introduced, similar to x230_edp
+
+---
+ src/mainboard/lenovo/x220/Kconfig             |  13 ++++++-----
+ src/mainboard/lenovo/x220/Kconfig.name        |   3 +++
+ src/mainboard/lenovo/x220/Makefile.inc        |   6 +++++
+ .../lenovo/x220/variants/x220_edp/data.vbt    | Bin 0 -> 4281 bytes
+ .../x220/variants/x220_edp/gma-mainboard.ads  |  21 ++++++++++++++++++
+ 5 files changed, 38 insertions(+), 5 deletions(-)
+ create mode 100644 src/mainboard/lenovo/x220/variants/x220_edp/data.vbt
+ create mode 100644 src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
+
+diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
+index eeb55b4393..bc73a47df9 100644
+--- a/src/mainboard/lenovo/x220/Kconfig
+++ b/src/mainboard/lenovo/x220/Kconfig
+@@ -1,4 +1,4 @@
+-if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
+if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 || BOARD_LENOVO_X220_EDP
+ 
+ config BOARD_SPECIFIC_OPTIONS
+ 	def_bool y
+@@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select DRIVERS_RICOH_RCE822
+ 	select EC_LENOVO_H8
+ 	select EC_LENOVO_PMH7
+-	select GFX_GMA_PANEL_1_ON_LVDS
+	select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 
+ 	select H8_HAS_BAT_THRESHOLDS_IMPL
+ 	select HAVE_ACPI_RESUME
+ 	select HAVE_ACPI_TABLES
+@@ -41,19 +41,22 @@ config MAINBOARD_DIR
+ 	default "lenovo/x220"
+ 
+ config VARIANT_DIR
+-	default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
+	default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X220_EDP
+ 	default "x1" if BOARD_LENOVO_X1
+ 
+ config FMDFILE
+ 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
+ 
+ config MAINBOARD_PART_NUMBER
+-	default "ThinkPad X220" if BOARD_LENOVO_X220
+	default "ThinkPad X220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220_EDP
+ 	default "ThinkPad X220i" if BOARD_LENOVO_X220I
+ 	default "ThinkPad X1" if BOARD_LENOVO_X1
+ 
+ config OVERRIDE_DEVICETREE
+ 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+	
+config INTEL_GMA_VBT_FILE
+       default "src/mainboard/\$(MAINBOARDDIR)/variants/x220_edp/data.vbt" if BOARD_LENOVO_X220_EDP	
+ 
+ config USBDEBUG_HCD_INDEX
+ 	int
+@@ -75,4 +78,4 @@ config PS2K_EISAID
+ config PS2M_EISAID
+ 	default "LEN0020"
+ 
+-endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
+endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 || BOARD_LENOVO_X220_EDP
+diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name
+index 988ac4fb55..cd501954e0 100644
+--- a/src/mainboard/lenovo/x220/Kconfig.name
+++ b/src/mainboard/lenovo/x220/Kconfig.name
+@@ -6,3 +6,6 @@ config BOARD_LENOVO_X220I
+ 
+ config BOARD_LENOVO_X1
+ 	bool "ThinkPad X1"
+	
+config BOARD_LENOVO_X220_EDP
+	bool "ThinkPad X220 eDP Mod (2K/FHD)"
+diff --git a/src/mainboard/lenovo/x220/Makefile.inc b/src/mainboard/lenovo/x220/Makefile.inc
+index b104bb52a9..052bf17a22 100644
+--- a/src/mainboard/lenovo/x220/Makefile.inc
+++ b/src/mainboard/lenovo/x220/Makefile.inc
+@@ -4,6 +4,12 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
+ romstage-y += variants/$(VARIANT_DIR)/gpio.c
+ romstage-y += variants/$(VARIANT_DIR)/romstage.c
+ 
+
+ifeq ($(CONFIG_BOARD_LENOVO_X220_EDP),y)
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x220_edp/gma-mainboard.ads
+else
+ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+endif
+
+ bootblock-y += early_init.c
+ romstage-y += early_init.c
+diff --git a/src/mainboard/lenovo/x220/variants/x220_edp/data.vbt b/src/mainboard/lenovo/x220/variants/x220_edp/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
+GIT binary patch
+literal 4281
+zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^
+zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
+zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
+zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
+zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
+zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
+z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
+zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
+z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
+z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
+zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT
+zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
+z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}(
+z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg
+zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW>
+zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn
+zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L
+zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy;
+z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY
+zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
+zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
+zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
+z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
+zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
+zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
+zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
+z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
+zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
+zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH
+z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
+zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
+p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads b/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
+new file mode 100644
+index 0000000000..f7cf0bc264
+--- /dev/null
+++ b/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
+@@ -0,0 +1,21 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (DP1,
+      DP2,
+      DP3,
+      HDMI1,
+      HDMI2,
+      HDMI3,
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
+-- 
+2.40.1
+
@@ -1,41 +0,0 @@
-From b2cf0657a2058118baf6f4ec96e356de3c9e493e Mon Sep 17 00:00:00 2001
-From: Riku Viitanen <riku.viitanen@protonmail.com>
-Date: Sun, 11 Feb 2024 19:02:20 +0200
-Subject: [PATCH] hp8560w: Add MXM System Infomation Structure
-
-Change-Id: I45b421f2d7baf8ca8dedbd3b1ab1e38392b6219b
-Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
---
- src/mainboard/hp/snb_ivb_laptops/Makefile.mk      |   6 ++++++
- .../hp/snb_ivb_laptops/variants/8560w/mxm-30-sis  | Bin 0 -> 129 bytes
- 2 files changed, 6 insertions(+)
- create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
-
-diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
-index c007bb68cd..7950abbc4e 100644
--- a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
-+++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
-@@ -9,3 +9,9 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb
- 
- # FIXME: Other variants with same size onboard RAM may exist.
- SPD_SOURCES = hynix_4g
-+
-+ifeq ($(CONFIG_BOARD_HP_8560W),y)
-+cbfs-files-y += mxm-30-sis
-+mxm-30-sis-file := variants/$(VARIANT_DIR)/mxm-30-sis
-+mxm-30-sis-type := raw
-+endif
-diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
-new file mode 100644
-index 0000000000000000000000000000000000000000..7e4e245a50d8d5d36ddb22e3b1aed3fa87a2f57d
-GIT binary patch
-literal 129
-zcmeZ`@Qr6?sAMn@-0}aX9Rou`%?mKiz;Fq|&xF!hw;=rNM_^h3Dy{$(SAdE$zF=lx
-o@?l{RW{6;7W}LwIl$Vj2apDSgHUS2PJFE;0Kxqas5d=FN0HAs+0RR91
-
-literal 0
-HcmV?d00001
-
-- 
-2.43.1
-
@@ -1,775 +0,0 @@
-From 7c7ce2087e1ff5f0eedb65793254163d01be3056 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Wed, 7 Feb 2024 10:23:38 -0700
-Subject: [PATCH] mb/dell: Add Latitude E5520 (Sandybridge)
-
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/e5520/Kconfig           |  37 ++++
- src/mainboard/dell/e5520/Kconfig.name      |   2 +
- src/mainboard/dell/e5520/Makefile.inc      |   5 +
- src/mainboard/dell/e5520/acpi/ec.asl       |   9 +
- src/mainboard/dell/e5520/acpi/platform.asl |  12 ++
- src/mainboard/dell/e5520/acpi/superio.asl  |   3 +
- src/mainboard/dell/e5520/acpi_tables.c     |  16 ++
- src/mainboard/dell/e5520/board_info.txt    |   6 +
- src/mainboard/dell/e5520/cmos.default      |   9 +
- src/mainboard/dell/e5520/cmos.layout       |  88 ++++++++++
- src/mainboard/dell/e5520/data.vbt          | Bin 0 -> 6144 bytes
- src/mainboard/dell/e5520/devicetree.cb     |  66 +++++++
- src/mainboard/dell/e5520/dsdt.asl          |  30 ++++
- src/mainboard/dell/e5520/early_init.c      |  32 ++++
- src/mainboard/dell/e5520/gma-mainboard.ads |  20 +++
- src/mainboard/dell/e5520/gpio.c            | 195 +++++++++++++++++++++
- src/mainboard/dell/e5520/hda_verb.c        |  33 ++++
- src/mainboard/dell/e5520/mainboard.c       |  21 +++
- 18 files changed, 584 insertions(+)
- create mode 100644 src/mainboard/dell/e5520/Kconfig
- create mode 100644 src/mainboard/dell/e5520/Kconfig.name
- create mode 100644 src/mainboard/dell/e5520/Makefile.inc
- create mode 100644 src/mainboard/dell/e5520/acpi/ec.asl
- create mode 100644 src/mainboard/dell/e5520/acpi/platform.asl
- create mode 100644 src/mainboard/dell/e5520/acpi/superio.asl
- create mode 100644 src/mainboard/dell/e5520/acpi_tables.c
- create mode 100644 src/mainboard/dell/e5520/board_info.txt
- create mode 100644 src/mainboard/dell/e5520/cmos.default
- create mode 100644 src/mainboard/dell/e5520/cmos.layout
- create mode 100644 src/mainboard/dell/e5520/data.vbt
- create mode 100644 src/mainboard/dell/e5520/devicetree.cb
- create mode 100644 src/mainboard/dell/e5520/dsdt.asl
- create mode 100644 src/mainboard/dell/e5520/early_init.c
- create mode 100644 src/mainboard/dell/e5520/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/e5520/gpio.c
- create mode 100644 src/mainboard/dell/e5520/hda_verb.c
- create mode 100644 src/mainboard/dell/e5520/mainboard.c
-
-diff --git a/src/mainboard/dell/e5520/Kconfig b/src/mainboard/dell/e5520/Kconfig
-new file mode 100644
-index 0000000000..213c54cf5c
--- /dev/null
-+++ b/src/mainboard/dell/e5520/Kconfig
-@@ -0,0 +1,37 @@
-+if BOARD_DELL_LATITUDE_E5520
-+
-+config BOARD_SPECIFIC_OPTIONS
-+	def_bool y
-+	select BOARD_ROMSIZE_KB_6144
-+	select EC_ACPI
-+	select EC_DELL_MEC5035
-+	select GFX_GMA_PANEL_1_ON_LVDS
-+	select HAVE_ACPI_RESUME
-+	select HAVE_ACPI_TABLES
-+	select HAVE_CMOS_DEFAULT
-+	select HAVE_OPTION_TABLE
-+	select INTEL_GMA_HAVE_VBT
-+	select INTEL_INT15
-+	select MAINBOARD_HAS_LIBGFXINIT
-+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+	select SERIRQ_CONTINUOUS_MODE
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+	select SYSTEM_TYPE_LAPTOP
-+	select USE_NATIVE_RAMINIT
-+
-+config DRAM_RESET_GATE_GPIO
-+	default 60
-+
-+config MAINBOARD_DIR
-+	default "dell/e5520"
-+
-+config MAINBOARD_PART_NUMBER
-+	default "Latitude E5520"
-+
-+config USBDEBUG_HCD_INDEX
-+	default 2
-+
-+config VGA_BIOS_ID
-+	default "8086,0126"
-+
-+endif # BOARD_DELL_LATITUDE_E5520
-diff --git a/src/mainboard/dell/e5520/Kconfig.name b/src/mainboard/dell/e5520/Kconfig.name
-new file mode 100644
-index 0000000000..c88913e8b3
--- /dev/null
-+++ b/src/mainboard/dell/e5520/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_DELL_LATITUDE_E5520
-+	bool "Latitude E5520"
-diff --git a/src/mainboard/dell/e5520/Makefile.inc b/src/mainboard/dell/e5520/Makefile.inc
-new file mode 100644
-index 0000000000..18391d8b18
--- /dev/null
-+++ b/src/mainboard/dell/e5520/Makefile.inc
-@@ -0,0 +1,5 @@
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e5520/acpi/ec.asl b/src/mainboard/dell/e5520/acpi/ec.asl
-new file mode 100644
-index 0000000000..0d429410a9
--- /dev/null
-+++ b/src/mainboard/dell/e5520/acpi/ec.asl
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Device(EC)
-+{
-+	Name (_HID, EISAID("PNP0C09"))
-+	Name (_UID, 0)
-+	Name (_GPE, 16)
-+/* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e5520/acpi/platform.asl b/src/mainboard/dell/e5520/acpi/platform.asl
-new file mode 100644
-index 0000000000..2d24bbd9b9
--- /dev/null
-+++ b/src/mainboard/dell/e5520/acpi/platform.asl
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+	/* FIXME: EC support  */
-+	Return(Package() {0, 0})
-+}
-+
-+Method(_PTS,1)
-+{
-+	/* FIXME: EC support  */
-+}
-diff --git a/src/mainboard/dell/e5520/acpi/superio.asl b/src/mainboard/dell/e5520/acpi/superio.asl
-new file mode 100644
-index 0000000000..55b1db5b11
--- /dev/null
-+++ b/src/mainboard/dell/e5520/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <drivers/pc80/pc/ps2_controller.asl>
-diff --git a/src/mainboard/dell/e5520/acpi_tables.c b/src/mainboard/dell/e5520/acpi_tables.c
-new file mode 100644
-index 0000000000..e2759659bf
--- /dev/null
-+++ b/src/mainboard/dell/e5520/acpi_tables.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi_gnvs.h>
-+#include <soc/nvs.h>
-+
-+/* FIXME: check this function.  */
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+	/* The lid is open by default. */
-+	gnvs->lids = 1;
-+
-+	/* Temperature at which OS will shutdown */
-+	gnvs->tcrt = 100;
-+	/* Temperature at which OS will throttle CPU */
-+	gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/dell/e5520/board_info.txt b/src/mainboard/dell/e5520/board_info.txt
-new file mode 100644
-index 0000000000..34d5ad9e0b
--- /dev/null
-+++ b/src/mainboard/dell/e5520/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: laptop
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-+Release year: 2011
-diff --git a/src/mainboard/dell/e5520/cmos.default b/src/mainboard/dell/e5520/cmos.default
-new file mode 100644
-index 0000000000..279415dfd1
--- /dev/null
-+++ b/src/mainboard/dell/e5520/cmos.default
-@@ -0,0 +1,9 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+bluetooth=Enable
-+wwan=Enable
-+wlan=Enable
-+sata_mode=AHCI
-+me_state=Disabled
-diff --git a/src/mainboard/dell/e5520/cmos.layout b/src/mainboard/dell/e5520/cmos.layout
-new file mode 100644
-index 0000000000..1aa7e77bce
--- /dev/null
-+++ b/src/mainboard/dell/e5520/cmos.layout
-@@ -0,0 +1,88 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0	120	r	0	reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384	1	e	4	boot_option
-+388	4	h	0	reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395	4	e	6	debug_level
-+
-+#400	8	r	0	reserved for century byte
-+
-+# coreboot config options: southbridge
-+408	1	e	1	nmi
-+409	2	e	7	power_on_after_fail
-+411     1       e       9       sata_mode
-+
-+# coreboot config options: EC
-+412	1	e	1	bluetooth
-+413	1	e	1	wwan
-+414	1	e	1	wlan
-+
-+# coreboot config options: ME
-+424	1	e	14	me_state
-+425	2	h	0	me_state_prev
-+
-+# coreboot config options: northbridge
-+432	3	e	11	gfx_uma_size
-+435	2	e	12	hybrid_graphics_mode
-+440	8	h	0	volume
-+
-+# VBOOT
-+448	128	r	0	vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896	32	r	0	mrc_scrambler_seed
-+928	32	r	0	mrc_scrambler_seed_s3
-+960	16	r	0	mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984	16	h	0	check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID	value	text
-+1	0	Disable
-+1	1	Enable
-+2	0	Enable
-+2	1	Disable
-+4	0	Fallback
-+4	1	Normal
-+6	0	Emergency
-+6	1	Alert
-+6	2	Critical
-+6	3	Error
-+6	4	Warning
-+6	5	Notice
-+6	6	Info
-+6	7	Debug
-+6	8	Spew
-+7	0	Disable
-+7	1	Enable
-+7	2	Keep
-+9	0	AHCI
-+9	1	Compatible
-+11	0	32M
-+11	1	64M
-+11	2	96M
-+11	3	128M
-+11	4	160M
-+11	5	192M
-+11	6	224M
-+14	0	Normal
-+14	1	Disabled
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 447 984
-diff --git a/src/mainboard/dell/e5520/data.vbt b/src/mainboard/dell/e5520/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729
-GIT binary patch
-literal 6144
-zcmeHKZ){Ul6hE);wSBvNZ|mL$bmQOM2BTvXUI!}^N9ejTij1vnu+)Wx6<c9(Y_%K6
-zzOV-@f<ehpWB5RHBpMBgG7}RuMuM2=l*E{6G$wq&gqTQ3#E2RZsOP@dvW*rP7>Fjj
-z&F`Lj?>YC}bI(2Z+}C+6zKyiGrosQXuW7A+&1%<rN+Y1ck(}dLrx)Ma#^x>lnvFGE
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-zXJ@#}wJyGMTXTcY<%@TBKh@(3hP$Gjv}E}rx-%9D_eLXhYe!c&-VyDg-Cdo1>Biji
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-H=7E0zE^L4Z
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/e5520/devicetree.cb b/src/mainboard/dell/e5520/devicetree.cb
-new file mode 100644
-index 0000000000..bef96ac14c
--- /dev/null
-+++ b/src/mainboard/dell/e5520/devicetree.cb
-@@ -0,0 +1,66 @@
-+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
-+	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
-+	register "gpu_cpu_backlight" = "0x00000218"
-+	register "gpu_dp_b_hotplug" = "4"
-+	register "gpu_dp_c_hotplug" = "4"
-+	register "gpu_dp_d_hotplug" = "4"
-+	register "gpu_panel_port_select" = "0"
-+	register "gpu_panel_power_backlight_off_delay" = "2300"
-+	register "gpu_panel_power_backlight_on_delay" = "2300"
-+	register "gpu_panel_power_cycle_delay" = "6"
-+	register "gpu_panel_power_down_delay" = "400"
-+	register "gpu_panel_power_up_delay" = "400"
-+	register "gpu_pch_backlight" = "0x13121312"
-+
-+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
-+
-+	device domain 0x0 on
-+		subsystemid 0x1028 0x049a inherit
-+
-+		device ref host_bridge on end # Host bridge
-+		device ref peg10 on end # PEG
-+		device ref igd on end # iGPU
-+
-+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-+			register "docking_supported" = "1"
-+			register "gen1_dec" = "0x007c0681"
-+			register "gen2_dec" = "0x007c0901"
-+			register "gen3_dec" = "0x003c07e1"
-+			register "gen4_dec" = "0x001c0901"
-+			register "gpi0_routing" = "2"
-+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
-+			register "pcie_port_coalesce" = "1"
-+			register "sata_interface_speed_support" = "0x3"
-+			register "sata_port_map" = "0x3b"
-+			register "spi_lvscc" = "0x2005"
-+			register "spi_uvscc" = "0x2005"
-+
-+			device ref mei1		off end
-+			device ref mei2		off end
-+			device ref me_ide_r	off end
-+			device ref me_kt	off end
-+			device ref gbe		off end
-+			device ref ehci2	on end
-+			device ref hda		on end
-+			device ref pcie_rp1	on end
-+			device ref pcie_rp2	on end
-+			device ref pcie_rp3	on end
-+			device ref pcie_rp4	off end
-+			device ref pcie_rp5	on end
-+			device ref pcie_rp6	on end
-+			device ref pcie_rp7	on end
-+			device ref pcie_rp8	off end
-+			device ref ehci1	on end
-+			device ref pci_bridge	off end
-+			device ref lpc		on
-+				chip ec/dell/mec5035
-+					device pnp ff.0 on end
-+				end
-+			end
-+			device ref sata1 on end
-+			device ref smbus on end
-+			device ref sata2 off end
-+			device ref thermal off end
-+		end
-+	end
-+end
-diff --git a/src/mainboard/dell/e5520/dsdt.asl b/src/mainboard/dell/e5520/dsdt.asl
-new file mode 100644
-index 0000000000..7d13c55b08
--- /dev/null
-+++ b/src/mainboard/dell/e5520/dsdt.asl
-@@ -0,0 +1,30 @@
-+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <acpi/acpi.h>
-+
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	ACPI_DSDT_REV_2,
-+	OEM_ID,
-+	ACPI_TABLE_CREATOR,
-+	0x20141018	/* OEM revision */
-+)
-+{
-+	#include <acpi/dsdt_top.asl>
-+	#include "acpi/platform.asl"
-+	#include <cpu/intel/common/acpi/cpu.asl>
-+	#include <southbridge/intel/common/acpi/platform.asl>
-+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-+	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+
-+	Device (\_SB.PCI0)
-+	{
-+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-+	}
-+}
-diff --git a/src/mainboard/dell/e5520/early_init.c b/src/mainboard/dell/e5520/early_init.c
-new file mode 100644
-index 0000000000..7297921546
--- /dev/null
-+++ b/src/mainboard/dell/e5520/early_init.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+	{ 1, 1, 0 },
-+	{ 1, 1, 0 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 2 },
-+	{ 1, 1, 2 },
-+	{ 1, 1, 3 },
-+	{ 1, 1, 3 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 7 },
-+	{ 1, 1, 6 },
-+	{ 1, 1, 6 },
-+	{ 1, 1, 7 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/e5520/gma-mainboard.ads b/src/mainboard/dell/e5520/gma-mainboard.ads
-new file mode 100644
-index 0000000000..2a16f44360
--- /dev/null
-+++ b/src/mainboard/dell/e5520/gma-mainboard.ads
-@@ -0,0 +1,20 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (
-+      HDMI1, -- mainboard HDMI
-+      DP2, -- dock DP
-+      DP3, -- dock DP
-+      Analog, -- mainboard VGA
-+      LVDS,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/e5520/gpio.c b/src/mainboard/dell/e5520/gpio.c
-new file mode 100644
-index 0000000000..f76b93d9f0
--- /dev/null
-+++ b/src/mainboard/dell/e5520/gpio.c
-@@ -0,0 +1,195 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_NATIVE,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_GPIO,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_NATIVE,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio12 = GPIO_DIR_OUTPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio12 = GPIO_LEVEL_HIGH,
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_GPIO,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_NATIVE,
-+	.gpio50 = GPIO_MODE_GPIO,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_GPIO,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_GPIO,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_OUTPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio46 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio50 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_OUTPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio53 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio55 = GPIO_DIR_OUTPUT,
-+	.gpio56 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_LOW,
-+	.gpio37 = GPIO_LEVEL_LOW,
-+	.gpio46 = GPIO_LEVEL_HIGH,
-+	.gpio50 = GPIO_LEVEL_HIGH,
-+	.gpio51 = GPIO_LEVEL_LOW,
-+	.gpio55 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_NATIVE,
-+	.gpio69 = GPIO_MODE_NATIVE,
-+	.gpio70 = GPIO_MODE_NATIVE,
-+	.gpio71 = GPIO_MODE_NATIVE,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_GPIO,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio74 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/e5520/hda_verb.c b/src/mainboard/dell/e5520/hda_verb.c
-new file mode 100644
-index 0000000000..e2efee3646
--- /dev/null
-+++ b/src/mainboard/dell/e5520/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x1028049a,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x1028049a),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/e5520/mainboard.c b/src/mainboard/dell/e5520/mainboard.c
-new file mode 100644
-index 0000000000..31e49802fc
--- /dev/null
-+++ b/src/mainboard/dell/e5520/mainboard.c
-@@ -0,0 +1,21 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/device.h>
-+#include <drivers/intel/gma/int15.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+#include <ec/acpi/ec.h>
-+#include <console/console.h>
-+#include <pc80/keyboard.h>
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+
-+	/* FIXME: fix these values. */
-+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
-+					GMA_INT15_PANEL_FIT_DEFAULT,
-+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+	.enable_dev = mainboard_enable,
-+};
-- 
-2.43.0
-
@@ -1,292 +0,0 @@
-From 7c755b4502ea007f2216ea76f2ed734452def883 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Sat, 2 Mar 2024 22:51:09 +0000
-Subject: [PATCH 1/2] nb/intel/haswell: make IOMMU a runtime option
-
-When I tested graphics cards on a coreboot port for Dell
-OptiPlex 9020 SFF, I could not use a graphics card unless
-I set iommu=off on the Linux cmdline.
-
-Coreboot's current behaviour is to check whether the CPU
-has vt-d support and, if it does, initialise the IOMMU.
-
-This patch maintains the current behaviour by default, but
-allows the user to turn *off* the IOMMU, even if vt-d is
-supported by the host CPU.
-
-If iommu=Disable is specified, the check will not be
-performed, and the IOMMU will be left disabled. This option
-has been added to all current Haswell boards, though it is
-recommended to leave the IOMMU turned on in most setups.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- src/mainboard/asrock/b85m_pro4/cmos.default    | 1 +
- src/mainboard/asrock/b85m_pro4/cmos.layout     | 3 +++
- src/mainboard/asrock/h81m-hds/cmos.default     | 1 +
- src/mainboard/asrock/h81m-hds/cmos.layout      | 6 ++++++
- src/mainboard/dell/optiplex_9020/cmos.default  | 1 +
- src/mainboard/dell/optiplex_9020/cmos.layout   | 6 ++++++
- src/mainboard/google/beltino/cmos.layout       | 5 +++++
- src/mainboard/google/slippy/cmos.layout        | 5 +++++
- src/mainboard/intel/baskingridge/cmos.layout   | 4 ++++
- src/mainboard/lenovo/haswell/cmos.default      | 1 +
- src/mainboard/lenovo/haswell/cmos.layout       | 3 +++
- src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
- src/mainboard/supermicro/x10slm-f/cmos.layout  | 6 ++++++
- src/northbridge/intel/haswell/early_init.c     | 5 +++++
- 14 files changed, 48 insertions(+)
-
-diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default
-index c51001c03c..1c5c17f841 100644
--- a/src/mainboard/asrock/b85m_pro4/cmos.default
-+++ b/src/mainboard/asrock/b85m_pro4/cmos.default
-@@ -2,3 +2,4 @@ boot_option=Fallback
- debug_level=Debug
- nmi=Enable
- power_on_after_fail=Disable
-+iommu=Enable
-diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout
-index efdc333fc2..c9883ea71d 100644
--- a/src/mainboard/asrock/b85m_pro4/cmos.layout
-+++ b/src/mainboard/asrock/b85m_pro4/cmos.layout
-@@ -11,6 +11,7 @@
- 	395	4	e	4	debug_level
- 	408	1	e	1	nmi
- 	409	2	e	5	power_on_after_fail
-+	412	1	e	6	iommu
- 	984	16	h	0	check_sum
- # -----------------------------------------------------------------
- 
-@@ -38,6 +39,8 @@
- 	5	0	Disable
- 	5	1	Enable
- 	5	2	Keep
-+	6	0	Disable
-+	6	1	Enable
- # -----------------------------------------------------------------
- 
- # -----------------------------------------------------------------
-diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default
-index c51001c03c..1c5c17f841 100644
--- a/src/mainboard/asrock/h81m-hds/cmos.default
-+++ b/src/mainboard/asrock/h81m-hds/cmos.default
-@@ -2,3 +2,4 @@ boot_option=Fallback
- debug_level=Debug
- nmi=Enable
- power_on_after_fail=Disable
-+iommu=Enable
-diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout
-index c9ba76c78f..95ee3d36fb 100644
--- a/src/mainboard/asrock/h81m-hds/cmos.layout
-+++ b/src/mainboard/asrock/h81m-hds/cmos.layout
-@@ -21,6 +21,9 @@ entries
- 408	1	e	1	nmi
- 409	2	e	5	power_on_after_fail
- 
-+# enable or disable iommu
-+412	1	e	6	iommu
-+
- # coreboot config options: check sums
- 984	16	h	0	check_sum
- 
-@@ -52,6 +55,9 @@ enumerations
- 5	1	Enable
- 5	2	Keep
- 
-+6	0	Disable
-+6	1	Enable
-+
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
-index b159660aa8..8253570f19 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
-+++ b/src/mainboard/dell/optiplex_9020/cmos.default
-@@ -2,3 +2,4 @@ boot_option=Fallback
- debug_level=Debug
- nmi=Disable
- power_on_after_fail=Disable
-+iommu=Enable
-diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
-index c9ba76c78f..72ff9c4bee 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
-+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
-@@ -21,6 +21,9 @@ entries
- 408	1	e	1	nmi
- 409	2	e	5	power_on_after_fail
- 
-+# turn iommu on or off
-+412	1	e	6	iommu
-+
- # coreboot config options: check sums
- 984	16	h	0	check_sum
- 
-@@ -52,6 +55,9 @@ enumerations
- 5	1	Enable
- 5	2	Keep
- 
-+6	0	Disable
-+6	1	Enable
-+
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout
-index 78d44c1415..c143979ae1 100644
--- a/src/mainboard/google/beltino/cmos.layout
-+++ b/src/mainboard/google/beltino/cmos.layout
-@@ -19,6 +19,9 @@ entries
- 408	1	e	1	nmi
- 409	2	e	7	power_on_after_fail
- 
-+# enable or disable iommu
-+412	1	e	8	iommu
-+
- # coreboot config options: bootloader
- #Used by ChromeOS:
- 416	128	r	0	vbnv
-@@ -47,6 +50,8 @@ enumerations
- 7	0	Disable
- 7	1	Enable
- 7	2	Keep
-+8	0	Disable
-+8	1	Enable
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout
-index 78d44c1415..c143979ae1 100644
--- a/src/mainboard/google/slippy/cmos.layout
-+++ b/src/mainboard/google/slippy/cmos.layout
-@@ -19,6 +19,9 @@ entries
- 408	1	e	1	nmi
- 409	2	e	7	power_on_after_fail
- 
-+# enable or disable iommu
-+412	1	e	8	iommu
-+
- # coreboot config options: bootloader
- #Used by ChromeOS:
- 416	128	r	0	vbnv
-@@ -47,6 +50,8 @@ enumerations
- 7	0	Disable
- 7	1	Enable
- 7	2	Keep
-+8	0	Disable
-+8	1	Enable
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout
-index 78d44c1415..f2c602f541 100644
--- a/src/mainboard/intel/baskingridge/cmos.layout
-+++ b/src/mainboard/intel/baskingridge/cmos.layout
-@@ -19,6 +19,8 @@ entries
- 408	1	e	1	nmi
- 409	2	e	7	power_on_after_fail
- 
-+412	1	e	8	iommu
-+
- # coreboot config options: bootloader
- #Used by ChromeOS:
- 416	128	r	0	vbnv
-@@ -47,6 +49,8 @@ enumerations
- 7	0	Disable
- 7	1	Enable
- 7	2	Keep
-+8	0	Disable
-+8	1	Enable
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default
-index bb8626d48b..051658d757 100644
--- a/src/mainboard/lenovo/haswell/cmos.default
-+++ b/src/mainboard/lenovo/haswell/cmos.default
-@@ -12,3 +12,4 @@ trackpoint=Enable
- backlight=Keyboard
- enable_dual_graphics=Disable
- usb_always_on=Disable
-+iommu=Enable
-diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout
-index 27915d3ab7..59df76b64c 100644
--- a/src/mainboard/lenovo/haswell/cmos.layout
-+++ b/src/mainboard/lenovo/haswell/cmos.layout
-@@ -23,6 +23,7 @@ entries
- 
- # coreboot config options: EC
- 411	1	e	8	first_battery
-+413	1	e	14	iommu
- 415	1	e	1	wlan
- 416	1	e	1	trackpoint
- 417	1	e	1	fn_ctrl_swap
-@@ -72,6 +73,8 @@ enumerations
- 13	0	Disable
- 13	1	AC and battery
- 13	2	AC only
-+14	0	Disable
-+14	1	Enable
- 
- # -----------------------------------------------------------------
- checksums
-diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default
-index f4047147f7..eea2c36b88 100644
--- a/src/mainboard/supermicro/x10slm-f/cmos.default
-+++ b/src/mainboard/supermicro/x10slm-f/cmos.default
-@@ -3,3 +3,4 @@ debug_level=Debug
- nmi=Enable
- power_on_after_fail=Keep
- hide_ast2400=Disable
-+iommu=Enable
-diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout
-index 38ba87aa45..24d39e97ee 100644
--- a/src/mainboard/supermicro/x10slm-f/cmos.layout
-+++ b/src/mainboard/supermicro/x10slm-f/cmos.layout
-@@ -21,6 +21,9 @@ entries
- 408	1	e	1	nmi
- 409	2	e	5	power_on_after_fail
- 
-+# enable or disable iommu
-+412	1	e	6	iommu
-+
- # coreboot config options: mainboard
- 416	1	e	1	hide_ast2400
- 
-@@ -55,6 +58,9 @@ enumerations
- 5	1	Enable
- 5	2	Keep
- 
-+6	0	Disable
-+6	1	Enable
-+
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
-index e47deb5da6..1a7e0b1076 100644
--- a/src/northbridge/intel/haswell/early_init.c
-+++ b/src/northbridge/intel/haswell/early_init.c
-@@ -5,6 +5,7 @@
- #include <device/mmio.h>
- #include <device/pci_def.h>
- #include <device/pci_ops.h>
-+#include <option.h>
- 
- #include "haswell.h"
- 
-@@ -157,6 +158,10 @@ static void haswell_setup_misc(void)
- static void haswell_setup_iommu(void)
- {
- 	const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
-+	u8 enable_iommu = get_uint_option("iommu", 1);
-+
-+	if (!enable_iommu)
-+		return;
- 
- 	if (capid0_a & VTD_DISABLE)
- 		return;
-- 
-2.39.2
-
@@ -1,29 +0,0 @@
-From 61041d49b94236400e836b8ea518d3a064b95c4e Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Sat, 2 Mar 2024 23:00:09 +0000
-Subject: [PATCH 2/2] dell/optiplex_9020: Disable IOMMU by default
-
-Needed to make graphics cards work. Turning it on is
-recommended if only using iGPU, otherwise leave it off
-by default. The IOMMU is extremely buggy when a graphics
-card is used. Leaving it off by default will ensure that
-the default ROM images in Libreboot will work on any setup.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- src/mainboard/dell/optiplex_9020/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
-index 8253570f19..7bccc80e51 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
-+++ b/src/mainboard/dell/optiplex_9020/cmos.default
-@@ -2,4 +2,4 @@ boot_option=Fallback
- debug_level=Debug
- nmi=Disable
- power_on_after_fail=Disable
-iommu=Enable
-+iommu=Disable
-- 
-2.39.2
-
@@ -1,774 +0,0 @@
-From 7dd58c8b301404a8bafee25a1e97a8a5d614b3d6 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Mon, 4 Mar 2024 18:05:43 -0700
-Subject: [PATCH] mb/dell: Add Latitude E5420 (Sandy Bridge)
-
---
- src/mainboard/dell/e5420/Kconfig           |  37 ++++
- src/mainboard/dell/e5420/Kconfig.name      |   2 +
- src/mainboard/dell/e5420/Makefile.mk       |   5 +
- src/mainboard/dell/e5420/acpi/ec.asl       |   9 +
- src/mainboard/dell/e5420/acpi/platform.asl |  12 ++
- src/mainboard/dell/e5420/acpi/superio.asl  |   3 +
- src/mainboard/dell/e5420/acpi_tables.c     |  16 ++
- src/mainboard/dell/e5420/board_info.txt    |   6 +
- src/mainboard/dell/e5420/cmos.default      |   9 +
- src/mainboard/dell/e5420/cmos.layout       |  88 ++++++++++
- src/mainboard/dell/e5420/data.vbt          | Bin 0 -> 6144 bytes
- src/mainboard/dell/e5420/devicetree.cb     |  66 +++++++
- src/mainboard/dell/e5420/dsdt.asl          |  30 ++++
- src/mainboard/dell/e5420/early_init.c      |  32 ++++
- src/mainboard/dell/e5420/gma-mainboard.ads |  20 +++
- src/mainboard/dell/e5420/gpio.c            | 195 +++++++++++++++++++++
- src/mainboard/dell/e5420/hda_verb.c        |  33 ++++
- src/mainboard/dell/e5420/mainboard.c       |  21 +++
- 18 files changed, 584 insertions(+)
- create mode 100644 src/mainboard/dell/e5420/Kconfig
- create mode 100644 src/mainboard/dell/e5420/Kconfig.name
- create mode 100644 src/mainboard/dell/e5420/Makefile.mk
- create mode 100644 src/mainboard/dell/e5420/acpi/ec.asl
- create mode 100644 src/mainboard/dell/e5420/acpi/platform.asl
- create mode 100644 src/mainboard/dell/e5420/acpi/superio.asl
- create mode 100644 src/mainboard/dell/e5420/acpi_tables.c
- create mode 100644 src/mainboard/dell/e5420/board_info.txt
- create mode 100644 src/mainboard/dell/e5420/cmos.default
- create mode 100644 src/mainboard/dell/e5420/cmos.layout
- create mode 100755 src/mainboard/dell/e5420/data.vbt
- create mode 100644 src/mainboard/dell/e5420/devicetree.cb
- create mode 100644 src/mainboard/dell/e5420/dsdt.asl
- create mode 100644 src/mainboard/dell/e5420/early_init.c
- create mode 100644 src/mainboard/dell/e5420/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/e5420/gpio.c
- create mode 100644 src/mainboard/dell/e5420/hda_verb.c
- create mode 100644 src/mainboard/dell/e5420/mainboard.c
-
-diff --git a/src/mainboard/dell/e5420/Kconfig b/src/mainboard/dell/e5420/Kconfig
-new file mode 100644
-index 0000000000..f4385045ae
--- /dev/null
-+++ b/src/mainboard/dell/e5420/Kconfig
-@@ -0,0 +1,37 @@
-+if BOARD_DELL_LATITUDE_E5420
-+
-+config BOARD_SPECIFIC_OPTIONS
-+	def_bool y
-+	select BOARD_ROMSIZE_KB_6144
-+	select EC_ACPI
-+	select EC_DELL_MEC5035
-+	select GFX_GMA_PANEL_1_ON_LVDS
-+	select HAVE_ACPI_RESUME
-+	select HAVE_ACPI_TABLES
-+	select HAVE_CMOS_DEFAULT
-+	select HAVE_OPTION_TABLE
-+	select INTEL_GMA_HAVE_VBT
-+	select INTEL_INT15
-+	select MAINBOARD_HAS_LIBGFXINIT
-+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+	select SERIRQ_CONTINUOUS_MODE
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+	select SYSTEM_TYPE_LAPTOP
-+	select USE_NATIVE_RAMINIT
-+
-+config DRAM_RESET_GATE_GPIO
-+	default 60
-+
-+config MAINBOARD_DIR
-+	default "dell/e5420"
-+
-+config MAINBOARD_PART_NUMBER
-+	default "Latitude E5420"
-+
-+config USBDEBUG_HCD_INDEX
-+	default 2
-+
-+config VGA_BIOS_ID
-+	default "8086,0116"
-+
-+endif # BOARD_DELL_LATITUDE_E5420
-diff --git a/src/mainboard/dell/e5420/Kconfig.name b/src/mainboard/dell/e5420/Kconfig.name
-new file mode 100644
-index 0000000000..eb495fb705
--- /dev/null
-+++ b/src/mainboard/dell/e5420/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_DELL_LATITUDE_E5420
-+	bool "Latitude E5420"
-diff --git a/src/mainboard/dell/e5420/Makefile.mk b/src/mainboard/dell/e5420/Makefile.mk
-new file mode 100644
-index 0000000000..18391d8b18
--- /dev/null
-+++ b/src/mainboard/dell/e5420/Makefile.mk
-@@ -0,0 +1,5 @@
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e5420/acpi/ec.asl b/src/mainboard/dell/e5420/acpi/ec.asl
-new file mode 100644
-index 0000000000..0d429410a9
--- /dev/null
-+++ b/src/mainboard/dell/e5420/acpi/ec.asl
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Device(EC)
-+{
-+	Name (_HID, EISAID("PNP0C09"))
-+	Name (_UID, 0)
-+	Name (_GPE, 16)
-+/* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e5420/acpi/platform.asl b/src/mainboard/dell/e5420/acpi/platform.asl
-new file mode 100644
-index 0000000000..2d24bbd9b9
--- /dev/null
-+++ b/src/mainboard/dell/e5420/acpi/platform.asl
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+	/* FIXME: EC support  */
-+	Return(Package() {0, 0})
-+}
-+
-+Method(_PTS,1)
-+{
-+	/* FIXME: EC support  */
-+}
-diff --git a/src/mainboard/dell/e5420/acpi/superio.asl b/src/mainboard/dell/e5420/acpi/superio.asl
-new file mode 100644
-index 0000000000..55b1db5b11
--- /dev/null
-+++ b/src/mainboard/dell/e5420/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <drivers/pc80/pc/ps2_controller.asl>
-diff --git a/src/mainboard/dell/e5420/acpi_tables.c b/src/mainboard/dell/e5420/acpi_tables.c
-new file mode 100644
-index 0000000000..e2759659bf
--- /dev/null
-+++ b/src/mainboard/dell/e5420/acpi_tables.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi_gnvs.h>
-+#include <soc/nvs.h>
-+
-+/* FIXME: check this function.  */
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+	/* The lid is open by default. */
-+	gnvs->lids = 1;
-+
-+	/* Temperature at which OS will shutdown */
-+	gnvs->tcrt = 100;
-+	/* Temperature at which OS will throttle CPU */
-+	gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/dell/e5420/board_info.txt b/src/mainboard/dell/e5420/board_info.txt
-new file mode 100644
-index 0000000000..34d5ad9e0b
--- /dev/null
-+++ b/src/mainboard/dell/e5420/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: laptop
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-+Release year: 2011
-diff --git a/src/mainboard/dell/e5420/cmos.default b/src/mainboard/dell/e5420/cmos.default
-new file mode 100644
-index 0000000000..279415dfd1
--- /dev/null
-+++ b/src/mainboard/dell/e5420/cmos.default
-@@ -0,0 +1,9 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+bluetooth=Enable
-+wwan=Enable
-+wlan=Enable
-+sata_mode=AHCI
-+me_state=Disabled
-diff --git a/src/mainboard/dell/e5420/cmos.layout b/src/mainboard/dell/e5420/cmos.layout
-new file mode 100644
-index 0000000000..1aa7e77bce
--- /dev/null
-+++ b/src/mainboard/dell/e5420/cmos.layout
-@@ -0,0 +1,88 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0	120	r	0	reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384	1	e	4	boot_option
-+388	4	h	0	reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395	4	e	6	debug_level
-+
-+#400	8	r	0	reserved for century byte
-+
-+# coreboot config options: southbridge
-+408	1	e	1	nmi
-+409	2	e	7	power_on_after_fail
-+411     1       e       9       sata_mode
-+
-+# coreboot config options: EC
-+412	1	e	1	bluetooth
-+413	1	e	1	wwan
-+414	1	e	1	wlan
-+
-+# coreboot config options: ME
-+424	1	e	14	me_state
-+425	2	h	0	me_state_prev
-+
-+# coreboot config options: northbridge
-+432	3	e	11	gfx_uma_size
-+435	2	e	12	hybrid_graphics_mode
-+440	8	h	0	volume
-+
-+# VBOOT
-+448	128	r	0	vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896	32	r	0	mrc_scrambler_seed
-+928	32	r	0	mrc_scrambler_seed_s3
-+960	16	r	0	mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984	16	h	0	check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID	value	text
-+1	0	Disable
-+1	1	Enable
-+2	0	Enable
-+2	1	Disable
-+4	0	Fallback
-+4	1	Normal
-+6	0	Emergency
-+6	1	Alert
-+6	2	Critical
-+6	3	Error
-+6	4	Warning
-+6	5	Notice
-+6	6	Info
-+6	7	Debug
-+6	8	Spew
-+7	0	Disable
-+7	1	Enable
-+7	2	Keep
-+9	0	AHCI
-+9	1	Compatible
-+11	0	32M
-+11	1	64M
-+11	2	96M
-+11	3	128M
-+11	4	160M
-+11	5	192M
-+11	6	224M
-+14	0	Normal
-+14	1	Disabled
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 447 984
-diff --git a/src/mainboard/dell/e5420/data.vbt b/src/mainboard/dell/e5420/data.vbt
-new file mode 100755
-index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57
-GIT binary patch
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-
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-HcmV?d00001
-
-diff --git a/src/mainboard/dell/e5420/devicetree.cb b/src/mainboard/dell/e5420/devicetree.cb
-new file mode 100644
-index 0000000000..f26413557d
--- /dev/null
-+++ b/src/mainboard/dell/e5420/devicetree.cb
-@@ -0,0 +1,66 @@
-+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
-+	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
-+	register "gpu_cpu_backlight" = "0x00000c31"
-+	register "gpu_dp_b_hotplug" = "4"
-+	register "gpu_dp_c_hotplug" = "4"
-+	register "gpu_dp_d_hotplug" = "4"
-+	register "gpu_panel_port_select" = "0"
-+	register "gpu_panel_power_backlight_off_delay" = "2300"
-+	register "gpu_panel_power_backlight_on_delay" = "2300"
-+	register "gpu_panel_power_cycle_delay" = "6"
-+	register "gpu_panel_power_down_delay" = "400"
-+	register "gpu_panel_power_up_delay" = "400"
-+	register "gpu_pch_backlight" = "0x13121312"
-+
-+	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
-+
-+	device domain 0x0 on
-+		subsystemid 0x1028 0x049b inherit
-+
-+		device ref host_bridge on end # Host bridge
-+		device ref peg10 on end # PEG
-+		device ref igd on end # iGPU
-+
-+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-+			register "docking_supported" = "1"
-+			register "gen1_dec" = "0x007c0681"
-+			register "gen2_dec" = "0x007c0901"
-+			register "gen3_dec" = "0x003c07e1"
-+			register "gen4_dec" = "0x001c0901"
-+			register "gpi0_routing" = "2"
-+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
-+			register "pcie_port_coalesce" = "1"
-+			register "sata_interface_speed_support" = "0x3"
-+			register "sata_port_map" = "0x3b"
-+			register "spi_lvscc" = "0x2005"
-+			register "spi_uvscc" = "0x2005"
-+
-+			device ref mei1		off end
-+			device ref mei2		off end
-+			device ref me_ide_r	off end
-+			device ref me_kt	off end
-+			device ref gbe		off end
-+			device ref ehci2	on end
-+			device ref hda		on end
-+			device ref pcie_rp1	on end
-+			device ref pcie_rp2	on end
-+			device ref pcie_rp3	on end
-+			device ref pcie_rp4	off end
-+			device ref pcie_rp5	on end
-+			device ref pcie_rp6	on end
-+			device ref pcie_rp7	on end
-+			device ref pcie_rp8	off end
-+			device ref ehci1	on end
-+			device ref pci_bridge	off end
-+			device ref lpc		on
-+				chip ec/dell/mec5035
-+					device pnp ff.0 on end
-+				end
-+			end
-+			device ref sata1 on end
-+			device ref smbus on end
-+			device ref sata2 off end
-+			device ref thermal off end
-+		end
-+	end
-+end
-diff --git a/src/mainboard/dell/e5420/dsdt.asl b/src/mainboard/dell/e5420/dsdt.asl
-new file mode 100644
-index 0000000000..7d13c55b08
--- /dev/null
-+++ b/src/mainboard/dell/e5420/dsdt.asl
-@@ -0,0 +1,30 @@
-+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <acpi/acpi.h>
-+
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	ACPI_DSDT_REV_2,
-+	OEM_ID,
-+	ACPI_TABLE_CREATOR,
-+	0x20141018	/* OEM revision */
-+)
-+{
-+	#include <acpi/dsdt_top.asl>
-+	#include "acpi/platform.asl"
-+	#include <cpu/intel/common/acpi/cpu.asl>
-+	#include <southbridge/intel/common/acpi/platform.asl>
-+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-+	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+
-+	Device (\_SB.PCI0)
-+	{
-+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-+	}
-+}
-diff --git a/src/mainboard/dell/e5420/early_init.c b/src/mainboard/dell/e5420/early_init.c
-new file mode 100644
-index 0000000000..7297921546
--- /dev/null
-+++ b/src/mainboard/dell/e5420/early_init.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+	{ 1, 1, 0 },
-+	{ 1, 1, 0 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 2 },
-+	{ 1, 1, 2 },
-+	{ 1, 1, 3 },
-+	{ 1, 1, 3 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 7 },
-+	{ 1, 1, 6 },
-+	{ 1, 1, 6 },
-+	{ 1, 1, 7 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/e5420/gma-mainboard.ads b/src/mainboard/dell/e5420/gma-mainboard.ads
-new file mode 100644
-index 0000000000..2a16f44360
--- /dev/null
-+++ b/src/mainboard/dell/e5420/gma-mainboard.ads
-@@ -0,0 +1,20 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (
-+      HDMI1, -- mainboard HDMI
-+      DP2, -- dock DP
-+      DP3, -- dock DP
-+      Analog, -- mainboard VGA
-+      LVDS,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/e5420/gpio.c b/src/mainboard/dell/e5420/gpio.c
-new file mode 100644
-index 0000000000..f76b93d9f0
--- /dev/null
-+++ b/src/mainboard/dell/e5420/gpio.c
-@@ -0,0 +1,195 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_NATIVE,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_GPIO,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_NATIVE,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio12 = GPIO_DIR_OUTPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio12 = GPIO_LEVEL_HIGH,
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_GPIO,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_NATIVE,
-+	.gpio50 = GPIO_MODE_GPIO,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_GPIO,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_GPIO,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_OUTPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio46 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio50 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_OUTPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio53 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio55 = GPIO_DIR_OUTPUT,
-+	.gpio56 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_LOW,
-+	.gpio37 = GPIO_LEVEL_LOW,
-+	.gpio46 = GPIO_LEVEL_HIGH,
-+	.gpio50 = GPIO_LEVEL_HIGH,
-+	.gpio51 = GPIO_LEVEL_LOW,
-+	.gpio55 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_NATIVE,
-+	.gpio69 = GPIO_MODE_NATIVE,
-+	.gpio70 = GPIO_MODE_NATIVE,
-+	.gpio71 = GPIO_MODE_NATIVE,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_GPIO,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio74 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/e5420/hda_verb.c b/src/mainboard/dell/e5420/hda_verb.c
-new file mode 100644
-index 0000000000..70e7c2e79a
--- /dev/null
-+++ b/src/mainboard/dell/e5420/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x1028049b,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x1028049b),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0xd5a30130),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/e5420/mainboard.c b/src/mainboard/dell/e5420/mainboard.c
-new file mode 100644
-index 0000000000..31e49802fc
--- /dev/null
-+++ b/src/mainboard/dell/e5420/mainboard.c
-@@ -0,0 +1,21 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/device.h>
-+#include <drivers/intel/gma/int15.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+#include <ec/acpi/ec.h>
-+#include <console/console.h>
-+#include <pc80/keyboard.h>
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+
-+	/* FIXME: fix these values. */
-+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
-+					GMA_INT15_PANEL_FIT_DEFAULT,
-+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+	.enable_dev = mainboard_enable,
-+};
-- 
-2.44.0
-
@@ -1,66 +0,0 @@
-From 4889f08306f1530211dcc6f6a4e999c6cc72f3ac Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Sat, 30 Mar 2024 05:57:54 +0000
-Subject: [PATCH 1/1] fix sata ports on dell 9020 sff and mt
-
-mate kukri has a patch under review on coreboot that sets
-sata port map to 0x7 on sff and 0xf on mt.
-
-see: intel 8 series pch datasheet, section 13.1.35
-
-basically, the 6 least significant bits enable the sata
-slots; 1 for enable and 0 for disable. there can be up
-to 6 ports. least significant bit is port 0, then next
-is port 1, and so on.
-
-coreboot currently enables ports 0, 1, 4 and 5, making this
-value 0x33 (converted to binary: 00110011). sff has ports
-0, 1 and 2 wired, so mate changed that to 0x7 (00000111).
-
-on mt, the blue ports are ports 0 and 1, but the two white
-ports don't work, but coreboot enables 4 and 5; it is
-likely that the blue ports are in fact 0 and 1, and the
-white ports are 2 and 3, but we've not tested this!
-
-it could be that the blue ports are ports 4 and 5, and
-the white ports are 2 and 3! we have not yet determined
-this, but mate set it to 0xf, meaning ports 0 1 2 and 3
-are enabled, in his patch under review. the chance that
-it's 2, 3, 4 and 5 on the board is unlikely, but it is
-theoretically possible and has not been confirmed.
-
-therefore, for now, i will set the value to 0x3f, which
-in binary is 00111111, thus enabling all 6 slots. the two
-that aren't physically wired don't really matter. enabling
-ports (from the pch) that electrically aren't there and
-then powering on is electrically equivalent to those ports
-being actually being wired, but with no devices plugged
-into them. therefore, 0x3f is an effective shotgun fix.
-
-i'll remove this patch and use mate's fix when the latter
-has been tested on MT; it has already been tested on SFF.
-
-this patch fixes the 3rd sata slot on 9020 sff, and the 3rd
-and 4th sata slots on 9020 MT
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- src/mainboard/dell/optiplex_9020/devicetree.cb | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
-index c0b17a15ff..7bfa6736a6 100644
--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
-+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
-@@ -23,7 +23,7 @@ chip northbridge/intel/haswell
- 			register "gen2_dec" = "0x007c0901"
- 			register "gen3_dec" = "0x003c07e1"
- 			register "gen4_dec" = "0x001c0901"
-			register "sata_port_map" = "0x33"
-+			register "sata_port_map" = "0x3f"
- 
- 			device pci 14.0 on  end				# xHCI controller
- 			device pci 16.0 on  end				# Management Engine interface 1
-- 
-2.39.2
-
@@ -1,54 +0,0 @@
-From c6ce9c635e6576c86c546177c3d770dec2f3c9ae Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Fri, 23 Feb 2024 13:33:31 +0000
-Subject: [PATCH 1/1] nb/haswell: Disable iGPU when dGPU is used
-
-This is usually is handled by Haswell mrc.bin, disabling VGA
-decode on the iGPU when a dGPU is installed. However, Broadwell
-mrc.bin does not, so the iGPU and dGPU are both enabled.
-
-This patch disables legacy VGA cycles for iGPU, under such
-conditions. It has been tested on Broadwell mrc.bin when
-using a graphics card on Dell OptiPlex 9020 SFF (currently
-under review at this time of writing, submitted by Mate
-Kukri).
-
-This patch has also been tested when Haswell mrc.bin is used,
-and there are seemingly no breaking changes caused by it.
-
-Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
-Signed-off-by: Leah Rowe <info@minifree.org>
-Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717
-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-Reviewed-by: Nico Huber <nico.h@gmx.de>
---
- src/northbridge/intel/haswell/gma.c | 7 +++++++
- 1 file changed, 7 insertions(+)
-
-diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
-index 6e6948b70f..48a0ba54c7 100644
--- a/src/northbridge/intel/haswell/gma.c
-+++ b/src/northbridge/intel/haswell/gma.c
-@@ -461,12 +461,19 @@ static void gma_generate_ssdt(const struct device *dev)
- 	drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
- }
- 
-+static void gma_func0_disable(struct device *dev)
-+{
-+	/* Disable VGA decode */
-+	pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
-+}
-+
- static struct device_operations gma_func0_ops = {
- 	.read_resources		= pci_dev_read_resources,
- 	.set_resources		= pci_dev_set_resources,
- 	.enable_resources	= pci_dev_enable_resources,
- 	.init			= gma_func0_init,
- 	.acpi_fill_ssdt		= gma_generate_ssdt,
-+	.vga_disable            = gma_func0_disable,
- 	.ops_pci		= &pci_dev_ops_pci,
- };
- 
-- 
-2.39.2
-
@@ -1,51 +0,0 @@
-From 0801b3ba8a0ce0109e30d27f405c912d5d705e9c Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Sat, 6 Apr 2024 01:22:47 +0100
-Subject: [PATCH 1/1] nb/haswell: Fully disable iGPU when dGPU is used
-
-My earlier patch disabled decode *and* disabled the iGPU itself, but
-a subsequent revision disabled only VGA decode. Upon revisiting, I
-found that, actually, yes, you also need to disable the iGPU entirely.
-
-Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU.
-With this patch, the iGPU is completely disabled when you install a
-graphics card, but the iGPU is available to use when no graphics card
-is present.
-
-For more context, see:
-
-Author: Leah Rowe <info@minifree.org>
-Date:   Fri Feb 23 13:33:31 2024 +0000
-
-    nb/haswell: Disable iGPU when dGPU is used
-
-And look at the Gerrit comments:
-
-https://review.coreboot.org/c/coreboot/+/80717/
-
-So, my original submission on change 80717 was actually correct.
-This patch fixes the issue. I tested on iGPU and dGPU, with both
-broadwell and haswell mrc.bin.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- src/northbridge/intel/haswell/gma.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
-index 48a0ba54c7..f0b848852d 100644
--- a/src/northbridge/intel/haswell/gma.c
-+++ b/src/northbridge/intel/haswell/gma.c
-@@ -465,6 +465,9 @@ static void gma_func0_disable(struct device *dev)
- {
- 	/* Disable VGA decode */
- 	pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
-+
-+	/* Required or else the graphics card doesn't work */
-+	dev->enabled = 0;
- }
- 
- static struct device_operations gma_func0_ops = {
-- 
-2.39.2
-
@@ -1,602 +0,0 @@
-From c58e0fea2a4e591e5ecd8a1f376c3b3af0fbb306 Mon Sep 17 00:00:00 2001
-From: Mate Kukri <kukri.mate@gmail.com>
-Date: Thu, 18 Apr 2024 20:28:45 +0100
-Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization
-
-There are 4 different chassis types specified by vendor firmware, each
-with a slightly different HWM configuration.
-
-The chassis type to use is determined at runtime by reading a set of
-4 PCH GPIOs: 70, 38, 17, and 1.
-
-Additionally vendor firmware also provides an option to run the fans at
-full speed. This is substituted with a coreboot nvram option in this
-implementation.
-
-This was tested to make fan control work on my OptiPlex 7020 SFF.
-
-NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
-however the OptiPlex 9020's SCH5555 does not use externally
-programmed EC firmware.
-
-Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
-Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
---
- src/mainboard/dell/optiplex_9020/Makefile.inc |   3 +-
- src/mainboard/dell/optiplex_9020/bootblock.c  |  25 +-
- src/mainboard/dell/optiplex_9020/cmos.default |   1 +
- src/mainboard/dell/optiplex_9020/cmos.layout  |   5 +-
- src/mainboard/dell/optiplex_9020/mainboard.c  | 387 ++++++++++++++++++
- src/mainboard/dell/optiplex_9020/sch5555_ec.c |  54 +++
- src/mainboard/dell/optiplex_9020/sch5555_ec.h |  10 +
- 7 files changed, 463 insertions(+), 22 deletions(-)
- create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c
- create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h
-
-diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc
-index 6ca2f2afaa..08e2e53577 100644
--- a/src/mainboard/dell/optiplex_9020/Makefile.inc
-+++ b/src/mainboard/dell/optiplex_9020/Makefile.inc
-@@ -2,4 +2,5 @@
- 
- romstage-y += gpio.c
- ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-bootblock-y += bootblock.c
-+ramstage-y += sch5555_ec.c
-+bootblock-y += bootblock.c sch5555_ec.c
-diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
-index 2837cf9cf1..e5e759273e 100644
--- a/src/mainboard/dell/optiplex_9020/bootblock.c
-+++ b/src/mainboard/dell/optiplex_9020/bootblock.c
-@@ -4,29 +4,14 @@
- #include <device/pnp_ops.h>
- #include <superio/smsc/sch555x/sch555x.h>
- #include <southbridge/intel/lynxpoint/pch.h>
-
-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
-{
-	// Clear EC-to-Host mailbox
-	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
-	outb(tmp, SCH555x_EMI_IOBASE + 1);
-
-	// Send address and value to the EC
-	sch555x_emi_write16(0, (addr1 * 2) | 0x101);
-	sch555x_emi_write32(4, val | (addr2 << 16));
-
-	// Wait for acknowledgement message from EC
-	outb(1, SCH555x_EMI_IOBASE);
-	size_t timeout = 0;
-	do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
-}
-+#include "sch5555_ec.h"
- 
- struct ec_init_entry {
- 	uint16_t addr;
- 	uint8_t val;
- };
- 
-static void ec_init(void)
-+static void bootblock_ec_init(void)
- {
- 	/*
- 	 * Tables from CORE_PEI
-@@ -108,9 +93,9 @@ void mainboard_config_superio(void)
- 	outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
- 	outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
- 
-	// Magic EC init
-	ec_init();
-+	// Perform bootblock EC initialization
-+	bootblock_ec_init();
- 
-	// Magic EC init is needed for UART1 initialization to work
-+	// Bootblock EC initialization is required for UART1 to work
- 	sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- }
-diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
-index 7bccc80e51..1909abcb9f 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.default
-+++ b/src/mainboard/dell/optiplex_9020/cmos.default
-@@ -3,3 +3,4 @@ debug_level=Debug
- nmi=Disable
- power_on_after_fail=Disable
- iommu=Disable
-+fan_full_speed=Disable
-diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
-index 72ff9c4bee..4a1496a878 100644
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
-+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
-@@ -22,7 +22,10 @@ entries
- 409	2	e	5	power_on_after_fail
- 
- # turn iommu on or off
-412	1	e	6	iommu
-+411	1	e	6	iommu
-+
-+# coreboot config options: EC
-+412	1	e	1	fan_full_speed
- 
- # coreboot config options: check sums
- 984	16	h	0	check_sum
-diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
-index c834fea5d3..0b7829c736 100644
--- a/src/mainboard/dell/optiplex_9020/mainboard.c
-+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
-@@ -1,7 +1,12 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
- 
-+#include <bootstate.h>
-+#include <cpu/x86/msr.h>
- #include <device/device.h>
- #include <drivers/intel/gma/int15.h>
-+#include <option.h>
-+#include <southbridge/intel/common/gpio.h>
-+#include "sch5555_ec.h"
- 
- static void mainboard_enable(struct device *dev)
- {
-@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev)
- struct chip_operations mainboard_ops = {
- 	.enable_dev = mainboard_enable,
- };
-+
-+#define HWM_TAB_ADD_TEMP_TARGET	1
-+#define HWM_TAB_PKG_POWER_ANY	0xffff
-+#define CHASSIS_TYPE_UNKNOWN	0xff
-+
-+struct hwm_tab_entry {
-+	uint16_t addr;
-+	uint8_t val;
-+	uint8_t flags;
-+	uint16_t pkg_power;
-+};
-+
-+struct hwm_tab_entry HWM_TAB3[] = {
-+	{ 0x005, 0x33, 0, 0xffff },
-+	{ 0x018, 0x2f, 0, 0xffff },
-+	{ 0x019, 0x2f, 0, 0xffff },
-+	{ 0x01a, 0x2f, 0, 0xffff },
-+	{ 0x080, 0x00, 0, 0xffff },
-+	{ 0x081, 0x00, 0, 0xffff },
-+	{ 0x083, 0xbb, 0, 0xffff },
-+	{ 0x085, 0x8a, 0, 0x0010 },
-+	{ 0x086, 0x4c, 0, 0x0010 },
-+	{ 0x08a, 0x66, 0, 0x0010 },
-+	{ 0x08b, 0x5b, 0, 0x0010 },
-+	{ 0x090, 0x65, 0, 0xffff },
-+	{ 0x091, 0x70, 0, 0xffff },
-+	{ 0x092, 0x86, 0, 0xffff },
-+	{ 0x096, 0xa4, 0, 0xffff },
-+	{ 0x097, 0xa4, 0, 0xffff },
-+	{ 0x098, 0xa4, 0, 0xffff },
-+	{ 0x09b, 0xa4, 0, 0xffff },
-+	{ 0x0a0, 0x0e, 0, 0xffff },
-+	{ 0x0a1, 0x0e, 0, 0xffff },
-+	{ 0x0ae, 0x7c, 0, 0xffff },
-+	{ 0x0af, 0x86, 0, 0xffff },
-+	{ 0x0b0, 0x9a, 0, 0xffff },
-+	{ 0x0b3, 0x9a, 0, 0xffff },
-+	{ 0x0b6, 0x08, 0, 0xffff },
-+	{ 0x0b7, 0x08, 0, 0xffff },
-+	{ 0x0ea, 0x64, 0, 0x0020 },
-+	{ 0x0ea, 0x5c, 0, 0x0010 },
-+	{ 0x0ef, 0xff, 0, 0xffff },
-+	{ 0x0f8, 0x15, 0, 0xffff },
-+	{ 0x0f9, 0x00, 0, 0xffff },
-+	{ 0x0f0, 0x30, 0, 0xffff },
-+	{ 0x0fd, 0x01, 0, 0xffff },
-+	{ 0x1a1, 0x00, 0, 0xffff },
-+	{ 0x1a2, 0x00, 0, 0xffff },
-+	{ 0x1b1, 0x08, 0, 0xffff },
-+	{ 0x1be, 0x99, 0, 0xffff },
-+	{ 0x280, 0xa0, 0, 0x0010 },
-+	{ 0x281, 0x0f, 0, 0x0010 },
-+	{ 0x282, 0x03, 0, 0xffff },
-+	{ 0x283, 0x0a, 0, 0xffff },
-+	{ 0x284, 0x80, 0, 0xffff },
-+	{ 0x285, 0x03, 0, 0xffff },
-+	{ 0x288, 0x68, 0, 0x0010 },
-+	{ 0x289, 0x10, 0, 0x0010 },
-+	{ 0x28a, 0x03, 0, 0xffff },
-+	{ 0x28b, 0x0a, 0, 0xffff },
-+	{ 0x28c, 0x80, 0, 0xffff },
-+	{ 0x28d, 0x03, 0, 0xffff },
-+};
-+
-+struct hwm_tab_entry HWM_TAB4[] = {
-+	{ 0x005, 0x33, 0, 0xffff },
-+	{ 0x018, 0x2f, 0, 0xffff },
-+	{ 0x019, 0x2f, 0, 0xffff },
-+	{ 0x01a, 0x2f, 0, 0xffff },
-+	{ 0x080, 0x00, 0, 0xffff },
-+	{ 0x081, 0x00, 0, 0xffff },
-+	{ 0x083, 0xbb, 0, 0xffff },
-+	{ 0x085, 0x99, 0, 0x0020 },
-+	{ 0x085, 0xad, 0, 0x0010 },
-+	{ 0x086, 0x1c, 0, 0xffff },
-+	{ 0x08a, 0x39, 0, 0x0020 },
-+	{ 0x08a, 0x41, 0, 0x0010 },
-+	{ 0x08b, 0x76, 0, 0x0020 },
-+	{ 0x08b, 0x8b, 0, 0x0010 },
-+	{ 0x090, 0x5e, 0, 0xffff },
-+	{ 0x091, 0x5e, 0, 0xffff },
-+	{ 0x092, 0x86, 0, 0xffff },
-+	{ 0x096, 0xa4, 0, 0xffff },
-+	{ 0x097, 0xa4, 0, 0xffff },
-+	{ 0x098, 0xa4, 0, 0xffff },
-+	{ 0x09b, 0xa4, 0, 0xffff },
-+	{ 0x0a0, 0x0a, 0, 0xffff },
-+	{ 0x0a1, 0x0a, 0, 0xffff },
-+	{ 0x0ae, 0x7c, 0, 0xffff },
-+	{ 0x0af, 0x7c, 0, 0xffff },
-+	{ 0x0b0, 0x9a, 0, 0xffff },
-+	{ 0x0b3, 0x7c, 0, 0xffff },
-+	{ 0x0b6, 0x08, 0, 0xffff },
-+	{ 0x0b7, 0x08, 0, 0xffff },
-+	{ 0x0ea, 0x64, 0, 0x0020 },
-+	{ 0x0ea, 0x5c, 0, 0x0010 },
-+	{ 0x0ef, 0xff, 0, 0xffff },
-+	{ 0x0f8, 0x15, 0, 0xffff },
-+	{ 0x0f9, 0x00, 0, 0xffff },
-+	{ 0x0f0, 0x30, 0, 0xffff },
-+	{ 0x0fd, 0x01, 0, 0xffff },
-+	{ 0x1a1, 0x00, 0, 0xffff },
-+	{ 0x1a2, 0x00, 0, 0xffff },
-+	{ 0x1b1, 0x08, 0, 0xffff },
-+	{ 0x1be, 0x90, 0, 0xffff },
-+	{ 0x280, 0x94, 0, 0x0020 },
-+	{ 0x281, 0x11, 0, 0x0020 },
-+	{ 0x280, 0x94, 0, 0x0010 },
-+	{ 0x281, 0x11, 0, 0x0010 },
-+	{ 0x282, 0x03, 0, 0xffff },
-+	{ 0x283, 0x0a, 0, 0xffff },
-+	{ 0x284, 0x80, 0, 0xffff },
-+	{ 0x285, 0x03, 0, 0xffff },
-+	{ 0x288, 0x28, 0, 0x0020 },
-+	{ 0x289, 0x0a, 0, 0x0020 },
-+	{ 0x288, 0x28, 0, 0x0010 },
-+	{ 0x289, 0x0a, 0, 0x0010 },
-+	{ 0x28a, 0x03, 0, 0xffff },
-+	{ 0x28b, 0x0a, 0, 0xffff },
-+	{ 0x28c, 0x80, 0, 0xffff },
-+	{ 0x28d, 0x03, 0, 0xffff },
-+};
-+
-+struct hwm_tab_entry HWM_TAB5[] = {
-+	{ 0x005, 0x33, 0, 0xffff },
-+	{ 0x018, 0x2f, 0, 0xffff },
-+	{ 0x019, 0x2f, 0, 0xffff },
-+	{ 0x01a, 0x2f, 0, 0xffff },
-+	{ 0x080, 0x00, 0, 0xffff },
-+	{ 0x081, 0x00, 0, 0xffff },
-+	{ 0x083, 0xbb, 0, 0xffff },
-+	{ 0x085, 0x66, 0, 0x0020 },
-+	{ 0x085, 0x5d, 0, 0x0010 },
-+	{ 0x086, 0x1c, 0, 0xffff },
-+	{ 0x08a, 0x39, 0, 0x0020 },
-+	{ 0x08a, 0x41, 0, 0x0010 },
-+	{ 0x08b, 0x76, 0, 0x0020 },
-+	{ 0x08b, 0x80, 0, 0x0010 },
-+	{ 0x090, 0x5d, 0, 0x0020 },
-+	{ 0x090, 0x5e, 0, 0x0010 },
-+	{ 0x091, 0x5e, 0, 0xffff },
-+	{ 0x092, 0x86, 0, 0xffff },
-+	{ 0x096, 0xa4, 0, 0xffff },
-+	{ 0x097, 0xa4, 0, 0xffff },
-+	{ 0x098, 0xa3, 0, 0x0020 },
-+	{ 0x098, 0xa4, 0, 0x0010 },
-+	{ 0x09b, 0xa4, 0, 0xffff },
-+	{ 0x0a0, 0x08, 0, 0xffff },
-+	{ 0x0a1, 0x0a, 0, 0xffff },
-+	{ 0x0ae, 0x7c, 0, 0xffff },
-+	{ 0x0af, 0x7c, 0, 0xffff },
-+	{ 0x0b0, 0x9a, 0, 0xffff },
-+	{ 0x0b3, 0x7c, 0, 0xffff },
-+	{ 0x0b6, 0x08, 0, 0xffff },
-+	{ 0x0b7, 0x08, 0, 0xffff },
-+	{ 0x0ea, 0x64, 0, 0x0020 },
-+	{ 0x0ea, 0x5c, 0, 0x0010 },
-+	{ 0x0ef, 0xff, 0, 0xffff },
-+	{ 0x0f8, 0x15, 0, 0xffff },
-+	{ 0x0f9, 0x00, 0, 0xffff },
-+	{ 0x0f0, 0x30, 0, 0xffff },
-+	{ 0x0fd, 0x01, 0, 0xffff },
-+	{ 0x1a1, 0x00, 0, 0xffff },
-+	{ 0x1a2, 0x00, 0, 0xffff },
-+	{ 0x1b1, 0x08, 0, 0xffff },
-+	{ 0x1be, 0x98, 0, 0x0020 },
-+	{ 0x1be, 0x90, 0, 0x0010 },
-+	{ 0x280, 0x94, 0, 0x0020 },
-+	{ 0x281, 0x11, 0, 0x0020 },
-+	{ 0x280, 0x94, 0, 0x0010 },
-+	{ 0x281, 0x11, 0, 0x0010 },
-+	{ 0x282, 0x03, 0, 0xffff },
-+	{ 0x283, 0x0a, 0, 0xffff },
-+	{ 0x284, 0x80, 0, 0xffff },
-+	{ 0x285, 0x03, 0, 0xffff },
-+	{ 0x288, 0x28, 0, 0x0020 },
-+	{ 0x289, 0x0a, 0, 0x0020 },
-+	{ 0x288, 0x28, 0, 0x0010 },
-+	{ 0x289, 0x0a, 0, 0x0010 },
-+	{ 0x28a, 0x03, 0, 0xffff },
-+	{ 0x28b, 0x0a, 0, 0xffff },
-+	{ 0x28c, 0x80, 0, 0xffff },
-+	{ 0x28d, 0x03, 0, 0xffff },
-+};
-+
-+struct hwm_tab_entry HWM_TAB6[] = {
-+	{ 0x005, 0x33, 0, 0xffff },
-+	{ 0x018, 0x2f, 0, 0xffff },
-+	{ 0x019, 0x2f, 0, 0xffff },
-+	{ 0x01a, 0x2f, 0, 0xffff },
-+	{ 0x080, 0x00, 0, 0xffff },
-+	{ 0x081, 0x00, 0, 0xffff },
-+	{ 0x083, 0xbb, 0, 0xffff },
-+	{ 0x085, 0x98, 0, 0xffff },
-+	{ 0x086, 0x3c, 0, 0xffff },
-+	{ 0x08a, 0x39, 0, 0x0020 },
-+	{ 0x08a, 0x3d, 0, 0x0010 },
-+	{ 0x08b, 0x44, 0, 0x0020 },
-+	{ 0x08b, 0x51, 0, 0x0010 },
-+	{ 0x090, 0x61, 0, 0xffff },
-+	{ 0x091, 0x6d, 0, 0xffff },
-+	{ 0x092, 0x86, 0, 0xffff },
-+	{ 0x096, 0xa4, 0, 0xffff },
-+	{ 0x097, 0xa4, 0, 0xffff },
-+	{ 0x098, 0x9f, 0, 0x0020 },
-+	{ 0x098, 0xa4, 0, 0x0010 },
-+	{ 0x09b, 0xa4, 0, 0xffff },
-+	{ 0x0a0, 0x0e, 0, 0xffff },
-+	{ 0x0a1, 0x0e, 0, 0xffff },
-+	{ 0x0ae, 0x7c, 0, 0xffff },
-+	{ 0x0af, 0x7c, 0, 0xffff },
-+	{ 0x0b0, 0x9b, 0, 0x0020 },
-+	{ 0x0b0, 0x98, 0, 0x0010 },
-+	{ 0x0b3, 0x9a, 0, 0xffff },
-+	{ 0x0b6, 0x08, 0, 0xffff },
-+	{ 0x0b7, 0x08, 0, 0xffff },
-+	{ 0x0ea, 0x64, 0, 0x0020 },
-+	{ 0x0ea, 0x5c, 0, 0x0010 },
-+	{ 0x0ef, 0xff, 0, 0xffff },
-+	{ 0x0f8, 0x15, 0, 0xffff },
-+	{ 0x0f9, 0x00, 0, 0xffff },
-+	{ 0x0f0, 0x30, 0, 0xffff },
-+	{ 0x0fd, 0x01, 0, 0xffff },
-+	{ 0x1a1, 0x00, 0, 0xffff },
-+	{ 0x1a2, 0x00, 0, 0xffff },
-+	{ 0x1b1, 0x08, 0, 0xffff },
-+	{ 0x1be, 0x9a, 0, 0x0020 },
-+	{ 0x1be, 0x96, 0, 0x0010 },
-+	{ 0x280, 0x94, 0, 0x0020 },
-+	{ 0x281, 0x11, 0, 0x0020 },
-+	{ 0x280, 0x94, 0, 0x0010 },
-+	{ 0x281, 0x11, 0, 0x0010 },
-+	{ 0x282, 0x03, 0, 0xffff },
-+	{ 0x283, 0x0a, 0, 0xffff },
-+	{ 0x284, 0x80, 0, 0xffff },
-+	{ 0x285, 0x03, 0, 0xffff },
-+	{ 0x288, 0x94, 0, 0x0020 },
-+	{ 0x289, 0x11, 0, 0x0020 },
-+	{ 0x288, 0x94, 0, 0x0010 },
-+	{ 0x289, 0x11, 0, 0x0010 },
-+	{ 0x28a, 0x03, 0, 0xffff },
-+	{ 0x28b, 0x0a, 0, 0xffff },
-+	{ 0x28c, 0x80, 0, 0xffff },
-+	{ 0x28d, 0x03, 0, 0xffff },
-+};
-+
-+static uint8_t get_chassis_type(void)
-+{
-+	uint8_t gpio_chassis_type;
-+
-+	// Read chassis type from GPIO
-+	gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
-+			    get_gpio(17) << 1 | get_gpio(1);
-+
-+	printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
-+
-+	// Turn it into internal chassis index
-+	switch (gpio_chassis_type) {
-+	case 0x08:
-+	case 0x0a:
-+		return 4;
-+	case 0x0b:
-+		return 3;
-+	case 0x0c:
-+		return 5;
-+	case 0x0d: // SFF
-+	case 0x0e:
-+	case 0x0f:
-+		return 6;
-+	default:
-+		return CHASSIS_TYPE_UNKNOWN;
-+	}
-+
-+}
-+
-+static uint8_t get_temp_target(void)
-+{
-+	uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff;
-+	if (!val)
-+		val = 20;
-+	return 0x95 - val;
-+}
-+
-+static uint16_t get_pkg_power(void)
-+{
-+	uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf;
-+	if (rapl_power_unit)
-+		rapl_power_unit = 2 << (rapl_power_unit - 1);
-+	uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff;
-+	if (pkg_power_info / rapl_power_unit > 0x41)
-+		return 32;
-+	else
-+		return 16;
-+}
-+
-+static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size)
-+{
-+	uint8_t temp_target = get_temp_target();
-+	uint16_t pkg_power = get_pkg_power();
-+
-+	printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target);
-+	printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power);
-+
-+	for (size_t i = 0; i < size; ++i) {
-+		// Skip entry if it doesn't apply for this package power
-+		if (arr[i].pkg_power != pkg_power &&
-+		    arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY)
-+			continue;
-+
-+		uint8_t val = arr[i].val;
-+
-+		// Add temp target to value if requested (current tables never do)
-+		if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET)
-+			val += temp_target;
-+
-+		// Perform write
-+		ec_write(1, arr[i].addr, val);
-+
-+	}
-+}
-+
-+static void sch5555_ec_hwm_init(void *arg)
-+{
-+	uint8_t chassis_type, saved_2fc;
-+
-+	printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n");
-+
-+	saved_2fc = ec_read(1, 0x2fc);
-+	ec_write(1, 0x2fc, 0xa0);
-+	ec_write(1, 0x2fd, 0x32);
-+
-+	chassis_type = get_chassis_type();
-+
-+	if (chassis_type != CHASSIS_TYPE_UNKNOWN) {
-+		printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type);
-+	} else {
-+		printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n");
-+	}
-+
-+	// Apply HWM table based on chassis type
-+	switch (chassis_type) {
-+	case 3:
-+		apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3));
-+		break;
-+	case 4:
-+		apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4));
-+		break;
-+	case 5:
-+		apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5));
-+		break;
-+	case 6:
-+		apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6));
-+		break;
-+	}
-+
-+	// NOTE: vendor firmware applies these when "max core address" > 2
-+	// i think this is always the case
-+	ec_write(1, 0x9e, 0x30);
-+	ec_write(1, 0xeb, ec_read(1, 0xea));
-+
-+	ec_write(1, 0x2fc, saved_2fc);
-+
-+	// Apply full speed fan config if requested or if the chassis type is unknown
-+	if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) {
-+		printk(BIOS_DEBUG, "Setting full fan speed\n");
-+		ec_write(1, 0x80, 0x60 | ec_read(1, 0x80));
-+		ec_write(1, 0x81, 0x60 | ec_read(1, 0x81));
-+	}
-+
-+	ec_read(1, 0xb8);
-+
-+	if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) {
-+		ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb);
-+		ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb);
-+		ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb);
-+		ec_write(1, 0x8a, 0x99);
-+		ec_write(1, 0x8b, 0x47);
-+		ec_write(1, 0x8c, 0x91);
-+	}
-+}
-+
-+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL);
-diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
-new file mode 100644
-index 0000000000..a1067ac063
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
-@@ -0,0 +1,54 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <arch/io.h>
-+#include <device/pnp_ops.h>
-+#include <superio/smsc/sch555x/sch555x.h>
-+#include "sch5555_ec.h"
-+
-+uint8_t ec_read(uint8_t addr1, uint16_t addr2)
-+{
-+	// clear ec-to-host mailbox
-+	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
-+	outb(tmp, SCH555x_EMI_IOBASE + 1);
-+
-+	// send address
-+	outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
-+	outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4);
-+
-+	outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
-+	outl(addr2 << 16, SCH555x_EMI_IOBASE + 4);
-+
-+	// send message to ec
-+	outb(1, SCH555x_EMI_IOBASE);
-+
-+	// wait for ack
-+	for (size_t retry = 0; retry < 0xfff; ++retry)
-+		if (inb(SCH555x_EMI_IOBASE + 1) & 1)
-+			break;
-+
-+	// read result
-+	outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2);
-+	return inb(SCH555x_EMI_IOBASE + 4);
-+}
-+
-+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
-+{
-+	// clear ec-to-host mailbox
-+	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
-+	outb(tmp, SCH555x_EMI_IOBASE + 1);
-+
-+	// send address and value
-+	outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
-+	outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4);
-+
-+	outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
-+	outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4);
-+
-+	// send message to ec
-+	outb(1, SCH555x_EMI_IOBASE);
-+
-+	// wait for ack
-+	for (size_t retry = 0; retry < 0xfff; ++retry)
-+		if (inb(SCH555x_EMI_IOBASE + 1) & 1)
-+			break;
-+}
-diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
-new file mode 100644
-index 0000000000..7e399e8e74
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
-@@ -0,0 +1,10 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#ifndef __SCH5555_EC_H__
-+#define __SCH5555_EC_H__
-+
-+uint8_t ec_read(uint8_t addr1, uint16_t addr2);
-+
-+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val);
-+
-+#endif
-- 
-2.39.2
-
@@ -1,49 +0,0 @@
-From cd3c553a313a26494e5dc31ff8323c3a919f190a Mon Sep 17 00:00:00 2001
-From: Mate Kukri <kukri.mate@gmail.com>
-Date: Wed, 10 Apr 2024 20:31:35 +0100
-Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device
-
-These machines come with a TPM1.2 device by default. It is somewhat
-obsolete these days, but there is no harm in enabling it.
-
-Change-Id: Iec05321862aed58695c256b00494e5953219786d
-Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
-Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827
-Reviewed-by: Angel Pons <th3fanbus@gmail.com>
-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
- src/mainboard/dell/optiplex_9020/Kconfig       | 2 ++
- src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++
- 2 files changed, 5 insertions(+)
-
-diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
-index 774a72f161..296938aa8d 100644
--- a/src/mainboard/dell/optiplex_9020/Kconfig
-+++ b/src/mainboard/dell/optiplex_9020/Kconfig
-@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS
- 	select INTEL_GMA_HAVE_VBT
- 	select INTEL_INT15
- 	select MAINBOARD_HAS_LIBGFXINIT
-+	select MAINBOARD_HAS_TPM1
- 	select MAINBOARD_USES_IFD_GBE_REGION
-+	select MEMORY_MAPPED_TPM
- 	select NORTHBRIDGE_INTEL_HASWELL
- 	select SERIRQ_CONTINUOUS_MODE
- 	select SOUTHBRIDGE_INTEL_LYNXPOINT
-diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
-index 7bfa6736a6..e5cbd64127 100644
--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
-+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
-@@ -70,6 +70,9 @@ chip northbridge/intel/haswell
- 					device pnp 2e.b  off end	# Floppy Controller
- 					device pnp 2e.11 off end	# Parallel Port
- 				end
-+				chip drivers/pc80/tpm
-+					device pnp 0c31.0 on end
-+				end
- 			end
- 			device pci 1f.2 on  end				# SATA controller 1
- 			device pci 1f.3 on  end				# SMBus
-- 
-2.39.2
-
@@ -1,47 +0,0 @@
-From 4ccef4fffd98071c339cb4135e2d8c805e554378 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Fri, 3 May 2024 17:45:52 +0100
-Subject: [PATCH 1/1] hp/8560w: turn on wifi
-
-according to angel pons, this gpio is WLAN_TRN_OFF#
-and setting it high will make wifi work. testing with
-this change as suggested by angel. see:
-
-https://review.coreboot.org/c/coreboot/+/39398/4/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c#158
-
-if it makes it into a libreboot release, you can assume
-the fix works. right now we have this problem:
-
-https://codeberg.org/libreboot/lbmk/issues/201
-
-Riku reported:
-
-[  333.890080] atkbd serio0: Unknown key pressed (translated set 2, code 0xf8 on isa0060/serio0).
-[  333.890102] atkbd serio0: Use 'setkeycodes e078 <keycode>' to make it known.
-[  334.104069] atkbd serio0: Unknown key released (translated set 2, code 0xf8 on isa0060/serio0).
-[  334.104090] atkbd serio0: Use 'setkeycodes e078 <keycode>' to make it known.
-
-The wifi stays to hardblocked in rfkill. When the wireless button
-is pressed, nothing changes except for these lines in dmesg.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
-index 560d668d6f..10cd11ce48 100644
--- a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
-+++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
-@@ -155,7 +155,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = {
- 	.gpio37 = GPIO_LEVEL_LOW,
- 	.gpio49 = GPIO_LEVEL_LOW,
- 	.gpio53 = GPIO_LEVEL_HIGH,
-	.gpio57 = GPIO_LEVEL_LOW,
-+	.gpio57 = GPIO_LEVEL_HIGH,
- 	.gpio60 = GPIO_LEVEL_HIGH,
- 	.gpio61 = GPIO_LEVEL_HIGH,
- };
-- 
-2.39.2
-
@@ -1,117 +0,0 @@
-From a8c4f7004ea1c9b8268a87dd0b700c250ec4747d Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 3 May 2024 11:03:32 -0600
-Subject: [PATCH] ec/dell/mec5035: Add S3 suspend SMI handler
-
-Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/ec/dell/mec5035/Makefile.mk  |  1 +
- src/ec/dell/mec5035/mec5035.c    | 14 ++++++++++++++
- src/ec/dell/mec5035/mec5035.h    | 19 +++++++++++++++++++
- src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++
- 4 files changed, 51 insertions(+)
- create mode 100644 src/ec/dell/mec5035/smihandler.c
-
-diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk
-index 4ebdd811f9..be557e4599 100644
--- a/src/ec/dell/mec5035/Makefile.mk
-+++ b/src/ec/dell/mec5035/Makefile.mk
-@@ -5,5 +5,6 @@ ifeq ($(CONFIG_EC_DELL_MEC5035),y)
- bootblock-y += mec5035.c
- romstage-y += mec5035.c
- ramstage-y += mec5035.c
-+smm-y += mec5035.c smihandler.c
- 
- endif
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 68b6b2f7fb..33bf046634 100644
--- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
- 	ec_command(CMD_RADIO_CTRL);
- }
- 
-+void mec5035_sleep_enable(void)
-+{
-+	u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
-+	write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
-+	ec_command(CMD_SLEEP_ENABLE);
-+}
-+
-+void mec5035_change_wake(u8 source, enum ec_wake_change change)
-+{
-+	u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
-+	write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS);
-+	ec_command(CMD_ACPI_WAKEUP_CHANGE);
-+}
-+
- void mec5035_early_init(void)
- {
- 	/* If this isn't sent the EC shuts down the system after about 15
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index fa15a9d621..069616fbc5 100644
--- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -4,6 +4,7 @@
- #define _EC_DELL_MEC5035_H_
- 
- #include <stdint.h>
-+#include <types.h>
- 
- #define NUM_REGISTERS	32
- 
-@@ -29,9 +30,27 @@ enum ec_radio_state {
- 	RADIO_ON
- };
- 
-+#define CMD_ACPI_WAKEUP_CHANGE 0x4a
-+#define ACPI_WAKEUP_NUM_ARGS 4
-+enum ec_wake_change {
-+	WAKE_OFF = 0,
-+	WAKE_ON
-+};
-+enum ec_acpi_wake_events {
-+	EC_ACPI_WAKE_PWRB = BIT(0),     /* Wake up by power button */
-+	EC_ACPI_WAKE_LID = BIT(1),      /* Wake up by lid switch */
-+	EC_ACPI_WAKE_RTC = BIT(5),      /* Wake up by RTC */
-+};
-+
-+#define CMD_SLEEP_ENABLE 0x64
-+#define SLEEP_EN_NUM_ARGS 2
-+
- u8 mec5035_mouse_touchpad(u8 setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
- void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
-+void mec5035_sleep(int slp_type);
-+void mec5035_change_wake(u8 source, enum ec_wake_change change);
-+void mec5035_sleep_enable(void);
- 
- #endif /* _EC_DELL_MEC5035_H_ */
-diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c
-new file mode 100644
-index 0000000000..1db834773d
--- /dev/null
-+++ b/src/ec/dell/mec5035/smihandler.c
-@@ -0,0 +1,17 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi.h>
-+#include <console/console.h>
-+#include <ec/acpi/ec.h>
-+#include "mec5035.h"
-+
-+void mec5035_sleep(int slp_type)
-+{
-+	switch (slp_type) {
-+	case ACPI_S3:
-+		/* System does not yet resume properly if woken by lid */
-+		mec5035_change_wake(EC_ACPI_WAKE_LID, WAKE_OFF);
-+		mec5035_sleep_enable();
-+		break;
-+	}
-+}
-- 
-2.44.0
-
@@ -1,133 +0,0 @@
-From 9ff35368733c5e5a852ebd6295f262710553913b Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 3 May 2024 16:31:12 -0600
-Subject: [PATCH] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes
-
-This should fix S3 suspend on these systems
-
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/e5420/smihandler.c | 9 +++++++++
- src/mainboard/dell/e5520/smihandler.c | 9 +++++++++
- src/mainboard/dell/e5530/smihandler.c | 9 +++++++++
- src/mainboard/dell/e6420/smihandler.c | 9 +++++++++
- src/mainboard/dell/e6430/smihandler.c | 9 +++++++++
- src/mainboard/dell/e6520/smihandler.c | 9 +++++++++
- src/mainboard/dell/e6530/smihandler.c | 9 +++++++++
- 7 files changed, 63 insertions(+)
- create mode 100644 src/mainboard/dell/e5420/smihandler.c
- create mode 100644 src/mainboard/dell/e5520/smihandler.c
- create mode 100644 src/mainboard/dell/e5530/smihandler.c
- create mode 100644 src/mainboard/dell/e6420/smihandler.c
- create mode 100644 src/mainboard/dell/e6430/smihandler.c
- create mode 100644 src/mainboard/dell/e6520/smihandler.c
- create mode 100644 src/mainboard/dell/e6530/smihandler.c
-
-diff --git a/src/mainboard/dell/e5420/smihandler.c b/src/mainboard/dell/e5420/smihandler.c
-new file mode 100644
-index 0000000000..334d7b1a5f
--- /dev/null
-+++ b/src/mainboard/dell/e5420/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/e5520/smihandler.c b/src/mainboard/dell/e5520/smihandler.c
-new file mode 100644
-index 0000000000..334d7b1a5f
--- /dev/null
-+++ b/src/mainboard/dell/e5520/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/e5530/smihandler.c b/src/mainboard/dell/e5530/smihandler.c
-new file mode 100644
-index 0000000000..334d7b1a5f
--- /dev/null
-+++ b/src/mainboard/dell/e5530/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/e6420/smihandler.c b/src/mainboard/dell/e6420/smihandler.c
-new file mode 100644
-index 0000000000..334d7b1a5f
--- /dev/null
-+++ b/src/mainboard/dell/e6420/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/e6430/smihandler.c b/src/mainboard/dell/e6430/smihandler.c
-new file mode 100644
-index 0000000000..334d7b1a5f
--- /dev/null
-+++ b/src/mainboard/dell/e6430/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/e6520/smihandler.c b/src/mainboard/dell/e6520/smihandler.c
-new file mode 100644
-index 0000000000..334d7b1a5f
--- /dev/null
-+++ b/src/mainboard/dell/e6520/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/e6530/smihandler.c b/src/mainboard/dell/e6530/smihandler.c
-new file mode 100644
-index 0000000000..334d7b1a5f
--- /dev/null
-+++ b/src/mainboard/dell/e6530/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_sleep(slp_typ);
-+}
-- 
-2.44.0
-
@@ -1,55 +0,0 @@
-From fa4f05e39744eb4c4606f940b8acc7fd053b11d4 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Sat, 4 May 2024 02:00:53 +0100
-Subject: [PATCH 1/1] nb/haswell: lock policy regs when disabling IOMMU
-
-Angel Pons told me I should do it. See comments here:
-https://review.coreboot.org/c/coreboot/+/81016
-
-I see no harm in complying with the request. I'll merge
-this into the main patch at a later date and try to
-get this upstreamed.
-
-Just a reminder: on Optiplex 9020 variants, Xorg locks up
-under Linux when tested with a graphics card; disabling
-IOMMU works around the issue. Intel graphics work just fine
-with IOMMU turned on. Libreboot disables IOMMU by default,
-on the 9020, so that users can install graphics cards easily.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- src/northbridge/intel/haswell/early_init.c | 15 +++++++--------
- 1 file changed, 7 insertions(+), 8 deletions(-)
-
-diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
-index 1a7e0b1076..e9506ee830 100644
--- a/src/northbridge/intel/haswell/early_init.c
-+++ b/src/northbridge/intel/haswell/early_init.c
-@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void)
- 	const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
- 	u8 enable_iommu = get_uint_option("iommu", 1);
- 
-	if (!enable_iommu)
-		return;
-
- 	if (capid0_a & VTD_DISABLE)
- 		return;
- 
-	/* Setup BARs: zeroize top 32 bits; set enable bit */
-	mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
-	mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
-	mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
-	mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
-+	if (enable_iommu) {
-+		/* Setup BARs: zeroize top 32 bits; set enable bit */
-+		mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
-+		mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
-+		mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
-+		mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
-+	}
- 
- 	/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
- 	u32 reg32;
-- 
-2.39.2
-
@@ -1,2 +1,4 @@
 tree="default"
-rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"
+romtype="normal"
+rev="d862695f5f432b5c78dada5f16c293a4c3f9fce6"
+arch="x86_64"
@@ -1,203 +0,0 @@
-From 4fbd327df271d613d4a56a36eafd88d9d642ec6b Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 1/9] util/ifdtool: add --nuke flag (all 0xFF on region)
-
-When this option is used, the region's contents are overwritten
-with all ones (0xFF).
-
-Example:
-
-./ifdtool --nuke gbe coreboot.rom
-./ifdtool --nuke bios coreboot.com
-./ifdtool --nuke me coreboot.com
-
-Rebased since the last revision update in lbmk.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
- 1 file changed, 81 insertions(+), 31 deletions(-)
-
-diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index 191b3216de..38132b4a28 100644
--- a/util/ifdtool/ifdtool.c
-+++ b/util/ifdtool/ifdtool.c
-@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
- 	       "                                         tgl    - Tiger Lake\n"
- 	       "                                         wbg    - Wellsburg\n"
- 	       "   -S | --setpchstrap                    Write a PCH strap\n"
-+	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
- 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
- 	       "   -v | --version:                       print the version\n"
- 	       "   -h | --help:                          print this help\n\n"
-@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
- 	       "\n");
- }
- 
-+static int
-+get_region_type_string(const char *region_type_string)
-+{
-+       if (!strcasecmp("Descriptor", region_type_string))
-+               return 0;
-+       else if (!strcasecmp("BIOS", region_type_string))
-+               return 1;
-+       else if (!strcasecmp("ME", region_type_string))
-+               return 2;
-+       else if (!strcasecmp("GbE", region_type_string))
-+               return 3;
-+       else if (!strcasecmp("Platform Data", region_type_string))
-+               return 4;
-+       else if (!strcasecmp("Device Exp1", region_type_string))
-+               return 5;
-+       else if (!strcasecmp("Secondary BIOS", region_type_string))
-+               return 6;
-+       else if (!strcasecmp("Reserved", region_type_string))
-+               return 7;
-+       else if (!strcasecmp("EC", region_type_string))
-+               return 8;
-+       else if (!strcasecmp("Device Exp2", region_type_string))
-+               return 9;
-+       else if (!strcasecmp("IE", region_type_string))
-+               return 10;
-+       else if (!strcasecmp("10GbE_0", region_type_string))
-+               return 11;
-+       else if (!strcasecmp("10GbE_1", region_type_string))
-+               return 12;
-+       else if (!strcasecmp("PTT", region_type_string))
-+               return 15;
-+       return -1;
-+}
-+
-+static void
-+nuke(const char *filename, char *image, int size, int region_type)
-+{
-+       int i;
-+       struct region region;
-+       const struct frba *frba = find_frba(image, size);
-+       if (!frba)
-+               exit(EXIT_FAILURE);
-+
-+       region = get_region(frba, region_type);
-+       if (region.size > 0) {
-+               for (i = region.base; i <= region.limit; i++) {
-+                       if ((i + 1) > (size))
-+                               break;
-+                       image[i] = 0xFF;
-+               }
-+               write_image(filename, image, size);
-+       }
-+}
-+
- int main(int argc, char *argv[])
- {
- 	int opt, option_index = 0;
-@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
- 	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
- 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
- 	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
-+	int mode_nuke = 0;
- 	int mode_gpr0_disable = 0;
- 	char *region_type_string = NULL, *region_fname = NULL;
- 	const char *layout_fname = NULL;
-@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
- 		{"validate", 0, NULL, 't'},
- 		{"setpchstrap", 1, NULL, 'S'},
- 		{"newvalue", 1, NULL, 'V'},
-+		{"nuke", 1, NULL, 'N'},
- 		{0, 0, 0, 0}
- 	};
- 
-@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
- 			region_fname++;
- 			// Descriptor, BIOS, ME, GbE, Platform
- 			// valid type?
-			if (!strcasecmp("Descriptor", region_type_string))
-				region_type = 0;
-			else if (!strcasecmp("BIOS", region_type_string))
-				region_type = 1;
-			else if (!strcasecmp("ME", region_type_string))
-				region_type = 2;
-			else if (!strcasecmp("GbE", region_type_string))
-				region_type = 3;
-			else if (!strcasecmp("Platform Data", region_type_string))
-				region_type = 4;
-			else if (!strcasecmp("Device Exp1", region_type_string))
-				region_type = 5;
-			else if (!strcasecmp("Secondary BIOS", region_type_string))
-				region_type = 6;
-			else if (!strcasecmp("Reserved", region_type_string))
-				region_type = 7;
-			else if (!strcasecmp("EC", region_type_string))
-				region_type = 8;
-			else if (!strcasecmp("Device Exp2", region_type_string))
-				region_type = 9;
-			else if (!strcasecmp("IE", region_type_string))
-				region_type = 10;
-			else if (!strcasecmp("10GbE_0", region_type_string))
-				region_type = 11;
-			else if (!strcasecmp("10GbE_1", region_type_string))
-				region_type = 12;
-			else if (!strcasecmp("PTT", region_type_string))
-				region_type = 15;
-			if (region_type == -1) {
-+                       if ((region_type =
-+                           get_region_type_string(region_type_string)) == -1) {
- 				fprintf(stderr, "No such region type: '%s'\n\n",
- 					region_type_string);
- 				fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
-@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
- 		case 't':
- 			mode_validate = 1;
- 			break;
-+               case 'N':
-+                       region_type_string = strdup(optarg);
-+                       if (!region_type_string) {
-+                               fprintf(stderr, "No region specified\n");
-+                               print_usage(argv[0]);
-+                               exit(EXIT_FAILURE);
-+                       }
-+                       if ((region_type =
-+                           get_region_type_string(region_type_string)) == -1) {
-+                               fprintf(stderr, "No such region type: '%s'\n\n",
-+                                       region_type_string);
-+                               print_usage(argv[0]);
-+                               exit(EXIT_FAILURE);
-+                       }
-+                       mode_nuke = 1;
-+                       break;
- 		case 'v':
- 			print_version();
- 			exit(EXIT_SUCCESS);
-@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
- 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
- 			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
- 			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
-			mode_gpr0_disable) > 1) {
-+			mode_gpr0_disable + mode_nuke) > 1) {
- 		fprintf(stderr, "You may not specify more than one mode.\n\n");
- 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
- 		exit(EXIT_FAILURE);
-@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
- 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
- 			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
- 			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
-			mode_validate + mode_gpr0_disable) == 0) {
-+			mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
- 		fprintf(stderr, "You need to specify a mode.\n\n");
- 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
- 		exit(EXIT_FAILURE);
-@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
- 		write_image(new_filename, image, size);
- 	}
- 
-+       if (mode_nuke) {
-+               nuke(new_filename, image, size, region_type);
-+       }
-+
- 	if (mode_altmedisable) {
- 		struct fpsba *fpsba = find_fpsba(image, size);
- 		struct fmsba *fmsba = find_fmsba(image, size);
-- 
-2.39.2
-
@@ -1,39 +0,0 @@
-From de4eeaf6d44cb05c60c0b0d54b43cdb88686b998 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 5/9] Remove warning for coreboot images built without a
- payload
-
-I added this in upstream to prevent people from accidentally flashing
-roms without a payload resulting in a no boot situation, but in
-libreboot lbmk handles the payload and thus this warning always comes
-up. This has caused confusion and concern so just patch it out.
---
- payloads/Makefile.mk | 13 +------------
- 1 file changed, 1 insertion(+), 12 deletions(-)
-
-diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
-index a2336aa876..4f1692a873 100644
--- a/payloads/Makefile.mk
-+++ b/payloads/Makefile.mk
-@@ -49,16 +49,5 @@ distclean-payloads:
- print-repo-info-payloads:
- 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
- 
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
-show_notices:: warn_no_payload
-endif
-
-warn_no_payload:
-	printf "\n\t** WARNING **\n"
-	printf "coreboot has been built without a payload. Writing\n"
-	printf "a coreboot image without a payload to your board's\n"
-	printf "flash chip will result in a non-booting system. You\n"
-	printf "can use cbfstool to add a payload to the image.\n\n"
-
- .PHONY: force-payload coreinfo nvramcui
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
-+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
-- 
-2.39.2
-
@@ -1,52 +0,0 @@
-From 6f4968919cf4e801caacf8392492457b79efa9c6 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Mon, 20 May 2024 10:24:16 -0600
-Subject: [PATCH] mb/dell/e6400: Use 100 MHz reference clock for display
-
-The E6400 uses a 100 MHz reference clock for spread spectrum support on
-LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
-the more common 1280 x 800 display panels, the numerical error was not
-large enough to cause noticable issues, but the actual pixel clock
-frequency derived from a 100 MHz reference using PLL configs calculated
-assuming a 96 MHz reference was not close enough for 1440 x 900 panels,
-which require a much higher pixel clock. This resulted in a garbled
-display in the pre-OS graphics environment provided by libgfxinit.
-
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/e6400/Kconfig   | 3 +++
- src/northbridge/intel/gm45/Kconfig | 4 ++++
- 2 files changed, 7 insertions(+)
-
-diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
-index 034de4be2b..4cb16af697 100644
--- a/src/mainboard/dell/e6400/Kconfig
-+++ b/src/mainboard/dell/e6400/Kconfig
-@@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS
- 	select INTEL_GMA_HAVE_VBT
- 	select EC_DELL_MEC5035
- 
-+config INTEL_GMA_DPLL_REF_FREQ
-+	default 100000000
-+
- config MAINBOARD_DIR
- 	default "dell/e6400"
- 
-diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
-index 2a266b9771..2432c9d78e 100644
--- a/src/northbridge/intel/gm45/Kconfig
-+++ b/src/northbridge/intel/gm45/Kconfig
-@@ -13,6 +13,10 @@ config NORTHBRIDGE_INTEL_GM45
- 
- if NORTHBRIDGE_INTEL_GM45
- 
-+config INTEL_GMA_DPLL_REF_FREQ
-+	int
-+	default 96000000
-+
- config VBOOT
- 	select VBOOT_STARTS_IN_BOOTBLOCK
- 
-- 
-2.45.1
-
@@ -1,7 +1,7 @@
-From 1a4f454e05b613cb080cdd063dd3efb1fdbb748b Mon Sep 17 00:00:00 2001
+From 38c76afbea4abfed2976bfbe10977e41f21665b0 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 20/20] util/ifdtool: add --nuke flag (all 0xFF on region)
+Subject: [PATCH 15/22] util/ifdtool: add --nuke flag (all 0xFF on region)

 When this option is used, the region's contents are overwritten
 with all ones (0xFF).
@@ -16,91 +16,91 @@ Rebased since the last revision update in lbmk.

 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
- util/ifdtool/ifdtool.c | 113 ++++++++++++++++++++++++++++++-----------
- 1 file changed, 82 insertions(+), 31 deletions(-)
+ util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
+ 1 file changed, 83 insertions(+), 31 deletions(-)

 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index 516570e0a3..1638e1710e 100644
+index ddbc0fb91b..7af9235ae3 100644
 --- a/util/ifdtool/ifdtool.c
 +++ b/util/ifdtool/ifdtool.c
-@@ -2143,6 +2143,7 @@ static void print_usage(const char *name)
- 	       "                                         tgl    - Tiger Lake\n"
+@@ -1847,6 +1847,7 @@ static void print_usage(const char *name)
 	       "                                         wbg    - Wellsburg\n"
 	       "   -S | --setpchstrap                    Write a PCH strap\n"
-+	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
+	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
 	       "   -v | --version:                       print the version\n"
 	       "   -h | --help:                          print this help\n\n"
-@@ -2151,6 +2152,60 @@ static void print_usage(const char *name)
+ 	       "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
+@@ -1854,6 +1855,60 @@ static void print_usage(const char *name)
 	       "\n");
 }
 
 +static int
 +get_region_type_string(const char *region_type_string)
 +{
-+       if (!strcasecmp("Descriptor", region_type_string))
-+               return 0;
-+       else if (!strcasecmp("BIOS", region_type_string))
-+               return 1;
-+       else if (!strcasecmp("ME", region_type_string))
-+               return 2;
-+       else if (!strcasecmp("GbE", region_type_string))
-+               return 3;
-+       else if (!strcasecmp("Platform Data", region_type_string))
-+               return 4;
-+       else if (!strcasecmp("Device Exp1", region_type_string))
-+               return 5;
-+       else if (!strcasecmp("Secondary BIOS", region_type_string))
-+               return 6;
-+       else if (!strcasecmp("Reserved", region_type_string))
-+               return 7;
-+       else if (!strcasecmp("EC", region_type_string))
-+               return 8;
-+       else if (!strcasecmp("Device Exp2", region_type_string))
-+               return 9;
-+       else if (!strcasecmp("IE", region_type_string))
-+               return 10;
-+       else if (!strcasecmp("10GbE_0", region_type_string))
-+               return 11;
-+       else if (!strcasecmp("10GbE_1", region_type_string))
-+               return 12;
-+       else if (!strcasecmp("PTT", region_type_string))
-+               return 15;
-+       return -1;
+	if (!strcasecmp("Descriptor", region_type_string))
+		return 0;
+	else if (!strcasecmp("BIOS", region_type_string))
+		return 1;
+	else if (!strcasecmp("ME", region_type_string))
+		return 2;
+	else if (!strcasecmp("GbE", region_type_string))
+		return 3;
+	else if (!strcasecmp("Platform Data", region_type_string))
+		return 4;
+	else if (!strcasecmp("Device Exp1", region_type_string))
+		return 5;
+	else if (!strcasecmp("Secondary BIOS", region_type_string))
+		return 6;
+	else if (!strcasecmp("Reserved", region_type_string))
+		return 7;
+	else if (!strcasecmp("EC", region_type_string))
+		return 8;
+	else if (!strcasecmp("Device Exp2", region_type_string))
+		return 9;
+	else if (!strcasecmp("IE", region_type_string))
+		return 10;
+	else if (!strcasecmp("10GbE_0", region_type_string))
+		return 11;
+	else if (!strcasecmp("10GbE_1", region_type_string))
+		return 12;
+	else if (!strcasecmp("PTT", region_type_string))
+		return 15;
+	return -1;
 +}
 +
 +static void
 +nuke(const char *filename, char *image, int size, int region_type)
 +{
-+       int i;
-+       struct region region;
-+       const struct frba *frba = find_frba(image, size);
-+       if (!frba)
-+               exit(EXIT_FAILURE);
+	int i;
+	struct region region;
+	const struct frba *frba = find_frba(image, size);
+	if (!frba)
+		exit(EXIT_FAILURE);
 +
-+       region = get_region(frba, region_type);
-+       if (region.size > 0) {
-+               for (i = region.base; i <= region.limit; i++) {
-+                       if ((i + 1) > (size))
-+                               break;
-+                       image[i] = 0xFF;
-+               }
-+               write_image(filename, image, size);
-+       }
+	region = get_region(frba, region_type);
+	if (region.size > 0) {
+		for (i = region.base; i <= region.limit; i++) {
+			if ((i + 1) > (size))
+				break;
+			image[i] = 0xFF;
+		}
+		write_image(filename, image, size);
+	}
 +}
 +
 int main(int argc, char *argv[])
 {
 	int opt, option_index = 0;
-@@ -2158,6 +2213,7 @@ int main(int argc, char *argv[])
+@@ -1861,6 +1916,7 @@ int main(int argc, char *argv[])
 	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
 	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
 +	int mode_nuke = 0;
- 	int mode_gpr0_disable = 0, mode_gpr0_enable = 0;
 	char *region_type_string = NULL, *region_fname = NULL;
 	const char *layout_fname = NULL;
-@@ -2192,6 +2248,7 @@ int main(int argc, char *argv[])
+ 	char *new_filename = NULL;
+@@ -1892,6 +1948,7 @@ int main(int argc, char *argv[])
 		{"validate", 0, NULL, 't'},
 		{"setpchstrap", 1, NULL, 'S'},
 		{"newvalue", 1, NULL, 'V'},
@@ -108,7 +108,7 @@ index 516570e0a3..1638e1710e 100644
 		{0, 0, 0, 0}
 	};
 
-@@ -2241,35 +2298,8 @@ int main(int argc, char *argv[])
+@@ -1941,35 +1998,8 @@ int main(int argc, char *argv[])
 			region_fname++;
 			// Descriptor, BIOS, ME, GbE, Platform
 			// valid type?
@@ -146,7 +146,7 @@ index 516570e0a3..1638e1710e 100644
 				fprintf(stderr, "No such region type: '%s'\n\n",
 					region_type_string);
 				fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
-@@ -2441,6 +2471,22 @@ int main(int argc, char *argv[])
+@@ -2135,6 +2165,22 @@ int main(int argc, char *argv[])
 		case 't':
 			mode_validate = 1;
 			break;
@@ -169,32 +169,33 @@ index 516570e0a3..1638e1710e 100644
 		case 'v':
 			print_version();
 			exit(EXIT_SUCCESS);
-@@ -2457,7 +2503,7 @@ int main(int argc, char *argv[])
+@@ -2150,7 +2196,8 @@ int main(int argc, char *argv[])
+ 
 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
 			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
- 			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
-			(mode_gpr0_disable | mode_gpr0_enable)) > 1) {
-+			(mode_gpr0_disable | mode_gpr0_enable) + mode_nuke) > 1) {
+-			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) {
+			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
+			mode_nuke) > 1) {
 		fprintf(stderr, "You may not specify more than one mode.\n\n");
 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
 		exit(EXIT_FAILURE);
-@@ -2466,7 +2512,8 @@ int main(int argc, char *argv[])
+@@ -2158,7 +2205,8 @@ int main(int argc, char *argv[])
+ 
 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
 			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
- 			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
-			mode_validate + (mode_gpr0_disable | mode_gpr0_enable)) == 0) {
-+			mode_validate + (mode_gpr0_disable | mode_gpr0_enable) +
-+			mode_nuke) == 0) {
+-			mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
+			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
+			mode_validate + mode_nuke) == 0) {
 		fprintf(stderr, "You need to specify a mode.\n\n");
 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
 		exit(EXIT_FAILURE);
-@@ -2576,6 +2623,10 @@ int main(int argc, char *argv[])
+@@ -2262,6 +2310,10 @@ int main(int argc, char *argv[])
 		write_image(new_filename, image, size);
 	}
 
 +	if (mode_nuke) {
-+		nuke(new_filename, image, size, region_type);
-+	}
+               nuke(new_filename, image, size, region_type);
+       }
 +
 	if (mode_altmedisable) {
 		struct fpsba *fpsba = find_fpsba(image, size);
@@ -1,7 +1,7 @@
-From 362e86f89b3980699e7e794df9b98018397fe2d8 Mon Sep 17 00:00:00 2001
+From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 1 Dec 2021 02:53:00 +0000
-Subject: [PATCH 2/9] fix speedstep on x200/t400: Revert
+Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
 "cpu/intel/model_1067x: enable PECI"

 This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
@@ -1,7 +1,7 @@
-From 883455573f07551eaf2b12ab80bedcd2b4904a17 Mon Sep 17 00:00:00 2001
+From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 17 Apr 2023 15:49:57 +0100
-Subject: [PATCH 3/9] GM45-type CPUs: don't enable alternative SMRR
+Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR

 This reverts the changes in coreboot revision:
 df7aecd92643d207feaf7fd840f8835097346644
@@ -1,8 +1,8 @@
-From 458fe39e9cd2536cfa8671427e6f557396143339 Mon Sep 17 00:00:00 2001
+From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 4/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
- models
+Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for
+ dGPU models

 Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -1,7 +1,7 @@
-From c25dcd8ac80598939edffd011df0fd9ba3d8a1a8 Mon Sep 17 00:00:00 2001
+From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 18/20] Remove warning for coreboot images built without a
+Subject: [PATCH 19/22] Remove warning for coreboot images built without a
 payload

 I added this in upstream to prevent people from accidentally flashing
@@ -9,19 +9,19 @@ roms without a payload resulting in a no boot situation, but in
 libreboot lbmk handles the payload and thus this warning always comes
 up. This has caused confusion and concern so just patch it out.
 ---
- payloads/Makefile.mk | 13 +------------
+ payloads/Makefile.inc | 13 +------------
 1 file changed, 1 insertion(+), 12 deletions(-)

-diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
-index a2336aa876..4f1692a873 100644
--- a/payloads/Makefile.mk
-+++ b/payloads/Makefile.mk
+diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
+index e735443a76..4f1692a873 100644
+--- a/payloads/Makefile.inc
+++ b/payloads/Makefile.inc
@@ -49,16 +49,5 @@ distclean-payloads:
 print-repo-info-payloads:
 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
 
 -ifeq ($(CONFIG_PAYLOAD_NONE),y)
-show_notices:: warn_no_payload
+-files_added:: warn_no_payload
 -endif
 -
 -warn_no_payload:
@@ -0,0 +1,61 @@
+From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sun, 27 Aug 2023 17:36:36 -0600
+Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios
+
+These were determined by sniffing the LPC bus while toggling the
+hardware wireless switch on the Latitude E6400. To differentiate devices
+options in the vendor BIOS to change which radios the switch controlled
+were used.
+
+Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/ec/dell/mec5035/mec5035.c | 9 +++++++++
+ src/ec/dell/mec5035/mec5035.h | 8 ++++++++
+ 2 files changed, 17 insertions(+)
+
+diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
+index 8da11e5b1c..e0335a4635 100644
+--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
+@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting)
+ 	return buf[0];
+ }
+ 
+void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on)
+{
+	/* From LPC traces and userspace testing with other values,
+	   the second byte has to be 2 for an unknown reason. */
+	u8 buf[3] = {dev, 2, on};
+	write_mailbox_regs(buf, 2, 3);
+	ec_command(CMD_RADIO_EN);
+}
+
+ void mec5035_early_init(void)
+ {
+ 	/* If this isn't sent the EC shuts down the system after about 15
+diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
+index e7a05b64d4..16512e2cc2 100644
+--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
+@@ -16,8 +16,16 @@
+ 
+ #define CMD_CPU_OK	0xc2
+ 
+#define CMD_RADIO_EN	0x2b
+enum mec5035_radio_dev {
+	RADIO_WLAN = 0,
+	RADIO_WWAN = 1,
+	RADIO_WPAN = 2,
+};
+
+ u8 mec5035_mouse_touchpad(u8 setting);
+ void mec5035_cpu_ok(void);
+ void mec5035_early_init(void);
+void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on);
+ 
+ #endif /* _EC_DELL_MEC5035_H_ */
+-- 
+2.39.2
+
@@ -0,0 +1,37 @@
+From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sun, 27 Aug 2023 19:15:37 -0600
+Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API
+
+Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/ec/dell/mec5035/mec5035.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
+index e0335a4635..20a33cc0ad 100644
+--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
+@@ -4,6 +4,7 @@
+ #include <console/console.h>
+ #include <device/device.h>
+ #include <device/pnp.h>
+#include <option.h>
+ #include <pc80/keyboard.h>
+ #include <stdint.h>
+ #include "mec5035.h"
+@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev)
+ 	mec5035_mouse_touchpad(TP_PS2_MOUSE);
+ 
+ 	pc_keyboard_init(NO_AUX_DEVICE);
+
+	mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1));
+	mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1));
+	mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1));
+ }
+ 
+ static struct device_operations ops = {
+-- 
+2.39.2
+
@@ -1,7 +1,7 @@
-From 536a1dd349f590cbefccac7e7364cafcdaec9600 Mon Sep 17 00:00:00 2001
+From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 22 Oct 2023 15:02:25 +0100
-Subject: [PATCH 22/30] don't use github for the acpica download
+Subject: [PATCH 1/1] don't use github for the acpica download

 i have the tarball from a previous download, and i placed
 it on libreboot rsync, which then got mirrored to princeton.
@@ -22,7 +22,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
 1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 23a5caf2bb..36565a906c 100755
+index ebc9fcb49a..a857110b4b 100755
 --- a/util/crossgcc/buildgcc
 +++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
@@ -0,0 +1,341 @@
+From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 29 Oct 2023 01:18:50 +0000
+Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
+ value"
+
+This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
+
+NOTE:
+
+this is done instead of merging:
+https://review.coreboot.org/c/coreboot/+/78623
+
+which is still under review for now
+
+the patch i'm reverting is this one:
+https://review.coreboot.org/c/coreboot/+/78270
+
+this was actually only merged the day before i
+updated coreboot revs in lbmk to the 12 october rev,
+so there's no harm in quickly reverting this for now
+
+however, later on, we will rely on the other patch
+---
+ src/Kconfig                                   | 3 ++-
+ src/cpu/qemu-x86/Kconfig                      | 3 +++
+ src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
+ src/northbridge/amd/pi/Kconfig                | 4 ++++
+ src/soc/amd/picasso/Kconfig                   | 4 ++++
+ src/soc/amd/stoneyridge/Kconfig               | 4 ++++
+ src/soc/cavium/cn81xx/Kconfig                 | 3 +++
+ src/soc/intel/alderlake/Kconfig               | 5 +++++
+ src/soc/intel/apollolake/Kconfig              | 4 ++++
+ src/soc/intel/cannonlake/Kconfig              | 4 ++++
+ src/soc/intel/elkhartlake/Kconfig             | 4 ++++
+ src/soc/intel/jasperlake/Kconfig              | 4 ++++
+ src/soc/intel/meteorlake/Kconfig              | 5 +++++
+ src/soc/intel/skylake/Kconfig                 | 4 ++++
+ src/soc/intel/tigerlake/Kconfig               | 4 ++++
+ src/soc/intel/xeon_sp/Kconfig                 | 4 ++++
+ src/soc/intel/xeon_sp/cpx/Kconfig             | 4 ++++
+ src/soc/intel/xeon_sp/skx/Kconfig             | 4 ++++
+ src/soc/intel/xeon_sp/spr/Kconfig             | 4 ++++
+ src/soc/qualcomm/ipq40xx/Kconfig              | 4 ++++
+ 20 files changed, 77 insertions(+), 1 deletion(-)
+
+diff --git a/src/Kconfig b/src/Kconfig
+index ae8024089e..1549719dd0 100644
+--- a/src/Kconfig
+++ b/src/Kconfig
+@@ -751,7 +751,8 @@ config RTC
+ 
+ config HEAP_SIZE
+ 	hex
+-	default 0x100000
+	default 0x100000 if FLATTENED_DEVICE_TREE
+	default 0x4000
+ 
+ config STACK_SIZE
+ 	hex
+diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
+index 0fa999e1ac..f3e2c4cea9 100644
+--- a/src/cpu/qemu-x86/Kconfig
+++ b/src/cpu/qemu-x86/Kconfig
+@@ -35,4 +35,7 @@ config MAX_CPUS
+ 	default 32 if SMM_TSEG
+ 	default 4
+ 
+config HEAP_SIZE
+	default 0x8000
+
+ endif
+diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
+index 7bc3b0bcbb..7f9300f2a7 100644
+--- a/src/mainboard/sifive/hifive-unleashed/Kconfig
+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
+@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select FLATTENED_DEVICE_TREE
+ 	select SPI_SDCARD
+ 
+config HEAP_SIZE
+	default 0x10000
+
+ config MAINBOARD_DIR
+ 	default "sifive/hifive-unleashed"
+ 
+diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
+index 4ffe82a15f..4518db149b 100644
+--- a/src/northbridge/amd/pi/Kconfig
+++ b/src/northbridge/amd/pi/Kconfig
+@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
+ 	hex
+ 	default 0x200000
+ 
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+ endif # NORTHBRIDGE_AMD_PI
+diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
+index c33f287067..796fe4eb13 100644
+--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
+@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
+ 	bool
+ 	default n
+ 
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+ config SERIRQ_CONTINUOUS_MODE
+ 	bool
+ 	default n
+diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
+index 6ff135e6a8..9af7455bae 100644
+--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
+@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
+ 	bool
+ 	default n
+ 
+config HEAP_SIZE
+	hex
+	default 0xc0000
+
+ config EHCI_BAR
+ 	hex
+ 	default 0xfef00000
+diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
+index 77ca97202b..368581f8f1 100644
+--- a/src/soc/cavium/cn81xx/Kconfig
+++ b/src/soc/cavium/cn81xx/Kconfig
+@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
+ 	int
+ 	default 1
+ 
+config HEAP_SIZE
+	default 0x10000
+
+ config STACK_SIZE
+ 	default 0x2000
+ 
+diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
+index 4b960c1d22..82ec8f263e 100644
+--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
+@@ -215,6 +215,11 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000 if BMP_LOGO
+	default 0x10000
+
+ config GFX_GMA_DEFAULT_MMIO
+ 	default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
+ 
+diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
+index 78ec2987ce..bce935d800 100644
+--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
+@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
+ 	help
+ 	  Name of file to store in the IFWI region.
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 6
+diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
+index a42a3c365b..80237f9810 100644
+--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
+@@ -160,6 +160,10 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config NHLT_DMIC_1CH_16B
+ 	bool
+ 	depends on ACPI_NHLT
+diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
+index 3361c0ddb9..7f1c767379 100644
+--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
+@@ -104,6 +104,10 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x0
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 7
+diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
+index 3d84991e09..ff5def3263 100644
+--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
+@@ -106,6 +106,10 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 8
+diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
+index 590e8b80e1..48030a1911 100644
+--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
+@@ -197,6 +197,11 @@ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000 if BMP_LOGO
+	default 0x10000
+
+ # Intel recommends reserving the PCIe TBT root port resources as below:
+ # - 42 buses
+ # - 194 MiB Non-prefetchable memory
+diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
+index e0df501460..d6a11363ee 100644
+--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
+@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
+ 	help
+ 	  If you set this option to n, will not use native SD controller.
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
+index c07a0d8365..0a4b7bfdb8 100644
+--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
+@@ -152,6 +152,10 @@ config IED_REGION_SIZE
+ config INTEL_TME
+ 	default n
+ 
+config HEAP_SIZE
+	hex
+	default 0x10000
+
+ config MAX_ROOT_PORTS
+ 	int
+ 	default 24 if SOC_INTEL_TIGERLAKE_PCH_H
+diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
+index e63bee5451..63ced01067 100644
+--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
+@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
+ config ECAM_MMCONF_BUS_NUMBER
+ 	default 256
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config HPET_MIN_TICKS
+ 	hex
+ 	default 0x80
+diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
+index ac166c3038..f54f7716b6 100644
+--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
+@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
+ 	hex
+ 	default 0x7C00
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config STACK_SIZE
+ 	hex
+ 	default 0x4000
+diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
+index 5d843878e1..c2c3d4e2e8 100644
+--- a/src/soc/intel/xeon_sp/skx/Kconfig
+++ b/src/soc/intel/xeon_sp/skx/Kconfig
+@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
+ 	hex
+ 	default 0x7C00
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config IED_REGION_SIZE
+ 	hex
+ 	default 0x400000
+diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
+index 43b87ade14..b1c4c783b7 100644
+--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
+@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
+ 	hex
+ 	default 0x8c00
+ 
+config HEAP_SIZE
+	hex
+	default 0x80000
+
+ config STACK_SIZE
+ 	hex
+ 	default 0x4000
+diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
+index 0ce92731c0..0eabb00752 100644
+--- a/src/soc/qualcomm/ipq40xx/Kconfig
+++ b/src/soc/qualcomm/ipq40xx/Kconfig
+@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
+ 	help
+ 	  Path for utils to combine SBL_ELF and bootblock
+ 
+config HEAP_SIZE
+	hex
+	default 0x8000
+
+ endif
+-- 
+2.39.2
+
@@ -1,7 +1,7 @@
-From f26df5dff7be4b0c9d8dced1cf6ed07472a174c7 Mon Sep 17 00:00:00 2001
+From e047dc3c95063f27517cd6754e9cbe496ac9313d Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH 8/9] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH] [NOT FOR MERGE] nb/intel/gm45: Make DDR2 raminit work

 List of changes:
 - Update some timing and ODT values
@@ -14,16 +14,12 @@ Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs.
 Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c
 Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 ---
- src/northbridge/intel/gm45/gm45.h             |  2 +-
- src/northbridge/intel/gm45/raminit.c          | 90 +++++++++++++++++--
- .../intel/gm45/raminit_rcomp_calibration.c    | 27 ++++--
- 3 files changed, 106 insertions(+), 13 deletions(-)

 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
-index d929533d92..997f8a0e5a 100644
+index f28c6d1..bdf0432 100644
 --- a/src/northbridge/intel/gm45/gm45.h
 +++ b/src/northbridge/intel/gm45/gm45.h
-@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
+@@ -419,7 +419,7 @@
 int raminit_read_vco_index(void);
 u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
 
@@ -33,10 +29,10 @@ index d929533d92..997f8a0e5a 100644
 void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
 void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
 diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
-index b7e013959a..df8f46fbbc 100644
+index ecada7b..2b8c44e 100644
 --- a/src/northbridge/intel/gm45/raminit.c
 +++ b/src/northbridge/intel/gm45/raminit.c
-@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping,
+@@ -1049,7 +1049,7 @@
 	}
 
 	/* Perform RCOMP calibration for DDR3. */
@@ -45,7 +41,7 @@ index b7e013959a..df8f46fbbc 100644
 
 	/* Run initial RCOMP. */
 	mchbar_setbits32(0x418, 1 << 17);
-@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
+@@ -1119,7 +1119,7 @@
 				reg = (reg & ~(0xf << 10)) | (2 << 10);
 			else
 				reg = (reg & ~(0xf << 10)) | (3 << 10);
@@ -54,7 +50,7 @@ index b7e013959a..df8f46fbbc 100644
 		} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
 			reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
 			reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
-@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff)
+@@ -1288,11 +1288,11 @@
 		reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32));
 		reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32));
 		if (timings->mem_clock == MEM_CLOCK_667MT) {
@@ -70,7 +66,7 @@ index b7e013959a..df8f46fbbc 100644
 		}
 		mchbar_write32(CxODT_HIGH(ch), reg);
 
-@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
+@@ -2217,6 +2217,84 @@
 		raminit_write_training(timings->mem_clock, dimms, s3resume);
 	}
 
@@ -156,10 +152,10 @@ index b7e013959a..df8f46fbbc 100644
 
 	/* Program final memory map (with real values). */
 diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-index aef863f05a..b74765fd9c 100644
+index aef863f..b74765f 100644
 --- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
 +++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step,
+@@ -161,11 +161,13 @@
 		mchbar += 4;
 	}
 }
@@ -174,7 +170,7 @@ index aef863f05a..b74765fd9c 100644
 	enum {
 		PULL_UP = 0,
 		PULL_DOWN = 1,
-@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
+@@ -196,6 +198,10 @@
 		reg = mchbar_read32(0x518);
 		lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
 		lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
@@ -185,7 +181,7 @@ index aef863f05a..b74765fd9c 100644
 	}
 	/* Cleanup? */
 	mchbar_setbits32(0x400, 1 << 3);
-@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
+@@ -216,13 +222,19 @@
 	for (channel = 0; channel < 2; ++channel) {
 		for (group = 0; group < 6; ++group) {
 			for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) {
@@ -210,7 +206,7 @@ index aef863f05a..b74765fd9c 100644
 			mchbar += 0x0010;
 			/* Channel B knows only the first two groups. */
 			if ((1 == channel) && (1 == group))
-@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
+@@ -230,4 +242,7 @@
 		}
 		mchbar += 0x0040;
 	}
@@ -218,6 +214,3 @@ index aef863f05a..b74765fd9c 100644
 +	mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
 +	mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
 }
-- 
-2.39.2
-
@@ -1,7 +1,7 @@
-From f318da0563ecb2386ac368e04bad88a8aacbc83d Mon Sep 17 00:00:00 2001
+From 1116145917035a92cc92a34e6a914a9506d17680 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 1 Nov 2023 16:33:11 +0000
-Subject: [PATCH 9/9] dell/e6400: crank up vram to 256MB (max)
+Subject: [PATCH 1/1] dell/e6400: crank up vram to 256MB (max)

 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
@@ -1,7 +1,7 @@
-From 936a8f113772c93d7501e7133159ab4e23436222 Mon Sep 17 00:00:00 2001
+From 89c47fad6e97fc6a7113ebbdedfcc42ae2b6fc7f Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 22:57:08 +0000
-Subject: [PATCH 25/30] use mirrorservice.org for gcc downloads
+Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads

 the gnu.org 302 redirect often fails

@@ -11,7 +11,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
 1 file changed, 5 insertions(+), 5 deletions(-)

 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 36565a906c..4d4ca06113 100755
+index 87f80ba7f6..b3aad5df7d 100755
 --- a/util/crossgcc/buildgcc
 +++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
@@ -1,4 +1,4 @@
 tree="dell"
-tree_depend="default"
-xtree="default"
-rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"
+romtype="normal"
+rev="d862695f5f432b5c78dada5f16c293a4c3f9fce6"
+arch="x86_64"
@@ -1,640 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-CONFIG_UTIL_GENPARSER=y
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_TSEG_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
-CONFIG_VGA_BIOS_ID="8086,0166"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x800000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_TPM_PIRQ=0x0
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xff7c0000
-CONFIG_DCACHE_RAM_SIZE=0x40000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-# CONFIG_ENABLE_DDR_2X_REFRESH is not set
-CONFIG_PCIEXP_AER=y
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-CONFIG_PCIEXP_L1_SUB_STATE=y
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=12288
-CONFIG_ROM_SIZE=0x00c00000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_EHCI_BAR=0xe8000000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_DISABLE_ME_PCI=y
-CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_HASWELL=y
-CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
-CONFIG_USE_NATIVE_RAMINIT=y
-
-#
-# Southbridge
-#
-# CONFIG_PCIEXP_HOTPLUG is not set
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
-CONFIG_FINALIZE_USB_ROUTE_XHCI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_SMSC_SCH555x=y
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
-CONFIG_TPM_INIT_RAMSTAGE=y
-# CONFIG_TPM_PPI is not set
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_DDI=y
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Haswell"
-CONFIG_GFX_GMA_PCH="Lynx_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-# CONFIG_NO_TPM is not set
-CONFIG_TPM1=y
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM1=y
-# CONFIG_TPM_DEACTIVATE is not set
-# CONFIG_DEBUG_TPM is not set
-# CONFIG_TPM_RDRESP_NEED_DELAY is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_INTEL_TXT is not set
-# CONFIG_STM is not set
-# CONFIG_INTEL_CBNT_SUPPORT is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_EM100PRO_SPI_CONSOLE is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y
@@ -1,7 +0,0 @@
-tree="haswell"
-xarch="i386-elf"
-payload_seabios="y"
-payload_seabios_withgrub="y"
-payload_memtest="y"
-grub_scan_disk="nvme ahci"
-grubtree="xhci"
@@ -1,640 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_TSEG_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
-CONFIG_VGA_BIOS_ID="8086,0166"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x800000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_TPM_PIRQ=0x0
-# CONFIG_BOARD_DELL_E6400 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xff7c0000
-CONFIG_DCACHE_RAM_SIZE=0x40000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-# CONFIG_ENABLE_DDR_2X_REFRESH is not set
-CONFIG_PCIEXP_AER=y
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-CONFIG_PCIEXP_L1_SUB_STATE=y
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=12288
-CONFIG_ROM_SIZE=0x00c00000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_EHCI_BAR=0xe8000000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_DISABLE_ME_PCI=y
-CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_HASWELL=y
-CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
-CONFIG_USE_NATIVE_RAMINIT=y
-
-#
-# Southbridge
-#
-# CONFIG_PCIEXP_HOTPLUG is not set
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
-CONFIG_FINALIZE_USB_ROUTE_XHCI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_SMSC_SCH555x=y
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
-CONFIG_TPM_INIT_RAMSTAGE=y
-# CONFIG_TPM_PPI is not set
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_DDI=y
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Haswell"
-CONFIG_GFX_GMA_PCH="Lynx_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-# CONFIG_NO_TPM is not set
-CONFIG_TPM1=y
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM1=y
-# CONFIG_TPM_DEACTIVATE is not set
-# CONFIG_DEBUG_TPM is not set
-# CONFIG_TPM_RDRESP_NEED_DELAY is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_INTEL_TXT is not set
-# CONFIG_STM is not set
-# CONFIG_INTEL_CBNT_SUPPORT is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_EM100PRO_SPI_CONSOLE is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y
@@ -1,7 +0,0 @@
-tree="haswell"
-xarch="i386-elf"
-payload_seabios="y"
-payload_seabios_withgrub="y"
-payload_memtest="y"
-grub_scan_disk="nvme ahci"
-grubtree="xhci"
@@ -1,620 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_TSEG_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E5420"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e5420"
-CONFIG_VGA_BIOS_ID="8086,0116"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x5ea000
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_BOARD_DELL_LATITUDE_E5420=y
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5420"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=6144
-CONFIG_ROM_SIZE=0x00600000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_ACPI=y
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y
@@ -1,617 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_TSEG_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E5420"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e5420"
-CONFIG_VGA_BIOS_ID="8086,0116"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x5ea000
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_BOARD_DELL_LATITUDE_E5420=y
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5420"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=6144
-CONFIG_ROM_SIZE=0x00600000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_ACPI=y
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y
@@ -1,620 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_TSEG_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E5520"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e5520"
-CONFIG_VGA_BIOS_ID="8086,0126"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x5ea000
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-CONFIG_BOARD_DELL_LATITUDE_E5520=y
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5520"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=6144
-CONFIG_ROM_SIZE=0x00600000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_ACPI=y
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y
@@ -1,617 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_TSEG_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E5520"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e5520"
-CONFIG_VGA_BIOS_ID="8086,0126"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x5ea000
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-CONFIG_BOARD_DELL_LATITUDE_E5520=y
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5520"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=6144
-CONFIG_ROM_SIZE=0x00600000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_ACPI=y
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y
@@ -1,620 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_TSEG_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E5530"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e5530"
-CONFIG_VGA_BIOS_ID="8086,0166"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0xBE7000
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-CONFIG_BOARD_DELL_LATITUDE_E5530=y
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_ivybridge/ifd_nogbe"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_ivybridge/me.bin"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5530"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=12288
-CONFIG_ROM_SIZE=0x00c00000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
-CONFIG_SOUTHBRIDGE_INTEL_C216=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_ACPI=y
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y
@@ -1,617 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_TSEG_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E5530"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e5530"
-CONFIG_VGA_BIOS_ID="8086,0166"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0xBE7000
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-CONFIG_BOARD_DELL_LATITUDE_E5530=y
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_ivybridge/ifd_nogbe"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_ivybridge/me.bin"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5530"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=12288
-CONFIG_ROM_SIZE=0x00c00000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
-CONFIG_SOUTHBRIDGE_INTEL_C216=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_ACPI=y
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y
@@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -136,7 +135,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_BOARD_DELL_E6400=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -152,6 +150,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
 CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom"
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
@@ -171,6 +170,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -184,7 +184,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=4096
@@ -214,7 +213,6 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
 # CONFIG_VGA_BIOS_SECOND is not set
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -223,15 +221,14 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000

 #
 # CPU
@@ -330,8 +327,6 @@ CONFIG_HAVE_EXP_X86_64_SUPPORT=y
 CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -368,7 +363,7 @@ CONFIG_LINEAR_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
+CONFIG_AZALIA_PLUGIN_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -379,6 +374,8 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -409,7 +406,6 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 CONFIG_HAVE_USBDEBUG_OPTIONS=y
@@ -425,10 +421,6 @@ CONFIG_INTEL_EDID=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
 CONFIG_GFX_GMA_DYN_CPU=y
@@ -467,7 +459,6 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module

@@ -495,7 +486,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
@@ -559,10 +549,6 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set

-#
-# Vendorcode Debug Settings
-#
-
 #
 # BLOB Debug Settings
 #
@@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -134,7 +133,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_BOARD_DELL_E6400=y
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -150,6 +148,7 @@ CONFIG_SPI_FLASH_WINBOND=y
 CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
 CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom"
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
@@ -169,6 +168,7 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -182,7 +182,6 @@ CONFIG_COREBOOT_ROMSIZE_KB_4096=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=4096
@@ -212,7 +211,6 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
 # CONFIG_VGA_BIOS_SECOND is not set
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -221,15 +219,14 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000

 #
 # CPU
@@ -328,8 +325,6 @@ CONFIG_HAVE_EXP_X86_64_SUPPORT=y
 CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -364,7 +359,7 @@ CONFIG_VGA_TEXT_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
+CONFIG_AZALIA_PLUGIN_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -375,6 +370,8 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -405,7 +402,6 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 CONFIG_HAVE_USBDEBUG_OPTIONS=y
@@ -421,10 +417,6 @@ CONFIG_INTEL_EDID=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
 CONFIG_GFX_GMA_DYN_CPU=y
@@ -463,7 +455,6 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module

@@ -491,7 +482,6 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
@@ -555,10 +545,6 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set

-#
-# Vendorcode Debug Settings
-#
-
 #
 # BLOB Debug Settings
 #
@@ -1,6 +1,11 @@
 tree="dell"
-xarch="i386-elf"
+romtype="4MiB ICH9 IFD NOR flash"
+arch="x86_64"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
-payload_seabios_withgrub="y"
 payload_memtest="y"
+payload_seabios_withgrub="y"
+payload_seabios_grubonly="y"
 grub_scan_disk="ahci"
+microcode_required="n"
@@ -1,568 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_TSEG_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E6400"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e6400"
-CONFIG_VGA_BIOS_ID="10de,06eb"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x3FD000
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-CONFIG_VGA_BIOS=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_BOARD_DELL_E6400=y
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefc0000
-CONFIG_DCACHE_RAM_SIZE=0x10000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom"
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6400"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_D3COLD_SUPPORT=y
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_4096=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_4096=y
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=4096
-CONFIG_ROM_SIZE=0x00400000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-# CONFIG_VGA_BIOS_SECOND is not set
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x61254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_SOCKET_P=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_GM45=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-# CONFIG_HAVE_ME_BIN is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_VGA_ROM_RUN_DEFAULT=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-# CONFIG_MAINBOARD_USE_LIBGFXINIT is not set
-# CONFIG_VGA_ROM_RUN is not set
-CONFIG_NO_GFX_INIT=y
-CONFIG_NO_EARLY_GFX_INIT=y
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-# CONFIG_VGA_BIOS_DGPU is not set
-CONFIG_INTEL_GMA_HAVE_VBT=y
-# CONFIG_INTEL_GMA_ADD_VBT is not set
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_EDID=y
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_NULL=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y
@@ -1,6 +0,0 @@
-tree="dell"
-xarch="i386-elf"
-payload_seabios="y"
-payload_seabios_withgrub="y"
-payload_memtest="y"
-grub_scan_disk="ahci"
@@ -22,7 +22,6 @@ CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -134,20 +133,11 @@ CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_USBDEBUG_HCD_INDEX=2
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
 # CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
 CONFIG_BOARD_DELL_LATITUDE_E6430=y
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
 # CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
 # CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
 # CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -165,6 +155,7 @@ CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_ivybridge/ifd"
 CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_ivybridge/me.bin"
 CONFIG_GBE_BIN_PATH="../../../config/ifd/dell_ivybridge/gbe"
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -174,6 +165,8 @@ CONFIG_HAVE_IFD_BIN=y
 CONFIG_PCIEXP_HOTPLUG_BUSES=8
 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
 CONFIG_D3COLD_SUPPORT=y
 CONFIG_PCIEXP_ASPM=y
@@ -181,6 +174,7 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
+CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -194,7 +188,6 @@ CONFIG_BOARD_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_12288=y
 # CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
 CONFIG_COREBOOT_ROMSIZE_KB=12288
@@ -225,7 +218,6 @@ CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -235,16 +227,15 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_CBFS_CACHE_ALIGN=8
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000

 #
 # CPU
@@ -293,8 +284,8 @@ CONFIG_RAMINIT_ENABLE_ECC=y
 #
 # Southbridge
 #
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
 CONFIG_SOUTHBRIDGE_INTEL_C216=y
+CONFIG_SOUTH_BRIDGE_OPTIONS=y
 # CONFIG_HIDE_MEI_ON_ERROR is not set
 CONFIG_PCIEXP_HOTPLUG=y
 CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
@@ -355,8 +346,6 @@ CONFIG_ARCH_ALL_STAGES_X86_32=y
 CONFIG_HAVE_EXP_X86_64_SUPPORT=y
 CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -392,7 +381,7 @@ CONFIG_LINEAR_FRAMEBUFFER=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
+CONFIG_AZALIA_PLUGIN_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -403,6 +392,8 @@ CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x800
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
@@ -433,7 +424,6 @@ CONFIG_SPI_FLASH_EON=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 CONFIG_HAVE_USBDEBUG_OPTIONS=y
@@ -447,10 +437,6 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y
 # CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
 CONFIG_GFX_GMA_DYN_CPU=y
@@ -489,7 +475,6 @@ CONFIG_NO_TPM=y
 CONFIG_PCR_BOOT_MODE=1
 CONFIG_PCR_HWID=1
 CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
 CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module

@@ -518,7 +503,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000

 #
 # Console
@@ -582,10 +566,6 @@ CONFIG_PAYLOAD_NONE=y
 #
 # CONFIG_DISPLAY_MTRRS is not set

-#
-# Vendorcode Debug Settings
-#
-
 #
 # BLOB Debug Settings
 #
--- a/Show More
+++ b/Show More