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https://codeberg.org/libreboot/lbmk.git
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Leah Rowe
742c00331e
the ddr2 fix broke *ddr3* on gm45 thinkpads in testing, depending on memory modules. this was established by removing patches, re-doing configs etc, on a user's X200 (testing gentoo and freebsd). the X200 kept randomly rebooting or having random glitches. the configs themselves (gm45 thinkpads) will also be re-done, because i found minor issues unrelated, but this patch moves dell e6400 to its own tree. the ddr2 fix is no longer present in coreboot/default, only coreboot/dell. i noticed minor differences in gm45 thinkpad configs, when re-doing the configs, versus what are currently in lbmk master; for instance, vbt was not enabled anymore, on thinkpad x200. modifications to these will be done separately. Signed-off-by: Leah Rowe <leah@libreboot.org>
48 lines
1.7 KiB
Diff
48 lines
1.7 KiB
Diff
From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
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From: Leah Rowe <leah@libreboot.org>
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Date: Wed, 1 Dec 2021 02:53:00 +0000
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Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
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"cpu/intel/model_1067x: enable PECI"
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This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
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Enabling PECI without microcode updates loaded causes the CPUID feature set
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to become corrupted. And one consequence is broken SpeedStep. At least, that's
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my understanding looking at Intel Errata. This revert is not a fix, because
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upstream is correct (upstream assumes microcode updates). We will simply
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maintain this revert patch in Libreboot, from now on.
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---
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src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
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1 file changed, 9 deletions(-)
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diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
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index 315e7c36fc..1423fd72bc 100644
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--- a/src/cpu/intel/model_1067x/model_1067x_init.c
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+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
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@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
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wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
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}
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-#define IA32_PECI_CTL 0x5a0
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-
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static void configure_misc(const int eist, const int tm2, const int emttm)
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{
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msr_t msr;
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@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
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msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
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wrmsr(IA32_MISC_ENABLE, msr);
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}
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-
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- /* Enable PECI
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- WARNING: due to Erratum AW67 described in Intel document #318733
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- the microcode must be updated before this MSR is written to. */
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- msr = rdmsr(IA32_PECI_CTL);
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- msr.lo |= 1;
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- wrmsr(IA32_PECI_CTL, msr);
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}
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#define PIC_SENS_CFG 0x1aa
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--
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2.39.2
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