experimental asus a88hm-e support

no auto-downloading or inserting of vga roms
and other files yet. i did this for someone one
irc who wanted an easier build

i deleted all other boards, just for this
branch. this branch *only* builds that one board.

Signed-off-by: Leah Rowe <leah@libreboot.org>

.gitignore

@@ -1,6 +1,7 @@
 *~
 *.o
 /lbmk.err.log
+/docs/
 /cbutils/
 /pciroms/
 /util/dell-flash-unlock/dell_flash_unlock

build

@@ -8,6 +8,9 @@
 [ "x${DEBUG+set}" = 'xset' ] && set -v
 set -u -e
 
+export LC_COLLATE=C
+export LC_ALL=C
+
 . "include/err.sh"
 . "include/option.sh"
 
@@ -40,7 +43,10 @@ main()
 {
 	xx_ id -u 1>/dev/null 2>/dev/null
 	[ $# -lt 1 ] && fail "Too few arguments. Try: ${0} help"
-	[ "${1}" = "dependencies" ] && xx_ install_packages $@ && lbmk_exit 0
+	if [ "${1}" = "dependencies" ]; then
+		xx_ install_packages $@
+		lbmk_exit 0
+	fi
 
 	initialise_command $@ && shift 1
 
@@ -56,9 +62,18 @@ initialise_command()
 {
 	[ "$(id -u)" != "0" ] || fail "this command as root is not permitted"
 
+	check_project
+
 	case "${1}" in
-	help) usage ${0} && lbmk_exit 0 ;;
-	list) items "${buildpath}" && lbmk_exit 0 ;;
+	help)
+		usage ${0}
+		lbmk_exit 0 ;;
+	list)
+		items "${buildpath}"
+		lbmk_exit 0 ;;
+	version)
+		mkversion
+		lbmk_exit 0 ;;
 	esac
 	option="${1}"
 }
@@ -91,7 +106,8 @@ git_init()
 
 	git init || fail "${PWD}: cannot initialise Git repository"
 	git add -A . || fail "${PWD}: cannot add files to Git repository"
-	git commit -m "${projectname} ${version}" --date "${cdate}" || \
+	git commit -m "${projectname} ${version}" --date "${cdate}" \
+	    --author="lbmk <lbmk@libreboot.org>" || \
 	    fail "${PWD}: can't commit ${projectname}/${version}, date ${cdate}"
 	git tag -a "${version}" -m "${projectname} ${version}" || \
 	    fail "${PWD}: cannot git-tag ${projectname}/${version}"
@@ -108,15 +124,26 @@ usage()
 {
 	progname=${0}
 	cat <<- EOF
+	$(mkversion)
+
 	USAGE:	${progname} <OPTION>
 
 	possible values for 'OPTION':
 	$(items "${buildpath}")
 
+	To know what ${projectname} version you're on, type:
+	${progname} version
+
 	Refer to ${projectname} documentation for more info.
 	EOF
 }
 
+mkversion()
+{
+	printf "revision: %s %s\n" "${projectname}" "${version}"
+	printf "revision date: %s\n" "$(date -Rud @${versiondate})"
+}
+
 lbmk_exit()
 {
 	tmp_cleanup || err "lbmk_exit: can't rm tmpdir upon exit $1: ${tmpdir}"

config/coreboot/asus_a88hm_e/config/normal

@@ -19,8 +19,7 @@ CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_UTIL_GENPARSER is not set
 CONFIG_OPTION_BACKEND_NONE=y
 # CONFIG_USE_OPTION_TABLE is not set
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_COMPRESS_RAMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -31,8 +30,8 @@ CONFIG_USE_BLOBS=y
 # CONFIG_UBSAN is not set
 CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
 # CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
+CONFIG_NO_STAGE_CACHE=y
+# CONFIG_CBMEM_STAGE_CACHE is not set
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
 # CONFIG_FW_CONFIG is not set
@@ -56,31 +55,33 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_ADLINK is not set
 # CONFIG_VENDOR_AMD is not set
 # CONFIG_VENDOR_AOPEN is not set
-CONFIG_VENDOR_APPLE=y
+# CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
+CONFIG_VENDOR_ASUS=y
+# CONFIG_VENDOR_BAP is not set
 # CONFIG_VENDOR_BIOSTAR is not set
 # CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
 # CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_ELMEX is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
 # CONFIG_VENDOR_GOOGLE is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
 # CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
+# CONFIG_VENDOR_JETWAY is not set
 # CONFIG_VENDOR_KONTRON is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
+# CONFIG_VENDOR_LIPPERT is not set
 # CONFIG_VENDOR_MSI is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
@@ -95,6 +96,7 @@ CONFIG_VENDOR_APPLE=y
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
 # CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SCALEWAY is not set
 # CONFIG_VENDOR_SIEMENS is not set
 # CONFIG_VENDOR_SIFIVE is not set
 # CONFIG_VENDOR_STARLABS is not set
@@ -103,66 +105,97 @@ CONFIG_VENDOR_APPLE=y
 # CONFIG_VENDOR_TI is not set
 # CONFIG_VENDOR_UP is not set
 CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="MacBook2,1"
+CONFIG_MAINBOARD_PART_NUMBER="A88XM-E"
 CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="apple/macbook21"
-CONFIG_VGA_BIOS_ID="8086,27a2"
+CONFIG_MAINBOARD_DIR="asus/a88xm-e"
+CONFIG_VGA_BIOS_ID="1002,9996"
 CONFIG_DIMM_MAX=4
 CONFIG_DIMM_SPD_SIZE=256
 CONFIG_FMDFILE=""
 # CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Apple"
-CONFIG_CBFS_SIZE=0x01000000
-CONFIG_MAX_CPUS=2
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_MAINBOARD_VENDOR="ASUS"
+CONFIG_CBFS_SIZE=0x00800000
+CONFIG_CONSOLE_SERIAL=y
+CONFIG_MAX_CPUS=4
+CONFIG_ONBOARD_VGA_IS_PRIMARY=y
 CONFIG_POST_DEVICE=y
 CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
+CONFIG_UART_FOR_CONSOLE=0
+CONFIG_EFS_SPI_READ_MODE=2
+CONFIG_EFS_SPI_SPEED=1
+CONFIG_EFS_SPI_MICRON_FLAG=0
+CONFIG_NORMAL_READ_SPI_SPEED=1
+CONFIG_ALT_SPI_SPEED=1
+CONFIG_TPM_SPI_SPEED=1
 # CONFIG_VBOOT is not set
+CONFIG_IRQ_SLOT_COUNT=11
+CONFIG_HW_MEM_HOLE_SIZEK=0x200000
+CONFIG_DEVICETREE="devicetree.cb"
+# CONFIG_HUDSON_LEGACY_FREE is not set
 CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_BOARD_APPLE_MACBOOK21=y
-# CONFIG_BOARD_APPLE_MACBOOK11 is not set
-# CONFIG_BOARD_APPLE_IMAC52 is not set
-# CONFIG_BOARD_APPLE_MACBOOKAIR4_2 is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Apple Inc."
+CONFIG_VGA_BIOS=y
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_BOARD_ASUS_A88XM_E=y
+# CONFIG_BOARD_ASUS_AM1I_A is not set
+# CONFIG_BOARD_ASUS_F2A85_M is not set
+# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set
+# CONFIG_BOARD_ASUS_F2A85_M_LE is not set
+# CONFIG_BOARD_ASUS_H61M_CS is not set
+# CONFIG_BOARD_ASUS_P8H61_M_LX is not set
+# CONFIG_BOARD_ASUS_P8H61_M_LX3_R2_0 is not set
+# CONFIG_BOARD_ASUS_P8H61_M_PRO is not set
+# CONFIG_BOARD_ASUS_P8H61_M_PRO_CM6630 is not set
+# CONFIG_BOARD_ASUS_MAXIMUS_IV_GENE_Z is not set
+# CONFIG_BOARD_ASUS_P2B is not set
+# CONFIG_BOARD_ASUS_P2B_D is not set
+# CONFIG_BOARD_ASUS_P2B_DS is not set
+# CONFIG_BOARD_ASUS_P2B_F is not set
+# CONFIG_BOARD_ASUS_P2B_LS is not set
+# CONFIG_BOARD_ASUS_P3B_F is not set
+# CONFIG_BOARD_ASUS_P5GC_MX is not set
+# CONFIG_BOARD_ASUS_P5QC is not set
+# CONFIG_BOARD_ASUS_P5Q_PRO is not set
+# CONFIG_BOARD_ASUS_P5QL_PRO is not set
+# CONFIG_BOARD_ASUS_P5Q_SE is not set
+# CONFIG_BOARD_ASUS_P5Q is not set
+# CONFIG_BOARD_ASUS_P5QL_EM is not set
+# CONFIG_BOARD_ASUS_P5QPL_AM is not set
+# CONFIG_BOARD_ASUS_P5G41T_M_LX is not set
+# CONFIG_BOARD_ASUS_P8C_WS is not set
+# CONFIG_BOARD_ASUS_P8H77_V is not set
+# CONFIG_BOARD_ASUS_P8Z77_M_PRO is not set
+# CONFIG_BOARD_ASUS_P8Z77_V_LX2 is not set
+# CONFIG_BOARD_ASUS_P8Z77_V is not set
+# CONFIG_BOARD_ASUS_P8Z77_M is not set
+# CONFIG_HUDSON_XHCI_FWM is not set
+# CONFIG_HUDSON_XHCI_ENABLE is not set
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefc0000
-CONFIG_DCACHE_RAM_SIZE=0x8000
+CONFIG_DCACHE_RAM_BASE=0x30000
+CONFIG_DCACHE_RAM_SIZE=0x10000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
+CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
+CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xF8000000
+CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
+CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_DRIVERS_INTEL_WIFI=y
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1"
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
+CONFIG_VGA_BIOS_FILE="../../../pciroms/pci1002,9996.rom"
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="A88XM-E"
 CONFIG_PS2K_EISAID="PNP0303"
 CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_D3COLD_SUPPORT=y
-# CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
+CONFIG_DRIVERS_UART_8250IO=y
+CONFIG_HEAP_SIZE=0xc0000
 CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_2048=y
+CONFIG_BOARD_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
@@ -170,24 +203,16 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_8192=y
 # CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
+CONFIG_COREBOOT_ROMSIZE_KB=8192
+CONFIG_ROM_SIZE=0x00800000
 # end of Mainboard
 
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
 #
 # Chipset
 #
@@ -195,110 +220,115 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y
 #
 # SoC
 #
+CONFIG_ARCH_ALL_STAGES_X86=y
 CONFIG_CHIPSET_DEVICETREE=""
 CONFIG_CBFS_MCACHE_SIZE=0x4000
 CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
+# CONFIG_VGA_BIOS_SECOND is not set
+CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d"
+CONFIG_BOTTOMIO_POSITION=0x80000000
 CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
+CONFIG_AHCI_ROM_ID="1022,7801"
 CONFIG_STACK_SIZE=0x2000
+CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
+# CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_TTYS0_BASE=0x3f8
+CONFIG_TTYS0_LCS=3
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_SOC_AMD_COMMON=y
+CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO=y
+CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM=y
 CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_INTEL_HAS_TOP_SWAP=y
-# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
-CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
+CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF=y
+# CONFIG_SOC_AMD_COMMON_BLOCK_SPI_DEBUG is not set
 
 #
 # CPU
 #
-CONFIG_CPU_INTEL_MODEL_6EX=y
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_SOCKET_M=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
+CONFIG_CPU_AMD_AGESA=y
+CONFIG_UDELAY_LAPIC_FIXED_FSB=200
+# CONFIG_ENABLE_MRC_CACHE is not set
+CONFIG_CPU_AMD_AGESA_FAMILY15_TN=y
+CONFIG_SSE2=y
+CONFIG_LEGACY_SMP_INIT=y
 CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
+CONFIG_UDELAY_LAPIC=y
+CONFIG_LAPIC_MONOTONIC_TIMER=y
+CONFIG_UNKNOWN_TSC_RATE=y
+CONFIG_TSC_SYNC_LFENCE=y
+CONFIG_LOGICAL_CPUS=y
+CONFIG_SMM_ASEG=y
+CONFIG_X86_AMD_FIXED_MTRRS=y
 CONFIG_SMP=y
 CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
 
 #
 # Northbridge
 #
-CONFIG_NORTHBRIDGE_INTEL_I945=y
-CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y
-CONFIG_I945_LVDS=y
+CONFIG_NORTHBRIDGE_AMD_AGESA=y
+CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN=y
 
 #
 # Southbridge
 #
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
+CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON=y
+CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y
+CONFIG_HUDSON_SATA_MODE=2
+
+#
+# AHCI
+#
+# CONFIG_HUDSON_AHCI_ROM is not set
+CONFIG_ACPI_ENABLE_THERMAL_ZONE=y
+# CONFIG_PCIEXP_HOTPLUG is not set
 CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
 CONFIG_RCBA_LENGTH=0x4000
 
 #
 # Super I/O
 #
+CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
+CONFIG_SUPERIO_ITE_ENV_CTRL=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG=y
+CONFIG_SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN=y
+CONFIG_SUPERIO_ITE_IT8728F=y
 
 #
 # Embedded Controllers
 #
-CONFIG_EC_ACPI=y
+
+#
+# AMD Platform Initialization
+#
+# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set
+CONFIG_CPU_AMD_AGESA_OPENSOURCE=y
+CONFIG_IDS_OPTIONS_HOOKED_UP=y
+CONFIG_IDS_ENABLED=y
+
+#
+# Warning: IDS options may not work. Enable at your own risk!
+#
+# CONFIG_IDS_CONTROL_ENABLED is not set
+# CONFIG_IDS_PERF_ANALYSIS is not set
+# CONFIG_IDS_TRACING_ENABLED is not set
+CONFIG_CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC=y
+# CONFIG_CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 is not set
+# CONFIG_CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 is not set
+# CONFIG_CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM is not set
+# CONFIG_AGESA_EXTRA_TIMESTAMPS is not set
+# end of AMD Platform Initialization
+
 CONFIG_ARCH_X86=y
 CONFIG_ARCH_BOOTBLOCK_X86_32=y
 CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -306,45 +336,29 @@ CONFIG_ARCH_ROMSTAGE_X86_32=y
 CONFIG_ARCH_POSTCAR_X86_32=y
 CONFIG_ARCH_RAMSTAGE_X86_32=y
 CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_NUM_IPI_STARTS=2
 CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
 CONFIG_BOOTBLOCK_SIMPLE=y
 # CONFIG_BOOTBLOCK_NORMAL is not set
 CONFIG_COLLECT_TIMESTAMPS_TSC=y
 CONFIG_HAVE_CF9_RESET=y
+CONFIG_HAVE_CF9_RESET_PREPARE=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
 # end of Chipset
 
 #
 # Devices
 #
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
-CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
+CONFIG_VGA_ROM_RUN_DEFAULT=y
 # CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
+CONFIG_NO_GFX_INIT=y
 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -352,19 +366,13 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
 # CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
 # CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-# CONFIG_INTEL_GMA_ADD_VBT is not set
+# CONFIG_VGA_BIOS_DGPU is not set
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR2=y
+CONFIG_RESOURCE_ALLOCATOR_V3=y
 # end of Devices
 
 #
@@ -372,7 +380,8 @@ CONFIG_USE_DDR2=y
 #
 CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
 # CONFIG_ELOG is not set
-# CONFIG_SMMSTORE is not set
+CONFIG_CACHE_MRC_SETTINGS=y
+# CONFIG_MRC_SETTINGS_PROTECT is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
@@ -381,31 +390,31 @@ CONFIG_SPI_FLASH_ADESTO=y
 CONFIG_SPI_FLASH_AMIC=y
 CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_DRIVERS_UART=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
+CONFIG_DRIVERS_AMD_PI=y
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
 # CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_EDID=y
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
+CONFIG_INTEL_GMA_OPREGION_2_0=y
 # CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
 CONFIG_USE_PC_CMOS_ALTCENTURY=y
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
+CONFIG_DRIVERS_WIFI_GENERIC=y
 # end of Generic Drivers
 
 #
@@ -427,10 +436,6 @@ CONFIG_VGA=y
 # Trusted Platform Module
 #
 CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
 # end of Trusted Platform Module
 
 #
@@ -440,24 +445,16 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
 CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
 # end of Memory initialization
 
-# CONFIG_STM is not set
 CONFIG_BOOTMEDIA_LOCK_NONE=y
 # CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
 # CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
 # end of Security
 
 CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
 CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -465,12 +462,27 @@ CONFIG_HEAP_SIZE=0x100000
 CONFIG_BOOTBLOCK_CONSOLE=y
 CONFIG_POSTCAR_CONSOLE=y
 CONFIG_SQUELCH_EARLY_SMP=y
+
+#
+# I/O mapped, 8250-compatible
+#
+
+#
+# Serial port base address = 0x3f8
+#
+# CONFIG_CONSOLE_SERIAL_921600 is not set
+# CONFIG_CONSOLE_SERIAL_460800 is not set
+# CONFIG_CONSOLE_SERIAL_230400 is not set
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+CONFIG_TTYS0_BAUD=115200
 # CONFIG_SPKMODEM is not set
 # CONFIG_CONSOLE_NE2K is not set
 CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
 # CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
@@ -496,15 +508,16 @@ CONFIG_RESUME_PATH_SAME_AS_BOOT=y
 CONFIG_HAVE_MONOTONIC_TIMER=y
 CONFIG_HAVE_OPTION_TABLE=y
 CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
+CONFIG_GFXUMA=y
 CONFIG_HAVE_MP_TABLE=y
+CONFIG_HAVE_PIRQ_TABLE=y
 
 #
 # System tables
 #
 CONFIG_GENERATE_MP_TABLE=y
+CONFIG_GENERATE_PIRQ_TABLE=y
 CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
 CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # end of System tables
 
@@ -512,6 +525,32 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # Payload
 #
 CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_BOOTBOOT is not set
+# CONFIG_PAYLOAD_FILO is not set
+# CONFIG_PAYLOAD_GRUB2 is not set
+# CONFIG_PAYLOAD_SEAGRUB is not set
+# CONFIG_PAYLOAD_LINUXBOOT is not set
+# CONFIG_PAYLOAD_SEABIOS is not set
+# CONFIG_PAYLOAD_UBOOT is not set
+# CONFIG_PAYLOAD_YABITS is not set
+# CONFIG_PAYLOAD_EDK2 is not set
+# CONFIG_PAYLOAD_LINUX is not set
+CONFIG_PAYLOAD_OPTIONS=""
+# CONFIG_PXE is not set
+# CONFIG_COMPRESS_SECONDARY_PAYLOAD is not set
+
+#
+# Secondary Payloads
+#
+# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
+# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set
+# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
+# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
+# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set
+# CONFIG_TINT_SECONDARY_PAYLOAD is not set
+# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set
+# end of Secondary Payloads
 # end of Payload
 
 #
@@ -530,18 +569,15 @@ CONFIG_PAYLOAD_NONE=y
 #
 # General Debug Settings
 #
+# CONFIG_GDB_STUB is not set
 # CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_PIRQ is not set
 # CONFIG_DEBUG_MALLOC is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set
 # CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
 # end of Debugging
 
 CONFIG_DECOMPRESS_OFAST=y

config/coreboot/asus_a88hm_e/target.cfg

@@ -3,6 +3,6 @@ romtype="normal"
 arch="x86_64"
 payload_seabios="y"
 payload_seabios_withgrub="y"
+payload_seabios_grubonly="y"
 payload_memtest="y"
 grub_scan_disk="ahci"
-grub_timeout=10

config/coreboot/d510mo/config/libgfxinit_txtmode

@@ -1,592 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-CONFIG_VENDOR_INTEL=y
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="D510MO"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="intel/d510mo"
-CONFIG_VGA_BIOS_ID="8086,a001"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Intel"
-CONFIG_CBFS_SIZE=0x00100000
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefc0000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_BOARD_INTEL_ADLRVP_P is not set
-# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
-# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
-# CONFIG_BOARD_INTEL_ADLRVP_M is not set
-# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
-# CONFIG_BOARD_INTEL_ADLRVP_N is not set
-# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
-# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
-# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
-# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
-# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
-# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
-# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
-# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
-
-#
-# Coffeelake RVP
-#
-# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
-# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
-# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
-# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
-# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
-CONFIG_BOARD_INTEL_D510MO=y
-# CONFIG_BOARD_INTEL_D945GCLF is not set
-# CONFIG_BOARD_INTEL_DCP847SKE is not set
-# CONFIG_BOARD_INTEL_DG41WV is not set
-# CONFIG_BOARD_INTEL_DG43GT is not set
-# CONFIG_BOARD_INTEL_DQ67SW is not set
-# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
-# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
-# CONFIG_BOARD_INTEL_GLKRVP is not set
-# CONFIG_BOARD_INTEL_HARCUVAR is not set
-# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
-# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
-# CONFIG_BOARD_INTEL_KBLRVP3 is not set
-# CONFIG_BOARD_INTEL_KBLRVP7 is not set
-# CONFIG_BOARD_INTEL_KBLRVP8 is not set
-# CONFIG_BOARD_INTEL_KBLRVP11 is not set
-# CONFIG_BOARD_INTEL_KUNIMITSU is not set
-# CONFIG_BOARD_INTEL_LEAFHILL is not set
-# CONFIG_BOARD_INTEL_MINNOW3 is not set
-# CONFIG_BOARD_INTEL_MTLRVP_P is not set
-# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
-# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
-# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
-# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
-# CONFIG_BOARD_INTEL_STRAGO is not set
-# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
-# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
-# CONFIG_BOARD_INTEL_WTM2 is not set
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
-CONFIG_PCIEXP_HOTPLUG_BUSES=32
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_D3COLD_SUPPORT=y
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_1024=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_1024=y
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=1024
-CONFIG_ROM_SIZE=0x00100000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x80000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_INTEL_HAS_TOP_SWAP=y
-# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
-CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_106CX=y
-CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_CPU_HAS_L2_ENABLE_MSR=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM=y
-CONFIG_SUPERIO_WINBOND_W83627THG=y
-
-#
-# Embedded Controllers
-#
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
-CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_EDID=y
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_NULL=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/d510mo/target.cfg

@@ -1,9 +0,0 @@
-tree="default"
-romtype="normal"
-arch="x86_64"
-payload_grub="n"
-payload_grub_withseabios="n"
-payload_seabios="y"
-payload_memtest="y"
-microcode_required="n"
-vendorfiles="n"

config/coreboot/d510mo_16mb/config/libgfxinit_txtmode

@@ -1,592 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-CONFIG_VENDOR_INTEL=y
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="D510MO"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="intel/d510mo"
-CONFIG_VGA_BIOS_ID="8086,a001"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Intel"
-CONFIG_CBFS_SIZE=0x01000000
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefc0000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_BOARD_INTEL_ADLRVP_P is not set
-# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
-# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
-# CONFIG_BOARD_INTEL_ADLRVP_M is not set
-# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
-# CONFIG_BOARD_INTEL_ADLRVP_N is not set
-# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
-# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
-# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
-# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
-# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
-# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
-# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
-# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
-
-#
-# Coffeelake RVP
-#
-# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
-# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
-# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
-# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
-# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
-CONFIG_BOARD_INTEL_D510MO=y
-# CONFIG_BOARD_INTEL_D945GCLF is not set
-# CONFIG_BOARD_INTEL_DCP847SKE is not set
-# CONFIG_BOARD_INTEL_DG41WV is not set
-# CONFIG_BOARD_INTEL_DG43GT is not set
-# CONFIG_BOARD_INTEL_DQ67SW is not set
-# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
-# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
-# CONFIG_BOARD_INTEL_GLKRVP is not set
-# CONFIG_BOARD_INTEL_HARCUVAR is not set
-# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
-# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
-# CONFIG_BOARD_INTEL_KBLRVP3 is not set
-# CONFIG_BOARD_INTEL_KBLRVP7 is not set
-# CONFIG_BOARD_INTEL_KBLRVP8 is not set
-# CONFIG_BOARD_INTEL_KBLRVP11 is not set
-# CONFIG_BOARD_INTEL_KUNIMITSU is not set
-# CONFIG_BOARD_INTEL_LEAFHILL is not set
-# CONFIG_BOARD_INTEL_MINNOW3 is not set
-# CONFIG_BOARD_INTEL_MTLRVP_P is not set
-# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
-# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
-# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
-# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
-# CONFIG_BOARD_INTEL_STRAGO is not set
-# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
-# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
-# CONFIG_BOARD_INTEL_WTM2 is not set
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
-CONFIG_PCIEXP_HOTPLUG_BUSES=32
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_D3COLD_SUPPORT=y
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_1024=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x80000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_INTEL_HAS_TOP_SWAP=y
-# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
-CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_106CX=y
-CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_CPU_HAS_L2_ENABLE_MSR=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM=y
-CONFIG_SUPERIO_WINBOND_W83627THG=y
-
-#
-# Embedded Controllers
-#
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
-CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_EDID=y
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_NULL=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/d510mo_16mb/target.cfg

@@ -1,8 +0,0 @@
-tree="default"
-romtype="normal"
-arch="x86_64"
-payload_seabios="y"
-payload_seabios_withgrub="y"
-payload_memtest="y"
-microcode_required="n"
-vendorfiles="n"

config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch

@@ -1,23 +0,0 @@
-From e8f5f6c372152c7deddd3080954d0f4fdd39ae2b Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@retroboot.org>
-Date: Fri, 19 Mar 2021 05:54:58 +0000
-Subject: [PATCH 01/22] apple/macbook21: Set default VRAM to 64MiB instead of
- 8MiB
-
----
- src/mainboard/apple/macbook21/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
-index cf1bc4566e..dc0df3b6d6 100644
---- a/src/mainboard/apple/macbook21/cmos.default
-+++ b/src/mainboard/apple/macbook21/cmos.default
-@@ -5,4 +5,4 @@ boot_devices=''
- boot_default=0x40
- cmos_defaults_loaded=Yes
- lpt=Enable
--gfx_uma_size=8M
-+gfx_uma_size=64M
--- 
-2.39.2
-

config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch

@@ -1,68 +0,0 @@
-From fdd756a8217548981a1eb62e504cc37371c9fd51 Mon Sep 17 00:00:00 2001
-From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
-Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 02/22] add c3 and clockgen to apple/macbook21
-
----
- src/mainboard/apple/macbook21/Kconfig       |  1 +
- src/mainboard/apple/macbook21/cstates.c     | 13 +++++++++++++
- src/mainboard/apple/macbook21/devicetree.cb |  6 ++++++
- 3 files changed, 20 insertions(+)
-
-diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
-index 5f5ffde588..27377b737c 100644
---- a/src/mainboard/apple/macbook21/Kconfig
-+++ b/src/mainboard/apple/macbook21/Kconfig
-@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
- 	select HAVE_ACPI_TABLES
- 	select HAVE_ACPI_RESUME
- 	select I945_LVDS
-+	select DRIVERS_I2C_CK505
- 
- config MAINBOARD_DIR
- 	default "apple/macbook21"
-diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c
-index 13d06f0839..88b8669c61 100644
---- a/src/mainboard/apple/macbook21/cstates.c
-+++ b/src/mainboard/apple/macbook21/cstates.c
-@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = {
- 			.addrh = 0,
- 		}
- 	},
-+	{
-+		.ctype = 3,
-+		.latency = 17,
-+		.power = 250,
-+		.resource = {
-+			.space_id = ACPI_ADDRESS_SPACE_FIXED,
-+			.bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
-+			.bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
-+			.access_size = ACPI_ACCESS_SIZE_UNDEFINED,
-+			.addrl = 0x20,
-+			.addrh = 0,
-+		}
-+	},
- };
- 
- int get_cst_entries(const acpi_cstate_t **entries)
-diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
-index fd86e939b9..263fbabcd1 100644
---- a/src/mainboard/apple/macbook21/devicetree.cb
-+++ b/src/mainboard/apple/macbook21/devicetree.cb
-@@ -100,7 +100,13 @@ chip northbridge/intel/i945
- 			end
- 			device pci 1f.3 on # SMBUS
- 				subsystemid 0x8086 0x7270
-+				chip drivers/i2c/ck505
-+					register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }"
-+					register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }"
-+					device i2c 69 on end
-+				end
- 			end
-+
- 		end
- 	end
- end
--- 
-2.39.2
-

config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch

@@ -1,23 +0,0 @@
-From c8332a8bac4986afec6c639f55c5876f83e50b76 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@osboot.org>
-Date: Sun, 3 Jan 2021 03:34:01 +0000
-Subject: [PATCH 03/22] lenovo/x60: 64MiB Video RAM changed to default
- (previously it was 8MiB)
-
----
- src/mainboard/lenovo/x60/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
-index 5c3576d1f3..88170a1aab 100644
---- a/src/mainboard/lenovo/x60/cmos.default
-+++ b/src/mainboard/lenovo/x60/cmos.default
-@@ -15,4 +15,4 @@ trackpoint=Enable
- sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
--gfx_uma_size=8M
-+gfx_uma_size=64M
--- 
-2.39.2
-

config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch

@@ -1,22 +0,0 @@
-From 2e3ad35c24a86cb3109f4e5139b9ffba931eb80b Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@osboot.org>
-Date: Mon, 22 Feb 2021 22:16:59 +0000
-Subject: [PATCH 04/22] lenovo/t60: make 64MiB VRAM the default in cmos.default
-
----
- src/mainboard/lenovo/t60/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
-index af865f16da..7f03157df7 100644
---- a/src/mainboard/lenovo/t60/cmos.default
-+++ b/src/mainboard/lenovo/t60/cmos.default
-@@ -15,4 +15,4 @@ trackpoint=Enable
- sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
--gfx_uma_size=8M
-+gfx_uma_size=64M
--- 
-2.39.2
-

config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch

@@ -1,23 +0,0 @@
-From 5fc03fbf8c7fa30588dab93c76b5532ce03b1610 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Fri, 14 May 2021 13:10:33 +0100
-Subject: [PATCH 05/22] lenovo/t400: set VRAM to 256MiB VRAM by default
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/mainboard/lenovo/t400/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
-index a326e315b1..b907a3e2df 100644
---- a/src/mainboard/lenovo/t400/cmos.default
-+++ b/src/mainboard/lenovo/t400/cmos.default
-@@ -13,4 +13,4 @@ power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
- hybrid_graphics_mode=Integrated Only
--gfx_uma_size=32M
-+gfx_uma_size=256M
--- 
-2.39.2
-

config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch

@@ -1,23 +0,0 @@
-From 93f607fed477b3e63b7929808937436ac2898b34 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Fri, 14 May 2021 13:11:59 +0100
-Subject: [PATCH 06/22] lenovo/x200: set VRAM to 256MiB by default
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/mainboard/lenovo/x200/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
-index bb4323836e..458b3f19c5 100644
---- a/src/mainboard/lenovo/x200/cmos.default
-+++ b/src/mainboard/lenovo/x200/cmos.default
-@@ -12,4 +12,4 @@ sticky_fn=Disable
- power_management_beeps=Enable
- low_battery_beep=Enable
- sata_mode=AHCI
--gfx_uma_size=32M
-+gfx_uma_size=256M
--- 
-2.39.2
-

config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch

@@ -1,23 +0,0 @@
-From 9faa780b2ac45bc1bf61aa252364ee3158c4cb10 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Fri, 14 May 2021 13:18:26 +0100
-Subject: [PATCH 07/22] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
-index 8372032119..bedad54d2a 100644
---- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
-+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
-@@ -2,4 +2,4 @@ boot_option=Fallback
- debug_level=Debug
- power_on_after_fail=Enable
- nmi=Enable
--gfx_uma_size=64M
-+gfx_uma_size=256M
--- 
-2.39.2
-

config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch

@@ -1,23 +0,0 @@
-From f1c59cd67446303a5cdf9107461247a63f894de3 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Fri, 14 May 2021 13:21:39 +0100
-Subject: [PATCH 08/22] acer/g43t-am3: set VRAM to 256MiB by default
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/mainboard/acer/g43t-am3/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
-index 706f5dd551..e8b45ea22c 100644
---- a/src/mainboard/acer/g43t-am3/cmos.default
-+++ b/src/mainboard/acer/g43t-am3/cmos.default
-@@ -3,4 +3,4 @@ debug_level=Debug
- power_on_after_fail=Disable
- nmi=Enable
- sata_mode=AHCI
--gfx_uma_size=64M
-+gfx_uma_size=256M
--- 
-2.39.2
-

config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch

@@ -1,34 +0,0 @@
-From 75858ba200a2a5835bca0af9b5f508a52ed978de Mon Sep 17 00:00:00 2001
-From: persmule <persmule@gmail.com>
-Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 09/22] lenovo/t400: Enable all SATA ports
-
-There are 2 SATA ports on the chassis of t400(s), but at least one dock for
-t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
-chassis, and another one on its dock.
-
-They have to be unmasked via device tree to use.
-
-This patch unmasked all SATA ports found within t400s with factory firmware.
----
- src/mainboard/lenovo/t400/devicetree.cb | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
-index 259c3e1b21..3d007533a4 100644
---- a/src/mainboard/lenovo/t400/devicetree.cb
-+++ b/src/mainboard/lenovo/t400/devicetree.cb
-@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
- 			register "gpe0_en" = "0x01000000"
- 			register "gpi1_routing"  = "2"
- 
--			# Set AHCI mode, enable ports 1 and 2.
--			register "sata_port_map"		= "0x03"
-+			# Set AHCI mode, enable ports 1, 2, 5 and 6.
-+			register "sata_port_map"		= "0x33"
- 			register "sata_clock_request"		= "0"
- 			register "sata_traffic_monitor"		= "0"
- 
--- 
-2.39.2
-

config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch

@@ -1,22 +0,0 @@
-From 2c103a71a37eb4db9d33928b2371a682ca04e65f Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 20 Dec 2021 01:29:31 +0000
-Subject: [PATCH 10/22] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
- default
-
----
- src/mainboard/lenovo/x230/cmos.default | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
-index 7314066c2b..2e315d4521 100644
---- a/src/mainboard/lenovo/x230/cmos.default
-+++ b/src/mainboard/lenovo/x230/cmos.default
-@@ -16,3 +16,4 @@ backlight=Both
- usb_always_on=Disable
- f1_to_f12_as_primary=Enable
- me_state=Normal
-+gfx_uma_size=224M
--- 
-2.39.2
-

config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch

@@ -1,38 +0,0 @@
-From 040f15039fa59d70cd54b8fff5d947e155666aa1 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 11/22] lenovo/x230: set me_state=Disabled in cmos.default
-
-I only recently found out about this. It's possible to use me_cleaner to
-do the same thing, but some people might just flash coreboot and not do
-anything with the ME region
-
-With this change, the ME is set to disabled. It's my understanding that this
-will accomplish more or less the same thing as me_cleaner, without actually
-using that. Of course, I still recommend using me_cleaner
-
-I saw this when I audited coreboot's git history, and saw this:
-
-commit 833e9bad4762e0dca6c867d3a18dbaf6d5166be8
-Author: Evgeny Zinoviev <me@ch1p.io>
-Date:   Thu Nov 21 21:47:31 2019 +0300
-
-    sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode
----
- src/mainboard/lenovo/x230/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
-index 2e315d4521..3585cbd58b 100644
---- a/src/mainboard/lenovo/x230/cmos.default
-+++ b/src/mainboard/lenovo/x230/cmos.default
-@@ -15,5 +15,5 @@ trackpoint=Enable
- backlight=Both
- usb_always_on=Disable
- f1_to_f12_as_primary=Enable
--me_state=Normal
-+me_state=Disabled
- gfx_uma_size=224M
--- 
-2.39.2
-

config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch

@@ -1,122 +0,0 @@
-From 81febff42c66bd53e44176f14b651339b503a9f3 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 12/22] set me_state=Disabled on all cmos.default files!
-
-yeah. why the hell isn't this the default
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/mainboard/lenovo/l520/cmos.default         | 2 +-
- src/mainboard/lenovo/t420/cmos.default         | 2 +-
- src/mainboard/lenovo/t420s/cmos.default        | 2 +-
- src/mainboard/lenovo/t430/cmos.default         | 2 +-
- src/mainboard/lenovo/t430s/cmos.default        | 2 +-
- src/mainboard/lenovo/t520/cmos.default         | 2 +-
- src/mainboard/lenovo/t530/cmos.default         | 2 +-
- src/mainboard/lenovo/x220/cmos.default         | 2 +-
- src/mainboard/protectli/vault_cml/cmos.default | 2 +-
- src/mainboard/system76/tgl-u/cmos.default      | 2 +-
- 10 files changed, 10 insertions(+), 10 deletions(-)
-
-diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
-index 681c40e78b..57cdcf9162 100644
---- a/src/mainboard/lenovo/l520/cmos.default
-+++ b/src/mainboard/lenovo/l520/cmos.default
-@@ -14,4 +14,4 @@ sticky_fn=Disable
- trackpoint=Enable
- backlight=Both
- usb_always_on=Disable
--me_state=Normal
-+me_state=Disabled
-diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
-index 8244071b8a..c011867916 100644
---- a/src/mainboard/lenovo/t420/cmos.default
-+++ b/src/mainboard/lenovo/t420/cmos.default
-@@ -14,4 +14,4 @@ sticky_fn=Disable
- trackpoint=Enable
- hybrid_graphics_mode=Integrated Only
- usb_always_on=Disable
--me_state=Normal
-+me_state=Disabled
-diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
-index 8244071b8a..c011867916 100644
---- a/src/mainboard/lenovo/t420s/cmos.default
-+++ b/src/mainboard/lenovo/t420s/cmos.default
-@@ -14,4 +14,4 @@ sticky_fn=Disable
- trackpoint=Enable
- hybrid_graphics_mode=Integrated Only
- usb_always_on=Disable
--me_state=Normal
-+me_state=Disabled
-diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
-index 26795fe5cf..55e1e6c04e 100644
---- a/src/mainboard/lenovo/t430/cmos.default
-+++ b/src/mainboard/lenovo/t430/cmos.default
-@@ -15,4 +15,4 @@ trackpoint=Enable
- backlight=Both
- usb_always_on=Disable
- hybrid_graphics_mode=Integrated Only
--me_state=Normal
-+me_state=Disabled
-diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
-index 52dbf70377..b16800ca9e 100644
---- a/src/mainboard/lenovo/t430s/cmos.default
-+++ b/src/mainboard/lenovo/t430s/cmos.default
-@@ -16,4 +16,4 @@ backlight=Both
- enable_dual_graphics=Disable
- usb_always_on=Disable
- f1_to_f12_as_primary=Enable
--me_state=Normal
-+me_state=Disabled
-diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
-index cf79b391e2..b66f7034dc 100644
---- a/src/mainboard/lenovo/t520/cmos.default
-+++ b/src/mainboard/lenovo/t520/cmos.default
-@@ -15,4 +15,4 @@ trackpoint=Enable
- backlight=Both
- hybrid_graphics_mode=Integrated Only
- usb_always_on=Disable
--me_state=Normal
-+me_state=Disabled
-diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
-index cf79b391e2..b66f7034dc 100644
---- a/src/mainboard/lenovo/t530/cmos.default
-+++ b/src/mainboard/lenovo/t530/cmos.default
-@@ -15,4 +15,4 @@ trackpoint=Enable
- backlight=Both
- hybrid_graphics_mode=Integrated Only
- usb_always_on=Disable
--me_state=Normal
-+me_state=Disabled
-diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
-index 6d1d57a795..52f303dfdb 100644
---- a/src/mainboard/lenovo/x220/cmos.default
-+++ b/src/mainboard/lenovo/x220/cmos.default
-@@ -13,4 +13,4 @@ usb_always_on=Disable
- fn_ctrl_swap=Disable
- sticky_fn=Disable
- trackpoint=Enable
--me_state=Normal
-+me_state=Disabled
-diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
-index 62715bc6ba..129b5fd121 100644
---- a/src/mainboard/protectli/vault_cml/cmos.default
-+++ b/src/mainboard/protectli/vault_cml/cmos.default
-@@ -1,3 +1,3 @@
- boot_option=Fallback
- debug_level=Debug
--me_state=Enable
-+me_state=Disabled
-diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
-index 62715bc6ba..129b5fd121 100644
---- a/src/mainboard/system76/tgl-u/cmos.default
-+++ b/src/mainboard/system76/tgl-u/cmos.default
-@@ -1,3 +1,3 @@
- boot_option=Fallback
- debug_level=Debug
--me_state=Enable
-+me_state=Disabled
--- 
-2.39.2
-

config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch

@@ -1,198 +0,0 @@
-From c73269315626678c191ea494338581abdc417f21 Mon Sep 17 00:00:00 2001
-From: Alexander Couzens <lynxis@fe80.eu>
-Date: Sat, 19 Mar 2022 13:42:33 +0000
-Subject: [PATCH 13/22] lenovo/x230: introduce FHD variant
-
-There is a modification for the x230 which uses the 2nd DP from the dock
-as the integrated panel's connection, which allows using a custom eDP
-panel instead of the stock LVDS display.
-
-There are several adapter boards present on the market and all of them
-uses the same method of enabling the custom eDP panel.
-
-To make this work with coreboot, the internal LVDS connector should be
-disabled in libgfxinit. The VBT has been modified as well, which allows
-brightness controls to work out of the box.
-
-The modifications done to the VBT are:
-- Remove the LVDS port entry.
-- Move the DP-3 (which is the 2nd DP on the dock) entry to the first
-  position on the list.
-- Set the DP-3 as internally connected.
-
-This has been reported to work with the following panels:
-- LP125WF2-SPB4 (1920*1080, 12.5")
-- LQ125T1JW02 (2560*1440, 12.5")
-- LQ133M1JW21 (1920*1080, 13.3")
-- LTN133HL10-201 (1920*1080, 13.3")
-- B133HAN04.6 (1920*1080, 13.3")
-- B133QAN02.0 (2560*1600, 13.3")
-
-Other eDP panels not on this list should work as well.
-
-Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0
-Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
-Signed-off-by: Felix Singer <felixsinger@posteo.net>
----
- src/mainboard/lenovo/x230/Kconfig             |  15 ++++++++-----
- src/mainboard/lenovo/x230/Kconfig.name        |   3 +++
- src/mainboard/lenovo/x230/Makefile.inc        |   5 +++++
- .../lenovo/x230/variants/x230_edp/data.vbt    | Bin 0 -> 4281 bytes
- .../x230/variants/x230_edp/gma-mainboard.ads  |  21 ++++++++++++++++++
- 5 files changed, 38 insertions(+), 6 deletions(-)
- create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
- create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
-
-diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
-index 279095629b..acfd0ed561 100644
---- a/src/mainboard/lenovo/x230/Kconfig
-+++ b/src/mainboard/lenovo/x230/Kconfig
-@@ -1,4 +1,4 @@
--if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S
-+if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
- 
- config BOARD_SPECIFIC_OPTIONS
- 	def_bool y
-@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
- 	select H8_HAS_BAT_THRESHOLDS_IMPL
- 	select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S
- 	select NO_UART_ON_SUPERIO
--	select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
-+	select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
- 	select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S
- 	select HAVE_ACPI_TABLES
- 	select HAVE_OPTION_TABLE
-@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
- 	select INTEL_INT15
- 	select DRIVERS_RICOH_RCE822
- 	select MEMORY_MAPPED_TPM
--	select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
-+	select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
- 	select MAINBOARD_HAS_LIBGFXINIT
- 	select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
- 	select INTEL_GMA_HAVE_VBT
-@@ -47,17 +47,20 @@ config MAINBOARD_DIR
- 	default "lenovo/x230"
- 
- config VARIANT_DIR
--	default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
-+	default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
- 	default "x230s" if BOARD_LENOVO_X230S
- 
- config MAINBOARD_PART_NUMBER
--	default "ThinkPad X230" if BOARD_LENOVO_X230
-+	default "ThinkPad X230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230_EDP
- 	default "ThinkPad X230t" if BOARD_LENOVO_X230T
- 	default "ThinkPad X230s" if BOARD_LENOVO_X230S
- 
- config OVERRIDE_DEVICETREE
- 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
- 
-+config INTEL_GMA_VBT_FILE
-+	default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
-+
- config USBDEBUG_HCD_INDEX
- 	int
- 	default 2
-@@ -79,4 +82,4 @@ config PS2M_EISAID
- config THINKPADEC_HKEY_EISAID
- 	default "LEN0068"
- 
--endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ||  BOARD_LENOVO_X230S
-+endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ||  BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
-diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name
-index 1a01436879..e7290a12dd 100644
---- a/src/mainboard/lenovo/x230/Kconfig.name
-+++ b/src/mainboard/lenovo/x230/Kconfig.name
-@@ -6,3 +6,6 @@ config BOARD_LENOVO_X230T
- 
- config BOARD_LENOVO_X230S
- 	bool "ThinkPad X230s"
-+
-+config BOARD_LENOVO_X230_EDP
-+	bool "ThinkPad X230 eDP Mod (2K/FHD)"
-diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc
-index 8e801f145d..6e6f9f90b9 100644
---- a/src/mainboard/lenovo/x230/Makefile.inc
-+++ b/src/mainboard/lenovo/x230/Makefile.inc
-@@ -5,4 +5,9 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
- romstage-y += variants/$(VARIANT_DIR)/early_init.c
- romstage-y += variants/$(VARIANT_DIR)/gpio.c
- ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
-+
-+ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y)
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads
-+else
- ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
-+endif
-diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt b/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
-GIT binary patch
-literal 4281
-zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^
-zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
-zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
-zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
-zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
-zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
-z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
-zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
-z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
-z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
-zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT
-zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
-z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}(
-z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg
-zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW>
-zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn
-zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L
-zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy;
-z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY
-zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
-zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
-zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
-z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
-zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
-zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
-zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
-z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
-zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
-zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH
-z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
-zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
-p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
-new file mode 100644
-index 0000000000..f7cf0bc264
---- /dev/null
-+++ b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
-@@ -0,0 +1,21 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (DP1,
-+      DP2,
-+      DP3,
-+      HDMI1,
-+      HDMI2,
-+      HDMI3,
-+      Analog,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
--- 
-2.39.2
-

config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch

@@ -1,25 +0,0 @@
-From c32229e3f82c00abb2bee4d0f7ddf33d4c7a04dc Mon Sep 17 00:00:00 2001
-From: Alexei Sorokin <sor.alexei@meowr.ru>
-Date: Sun, 27 Nov 2022 18:36:26 +0300
-Subject: [PATCH 14/22] lenovo/x230: fix the data.vbt path for the EDP variant
-
----
- src/mainboard/lenovo/x230/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
-index acfd0ed561..34108c3c04 100644
---- a/src/mainboard/lenovo/x230/Kconfig
-+++ b/src/mainboard/lenovo/x230/Kconfig
-@@ -59,7 +59,7 @@ config OVERRIDE_DEVICETREE
- 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
- 
- config INTEL_GMA_VBT_FILE
--	default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
-+       default "src/mainboard/\$(MAINBOARDDIR)/variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
- 
- config USBDEBUG_HCD_INDEX
- 	int
--- 
-2.39.2
-

config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch

@@ -1,205 +0,0 @@
-From 38c76afbea4abfed2976bfbe10977e41f21665b0 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 15/22] util/ifdtool: add --nuke flag (all 0xFF on region)
-
-When this option is used, the region's contents are overwritten
-with all ones (0xFF).
-
-Example:
-
-./ifdtool --nuke gbe coreboot.rom
-./ifdtool --nuke bios coreboot.com
-./ifdtool --nuke me coreboot.com
-
-Rebased since the last revision update in lbmk.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
- 1 file changed, 83 insertions(+), 31 deletions(-)
-
-diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index ddbc0fb91b..7af9235ae3 100644
---- a/util/ifdtool/ifdtool.c
-+++ b/util/ifdtool/ifdtool.c
-@@ -1847,6 +1847,7 @@ static void print_usage(const char *name)
- 	       "                                         wbg    - Wellsburg\n"
- 	       "   -S | --setpchstrap                    Write a PCH strap\n"
- 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
-+	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
- 	       "   -v | --version:                       print the version\n"
- 	       "   -h | --help:                          print this help\n\n"
- 	       "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
-@@ -1854,6 +1855,60 @@ static void print_usage(const char *name)
- 	       "\n");
- }
- 
-+static int
-+get_region_type_string(const char *region_type_string)
-+{
-+	if (!strcasecmp("Descriptor", region_type_string))
-+		return 0;
-+	else if (!strcasecmp("BIOS", region_type_string))
-+		return 1;
-+	else if (!strcasecmp("ME", region_type_string))
-+		return 2;
-+	else if (!strcasecmp("GbE", region_type_string))
-+		return 3;
-+	else if (!strcasecmp("Platform Data", region_type_string))
-+		return 4;
-+	else if (!strcasecmp("Device Exp1", region_type_string))
-+		return 5;
-+	else if (!strcasecmp("Secondary BIOS", region_type_string))
-+		return 6;
-+	else if (!strcasecmp("Reserved", region_type_string))
-+		return 7;
-+	else if (!strcasecmp("EC", region_type_string))
-+		return 8;
-+	else if (!strcasecmp("Device Exp2", region_type_string))
-+		return 9;
-+	else if (!strcasecmp("IE", region_type_string))
-+		return 10;
-+	else if (!strcasecmp("10GbE_0", region_type_string))
-+		return 11;
-+	else if (!strcasecmp("10GbE_1", region_type_string))
-+		return 12;
-+	else if (!strcasecmp("PTT", region_type_string))
-+		return 15;
-+	return -1;
-+}
-+
-+static void
-+nuke(const char *filename, char *image, int size, int region_type)
-+{
-+	int i;
-+	struct region region;
-+	const struct frba *frba = find_frba(image, size);
-+	if (!frba)
-+		exit(EXIT_FAILURE);
-+
-+	region = get_region(frba, region_type);
-+	if (region.size > 0) {
-+		for (i = region.base; i <= region.limit; i++) {
-+			if ((i + 1) > (size))
-+				break;
-+			image[i] = 0xFF;
-+		}
-+		write_image(filename, image, size);
-+	}
-+}
-+
- int main(int argc, char *argv[])
- {
- 	int opt, option_index = 0;
-@@ -1861,6 +1916,7 @@ int main(int argc, char *argv[])
- 	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
- 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
- 	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
-+	int mode_nuke = 0;
- 	char *region_type_string = NULL, *region_fname = NULL;
- 	const char *layout_fname = NULL;
- 	char *new_filename = NULL;
-@@ -1892,6 +1948,7 @@ int main(int argc, char *argv[])
- 		{"validate", 0, NULL, 't'},
- 		{"setpchstrap", 1, NULL, 'S'},
- 		{"newvalue", 1, NULL, 'V'},
-+		{"nuke", 1, NULL, 'N'},
- 		{0, 0, 0, 0}
- 	};
- 
-@@ -1941,35 +1998,8 @@ int main(int argc, char *argv[])
- 			region_fname++;
- 			// Descriptor, BIOS, ME, GbE, Platform
- 			// valid type?
--			if (!strcasecmp("Descriptor", region_type_string))
--				region_type = 0;
--			else if (!strcasecmp("BIOS", region_type_string))
--				region_type = 1;
--			else if (!strcasecmp("ME", region_type_string))
--				region_type = 2;
--			else if (!strcasecmp("GbE", region_type_string))
--				region_type = 3;
--			else if (!strcasecmp("Platform Data", region_type_string))
--				region_type = 4;
--			else if (!strcasecmp("Device Exp1", region_type_string))
--				region_type = 5;
--			else if (!strcasecmp("Secondary BIOS", region_type_string))
--				region_type = 6;
--			else if (!strcasecmp("Reserved", region_type_string))
--				region_type = 7;
--			else if (!strcasecmp("EC", region_type_string))
--				region_type = 8;
--			else if (!strcasecmp("Device Exp2", region_type_string))
--				region_type = 9;
--			else if (!strcasecmp("IE", region_type_string))
--				region_type = 10;
--			else if (!strcasecmp("10GbE_0", region_type_string))
--				region_type = 11;
--			else if (!strcasecmp("10GbE_1", region_type_string))
--				region_type = 12;
--			else if (!strcasecmp("PTT", region_type_string))
--				region_type = 15;
--			if (region_type == -1) {
-+			if ((region_type =
-+			    get_region_type_string(region_type_string)) == -1) {
- 				fprintf(stderr, "No such region type: '%s'\n\n",
- 					region_type_string);
- 				fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
-@@ -2135,6 +2165,22 @@ int main(int argc, char *argv[])
- 		case 't':
- 			mode_validate = 1;
- 			break;
-+               case 'N':
-+                       region_type_string = strdup(optarg);
-+                       if (!region_type_string) {
-+                               fprintf(stderr, "No region specified\n");
-+                               print_usage(argv[0]);
-+                               exit(EXIT_FAILURE);
-+                       }
-+                       if ((region_type =
-+                           get_region_type_string(region_type_string)) == -1) {
-+                               fprintf(stderr, "No such region type: '%s'\n\n",
-+                                       region_type_string);
-+                               print_usage(argv[0]);
-+                               exit(EXIT_FAILURE);
-+                       }
-+                       mode_nuke = 1;
-+                       break;
- 		case 'v':
- 			print_version();
- 			exit(EXIT_SUCCESS);
-@@ -2150,7 +2196,8 @@ int main(int argc, char *argv[])
- 
- 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
- 			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
--			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) {
-+			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
-+			mode_nuke) > 1) {
- 		fprintf(stderr, "You may not specify more than one mode.\n\n");
- 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
- 		exit(EXIT_FAILURE);
-@@ -2158,7 +2205,8 @@ int main(int argc, char *argv[])
- 
- 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
- 			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
--			mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
-+			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
-+			mode_validate + mode_nuke) == 0) {
- 		fprintf(stderr, "You need to specify a mode.\n\n");
- 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
- 		exit(EXIT_FAILURE);
-@@ -2262,6 +2310,10 @@ int main(int argc, char *argv[])
- 		write_image(new_filename, image, size);
- 	}
- 
-+	if (mode_nuke) {
-+               nuke(new_filename, image, size, region_type);
-+       }
-+
- 	if (mode_altmedisable) {
- 		struct fpsba *fpsba = find_fpsba(image, size);
- 		struct fmsba *fmsba = find_fmsba(image, size);
--- 
-2.39.2
-

config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch

@@ -1,47 +0,0 @@
-From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Wed, 1 Dec 2021 02:53:00 +0000
-Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
- "cpu/intel/model_1067x: enable PECI"
-
-This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
-
-Enabling PECI without microcode updates loaded causes the CPUID feature set
-to become corrupted. And one consequence is broken SpeedStep. At least, that's
-my understanding looking at Intel Errata. This revert is not a fix, because
-upstream is correct (upstream assumes microcode updates). We will simply
-maintain this revert patch in Libreboot, from now on.
----
- src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
- 1 file changed, 9 deletions(-)
-
-diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
-index 315e7c36fc..1423fd72bc 100644
---- a/src/cpu/intel/model_1067x/model_1067x_init.c
-+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
-@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
- 	wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
- }
- 
--#define IA32_PECI_CTL		0x5a0
--
- static void configure_misc(const int eist, const int tm2, const int emttm)
- {
- 	msr_t msr;
-@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
- 		msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
- 		wrmsr(IA32_MISC_ENABLE, msr);
- 	}
--
--	/* Enable PECI
--	   WARNING: due to Erratum AW67 described in Intel document #318733
--	   the microcode must be updated before this MSR is written to. */
--	msr = rdmsr(IA32_PECI_CTL);
--	msr.lo |= 1;
--	wrmsr(IA32_PECI_CTL, msr);
- }
- 
- #define PIC_SENS_CFG	0x1aa
--- 
-2.39.2
-

config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch

@@ -1,173 +0,0 @@
-From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 17 Apr 2023 15:49:57 +0100
-Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR
-
-This reverts the changes in coreboot revision:
-df7aecd92643d207feaf7fd840f8835097346644
-
-While this fix is *technically correct*, the one in
-coreboot, it breaks rebooting as tested on several
-GM45 ThinkPads e.g. X200, T400, when microcode
-updates are not applied.
-
-Since November 2022, Libreboot includes microcode
-updates by default, but it tells users how to remove
-it from the ROM (with cbfstool) if they wish.
-
-Well, with Libreboot 20221214, 20230319 and 20230413,
-mitigations present in Libreboot 20220710 (which did
-not have microcode updates) do not exist.
-
-This patch, along with the other patch to remove PECI
-support (which breaks speedstep when microcode updates
-are not applied) have now been re-added to Libreboot.
-
-It is still best to use microcode updates by default.
-These patches in coreboot are not critically urgent,
-and you can use the machines with or without them,
-regardless of ucode.
-
-I'll probably re-write this and the other patch at
-some point, applying the change conditionally upon
-whether or not microcode is applied.
-
-Pragmatism is a good thing. I recommend it.
----
- src/cpu/intel/model_1067x/model_1067x_init.c |  4 +++
- src/cpu/intel/model_1067x/mp_init.c          | 26 --------------------
- src/cpu/intel/model_106cx/model_106cx_init.c |  4 +++
- src/cpu/intel/model_6ex/model_6ex_init.c     |  4 +++
- src/cpu/intel/model_6fx/model_6fx_init.c     |  4 +++
- 5 files changed, 16 insertions(+), 26 deletions(-)
-
-diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
-index 1423fd72bc..d1f98ca43a 100644
---- a/src/cpu/intel/model_1067x/model_1067x_init.c
-+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
-@@ -8,6 +8,7 @@
- #include <cpu/x86/cache.h>
- #include <cpu/x86/name.h>
- #include <cpu/intel/smm_reloc.h>
-+#include <cpu/intel/common/common.h>
- 
- #define MSR_BBL_CR_CTL3		0x11e
- 
-@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
- 	fill_processor_name(processor_name);
- 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
- 
-+	/* Set virtualization based on Kconfig option */
-+	set_vmx_and_lock();
-+
- 	/* Configure C States */
- 	configure_c_states(quad);
- 
-diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
-index bc53214310..72f40f6762 100644
---- a/src/cpu/intel/model_1067x/mp_init.c
-+++ b/src/cpu/intel/model_1067x/mp_init.c
-@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
- 	smm_initialize();
- }
- 
--#define SMRR_SUPPORTED (1 << 11)
--
- static void per_cpu_smm_trigger(void)
- {
--	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
--	if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
--		set_feature_ctrl_vmx();
--		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
--		/* We don't care if the lock is already setting
--		   as our smm relocation handler is able to handle
--		   setups where SMRR is not enabled here. */
--		if (ia32_ft_ctrl.lo & (1 << 0)) {
--			/* IA32_FEATURE_CONTROL locked. If we set it again we
--			   get an illegal instruction. */
--			printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
--			printk(BIOS_DEBUG, "SMRR status: %senabled\n",
--			       ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
--		} else {
--			if (!CONFIG(SET_IA32_FC_LOCK_BIT))
--				printk(BIOS_INFO,
--				       "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
--			ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
--			wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
--		}
--	} else {
--		set_vmx_and_lock();
--	}
--
- 	/* Relocate the SMM handler. */
- 	smm_relocate();
- }
-diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
-index 05f5f327cc..0450c2ad83 100644
---- a/src/cpu/intel/model_106cx/model_106cx_init.c
-+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
-@@ -7,6 +7,7 @@
- #include <cpu/intel/speedstep.h>
- #include <cpu/x86/cache.h>
- #include <cpu/x86/name.h>
-+#include <cpu/intel/common/common.h>
- 
- #define HIGHEST_CLEVEL		3
- static void configure_c_states(void)
-@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
- 	fill_processor_name(processor_name);
- 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
- 
-+	/* Set virtualization based on Kconfig option */
-+	set_vmx_and_lock();
-+
- 	/* Configure C States */
- 	configure_c_states();
- 
-diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
-index 5bd1c32815..f3bb08cde3 100644
---- a/src/cpu/intel/model_6ex/model_6ex_init.c
-+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
-@@ -7,6 +7,7 @@
- #include <cpu/intel/speedstep.h>
- #include <cpu/x86/cache.h>
- #include <cpu/x86/name.h>
-+#include <cpu/intel/common/common.h>
- 
- #define HIGHEST_CLEVEL		3
- static void configure_c_states(void)
-@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
- 	/* Setup Page Attribute Tables (PAT) */
- 	// TODO set up PAT
- 
-+	/* Set virtualization based on Kconfig option */
-+	set_vmx_and_lock();
-+
- 	/* Configure C States */
- 	configure_c_states();
- 
-diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
-index 535fb8fae7..f7b05facd2 100644
---- a/src/cpu/intel/model_6fx/model_6fx_init.c
-+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
-@@ -7,6 +7,7 @@
- #include <cpu/intel/speedstep.h>
- #include <cpu/x86/cache.h>
- #include <cpu/x86/name.h>
-+#include <cpu/intel/common/common.h>
- 
- #define HIGHEST_CLEVEL		3
- static void configure_c_states(void)
-@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
- 	/* Setup Page Attribute Tables (PAT) */
- 	// TODO set up PAT
- 
-+	/* Set virtualization based on Kconfig option */
-+	set_vmx_and_lock();
-+
- 	/* Configure C States */
- 	configure_c_states();
- 
--- 
-2.39.2
-

config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch

@@ -1,28 +0,0 @@
-From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for
- dGPU models
-
-Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/e6400/devicetree.cb | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
-index bb954cbd7b..e9f3915d17 100644
---- a/src/mainboard/dell/e6400/devicetree.cb
-+++ b/src/mainboard/dell/e6400/devicetree.cb
-@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
- 		ops gm45_pci_domain_ops
- 
- 		device pci 00.0 on end # host bridge
--		device pci 01.0 off end
-+		device pci 01.0 on end
- 		device pci 02.0 on end # VGA
- 		device pci 02.1 on end # Display
- 		device pci 03.0 on end # ME
--- 
-2.39.2
-

config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -1,39 +0,0 @@
-From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 19/22] Remove warning for coreboot images built without a
- payload
-
-I added this in upstream to prevent people from accidentally flashing
-roms without a payload resulting in a no boot situation, but in
-libreboot lbmk handles the payload and thus this warning always comes
-up. This has caused confusion and concern so just patch it out.
----
- payloads/Makefile.inc | 13 +------------
- 1 file changed, 1 insertion(+), 12 deletions(-)
-
-diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
-index e735443a76..4f1692a873 100644
---- a/payloads/Makefile.inc
-+++ b/payloads/Makefile.inc
-@@ -49,16 +49,5 @@ distclean-payloads:
- print-repo-info-payloads:
- 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
- 
--ifeq ($(CONFIG_PAYLOAD_NONE),y)
--files_added:: warn_no_payload
--endif
--
--warn_no_payload:
--	printf "\n\t** WARNING **\n"
--	printf "coreboot has been built without a payload. Writing\n"
--	printf "a coreboot image without a payload to your board's\n"
--	printf "flash chip will result in a non-booting system. You\n"
--	printf "can use cbfstool to add a payload to the image.\n\n"
--
- .PHONY: force-payload coreinfo nvramcui
--.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
-+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--- 
-2.39.2
-

config/coreboot/default/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch

@@ -1,61 +0,0 @@
-From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 27 Aug 2023 17:36:36 -0600
-Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios
-
-These were determined by sniffing the LPC bus while toggling the
-hardware wireless switch on the Latitude E6400. To differentiate devices
-options in the vendor BIOS to change which radios the switch controlled
-were used.
-
-Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/mec5035.c | 9 +++++++++
- src/ec/dell/mec5035/mec5035.h | 8 ++++++++
- 2 files changed, 17 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 8da11e5b1c..e0335a4635 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting)
- 	return buf[0];
- }
- 
-+void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on)
-+{
-+	/* From LPC traces and userspace testing with other values,
-+	   the second byte has to be 2 for an unknown reason. */
-+	u8 buf[3] = {dev, 2, on};
-+	write_mailbox_regs(buf, 2, 3);
-+	ec_command(CMD_RADIO_EN);
-+}
-+
- void mec5035_early_init(void)
- {
- 	/* If this isn't sent the EC shuts down the system after about 15
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index e7a05b64d4..16512e2cc2 100644
---- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -16,8 +16,16 @@
- 
- #define CMD_CPU_OK	0xc2
- 
-+#define CMD_RADIO_EN	0x2b
-+enum mec5035_radio_dev {
-+	RADIO_WLAN = 0,
-+	RADIO_WWAN = 1,
-+	RADIO_WPAN = 2,
-+};
-+
- u8 mec5035_mouse_touchpad(u8 setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
-+void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on);
- 
- #endif /* _EC_DELL_MEC5035_H_ */
--- 
-2.39.2
-

config/coreboot/default/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch

@@ -1,37 +0,0 @@
-From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 27 Aug 2023 19:15:37 -0600
-Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API
-
-Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/mec5035.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index e0335a4635..20a33cc0ad 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -4,6 +4,7 @@
- #include <console/console.h>
- #include <device/device.h>
- #include <device/pnp.h>
-+#include <option.h>
- #include <pc80/keyboard.h>
- #include <stdint.h>
- #include "mec5035.h"
-@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev)
- 	mec5035_mouse_touchpad(TP_PS2_MOUSE);
- 
- 	pc_keyboard_init(NO_AUX_DEVICE);
-+
-+	mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1));
-+	mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1));
-+	mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1));
- }
- 
- static struct device_operations ops = {
--- 
-2.39.2
-

config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch

@@ -1,820 +0,0 @@
-From db1cb588b64f17c7ed08201bf1e09ab5393e4b04 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sat, 19 Aug 2023 16:19:10 -0600
-Subject: [PATCH 22/22] mb/dell: Add Latitude E6430 (Ivy Bridge)
-
-Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested.
-This is based on the autoport output with some manual tweaks. The flash
-is 8MiB + 4MiB, and is fairly easily accessed by removing the keyboard.
-It can also be internally flashed by sending a command to the EC, which
-causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections. [1] The EC is the SMSC MEC5055,
-which seems to be compatible with the existing MEC5035 code.
-
-Working:
-- Libgfxinit
-- USB EHCI debug (left side usb port is HCD index 2, middle port on the
-  right side is HCD index 1)
-- Keyboard
-- Touchpad/trackpoint
-- ExpressCard
-- Audio
-- Ethernet
-- SD card reader
-- mPCIe WiFi
-- SeaBIOS 1.16.2
-- edk2 (MrChromebox' fork, uefipayload_202306)
-- Internal flashing
-
-Not working:
-- S3 suspend: It seems like the EC also controls the DRAM reset gate so
-  there may be a command that needs to be implemented for this
-- Physical Wireless switch
-- Battery reporting
-- Brightness hotkeys
-
-Unknown/untested:
-- Dock
-- eSATA
-- TPM
-- dGPU on non-UMA model
-
-[1] https://github.com/nic3-14159/e6400-flash-unlock
-
-Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/e6430/Kconfig           |  36 ++++
- src/mainboard/dell/e6430/Kconfig.name      |   2 +
- src/mainboard/dell/e6430/Makefile.inc      |   6 +
- src/mainboard/dell/e6430/acpi/ec.asl       |   9 +
- src/mainboard/dell/e6430/acpi/platform.asl |  12 ++
- src/mainboard/dell/e6430/acpi/superio.asl  |   3 +
- src/mainboard/dell/e6430/acpi_tables.c     |  16 ++
- src/mainboard/dell/e6430/board_info.txt    |   6 +
- src/mainboard/dell/e6430/cmos.default      |   9 +
- src/mainboard/dell/e6430/cmos.layout       |  88 ++++++++++
- src/mainboard/dell/e6430/data.vbt          | Bin 0 -> 6144 bytes
- src/mainboard/dell/e6430/devicetree.cb     |  68 ++++++++
- src/mainboard/dell/e6430/dsdt.asl          |  30 ++++
- src/mainboard/dell/e6430/early_init.c      |  38 ++++
- src/mainboard/dell/e6430/gma-mainboard.ads |  20 +++
- src/mainboard/dell/e6430/gpio.c            | 192 +++++++++++++++++++++
- src/mainboard/dell/e6430/hda_verb.c        |  33 ++++
- src/mainboard/dell/e6430/mainboard.c       |  21 +++
- 18 files changed, 589 insertions(+)
- create mode 100644 src/mainboard/dell/e6430/Kconfig
- create mode 100644 src/mainboard/dell/e6430/Kconfig.name
- create mode 100644 src/mainboard/dell/e6430/Makefile.inc
- create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl
- create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl
- create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl
- create mode 100644 src/mainboard/dell/e6430/acpi_tables.c
- create mode 100644 src/mainboard/dell/e6430/board_info.txt
- create mode 100644 src/mainboard/dell/e6430/cmos.default
- create mode 100644 src/mainboard/dell/e6430/cmos.layout
- create mode 100644 src/mainboard/dell/e6430/data.vbt
- create mode 100644 src/mainboard/dell/e6430/devicetree.cb
- create mode 100644 src/mainboard/dell/e6430/dsdt.asl
- create mode 100644 src/mainboard/dell/e6430/early_init.c
- create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/e6430/gpio.c
- create mode 100644 src/mainboard/dell/e6430/hda_verb.c
- create mode 100644 src/mainboard/dell/e6430/mainboard.c
-
-diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
-new file mode 100644
-index 0000000000..3178d12aff
---- /dev/null
-+++ b/src/mainboard/dell/e6430/Kconfig
-@@ -0,0 +1,36 @@
-+if BOARD_DELL_LATITUDE_E6430
-+
-+config BOARD_SPECIFIC_OPTIONS
-+	def_bool y
-+	select BOARD_ROMSIZE_KB_12288
-+	select EC_ACPI
-+	select EC_DELL_MEC5035
-+	select GFX_GMA_PANEL_1_ON_LVDS
-+	select HAVE_ACPI_RESUME
-+	select HAVE_ACPI_TABLES
-+	select HAVE_CMOS_DEFAULT
-+	select HAVE_OPTION_TABLE
-+	select INTEL_INT15
-+	select MAINBOARD_HAS_LIBGFXINIT
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
-+	select SERIRQ_CONTINUOUS_MODE
-+	select SOUTHBRIDGE_INTEL_C216
-+	select SYSTEM_TYPE_LAPTOP
-+	select USE_NATIVE_RAMINIT
-+
-+config MAINBOARD_DIR
-+	default "dell/e6430"
-+
-+config MAINBOARD_PART_NUMBER
-+	default "Latitude E6430"
-+
-+config VGA_BIOS_ID
-+	default "8086,0166"
-+
-+config DRAM_RESET_GATE_GPIO
-+	default 60
-+
-+config USBDEBUG_HCD_INDEX
-+	default 2
-+endif
-diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
-new file mode 100644
-index 0000000000..f866b03585
---- /dev/null
-+++ b/src/mainboard/dell/e6430/Kconfig.name
-@@ -0,0 +1,2 @@
-+config BOARD_DELL_LATITUDE_E6430
-+	bool "Latitude E6430"
-diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc
-new file mode 100644
-index 0000000000..ba64e93eb8
---- /dev/null
-+++ b/src/mainboard/dell/e6430/Makefile.inc
-@@ -0,0 +1,6 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+bootblock-y += early_init.c
-+bootblock-y += gpio.c
-+romstage-y += early_init.c
-+romstage-y += gpio.c
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl
-new file mode 100644
-index 0000000000..0d429410a9
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi/ec.asl
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Device(EC)
-+{
-+	Name (_HID, EISAID("PNP0C09"))
-+	Name (_UID, 0)
-+	Name (_GPE, 16)
-+/* FIXME: EC support */
-+}
-diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl
-new file mode 100644
-index 0000000000..2d24bbd9b9
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi/platform.asl
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+Method(_WAK, 1)
-+{
-+	/* FIXME: EC support  */
-+	Return(Package() {0, 0})
-+}
-+
-+Method(_PTS,1)
-+{
-+	/* FIXME: EC support  */
-+}
-diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl
-new file mode 100644
-index 0000000000..55b1db5b11
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi/superio.asl
-@@ -0,0 +1,3 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <drivers/pc80/pc/ps2_controller.asl>
-diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c
-new file mode 100644
-index 0000000000..e2759659bf
---- /dev/null
-+++ b/src/mainboard/dell/e6430/acpi_tables.c
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi_gnvs.h>
-+#include <soc/nvs.h>
-+
-+/* FIXME: check this function.  */
-+void mainboard_fill_gnvs(struct global_nvs *gnvs)
-+{
-+	/* The lid is open by default. */
-+	gnvs->lids = 1;
-+
-+	/* Temperature at which OS will shutdown */
-+	gnvs->tcrt = 100;
-+	/* Temperature at which OS will throttle CPU */
-+	gnvs->tpsv = 90;
-+}
-diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt
-new file mode 100644
-index 0000000000..4601a4aaba
---- /dev/null
-+++ b/src/mainboard/dell/e6430/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: laptop
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-+Release year: 2012
-diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
-new file mode 100644
-index 0000000000..2a5b30f2b7
---- /dev/null
-+++ b/src/mainboard/dell/e6430/cmos.default
-@@ -0,0 +1,9 @@
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+bluetooth=Enable
-+wwan=Enable
-+wlan=Enable
-+sata_mode=AHCI
-+me_state=Normal
-diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
-new file mode 100644
-index 0000000000..e85ea4c661
---- /dev/null
-+++ b/src/mainboard/dell/e6430/cmos.layout
-@@ -0,0 +1,88 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0	120	r	0	reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384	1	e	4	boot_option
-+388	4	h	0	reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395	4	e	6	debug_level
-+
-+#400	8	r	0	reserved for century byte
-+
-+# coreboot config options: southbridge
-+408	1	e	1	nmi
-+409	2	e	7	power_on_after_fail
-+411     1       e       9       sata_mode
-+
-+# coreboot config options: EC
-+412	1	e	1	bluetooth
-+413	1	e	1	wwan
-+415	1	e	1	wlan
-+
-+# coreboot config options: ME
-+424	1	e	14	me_state
-+425	2	h	0	me_state_prev
-+
-+# coreboot config options: northbridge
-+432	3	e	11	gfx_uma_size
-+435	2	e	12	hybrid_graphics_mode
-+440	8	h	0	volume
-+
-+# VBOOT
-+448	128	r	0	vbnv
-+
-+# SandyBridge MRC Scrambler Seed values
-+896	32	r	0	mrc_scrambler_seed
-+928	32	r	0	mrc_scrambler_seed_s3
-+960	16	r	0	mrc_scrambler_seed_chk
-+
-+# coreboot config options: check sums
-+984	16	h	0	check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID	value	text
-+1	0	Disable
-+1	1	Enable
-+2	0	Enable
-+2	1	Disable
-+4	0	Fallback
-+4	1	Normal
-+6	0	Emergency
-+6	1	Alert
-+6	2	Critical
-+6	3	Error
-+6	4	Warning
-+6	5	Notice
-+6	6	Info
-+6	7	Debug
-+6	8	Spew
-+7	0	Disable
-+7	1	Enable
-+7	2	Keep
-+9	0	AHCI
-+9	1	Compatible
-+11	0	32M
-+11	1	64M
-+11	2	96M
-+11	3	128M
-+11	4	160M
-+11	5	192M
-+11	6	224M
-+14	0	Normal
-+14	1	Disabled
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 447 984
-diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d
-GIT binary patch
-literal 6144
-zcmeHKU2Gdw7XHRFw#VZc+nI!tq)j-qG$b@>#vu)%WW~fb!7ZV6LkJc^+qlG~(WXgp
-zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;)
-zjkMh#DR=zcpL5Use9xJ4?#x^=mKdcQb|t!Zj3v6R-<{Yod<{*&!ppI%xUMXT9lLMX
-zn;IM)+?yEQoxF~o#5x>}{dfwPkR;RSiC=!jj_JAlRQpJWpd}$VY+XtFX9|?cO&y#m
-z<SE`uGt*OdcG7S%MVsQ5GkI`wn)VeYZ#ytIou8d0Yb)J)AUAzmo)Vpuq&7;?RQ_;&
-zie?W??w`vSW@&DQ`Yr3=;cjcIHNi^L`QOvN$?05SGCy0nZ&#9>IdrG<AJm@gpdQPz
-zx_Yd5oSZFFa;9)-D-BLf(TLc`ERE!6^M%9tiLHiaXuwHXRU|<2BX~C?>4zSq6a*B6
-zRA?%66|w}s0z*YuMNq*73a(KQQ8A>TT}4_&3_e5hDZs@lHpaYN60rOh%jBQN+*9zu
-zIASsRL<3j>pYk93g@PXvaUZbpk)yEWDA4C2Ai!cNXi4M~3gjt#<|(LxR49-{<^K|T
-zqL5SnLUq0r*kw>Q!0PGk>)$?LCsIS{ox_=t(Xs5!w-o>M=erl0apv_Z`-(^w_5@pz
-z)}lBfx8o(*hgal&<dh}67_jhVpb;fTbFdMn7Q<$~Ll)yIMvJN<r<#~$+{1W;@r<hB
-z1mh&*ZN|rpFBo4lzGDPK8tNG98Jij1j4K&Q#`TPw7&*r87<Vw{8Gm6s$astqxC3WO
-zz9NE-Ek(&|>)aMG1rKzf_^2m;)RTu!i#rBrUK{pWM_5BuDg}f1vGgAMqNM&t?7(IQ
-zcDa=Dn9^Q5?6k6+@y4UvvL3SDxKs*_^RS1n^H*!{fYZz^rPBX<FZ?DhF0v6`u90ic
-zA-5^lMeh7u!RIful;@oGY=u>mV(=eO(Cd-pvqPqVBRYz~7nA{nO7|Kv{w^;?LXb8F
-zZpK}KE=2zd4)ya^Le2qLGkt7<&s%Z6*Z`k>QW26OPC!Y8WP|wUI8Rlea-W3+oBO=P
-z7W#bDD=HM*SuTlWaHmLu%9{LBg+7xrp>y^-%p_)+nfZB&dFmKmF?B(+QtAm&-^!?J
-zr{Qq~n%$Y;KvfME{x@gVUB~vz&MBs@*k&z6fZ?Ic-b`*fKea1&Fkj=~!ZaqDU=O0r
-zYCPKK+S_PdhGTnR+18<YSJL`a_aBz`G`HE=V`WMDYTMfPLXT~qEK3^O(Kj!<{?_~E
-z{ct?ZJ!#R&H|_;QGyr;2JDTu4Urkt)#LW}e65l@e>g0GR_nHOE`gieuP-A>69j*W0
-z><PPSE2YwgK714^F4A&KOda3ou4=7C($dQbCP^XH=U4QVf8#_di>h~9>kwTD6>nL4
-zBSLUr+fHA!LgjQi9)hfgsV8iv!rHDd&4tY)VQn!?C&K1ZSo<JM{|K9!t~KbiT{nky
-zZA_;>>gEHwc1)*Nb@P2)`%EVorfFy!3`!X0sG<GVpasKx*wBs}^oC)6VrYLeNR61y
-z5$%!)?TnbWM6~@8x-Vir9?_nP(0dVcIij74P%LV0jB1@x<FeCA(YGuW>p0XopwxoS
-z0g?6TPW!DC<JKR&l%Knmp5z$x;*#X7@7xT>ql9>N1GN_$T-UVr&HErC5juykd~Sxy
-zq!PK|<^jJ^DuQ9)7p<sFLXlH${*3wEJ(L;FsEd;DgJ^{x0*)Wd^<xJzFfF2O*!)Bc
-zXtuum#xVj7H8Tulu*qs$*N1J-3WmV*15LsWQhjX<ZR^LFq0OSkUSwZ$8NS&h7|>t`
-z7FKz(x)t4R_RHf7I)6EA!d)M`R($wttvJgMee=p9zrFL_EL#DYA0wUzD?Ryj%h>lB
-ztg|e-5!;@t?uT+rR=1)e9yp?8gwNW88`Zyt!8rx=+B{i(4~DY`_-WO>sGeD;nsGcs
-z7h1ZN6srJX#Uke;d$JhpccQxNhw2Qz?Zw91`@8IHm-n!7{19~*_}LvecV2YZ7%!rJ
-zJQk}HtK2>CvB*WQ@u9a$Eq*zF2M=FM=@c`>dwDQ;<8EgZ-}dvt6=k(8Kqfa=nDJJ{
-z`Qth}G~%sFr{ZEKZb_%aySrD?sV%fJw`vFfda&ho1a>X)H^I}D_0A<|*{8kwEBU8>
-qS<b6g={WLAp3+&R^8(yo-t$_!=7BX2ta)I~18W{w^T5By1OEis_@J`@
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
-new file mode 100644
-index 0000000000..56dd9e5fe2
---- /dev/null
-+++ b/src/mainboard/dell/e6430/devicetree.cb
-@@ -0,0 +1,68 @@
-+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
-+	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
-+	register "gpu_cpu_backlight" = "0x00001312"
-+	register "gpu_dp_b_hotplug" = "4"
-+	register "gpu_dp_c_hotplug" = "4"
-+	register "gpu_dp_d_hotplug" = "4"
-+	register "gpu_panel_port_select" = "0"
-+	register "gpu_panel_power_backlight_off_delay" = "2300"
-+	register "gpu_panel_power_backlight_on_delay" = "2300"
-+	register "gpu_panel_power_cycle_delay" = "6"
-+	register "gpu_panel_power_down_delay" = "400"
-+	register "gpu_panel_power_up_delay" = "400"
-+	register "gpu_pch_backlight" = "0x13121312"
-+
-+	device domain 0x0 on
-+		subsystemid 0x1028 0x0534 inherit
-+
-+		device ref host_bridge on end # Host bridge
-+		device ref peg10 off end # PEG
-+		device ref igd on end # iGPU
-+
-+		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
-+			register "docking_supported" = "1"
-+			register "gen1_dec" = "0x007c0681"
-+			register "gen2_dec" = "0x005c0921"
-+			register "gen3_dec" = "0x003c07e1"
-+			register "gen4_dec" = "0x007c0901"
-+			register "gpi0_routing" = "2"
-+			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
-+			register "pcie_port_coalesce" = "1"
-+			register "sata_interface_speed_support" = "0x3"
-+			register "sata_port_map" = "0x33"
-+			register "spi_lvscc" = "0x2005"
-+			register "spi_uvscc" = "0x2005"
-+			register "superspeed_capable_ports" = "0x0000000f"
-+			register "xhci_overcurrent_mapping" = "0x00000c03"
-+			register "xhci_switchable_ports" = "0x0000000f"
-+
-+			device ref xhci		on end # USB 3.0 Controller
-+			device ref mei1		on end # Management Engine Interface 1
-+			device ref mei2		off end # Management Engine Interface 2
-+			device ref me_ide_r	off end # Management Engine IDE-R
-+			device ref me_kt	on end # Management Engine KT
-+			device ref gbe		on end # Intel Gigabit Ethernet
-+			device ref ehci2	on end # USB2 EHCI #2
-+			device ref hda		on end # High Definition Audio
-+			device ref pcie_rp1	on end # PCIe Port #1
-+			device ref pcie_rp2	on end # PCIe Port #2
-+			device ref pcie_rp3	on end # PCIe Port #3
-+			device ref pcie_rp4	on end # PCIe Port #4
-+			device ref pcie_rp5	off end # PCIe Port #5
-+			device ref pcie_rp6	on end # PCIe Port #6
-+			device ref pcie_rp7	off end # PCIe Port #7
-+			device ref pcie_rp8	off end # PCIe Port #8
-+			device ref ehci1	on end # USB2 EHCI #1
-+			device ref pci_bridge	off end # PCI bridge
-+			device ref lpc		on # LPC bridge
-+				chip ec/dell/mec5035
-+					device pnp ff.0 on end
-+				end
-+			end
-+			device ref sata1	on end # SATA Controller 1
-+			device ref smbus	on end # SMBus
-+			device ref sata2	off end # SATA Controller 2
-+			device ref thermal	off end # Thermal
-+		end
-+	end
-+end
-diff --git a/src/mainboard/dell/e6430/dsdt.asl b/src/mainboard/dell/e6430/dsdt.asl
-new file mode 100644
-index 0000000000..7d13c55b08
---- /dev/null
-+++ b/src/mainboard/dell/e6430/dsdt.asl
-@@ -0,0 +1,30 @@
-+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
-+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <acpi/acpi.h>
-+
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	ACPI_DSDT_REV_2,
-+	OEM_ID,
-+	ACPI_TABLE_CREATOR,
-+	0x20141018	/* OEM revision */
-+)
-+{
-+	#include <acpi/dsdt_top.asl>
-+	#include "acpi/platform.asl"
-+	#include <cpu/intel/common/acpi/cpu.asl>
-+	#include <southbridge/intel/common/acpi/platform.asl>
-+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
-+	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+
-+	Device (\_SB.PCI0)
-+	{
-+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
-+		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
-+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
-+	}
-+}
-diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
-new file mode 100644
-index 0000000000..7944157f59
---- /dev/null
-+++ b/src/mainboard/dell/e6430/early_init.c
-@@ -0,0 +1,38 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <northbridge/intel/sandybridge/raminit_native.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+	{ 1, 1, 0 },
-+	{ 1, 1, 0 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 1 },
-+	{ 1, 0, 2 },
-+	{ 1, 1, 2 },
-+	{ 1, 1, 3 },
-+	{ 1, 1, 3 },
-+	{ 1, 1, 4 },
-+	{ 1, 1, 4 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 5 },
-+	{ 1, 2, 6 },
-+	{ 1, 2, 6 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
-+	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
-+	mec5035_early_init();
-+}
-+
-+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-+{
-+	read_spd(&spd[0], 0x50, id_only);
-+	read_spd(&spd[2], 0x52, id_only);
-+}
-diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
-new file mode 100644
-index 0000000000..1310830c8e
---- /dev/null
-+++ b/src/mainboard/dell/e6430/gma-mainboard.ads
-@@ -0,0 +1,20 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (
-+      HDMI1, -- mainboard HDMI
-+      DP2, -- dock DP
-+      DP3, -- dock DP
-+      Analog, --mainboard VGA
-+      LVDS,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c
-new file mode 100644
-index 0000000000..777570765a
---- /dev/null
-+++ b/src/mainboard/dell/e6430/gpio.c
-@@ -0,0 +1,192 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_GPIO,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio1 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+	.gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio13 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c
-new file mode 100644
-index 0000000000..56ada95c58
---- /dev/null
-+++ b/src/mainboard/dell/e6430/hda_verb.c
-@@ -0,0 +1,33 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76df,	/* Codec Vendor / Device ID: IDT */
-+	0x10280534,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x10280534),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862806,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c
-new file mode 100644
-index 0000000000..31e49802fc
---- /dev/null
-+++ b/src/mainboard/dell/e6430/mainboard.c
-@@ -0,0 +1,21 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/device.h>
-+#include <drivers/intel/gma/int15.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+#include <ec/acpi/ec.h>
-+#include <console/console.h>
-+#include <pc80/keyboard.h>
-+
-+static void mainboard_enable(struct device *dev)
-+{
-+
-+	/* FIXME: fix these values. */
-+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
-+					GMA_INT15_PANEL_FIT_DEFAULT,
-+					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
-+}
-+
-+struct chip_operations mainboard_ops = {
-+	.enable_dev = mainboard_enable,
-+};
--- 
-2.39.2
-

config/coreboot/default/patches/0023-HACK-Disable-coreboot-related-BL31-features.patch

@@ -1,28 +0,0 @@
-From 9f52555eac217623ad2edc72492f9ded6a5b538d Mon Sep 17 00:00:00 2001
-From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
-Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH] HACK: Disable coreboot related BL31 features
-
-I don't know why, but removing this BL31 make argument lets gru-kevin
-power off properly when shut down from Linux. Needs investigation.
----
- src/arch/arm64/Makefile.inc | 3 ---
- 1 file changed, 3 deletions(-)
-
-diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
-index 6b49743633c3..e1982d92cc5c 100644
---- a/src/arch/arm64/Makefile.inc
-+++ b/src/arch/arm64/Makefile.inc
-@@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
- # Always enable crash reporting, even on a release build
- BL31_MAKEARGS += CRASH_REPORTING=1
- 
--# Enable coreboot-specific features like CBMEM console support
--BL31_MAKEARGS += COREBOOT=1
--
- # Avoid build/release|build/debug distinction by overriding BUILD_PLAT directly
- BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
- 
--- 
-2.40.1
-

config/coreboot/default/target.cfg

@@ -1,4 +1,4 @@
 tree="default"
 romtype="normal"
-rev="d862695f5f432b5c78dada5f16c293a4c3f9fce6"
+rev="54d0cc9a3cf31963ebf0ca85a87a7e464ef678a7" # 4.18_branch
 arch="x86_64"

config/coreboot/e6400_4mb/config/libgfxinit_corebootfb

@@ -1,586 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E6400"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e6400"
-CONFIG_VGA_BIOS_ID="10de,06eb"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x3FD000
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-CONFIG_VGA_BIOS=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_BOARD_DELL_E6400=y
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefc0000
-CONFIG_DCACHE_RAM_SIZE=0x10000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom"
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6400"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_4096=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_4096=y
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=4096
-CONFIG_ROM_SIZE=0x00400000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-# CONFIG_VGA_BIOS_SECOND is not set
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x61254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_SOCKET_P=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_GM45=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-# CONFIG_HAVE_ME_BIN is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_VGA_ROM_RUN_DEFAULT=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-# CONFIG_VGA_BIOS_DGPU is not set
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_EDID=y
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_NULL=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/e6400_4mb/config/libgfxinit_txtmode

@@ -1,582 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E6400"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e6400"
-CONFIG_VGA_BIOS_ID="10de,06eb"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x3FD000
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-CONFIG_VGA_BIOS=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_BOARD_DELL_E6400=y
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefc0000
-CONFIG_DCACHE_RAM_SIZE=0x10000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom"
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6400"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_4096=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_4096=y
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=4096
-CONFIG_ROM_SIZE=0x00400000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-# CONFIG_VGA_BIOS_SECOND is not set
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x61254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_SOCKET_P=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_GM45=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-# CONFIG_HAVE_ME_BIN is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_VGA_ROM_RUN_DEFAULT=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-# CONFIG_VGA_BIOS_DGPU is not set
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_EDID=y
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_NULL=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/e6400_4mb/target.cfg

@@ -1,9 +0,0 @@
-tree="default"
-romtype="4MiB ICH9 IFD NOR flash"
-arch="x86_64"
-payload_grub="n"
-payload_grub_withseabios="n"
-payload_seabios="y"
-payload_memtest="y"
-grub_scan_disk="ahci"
-microcode_required="n"

config/coreboot/e6430_12mb/config/libgfxinit_corebootfb

@@ -1,599 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-CONFIG_OPTION_BACKEND_NONE=y
-# CONFIG_USE_OPTION_TABLE is not set
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E6430"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e6430"
-CONFIG_VGA_BIOS_ID="8086,0166"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0xBE5000
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_E6400 is not set
-CONFIG_BOARD_DELL_LATITUDE_E6430=y
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/e6430/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/e6430/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/e6430/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6430"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=12288
-CONFIG_ROM_SIZE=0x00c00000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_C216=y
-CONFIG_SOUTH_BRIDGE_OPTIONS=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_ACPI=y
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-# CONFIG_INTEL_GMA_ADD_VBT is not set
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-CONFIG_USE_PC_CMOS_ALTCENTURY=y
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/e6430_12mb/config/libgfxinit_txtmode

@@ -1,596 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-CONFIG_OPTION_BACKEND_NONE=y
-# CONFIG_USE_OPTION_TABLE is not set
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Latitude E6430"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/e6430"
-CONFIG_VGA_BIOS_ID="8086,0166"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0xBE5000
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-# CONFIG_BOARD_DELL_E6400 is not set
-CONFIG_BOARD_DELL_LATITUDE_E6430=y
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/e6430/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/e6430/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/e6430/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6430"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=12288
-CONFIG_ROM_SIZE=0x00c00000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_C216=y
-CONFIG_SOUTH_BRIDGE_OPTIONS=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_ACPI=y
-CONFIG_EC_DELL_MEC5035=y
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-# CONFIG_INTEL_GMA_ADD_VBT is not set
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-CONFIG_USE_PC_CMOS_ALTCENTURY=y
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/e6430_12mb/target.cfg

@@ -1,8 +0,0 @@
-tree="default"
-romtype="normal"
-arch="x86_64"
-payload_grub="n"
-payload_seabios_withgrub="n"
-payload_seabios="y"
-payload_memtest="y"
-grub_scan_disk="ahci"

config/coreboot/fam15h_rdimm/patches/0003-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch

@@ -1,38 +0,0 @@
-From 7a00638cea41ad939a59fc0e5996959435fbdb7f Mon Sep 17 00:00:00 2001
-From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
-Date: Sun, 7 Feb 2021 16:40:05 +0100
-Subject: [PATCH 3/6] Tweak cmos defaults for KCMA-D8 (for a little speed
- boost)
-
-63xx CPUs have the option to use a reduced latency value inside the crossbar.
-Setting "experimental_memory_speed_boost=Enable" aparently only has an effect
-on 63xx CPUs and may, in certain cases, yield a slight memory bandwidth
-increase (according to Timothy Pearson), but maybe it also works for
-43xx CPUs.
-
-Setting "l3_cache_partitioning=Enable" will increase performance in certain
-situations. See:
-https://developer.arm.com/documentation/100453/0401/functional-description/l3-cache/l3-cache-partitioning?lang=en
----
- src/mainboard/asus/kcma-d8/cmos.default | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default
-index 306687157f..4e033d756f 100644
---- a/src/mainboard/asus/kcma-d8/cmos.default
-+++ b/src/mainboard/asus/kcma-d8/cmos.default
-@@ -21,9 +21,9 @@ sata_ahci_mode=Enable
- sata_alpm=Disable
- maximum_p_state_limit=0xf
- probe_filter=Auto
--l3_cache_partitioning=Disable
-+l3_cache_partitioning=Enable
- gart=Enable
- ehci_async_data_cache=Enable
--experimental_memory_speed_boost=Disable
-+experimental_memory_speed_boost=Enable
- power_on_after_fail=On
- boot_option=Fallback
--- 
-2.25.1
-

config/coreboot/fam15h_rdimm/patches/0006-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch

@@ -1,32 +0,0 @@
-From f0aac7261e16adc8e61eca7a506ff2de5112be47 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Fri, 7 May 2021 19:43:32 +0100
-Subject: [PATCH 6/6] asus/kgpe-d16: enable lc_cache_partitioning and
- experimental_memory_speed_boost
-
-This really only benefits 63xx opterons which are less reliable in libreboot due
-to lack of CPU microcode updates, but we might aswell enable this anyway.
----
- src/mainboard/asus/kgpe-d16/cmos.default | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
-index 7c496a50d7..8a25620e1d 100644
---- a/src/mainboard/asus/kgpe-d16/cmos.default
-+++ b/src/mainboard/asus/kgpe-d16/cmos.default
-@@ -21,10 +21,10 @@ sata_ahci_mode=Enable
- sata_alpm=Disable
- maximum_p_state_limit=0xf
- probe_filter=Auto
--l3_cache_partitioning=Disable
-+l3_cache_partitioning=Enable
- ieee1394_controller=Enable
- gart=Enable
- ehci_async_data_cache=Enable
--experimental_memory_speed_boost=Disable
-+experimental_memory_speed_boost=Enable
- power_on_after_fail=On
- boot_option=Fallback
--- 
-2.25.1
-

config/coreboot/fam15h_rdimm/patches/0007-util-cbfstool-Makefile-support-distclean.patch

@@ -1,41 +0,0 @@
-From d5dc3f23eb546cf328fdfe1e918afa028fb9cd8c Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 9 Jul 2023 04:13:52 +0100
-Subject: [PATCH 1/1] util/cbfstool Makefile: support distclean
-
-it just does make-clean
-
-this is so that this super-old coreboot revision
-interfaces well with lbmk, which runs distclean
-on cbfstool (which is supported, on modern cbfstool)
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/cbfstool/Makefile | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
-index d5321f6959..b8424d7d87 100644
---- a/util/cbfstool/Makefile
-+++ b/util/cbfstool/Makefile
-@@ -26,7 +26,7 @@ ifittool: $(objutil)/cbfstool/ifittool
- 
- cbfs-compression-tool: $(objutil)/cbfstool/cbfs-compression-tool
- 
--.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool
-+.PHONY: distclean clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool
- clean:
- 	$(RM) fmd_parser.c fmd_parser.h fmd_scanner.c fmd_scanner.h
- 	$(RM) $(objutil)/cbfstool/cbfstool $(cbfsobj)
-@@ -55,6 +55,8 @@ install: all
- 	$(INSTALL) ifittool $(DESTDIR)$(BINDIR)
- 	$(INSTALL) cbfs-compression-tool $(DESTDIR)$(BINDIR)
- 
-+distclean: clean
-+
- ifneq ($(V),1)
- .SILENT:
- endif
--- 
-2.40.1
-

config/coreboot/fam15h_rdimm/patches/0008-crossgcc-patch-binutils-2.32-for-newer-hostcc.patch

@@ -1,37 +0,0 @@
-From 4b4b2bdc2cedb3e219c6f90809e5684441b1dafa Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 9 Jul 2023 04:54:19 +0100
-Subject: [PATCH 1/1] crossgcc: patch binutils 2.32 for newer hostcc
-
-tested on debian sid as of 9 July 2023
-
-implicit string declaration
-
-easy peasy
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/crossgcc/patches/binutils-2.32_stringfix.patch | 11 +++++++++++
- 1 file changed, 11 insertions(+)
- create mode 100644 util/crossgcc/patches/binutils-2.32_stringfix.patch
-
-diff --git a/util/crossgcc/patches/binutils-2.32_stringfix.patch b/util/crossgcc/patches/binutils-2.32_stringfix.patch
-new file mode 100644
-index 0000000000..de27a2752a
---- /dev/null
-+++ b/util/crossgcc/patches/binutils-2.32_stringfix.patch
-@@ -0,0 +1,11 @@
-+diff -u binutils-2.32/gold/errors.h binutils-2.32.patched/gold/errors.h
-+--- binutils-2.32/gold/errors.h
-++++ binutils-2.32.patched/gold/errors.h
-+@@ -24,6 +24,7 @@
-+ #define GOLD_ERRORS_H
-+
-+ #include <cstdarg>
-++#include <string>
-+
-+ #include "gold-threads.h"
-+
--- 
-2.40.1
-

config/coreboot/fam15h_rdimm/patches/0009-fix-crossgcc-acpica-build-on-newer-hostcc.patch

@@ -1,108 +0,0 @@
-From 373dd351e374f391c9e2048e5f3e535267a04719 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 9 Jul 2023 19:37:39 +0100
-Subject: [PATCH 1/1] fix crossgcc/acpica build on newer hostcc
-
-Changes made to acpica/iasl:
-
-remove superfluous YYSTYPE declaration
-
-make LuxBuffer variables static, to avoid warnings
-treated as errors about multiple definitions
-
-AcpiGbl_DbOpt_NoRegionSupport - remove this definition
-in source/tools/acpiexec/aemain.c because it's already
-re-defined by acpiexec. otherwise the linker complains
-about multiple definitions
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- .../acpica-unix2-20190703_mitigategcc.patch   | 76 +++++++++++++++++++
- 1 file changed, 76 insertions(+)
- create mode 100644 util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
-
-diff --git a/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch b/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
-new file mode 100644
-index 0000000000..8de47245bd
---- /dev/null
-+++ b/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
-@@ -0,0 +1,76 @@
-+From 66b927d923183ff62c9a757fafdeca9d1ac3fa87 Mon Sep 17 00:00:00 2001
-+From: Leah Rowe <leah@libreboot.org>
-+Date: Sun, 9 Jul 2023 18:58:11 +0100
-+Subject: [PATCH 1/1] fix building on newer hostcc (debian sid tested)
-+
-+remove superfluous YYSTYPE declaration
-+
-+make LuxBuffer variables static, to avoid warnings
-+treated as errors about multiple definitions
-+
-+AcpiGbl_DbOpt_NoRegionSupport - remove this definition
-+in source/tools/acpiexec/aemain.c because it's already
-+re-defined by acpiexec. otherwise the linker complains
-+about multiple definitions
-+
-+Signed-off-by: Leah Rowe <leah@libreboot.org>
-+---
-+ source/compiler/aslcompiler.l  | 1 -
-+ source/compiler/dtparser.l     | 2 +-
-+ source/compiler/prparser.l     | 2 +-
-+ source/tools/acpiexec/aemain.c | 1 -
-+ 4 files changed, 2 insertions(+), 4 deletions(-)
-+
-+diff --git a/source/compiler/aslcompiler.l b/source/compiler/aslcompiler.l
-+index 1949b32..a24f028 100644
-+--- a/source/compiler/aslcompiler.l
-++++ b/source/compiler/aslcompiler.l
-+@@ -48,7 +48,6 @@
-+ 
-+ #include <stdlib.h>
-+ #include <string.h>
-+-YYSTYPE AslCompilerlval;
-+ 
-+ /*
-+  * Generation:  Use the following command line:
-+diff --git a/source/compiler/dtparser.l b/source/compiler/dtparser.l
-+index 6517e52..d35181c 100644
-+--- a/source/compiler/dtparser.l
-++++ b/source/compiler/dtparser.l
-+@@ -100,7 +100,7 @@ NewLine         [\n]
-+ /*
-+  * Local support functions
-+  */
-+-YY_BUFFER_STATE         LexBuffer;
-++static YY_BUFFER_STATE         LexBuffer;
-+ 
-+ /******************************************************************************
-+  *
-+diff --git a/source/compiler/prparser.l b/source/compiler/prparser.l
-+index bcdef14..5a1b848 100644
-+--- a/source/compiler/prparser.l
-++++ b/source/compiler/prparser.l
-+@@ -116,7 +116,7 @@ Identifier      [a-zA-Z][0-9a-zA-Z]*
-+ /*
-+  * Local support functions
-+  */
-+-YY_BUFFER_STATE         LexBuffer;
-++static YY_BUFFER_STATE         LexBuffer;
-+ 
-+ 
-+ /******************************************************************************
-+diff --git a/source/tools/acpiexec/aemain.c b/source/tools/acpiexec/aemain.c
-+index 58640dd..cd0add6 100644
-+--- a/source/tools/acpiexec/aemain.c
-++++ b/source/tools/acpiexec/aemain.c
-+@@ -84,7 +84,6 @@ BOOLEAN                     AcpiGbl_VerboseHandlers = FALSE;
-+ UINT8                       AcpiGbl_RegionFillValue = 0;
-+ BOOLEAN                     AcpiGbl_IgnoreErrors = FALSE;
-+ BOOLEAN                     AcpiGbl_AbortLoopOnTimeout = FALSE;
-+-BOOLEAN                     AcpiGbl_DbOpt_NoRegionSupport = FALSE;
-+ UINT8                       AcpiGbl_UseHwReducedFadt = FALSE;
-+ BOOLEAN                     AcpiGbl_DoInterfaceTests = FALSE;
-+ BOOLEAN                     AcpiGbl_LoadTestTables = FALSE;
-+-- 
-+2.40.1
-+
--- 
-2.40.1
-

config/coreboot/fam15h_rdimm/patches/0010-coreboot-fam15h-use-new-upstream-for-acpica.patch

@@ -1,38 +0,0 @@
-From ba94a3f27a26d181291b5908bdd627be375eb606 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 16 Jul 2023 00:44:22 +0100
-Subject: [PATCH 1/1] coreboot/fam15h: use new upstream for acpica
-
-the original upstream died
-
-i decided to host it myself, on libreboot rsync,
-for use by mirrors.
-
-this is also useful for GNU Boot, when downloading
-acpica on coreboot 4.11_branch, for fam15h boards
-
-this change is not necessary on other coreboot trees,
-which adhere to new coreboot policy (newer coreboot
-pulls acpica from github, which is fairly reliable)
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/crossgcc/buildgcc | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index b75b90a877..e3efa722f1 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -73,7 +73,7 @@ MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
- GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
- BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
- GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
--IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
-+IASL_ARCHIVE="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
- PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
- EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
- # CLANG toolchain archive locations
--- 
-2.40.1
-

config/coreboot/fam15h_rdimm/target.cfg

@@ -1,9 +0,0 @@
-tree="fam15h_rdimm"
-romtype="normal"
-rev="1c13f8d85c7306213cd525308ee8973e5663a3f8"
-arch="x86_64"
-payload_grub="n"
-payload_grub_withseabios="n"
-payload_seabios="n"
-payload_memtest="n"
-crossgcc_ada="n"

config/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch

@@ -1,31 +0,0 @@
-From 8f2988cba4fffef1bd4f65e123c76bf4b7a18672 Mon Sep 17 00:00:00 2001
-From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
-Date: Sun, 7 Feb 2021 15:29:40 +0100
-Subject: [PATCH 1/6] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training
- failure on Fam15h" (fixes a bug that prevent certain RAM modules from
- booting)
-
-This reverts commit 610d1c67b2298a9840681c2b4492b6d3fdf44a46.
-
-After 610d1c67b2298a9840681c2b4492b6d3fdf44a46 many RAM modules wouldn't work and you couldn't even see any output on the screen.
----
- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
-index ddaaaab8d5..3b07786b91 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
-@@ -71,6 +71,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
- 		misc2 |= ((cs_mux_67 & 0x1) << 27);
- 		misc2 &= ~(0x1 << 26);		/* CsMux45 = cs_mux_45 */
- 		misc2 |= ((cs_mux_45 & 0x1) << 26);
-+
-+		if (pDCTstat->Status & (1 << SB_Registered))
-+			misc2 |= 1 << SubMemclkRegDly;
- 	} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
- 		if (pDCTstat->Status & (1 << SB_Registered)) {
- 			misc2 |= 1 << SubMemclkRegDly;
--- 
-2.25.1
-

config/coreboot/fam15h_udimm/patches/0003-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch

@@ -1,38 +0,0 @@
-From 7a00638cea41ad939a59fc0e5996959435fbdb7f Mon Sep 17 00:00:00 2001
-From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
-Date: Sun, 7 Feb 2021 16:40:05 +0100
-Subject: [PATCH 3/6] Tweak cmos defaults for KCMA-D8 (for a little speed
- boost)
-
-63xx CPUs have the option to use a reduced latency value inside the crossbar.
-Setting "experimental_memory_speed_boost=Enable" aparently only has an effect
-on 63xx CPUs and may, in certain cases, yield a slight memory bandwidth
-increase (according to Timothy Pearson), but maybe it also works for
-43xx CPUs.
-
-Setting "l3_cache_partitioning=Enable" will increase performance in certain
-situations. See:
-https://developer.arm.com/documentation/100453/0401/functional-description/l3-cache/l3-cache-partitioning?lang=en
----
- src/mainboard/asus/kcma-d8/cmos.default | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default
-index 306687157f..4e033d756f 100644
---- a/src/mainboard/asus/kcma-d8/cmos.default
-+++ b/src/mainboard/asus/kcma-d8/cmos.default
-@@ -21,9 +21,9 @@ sata_ahci_mode=Enable
- sata_alpm=Disable
- maximum_p_state_limit=0xf
- probe_filter=Auto
--l3_cache_partitioning=Disable
-+l3_cache_partitioning=Enable
- gart=Enable
- ehci_async_data_cache=Enable
--experimental_memory_speed_boost=Disable
-+experimental_memory_speed_boost=Enable
- power_on_after_fail=On
- boot_option=Fallback
--- 
-2.25.1
-

config/coreboot/fam15h_udimm/patches/0006-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch

@@ -1,32 +0,0 @@
-From f0aac7261e16adc8e61eca7a506ff2de5112be47 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Fri, 7 May 2021 19:43:32 +0100
-Subject: [PATCH 6/6] asus/kgpe-d16: enable lc_cache_partitioning and
- experimental_memory_speed_boost
-
-This really only benefits 63xx opterons which are less reliable in libreboot due
-to lack of CPU microcode updates, but we might aswell enable this anyway.
----
- src/mainboard/asus/kgpe-d16/cmos.default | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
-index 7c496a50d7..8a25620e1d 100644
---- a/src/mainboard/asus/kgpe-d16/cmos.default
-+++ b/src/mainboard/asus/kgpe-d16/cmos.default
-@@ -21,10 +21,10 @@ sata_ahci_mode=Enable
- sata_alpm=Disable
- maximum_p_state_limit=0xf
- probe_filter=Auto
--l3_cache_partitioning=Disable
-+l3_cache_partitioning=Enable
- ieee1394_controller=Enable
- gart=Enable
- ehci_async_data_cache=Enable
--experimental_memory_speed_boost=Disable
-+experimental_memory_speed_boost=Enable
- power_on_after_fail=On
- boot_option=Fallback
--- 
-2.25.1
-

config/coreboot/fam15h_udimm/patches/0007-util-cbfstool-Makefile-support-distclean.patch

@@ -1,41 +0,0 @@
-From d5dc3f23eb546cf328fdfe1e918afa028fb9cd8c Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 9 Jul 2023 04:13:52 +0100
-Subject: [PATCH 1/1] util/cbfstool Makefile: support distclean
-
-it just does make-clean
-
-this is so that this super-old coreboot revision
-interfaces well with lbmk, which runs distclean
-on cbfstool (which is supported, on modern cbfstool)
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/cbfstool/Makefile | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
-index d5321f6959..b8424d7d87 100644
---- a/util/cbfstool/Makefile
-+++ b/util/cbfstool/Makefile
-@@ -26,7 +26,7 @@ ifittool: $(objutil)/cbfstool/ifittool
- 
- cbfs-compression-tool: $(objutil)/cbfstool/cbfs-compression-tool
- 
--.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool
-+.PHONY: distclean clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool
- clean:
- 	$(RM) fmd_parser.c fmd_parser.h fmd_scanner.c fmd_scanner.h
- 	$(RM) $(objutil)/cbfstool/cbfstool $(cbfsobj)
-@@ -55,6 +55,8 @@ install: all
- 	$(INSTALL) ifittool $(DESTDIR)$(BINDIR)
- 	$(INSTALL) cbfs-compression-tool $(DESTDIR)$(BINDIR)
- 
-+distclean: clean
-+
- ifneq ($(V),1)
- .SILENT:
- endif
--- 
-2.40.1
-

config/coreboot/fam15h_udimm/patches/0008-crossgcc-patch-binutils-2.32-for-newer-hostcc.patch

@@ -1,37 +0,0 @@
-From 4b4b2bdc2cedb3e219c6f90809e5684441b1dafa Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 9 Jul 2023 04:54:19 +0100
-Subject: [PATCH 1/1] crossgcc: patch binutils 2.32 for newer hostcc
-
-tested on debian sid as of 9 July 2023
-
-implicit string declaration
-
-easy peasy
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/crossgcc/patches/binutils-2.32_stringfix.patch | 11 +++++++++++
- 1 file changed, 11 insertions(+)
- create mode 100644 util/crossgcc/patches/binutils-2.32_stringfix.patch
-
-diff --git a/util/crossgcc/patches/binutils-2.32_stringfix.patch b/util/crossgcc/patches/binutils-2.32_stringfix.patch
-new file mode 100644
-index 0000000000..de27a2752a
---- /dev/null
-+++ b/util/crossgcc/patches/binutils-2.32_stringfix.patch
-@@ -0,0 +1,11 @@
-+diff -u binutils-2.32/gold/errors.h binutils-2.32.patched/gold/errors.h
-+--- binutils-2.32/gold/errors.h
-++++ binutils-2.32.patched/gold/errors.h
-+@@ -24,6 +24,7 @@
-+ #define GOLD_ERRORS_H
-+
-+ #include <cstdarg>
-++#include <string>
-+
-+ #include "gold-threads.h"
-+
--- 
-2.40.1
-

config/coreboot/fam15h_udimm/patches/0009-fix-crossgcc-acpica-build-on-newer-hostcc.patch

@@ -1,108 +0,0 @@
-From 373dd351e374f391c9e2048e5f3e535267a04719 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 9 Jul 2023 19:37:39 +0100
-Subject: [PATCH 1/1] fix crossgcc/acpica build on newer hostcc
-
-Changes made to acpica/iasl:
-
-remove superfluous YYSTYPE declaration
-
-make LuxBuffer variables static, to avoid warnings
-treated as errors about multiple definitions
-
-AcpiGbl_DbOpt_NoRegionSupport - remove this definition
-in source/tools/acpiexec/aemain.c because it's already
-re-defined by acpiexec. otherwise the linker complains
-about multiple definitions
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- .../acpica-unix2-20190703_mitigategcc.patch   | 76 +++++++++++++++++++
- 1 file changed, 76 insertions(+)
- create mode 100644 util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
-
-diff --git a/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch b/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
-new file mode 100644
-index 0000000000..8de47245bd
---- /dev/null
-+++ b/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
-@@ -0,0 +1,76 @@
-+From 66b927d923183ff62c9a757fafdeca9d1ac3fa87 Mon Sep 17 00:00:00 2001
-+From: Leah Rowe <leah@libreboot.org>
-+Date: Sun, 9 Jul 2023 18:58:11 +0100
-+Subject: [PATCH 1/1] fix building on newer hostcc (debian sid tested)
-+
-+remove superfluous YYSTYPE declaration
-+
-+make LuxBuffer variables static, to avoid warnings
-+treated as errors about multiple definitions
-+
-+AcpiGbl_DbOpt_NoRegionSupport - remove this definition
-+in source/tools/acpiexec/aemain.c because it's already
-+re-defined by acpiexec. otherwise the linker complains
-+about multiple definitions
-+
-+Signed-off-by: Leah Rowe <leah@libreboot.org>
-+---
-+ source/compiler/aslcompiler.l  | 1 -
-+ source/compiler/dtparser.l     | 2 +-
-+ source/compiler/prparser.l     | 2 +-
-+ source/tools/acpiexec/aemain.c | 1 -
-+ 4 files changed, 2 insertions(+), 4 deletions(-)
-+
-+diff --git a/source/compiler/aslcompiler.l b/source/compiler/aslcompiler.l
-+index 1949b32..a24f028 100644
-+--- a/source/compiler/aslcompiler.l
-++++ b/source/compiler/aslcompiler.l
-+@@ -48,7 +48,6 @@
-+ 
-+ #include <stdlib.h>
-+ #include <string.h>
-+-YYSTYPE AslCompilerlval;
-+ 
-+ /*
-+  * Generation:  Use the following command line:
-+diff --git a/source/compiler/dtparser.l b/source/compiler/dtparser.l
-+index 6517e52..d35181c 100644
-+--- a/source/compiler/dtparser.l
-++++ b/source/compiler/dtparser.l
-+@@ -100,7 +100,7 @@ NewLine         [\n]
-+ /*
-+  * Local support functions
-+  */
-+-YY_BUFFER_STATE         LexBuffer;
-++static YY_BUFFER_STATE         LexBuffer;
-+ 
-+ /******************************************************************************
-+  *
-+diff --git a/source/compiler/prparser.l b/source/compiler/prparser.l
-+index bcdef14..5a1b848 100644
-+--- a/source/compiler/prparser.l
-++++ b/source/compiler/prparser.l
-+@@ -116,7 +116,7 @@ Identifier      [a-zA-Z][0-9a-zA-Z]*
-+ /*
-+  * Local support functions
-+  */
-+-YY_BUFFER_STATE         LexBuffer;
-++static YY_BUFFER_STATE         LexBuffer;
-+ 
-+ 
-+ /******************************************************************************
-+diff --git a/source/tools/acpiexec/aemain.c b/source/tools/acpiexec/aemain.c
-+index 58640dd..cd0add6 100644
-+--- a/source/tools/acpiexec/aemain.c
-++++ b/source/tools/acpiexec/aemain.c
-+@@ -84,7 +84,6 @@ BOOLEAN                     AcpiGbl_VerboseHandlers = FALSE;
-+ UINT8                       AcpiGbl_RegionFillValue = 0;
-+ BOOLEAN                     AcpiGbl_IgnoreErrors = FALSE;
-+ BOOLEAN                     AcpiGbl_AbortLoopOnTimeout = FALSE;
-+-BOOLEAN                     AcpiGbl_DbOpt_NoRegionSupport = FALSE;
-+ UINT8                       AcpiGbl_UseHwReducedFadt = FALSE;
-+ BOOLEAN                     AcpiGbl_DoInterfaceTests = FALSE;
-+ BOOLEAN                     AcpiGbl_LoadTestTables = FALSE;
-+-- 
-+2.40.1
-+
--- 
-2.40.1
-

config/coreboot/fam15h_udimm/patches/0010-coreboot-fam15h-use-new-upstream-for-acpica.patch

@@ -1,38 +0,0 @@
-From ba94a3f27a26d181291b5908bdd627be375eb606 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 16 Jul 2023 00:44:22 +0100
-Subject: [PATCH 1/1] coreboot/fam15h: use new upstream for acpica
-
-the original upstream died
-
-i decided to host it myself, on libreboot rsync,
-for use by mirrors.
-
-this is also useful for GNU Boot, when downloading
-acpica on coreboot 4.11_branch, for fam15h boards
-
-this change is not necessary on other coreboot trees,
-which adhere to new coreboot policy (newer coreboot
-pulls acpica from github, which is fairly reliable)
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/crossgcc/buildgcc | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index b75b90a877..e3efa722f1 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -73,7 +73,7 @@ MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
- GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
- BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
- GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
--IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
-+IASL_ARCHIVE="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
- PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
- EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
- # CLANG toolchain archive locations
--- 
-2.40.1
-

config/coreboot/fam15h_udimm/target.cfg

@@ -1,9 +0,0 @@
-tree="fam15h_udimm"
-romtype="normal"
-rev="1c13f8d85c7306213cd525308ee8973e5663a3f8"
-arch="x86_64"
-payload_grub="n"
-payload_grub_withseabios="n"
-payload_seabios="n"
-payload_memtest="n"
-crossgcc_ada="n"

config/coreboot/g43t-am3/config/libgfxinit_txtmode

@@ -1,571 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-CONFIG_VENDOR_ACER=y
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="G43T-AM3"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="acer/g43t-am3"
-CONFIG_VGA_BIOS_ID="8086,2e22"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Acer"
-# CONFIG_BOARD_ACER_VN7_572G is not set
-CONFIG_BOARD_ACER_G43T_AM3=y
-CONFIG_CBFS_SIZE=0x200000
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Acer"
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfeff8000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="G43T-AM3"
-# CONFIG_HAVE_IFD_BIN is not set
-CONFIG_PCIEXP_HOTPLUG_BUSES=32
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_2048=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_2048=y
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=2048
-CONFIG_ROM_SIZE=0x00200000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_MODEL_F3X=y
-CONFIG_CPU_INTEL_MODEL_F4X=y
-CONFIG_CPU_INTEL_SOCKET_LGA775=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_X4X=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
-CONFIG_SUPERIO_ITE_ENV_CTRL=y
-CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
-CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
-CONFIG_SUPERIO_ITE_IT8720F=y
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_NULL=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/g43t-am3/target.cfg

@@ -1,8 +0,0 @@
-tree="default"
-romtype="normal"
-arch="x86_64"
-payload_seabios="y"
-payload_memtest="y"
-microcode_required="n"
-vendorfiles="n"
-grub_timeout=10

config/coreboot/g43t-am3_16mb/config/libgfxinit_txtmode

@@ -1,571 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-CONFIG_VENDOR_ACER=y
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="G43T-AM3"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="acer/g43t-am3"
-CONFIG_VGA_BIOS_ID="8086,2e22"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Acer"
-# CONFIG_BOARD_ACER_VN7_572G is not set
-CONFIG_BOARD_ACER_G43T_AM3=y
-CONFIG_CBFS_SIZE=0x1000000
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Acer"
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfeff8000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="G43T-AM3"
-# CONFIG_HAVE_IFD_BIN is not set
-CONFIG_PCIEXP_HOTPLUG_BUSES=32
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_2048=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_MODEL_F3X=y
-CONFIG_CPU_INTEL_MODEL_F4X=y
-CONFIG_CPU_INTEL_SOCKET_LGA775=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_X4X=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
-CONFIG_SUPERIO_ITE_ENV_CTRL=y
-CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
-CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
-CONFIG_SUPERIO_ITE_IT8720F=y
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_NULL=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/g43t-am3_16mb/target.cfg

@@ -1,8 +0,0 @@
-tree="default"
-romtype="normal"
-arch="x86_64"
-payload_seabios="y"
-payload_memtest="y"
-microcode_required="n"
-vendorfiles="n"
-grub_timeout=10

config/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode

@@ -1,578 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-CONFIG_VENDOR_GIGABYTE=y
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="GA-G41M-ES2L"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="gigabyte/ga-g41m-es2l"
-CONFIG_VGA_BIOS_ID="8086,2e32"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="GIGABYTE"
-CONFIG_CBFS_SIZE=0x00100000
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="GIGABYTE"
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfeff8000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-# CONFIG_BOARD_GIGABYTE_GA_945GCM_S2L is not set
-# CONFIG_BOARD_GIGABYTE_GA_945GCM_S2C is not set
-# CONFIG_BOARD_GIGABYTE_GA_B75M_D3H is not set
-# CONFIG_BOARD_GIGABYTE_GA_B75M_D3V is not set
-# CONFIG_BOARD_GIGABYTE_GA_B75_D3V is not set
-# CONFIG_BOARD_GIGABYTE_GA_D510UD is not set
-CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y
-# CONFIG_BOARD_GIGABYTE_GA_H61M_S2PV is not set
-# CONFIG_BOARD_GIGABYTE_GA_H61M_DS2 is not set
-# CONFIG_BOARD_GIGABYTE_GA_H61M_DS2V is not set
-# CONFIG_BOARD_GIGABYTE_GA_H61MA_D3V is not set
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="GA-G41M-ES2L"
-CONFIG_PCIEXP_HOTPLUG_BUSES=32
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-CONFIG_PCIEXP_L1_SUB_STATE=y
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_BOARD_ROMSIZE_KB_1024=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_1024=y
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=1024
-CONFIG_ROM_SIZE=0x00100000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_INTEL_HAS_TOP_SWAP=y
-# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
-CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_MODEL_F3X=y
-CONFIG_CPU_INTEL_MODEL_F4X=y
-CONFIG_CPU_INTEL_SOCKET_LGA775=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_X4X=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
-CONFIG_SUPERIO_ITE_ENV_CTRL=y
-CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
-CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
-CONFIG_SUPERIO_ITE_IT8718F=y
-
-#
-# Embedded Controllers
-#
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
-CONFIG_REALTEK_8168_RESET=y
-CONFIG_REALTEK_8168_MACADDRESS="00:e0:4c:00:c0:b0"
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_NULL=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/ga-g41m-es2l/target.cfg

@@ -1,9 +0,0 @@
-tree="default"
-romtype="normal"
-arch="x86_64"
-payload_seabios="y"
-payload_memtest="y"
-grub_scan_disk="ata"
-microcode_required="n"
-vendorfiles="n"
-grub_timeout=10

config/coreboot/gru_bob/config/libgfxinit_corebootfb

@@ -1,950 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_ALLOW_EXPERIMENTAL_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-CONFIG_OPTION_BACKEND_NONE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_COMPRESS_PRERAM_STAGES=y
-CONFIG_COMPRESS_BOOTBLOCK=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-# CONFIG_COLLECT_TIMESTAMPS is not set
-# CONFIG_USE_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_CBMEM_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-CONFIG_VENDOR_GOOGLE=y
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Bob"
-CONFIG_MAINBOARD_DIR="google/gru"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Google"
-CONFIG_CBFS_SIZE=0x00800000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_MAX_CPUS=1
-CONFIG_POST_DEVICE=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_CHROMEOS is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=1
-CONFIG_CONSOLE_SERIAL_UART_ADDRESS=0xFF1A0000
-# CONFIG_CONSOLE_POST is not set
-CONFIG_MEMLAYOUT_LD_FILE="src/soc/rockchip/rk3399/memlayout.ld"
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_SPI_FLASH_WINBOND=y
-
-#
-# Asurada
-#
-# CONFIG_BOARD_GOOGLE_ASURADA is not set
-# CONFIG_BOARD_GOOGLE_HAYATO is not set
-# CONFIG_BOARD_GOOGLE_SPHERION is not set
-
-#
-# Auron
-#
-# CONFIG_BOARD_GOOGLE_AURON_PAINE is not set
-# CONFIG_BOARD_GOOGLE_AURON_YUNA is not set
-# CONFIG_BOARD_GOOGLE_BUDDY is not set
-# CONFIG_BOARD_GOOGLE_GANDOF is not set
-# CONFIG_BOARD_GOOGLE_LULU is not set
-# CONFIG_BOARD_GOOGLE_SAMUS is not set
-
-#
-# Beltino
-#
-# CONFIG_BOARD_GOOGLE_MCCLOUD is not set
-# CONFIG_BOARD_GOOGLE_MONROE is not set
-# CONFIG_BOARD_GOOGLE_PANTHER is not set
-# CONFIG_BOARD_GOOGLE_TRICKY is not set
-# CONFIG_BOARD_GOOGLE_ZAKO is not set
-
-#
-# Brya
-#
-# CONFIG_BOARD_GOOGLE_AGAH is not set
-# CONFIG_BOARD_GOOGLE_ANAHERA is not set
-# CONFIG_BOARD_GOOGLE_ANAHERA4ES is not set
-# CONFIG_BOARD_GOOGLE_AURASH is not set
-# CONFIG_BOARD_GOOGLE_BANSHEE is not set
-# CONFIG_BOARD_GOOGLE_BRASK is not set
-# CONFIG_BOARD_GOOGLE_BRYA0 is not set
-# CONFIG_BOARD_GOOGLE_CRAASK is not set
-# CONFIG_BOARD_GOOGLE_CRAASKOV is not set
-# CONFIG_BOARD_GOOGLE_CONSTITUTION is not set
-# CONFIG_BOARD_GOOGLE_CROTA is not set
-# CONFIG_BOARD_GOOGLE_FELWINTER is not set
-# CONFIG_BOARD_GOOGLE_GAELIN is not set
-# CONFIG_BOARD_GOOGLE_GIMBLE is not set
-# CONFIG_BOARD_GOOGLE_GIMBLE4ES is not set
-# CONFIG_BOARD_GOOGLE_GLADIOS is not set
-# CONFIG_BOARD_GOOGLE_GOTHRAX is not set
-# CONFIG_BOARD_GOOGLE_HADES is not set
-# CONFIG_BOARD_GOOGLE_KANO is not set
-# CONFIG_BOARD_GOOGLE_KINOX is not set
-# CONFIG_BOARD_GOOGLE_KULDAX is not set
-# CONFIG_BOARD_GOOGLE_JOXER is not set
-# CONFIG_BOARD_GOOGLE_LISBON is not set
-# CONFIG_BOARD_GOOGLE_MARASOV is not set
-# CONFIG_BOARD_GOOGLE_MITHRAX is not set
-# CONFIG_BOARD_GOOGLE_MOLI is not set
-# CONFIG_BOARD_GOOGLE_NIVVIKS is not set
-# CONFIG_BOARD_GOOGLE_NEREID is not set
-# CONFIG_BOARD_GOOGLE_OMNIGUL is not set
-# CONFIG_BOARD_GOOGLE_OSIRIS is not set
-# CONFIG_BOARD_GOOGLE_PIRRHA is not set
-# CONFIG_BOARD_GOOGLE_PRIMUS is not set
-# CONFIG_BOARD_GOOGLE_PRIMUS4ES is not set
-# CONFIG_BOARD_GOOGLE_PUJJO is not set
-# CONFIG_BOARD_GOOGLE_QUANDISO is not set
-# CONFIG_BOARD_GOOGLE_REDRIX is not set
-# CONFIG_BOARD_GOOGLE_REDRIX4ES is not set
-# CONFIG_BOARD_GOOGLE_SKOLAS is not set
-# CONFIG_BOARD_GOOGLE_SKOLAS4ES is not set
-# CONFIG_BOARD_GOOGLE_TAEKO is not set
-# CONFIG_BOARD_GOOGLE_TAEKO4ES is not set
-# CONFIG_BOARD_GOOGLE_TANIKS is not set
-# CONFIG_BOARD_GOOGLE_ULDREN is not set
-# CONFIG_BOARD_GOOGLE_VELL is not set
-# CONFIG_BOARD_GOOGLE_VOLMAR is not set
-# CONFIG_BOARD_GOOGLE_XIVU is not set
-# CONFIG_BOARD_GOOGLE_YAVIKS is not set
-# CONFIG_BOARD_GOOGLE_YAVILLA is not set
-# CONFIG_BOARD_GOOGLE_ZYDRON is not set
-# CONFIG_BOARD_GOOGLE_NOKRIS is not set
-# CONFIG_BOARD_GOOGLE_DOCHI is not set
-
-#
-# Butterfly
-#
-# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set
-
-#
-# Cherry
-#
-# CONFIG_BOARD_GOOGLE_CHERRY is not set
-# CONFIG_BOARD_GOOGLE_DOJO is not set
-# CONFIG_BOARD_GOOGLE_TOMATO is not set
-
-#
-# Kingler
-#
-# CONFIG_BOARD_GOOGLE_KINGLER is not set
-# CONFIG_BOARD_GOOGLE_STEELIX is not set
-# CONFIG_BOARD_GOOGLE_VOLTORB is not set
-# CONFIG_BOARD_GOOGLE_PONYTA is not set
-
-#
-# Krabby
-#
-# CONFIG_BOARD_GOOGLE_KRABBY is not set
-# CONFIG_BOARD_GOOGLE_TENTACRUEL is not set
-# CONFIG_BOARD_GOOGLE_MAGIKARP is not set
-
-#
-# Staryu
-#
-# CONFIG_BOARD_GOOGLE_STARMIE is not set
-
-#
-# Cyan
-#
-# CONFIG_BOARD_GOOGLE_BANON is not set
-# CONFIG_BOARD_GOOGLE_CELES is not set
-# CONFIG_BOARD_GOOGLE_CYAN is not set
-# CONFIG_BOARD_GOOGLE_EDGAR is not set
-# CONFIG_BOARD_GOOGLE_KEFKA is not set
-# CONFIG_BOARD_GOOGLE_REKS is not set
-# CONFIG_BOARD_GOOGLE_RELM is not set
-# CONFIG_BOARD_GOOGLE_SETZER is not set
-# CONFIG_BOARD_GOOGLE_TERRA is not set
-# CONFIG_BOARD_GOOGLE_ULTIMA is not set
-# CONFIG_BOARD_GOOGLE_WIZPIG is not set
-
-#
-# Daisy
-#
-# CONFIG_BOARD_GOOGLE_DAISY is not set
-
-#
-# Dedede
-#
-# CONFIG_BOARD_GOOGLE_BOTEN is not set
-# CONFIG_BOARD_GOOGLE_DIBBI is not set
-# CONFIG_BOARD_GOOGLE_DEDEDE is not set
-# CONFIG_BOARD_GOOGLE_DRAWCIA is not set
-# CONFIG_BOARD_GOOGLE_HABOKI is not set
-# CONFIG_BOARD_GOOGLE_MADOO is not set
-# CONFIG_BOARD_GOOGLE_WADDLEDOO is not set
-# CONFIG_BOARD_GOOGLE_WADDLEDEE is not set
-# CONFIG_BOARD_GOOGLE_LALALA is not set
-# CONFIG_BOARD_GOOGLE_MAGOLOR is not set
-# CONFIG_BOARD_GOOGLE_METAKNIGHT is not set
-# CONFIG_BOARD_GOOGLE_LANTIS is not set
-# CONFIG_BOARD_GOOGLE_GALTIC is not set
-# CONFIG_BOARD_GOOGLE_SASUKE is not set
-# CONFIG_BOARD_GOOGLE_STORO is not set
-# CONFIG_BOARD_GOOGLE_SASUKETTE is not set
-# CONFIG_BOARD_GOOGLE_KRACKO is not set
-# CONFIG_BOARD_GOOGLE_BLIPPER is not set
-# CONFIG_BOARD_GOOGLE_CRET is not set
-# CONFIG_BOARD_GOOGLE_PIRIKA is not set
-# CONFIG_BOARD_GOOGLE_CAPPY2 is not set
-# CONFIG_BOARD_GOOGLE_BUGZZY is not set
-# CONFIG_BOARD_GOOGLE_CORORI is not set
-# CONFIG_BOARD_GOOGLE_DRIBLEE is not set
-# CONFIG_BOARD_GOOGLE_GOOEY is not set
-# CONFIG_BOARD_GOOGLE_BEADRIX is not set
-# CONFIG_BOARD_GOOGLE_SHOTZO is not set
-# CONFIG_BOARD_GOOGLE_TARANZA is not set
-# CONFIG_BOARD_GOOGLE_BOXY is not set
-# CONFIG_BOARD_GOOGLE_DEXI is not set
-
-#
-# Drallion
-#
-# CONFIG_BOARD_GOOGLE_DRALLION is not set
-
-#
-# Eve
-#
-# CONFIG_BOARD_GOOGLE_EVE is not set
-
-#
-# Fizz
-#
-# CONFIG_BOARD_GOOGLE_FIZZ is not set
-# CONFIG_BOARD_GOOGLE_KARMA is not set
-# CONFIG_BOARD_GOOGLE_ENDEAVOUR is not set
-
-#
-# Foster
-#
-# CONFIG_BOARD_GOOGLE_FOSTER is not set
-
-#
-# Gale
-#
-# CONFIG_BOARD_GOOGLE_GALE is not set
-
-#
-# Geralt
-#
-# CONFIG_BOARD_GOOGLE_GERALT is not set
-
-#
-# Glados
-#
-# CONFIG_BOARD_GOOGLE_ASUKA is not set
-# CONFIG_BOARD_GOOGLE_CAROLINE is not set
-# CONFIG_BOARD_GOOGLE_CAVE is not set
-# CONFIG_BOARD_GOOGLE_CHELL is not set
-# CONFIG_BOARD_GOOGLE_GLADOS is not set
-# CONFIG_BOARD_GOOGLE_LARS is not set
-# CONFIG_BOARD_GOOGLE_SENTRY is not set
-
-#
-# Gru
-#
-# CONFIG_BOARD_GOOGLE_KEVIN is not set
-# CONFIG_BOARD_GOOGLE_GRU is not set
-CONFIG_BOARD_GOOGLE_BOB=y
-# CONFIG_BOARD_GOOGLE_SCARLET is not set
-# CONFIG_BOARD_GOOGLE_NEFARIO is not set
-# CONFIG_BOARD_GOOGLE_RAINIER is not set
-
-#
-# Guybrush
-#
-# CONFIG_BOARD_GOOGLE_GUYBRUSH is not set
-# CONFIG_BOARD_GOOGLE_NIPPERKIN is not set
-# CONFIG_BOARD_GOOGLE_DEWATT is not set
-
-#
-# Hatch
-#
-# CONFIG_BOARD_GOOGLE_AKEMI is not set
-# CONFIG_BOARD_GOOGLE_DRATINI is not set
-# CONFIG_BOARD_GOOGLE_HATCH is not set
-# CONFIG_BOARD_GOOGLE_HELIOS is not set
-# CONFIG_BOARD_GOOGLE_HELIOS_DISKSWAP is not set
-# CONFIG_BOARD_GOOGLE_JINLON is not set
-# CONFIG_BOARD_GOOGLE_KINDRED is not set
-# CONFIG_BOARD_GOOGLE_KOHAKU is not set
-# CONFIG_BOARD_GOOGLE_MUSHU is not set
-# CONFIG_BOARD_GOOGLE_NIGHTFURY is not set
-# CONFIG_BOARD_GOOGLE_PALKIA is not set
-
-#
-# Herobrine
-#
-
-#
-# (Herobrine requires 'Allow QC blobs repository')
-#
-
-#
-# Jecht
-#
-# CONFIG_BOARD_GOOGLE_GUADO is not set
-# CONFIG_BOARD_GOOGLE_JECHT is not set
-# CONFIG_BOARD_GOOGLE_RIKKU is not set
-# CONFIG_BOARD_GOOGLE_TIDUS is not set
-
-#
-# Kahlee
-#
-# CONFIG_BOARD_GOOGLE_ALEENA is not set
-# CONFIG_BOARD_GOOGLE_CAREENA is not set
-# CONFIG_BOARD_GOOGLE_GRUNT is not set
-# CONFIG_BOARD_GOOGLE_LIARA is not set
-# CONFIG_BOARD_GOOGLE_NUWANI is not set
-# CONFIG_BOARD_GOOGLE_TREEYA is not set
-
-#
-# Kukui
-#
-# CONFIG_BOARD_GOOGLE_KUKUI is not set
-# CONFIG_BOARD_GOOGLE_KRANE is not set
-# CONFIG_BOARD_GOOGLE_KODAMA is not set
-# CONFIG_BOARD_GOOGLE_KAKADU is not set
-# CONFIG_BOARD_GOOGLE_FLAPJACK is not set
-# CONFIG_BOARD_GOOGLE_KATSU is not set
-
-#
-# Jacuzzi
-#
-# CONFIG_BOARD_GOOGLE_JACUZZI is not set
-# CONFIG_BOARD_GOOGLE_JUNIPER is not set
-# CONFIG_BOARD_GOOGLE_KAPPA is not set
-# CONFIG_BOARD_GOOGLE_DAMU is not set
-# CONFIG_BOARD_GOOGLE_CERISE is not set
-# CONFIG_BOARD_GOOGLE_STERN is not set
-# CONFIG_BOARD_GOOGLE_WILLOW is not set
-# CONFIG_BOARD_GOOGLE_ESCHE is not set
-# CONFIG_BOARD_GOOGLE_BURNET is not set
-# CONFIG_BOARD_GOOGLE_FENNEL is not set
-# CONFIG_BOARD_GOOGLE_COZMO is not set
-# CONFIG_BOARD_GOOGLE_MAKOMO is not set
-# CONFIG_BOARD_GOOGLE_MUNNA is not set
-# CONFIG_BOARD_GOOGLE_PICO is not set
-
-#
-# Link
-#
-# CONFIG_BOARD_GOOGLE_LINK is not set
-
-#
-# Mistral
-#
-# CONFIG_BOARD_GOOGLE_MISTRAL is not set
-
-#
-# Myst
-#
-# CONFIG_BOARD_GOOGLE_MYST is not set
-
-#
-# Nyan
-#
-# CONFIG_BOARD_GOOGLE_NYAN is not set
-
-#
-# Nyan Big
-#
-# CONFIG_BOARD_GOOGLE_NYAN_BIG is not set
-
-#
-# Nyan Blaze
-#
-# CONFIG_BOARD_GOOGLE_NYAN_BLAZE is not set
-
-#
-# Oak
-#
-# CONFIG_BOARD_GOOGLE_OAK is not set
-# CONFIG_BOARD_GOOGLE_ELM is not set
-# CONFIG_BOARD_GOOGLE_HANA is not set
-
-#
-# Octopus
-#
-# CONFIG_BOARD_GOOGLE_AMPTON is not set
-# CONFIG_BOARD_GOOGLE_BLOOG is not set
-# CONFIG_BOARD_GOOGLE_BOBBA is not set
-# CONFIG_BOARD_GOOGLE_CASTA is not set
-# CONFIG_BOARD_GOOGLE_DOOD is not set
-# CONFIG_BOARD_GOOGLE_FLEEX is not set
-# CONFIG_BOARD_GOOGLE_FOOB is not set
-# CONFIG_BOARD_GOOGLE_GARG is not set
-# CONFIG_BOARD_GOOGLE_LICK is not set
-# CONFIG_BOARD_GOOGLE_MEEP is not set
-# CONFIG_BOARD_GOOGLE_OCTOPUS is not set
-# CONFIG_BOARD_GOOGLE_PHASER is not set
-# CONFIG_BOARD_GOOGLE_YORP is not set
-
-#
-# Parrot
-#
-# CONFIG_BOARD_GOOGLE_PARROT is not set
-
-#
-# Peach Pit
-#
-# CONFIG_BOARD_GOOGLE_PEACH_PIT is not set
-
-#
-# Poppy
-#
-# CONFIG_BOARD_GOOGLE_ATLAS is not set
-# CONFIG_BOARD_GOOGLE_POPPY is not set
-# CONFIG_BOARD_GOOGLE_NAMI is not set
-# CONFIG_BOARD_GOOGLE_NAUTILUS is not set
-# CONFIG_BOARD_GOOGLE_NOCTURNE is not set
-# CONFIG_BOARD_GOOGLE_RAMMUS is not set
-# CONFIG_BOARD_GOOGLE_SORAKA is not set
-
-#
-# Puff
-#
-# CONFIG_BOARD_GOOGLE_AMBASSADOR is not set
-# CONFIG_BOARD_GOOGLE_DOOLY is not set
-# CONFIG_BOARD_GOOGLE_DUFFY_LEGACY is not set
-# CONFIG_BOARD_GOOGLE_DUFFY is not set
-# CONFIG_BOARD_GOOGLE_FAFFY is not set
-# CONFIG_BOARD_GOOGLE_GENESIS is not set
-# CONFIG_BOARD_GOOGLE_KAISA_LEGACY is not set
-# CONFIG_BOARD_GOOGLE_KAISA is not set
-# CONFIG_BOARD_GOOGLE_MOONBUGGY is not set
-# CONFIG_BOARD_GOOGLE_NOIBAT is not set
-# CONFIG_BOARD_GOOGLE_PUFF is not set
-# CONFIG_BOARD_GOOGLE_SCOUT is not set
-# CONFIG_BOARD_GOOGLE_WYVERN is not set
-
-#
-# Rambi
-#
-# CONFIG_BOARD_GOOGLE_BANJO is not set
-# CONFIG_BOARD_GOOGLE_CANDY is not set
-# CONFIG_BOARD_GOOGLE_CLAPPER is not set
-# CONFIG_BOARD_GOOGLE_ENGUARDE is not set
-# CONFIG_BOARD_GOOGLE_EXPRESSO is not set
-# CONFIG_BOARD_GOOGLE_GLIMMER is not set
-# CONFIG_BOARD_GOOGLE_GNAWTY is not set
-# CONFIG_BOARD_GOOGLE_HELI is not set
-# CONFIG_BOARD_GOOGLE_KIP is not set
-# CONFIG_BOARD_GOOGLE_NINJA is not set
-# CONFIG_BOARD_GOOGLE_ORCO is not set
-# CONFIG_BOARD_GOOGLE_QUAWKS is not set
-# CONFIG_BOARD_GOOGLE_SQUAWKS is not set
-# CONFIG_BOARD_GOOGLE_RAMBI is not set
-# CONFIG_BOARD_GOOGLE_SUMO is not set
-# CONFIG_BOARD_GOOGLE_SWANKY is not set
-# CONFIG_BOARD_GOOGLE_WINKY is not set
-
-#
-# Reef
-#
-# CONFIG_BOARD_GOOGLE_REEF is not set
-# CONFIG_BOARD_GOOGLE_PYRO is not set
-# CONFIG_BOARD_GOOGLE_SAND is not set
-# CONFIG_BOARD_GOOGLE_SNAPPY is not set
-# CONFIG_BOARD_GOOGLE_CORAL is not set
-
-#
-# Rex
-#
-# CONFIG_BOARD_GOOGLE_REX0 is not set
-# CONFIG_BOARD_GOOGLE_SCREEBO is not set
-# CONFIG_BOARD_GOOGLE_SCREEBO4ES is not set
-# CONFIG_BOARD_GOOGLE_KARIS is not set
-# CONFIG_BOARD_GOOGLE_KARIS4ES is not set
-# CONFIG_BOARD_GOOGLE_REX_EC_ISH is not set
-# CONFIG_BOARD_GOOGLE_OVIS is not set
-# CONFIG_BOARD_GOOGLE_OVIS4ES is not set
-# CONFIG_BOARD_GOOGLE_REX4ES is not set
-# CONFIG_BOARD_GOOGLE_REX4ES_EC_ISH is not set
-
-#
-# Sarien
-#
-# CONFIG_BOARD_GOOGLE_ARCADA is not set
-# CONFIG_BOARD_GOOGLE_SARIEN is not set
-
-#
-# Skyrim
-#
-# CONFIG_BOARD_GOOGLE_SKYRIM is not set
-# CONFIG_BOARD_GOOGLE_WINTERHOLD is not set
-# CONFIG_BOARD_GOOGLE_FROSTFLOW is not set
-# CONFIG_BOARD_GOOGLE_CRYSTALDRIFT is not set
-# CONFIG_BOARD_GOOGLE_MARKARTH is not set
-
-#
-# Slippy
-#
-# CONFIG_BOARD_GOOGLE_FALCO is not set
-# CONFIG_BOARD_GOOGLE_LEON is not set
-# CONFIG_BOARD_GOOGLE_PEPPY is not set
-# CONFIG_BOARD_GOOGLE_WOLF is not set
-
-#
-# Smaug
-#
-# CONFIG_BOARD_GOOGLE_SMAUG is not set
-
-#
-# Storm
-#
-# CONFIG_BOARD_GOOGLE_STORM is not set
-
-#
-# Stout
-#
-# CONFIG_BOARD_GOOGLE_STOUT is not set
-
-#
-# Trogdor
-#
-
-#
-# (Trogdor requires 'Allow QC blobs repository')
-#
-
-#
-# Veyron
-#
-# CONFIG_BOARD_GOOGLE_VEYRON_JAQ is not set
-# CONFIG_BOARD_GOOGLE_VEYRON_JERRY is not set
-# CONFIG_BOARD_GOOGLE_VEYRON_MIGHTY is not set
-# CONFIG_BOARD_GOOGLE_VEYRON_MINNIE is not set
-# CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY is not set
-
-#
-# Veyron Mickey
-#
-# CONFIG_BOARD_GOOGLE_VEYRON_MICKEY is not set
-
-#
-# Veyron Rialto
-#
-# CONFIG_BOARD_GOOGLE_VEYRON_RIALTO is not set
-
-#
-# Volteer
-#
-# CONFIG_BOARD_GOOGLE_CHRONICLER is not set
-# CONFIG_BOARD_GOOGLE_COLLIS is not set
-# CONFIG_BOARD_GOOGLE_COPANO is not set
-# CONFIG_BOARD_GOOGLE_DELBIN is not set
-# CONFIG_BOARD_GOOGLE_DROBIT is not set
-# CONFIG_BOARD_GOOGLE_ELDRID is not set
-# CONFIG_BOARD_GOOGLE_ELEMI is not set
-# CONFIG_BOARD_GOOGLE_HALVOR is not set
-# CONFIG_BOARD_GOOGLE_LINDAR is not set
-# CONFIG_BOARD_GOOGLE_MALEFOR is not set
-# CONFIG_BOARD_GOOGLE_TERRADOR is not set
-# CONFIG_BOARD_GOOGLE_TODOR is not set
-# CONFIG_BOARD_GOOGLE_TRONDO is not set
-# CONFIG_BOARD_GOOGLE_VOEMA is not set
-# CONFIG_BOARD_GOOGLE_VOLET is not set
-# CONFIG_BOARD_GOOGLE_VOLTEER is not set
-# CONFIG_BOARD_GOOGLE_VOLTEER2 is not set
-# CONFIG_BOARD_GOOGLE_VOLTEER2_TI50 is not set
-# CONFIG_BOARD_GOOGLE_VOXEL is not set
-
-#
-# Zork
-#
-# CONFIG_BOARD_GOOGLE_DALBOZ is not set
-# CONFIG_BOARD_GOOGLE_VILBOZ is not set
-# CONFIG_BOARD_GOOGLE_EZKINIL is not set
-# CONFIG_BOARD_GOOGLE_MORPHIUS is not set
-# CONFIG_BOARD_GOOGLE_TREMBYLE is not set
-# CONFIG_BOARD_GOOGLE_BERKNIP is not set
-# CONFIG_BOARD_GOOGLE_WOOMAX is not set
-# CONFIG_BOARD_GOOGLE_DIRINBOZ is not set
-# CONFIG_BOARD_GOOGLE_SHUBOZ is not set
-# CONFIG_BOARD_GOOGLE_GUMBOZ is not set
-CONFIG_DRIVER_TPM_SPI_BUS=0x0
-CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x5
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_DRIVER_TPM_I2C_BUS=0x0
-CONFIG_DRIVER_TPM_I2C_ADDR=0x20
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_PMIC_BUS=-1
-CONFIG_BOARD_GOOGLE_GRU_COMMON=y
-CONFIG_GRU_HAS_TPM2=y
-CONFIG_GRU_HAS_CENTERLOG_PWM=y
-CONFIG_GRU_HAS_WLAN_RESET=y
-CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME=""
-CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US=0
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_DRIVER_TPM_SPI_CHIP=0
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=8192
-CONFIG_ROM_SIZE=0x00800000
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_ARM64_BL31_EXTERNAL_FILE=""
-CONFIG_ARCH_ARMV8_EXTENSION=0
-CONFIG_STACK_SIZE=0x0
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_GENERIC_UDELAY=y
-CONFIG_SOC_ROCKCHIP_RK3399=y
-CONFIG_RK3399_SPREAD_SPECTRUM_DDR=y
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-
-#
-# Northbridge
-#
-
-#
-# Southbridge
-#
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_SUPPORTS_DPTF_TEVT=y
-CONFIG_EC_GOOGLE_CHROMEEC=y
-CONFIG_EC_GOOGLE_CHROMEEC_SPI=y
-CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP=0x0
-CONFIG_EC_GOOGLE_CHROMEEC_RTC=y
-CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_NONE=y
-# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL is not set
-# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN is not set
-CONFIG_MAINBOARD_HAS_CHROMEOS=y
-
-#
-# ChromeOS
-#
-# end of ChromeOS
-
-CONFIG_ARCH_ARM64=y
-CONFIG_ARCH_BOOTBLOCK_ARM64=y
-CONFIG_ARCH_VERSTAGE_ARM64=y
-CONFIG_ARCH_ROMSTAGE_ARM64=y
-CONFIG_ARCH_RAMSTAGE_ARM64=y
-CONFIG_ARCH_BOOTBLOCK_ARMV8_64=y
-CONFIG_ARCH_VERSTAGE_ARMV8_64=y
-CONFIG_ARCH_ROMSTAGE_ARMV8_64=y
-CONFIG_ARCH_RAMSTAGE_ARMV8_64=y
-CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE=y
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
-CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y
-CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_COMMON_CBFS_SPI_WRAPPER=y
-CONFIG_SPI_FLASH=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_TPM_INIT_RAMSTAGE=y
-CONFIG_DRIVERS_UART=y
-CONFIG_UART_OVERRIDE_REFCLK=y
-CONFIG_DRIVERS_UART_8250MEM=y
-CONFIG_DRIVERS_UART_8250MEM_32=y
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_SPI_TPM=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-CONFIG_TPM_GOOGLE=y
-CONFIG_TPM_GOOGLE_CR50=y
-CONFIG_TPM_GOOGLE_IMMEDIATELY_COMMIT_FW_SECDATA=y
-CONFIG_GOOGLE_TPM_IRQ_TIMEOUT_MS=10
-CONFIG_CR50_RESET_CLEAR_EC_AP_IDLE_FLAG=y
-
-#
-# Trusted Platform Module
-#
-# CONFIG_NO_TPM is not set
-CONFIG_TPM2=y
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM2=y
-# CONFIG_DEBUG_TPM is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-CONFIG_TPM_SETUP_HIBERNATE_ON_ERR=y
-
-#
-# Memory initialization
-#
-# end of Memory initialization
-
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_CUSTOM_MADT=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-
-#
-# memory mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-CONFIG_POST_DEVICE_NONE=y
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_MONOTONIC_TIMER=y
-
-#
-# System tables
-#
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-# end of Debugging
-
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_NO_XIP_EARLY_STAGES=y
-CONFIG_GENERIC_GPIO_LIB=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/gru_bob/target.cfg

@@ -1,6 +0,0 @@
-tree="default"
-romtype="normal"
-arch="AArch64"
-payload_uboot="y"
-vendorfiles="n"
-microcode_required="n"

config/coreboot/gru_kevin/config/libgfxinit_corebootfb

@@ -1,947 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_ALLOW_EXPERIMENTAL_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-CONFIG_OPTION_BACKEND_NONE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_COMPRESS_PRERAM_STAGES=y
-CONFIG_COMPRESS_BOOTBLOCK=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-# CONFIG_COLLECT_TIMESTAMPS is not set
-# CONFIG_USE_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_CBMEM_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-CONFIG_VENDOR_GOOGLE=y
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="Kevin"
-CONFIG_MAINBOARD_DIR="google/gru"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Google"
-CONFIG_CBFS_SIZE=0x00800000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_MAX_CPUS=1
-CONFIG_POST_DEVICE=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_CHROMEOS is not set
-CONFIG_OVERRIDE_DEVICETREE=""
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=1
-CONFIG_CONSOLE_SERIAL_UART_ADDRESS=0xFF1A0000
-# CONFIG_CONSOLE_POST is not set
-CONFIG_MEMLAYOUT_LD_FILE="src/soc/rockchip/rk3399/memlayout.ld"
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_SPI_FLASH_WINBOND=y
-
-#
-# Asurada
-#
-# CONFIG_BOARD_GOOGLE_ASURADA is not set
-# CONFIG_BOARD_GOOGLE_HAYATO is not set
-# CONFIG_BOARD_GOOGLE_SPHERION is not set
-
-#
-# Auron
-#
-# CONFIG_BOARD_GOOGLE_AURON_PAINE is not set
-# CONFIG_BOARD_GOOGLE_AURON_YUNA is not set
-# CONFIG_BOARD_GOOGLE_BUDDY is not set
-# CONFIG_BOARD_GOOGLE_GANDOF is not set
-# CONFIG_BOARD_GOOGLE_LULU is not set
-# CONFIG_BOARD_GOOGLE_SAMUS is not set
-
-#
-# Beltino
-#
-# CONFIG_BOARD_GOOGLE_MCCLOUD is not set
-# CONFIG_BOARD_GOOGLE_MONROE is not set
-# CONFIG_BOARD_GOOGLE_PANTHER is not set
-# CONFIG_BOARD_GOOGLE_TRICKY is not set
-# CONFIG_BOARD_GOOGLE_ZAKO is not set
-
-#
-# Brya
-#
-# CONFIG_BOARD_GOOGLE_AGAH is not set
-# CONFIG_BOARD_GOOGLE_ANAHERA is not set
-# CONFIG_BOARD_GOOGLE_ANAHERA4ES is not set
-# CONFIG_BOARD_GOOGLE_AURASH is not set
-# CONFIG_BOARD_GOOGLE_BANSHEE is not set
-# CONFIG_BOARD_GOOGLE_BRASK is not set
-# CONFIG_BOARD_GOOGLE_BRYA0 is not set
-# CONFIG_BOARD_GOOGLE_CRAASK is not set
-# CONFIG_BOARD_GOOGLE_CRAASKOV is not set
-# CONFIG_BOARD_GOOGLE_CONSTITUTION is not set
-# CONFIG_BOARD_GOOGLE_CROTA is not set
-# CONFIG_BOARD_GOOGLE_FELWINTER is not set
-# CONFIG_BOARD_GOOGLE_GAELIN is not set
-# CONFIG_BOARD_GOOGLE_GIMBLE is not set
-# CONFIG_BOARD_GOOGLE_GIMBLE4ES is not set
-# CONFIG_BOARD_GOOGLE_GLADIOS is not set
-# CONFIG_BOARD_GOOGLE_GOTHRAX is not set
-# CONFIG_BOARD_GOOGLE_HADES is not set
-# CONFIG_BOARD_GOOGLE_KANO is not set
-# CONFIG_BOARD_GOOGLE_KINOX is not set
-# CONFIG_BOARD_GOOGLE_KULDAX is not set
-# CONFIG_BOARD_GOOGLE_JOXER is not set
-# CONFIG_BOARD_GOOGLE_LISBON is not set
-# CONFIG_BOARD_GOOGLE_MARASOV is not set
-# CONFIG_BOARD_GOOGLE_MITHRAX is not set
-# CONFIG_BOARD_GOOGLE_MOLI is not set
-# CONFIG_BOARD_GOOGLE_NIVVIKS is not set
-# CONFIG_BOARD_GOOGLE_NEREID is not set
-# CONFIG_BOARD_GOOGLE_OMNIGUL is not set
-# CONFIG_BOARD_GOOGLE_OSIRIS is not set
-# CONFIG_BOARD_GOOGLE_PIRRHA is not set
-# CONFIG_BOARD_GOOGLE_PRIMUS is not set
-# CONFIG_BOARD_GOOGLE_PRIMUS4ES is not set
-# CONFIG_BOARD_GOOGLE_PUJJO is not set
-# CONFIG_BOARD_GOOGLE_QUANDISO is not set
-# CONFIG_BOARD_GOOGLE_REDRIX is not set
-# CONFIG_BOARD_GOOGLE_REDRIX4ES is not set
-# CONFIG_BOARD_GOOGLE_SKOLAS is not set
-# CONFIG_BOARD_GOOGLE_SKOLAS4ES is not set
-# CONFIG_BOARD_GOOGLE_TAEKO is not set
-# CONFIG_BOARD_GOOGLE_TAEKO4ES is not set
-# CONFIG_BOARD_GOOGLE_TANIKS is not set
-# CONFIG_BOARD_GOOGLE_ULDREN is not set
-# CONFIG_BOARD_GOOGLE_VELL is not set
-# CONFIG_BOARD_GOOGLE_VOLMAR is not set
-# CONFIG_BOARD_GOOGLE_XIVU is not set
-# CONFIG_BOARD_GOOGLE_YAVIKS is not set
-# CONFIG_BOARD_GOOGLE_YAVILLA is not set
-# CONFIG_BOARD_GOOGLE_ZYDRON is not set
-# CONFIG_BOARD_GOOGLE_NOKRIS is not set
-# CONFIG_BOARD_GOOGLE_DOCHI is not set
-
-#
-# Butterfly
-#
-# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set
-
-#
-# Cherry
-#
-# CONFIG_BOARD_GOOGLE_CHERRY is not set
-# CONFIG_BOARD_GOOGLE_DOJO is not set
-# CONFIG_BOARD_GOOGLE_TOMATO is not set
-
-#
-# Kingler
-#
-# CONFIG_BOARD_GOOGLE_KINGLER is not set
-# CONFIG_BOARD_GOOGLE_STEELIX is not set
-# CONFIG_BOARD_GOOGLE_VOLTORB is not set
-# CONFIG_BOARD_GOOGLE_PONYTA is not set
-
-#
-# Krabby
-#
-# CONFIG_BOARD_GOOGLE_KRABBY is not set
-# CONFIG_BOARD_GOOGLE_TENTACRUEL is not set
-# CONFIG_BOARD_GOOGLE_MAGIKARP is not set
-
-#
-# Staryu
-#
-# CONFIG_BOARD_GOOGLE_STARMIE is not set
-
-#
-# Cyan
-#
-# CONFIG_BOARD_GOOGLE_BANON is not set
-# CONFIG_BOARD_GOOGLE_CELES is not set
-# CONFIG_BOARD_GOOGLE_CYAN is not set
-# CONFIG_BOARD_GOOGLE_EDGAR is not set
-# CONFIG_BOARD_GOOGLE_KEFKA is not set
-# CONFIG_BOARD_GOOGLE_REKS is not set
-# CONFIG_BOARD_GOOGLE_RELM is not set
-# CONFIG_BOARD_GOOGLE_SETZER is not set
-# CONFIG_BOARD_GOOGLE_TERRA is not set
-# CONFIG_BOARD_GOOGLE_ULTIMA is not set
-# CONFIG_BOARD_GOOGLE_WIZPIG is not set
-
-#
-# Daisy
-#
-# CONFIG_BOARD_GOOGLE_DAISY is not set
-
-#
-# Dedede
-#
-# CONFIG_BOARD_GOOGLE_BOTEN is not set
-# CONFIG_BOARD_GOOGLE_DIBBI is not set
-# CONFIG_BOARD_GOOGLE_DEDEDE is not set
-# CONFIG_BOARD_GOOGLE_DRAWCIA is not set
-# CONFIG_BOARD_GOOGLE_HABOKI is not set
-# CONFIG_BOARD_GOOGLE_MADOO is not set
-# CONFIG_BOARD_GOOGLE_WADDLEDOO is not set
-# CONFIG_BOARD_GOOGLE_WADDLEDEE is not set
-# CONFIG_BOARD_GOOGLE_LALALA is not set
-# CONFIG_BOARD_GOOGLE_MAGOLOR is not set
-# CONFIG_BOARD_GOOGLE_METAKNIGHT is not set
-# CONFIG_BOARD_GOOGLE_LANTIS is not set
-# CONFIG_BOARD_GOOGLE_GALTIC is not set
-# CONFIG_BOARD_GOOGLE_SASUKE is not set
-# CONFIG_BOARD_GOOGLE_STORO is not set
-# CONFIG_BOARD_GOOGLE_SASUKETTE is not set
-# CONFIG_BOARD_GOOGLE_KRACKO is not set
-# CONFIG_BOARD_GOOGLE_BLIPPER is not set
-# CONFIG_BOARD_GOOGLE_CRET is not set
-# CONFIG_BOARD_GOOGLE_PIRIKA is not set
-# CONFIG_BOARD_GOOGLE_CAPPY2 is not set
-# CONFIG_BOARD_GOOGLE_BUGZZY is not set
-# CONFIG_BOARD_GOOGLE_CORORI is not set
-# CONFIG_BOARD_GOOGLE_DRIBLEE is not set
-# CONFIG_BOARD_GOOGLE_GOOEY is not set
-# CONFIG_BOARD_GOOGLE_BEADRIX is not set
-# CONFIG_BOARD_GOOGLE_SHOTZO is not set
-# CONFIG_BOARD_GOOGLE_TARANZA is not set
-# CONFIG_BOARD_GOOGLE_BOXY is not set
-# CONFIG_BOARD_GOOGLE_DEXI is not set
-
-#
-# Drallion
-#
-# CONFIG_BOARD_GOOGLE_DRALLION is not set
-
-#
-# Eve
-#
-# CONFIG_BOARD_GOOGLE_EVE is not set
-
-#
-# Fizz
-#
-# CONFIG_BOARD_GOOGLE_FIZZ is not set
-# CONFIG_BOARD_GOOGLE_KARMA is not set
-# CONFIG_BOARD_GOOGLE_ENDEAVOUR is not set
-
-#
-# Foster
-#
-# CONFIG_BOARD_GOOGLE_FOSTER is not set
-
-#
-# Gale
-#
-# CONFIG_BOARD_GOOGLE_GALE is not set
-
-#
-# Geralt
-#
-# CONFIG_BOARD_GOOGLE_GERALT is not set
-
-#
-# Glados
-#
-# CONFIG_BOARD_GOOGLE_ASUKA is not set
-# CONFIG_BOARD_GOOGLE_CAROLINE is not set
-# CONFIG_BOARD_GOOGLE_CAVE is not set
-# CONFIG_BOARD_GOOGLE_CHELL is not set
-# CONFIG_BOARD_GOOGLE_GLADOS is not set
-# CONFIG_BOARD_GOOGLE_LARS is not set
-# CONFIG_BOARD_GOOGLE_SENTRY is not set
-
-#
-# Gru
-#
-CONFIG_BOARD_GOOGLE_KEVIN=y
-# CONFIG_BOARD_GOOGLE_GRU is not set
-# CONFIG_BOARD_GOOGLE_BOB is not set
-# CONFIG_BOARD_GOOGLE_SCARLET is not set
-# CONFIG_BOARD_GOOGLE_NEFARIO is not set
-# CONFIG_BOARD_GOOGLE_RAINIER is not set
-
-#
-# Guybrush
-#
-# CONFIG_BOARD_GOOGLE_GUYBRUSH is not set
-# CONFIG_BOARD_GOOGLE_NIPPERKIN is not set
-# CONFIG_BOARD_GOOGLE_DEWATT is not set
-
-#
-# Hatch
-#
-# CONFIG_BOARD_GOOGLE_AKEMI is not set
-# CONFIG_BOARD_GOOGLE_DRATINI is not set
-# CONFIG_BOARD_GOOGLE_HATCH is not set
-# CONFIG_BOARD_GOOGLE_HELIOS is not set
-# CONFIG_BOARD_GOOGLE_HELIOS_DISKSWAP is not set
-# CONFIG_BOARD_GOOGLE_JINLON is not set
-# CONFIG_BOARD_GOOGLE_KINDRED is not set
-# CONFIG_BOARD_GOOGLE_KOHAKU is not set
-# CONFIG_BOARD_GOOGLE_MUSHU is not set
-# CONFIG_BOARD_GOOGLE_NIGHTFURY is not set
-# CONFIG_BOARD_GOOGLE_PALKIA is not set
-
-#
-# Herobrine
-#
-
-#
-# (Herobrine requires 'Allow QC blobs repository')
-#
-
-#
-# Jecht
-#
-# CONFIG_BOARD_GOOGLE_GUADO is not set
-# CONFIG_BOARD_GOOGLE_JECHT is not set
-# CONFIG_BOARD_GOOGLE_RIKKU is not set
-# CONFIG_BOARD_GOOGLE_TIDUS is not set
-
-#
-# Kahlee
-#
-# CONFIG_BOARD_GOOGLE_ALEENA is not set
-# CONFIG_BOARD_GOOGLE_CAREENA is not set
-# CONFIG_BOARD_GOOGLE_GRUNT is not set
-# CONFIG_BOARD_GOOGLE_LIARA is not set
-# CONFIG_BOARD_GOOGLE_NUWANI is not set
-# CONFIG_BOARD_GOOGLE_TREEYA is not set
-
-#
-# Kukui
-#
-# CONFIG_BOARD_GOOGLE_KUKUI is not set
-# CONFIG_BOARD_GOOGLE_KRANE is not set
-# CONFIG_BOARD_GOOGLE_KODAMA is not set
-# CONFIG_BOARD_GOOGLE_KAKADU is not set
-# CONFIG_BOARD_GOOGLE_FLAPJACK is not set
-# CONFIG_BOARD_GOOGLE_KATSU is not set
-
-#
-# Jacuzzi
-#
-# CONFIG_BOARD_GOOGLE_JACUZZI is not set
-# CONFIG_BOARD_GOOGLE_JUNIPER is not set
-# CONFIG_BOARD_GOOGLE_KAPPA is not set
-# CONFIG_BOARD_GOOGLE_DAMU is not set
-# CONFIG_BOARD_GOOGLE_CERISE is not set
-# CONFIG_BOARD_GOOGLE_STERN is not set
-# CONFIG_BOARD_GOOGLE_WILLOW is not set
-# CONFIG_BOARD_GOOGLE_ESCHE is not set
-# CONFIG_BOARD_GOOGLE_BURNET is not set
-# CONFIG_BOARD_GOOGLE_FENNEL is not set
-# CONFIG_BOARD_GOOGLE_COZMO is not set
-# CONFIG_BOARD_GOOGLE_MAKOMO is not set
-# CONFIG_BOARD_GOOGLE_MUNNA is not set
-# CONFIG_BOARD_GOOGLE_PICO is not set
-
-#
-# Link
-#
-# CONFIG_BOARD_GOOGLE_LINK is not set
-
-#
-# Mistral
-#
-# CONFIG_BOARD_GOOGLE_MISTRAL is not set
-
-#
-# Myst
-#
-# CONFIG_BOARD_GOOGLE_MYST is not set
-
-#
-# Nyan
-#
-# CONFIG_BOARD_GOOGLE_NYAN is not set
-
-#
-# Nyan Big
-#
-# CONFIG_BOARD_GOOGLE_NYAN_BIG is not set
-
-#
-# Nyan Blaze
-#
-# CONFIG_BOARD_GOOGLE_NYAN_BLAZE is not set
-
-#
-# Oak
-#
-# CONFIG_BOARD_GOOGLE_OAK is not set
-# CONFIG_BOARD_GOOGLE_ELM is not set
-# CONFIG_BOARD_GOOGLE_HANA is not set
-
-#
-# Octopus
-#
-# CONFIG_BOARD_GOOGLE_AMPTON is not set
-# CONFIG_BOARD_GOOGLE_BLOOG is not set
-# CONFIG_BOARD_GOOGLE_BOBBA is not set
-# CONFIG_BOARD_GOOGLE_CASTA is not set
-# CONFIG_BOARD_GOOGLE_DOOD is not set
-# CONFIG_BOARD_GOOGLE_FLEEX is not set
-# CONFIG_BOARD_GOOGLE_FOOB is not set
-# CONFIG_BOARD_GOOGLE_GARG is not set
-# CONFIG_BOARD_GOOGLE_LICK is not set
-# CONFIG_BOARD_GOOGLE_MEEP is not set
-# CONFIG_BOARD_GOOGLE_OCTOPUS is not set
-# CONFIG_BOARD_GOOGLE_PHASER is not set
-# CONFIG_BOARD_GOOGLE_YORP is not set
-
-#
-# Parrot
-#
-# CONFIG_BOARD_GOOGLE_PARROT is not set
-
-#
-# Peach Pit
-#
-# CONFIG_BOARD_GOOGLE_PEACH_PIT is not set
-
-#
-# Poppy
-#
-# CONFIG_BOARD_GOOGLE_ATLAS is not set
-# CONFIG_BOARD_GOOGLE_POPPY is not set
-# CONFIG_BOARD_GOOGLE_NAMI is not set
-# CONFIG_BOARD_GOOGLE_NAUTILUS is not set
-# CONFIG_BOARD_GOOGLE_NOCTURNE is not set
-# CONFIG_BOARD_GOOGLE_RAMMUS is not set
-# CONFIG_BOARD_GOOGLE_SORAKA is not set
-
-#
-# Puff
-#
-# CONFIG_BOARD_GOOGLE_AMBASSADOR is not set
-# CONFIG_BOARD_GOOGLE_DOOLY is not set
-# CONFIG_BOARD_GOOGLE_DUFFY_LEGACY is not set
-# CONFIG_BOARD_GOOGLE_DUFFY is not set
-# CONFIG_BOARD_GOOGLE_FAFFY is not set
-# CONFIG_BOARD_GOOGLE_GENESIS is not set
-# CONFIG_BOARD_GOOGLE_KAISA_LEGACY is not set
-# CONFIG_BOARD_GOOGLE_KAISA is not set
-# CONFIG_BOARD_GOOGLE_MOONBUGGY is not set
-# CONFIG_BOARD_GOOGLE_NOIBAT is not set
-# CONFIG_BOARD_GOOGLE_PUFF is not set
-# CONFIG_BOARD_GOOGLE_SCOUT is not set
-# CONFIG_BOARD_GOOGLE_WYVERN is not set
-
-#
-# Rambi
-#
-# CONFIG_BOARD_GOOGLE_BANJO is not set
-# CONFIG_BOARD_GOOGLE_CANDY is not set
-# CONFIG_BOARD_GOOGLE_CLAPPER is not set
-# CONFIG_BOARD_GOOGLE_ENGUARDE is not set
-# CONFIG_BOARD_GOOGLE_EXPRESSO is not set
-# CONFIG_BOARD_GOOGLE_GLIMMER is not set
-# CONFIG_BOARD_GOOGLE_GNAWTY is not set
-# CONFIG_BOARD_GOOGLE_HELI is not set
-# CONFIG_BOARD_GOOGLE_KIP is not set
-# CONFIG_BOARD_GOOGLE_NINJA is not set
-# CONFIG_BOARD_GOOGLE_ORCO is not set
-# CONFIG_BOARD_GOOGLE_QUAWKS is not set
-# CONFIG_BOARD_GOOGLE_SQUAWKS is not set
-# CONFIG_BOARD_GOOGLE_RAMBI is not set
-# CONFIG_BOARD_GOOGLE_SUMO is not set
-# CONFIG_BOARD_GOOGLE_SWANKY is not set
-# CONFIG_BOARD_GOOGLE_WINKY is not set
-
-#
-# Reef
-#
-# CONFIG_BOARD_GOOGLE_REEF is not set
-# CONFIG_BOARD_GOOGLE_PYRO is not set
-# CONFIG_BOARD_GOOGLE_SAND is not set
-# CONFIG_BOARD_GOOGLE_SNAPPY is not set
-# CONFIG_BOARD_GOOGLE_CORAL is not set
-
-#
-# Rex
-#
-# CONFIG_BOARD_GOOGLE_REX0 is not set
-# CONFIG_BOARD_GOOGLE_SCREEBO is not set
-# CONFIG_BOARD_GOOGLE_SCREEBO4ES is not set
-# CONFIG_BOARD_GOOGLE_KARIS is not set
-# CONFIG_BOARD_GOOGLE_KARIS4ES is not set
-# CONFIG_BOARD_GOOGLE_REX_EC_ISH is not set
-# CONFIG_BOARD_GOOGLE_OVIS is not set
-# CONFIG_BOARD_GOOGLE_OVIS4ES is not set
-# CONFIG_BOARD_GOOGLE_REX4ES is not set
-# CONFIG_BOARD_GOOGLE_REX4ES_EC_ISH is not set
-
-#
-# Sarien
-#
-# CONFIG_BOARD_GOOGLE_ARCADA is not set
-# CONFIG_BOARD_GOOGLE_SARIEN is not set
-
-#
-# Skyrim
-#
-# CONFIG_BOARD_GOOGLE_SKYRIM is not set
-# CONFIG_BOARD_GOOGLE_WINTERHOLD is not set
-# CONFIG_BOARD_GOOGLE_FROSTFLOW is not set
-# CONFIG_BOARD_GOOGLE_CRYSTALDRIFT is not set
-# CONFIG_BOARD_GOOGLE_MARKARTH is not set
-
-#
-# Slippy
-#
-# CONFIG_BOARD_GOOGLE_FALCO is not set
-# CONFIG_BOARD_GOOGLE_LEON is not set
-# CONFIG_BOARD_GOOGLE_PEPPY is not set
-# CONFIG_BOARD_GOOGLE_WOLF is not set
-
-#
-# Smaug
-#
-# CONFIG_BOARD_GOOGLE_SMAUG is not set
-
-#
-# Storm
-#
-# CONFIG_BOARD_GOOGLE_STORM is not set
-
-#
-# Stout
-#
-# CONFIG_BOARD_GOOGLE_STOUT is not set
-
-#
-# Trogdor
-#
-
-#
-# (Trogdor requires 'Allow QC blobs repository')
-#
-
-#
-# Veyron
-#
-# CONFIG_BOARD_GOOGLE_VEYRON_JAQ is not set
-# CONFIG_BOARD_GOOGLE_VEYRON_JERRY is not set
-# CONFIG_BOARD_GOOGLE_VEYRON_MIGHTY is not set
-# CONFIG_BOARD_GOOGLE_VEYRON_MINNIE is not set
-# CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY is not set
-
-#
-# Veyron Mickey
-#
-# CONFIG_BOARD_GOOGLE_VEYRON_MICKEY is not set
-
-#
-# Veyron Rialto
-#
-# CONFIG_BOARD_GOOGLE_VEYRON_RIALTO is not set
-
-#
-# Volteer
-#
-# CONFIG_BOARD_GOOGLE_CHRONICLER is not set
-# CONFIG_BOARD_GOOGLE_COLLIS is not set
-# CONFIG_BOARD_GOOGLE_COPANO is not set
-# CONFIG_BOARD_GOOGLE_DELBIN is not set
-# CONFIG_BOARD_GOOGLE_DROBIT is not set
-# CONFIG_BOARD_GOOGLE_ELDRID is not set
-# CONFIG_BOARD_GOOGLE_ELEMI is not set
-# CONFIG_BOARD_GOOGLE_HALVOR is not set
-# CONFIG_BOARD_GOOGLE_LINDAR is not set
-# CONFIG_BOARD_GOOGLE_MALEFOR is not set
-# CONFIG_BOARD_GOOGLE_TERRADOR is not set
-# CONFIG_BOARD_GOOGLE_TODOR is not set
-# CONFIG_BOARD_GOOGLE_TRONDO is not set
-# CONFIG_BOARD_GOOGLE_VOEMA is not set
-# CONFIG_BOARD_GOOGLE_VOLET is not set
-# CONFIG_BOARD_GOOGLE_VOLTEER is not set
-# CONFIG_BOARD_GOOGLE_VOLTEER2 is not set
-# CONFIG_BOARD_GOOGLE_VOLTEER2_TI50 is not set
-# CONFIG_BOARD_GOOGLE_VOXEL is not set
-
-#
-# Zork
-#
-# CONFIG_BOARD_GOOGLE_DALBOZ is not set
-# CONFIG_BOARD_GOOGLE_VILBOZ is not set
-# CONFIG_BOARD_GOOGLE_EZKINIL is not set
-# CONFIG_BOARD_GOOGLE_MORPHIUS is not set
-# CONFIG_BOARD_GOOGLE_TREMBYLE is not set
-# CONFIG_BOARD_GOOGLE_BERKNIP is not set
-# CONFIG_BOARD_GOOGLE_WOOMAX is not set
-# CONFIG_BOARD_GOOGLE_DIRINBOZ is not set
-# CONFIG_BOARD_GOOGLE_SHUBOZ is not set
-# CONFIG_BOARD_GOOGLE_GUMBOZ is not set
-CONFIG_DRIVER_TPM_SPI_BUS=0x0
-CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x5
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_DRIVER_TPM_I2C_BUS=0x0
-CONFIG_DRIVER_TPM_I2C_ADDR=0x20
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_PMIC_BUS=-1
-CONFIG_BOARD_GOOGLE_GRU_COMMON=y
-# CONFIG_GRU_HAS_TPM2 is not set
-CONFIG_GRU_HAS_CENTERLOG_PWM=y
-CONFIG_GRU_HAS_WLAN_RESET=y
-CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME=""
-CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US=0
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=8192
-CONFIG_ROM_SIZE=0x00800000
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_ARM64_BL31_EXTERNAL_FILE=""
-CONFIG_ARCH_ARMV8_EXTENSION=0
-CONFIG_STACK_SIZE=0x0
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_GENERIC_UDELAY=y
-CONFIG_SOC_ROCKCHIP_RK3399=y
-# CONFIG_RK3399_SPREAD_SPECTRUM_DDR is not set
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-
-#
-# Northbridge
-#
-
-#
-# Southbridge
-#
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_SUPPORTS_DPTF_TEVT=y
-CONFIG_EC_GOOGLE_CHROMEEC=y
-CONFIG_EC_GOOGLE_CHROMEEC_SPI=y
-CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP=0x0
-CONFIG_EC_GOOGLE_CHROMEEC_RTC=y
-CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_NONE=y
-# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL is not set
-# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN is not set
-CONFIG_MAINBOARD_HAS_CHROMEOS=y
-
-#
-# ChromeOS
-#
-# end of ChromeOS
-
-CONFIG_ARCH_ARM64=y
-CONFIG_ARCH_BOOTBLOCK_ARM64=y
-CONFIG_ARCH_VERSTAGE_ARM64=y
-CONFIG_ARCH_ROMSTAGE_ARM64=y
-CONFIG_ARCH_RAMSTAGE_ARM64=y
-CONFIG_ARCH_BOOTBLOCK_ARMV8_64=y
-CONFIG_ARCH_VERSTAGE_ARMV8_64=y
-CONFIG_ARCH_ROMSTAGE_ARMV8_64=y
-CONFIG_ARCH_RAMSTAGE_ARMV8_64=y
-CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE=y
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
-CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y
-CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_COMMON_CBFS_SPI_WRAPPER=y
-CONFIG_SPI_FLASH=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_TPM_INIT_RAMSTAGE=y
-CONFIG_DRIVERS_UART=y
-CONFIG_UART_OVERRIDE_REFCLK=y
-CONFIG_DRIVERS_UART_8250MEM=y
-CONFIG_DRIVERS_UART_8250MEM_32=y
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_I2C_TPM=y
-CONFIG_DRIVER_TIS_DEFAULT=y
-# CONFIG_DRIVER_I2C_TPM_ACPI is not set
-# CONFIG_DRIVER_TPM_DISPLAY_TIS_BYTES is not set
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-# CONFIG_NO_TPM is not set
-CONFIG_TPM1=y
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM1=y
-# CONFIG_TPM_DEACTIVATE is not set
-# CONFIG_DEBUG_TPM is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-CONFIG_TPM_SETUP_HIBERNATE_ON_ERR=y
-
-#
-# Memory initialization
-#
-# end of Memory initialization
-
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_CUSTOM_MADT=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-
-#
-# memory mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-CONFIG_POST_DEVICE_NONE=y
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_MONOTONIC_TIMER=y
-
-#
-# System tables
-#
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-# end of Debugging
-
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_NO_XIP_EARLY_STAGES=y
-CONFIG_GENERIC_GPIO_LIB=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/gru_kevin/target.cfg

@@ -1,6 +0,0 @@
-tree="default"
-romtype="normal"
-arch="AArch64"
-payload_uboot="y"
-vendorfiles="n"
-microcode_required="n"

config/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch

@@ -1,54 +0,0 @@
-From dd58f5e9108bc596c93071705d2b53233d13ade6 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 20:36:10 +0200
-Subject: [PATCH 01/26] commonlib/clamp.h: Add more clamping functions
-
-Add more clamping functions that work with different types.
-
-Change-Id: I14cf335d5a54f769f8fd9184450957e876affd6b
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- src/commonlib/include/commonlib/clamp.h | 26 +++++++++++++++++--------
- 1 file changed, 18 insertions(+), 8 deletions(-)
-
-diff --git a/src/commonlib/include/commonlib/clamp.h b/src/commonlib/include/commonlib/clamp.h
-index e01a107ed4..526185195c 100644
---- a/src/commonlib/include/commonlib/clamp.h
-+++ b/src/commonlib/include/commonlib/clamp.h
-@@ -8,15 +8,25 @@
- /*
-  * Clamp a value, so that it is between a lower and an upper bound.
-  */
--static inline u32 clamp_u32(const u32 min, const u32 val, const u32 max)
--{
--	if (val > max)
--		return max;
-+#define __MAKE_CLAMP_FUNC(type) \
-+	static inline type clamp_##type(const type min, const type val, const type max) \
-+	{				\
-+		if (val > max)		\
-+			return max;	\
-+		if (val < min)		\
-+			return min;	\
-+		return val;		\
-+	}				\
- 
--	if (val < min)
--		return min;
-+__MAKE_CLAMP_FUNC(s8)	/* clamp_s8  */
-+__MAKE_CLAMP_FUNC(u8)	/* clamp_u8  */
-+__MAKE_CLAMP_FUNC(s16)	/* clamp_s16 */
-+__MAKE_CLAMP_FUNC(u16)	/* clamp_u16 */
-+__MAKE_CLAMP_FUNC(s32)	/* clamp_s32 */
-+__MAKE_CLAMP_FUNC(u32)	/* clamp_u32 */
-+__MAKE_CLAMP_FUNC(s64)	/* clamp_s64 */
-+__MAKE_CLAMP_FUNC(u64)	/* clamp_u64 */
- 
--	return val;
--}
-+#undef __MAKE_CLAMP_FUNC
- 
- #endif /* COMMONLIB_CLAMP_H */
--- 
-2.39.2
-

config/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch

@@ -1,143 +0,0 @@
-From c07391821c32cafea950574b85468f5b3284b6df Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 21:12:14 +0200
-Subject: [PATCH 02/26] nb/intel/haswell: Introduce option to not use MRC.bin
-
-Introduce the `USE_NATIVE_RAMINIT` Kconfig option, which should allow
-booting coreboot on Haswell mainboards without the need of the closed
-source MRC.bin. For now, this option does not work at all; the needed
-magic will be implemented in subsequent commits. Add a config file to
-make sure the newly-introduced option gets build-tested.
-
-Change-Id: I46c77586f9b5771624082e07c60c205e578edd8e
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- configs/config.asrock_b85m_pro4.native_raminit    |  5 +++++
- src/northbridge/intel/haswell/Kconfig             | 13 +++++++++++++
- src/northbridge/intel/haswell/Makefile.inc        |  7 ++++++-
- .../intel/haswell/native_raminit/Makefile.inc     |  3 +++
- .../intel/haswell/native_raminit/raminit_native.c | 15 +++++++++++++++
- 5 files changed, 42 insertions(+), 1 deletion(-)
- create mode 100644 configs/config.asrock_b85m_pro4.native_raminit
- create mode 100644 src/northbridge/intel/haswell/native_raminit/Makefile.inc
- create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.c
-
-diff --git a/configs/config.asrock_b85m_pro4.native_raminit b/configs/config.asrock_b85m_pro4.native_raminit
-new file mode 100644
-index 0000000000..2de538926f
---- /dev/null
-+++ b/configs/config.asrock_b85m_pro4.native_raminit
-@@ -0,0 +1,5 @@
-+# Configuration used to build-test native raminit
-+CONFIG_VENDOR_ASROCK=y
-+CONFIG_BOARD_ASROCK_B85M_PRO4=y
-+CONFIG_USE_NATIVE_RAMINIT=y
-+CONFIG_DEBUG_RAM_SETUP=y
-diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
-index 50acb09a91..b659bf6d98 100644
---- a/src/northbridge/intel/haswell/Kconfig
-+++ b/src/northbridge/intel/haswell/Kconfig
-@@ -9,6 +9,14 @@ config NORTHBRIDGE_INTEL_HASWELL
- 
- if NORTHBRIDGE_INTEL_HASWELL
- 
-+config USE_NATIVE_RAMINIT
-+	bool "[NOT WORKING] Use native raminit"
-+	default n
-+	select HAVE_DEBUG_RAM_SETUP
-+	help
-+	  Select if you want to use coreboot implementation of raminit rather than
-+	  MRC.bin. Currently incomplete and does not boot.
-+
- config HASWELL_VBOOT_IN_BOOTBLOCK
- 	depends on VBOOT
- 	bool "Start verstage in bootblock"
-@@ -45,6 +53,7 @@ config DCACHE_RAM_BASE
- 
- config DCACHE_RAM_SIZE
- 	hex
-+	default 0x40000 if USE_NATIVE_RAMINIT
- 	default 0x10000
- 	help
- 	  The size of the cache-as-ram region required during bootblock
-@@ -53,12 +62,14 @@ config DCACHE_RAM_SIZE
- 
- config DCACHE_RAM_MRC_VAR_SIZE
- 	hex
-+	default 0x0 if USE_NATIVE_RAMINIT
- 	default 0x30000
- 	help
- 	  The amount of cache-as-ram region required by the reference code.
- 
- config DCACHE_BSP_STACK_SIZE
- 	hex
-+	default 0x20000 if USE_NATIVE_RAMINIT
- 	default 0x2000
- 	help
- 	  The amount of anticipated stack usage in CAR by bootblock and
-@@ -66,6 +77,7 @@ config DCACHE_BSP_STACK_SIZE
- 
- config HAVE_MRC
- 	bool "Add a System Agent binary"
-+	depends on !USE_NATIVE_RAMINIT
- 	help
- 	  Select this option to add a System Agent binary to
- 	  the resulting coreboot image.
-@@ -82,6 +94,7 @@ config MRC_FILE
- 
- config HASWELL_HIDE_PEG_FROM_MRC
- 	bool "Hide PEG devices from MRC to work around hardcoded MRC behavior"
-+	depends on !USE_NATIVE_RAMINIT
- 	default y
- 	help
- 	  If set, hides all PEG devices from MRC. This allows the iGPU
-diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
-index 2d1532be05..329f1f7ffe 100644
---- a/src/northbridge/intel/haswell/Makefile.inc
-+++ b/src/northbridge/intel/haswell/Makefile.inc
-@@ -19,6 +19,11 @@ romstage-y += report_platform.c
- 
- postcar-y += memmap.c
- 
--subdirs-y += haswell_mrc
-+ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
-+subdirs-y  += native_raminit
-+
-+else
-+subdirs-y  += haswell_mrc
-+endif
- 
- endif
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-new file mode 100644
-index 0000000000..8cfb4fb33e
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -0,0 +1,3 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+romstage-y += raminit_native.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-new file mode 100644
-index 0000000000..1aafdf8659
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -0,0 +1,15 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <northbridge/intel/haswell/raminit.h>
-+
-+void perform_raminit(const int s3resume)
-+{
-+	/*
-+	 * See, this function's name is a lie. There are more things to
-+	 * do that memory initialisation, but they are relatively easy.
-+	 */
-+
-+	/** TODO: Implement the required magic **/
-+	die("NATIVE RAMINIT: More Magic (tm) required.\n");
-+}
--- 
-2.39.2
-

config/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch

@@ -1,615 +0,0 @@
-From 6ec71c6df97eded010e96c4ea2bd37cc6a13849d Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 21:56:48 +0200
-Subject: [PATCH 03/26] haswell/lynxpoint: Add native DMI init
-
-Implement native DMI init for Haswell and Lynx Point. This is only
-needed on non-ULT platforms, and only when MRC.bin is not used.
-
-TEST=Verify DMI initialises correctly on Asrock B85M Pro4.
-
-Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- src/northbridge/intel/haswell/Makefile.inc    |   1 +
- src/northbridge/intel/haswell/early_dmi.c     |  96 ++++++++++++
- src/northbridge/intel/haswell/early_pcie.c    | 121 ++++++++++++++
- src/northbridge/intel/haswell/haswell.h       |   3 +
- .../haswell/native_raminit/raminit_native.c   |  15 ++
- src/northbridge/intel/haswell/vcu_mailbox.c   | 147 ++++++++++++++++++
- src/northbridge/intel/haswell/vcu_mailbox.h   |  16 ++
- src/southbridge/intel/lynxpoint/Makefile.inc  |   2 +
- .../intel/lynxpoint/early_pch_native.c        |  52 +++++++
- src/southbridge/intel/lynxpoint/pch.h         |  20 ++-
- 10 files changed, 472 insertions(+), 1 deletion(-)
- create mode 100644 src/northbridge/intel/haswell/early_dmi.c
- create mode 100644 src/northbridge/intel/haswell/early_pcie.c
- create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.c
- create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.h
- create mode 100644 src/southbridge/intel/lynxpoint/early_pch_native.c
-
-diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
-index 329f1f7ffe..df0b097296 100644
---- a/src/northbridge/intel/haswell/Makefile.inc
-+++ b/src/northbridge/intel/haswell/Makefile.inc
-@@ -20,6 +20,7 @@ romstage-y += report_platform.c
- postcar-y += memmap.c
- 
- ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
-+romstage-y += early_dmi.c early_pcie.c vcu_mailbox.c
- subdirs-y  += native_raminit
- 
- else
-diff --git a/src/northbridge/intel/haswell/early_dmi.c b/src/northbridge/intel/haswell/early_dmi.c
-new file mode 100644
-index 0000000000..9941242fd5
---- /dev/null
-+++ b/src/northbridge/intel/haswell/early_dmi.c
-@@ -0,0 +1,96 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
-+#include <types.h>
-+
-+static void dmi_print_link_status(int loglevel)
-+{
-+	const uint16_t dmilsts = dmibar_read16(DMILSTS);
-+	printk(loglevel, "DMI: Running at Gen%u x%u\n", dmilsts & 0xf, dmilsts >> 4 & 0x1f);
-+}
-+
-+#define RETRAIN	(1 << 5)
-+
-+#define LTRN	(1 << 11)
-+
-+static void dmi_setup_physical_layer(void)
-+{
-+	/* Program DMI AFE settings, which are needed for DMI to work */
-+	peg_dmi_recipe(false, 0);
-+
-+	/* Additional DMI programming steps */
-+	dmibar_setbits32(0x258, 1 << 29);
-+	dmibar_clrsetbits32(0x208, 0x7ff, 0x6b5);
-+	dmibar_clrsetbits32(0x22c, 0xffff, 0x2020);
-+
-+	/* Write SA reference code version */
-+	dmibar_write32(0x71c, 0x0000000f);
-+	dmibar_write32(0x720, 0x01060200);
-+
-+	/* We also have to bring up the PCH side of the DMI link */
-+	pch_dmi_setup_physical_layer();
-+
-+	/* Write-once settings */
-+	dmibar_clrsetbits32(DMILCAP, 0x3f00f, 2 << 0);
-+
-+	printk(BIOS_DEBUG, "Retraining DMI at Gen2 speeds...\n");
-+	dmi_print_link_status(BIOS_DEBUG);
-+
-+	/* Retrain link */
-+	dmibar_setbits16(DMILCTL, RETRAIN);
-+	do {} while (dmibar_read16(DMILSTS) & LTRN);
-+	dmi_print_link_status(BIOS_DEBUG);
-+
-+	/* Retrain link again for DMI Gen2 speeds */
-+	dmibar_setbits16(DMILCTL, RETRAIN);
-+	do {} while (dmibar_read16(DMILSTS) & LTRN);
-+	dmi_print_link_status(BIOS_INFO);
-+}
-+
-+#define VC_ACTIVE	(1U << 31)
-+
-+#define VCNEGPND	(1 << 1)
-+
-+#define DMI_VC_CFG(vcid, tcmap)	(VC_ACTIVE | ((vcid) << 24) | (tcmap))
-+
-+static void dmi_tc_vc_mapping(void)
-+{
-+	printk(BIOS_DEBUG, "Programming SA  DMI VC/TC mappings...\n");
-+
-+	if (CONFIG(INTEL_LYNXPOINT_LP))
-+		dmibar_setbits8(0xa78, 1 << 1);
-+
-+	/* Each TC is mapped to one and only one VC */
-+	const u32 vc0 = DMI_VC_CFG(0, (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 0));
-+	const u32 vc1 = DMI_VC_CFG(1, (1 << 1));
-+	const u32 vcp = DMI_VC_CFG(2, (1 << 2));
-+	const u32 vcm = DMI_VC_CFG(7, (1 << 7));
-+	dmibar_write32(DMIVC0RCTL, vc0);
-+	dmibar_write32(DMIVC1RCTL, vc1);
-+	dmibar_write32(DMIVCPRCTL, vcp);
-+	dmibar_write32(DMIVCMRCTL, vcm);
-+
-+	/* Set Extended VC Count (EVCC) to 1 if VC1 is active */
-+	dmibar_clrsetbits8(DMIPVCCAP1, 7, !!(vc1 & VC_ACTIVE));
-+
-+	/*
-+	 * We also have to program the PCH side of the DMI link. Since both ends
-+	 * must use the same Virtual Channel settings, we pass them as arguments.
-+	 */
-+	pch_dmi_tc_vc_mapping(vc0, vc1, vcp, vcm);
-+
-+	printk(BIOS_DEBUG, "Waiting for SA  DMI VC negotiation... ");
-+	do {} while (dmibar_read16(DMIVC0RSTS) & VCNEGPND);
-+	do {} while (dmibar_read16(DMIVC1RSTS) & VCNEGPND);
-+	do {} while (dmibar_read16(DMIVCPRSTS) & VCNEGPND);
-+	do {} while (dmibar_read16(DMIVCMRSTS) & VCNEGPND);
-+	printk(BIOS_DEBUG, "done!\n");
-+}
-+
-+void dmi_early_init(void)
-+{
-+	dmi_setup_physical_layer();
-+	dmi_tc_vc_mapping();
-+}
-diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c
-new file mode 100644
-index 0000000000..d3940e3fac
---- /dev/null
-+++ b/src/northbridge/intel/haswell/early_pcie.c
-@@ -0,0 +1,121 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <device/pci_def.h>
-+#include <device/pci_mmio_cfg.h>
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/vcu_mailbox.h>
-+#include <types.h>
-+
-+#define PEG_DEV(func)		PCI_DEV(0, 1, func)
-+
-+#define MAX_PEG_FUNC		3
-+
-+static void peg_dmi_unset_and_set_mask_pcicfg(
-+	volatile union pci_bank *const bank,
-+	const uint32_t offset,
-+	const uint32_t unset_mask,
-+	const uint32_t set_mask,
-+	const uint32_t shift,
-+	const bool valid)
-+{
-+	if (!valid)
-+		return;
-+
-+	volatile uint32_t *const addr = &bank->reg32[offset / sizeof(uint32_t)];
-+	clrsetbits32(addr, unset_mask << shift, set_mask << shift);
-+}
-+
-+static void peg_dmi_unset_and_set_mask_common(
-+	const bool is_peg,
-+	const uint32_t offset,
-+	const uint32_t unset,
-+	const uint32_t set,
-+	const uint32_t shift,
-+	const bool valid)
-+{
-+	const uint32_t unset_mask = unset << shift;
-+	const uint32_t   set_mask =   set << shift;
-+	if (is_peg) {
-+		for (uint8_t i = 0; i < MAX_PEG_FUNC; i++)
-+			pci_update_config32(PEG_DEV(i), offset, ~unset_mask, set_mask);
-+	} else {
-+		dmibar_clrsetbits32(offset, unset_mask, set_mask);
-+	}
-+}
-+
-+static void peg_dmi_unset_and_set_mask_vcu_mmio(
-+	const uint32_t addr,
-+	const uint32_t unset_mask,
-+	const uint32_t set_mask,
-+	const uint32_t shift,
-+	const bool valid)
-+{
-+	if (!valid)
-+		return;
-+
-+	vcu_update_mmio(addr, ~(unset_mask << shift), set_mask << shift);
-+}
-+
-+#define BUNDLE_STEP	0x20
-+
-+static void *const dmibar = (void *)(uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE;
-+
-+void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev)
-+{
-+	const bool always = true;
-+	const bool is_dmi = !is_peg;
-+
-+	/* Treat DMIBAR and PEG devices the same way */
-+	volatile union pci_bank *const bank = is_peg ? pci_map_bus(dev) : dmibar;
-+
-+	const size_t bundles = (is_peg ? 8 : 2) * BUNDLE_STEP;
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP) {
-+		/* These are actually per-lane */
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa00 + i, 0x1f, 0x0c,  0, always);
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa10 + i, 0x1f, 0x0c,  0, always);
-+	}
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x02,  0, is_peg);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x03,  5, is_peg);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x3f, 0x09,  5, always);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x0f, 0x05, 21, is_peg);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x08,  6, is_peg);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x00, 10, always);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x07, 0x00, 18, always);
-+
-+	peg_dmi_unset_and_set_mask_vcu_mmio(0x0c008001, 0x1f, 0x03, 25, is_peg);
-+	peg_dmi_unset_and_set_mask_vcu_mmio(0x0c0c8001, 0x3f, 0x00, 23, is_dmi);
-+
-+	peg_dmi_unset_and_set_mask_pcicfg(bank, 0xc28, 0x1f, 0x13, 18, always);
-+
-+	peg_dmi_unset_and_set_mask_common(is_peg, 0xc38, 0x01, 0x00,  6, always);
-+	peg_dmi_unset_and_set_mask_common(is_peg, 0x260, 0x03, 0x02,  0, always);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x900 + i, 0x03, 0x00, 26, always);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x03, 0x03, 10, always);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x1f, 0x07, 25, is_peg);
-+
-+	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
-+		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x91c + i, 0x07, 0x05, 27, is_peg);
-+}
-diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
-index 1b29f6baf0..30b4abd0a7 100644
---- a/src/northbridge/intel/haswell/haswell.h
-+++ b/src/northbridge/intel/haswell/haswell.h
-@@ -34,6 +34,9 @@ void haswell_early_initialization(void);
- void haswell_late_initialization(void);
- void haswell_unhide_peg(void);
- 
-+void dmi_early_init(void);
-+void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev);
-+
- void report_platform_info(void);
- 
- struct acpi_rsdp;
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index 1aafdf8659..0938e026e3 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -1,7 +1,19 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
- #include <console/console.h>
-+#include <northbridge/intel/haswell/haswell.h>
- #include <northbridge/intel/haswell/raminit.h>
-+#include <types.h>
-+
-+static bool early_init_native(int s3resume)
-+{
-+	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
-+
-+	if (!CONFIG(INTEL_LYNXPOINT_LP))
-+		dmi_early_init();
-+
-+	return false;
-+}
- 
- void perform_raminit(const int s3resume)
- {
-@@ -9,6 +21,9 @@ void perform_raminit(const int s3resume)
- 	 * See, this function's name is a lie. There are more things to
- 	 * do that memory initialisation, but they are relatively easy.
- 	 */
-+	const bool cpu_replaced = early_init_native(s3resume);
-+
-+	(void)cpu_replaced;
- 
- 	/** TODO: Implement the required magic **/
- 	die("NATIVE RAMINIT: More Magic (tm) required.\n");
-diff --git a/src/northbridge/intel/haswell/vcu_mailbox.c b/src/northbridge/intel/haswell/vcu_mailbox.c
-new file mode 100644
-index 0000000000..aead144023
---- /dev/null
-+++ b/src/northbridge/intel/haswell/vcu_mailbox.c
-@@ -0,0 +1,147 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <assert.h>
-+#include <console/console.h>
-+#include <delay.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/vcu_mailbox.h>
-+#include <stdint.h>
-+
-+/*
-+ * This is a library for the VCU (Validation Control Unit) mailbox. This
-+ * mailbox is primarily used to adjust some magic PCIe tuning parameters.
-+ *
-+ * There are two revisions of the VCU mailbox. Rev1 is specific to Haswell
-+ * stepping A0, and all other steppings use Rev2. Haswell stepping A0 CPUs
-+ * are early Engineering Samples with undocumented errata, and most likely
-+ * need special microcode updates to boot. Thus, the code does not support
-+ * VCU mailbox Rev1, because no one should need it anymore.
-+ */
-+
-+#define VCU_MAILBOX_INTERFACE	0x6c00
-+#define VCU_MAILBOX_DATA	0x6c04
-+
-+#define VCU_RUN_BUSY		(1 << 31)
-+
-+enum vcu_opcode {
-+	VCU_OPCODE_READ_VCU_API_VER_ID	= 0x01,
-+	VCU_OPCODE_OPEN_SEQ		= 0x02,
-+	VCU_OPCODE_CLOSE_SEQ		= 0x03,
-+	VCU_OPCODE_READ_DATA		= 0x07,
-+	VCU_OPCODE_WRITE_DATA		= 0x08,
-+	VCU_OPCODE_READ_CSR		= 0x13,
-+	VCU_OPCODE_WRITE_CSR		= 0x14,
-+	VCU_OPCODE_READ_MMIO		= 0x15,
-+	VCU_OPCODE_WRITE_MMIO		= 0x16,
-+};
-+
-+enum vcu_sequence {
-+	SEQ_ID_READ_CSR		= 0x1,
-+	SEQ_ID_WRITE_CSR	= 0x2,
-+	SEQ_ID_READ_MMIO	= 0x3,
-+	SEQ_ID_WRITE_MMIO	= 0x4,
-+};
-+
-+#define VCU_RESPONSE_MASK		0xffff
-+#define VCU_RESPONSE_SUCCESS		0x40
-+#define VCU_RESPONSE_BUSY		0x80
-+#define VCU_RESPONSE_THREAD_UNAVAILABLE	0x82
-+#define VCU_RESPONSE_ILLEGAL		0x90
-+
-+/* FIXME: Use timer API */
-+static void send_vcu_command(const enum vcu_opcode opcode, const uint32_t data)
-+{
-+	for (unsigned int i = 0; i < 10; i++) {
-+		mchbar_write32(VCU_MAILBOX_DATA, data);
-+		mchbar_write32(VCU_MAILBOX_INTERFACE, opcode | VCU_RUN_BUSY);
-+		uint32_t vcu_interface;
-+		for (unsigned int j = 0; j < 100; j++) {
-+			vcu_interface = mchbar_read32(VCU_MAILBOX_INTERFACE);
-+			if (!(vcu_interface & VCU_RUN_BUSY))
-+				break;
-+
-+			udelay(10);
-+		}
-+		if (vcu_interface & VCU_RUN_BUSY)
-+			continue;
-+
-+		if ((vcu_interface & VCU_RESPONSE_MASK) == VCU_RESPONSE_SUCCESS)
-+			return;
-+	}
-+	printk(BIOS_ERR, "VCU: Failed to send command\n");
-+}
-+
-+static enum vcu_opcode get_register_opcode(enum vcu_sequence seq)
-+{
-+	switch (seq) {
-+	case SEQ_ID_READ_CSR:
-+		return VCU_OPCODE_READ_CSR;
-+	case SEQ_ID_WRITE_CSR:
-+		return VCU_OPCODE_WRITE_CSR;
-+	case SEQ_ID_READ_MMIO:
-+		return VCU_OPCODE_READ_MMIO;
-+	case SEQ_ID_WRITE_MMIO:
-+		return VCU_OPCODE_WRITE_MMIO;
-+	default:
-+		return dead_code_t(enum vcu_opcode);
-+	}
-+}
-+
-+static enum vcu_opcode get_data_opcode(enum vcu_sequence seq)
-+{
-+	switch (seq) {
-+	case SEQ_ID_READ_CSR:
-+	case SEQ_ID_READ_MMIO:
-+		return VCU_OPCODE_READ_DATA;
-+	case SEQ_ID_WRITE_CSR:
-+	case SEQ_ID_WRITE_MMIO:
-+		return VCU_OPCODE_WRITE_DATA;
-+	default:
-+		return dead_code_t(enum vcu_opcode);
-+	}
-+}
-+
-+static uint32_t send_vcu_sequence(uint32_t addr, enum vcu_sequence seq, uint32_t wr_data)
-+{
-+	send_vcu_command(VCU_OPCODE_OPEN_SEQ, seq);
-+
-+	send_vcu_command(get_register_opcode(seq), addr);
-+
-+	send_vcu_command(get_data_opcode(seq), wr_data);
-+
-+	const uint32_t rd_data = mchbar_read32(VCU_MAILBOX_DATA);
-+
-+	send_vcu_command(VCU_OPCODE_CLOSE_SEQ, seq);
-+
-+	return rd_data;
-+}
-+
-+uint32_t vcu_read_csr(uint32_t addr)
-+{
-+	return send_vcu_sequence(addr, SEQ_ID_READ_CSR, 0);
-+}
-+
-+void vcu_write_csr(uint32_t addr, uint32_t data)
-+{
-+	send_vcu_sequence(addr, SEQ_ID_WRITE_CSR, data);
-+}
-+
-+void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue)
-+{
-+	vcu_write_csr(addr, (vcu_read_csr(addr) & andvalue) | orvalue);
-+}
-+
-+uint32_t vcu_read_mmio(uint32_t addr)
-+{
-+	return send_vcu_sequence(addr, SEQ_ID_READ_MMIO, 0);
-+}
-+
-+void vcu_write_mmio(uint32_t addr, uint32_t data)
-+{
-+	send_vcu_sequence(addr, SEQ_ID_WRITE_MMIO, data);
-+}
-+
-+void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue)
-+{
-+	vcu_write_mmio(addr, (vcu_read_mmio(addr) & andvalue) | orvalue);
-+}
-diff --git a/src/northbridge/intel/haswell/vcu_mailbox.h b/src/northbridge/intel/haswell/vcu_mailbox.h
-new file mode 100644
-index 0000000000..ba0a62e486
---- /dev/null
-+++ b/src/northbridge/intel/haswell/vcu_mailbox.h
-@@ -0,0 +1,16 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#ifndef HASWELL_VCU_MAILBOX_H
-+#define HASWELL_VCU_MAILBOX_H
-+
-+#include <stdint.h>
-+
-+uint32_t vcu_read_csr(uint32_t addr);
-+void vcu_write_csr(uint32_t addr, uint32_t data);
-+void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue);
-+
-+uint32_t vcu_read_mmio(uint32_t addr);
-+void vcu_write_mmio(uint32_t addr, uint32_t data);
-+void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue);
-+
-+#endif /* HASWELL_VCU_MAILBOX_H */
-diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
-index 02022d348d..b8503ac8bc 100644
---- a/src/southbridge/intel/lynxpoint/Makefile.inc
-+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
-@@ -37,6 +37,8 @@ bootblock-y += early_pch.c
- romstage-y += early_usb.c early_me.c me_status.c early_pch.c
- romstage-y += pmutil.c
- 
-+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c
-+
- ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
- romstage-y += lp_gpio.c
- ramstage-y += lp_gpio.c
-diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c
-new file mode 100644
-index 0000000000..c28ddfcf5d
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c
-@@ -0,0 +1,52 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
-+#include <types.h>
-+
-+void pch_dmi_setup_physical_layer(void)
-+{
-+	/* FIXME: We need to make sure the SA supports Gen2 as well */
-+	if ((RCBA32(0x21a4) & 0x0f) == 0x02) {
-+		/* Set Gen 2 Common Clock N_FTS */
-+		RCBA32_AND_OR(0x2340, ~0x00ff0000, 0x3a << 16);
-+
-+		/* Set Target Link Speed to DMI Gen2 */
-+		RCBA8_AND_OR(DLCTL2, ~0x07, 0x02);
-+	}
-+}
-+
-+#define VC_ACTIVE	(1U << 31)
-+
-+#define VCNEGPND	(1 << 1)
-+
-+void pch_dmi_tc_vc_mapping(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm)
-+{
-+	printk(BIOS_DEBUG, "Programming PCH DMI VC/TC mappings...\n");
-+
-+	RCBA32_AND_OR(CIR0050, ~(0xf << 20), 2 << 20);
-+	if (vcp & VC_ACTIVE)
-+		RCBA32_OR(CIR0050, 1 << 19 | 1 << 17);
-+
-+	RCBA32(CIR0050);	/* Posted Write */
-+
-+	/* Use the same virtual channel mapping on both ends of the DMI link */
-+	RCBA32(V0CTL) = vc0;
-+	RCBA32(V1CTL) = vc1;
-+	RCBA32(V1CTL);		/* Posted Write */
-+	RCBA32(VPCTL) = vcp;
-+	RCBA32(VPCTL);		/* Posted Write */
-+	RCBA32(VMCTL) = vcm;
-+
-+	/* Lock the registers */
-+	RCBA32_OR(CIR0050, 1U << 31);
-+	RCBA32(CIR0050);	/* Posted Write */
-+
-+	printk(BIOS_DEBUG, "Waiting for PCH DMI VC negotiation... ");
-+	do {} while (RCBA16(V0STS) & VCNEGPND);
-+	do {} while (RCBA16(V1STS) & VCNEGPND);
-+	do {} while (RCBA16(VPSTS) & VCNEGPND);
-+	do {} while (RCBA16(VMSTS) & VCNEGPND);
-+	printk(BIOS_DEBUG, "done!\n");
-+}
-diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
-index 7d9fc6d6af..b5e0c2a830 100644
---- a/src/southbridge/intel/lynxpoint/pch.h
-+++ b/src/southbridge/intel/lynxpoint/pch.h
-@@ -113,6 +113,9 @@ enum pch_platform_type {
- 	PCH_TYPE_ULT	 = 5,
- };
- 
-+void pch_dmi_setup_physical_layer(void);
-+void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
-+
- void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
- void usb_ehci_disable(pci_devfn_t dev);
- void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
-@@ -406,9 +409,10 @@ void mainboard_config_rcba(void);
- 
- /* Southbridge IO BARs */
- 
-+#define PMBASE			0x40
- #define GPIOBASE		0x48
- 
--#define PMBASE		0x40
-+#define CIR0050		0x0050	/* 32bit */
- 
- #define RPC		0x0400	/* 32bit */
- #define RPFN		0x0404	/* 32bit */
-@@ -431,6 +435,20 @@ void mainboard_config_rcba(void);
- #define IOTR2		0x1e90	/* 64bit */
- #define IOTR3		0x1e98	/* 64bit */
- 
-+#define V0CTL		0x2014	/* 32bit */
-+#define V0STS		0x201a	/* 16bit */
-+
-+#define V1CTL		0x2020	/* 32bit */
-+#define V1STS		0x2026	/* 16bit */
-+
-+#define VPCTL		0x2030	/* 32bit */
-+#define VPSTS		0x2038	/* 16bit */
-+
-+#define VMCTL		0x2040	/* 32bit */
-+#define VMSTS		0x2048	/* 16bit */
-+
-+#define DLCTL2		0x21b0
-+
- #define TCTL		0x3000	/*  8bit */
- 
- #define NOINT		0
--- 
-2.39.2
-

config/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch

@@ -1,148 +0,0 @@
-From 98142e01fc8ebb3b762974e9e4de75e7f5c073b4 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 22:18:21 +0200
-Subject: [PATCH 04/26] haswell/lynxpoint: Add native early ME init
-
-Implement native early ME init for Lynx Point. This is only needed when
-MRC.bin is not used.
-
-Change-Id: If416e2078f139f26b4742c564b70e018725bf003
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../haswell/native_raminit/raminit_native.c   | 17 ++++++++++-
- src/southbridge/intel/lynxpoint/early_me.c    | 30 ++++++++++++++++++-
- src/southbridge/intel/lynxpoint/me.h          |  7 +++--
- 3 files changed, 50 insertions(+), 4 deletions(-)
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index 0938e026e3..6a002548c1 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -1,18 +1,24 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
- #include <console/console.h>
-+#include <delay.h>
- #include <northbridge/intel/haswell/haswell.h>
- #include <northbridge/intel/haswell/raminit.h>
-+#include <southbridge/intel/lynxpoint/me.h>
- #include <types.h>
- 
- static bool early_init_native(int s3resume)
- {
- 	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
- 
-+	intel_early_me_init();
-+	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
-+	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
-+
- 	if (!CONFIG(INTEL_LYNXPOINT_LP))
- 		dmi_early_init();
- 
--	return false;
-+	return cpu_replaced;
- }
- 
- void perform_raminit(const int s3resume)
-@@ -25,6 +31,15 @@ void perform_raminit(const int s3resume)
- 
- 	(void)cpu_replaced;
- 
-+	/** TODO: Move after raminit */
-+	if (intel_early_me_uma_size() > 0) {
-+		/** TODO: Update status once raminit is implemented **/
-+		uint8_t me_status = ME_INIT_STATUS_ERROR;
-+		intel_early_me_init_done(me_status);
-+	}
-+
-+	intel_early_me_status();
-+
- 	/** TODO: Implement the required magic **/
- 	die("NATIVE RAMINIT: More Magic (tm) required.\n");
- }
-diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
-index 947c570e16..07013c5539 100644
---- a/src/southbridge/intel/lynxpoint/early_me.c
-+++ b/src/southbridge/intel/lynxpoint/early_me.c
-@@ -1,11 +1,12 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
- 
- #include <arch/io.h>
-+#include <cf9_reset.h>
- #include <device/pci_ops.h>
- #include <console/console.h>
- #include <delay.h>
- #include <halt.h>
--
-+#include <timer.h>
- #include "me.h"
- #include "pch.h"
- 
-@@ -60,6 +61,33 @@ int intel_early_me_init(void)
- 	return 0;
- }
- 
-+bool intel_early_me_cpu_replacement_check(void)
-+{
-+	printk(BIOS_DEBUG, "ME: Checking whether CPU was replaced... ");
-+
-+	struct stopwatch timer;
-+	stopwatch_init_msecs_expire(&timer, 50);
-+
-+	union me_hfs2 hfs2;
-+	do {
-+		hfs2.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2);
-+		if (stopwatch_expired(&timer)) {
-+			/* Assume CPU was replaced just in case */
-+			printk(BIOS_DEBUG, "timed out, assuming CPU was replaced\n");
-+			return true;
-+		}
-+		udelay(ME_DELAY);
-+	} while (!hfs2.cpu_replaced_valid);
-+
-+	if (hfs2.warm_reset_request) {
-+		printk(BIOS_DEBUG, "warm reset needed for dynamic fusing\n");
-+		system_reset();
-+	}
-+
-+	printk(BIOS_DEBUG, "%sreplaced\n", hfs2.cpu_replaced_sts ? "" : "not ");
-+	return hfs2.cpu_replaced_sts;
-+}
-+
- int intel_early_me_uma_size(void)
- {
- 	union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) };
-diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h
-index fe8b0260c4..6990322651 100644
---- a/src/southbridge/intel/lynxpoint/me.h
-+++ b/src/southbridge/intel/lynxpoint/me.h
-@@ -177,14 +177,16 @@ union me_did {
- union me_hfs2 {
- 	struct __packed {
- 		u32 bist_in_progress: 1;
--		u32 reserved1: 2;
-+		u32 icc_prog_sts: 2;
- 		u32 invoke_mebx: 1;
- 		u32 cpu_replaced_sts: 1;
- 		u32 mbp_rdy: 1;
- 		u32 mfs_failure: 1;
- 		u32 warm_reset_request: 1;
- 		u32 cpu_replaced_valid: 1;
--		u32 reserved2: 4;
-+		u32 reserved: 2;
-+		u32 fw_upd_ipu: 1;
-+		u32 reserved2: 1;
- 		u32 mbp_cleared: 1;
- 		u32 reserved3: 2;
- 		u32 current_state: 8;
-@@ -338,6 +340,7 @@ void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2);
- 
- void intel_early_me_status(void);
- int intel_early_me_init(void);
-+bool intel_early_me_cpu_replacement_check(void);
- int intel_early_me_uma_size(void);
- int intel_early_me_init_done(u8 status);
- 
--- 
-2.39.2
-

config/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch

@@ -1,783 +0,0 @@
-From 9bfb8614dbf1d9800ef8251cb3d839bcdbe5577f Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 23:17:39 +0200
-Subject: [PATCH 05/26] sb/intel/lynxpoint: Add native USB init
-
-Implement native USB initialisation for Lynx Point. This is only needed
-when MRC.bin is not used.
-
-TO DO: Figure out how to deal with the FIXME's and TODO's lying around.
-
-Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../haswell/native_raminit/raminit_native.c   |   3 +
- src/southbridge/intel/lynxpoint/Makefile.inc  |   2 +-
- src/southbridge/intel/lynxpoint/early_usb.c   |  11 -
- .../intel/lynxpoint/early_usb_native.c        | 584 ++++++++++++++++++
- src/southbridge/intel/lynxpoint/pch.h         |  49 ++
- 5 files changed, 637 insertions(+), 12 deletions(-)
- create mode 100644 src/southbridge/intel/lynxpoint/early_usb_native.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index 6a002548c1..ef61d4ee09 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -5,6 +5,7 @@
- #include <northbridge/intel/haswell/haswell.h>
- #include <northbridge/intel/haswell/raminit.h>
- #include <southbridge/intel/lynxpoint/me.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
- #include <types.h>
- 
- static bool early_init_native(int s3resume)
-@@ -15,6 +16,8 @@ static bool early_init_native(int s3resume)
- 	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
- 	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
- 
-+	early_usb_init();
-+
- 	if (!CONFIG(INTEL_LYNXPOINT_LP))
- 		dmi_early_init();
- 
-diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
-index b8503ac8bc..0e1f2fe4eb 100644
---- a/src/southbridge/intel/lynxpoint/Makefile.inc
-+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
-@@ -37,7 +37,7 @@ bootblock-y += early_pch.c
- romstage-y += early_usb.c early_me.c me_status.c early_pch.c
- romstage-y += pmutil.c
- 
--romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c
-+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c
- 
- ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
- romstage-y += lp_gpio.c
-diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
-index a753681ce0..52e8ac17f8 100644
---- a/src/southbridge/intel/lynxpoint/early_usb.c
-+++ b/src/southbridge/intel/lynxpoint/early_usb.c
-@@ -4,17 +4,6 @@
- #include <device/pci_def.h>
- #include "pch.h"
- 
--/* HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index
-- * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
-- */
--#if CONFIG_USBDEBUG_HCD_INDEX != 2
--#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
--#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
--#else
--#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
--#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
--#endif
--
- /*
-  * Setup USB controller MMIO BAR to prevent the
-  * reference code from resetting the controller.
-diff --git a/src/southbridge/intel/lynxpoint/early_usb_native.c b/src/southbridge/intel/lynxpoint/early_usb_native.c
-new file mode 100644
-index 0000000000..cb6f6ee8e6
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/early_usb_native.c
-@@ -0,0 +1,584 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <delay.h>
-+#include <device/mmio.h>
-+#include <device/pci_def.h>
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/raminit.h>
-+#include <southbridge/intel/lynxpoint/iobp.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
-+#include <timer.h>
-+#include <types.h>
-+
-+static unsigned int is_usbr_enabled(void)
-+{
-+	return !!(pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) & BIT(5));
-+}
-+
-+static char *const xhci_bar = (char *)PCH_XHCI_TEMP_BAR0;
-+
-+static void ehci_hcs_init(const pci_devfn_t dev, const uintptr_t ehci_bar)
-+{
-+	pci_write_config32(dev, PCI_BASE_ADDRESS_0, ehci_bar);
-+
-+	/** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/
-+	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-+
-+	char *const mem_bar = (char *)ehci_bar;
-+
-+	/**
-+	 * Shared EHCI/XHCI ports w/a.
-+	 * This step is required when some of the ports are routed to EHCI
-+	 * and other ports are routed XHCI at the same time.
-+	 *
-+	 * FIXME: Under which conditions should this be done?
-+	 */
-+	pci_and_config16(dev, 0x78, ~0x03);
-+
-+	/* Skip reset if usbdebug is enabled */
-+	if (!CONFIG(USBDEBUG_IN_PRE_RAM))
-+		setbits32(mem_bar + EHCI_USB_CMD, EHCI_USB_CMD_HCRESET);
-+
-+	/* 2: Configure number of controllers and ports */
-+	pci_or_config16(dev, EHCI_ACCESS_CNTL, ACCESS_CNTL_ENABLE);
-+	clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf << 12, 0);
-+	clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf <<  0, 2 + is_usbr_enabled());
-+	pci_and_config16(dev, EHCI_ACCESS_CNTL, ~ACCESS_CNTL_ENABLE);
-+
-+	pci_or_config16(dev, 0x78, BIT(2));
-+	pci_or_config16(dev, 0x7c, BIT(14) | BIT(7));
-+	pci_update_config32(dev, 0x8c, ~(0xf << 8), (4 << 8));
-+	pci_update_config32(dev, 0x8c, ~BIT(26), BIT(17));
-+}
-+
-+static inline unsigned int physical_port_count(void)
-+{
-+	return MAX_USB2_PORTS;
-+}
-+
-+static unsigned int hs_port_count(void)
-+{
-+	/** TODO: Apparently, WPT-LP has 10 USB2 ports **/
-+	if (CONFIG(INTEL_LYNXPOINT_LP))
-+		return 8;
-+
-+	switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 1) & 3) {
-+	case 3:
-+		return 8;
-+	case 2:
-+		return 10;
-+	case 1:
-+		return 12;
-+	case 0:
-+	default:
-+		return 14;
-+	}
-+}
-+
-+static unsigned int ss_port_count(void)
-+{
-+	if (CONFIG(INTEL_LYNXPOINT_LP))
-+		return 4;
-+
-+	switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 3) & 3) {
-+	case 3:
-+		return 0;
-+	case 2:
-+		return 2;
-+	case 1:
-+		return 4;
-+	case 0:
-+	default:
-+		return 6;
-+	}
-+}
-+
-+static void common_ehci_hcs_init(void)
-+{
-+	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
-+
-+	ehci_hcs_init(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0);
-+	if (!is_lp)
-+		ehci_hcs_init(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0);
-+
-+	pch_iobp_update(0xe5007f04, 0, 0x00004481);
-+
-+	for (unsigned int port = 0; port < physical_port_count(); port++)
-+		pch_iobp_update(0xe500400f + port * 0x100, ~(1 << 0), 0 << 0);
-+
-+	pch_iobp_update(0xe5007f14, ~(3 << 19), (3 << 19));
-+
-+	if (is_lp)
-+		pch_iobp_update(0xe5007f02, ~(3 << 22), (0 << 22));
-+}
-+
-+static void xhci_open_memory_space(void)
-+{
-+	/** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/
-+	pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, (uintptr_t)xhci_bar);
-+	pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
-+}
-+
-+static void xhci_close_memory_space(void)
-+{
-+	pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
-+	pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, 0);
-+}
-+
-+static void common_xhci_hc_init(void)
-+{
-+	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
-+
-+	if (!is_lp) {
-+		const unsigned int max_ports = 15 + ss_port_count();
-+		clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_1, 0xf << 28, max_ports << 28);
-+	}
-+
-+	clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_3, 0xffff << 16 | 0xff, 0x200 << 16 | 0x0a);
-+	clrsetbits32(xhci_bar + XHCI_HCC_PARAMS, BIT(5), BIT(10) | BIT(9));
-+
-+	if (!is_lp)
-+		clrsetbits32(xhci_bar + 0x8008, BIT(19), 0);
-+
-+	if (is_lp)
-+		clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16));
-+	else
-+		clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16) | BIT(20));
-+
-+	clrsetbits32(xhci_bar + 0x8060, 0, BIT(25) | BIT(18));
-+	clrsetbits32(xhci_bar + 0x8090, 0, BIT(14) | BIT(8));
-+	clrsetbits32(xhci_bar + 0x8094, 0, BIT(23) | BIT(21) | BIT(14));
-+	clrsetbits32(xhci_bar + 0x80e0, BIT(16), BIT(6));
-+	clrsetbits32(xhci_bar + 0x80ec, (7 << 12) | (7 << 9), (0 << 12) | (6 << 9));
-+	clrsetbits32(xhci_bar + 0x80f0, BIT(20), 0);
-+
-+	if (is_lp)
-+		clrsetbits32(xhci_bar + 0x80fc, 0, BIT(25));
-+
-+	if (is_lp)
-+		clrsetbits32(xhci_bar + 0x8110, BIT(8) | BIT(2), BIT(20) | BIT(11));
-+	else
-+		clrsetbits32(xhci_bar + 0x8110, BIT(2), BIT(20) | BIT(11));
-+
-+	if (is_lp)
-+		write32(xhci_bar + 0x8140, 0xff00f03c);
-+	else
-+		write32(xhci_bar + 0x8140, 0xff03c132);
-+
-+	if (is_lp)
-+		clrsetbits32(xhci_bar + 0x8154, BIT(21), BIT(13));
-+	else
-+		clrsetbits32(xhci_bar + 0x8154, BIT(21) | BIT(13), 0);
-+
-+	clrsetbits32(xhci_bar + 0x8154, BIT(3), 0);
-+
-+	if (is_lp) {
-+		clrsetbits32(xhci_bar + 0x8164, 0, BIT(1) | BIT(0));
-+		write32(xhci_bar + 0x8174, 0x01400c0a);
-+		write32(xhci_bar + 0x817c, 0x033200a3);
-+		write32(xhci_bar + 0x8180, 0x00cb0028);
-+		write32(xhci_bar + 0x8184, 0x0064001e);
-+	}
-+
-+	/*
-+	 * Note: Register at offset 0x44 is 32-bit, but bit 31 is write-once.
-+	 * We use these weird partial accesses here to avoid locking bit 31.
-+	 */
-+	pci_or_config16(PCH_XHCI_DEV, 0x44, BIT(15) | BIT(14) | BIT(10) | BIT(0));
-+	pci_or_config8(PCH_XHCI_DEV, 0x44 + 2, 0x0f);
-+
-+	/* LPT-LP >= B0 */
-+	if (is_lp)
-+		clrsetbits32(xhci_bar + 0x8188, 0, BIT(26) | BIT(24));
-+
-+	/* LPT-H >= C0 */
-+	if (!is_lp)
-+		clrsetbits32(xhci_bar + 0x8188, 0, BIT(24));
-+}
-+
-+static inline bool is_mem_sr(void)
-+{
-+	return pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2) & GEN_PMCON_2_MEM_SR;
-+}
-+
-+static bool should_restore_xhci_smart_auto(void)
-+{
-+	if (!is_mem_sr())
-+		return false;
-+
-+	return pci_read_config32(PCH_LPC_DEV, PMIR) & PMIR_XHCI_SMART_AUTO;
-+}
-+
-+enum usb_port_route {
-+	ROUTE_TO_EHCI,
-+	ROUTE_TO_XHCI,
-+};
-+
-+/* Returns whether port reset was successful */
-+static bool reset_usb2_ports(const unsigned int ehci_ports)
-+{
-+	for (unsigned int port = 0; port < ehci_ports; port++) {
-+		/* Initiate port reset for all USB2 ports */
-+		clrsetbits32(
-+			xhci_bar + XHCI_USB2_PORTSC(port),
-+			XHCI_USB2_PORTSC_PED,
-+			XHCI_USB2_PORTSC_PR);
-+	}
-+	/* Poll for port reset bit to be cleared or time out at 100ms */
-+	struct stopwatch timer;
-+	stopwatch_init_msecs_expire(&timer, 100);
-+	uint32_t reg32;
-+	do {
-+		reg32 = 0;
-+		for (unsigned int port = 0; port < ehci_ports; port++)
-+			reg32 |= read32(xhci_bar + XHCI_USB2_PORTSC(port));
-+
-+		reg32 &= XHCI_USB2_PORTSC_PR;
-+		if (!reg32) {
-+			const long elapsed_time = stopwatch_duration_usecs(&timer);
-+			printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time);
-+			return true;
-+		}
-+		/* Reference code has a 10 ms delay here, but a smaller delay works too */
-+		udelay(100);
-+	} while (!stopwatch_expired(&timer));
-+	printk(BIOS_ERR, "%s: timed out\n", __func__);
-+	return !reg32;
-+}
-+
-+/* Returns whether warm reset was successful */
-+static bool warm_reset_usb3_ports(const unsigned int xhci_ports)
-+{
-+	for (unsigned int port = 0; port < xhci_ports; port++) {
-+		/* Initiate warm reset for all USB3 ports */
-+		clrsetbits32(
-+			xhci_bar + XHCI_USB3_PORTSC(port),
-+			XHCI_USB3_PORTSC_PED,
-+			XHCI_USB3_PORTSC_WPR);
-+	}
-+	/* Poll for port reset bit to be cleared or time out at 100ms */
-+	struct stopwatch timer;
-+	stopwatch_init_msecs_expire(&timer, 100);
-+	uint32_t reg32;
-+	do {
-+		reg32 = 0;
-+		for (unsigned int port = 0; port < xhci_ports; port++)
-+			reg32 |= read32(xhci_bar + XHCI_USB3_PORTSC(port));
-+
-+		reg32 &= XHCI_USB3_PORTSC_PR;
-+		if (!reg32) {
-+			const long elapsed_time = stopwatch_duration_usecs(&timer);
-+			printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time);
-+			return true;
-+		}
-+		/* Reference code has a 10 ms delay here, but a smaller delay works too */
-+		udelay(100);
-+	} while (!stopwatch_expired(&timer));
-+	printk(BIOS_ERR, "%s: timed out\n", __func__);
-+	return !reg32;
-+}
-+
-+static void perform_xhci_ehci_switching_flow(const enum usb_port_route usb_route)
-+{
-+	const pci_devfn_t dev = PCH_XHCI_DEV;
-+
-+	const unsigned int ehci_ports = hs_port_count() + is_usbr_enabled();
-+	const unsigned int xhci_ports = ss_port_count();
-+
-+	const uint32_t ehci_mask = BIT(ehci_ports) - 1;
-+	const uint32_t xhci_mask = BIT(xhci_ports) - 1;
-+
-+	/** TODO: Handle USBr port? How, though? **/
-+	pci_update_config32(dev, XHCI_USB2PRM, ~XHCI_USB2PR_HCSEL, ehci_mask);
-+	pci_update_config32(dev, XHCI_USB3PRM, ~XHCI_USB3PR_SSEN,  xhci_mask);
-+
-+	/*
-+	 * Workaround for USB2PR / USB3PR value not surviving warm reset.
-+	 * Restore USB Port Routing registers if OS HC Switch driver has been executed.
-+	 */
-+	if (should_restore_xhci_smart_auto()) {
-+		/** FIXME: Derive values from mainboard code instead? **/
-+		pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_mask);
-+		pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN,  xhci_mask);
-+	}
-+
-+	/* Later stages shouldn't need the value of this bit */
-+	pci_and_config32(PCH_LPC_DEV, PMIR, ~PMIR_XHCI_SMART_AUTO);
-+
-+	/**
-+	 * FIXME: Things here depend on the chosen routing mode.
-+	 *        For now, implement both functions.
-+	 */
-+
-+	/* Route to EHCI if xHCI disabled or auto mode */
-+	if (usb_route == ROUTE_TO_EHCI) {
-+		if (!reset_usb2_ports(ehci_ports))
-+			printk(BIOS_ERR, "USB2 port reset timed out\n");
-+
-+		pci_and_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL);
-+
-+		for (unsigned int port = 0; port < ehci_ports; port++) {
-+			clrsetbits32(
-+				xhci_bar + XHCI_USB2_PORTSC(port),
-+				XHCI_USB2_PORTSC_PED,
-+				XHCI_USB2_PORTSC_CHST);
-+		}
-+
-+		if (!warm_reset_usb3_ports(xhci_ports))
-+			printk(BIOS_ERR, "USB3 warm reset timed out\n");
-+
-+		/* FIXME: BWG says this should be inside the warm reset function */
-+		pci_and_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN);
-+
-+		for (unsigned int port = 0; port < ehci_ports; port++) {
-+			clrsetbits32(
-+				xhci_bar + XHCI_USB3_PORTSC(port),
-+				XHCI_USB3_PORTSC_PED,
-+				XHCI_USB3_PORTSC_CHST);
-+		}
-+
-+		setbits32(xhci_bar + XHCI_USBCMD, BIT(0));
-+		clrbits32(xhci_bar + XHCI_USBCMD, BIT(0));
-+	}
-+
-+	/* Route to xHCI if xHCI enabled */
-+	if (usb_route == ROUTE_TO_XHCI) {
-+		if (is_mem_sr()) {
-+			if (!warm_reset_usb3_ports(xhci_ports))
-+				printk(BIOS_ERR, "USB3 warm reset timed out\n");
-+		}
-+
-+		const uint32_t xhci_port_mask = pci_read_config32(dev, XHCI_USB3PRM) & 0x3f;
-+		pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN, xhci_port_mask);
-+
-+		const uint32_t ehci_port_mask = pci_read_config32(dev, XHCI_USB2PRM) & 0x7fff;
-+		pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_port_mask);
-+	}
-+}
-+
-+/* Do not shift in this macro, as it can cause undefined behaviour for bad port/oc values */
-+#define PORT_TO_OC_SHIFT(port, oc)	((oc) * 8 + (port))
-+
-+/* Avoid shifting into undefined behaviour */
-+static inline bool shift_ok(const int shift)
-+{
-+	return shift >= 0 && shift < 32;
-+}
-+
-+static void usb_overcurrent_mapping(void)
-+{
-+	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
-+
-+	uint32_t ehci_1_ocmap = 0;
-+	uint32_t ehci_2_ocmap = 0;
-+	uint32_t xhci_1_ocmap = 0;
-+	uint32_t xhci_2_ocmap = 0;
-+
-+	/*
-+	 * EHCI
-+	 */
-+	for (unsigned int idx = 0; idx < physical_port_count(); idx++) {
-+		const struct usb2_port_config *const port = &mainboard_usb2_ports[idx];
-+		printk(BIOS_DEBUG, "USB2 port %u => ", idx);
-+		if (!port->enable) {
-+			printk(BIOS_DEBUG, "disabled\n");
-+			continue;
-+		}
-+		const unsigned short oc_pin = port->oc_pin;
-+		if (oc_pin == USB_OC_PIN_SKIP) {
-+			printk(BIOS_DEBUG, "not mapped to OC pin\n");
-+			continue;
-+		}
-+		/* Ports 0 .. 7 => OC 0 .. 3 */
-+		if (idx < 8 && oc_pin <= 3) {
-+			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin);
-+			if (shift_ok(shift)) {
-+				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
-+				ehci_1_ocmap |= 1 << shift;
-+				continue;
-+			}
-+		}
-+		/* Ports 8 .. 13 => OC 4 .. 7 (LPT-H only) */
-+		if (!is_lp && idx >= 8 && oc_pin >= 4) {
-+			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4);
-+			if (shift_ok(shift)) {
-+				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
-+				ehci_2_ocmap |= 1 << shift;
-+				continue;
-+			}
-+		}
-+		printk(BIOS_ERR, "Invalid OC pin %u for USB2 port %u\n", oc_pin, idx);
-+	}
-+	printk(BIOS_DEBUG, "\n");
-+	pci_write_config32(PCH_EHCI1_DEV, EHCI_OCMAP, ehci_1_ocmap);
-+	if (!is_lp)
-+		pci_write_config32(PCH_EHCI2_DEV, EHCI_OCMAP, ehci_2_ocmap);
-+
-+	/*
-+	 * xHCI
-+	 */
-+	for (unsigned int idx = 0; idx < ss_port_count(); idx++) {
-+		const struct usb3_port_config *const port = &mainboard_usb3_ports[idx];
-+		printk(BIOS_DEBUG, "USB3 port %u => ", idx);
-+		if (!port->enable) {
-+			printk(BIOS_DEBUG, "disabled\n");
-+			continue;
-+		}
-+		const unsigned short oc_pin = port->oc_pin;
-+		if (oc_pin == USB_OC_PIN_SKIP) {
-+			printk(BIOS_DEBUG, "not mapped to OC pin\n");
-+			continue;
-+		}
-+		/* Ports 0 .. 5 => OC 0 .. 3 */
-+		if (oc_pin <= 3) {
-+			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin);
-+			if (shift_ok(shift)) {
-+				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
-+				xhci_1_ocmap |= 1 << shift;
-+				continue;
-+			}
-+		}
-+		/* Ports 0 .. 5 => OC 4 .. 7 (LPT-H only) */
-+		if (!is_lp && oc_pin >= 4) {
-+			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4);
-+			if (shift_ok(shift)) {
-+				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
-+				xhci_2_ocmap |= 1 << shift;
-+				continue;
-+			}
-+		}
-+		printk(BIOS_ERR, "Invalid OC pin %u for USB3 port %u\n", oc_pin, idx);
-+	}
-+	printk(BIOS_DEBUG, "\n");
-+	pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM1, ehci_1_ocmap);
-+	pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM1, xhci_1_ocmap);
-+	if (!is_lp) {
-+		pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM2, ehci_2_ocmap);
-+		pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM2, xhci_2_ocmap);
-+	}
-+}
-+
-+static uint8_t get_ehci_tune_param_1(const struct usb2_port_config *const port)
-+{
-+	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
-+
-+	const enum pch_platform_type plat_type = get_pch_platform_type();
-+	const enum usb2_port_location location = port->location;
-+	const uint16_t length = port->length;
-+	if (!is_lp) {
-+		if (plat_type == PCH_TYPE_DESKTOP) {
-+			if (location == USB_PORT_BACK_PANEL)
-+				return 4; /* Back Panel */
-+			else
-+				return 3; /* Front Panel */
-+
-+		} else if (plat_type == PCH_TYPE_MOBILE) {
-+			if (location == USB_PORT_INTERNAL)
-+				return 5; /* Internal Topology */
-+			else if (location == USB_PORT_DOCK)
-+				return 4; /* Dock */
-+			else if (length < 0x70)
-+				return 5; /* Back Panel, less than 7" */
-+			else
-+				return 6; /* Back Panel, 7" or more */
-+		}
-+	} else {
-+		if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) {
-+			if (length < 0x70)
-+				return 5; /* Back Panel, less than 7" */
-+			else
-+				return 6; /* Back Panel, 7" or more */
-+		} else if (location == USB_PORT_DOCK) {
-+			return 4; /* Dock */
-+		} else {
-+			return 5; /* Internal Topology */
-+		}
-+	}
-+	printk(BIOS_ERR, "%s: Unhandled case\n", __func__);
-+	return 0;
-+}
-+
-+static uint8_t get_ehci_tune_param_2(const struct usb2_port_config *const port)
-+{
-+	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
-+
-+	const enum pch_platform_type plat_type = get_pch_platform_type();
-+	const enum usb2_port_location location = port->location;
-+	const uint16_t length = port->length;
-+	if (!is_lp) {
-+		if (plat_type == PCH_TYPE_DESKTOP) {
-+			if (location == USB_PORT_BACK_PANEL) {
-+				if (length < 0x80)
-+					return 2; /* Back Panel, less than 8" */
-+				else if (length < 0x130)
-+					return 3; /* Back Panel, 8"-13" */
-+				else
-+					return 4; /* Back Panel, 13" or more */
-+			} else {
-+				return 2; /* Front Panel */
-+			}
-+
-+		} else if (plat_type == PCH_TYPE_MOBILE) {
-+			if (location == USB_PORT_INTERNAL) {
-+				return 2; /* Internal Topology */
-+			} else if (location == USB_PORT_DOCK) {
-+				if (length < 0x50)
-+					return 1; /* Dock, less than 5" */
-+				else
-+					return 2; /* Dock, 5" or more */
-+			} else {
-+				if (length < 0x100)
-+					return 2; /* Back Panel, less than 10" */
-+				else
-+					return 3; /* Back Panel, 10" or more */
-+			}
-+		}
-+	} else {
-+		if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) {
-+			if (length < 0x100)
-+				return 2; /* Back Panel, less than 10" */
-+			else
-+				return 3; /* Back Panel, 10" or more */
-+		} else if (location == USB_PORT_DOCK) {
-+			if (length < 0x50)
-+				return 1; /* Dock, less than 5" */
-+			else
-+				return 2; /* Dock, 5" or more */
-+		} else {
-+			return 2; /* Internal Topology */
-+		}
-+	}
-+	printk(BIOS_ERR, "%s: Unhandled case\n", __func__);
-+	return 0;
-+}
-+
-+static void program_ehci_port_length(void)
-+{
-+	for (unsigned int port = 0; port < physical_port_count(); port++) {
-+		if (!mainboard_usb2_ports[port].enable)
-+			continue;
-+		const uint32_t addr = 0xe5004000 + (port + 1) * 0x100;
-+		const uint8_t param_1 = get_ehci_tune_param_1(&mainboard_usb2_ports[port]);
-+		const uint8_t param_2 = get_ehci_tune_param_2(&mainboard_usb2_ports[port]);
-+		pch_iobp_update(addr, ~0x7f00, param_2 << 11 | param_1 << 8);
-+	}
-+}
-+
-+void early_usb_init(void)
-+{
-+	/** TODO: Make this configurable? How do the modes affect usbdebug? **/
-+	const enum usb_port_route usb_route = ROUTE_TO_XHCI;
-+	///(pd->boot_mode == 2 && pd->usb_xhci_on_resume) ? ROUTE_TO_XHCI : ROUTE_TO_EHCI;
-+
-+	common_ehci_hcs_init();
-+	xhci_open_memory_space();
-+	common_xhci_hc_init();
-+	perform_xhci_ehci_switching_flow(usb_route);
-+	usb_overcurrent_mapping();
-+	program_ehci_port_length();
-+	/** FIXME: USB per port control is missing, is it needed? **/
-+	xhci_close_memory_space();
-+	/** TODO: Close EHCI memory space? **/
-+}
-diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
-index b5e0c2a830..ad983d86cf 100644
---- a/src/southbridge/intel/lynxpoint/pch.h
-+++ b/src/southbridge/intel/lynxpoint/pch.h
-@@ -115,6 +115,7 @@ enum pch_platform_type {
- 
- void pch_dmi_setup_physical_layer(void);
- void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
-+void early_usb_init(void);
- 
- void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
- void usb_ehci_disable(pci_devfn_t dev);
-@@ -202,6 +203,8 @@ void mainboard_config_rcba(void);
- #define GEN_PMCON_1		0xa0
- #define  SMI_LOCK		(1 << 4)
- #define GEN_PMCON_2		0xa2
-+#define  GEN_PMCON_2_DISB	(1 << 7)
-+#define  GEN_PMCON_2_MEM_SR	(1 << 5)
- #define  SYSTEM_RESET_STS	(1 << 4)
- #define  THERMTRIP_STS		(1 << 3)
- #define  SYSPWR_FLR		(1 << 1)
-@@ -215,6 +218,7 @@ void mainboard_config_rcba(void);
- #define PMIR			0xac
- #define  PMIR_CF9LOCK		(1 << 31)
- #define  PMIR_CF9GR		(1 << 20)
-+#define  PMIR_XHCI_SMART_AUTO	(1 << 16) /* c.f. LPT BWG or WPT-LP BIOS spec */
- 
- /* GEN_PMCON_3 bits */
- #define RTC_BATTERY_DEAD	(1 << 2)
-@@ -282,6 +286,20 @@ void mainboard_config_rcba(void);
- #define SATA_DTLE_DATA_SHIFT	24
- #define SATA_DTLE_EDGE_SHIFT	16
- 
-+/*
-+ * HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index
-+ * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
-+ */
-+#if CONFIG_USBDEBUG_HCD_INDEX != 2
-+#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
-+#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
-+#else
-+#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
-+#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
-+#endif
-+
-+#define PCH_XHCI_TEMP_BAR0	0xe8100000
-+
- /* EHCI PCI Registers */
- #define EHCI_PWR_CTL_STS	0x54
- #define  PWR_CTL_SET_MASK	0x3
-@@ -289,10 +307,15 @@ void mainboard_config_rcba(void);
- #define  PWR_CTL_SET_D3		0x3
- #define  PWR_CTL_ENABLE_PME	(1 << 8)
- #define  PWR_CTL_STATUS_PME	(1 << 15)
-+#define EHCI_OCMAP		0x74
-+#define EHCI_ACCESS_CNTL	0x80
-+#define  ACCESS_CNTL_ENABLE	(1 << 0)
- 
- /* EHCI Memory Registers */
-+#define EHCI_HCS_PARAMS		0x04
- #define EHCI_USB_CMD		0x20
- #define  EHCI_USB_CMD_RUN	(1 << 0)
-+#define  EHCI_USB_CMD_HCRESET	(1 << 1)
- #define  EHCI_USB_CMD_PSE	(1 << 4)
- #define  EHCI_USB_CMD_ASE	(1 << 5)
- #define EHCI_PORTSC(port)	(0x64 + (port) * 4)
-@@ -301,6 +324,10 @@ void mainboard_config_rcba(void);
- 
- /* XHCI PCI Registers */
- #define XHCI_PWR_CTL_STS	0x74
-+#define XHCI_U2OCM1		0xc0
-+#define XHCI_U2OCM2		0xc4
-+#define XHCI_U3OCM1		0xc8
-+#define XHCI_U3OCM2		0xcc
- #define XHCI_USB2PR		0xd0
- #define XHCI_USB2PRM		0xd4
- #define  XHCI_USB2PR_HCSEL	0x7fff
-@@ -313,6 +340,27 @@ void mainboard_config_rcba(void);
- #define XHCI_USB3PDO		0xe8
- 
- /* XHCI Memory Registers */
-+#define XHCI_HCS_PARAMS_1	0x04
-+#define XHCI_HCS_PARAMS_2	0x08
-+#define XHCI_HCS_PARAMS_3	0x0c
-+#define XHCI_HCC_PARAMS		0x10
-+#define XHCI_USBCMD		0x80
-+#define XHCI_USB2_PORTSC(port)	(0x480 + ((port) * 0x10))
-+#define  XHCI_USB2_PORTSC_WPR	(1 << 31)	/* Warm Port Reset */
-+#define  XHCI_USB2_PORTSC_CEC	(1 << 23)	/* Port Config Error Change */
-+#define  XHCI_USB2_PORTSC_PLC	(1 << 22)	/* Port Link State Change */
-+#define  XHCI_USB2_PORTSC_PRC	(1 << 21)	/* Port Reset Change */
-+#define  XHCI_USB2_PORTSC_OCC	(1 << 20)	/* Over-current Change */
-+#define  XHCI_USB2_PORTSC_WRC	(1 << 19)	/* Warm Port Reset Change */
-+#define  XHCI_USB2_PORTSC_PEC	(1 << 18)	/* Port Enabled Disabled Change */
-+#define  XHCI_USB2_PORTSC_CSC	(1 << 17)	/* Connect Status Change */
-+#define  XHCI_USB2_PORTSC_CHST	(0x7f << 17)
-+#define  XHCI_USB2_PORTSC_LWS	(1 << 16)	/* Port Link State Write Strobe */
-+#define  XHCI_USB2_PORTSC_PP	(1 <<  9)
-+#define  XHCI_USB2_PORTSC_PR	(1 <<  4)	/* Port Reset */
-+#define  XHCI_USB2_PORTSC_PED	(1 <<  1)	/* Port Enable/Disabled */
-+#define  XHCI_USB2_PORTSC_CCS	(1 <<  0)	/* Current Connect Status */
-+
- #define XHCI_USB3_PORTSC(port)	((pch_is_lp() ? 0x510 : 0x570) + ((port) * 0x10))
- #define  XHCI_USB3_PORTSC_CHST	(0x7f << 17)
- #define  XHCI_USB3_PORTSC_WCE	(1 << 25)	/* Wake on Connect */
-@@ -320,6 +368,7 @@ void mainboard_config_rcba(void);
- #define  XHCI_USB3_PORTSC_WOE	(1 << 27)	/* Wake on Overcurrent */
- #define  XHCI_USB3_PORTSC_WRC	(1 << 19)	/* Warm Reset Complete */
- #define  XHCI_USB3_PORTSC_LWS	(1 << 16)	/* Link Write Strobe */
-+#define  XHCI_USB3_PORTSC_PR	(1 << 4)	/* Port Reset */
- #define  XHCI_USB3_PORTSC_PED	(1 << 1)	/* Port Enabled/Disabled */
- #define  XHCI_USB3_PORTSC_WPR	(1 << 31)	/* Warm Port Reset */
- #define  XHCI_USB3_PORTSC_PLS	(0xf << 5)	/* Port Link State */
--- 
-2.39.2
-

config/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch

@@ -1,128 +0,0 @@
-From 92be49d8422b4bc1c89bb49535f4dc6a01d47295 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 23:22:11 +0200
-Subject: [PATCH 06/26] sb/intel/lynxpoint: Add native thermal init
-
-Implement native thermal initialisation for Lynx Point. This is only
-needed when MRC.bin is not used.
-
-Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../haswell/native_raminit/raminit_native.c   |  1 +
- src/southbridge/intel/lynxpoint/Makefile.inc  |  2 +-
- src/southbridge/intel/lynxpoint/pch.h         |  1 +
- src/southbridge/intel/lynxpoint/thermal.c     | 64 +++++++++++++++++++
- 4 files changed, 67 insertions(+), 1 deletion(-)
- create mode 100644 src/southbridge/intel/lynxpoint/thermal.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index ef61d4ee09..dd1f1ec14e 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -16,6 +16,7 @@ static bool early_init_native(int s3resume)
- 	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
- 	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
- 
-+	early_thermal_init();
- 	early_usb_init();
- 
- 	if (!CONFIG(INTEL_LYNXPOINT_LP))
-diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
-index 0e1f2fe4eb..a9a9b153d6 100644
---- a/src/southbridge/intel/lynxpoint/Makefile.inc
-+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
-@@ -37,7 +37,7 @@ bootblock-y += early_pch.c
- romstage-y += early_usb.c early_me.c me_status.c early_pch.c
- romstage-y += pmutil.c
- 
--romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c
-+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c
- 
- ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
- romstage-y += lp_gpio.c
-diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
-index ad983d86cf..38a9349220 100644
---- a/src/southbridge/intel/lynxpoint/pch.h
-+++ b/src/southbridge/intel/lynxpoint/pch.h
-@@ -116,6 +116,7 @@ enum pch_platform_type {
- void pch_dmi_setup_physical_layer(void);
- void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
- void early_usb_init(void);
-+void early_thermal_init(void);
- 
- void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
- void usb_ehci_disable(pci_devfn_t dev);
-diff --git a/src/southbridge/intel/lynxpoint/thermal.c b/src/southbridge/intel/lynxpoint/thermal.c
-new file mode 100644
-index 0000000000..e71969ea0c
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/thermal.c
-@@ -0,0 +1,64 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/mmio.h>
-+#include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/pch.h>
-+#include <types.h>
-+
-+#define TBARB_TEMP 0x40000000
-+
-+#define THERMAL_DEV PCI_DEV(0, 0x1f, 6)
-+
-+/* Early thermal init, it may need to be done prior to giving ME its memory */
-+void early_thermal_init(void)
-+{
-+	/* Program address for temporary BAR */
-+	pci_write_config32(THERMAL_DEV, 0x40, TBARB_TEMP);
-+	pci_write_config32(THERMAL_DEV, 0x44, 0);
-+
-+	/* Activate temporary BAR */
-+	pci_or_config32(THERMAL_DEV, 0x40, 1);
-+
-+	/*
-+	 * BWG section 17.3.1 says:
-+	 *
-+	 * ### Initializing Lynx Point Thermal Sensors ###
-+	 *
-+	 * The System BIOS must perform the following steps to initialize the Lynx
-+	 * Point thermal subsystem device, D31:F6. The System BIOS is required to
-+	 * repeat this process on a resume from Sx. BIOS may enable any or all of
-+	 * the registers below based on OEM's platform configuration. Intel does
-+	 * not recommend a value on some of the registers, since each platform has
-+	 * different temperature trip points and one may enable a trip to cause an
-+	 * SMI while another platform would cause an interrupt instead.
-+	 *
-+	 * The recommended flow for enabling thermal sensor is by setting up various
-+	 * temperature trip points first, followed by enabling the desired trip
-+	 * alert method and then enable the actual sensors from TSEL registers.
-+	 * If this flow is not followed, software will need to take special care
-+	 * to handle false events during setting up those registers.
-+	 */
-+
-+	/* Step 1: Program CTT */
-+	write16p(TBARB_TEMP + 0x10, 0x0154);
-+
-+	/* Step 2: Clear trip status from TSS and TAS */
-+	write8p(TBARB_TEMP + 0x06, 0xff);
-+	write8p(TBARB_TEMP + 0x80, 0xff);
-+
-+	/* Step 3: Program TSGPEN and TSPIEN to zero */
-+	write8p(TBARB_TEMP + 0x84, 0x00);
-+	write8p(TBARB_TEMP + 0x82, 0x00);
-+
-+	/*
-+	 * Step 4: If thermal reporting to an EC over SMBus is supported,
-+	 *         then write 0x01 to TSREL, else leave at default.
-+	 */
-+	write8p(TBARB_TEMP + 0x0a, 0x01);
-+
-+	/* Disable temporary BAR */
-+	pci_and_config32(THERMAL_DEV, 0x40, ~1);
-+
-+	/* Clear temporary BAR address */
-+	pci_write_config32(THERMAL_DEV, 0x40, 0);
-+}
--- 
-2.39.2
-

config/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch

@@ -1,785 +0,0 @@
-From 7378cb4fefc87b9a096bb14820a44f26f3a628f5 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Fri, 6 May 2022 23:43:46 +0200
-Subject: [PATCH 07/26] sb/intel/lynxpoint: Add native PCH init
-
-Implement native PCH initialisation for Lynx Point. This is only needed
-when MRC.bin is not used.
-
-Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../haswell/native_raminit/raminit_native.c   |   3 +-
- src/southbridge/intel/lynxpoint/Makefile.inc  |   1 +
- .../intel/lynxpoint/early_pch_native.c        | 123 +++++++++
- .../intel/lynxpoint/hsio/Makefile.inc         |   8 +
- src/southbridge/intel/lynxpoint/hsio/common.c |  52 ++++
- src/southbridge/intel/lynxpoint/hsio/hsio.h   |  46 ++++
- .../intel/lynxpoint/hsio/lpt_h_cx.c           | 244 ++++++++++++++++++
- .../intel/lynxpoint/hsio/lpt_lp_bx.c          | 180 +++++++++++++
- src/southbridge/intel/lynxpoint/pch.h         |   6 +
- 9 files changed, 661 insertions(+), 2 deletions(-)
- create mode 100644 src/southbridge/intel/lynxpoint/hsio/Makefile.inc
- create mode 100644 src/southbridge/intel/lynxpoint/hsio/common.c
- create mode 100644 src/southbridge/intel/lynxpoint/hsio/hsio.h
- create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
- create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index dd1f1ec14e..b6efb6b40d 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -16,8 +16,7 @@ static bool early_init_native(int s3resume)
- 	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
- 	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
- 
--	early_thermal_init();
--	early_usb_init();
-+	early_pch_init_native(s3resume);
- 
- 	if (!CONFIG(INTEL_LYNXPOINT_LP))
- 		dmi_early_init();
-diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
-index a9a9b153d6..63243ecc86 100644
---- a/src/southbridge/intel/lynxpoint/Makefile.inc
-+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
-@@ -38,6 +38,7 @@ romstage-y += early_usb.c early_me.c me_status.c early_pch.c
- romstage-y += pmutil.c
- 
- romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c
-+subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio
- 
- ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
- romstage-y += lp_gpio.c
-diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c
-index c28ddfcf5d..421821fa5d 100644
---- a/src/southbridge/intel/lynxpoint/early_pch_native.c
-+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c
-@@ -1,10 +1,133 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
- #include <console/console.h>
-+#include <device/pci_def.h>
- #include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
- #include <southbridge/intel/lynxpoint/pch.h>
- #include <types.h>
- 
-+static void early_sata_init(const uint8_t pch_revision)
-+{
-+	const bool is_mobile = get_pch_platform_type() != PCH_TYPE_DESKTOP;
-+
-+	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
-+	printk(BIOS_DEBUG, "HSIO lane owner: 0x%02x\n", lane_owner);
-+
-+	/* BWG Step 2 */
-+	pci_update_config32(PCH_SATA_DEV, SATA_SCLKG, ~0x1ff, 0x183);
-+
-+	/* BWG Step 3: Set OOB Retry Mode */
-+	pci_or_config16(PCH_SATA_DEV, SATA_PCS, 1 << 15);
-+
-+	/* BWG Step 4: Program the SATA mPHY tables */
-+	if (pch_is_lp()) {
-+		if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) {
-+			program_hsio_sata_lpt_lp_bx(is_mobile);
-+		} else {
-+			printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision);
-+		}
-+	} else {
-+		if (pch_revision >= LPT_H_STEP_C0) {
-+			program_hsio_sata_lpt_h_cx(is_mobile);
-+		} else {
-+			printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision);
-+		}
-+	}
-+
-+	/** FIXME: Program SATA RxEq tables **/
-+
-+	/* BWG Step 5 */
-+	/** FIXME: Only for desktop and mobile (skip this on workstation and server) **/
-+	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(22));
-+
-+	/* BWG Step 6 */
-+	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(19));
-+
-+	/* BWG Step 7 */
-+	pci_update_config32(PCH_SATA_DEV, 0x98, ~(0x3f << 7), 0x04 << 7);
-+
-+	/* BWG Step 8 */
-+	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(20));
-+
-+	/* BWG Step 9 */
-+	pci_update_config32(PCH_SATA_DEV, 0x98, ~(3 << 5), 1 << 5);
-+
-+	/* BWG Step 10 */
-+	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(18));
-+
-+	/* Enable SATA ports */
-+	uint8_t sata_pcs = 0;
-+	if (CONFIG(INTEL_LYNXPOINT_LP)) {
-+		for (uint8_t i = 0; i < 4; i++) {
-+			if ((lane_owner & BIT(7 - i)) == 0) {
-+				sata_pcs |= BIT(i);
-+			}
-+		}
-+	} else {
-+		sata_pcs |= 0x0f;
-+		for (uint8_t i = 4; i < 6; i++) {
-+			if ((lane_owner & BIT(i)) == 0) {
-+				sata_pcs |= BIT(i);
-+			}
-+		}
-+	}
-+	printk(BIOS_DEBUG, "SATA port enables: 0x%02x\n", sata_pcs);
-+	pci_or_config8(PCH_SATA_DEV, SATA_PCS, sata_pcs);
-+}
-+
-+void early_pch_init_native(int s3resume)
-+{
-+	const uint8_t pch_revision = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
-+
-+	RCBA16(DISPBDF) = 0x0010;
-+	RCBA32_OR(FD2, PCH_ENABLE_DBDF);
-+
-+	/** FIXME: Check GEN_PMCON_3 and handle RTC failure? **/
-+
-+	RCBA32(PRSTS) = BIT(4);
-+
-+	early_sata_init(pch_revision);
-+
-+	pci_or_config8(PCH_LPC_DEV, 0xa6, 1 << 1);
-+	pci_and_config8(PCH_LPC_DEV, 0xdc, ~(1 << 5 | 1 << 1));
-+
-+	/** TODO: Send GET HSIO VER and update ChipsetInit table? Is it needed? **/
-+
-+	/** FIXME: GbE handling? **/
-+
-+	pci_update_config32(PCH_LPC_DEV, 0xac, ~(1 << 20), 0);
-+
-+	for (uint8_t i = 0; i < 8; i++)
-+		pci_update_config32(PCI_DEV(0, 0x1c, i), 0x338, ~(1 << 26), 0);
-+
-+	pci_update_config8(PCI_DEV(0, 0x1c, 0), 0xf4, ~(3 << 5), 1 << 7);
-+
-+	pci_update_config8(PCI_DEV(0, 26, 0), 0x88, ~(1 << 2), 0);
-+	pci_update_config8(PCI_DEV(0, 29, 0), 0x88, ~(1 << 2), 0);
-+
-+	/** FIXME: Disable SATA2 device? **/
-+
-+	if (pch_is_lp()) {
-+		if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) {
-+			program_hsio_xhci_lpt_lp_bx();
-+			program_hsio_igbe_lpt_lp_bx();
-+		} else {
-+			printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision);
-+		}
-+	} else {
-+		if (pch_revision >= LPT_H_STEP_C0) {
-+			program_hsio_xhci_lpt_h_cx();
-+			program_hsio_igbe_lpt_h_cx();
-+		} else {
-+			printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision);
-+		}
-+	}
-+
-+	early_thermal_init();
-+	early_usb_init();
-+}
-+
- void pch_dmi_setup_physical_layer(void)
- {
- 	/* FIXME: We need to make sure the SA supports Gen2 as well */
-diff --git a/src/southbridge/intel/lynxpoint/hsio/Makefile.inc b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc
-new file mode 100644
-index 0000000000..6b74997511
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc
-@@ -0,0 +1,8 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+romstage-y += common.c
-+ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
-+romstage-y += lpt_lp_bx.c
-+else
-+romstage-y += lpt_h_cx.c
-+endif
-diff --git a/src/southbridge/intel/lynxpoint/hsio/common.c b/src/southbridge/intel/lynxpoint/hsio/common.c
-new file mode 100644
-index 0000000000..9935ca347a
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/hsio/common.c
-@@ -0,0 +1,52 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
-+#include <types.h>
-+
-+/*
-+ * FIXME: Ask Intel whether all lanes need to be programmed as specified
-+ * in the PCH BWG. If not, make separate tables and only check this once.
-+ */
-+void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or)
-+{
-+	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
-+
-+	if ((addr & 0xfe00) == 0x2000 && (lane_owner & (1 << 4)))
-+		return;
-+
-+	if ((addr & 0xfe00) == 0x2200 && (lane_owner & (1 << 5)))
-+		return;
-+
-+	if (CONFIG(INTEL_LYNXPOINT_LP)) {
-+		if ((addr & 0xfe00) == 0x2400 && (lane_owner & (1 << 6)))
-+			return;
-+
-+		if ((addr & 0xfe00) == 0x2600 && (lane_owner & (1 << 7)))
-+			return;
-+	}
-+	hsio_update(addr, and, or);
-+}
-+
-+/*
-+ * FIXME: Ask Intel whether all lanes need to be programmed as specified
-+ * in the PCH BWG. If not, make separate tables and only check this once.
-+ */
-+void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or)
-+{
-+	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
-+	if (CONFIG(INTEL_LYNXPOINT_LP)) {
-+		if ((addr & 0xfe00) == 0x2400 && ((lane_owner >> 0) & 3) != 2)
-+			return;
-+
-+		if ((addr & 0xfe00) == 0x2600 && ((lane_owner >> 2) & 3) != 2)
-+			return;
-+	} else {
-+		if ((addr & 0xfe00) == 0x2c00 && ((lane_owner >> 2) & 3) != 2)
-+			return;
-+
-+		if ((addr & 0xfe00) == 0x2e00 && ((lane_owner >> 0) & 3) != 2)
-+			return;
-+	}
-+	hsio_update(addr, and, or);
-+}
-diff --git a/src/southbridge/intel/lynxpoint/hsio/hsio.h b/src/southbridge/intel/lynxpoint/hsio/hsio.h
-new file mode 100644
-index 0000000000..689ef4a05b
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/hsio/hsio.h
-@@ -0,0 +1,46 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H
-+#define SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H
-+
-+#include <southbridge/intel/lynxpoint/iobp.h>
-+#include <types.h>
-+
-+struct hsio_table_row {
-+	uint32_t addr;
-+	uint32_t and;
-+	uint32_t or;
-+};
-+
-+static inline void hsio_update(const uint32_t addr, const uint32_t and, const uint32_t or)
-+{
-+	pch_iobp_update(addr, and, or);
-+}
-+
-+static inline void hsio_update_row(const struct hsio_table_row row)
-+{
-+	hsio_update(row.addr, row.and, row.or);
-+}
-+
-+void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or);
-+void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or);
-+
-+static inline void hsio_sata_shared_update_row(const struct hsio_table_row row)
-+{
-+	hsio_sata_shared_update(row.addr, row.and, row.or);
-+}
-+
-+static inline void hsio_xhci_shared_update_row(const struct hsio_table_row row)
-+{
-+	hsio_xhci_shared_update(row.addr, row.and, row.or);
-+}
-+
-+void program_hsio_sata_lpt_h_cx(const bool is_mobile);
-+void program_hsio_xhci_lpt_h_cx(void);
-+void program_hsio_igbe_lpt_h_cx(void);
-+
-+void program_hsio_sata_lpt_lp_bx(const bool is_mobile);
-+void program_hsio_xhci_lpt_lp_bx(void);
-+void program_hsio_igbe_lpt_lp_bx(void);
-+
-+#endif
-diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
-new file mode 100644
-index 0000000000..b5dd402742
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
-@@ -0,0 +1,244 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
-+#include <types.h>
-+
-+const struct hsio_table_row hsio_sata_shared_lpt_h_cx[] = {
-+	{ 0xea002008, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002208, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002038, ~0x3f00000f, 0x0700000d },
-+	{ 0xea002238, ~0x3f00000f, 0x0700000d },
-+	{ 0xea00202c, ~0x00020f00, 0x00020100 },
-+	{ 0xea00222c, ~0x00020f00, 0x00020100 },
-+	{ 0xea002040, ~0x1f000000, 0x01000000 },
-+	{ 0xea002240, ~0x1f000000, 0x01000000 },
-+	{ 0xea002010, ~0xffff0000, 0x0d510000 },
-+	{ 0xea002210, ~0xffff0000, 0x0d510000 },
-+	{ 0xea002018, ~0xffff0300, 0x38250100 },
-+	{ 0xea002218, ~0xffff0300, 0x38250100 },
-+	{ 0xea002000, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002200, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002028, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea002228, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea00201c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00221c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00208c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00228c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea0020a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0022a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0020ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0022ac, ~0x00000030, 0x00000020 },
-+	{ 0xea002140, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002340, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002144, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002344, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002148, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002348, ~0x00ffffff, 0x00140998 },
-+	{ 0xea00217c, ~0x03000000, 0x03000000 },
-+	{ 0xea00237c, ~0x03000000, 0x03000000 },
-+	{ 0xea002178, ~0x00001f00, 0x00001800 },
-+	{ 0xea002378, ~0x00001f00, 0x00001800 },
-+	{ 0xea00210c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00230c, ~0x0038000f, 0x00000005 },
-+};
-+
-+const struct hsio_table_row hsio_sata_lpt_h_cx[] = {
-+	{ 0xea008008, ~0xff000000, 0x1c000000 },
-+	{ 0xea002408, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002608, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea000808, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea000a08, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002438, ~0x3f00000f, 0x0700000d },
-+	{ 0xea002638, ~0x3f00000f, 0x0700000d },
-+	{ 0xea000838, ~0x3f00000f, 0x0700000d },
-+	{ 0xea000a38, ~0x3f00000f, 0x0700000d },
-+	{ 0xea002440, ~0x1f000000, 0x01000000 },
-+	{ 0xea002640, ~0x1f000000, 0x01000000 },
-+	{ 0xea000840, ~0x1f000000, 0x01000000 },
-+	{ 0xea000a40, ~0x1f000000, 0x01000000 },
-+	{ 0xea002410, ~0xffff0000, 0x0d510000 },
-+	{ 0xea002610, ~0xffff0000, 0x0d510000 },
-+	{ 0xea000810, ~0xffff0000, 0x0d510000 },
-+	{ 0xea000a10, ~0xffff0000, 0x0d510000 },
-+	{ 0xea00242c, ~0x00020800, 0x00020000 },
-+	{ 0xea00262c, ~0x00020800, 0x00020000 },
-+	{ 0xea00082c, ~0x00020800, 0x00020000 },
-+	{ 0xea000a2c, ~0x00020800, 0x00020000 },
-+	{ 0xea002418, ~0xffff0300, 0x38250100 },
-+	{ 0xea002618, ~0xffff0300, 0x38250100 },
-+	{ 0xea000818, ~0xffff0300, 0x38250100 },
-+	{ 0xea000a18, ~0xffff0300, 0x38250100 },
-+	{ 0xea002400, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002600, ~0xcf030000, 0xcf030000 },
-+	{ 0xea000800, ~0xcf030000, 0xcf030000 },
-+	{ 0xea000a00, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002428, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea002628, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea000828, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea000a28, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea00241c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00261c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00081c, ~0x00007c00, 0x00002400 },
-+	{ 0xea000a1c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00248c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00268c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00088c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea000a8c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea0024a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0026a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0008a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea000aa4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0024ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0026ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0008ac, ~0x00000030, 0x00000020 },
-+	{ 0xea000aac, ~0x00000030, 0x00000020 },
-+	{ 0xea002540, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002740, ~0x00ffffff, 0x00140718 },
-+	{ 0xea000940, ~0x00ffffff, 0x00140718 },
-+	{ 0xea000b40, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002544, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002744, ~0x00ffffff, 0x00140998 },
-+	{ 0xea000944, ~0x00ffffff, 0x00140998 },
-+	{ 0xea000b44, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002548, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002748, ~0x00ffffff, 0x00140998 },
-+	{ 0xea000948, ~0x00ffffff, 0x00140998 },
-+	{ 0xea000b48, ~0x00ffffff, 0x00140998 },
-+	{ 0xea00257c, ~0x03000000, 0x03000000 },
-+	{ 0xea00277c, ~0x03000000, 0x03000000 },
-+	{ 0xea00097c, ~0x03000000, 0x03000000 },
-+	{ 0xea000b7c, ~0x03000000, 0x03000000 },
-+	{ 0xea002578, ~0x00001f00, 0x00001800 },
-+	{ 0xea002778, ~0x00001f00, 0x00001800 },
-+	{ 0xea000978, ~0x00001f00, 0x00001800 },
-+	{ 0xea000b78, ~0x00001f00, 0x00001800 },
-+	{ 0xea00250c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00270c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00090c, ~0x0038000f, 0x00000005 },
-+	{ 0xea000b0c, ~0x0038000f, 0x00000005 },
-+};
-+
-+const struct hsio_table_row hsio_xhci_shared_lpt_h_cx[] = {
-+	{ 0xe9002c2c, ~0x00000700, 0x00000100 },
-+	{ 0xe9002e2c, ~0x00000700, 0x00000100 },
-+	{ 0xe9002dcc, ~0x00001407, 0x00001407 },
-+	{ 0xe9002fcc, ~0x00001407, 0x00001407 },
-+	{ 0xe9002d68, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9002f68, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9002d6c, ~0x000000ff, 0x0000003f },
-+	{ 0xe9002f6c, ~0x000000ff, 0x0000003f },
-+	{ 0xe9002d4c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe9002f4c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe9002d14, ~0x38000700, 0x00000100 },
-+	{ 0xe9002f14, ~0x38000700, 0x00000100 },
-+	{ 0xe9002d64, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002f64, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002d70, ~0x00000018, 0x00000000 },
-+	{ 0xe9002f70, ~0x00000018, 0x00000000 },
-+	{ 0xe9002c38, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9002e38, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9002d40, ~0x00800000, 0x00000000 },
-+	{ 0xe9002f40, ~0x00800000, 0x00000000 },
-+};
-+
-+const struct hsio_table_row hsio_xhci_lpt_h_cx[] = {
-+	{ 0xe90031cc, ~0x00001407, 0x00001407 },
-+	{ 0xe90033cc, ~0x00001407, 0x00001407 },
-+	{ 0xe90015cc, ~0x00001407, 0x00001407 },
-+	{ 0xe90017cc, ~0x00001407, 0x00001407 },
-+	{ 0xe9003168, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9003368, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9001568, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9001768, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe900316c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900336c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900156c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900176c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900314c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe900334c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe900154c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe900174c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe9003114, ~0x38000700, 0x00000100 },
-+	{ 0xe9003314, ~0x38000700, 0x00000100 },
-+	{ 0xe9001514, ~0x38000700, 0x00000100 },
-+	{ 0xe9001714, ~0x38000700, 0x00000100 },
-+	{ 0xe9003164, ~0x0000f000, 0x00005000 },
-+	{ 0xe9003364, ~0x0000f000, 0x00005000 },
-+	{ 0xe9001564, ~0x0000f000, 0x00005000 },
-+	{ 0xe9001764, ~0x0000f000, 0x00005000 },
-+	{ 0xe9003170, ~0x00000018, 0x00000000 },
-+	{ 0xe9003370, ~0x00000018, 0x00000000 },
-+	{ 0xe9001570, ~0x00000018, 0x00000000 },
-+	{ 0xe9001770, ~0x00000018, 0x00000000 },
-+	{ 0xe9003038, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9003238, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9001438, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9001638, ~0x3f00000f, 0x0700000b },
-+	{ 0xe9003140, ~0x00800000, 0x00000000 },
-+	{ 0xe9003340, ~0x00800000, 0x00000000 },
-+	{ 0xe9001540, ~0x00800000, 0x00000000 },
-+	{ 0xe9001740, ~0x00800000, 0x00000000 },
-+};
-+
-+void program_hsio_sata_lpt_h_cx(const bool is_mobile)
-+{
-+	const struct hsio_table_row *pch_hsio_table;
-+	size_t len;
-+
-+	pch_hsio_table = hsio_sata_lpt_h_cx;
-+	len = ARRAY_SIZE(hsio_sata_lpt_h_cx);
-+	for (size_t i = 0; i < len; i++)
-+		hsio_update_row(pch_hsio_table[i]);
-+
-+	pch_hsio_table = hsio_sata_shared_lpt_h_cx;
-+	len = ARRAY_SIZE(hsio_sata_shared_lpt_h_cx);
-+	for (size_t i = 0; i < len; i++)
-+		hsio_sata_shared_update_row(pch_hsio_table[i]);
-+
-+	const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67;
-+
-+	hsio_update(0xea002490, ~0x0000ffff, hsio_sata_value);
-+	hsio_update(0xea002690, ~0x0000ffff, hsio_sata_value);
-+	hsio_update(0xea000890, ~0x0000ffff, hsio_sata_value);
-+	hsio_update(0xea000a90, ~0x0000ffff, hsio_sata_value);
-+
-+	hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value);
-+	hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value);
-+}
-+
-+void program_hsio_xhci_lpt_h_cx(void)
-+{
-+	const struct hsio_table_row *pch_hsio_table;
-+	size_t len;
-+
-+	pch_hsio_table = hsio_xhci_lpt_h_cx;
-+	len = ARRAY_SIZE(hsio_xhci_lpt_h_cx);
-+
-+	for (size_t i = 0; i < len; i++)
-+		hsio_update_row(pch_hsio_table[i]);
-+
-+	pch_hsio_table = hsio_xhci_shared_lpt_h_cx;
-+	len = ARRAY_SIZE(hsio_xhci_shared_lpt_h_cx);
-+
-+	for (size_t i = 0; i < len; i++)
-+		hsio_xhci_shared_update_row(pch_hsio_table[i]);
-+}
-+
-+void program_hsio_igbe_lpt_h_cx(void)
-+{
-+	const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc);
-+	if (!(strpfusecfg1 & (1 << 19)))
-+		return;
-+
-+	const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7;
-+	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
-+	if (gbe_port == 0 && ((lane_owner >> 0) & 3) != 1)
-+		return;
-+
-+	if (gbe_port == 1 && ((lane_owner >> 2) & 3) != 1)
-+		return;
-+
-+	const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x2e - 2 * gbe_port) << 8;
-+	hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100);
-+}
-diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
-new file mode 100644
-index 0000000000..24679e791a
---- /dev/null
-+++ b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
-@@ -0,0 +1,180 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/pci_ops.h>
-+#include <southbridge/intel/lynxpoint/iobp.h>
-+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
-+#include <types.h>
-+
-+const struct hsio_table_row hsio_sata_shared_lpt_lp_bx[] = {
-+	{ 0xea008008, ~0xff000000, 0x1c000000 },
-+	{ 0xea002008, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002208, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002408, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002608, ~0xfffc6108, 0xea6c6108 },
-+	{ 0xea002038, ~0x0000000f, 0x0000000d },
-+	{ 0xea002238, ~0x0000000f, 0x0000000d },
-+	{ 0xea002438, ~0x0000000f, 0x0000000d },
-+	{ 0xea002638, ~0x0000000f, 0x0000000d },
-+	{ 0xea00202c, ~0x00020f00, 0x00020100 },
-+	{ 0xea00222c, ~0x00020f00, 0x00020100 },
-+	{ 0xea00242c, ~0x00020f00, 0x00020100 },
-+	{ 0xea00262c, ~0x00020f00, 0x00020100 },
-+	{ 0xea002040, ~0x1f000000, 0x01000000 },
-+	{ 0xea002240, ~0x1f000000, 0x01000000 },
-+	{ 0xea002440, ~0x1f000000, 0x01000000 },
-+	{ 0xea002640, ~0x1f000000, 0x01000000 },
-+	{ 0xea002010, ~0xffff0000, 0x55510000 },
-+	{ 0xea002210, ~0xffff0000, 0x55510000 },
-+	{ 0xea002410, ~0xffff0000, 0x55510000 },
-+	{ 0xea002610, ~0xffff0000, 0x55510000 },
-+	{ 0xea002140, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002340, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002540, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002740, ~0x00ffffff, 0x00140718 },
-+	{ 0xea002144, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002344, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002544, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002744, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002148, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002348, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002548, ~0x00ffffff, 0x00140998 },
-+	{ 0xea002748, ~0x00ffffff, 0x00140998 },
-+	{ 0xea00217c, ~0x03000000, 0x03000000 },
-+	{ 0xea00237c, ~0x03000000, 0x03000000 },
-+	{ 0xea00257c, ~0x03000000, 0x03000000 },
-+	{ 0xea00277c, ~0x03000000, 0x03000000 },
-+	{ 0xea00208c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00228c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00248c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea00268c, ~0x00ff0000, 0x00800000 },
-+	{ 0xea0020a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0022a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0024a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0026a4, ~0x0030ff00, 0x00308300 },
-+	{ 0xea0020ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0022ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0024ac, ~0x00000030, 0x00000020 },
-+	{ 0xea0026ac, ~0x00000030, 0x00000020 },
-+	{ 0xea002018, ~0xffff0300, 0x38250100 },
-+	{ 0xea002218, ~0xffff0300, 0x38250100 },
-+	{ 0xea002418, ~0xffff0300, 0x38250100 },
-+	{ 0xea002618, ~0xffff0300, 0x38250100 },
-+	{ 0xea002000, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002200, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002400, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002600, ~0xcf030000, 0xcf030000 },
-+	{ 0xea002028, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea002228, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea002428, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea002628, ~0xff1f0000, 0x580e0000 },
-+	{ 0xea00201c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00221c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00241c, ~0x00007c00, 0x00002400 },
-+	{ 0xea00261c, ~0x00007c00, 0x00002400 },
-+	{ 0xea002178, ~0x00001f00, 0x00001800 },
-+	{ 0xea002378, ~0x00001f00, 0x00001800 },
-+	{ 0xea002578, ~0x00001f00, 0x00001800 },
-+	{ 0xea002778, ~0x00001f00, 0x00001800 },
-+	{ 0xea00210c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00230c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00250c, ~0x0038000f, 0x00000005 },
-+	{ 0xea00270c, ~0x0038000f, 0x00000005 },
-+};
-+
-+const struct hsio_table_row hsio_xhci_shared_lpt_lp_bx[] = {
-+	{ 0xe90025cc, ~0x00001407, 0x00001407 },
-+	{ 0xe90027cc, ~0x00001407, 0x00001407 },
-+	{ 0xe9002568, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9002768, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe900242c, ~0x00000700, 0x00000100 },
-+	{ 0xe900262c, ~0x00000700, 0x00000100 },
-+	{ 0xe900256c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900276c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900254c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe900274c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe9002564, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002764, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002570, ~0x00000018, 0x00000000 },
-+	{ 0xe9002770, ~0x00000018, 0x00000000 },
-+	{ 0xe9002514, ~0x38000700, 0x00000100 },
-+	{ 0xe9002714, ~0x38000700, 0x00000100 },
-+	{ 0xe9002438, ~0x0000000f, 0x0000000b },
-+	{ 0xe9002638, ~0x0000000f, 0x0000000b },
-+	{ 0xe9002414, ~0x0000fe00, 0x00006600 },
-+	{ 0xe9002614, ~0x0000fe00, 0x00006600 },
-+	{ 0xe9002540, ~0x00800000, 0x00000000 },
-+	{ 0xe9002740, ~0x00800000, 0x00000000 },
-+};
-+
-+const struct hsio_table_row hsio_xhci_lpt_lp_bx[] = {
-+	{ 0xe90021cc, ~0x00001407, 0x00001407 },
-+	{ 0xe90023cc, ~0x00001407, 0x00001407 },
-+	{ 0xe9002168, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe9002368, ~0x01000f3c, 0x00000a28 },
-+	{ 0xe900216c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900236c, ~0x000000ff, 0x0000003f },
-+	{ 0xe900214c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe900234c, ~0x00ffff00, 0x00120500 },
-+	{ 0xe9002164, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002364, ~0x0000f000, 0x00005000 },
-+	{ 0xe9002170, ~0x00000018, 0x00000000 },
-+	{ 0xe9002370, ~0x00000018, 0x00000000 },
-+	{ 0xe9002114, ~0x38000700, 0x00000100 },
-+	{ 0xe9002314, ~0x38000700, 0x00000100 },
-+	{ 0xe9002038, ~0x0000000f, 0x0000000b },
-+	{ 0xe9002238, ~0x0000000f, 0x0000000b },
-+	{ 0xe9002014, ~0x0000fe00, 0x00006600 },
-+	{ 0xe9002214, ~0x0000fe00, 0x00006600 },
-+	{ 0xe9002140, ~0x00800000, 0x00000000 },
-+	{ 0xe9002340, ~0x00800000, 0x00000000 },
-+};
-+
-+void program_hsio_sata_lpt_lp_bx(const bool is_mobile)
-+{
-+	const struct hsio_table_row *pch_hsio_table;
-+	size_t len;
-+
-+	pch_hsio_table = hsio_sata_shared_lpt_lp_bx;
-+	len = ARRAY_SIZE(hsio_sata_shared_lpt_lp_bx);
-+	for (size_t i = 0; i < len; i++)
-+		hsio_sata_shared_update_row(pch_hsio_table[i]);
-+
-+	const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67;
-+
-+	hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value);
-+	hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value);
-+	hsio_sata_shared_update(0xea002490, ~0x0000ffff, hsio_sata_value);
-+	hsio_sata_shared_update(0xea002690, ~0x0000ffff, hsio_sata_value);
-+}
-+
-+void program_hsio_xhci_lpt_lp_bx(void)
-+{
-+	const struct hsio_table_row *pch_hsio_table;
-+	size_t len;
-+
-+	pch_hsio_table = hsio_xhci_lpt_lp_bx;
-+	len = ARRAY_SIZE(hsio_xhci_lpt_lp_bx);
-+
-+	for (size_t i = 0; i < len; i++)
-+		hsio_update_row(pch_hsio_table[i]);
-+
-+	pch_hsio_table = hsio_xhci_shared_lpt_lp_bx;
-+	len = ARRAY_SIZE(hsio_xhci_shared_lpt_lp_bx);
-+
-+	for (size_t i = 0; i < len; i++)
-+		hsio_xhci_shared_update_row(pch_hsio_table[i]);
-+}
-+
-+void program_hsio_igbe_lpt_lp_bx(void)
-+{
-+	const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc);
-+	if (!(strpfusecfg1 & (1 << 19)))
-+		return;
-+
-+	const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7;
-+	if (gbe_port > 5)
-+		return;
-+
-+	const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x08 + 2 * gbe_port) << 8;
-+	hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100);
-+}
-diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
-index 38a9349220..74b4d50017 100644
---- a/src/southbridge/intel/lynxpoint/pch.h
-+++ b/src/southbridge/intel/lynxpoint/pch.h
-@@ -117,6 +117,7 @@ void pch_dmi_setup_physical_layer(void);
- void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
- void early_usb_init(void);
- void early_thermal_init(void);
-+void early_pch_init_native(int s3resume);
- 
- void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
- void usb_ehci_disable(pci_devfn_t dev);
-@@ -271,6 +272,10 @@ void mainboard_config_rcba(void);
- #define   IDE_DECODE_ENABLE	(1 << 15)
- #define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
- 
-+#define SATA_MAP		0x90
-+#define SATA_PCS		0x92
-+#define SATA_SCLKG		0x94
-+
- #define SATA_SIRI		0xa0 /* SATA Indexed Register Index */
- #define SATA_SIRD		0xa4 /* SATA Indexed Register Data */
- #define SATA_SP			0xd0 /* Scratchpad */
-@@ -580,6 +585,7 @@ void mainboard_config_rcba(void);
- #define D19IR		0x3168	/* 16bit */
- #define ACPIIRQEN	0x31e0	/* 32bit */
- #define OIC		0x31fe	/* 16bit */
-+#define PRSTS		0x3310	/* 32bit */
- #define PMSYNC_CONFIG	0x33c4	/* 32bit */
- #define PMSYNC_CONFIG2	0x33cc	/* 32bit */
- #define SOFT_RESET_CTRL 0x38f4
--- 
-2.39.2
-

config/coreboot/haswell/patches/0008-nb-intel-haswell-Add-native-raminit-scaffolding.patch

@@ -1,407 +0,0 @@
-From 46cdec8cbce15ca11ad9a49a3ee415a78f781997 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 00:26:10 +0200
-Subject: [PATCH 08/26] nb/intel/haswell: Add native raminit scaffolding
-
-Implement some scaffolding for Haswell native raminit, like bootmode
-selection, handling of MRC cache and CPU detection.
-
-Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/raminit_main.c     | 104 ++++++++++
- .../haswell/native_raminit/raminit_native.c   | 189 +++++++++++++++++-
- .../haswell/native_raminit/raminit_native.h   |  34 ++++
- 4 files changed, 322 insertions(+), 6 deletions(-)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_main.c
- create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.h
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index 8cfb4fb33e..90af951c5a 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -1,3 +1,4 @@
- ## SPDX-License-Identifier: GPL-2.0-or-later
- 
-+romstage-y += raminit_main.c
- romstage-y += raminit_native.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-new file mode 100644
-index 0000000000..9b42c25b40
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -0,0 +1,104 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <assert.h>
-+#include <console/console.h>
-+#include <cpu/intel/haswell/haswell.h>
-+#include <delay.h>
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/haswell/chip.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/raminit.h>
-+#include <string.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+struct task_entry {
-+	enum raminit_status (*task)(struct sysinfo *);
-+	bool is_enabled;
-+	const char *name;
-+};
-+
-+static const struct task_entry cold_boot[] = {
-+};
-+
-+/* Return a generic stepping value to make stepping checks simpler */
-+static enum generic_stepping get_stepping(const uint32_t cpuid)
-+{
-+	switch (cpuid) {
-+	case CPUID_HASWELL_A0:
-+		die("Haswell stepping A0 is not supported\n");
-+	case CPUID_HASWELL_B0:
-+	case CPUID_HASWELL_ULT_B0:
-+	case CPUID_CRYSTALWELL_B0:
-+		return STEPPING_B0;
-+	case CPUID_HASWELL_C0:
-+	case CPUID_HASWELL_ULT_C0:
-+	case CPUID_CRYSTALWELL_C0:
-+		return STEPPING_C0;
-+	default:
-+		/** TODO: Add Broadwell support someday **/
-+		die("Unknown CPUID 0x%x\n", cpuid);
-+	}
-+}
-+
-+static void initialize_ctrl(struct sysinfo *ctrl)
-+{
-+	const struct northbridge_intel_haswell_config *cfg = config_of_soc();
-+	const enum raminit_boot_mode bootmode = ctrl->bootmode;
-+
-+	memset(ctrl, 0, sizeof(*ctrl));
-+
-+	ctrl->cpu = cpu_get_cpuid();
-+	ctrl->stepping = get_stepping(ctrl->cpu);
-+	ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved;
-+	ctrl->bootmode = bootmode;
-+}
-+
-+static enum raminit_status try_raminit(struct sysinfo *ctrl)
-+{
-+	const struct task_entry *const schedule = cold_boot;
-+	const size_t length = ARRAY_SIZE(cold_boot);
-+
-+	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
-+
-+	for (size_t i = 0; i < length; i++) {
-+		const struct task_entry *const entry = &schedule[i];
-+		assert(entry);
-+		assert(entry->name);
-+		if (!entry->is_enabled)
-+			continue;
-+
-+		assert(entry->task);
-+		printk(RAM_DEBUG, "\nExecuting raminit task %s\n", entry->name);
-+		status = entry->task(ctrl);
-+		printk(RAM_DEBUG, "\n");
-+		if (status) {
-+			printk(BIOS_ERR, "raminit failed on step %s\n", entry->name);
-+			break;
-+		}
-+	}
-+
-+	return status;
-+}
-+
-+void raminit_main(const enum raminit_boot_mode bootmode)
-+{
-+	/*
-+	 * The mighty_ctrl struct. Will happily nuke the pre-RAM stack
-+	 * if left unattended. Make it static and pass pointers to it.
-+	 */
-+	static struct sysinfo mighty_ctrl;
-+
-+	mighty_ctrl.bootmode = bootmode;
-+	initialize_ctrl(&mighty_ctrl);
-+
-+	/** TODO: Try more than once **/
-+	enum raminit_status status = try_raminit(&mighty_ctrl);
-+
-+	if (status != RAMINIT_STATUS_SUCCESS)
-+		die("Memory initialization was met with utmost failure and misery\n");
-+
-+	/** TODO: Implement the required magic **/
-+	die("NATIVE RAMINIT: More Magic (tm) required.\n");
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index b6efb6b40d..0869db3902 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -1,13 +1,45 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
-+#include <arch/cpu.h>
-+#include <assert.h>
-+#include <cbmem.h>
-+#include <cf9_reset.h>
- #include <console/console.h>
-+#include <cpu/x86/msr.h>
- #include <delay.h>
-+#include <device/pci_ops.h>
-+#include <mrc_cache.h>
- #include <northbridge/intel/haswell/haswell.h>
- #include <northbridge/intel/haswell/raminit.h>
- #include <southbridge/intel/lynxpoint/me.h>
- #include <southbridge/intel/lynxpoint/pch.h>
- #include <types.h>
- 
-+#include "raminit_native.h"
-+
-+static void wait_txt_clear(void)
-+{
-+	const struct cpuid_result cpuid = cpuid_ext(1, 0);
-+
-+	/* Check if TXT is supported */
-+	if (!(cpuid.ecx & BIT(6)))
-+		return;
-+
-+	/* Some TXT public bit */
-+	if (!(read32p(0xfed30010) & 1))
-+		return;
-+
-+	/* Wait for TXT clear */
-+	do {} while (!(read8p(0xfed40000) & (1 << 7)));
-+}
-+
-+static enum raminit_boot_mode get_boot_mode(void)
-+{
-+	const uint16_t pmcon_2 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2);
-+	const uint16_t bitmask = GEN_PMCON_2_DISB | GEN_PMCON_2_MEM_SR;
-+	return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD;
-+}
-+
- static bool early_init_native(int s3resume)
- {
- 	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
-@@ -24,6 +56,120 @@ static bool early_init_native(int s3resume)
- 	return cpu_replaced;
- }
- 
-+#define MRC_CACHE_VERSION 1
-+
-+struct mrc_data {
-+	const void *buffer;
-+	size_t buffer_len;
-+};
-+
-+static void save_mrc_data(struct mrc_data *md)
-+{
-+	mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len);
-+}
-+
-+static struct mrc_data prepare_mrc_cache(void)
-+{
-+	struct mrc_data md = {0};
-+	md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
-+						MRC_CACHE_VERSION,
-+						&md.buffer_len);
-+	return md;
-+}
-+
-+static const char *const bm_names[] = {
-+	"BOOTMODE_COLD",
-+	"BOOTMODE_WARM",
-+	"BOOTMODE_S3",
-+	"BOOTMODE_FAST",
-+};
-+
-+static void clear_disb(void)
-+{
-+	pci_and_config16(PCH_LPC_DEV, GEN_PMCON_2, ~GEN_PMCON_2_DISB);
-+}
-+
-+static void raminit_reset(void)
-+{
-+	clear_disb();
-+	system_reset();
-+}
-+
-+static enum raminit_boot_mode do_actual_raminit(
-+	struct mrc_data *md,
-+	const bool s3resume,
-+	const bool cpu_replaced,
-+	const enum raminit_boot_mode orig_bootmode)
-+{
-+	enum raminit_boot_mode bootmode = orig_bootmode;
-+
-+	bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/
-+
-+	if (s3resume) {
-+		if (bootmode == BOOTMODE_COLD) {
-+			printk(BIOS_EMERG, "Memory may not be in self-refresh for S3 resume\n");
-+			printk(BIOS_EMERG, "S3 resume and cold boot are mutually exclusive\n");
-+			raminit_reset();
-+		}
-+		/* Only a true mad hatter would replace a CPU in S3 */
-+		if (cpu_replaced) {
-+			printk(BIOS_EMERG, "Oh no, CPU was replaced during S3\n");
-+			/*
-+			 * No reason to continue, memory consistency is most likely lost
-+			 * and ME will probably request a reset through DID response too.
-+			 */
-+			/** TODO: Figure out why past self commented this out **/
-+			//raminit_reset();
-+		}
-+		bootmode = BOOTMODE_S3;
-+		if (!save_data_valid) {
-+			printk(BIOS_EMERG, "No training data, S3 resume is impossible\n");
-+			/* Failed S3 resume, reset to come up cleanly */
-+			raminit_reset();
-+		}
-+	}
-+	if (!s3resume && cpu_replaced) {
-+		printk(BIOS_NOTICE, "CPU was replaced, forcing a cold boot\n");
-+		/*
-+		 * Looks like the ME will get angry if raminit takes too long.
-+		 * It will report that the CPU has been replaced on next boot.
-+		 * Try to continue anyway. This should not happen in most cases.
-+		 */
-+		/** TODO: Figure out why past self commented this out **/
-+		//save_data_valid = false;
-+	}
-+	if (bootmode == BOOTMODE_COLD) {
-+		/* If possible, promote to a fast boot */
-+		if (save_data_valid)
-+			bootmode = BOOTMODE_FAST;
-+
-+		clear_disb();
-+	} else if (bootmode == BOOTMODE_WARM) {
-+		/* If a warm reset happened before raminit is done, force a cold boot */
-+		if (mchbar_read32(SSKPD) == 0 && mchbar_read32(SSKPD + 4) == 0) {
-+			printk(BIOS_NOTICE, "Warm reset occurred early in cold boot\n");
-+			save_data_valid = false;
-+		}
-+		if (!save_data_valid)
-+			bootmode = BOOTMODE_COLD;
-+	}
-+	assert(save_data_valid != (bootmode == BOOTMODE_COLD));
-+	if (save_data_valid) {
-+		printk(BIOS_INFO, "Using cached memory parameters\n");
-+		die("RAMINIT: Fast boot is not yet implemented\n");
-+	}
-+	printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]);
-+	printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]);
-+
-+	/*
-+	 * And now, the actual memory initialization thing.
-+	 */
-+	printk(RAM_DEBUG, "\nStarting native raminit\n");
-+	raminit_main(bootmode);
-+
-+	return bootmode;
-+}
-+
- void perform_raminit(const int s3resume)
- {
- 	/*
-@@ -32,17 +178,48 @@ void perform_raminit(const int s3resume)
- 	 */
- 	const bool cpu_replaced = early_init_native(s3resume);
- 
--	(void)cpu_replaced;
-+	wait_txt_clear();
-+	wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
-+
-+	const enum raminit_boot_mode orig_bootmode = get_boot_mode();
-+
-+	struct mrc_data md = prepare_mrc_cache();
-+
-+	const enum raminit_boot_mode bootmode =
-+			do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode);
-+
-+	/** TODO: report_memory_config **/
- 
--	/** TODO: Move after raminit */
- 	if (intel_early_me_uma_size() > 0) {
--		/** TODO: Update status once raminit is implemented **/
--		uint8_t me_status = ME_INIT_STATUS_ERROR;
-+		/*
-+		 * The 'other' success value is to report loss of memory
-+		 * consistency to ME if warm boot was downgraded to cold.
-+		 */
-+		uint8_t me_status;
-+		if (BOOTMODE_WARM == orig_bootmode && BOOTMODE_COLD == bootmode)
-+			me_status = ME_INIT_STATUS_SUCCESS_OTHER;
-+		else
-+			me_status = ME_INIT_STATUS_SUCCESS;
-+
-+		/** TODO: Remove this once raminit is implemented **/
-+		me_status = ME_INIT_STATUS_ERROR;
- 		intel_early_me_init_done(me_status);
- 	}
- 
-+	post_code(0x3b);
-+
- 	intel_early_me_status();
- 
--	/** TODO: Implement the required magic **/
--	die("NATIVE RAMINIT: More Magic (tm) required.\n");
-+	const bool cbmem_was_initted = !cbmem_recovery(s3resume);
-+	if (s3resume && !cbmem_was_initted) {
-+		/* Failed S3 resume, reset to come up cleanly */
-+		printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
-+		system_reset();
-+	}
-+
-+	/* Save training data on non-S3 resumes */
-+	if (!s3resume)
-+		save_mrc_data(&md);
-+
-+	/** TODO: setup_sdram_meminfo **/
- }
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-new file mode 100644
-index 0000000000..885f0184f4
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -0,0 +1,34 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#ifndef HASWELL_RAMINIT_NATIVE_H
-+#define HASWELL_RAMINIT_NATIVE_H
-+
-+enum raminit_boot_mode {
-+	BOOTMODE_COLD,
-+	BOOTMODE_WARM,
-+	BOOTMODE_S3,
-+	BOOTMODE_FAST,
-+};
-+
-+enum raminit_status {
-+	RAMINIT_STATUS_SUCCESS = 0,
-+	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
-+};
-+
-+enum generic_stepping {
-+	STEPPING_A0 = 1,
-+	STEPPING_B0 = 2,
-+	STEPPING_C0 = 3,
-+};
-+
-+struct sysinfo {
-+	enum raminit_boot_mode bootmode;
-+	enum generic_stepping stepping;
-+	uint32_t cpu;		/* CPUID value */
-+
-+	bool dq_pins_interleaved;
-+};
-+
-+void raminit_main(enum raminit_boot_mode bootmode);
-+
-+#endif
--- 
-2.39.2
-

config/coreboot/haswell/patches/0009-nb-intel-haswell-nri-Only-do-CPU-replacement-check-o.patch

@@ -1,57 +0,0 @@
-From 731216aef3129ae27ad5adc7266cb8a58090c9fc Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sun, 26 Jun 2022 10:32:12 +0200
-Subject: [PATCH 09/26] nb/intel/haswell/nri: Only do CPU replacement check on
- cold boots
-
-CPU replacement check should only be done on cold boots.
-
-Change-Id: I98efa105f4df755b23febe12dd7b356787847852
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/raminit_native.c   | 13 ++++++-------
- 1 file changed, 6 insertions(+), 7 deletions(-)
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index 0869db3902..bd9bc8e692 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -40,15 +40,14 @@ static enum raminit_boot_mode get_boot_mode(void)
- 	return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD;
- }
- 
--static bool early_init_native(int s3resume)
-+static bool early_init_native(enum raminit_boot_mode bootmode)
- {
- 	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
- 
- 	intel_early_me_init();
--	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
--	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
-+	bool cpu_replaced = bootmode == BOOTMODE_COLD && intel_early_me_cpu_replacement_check();
- 
--	early_pch_init_native(s3resume);
-+	early_pch_init_native(bootmode == BOOTMODE_S3);
- 
- 	if (!CONFIG(INTEL_LYNXPOINT_LP))
- 		dmi_early_init();
-@@ -176,13 +175,13 @@ void perform_raminit(const int s3resume)
- 	 * See, this function's name is a lie. There are more things to
- 	 * do that memory initialisation, but they are relatively easy.
- 	 */
--	const bool cpu_replaced = early_init_native(s3resume);
-+	const enum raminit_boot_mode orig_bootmode = get_boot_mode();
-+
-+	const bool cpu_replaced = early_init_native(s3resume ? BOOTMODE_S3 : orig_bootmode);
- 
- 	wait_txt_clear();
- 	wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
- 
--	const enum raminit_boot_mode orig_bootmode = get_boot_mode();
--
- 	struct mrc_data md = prepare_mrc_cache();
- 
- 	const enum raminit_boot_mode bootmode =
--- 
-2.39.2
-

config/coreboot/haswell/patches/0010-haswell-NRI-Collect-SPD-info.patch

@@ -1,344 +0,0 @@
-From 354969af4361bcc7dc240ef5871d169728f7f0cc Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 13:48:53 +0200
-Subject: [PATCH 10/26] haswell NRI: Collect SPD info
-
-Collect SPD data from DIMMs and memory-down, and find the common
-supported settings.
-
-Change-Id: I4e6a1408a638a463ecae37a447cfed1d6556e44a
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/raminit_main.c     |   1 +
- .../haswell/native_raminit/raminit_native.h   |  57 +++++
- .../haswell/native_raminit/spd_bitmunching.c  | 206 ++++++++++++++++++
- 4 files changed, 265 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index 90af951c5a..ebf7abc6ec 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -2,3 +2,4 @@
- 
- romstage-y += raminit_main.c
- romstage-y += raminit_native.c
-+romstage-y += spd_bitmunching.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 9b42c25b40..2d2cfa48bb 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -20,6 +20,7 @@ struct task_entry {
- };
- 
- static const struct task_entry cold_boot[] = {
-+	{ collect_spd_info,                                       true, "PROCSPD",    },
- };
- 
- /* Return a generic stepping value to make stepping checks simpler */
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 885f0184f4..1a0793947e 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -3,6 +3,15 @@
- #ifndef HASWELL_RAMINIT_NATIVE_H
- #define HASWELL_RAMINIT_NATIVE_H
- 
-+#include <device/dram/ddr3.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+
-+#define SPD_LEN 256
-+
-+/* 8 data lanes + 1 ECC lane */
-+#define NUM_LANES		9
-+#define NUM_LANES_NO_ECC	8
-+
- enum raminit_boot_mode {
- 	BOOTMODE_COLD,
- 	BOOTMODE_WARM,
-@@ -12,6 +21,8 @@ enum raminit_boot_mode {
- 
- enum raminit_status {
- 	RAMINIT_STATUS_SUCCESS = 0,
-+	RAMINIT_STATUS_NO_MEMORY_INSTALLED,
-+	RAMINIT_STATUS_UNSUPPORTED_MEMORY,
- 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
- };
- 
-@@ -21,14 +32,60 @@ enum generic_stepping {
- 	STEPPING_C0 = 3,
- };
- 
-+struct raminit_dimm_info {
-+	spd_raw_data raw_spd;
-+	struct dimm_attr_ddr3_st data;
-+	uint8_t spd_addr;
-+	bool valid;
-+};
-+
- struct sysinfo {
- 	enum raminit_boot_mode bootmode;
- 	enum generic_stepping stepping;
- 	uint32_t cpu;		/* CPUID value */
- 
- 	bool dq_pins_interleaved;
-+
-+	/** TODO: ECC support untested **/
-+	bool is_ecc;
-+
-+	/**
-+	 * FIXME: LPDDR support is incomplete. The largest chunks are missing,
-+	 * but some LPDDR-specific variations in algorithms have been handled.
-+	 * LPDDR-specific functions have stubs which will halt upon execution.
-+	 */
-+	bool lpddr;
-+
-+	struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS];
-+	union dimm_flags_ddr3_st flags;
-+	uint16_t cas_supported;
-+
-+	/* Except for tCK, everything is eventually stored in DCLKs */
-+	uint32_t tCK;
-+	uint32_t tAA;			/* Also known as tCL */
-+	uint32_t tWR;
-+	uint32_t tRCD;
-+	uint32_t tRRD;
-+	uint32_t tRP;
-+	uint32_t tRAS;
-+	uint32_t tRC;
-+	uint32_t tRFC;
-+	uint32_t tWTR;
-+	uint32_t tRTP;
-+	uint32_t tFAW;
-+	uint32_t tCWL;
-+	uint32_t tCMD;
-+
-+	uint8_t lanes;			/* 8 or 9 */
-+	uint8_t chanmap;
-+	uint8_t dpc[NUM_CHANNELS];	/* DIMMs per channel */
-+	uint8_t rankmap[NUM_CHANNELS];
-+	uint8_t rank_mirrored[NUM_CHANNELS];
-+	uint32_t channel_size_mb[NUM_CHANNELS];
- };
- 
- void raminit_main(enum raminit_boot_mode bootmode);
- 
-+enum raminit_status collect_spd_info(struct sysinfo *ctrl);
-+
- #endif
-diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-new file mode 100644
-index 0000000000..dbe02c72d0
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-@@ -0,0 +1,206 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <cbfs.h>
-+#include <commonlib/clamp.h>
-+#include <console/console.h>
-+#include <device/dram/ddr3.h>
-+#include <device/smbus_host.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <northbridge/intel/haswell/raminit.h>
-+#include <string.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+static const uint8_t *get_spd_data_from_cbfs(struct spd_info *spdi)
-+{
-+	if (!CONFIG(HAVE_SPD_IN_CBFS))
-+		return NULL;
-+
-+	printk(RAM_DEBUG, "SPD index %u\n", spdi->spd_index);
-+
-+	size_t spd_file_len;
-+	uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len);
-+
-+	if (!spd_file) {
-+		printk(BIOS_ERR, "SPD data not found in CBFS\n");
-+		return NULL;
-+	}
-+
-+	if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
-+		printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
-+		spdi->spd_index = 0;
-+	}
-+
-+	if (spd_file_len < SPD_LEN) {
-+		printk(BIOS_ERR, "Invalid SPD data in CBFS\n");
-+		return NULL;
-+	}
-+
-+	return spd_file + (spdi->spd_index * SPD_LEN);
-+}
-+
-+static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t *cbfs_spd)
-+{
-+	if (dimm->spd_addr == SPD_MEMORY_DOWN) {
-+		if (cbfs_spd) {
-+			memcpy(dimm->raw_spd, cbfs_spd, SPD_LEN);
-+			dimm->valid = true;
-+			printk(RAM_DEBUG, "memory-down\n");
-+			return;
-+		} else {
-+			printk(RAM_DEBUG, "memory-down but no CBFS SPD data, ignoring\n");
-+			return;
-+		}
-+	}
-+	printk(RAM_DEBUG, "slotted ");
-+	const uint8_t spd_mem_type = smbus_read_byte(dimm->spd_addr, SPD_MEMORY_TYPE);
-+	if (spd_mem_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
-+		printk(RAM_DEBUG, "and not DDR3, ignoring\n");
-+		return;
-+	}
-+	printk(RAM_DEBUG, "and DDR3\n");
-+	if (i2c_eeprom_read(dimm->spd_addr, 0, SPD_LEN, dimm->raw_spd) != SPD_LEN) {
-+		printk(BIOS_WARNING, "I2C block read failed, trying SMBus byte reads\n");
-+		for (uint32_t i = 0; i < SPD_LEN; i++)
-+			dimm->raw_spd[i] = smbus_read_byte(dimm->spd_addr, i);
-+	}
-+	dimm->valid = true;
-+}
-+
-+static void get_spd_data(struct sysinfo *ctrl)
-+{
-+	struct spd_info spdi = {0};
-+	mb_get_spd_map(&spdi);
-+	const uint8_t *cbfs_spd = get_spd_data_from_cbfs(&spdi);
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
-+			struct raminit_dimm_info *const dimm = &ctrl->dimms[channel][slot];
-+			dimm->spd_addr = spdi.addresses[channel + channel + slot];
-+			if (!dimm->spd_addr)
-+				continue;
-+
-+			printk(RAM_DEBUG, "CH%uS%u is ", channel, slot);
-+			get_spd_for_dimm(dimm, cbfs_spd);
-+		}
-+	}
-+}
-+
-+static void decode_spd(struct raminit_dimm_info *const dimm)
-+{
-+	/** TODO: Hook up somewhere, and handle lack of XMP data **/
-+	const bool enable_xmp = false;
-+	memset(&dimm->data, 0, sizeof(dimm->data));
-+	if (enable_xmp)
-+		spd_xmp_decode_ddr3(&dimm->data, dimm->raw_spd, DDR3_XMP_PROFILE_1);
-+	else
-+		spd_decode_ddr3(&dimm->data, dimm->raw_spd);
-+
-+	if (CONFIG(DEBUG_RAM_SETUP))
-+		dram_print_spd_ddr3(&dimm->data);
-+}
-+
-+static enum raminit_status find_common_spd_parameters(struct sysinfo *ctrl)
-+{
-+	ctrl->cas_supported = 0xffff;
-+	ctrl->flags.raw = 0xffffffff;
-+
-+	ctrl->tCK  = 0;
-+	ctrl->tAA  = 0;
-+	ctrl->tWR  = 0;
-+	ctrl->tRCD = 0;
-+	ctrl->tRRD = 0;
-+	ctrl->tRP  = 0;
-+	ctrl->tRAS = 0;
-+	ctrl->tRC  = 0;
-+	ctrl->tRFC = 0;
-+	ctrl->tWTR = 0;
-+	ctrl->tRTP = 0;
-+	ctrl->tFAW = 0;
-+	ctrl->tCWL = 0;
-+	ctrl->tCMD = 0;
-+	ctrl->chanmap = 0;
-+
-+	bool yes_ecc = false;
-+	bool not_ecc = false;
-+
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		ctrl->dpc[channel] = 0;
-+		ctrl->rankmap[channel] = 0;
-+		ctrl->rank_mirrored[channel] = 0;
-+		ctrl->channel_size_mb[channel] = 0;
-+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
-+			struct raminit_dimm_info *const dimm = &ctrl->dimms[channel][slot];
-+			if (!dimm->valid)
-+				continue;
-+
-+			printk(RAM_DEBUG, "\nCH%uS%u SPD:\n", channel, slot);
-+			decode_spd(dimm);
-+
-+			ctrl->chanmap |= BIT(channel);
-+			ctrl->dpc[channel]++;
-+			ctrl->channel_size_mb[channel] += dimm->data.size_mb;
-+
-+			/* The first rank of a populated slot is always present */
-+			const uint8_t rank = slot + slot;
-+			assert(dimm->data.ranks);
-+			ctrl->rankmap[channel] |= (BIT(dimm->data.ranks) - 1) << rank;
-+
-+			if (dimm->data.flags.pins_mirrored)
-+				ctrl->rank_mirrored[channel] |= BIT(rank + 1);
-+
-+			/* Find common settings */
-+			ctrl->cas_supported &= dimm->data.cas_supported;
-+			ctrl->flags.raw &= dimm->data.flags.raw;
-+			ctrl->tCK  = MAX(ctrl->tCK,  dimm->data.tCK);
-+			ctrl->tAA  = MAX(ctrl->tAA,  dimm->data.tAA);
-+			ctrl->tWR  = MAX(ctrl->tWR,  dimm->data.tWR);
-+			ctrl->tRCD = MAX(ctrl->tRCD, dimm->data.tRCD);
-+			ctrl->tRRD = MAX(ctrl->tRRD, dimm->data.tRRD);
-+			ctrl->tRP  = MAX(ctrl->tRP,  dimm->data.tRP);
-+			ctrl->tRAS = MAX(ctrl->tRAS, dimm->data.tRAS);
-+			ctrl->tRC  = MAX(ctrl->tRC,  dimm->data.tRC);
-+			ctrl->tRFC = MAX(ctrl->tRFC, dimm->data.tRFC);
-+			ctrl->tWTR = MAX(ctrl->tWTR, dimm->data.tWTR);
-+			ctrl->tRTP = MAX(ctrl->tRTP, dimm->data.tRTP);
-+			ctrl->tFAW = MAX(ctrl->tFAW, dimm->data.tFAW);
-+			ctrl->tCWL = MAX(ctrl->tCWL, dimm->data.tCWL);
-+			ctrl->tCMD = MAX(ctrl->tCMD, dimm->data.tCMD);
-+
-+			yes_ecc |=  dimm->data.flags.is_ecc;
-+			not_ecc |= !dimm->data.flags.is_ecc;
-+		}
-+	}
-+
-+	if (!ctrl->chanmap) {
-+		printk(BIOS_ERR, "No DIMMs were found\n");
-+		return RAMINIT_STATUS_NO_MEMORY_INSTALLED;
-+	}
-+	if (!ctrl->cas_supported) {
-+		printk(BIOS_ERR, "Could not resolve common CAS latency\n");
-+		return RAMINIT_STATUS_UNSUPPORTED_MEMORY;
-+	}
-+	/** TODO: Properly handle ECC support and ECC forced **/
-+	if (yes_ecc && not_ecc) {
-+		/** TODO: Test if the ECC DIMMs can be operated as non-ECC DIMMs **/
-+		printk(BIOS_ERR, "Both ECC and non-ECC DIMMs present, this is unsupported\n");
-+		return RAMINIT_STATUS_UNSUPPORTED_MEMORY;
-+	}
-+	if (yes_ecc)
-+		ctrl->lanes = NUM_LANES;
-+	else
-+		ctrl->lanes = NUM_LANES_NO_ECC;
-+
-+	ctrl->is_ecc = yes_ecc;
-+
-+	/** TODO: Complete LPDDR support **/
-+	ctrl->lpddr = false;
-+
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
-+enum raminit_status collect_spd_info(struct sysinfo *ctrl)
-+{
-+	get_spd_data(ctrl);
-+	return find_common_spd_parameters(ctrl);
-+}
--- 
-2.39.2
-

config/coreboot/haswell/patches/0011-haswell-NRI-Initialise-MPLL.patch

@@ -1,346 +0,0 @@
-From 77a89d55ab7a715dc20c34a6edacaaf781b56087 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 14:36:10 +0200
-Subject: [PATCH 11/26] haswell NRI: Initialise MPLL
-
-Add code to initialise the MPLL (Memory PLL). The procedure is similar
-to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
-
-Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   2 +
- .../intel/haswell/native_raminit/init_mpll.c  | 210 ++++++++++++++++++
- .../haswell/native_raminit/io_comp_control.c  |  22 ++
- .../haswell/native_raminit/raminit_main.c     |   1 +
- .../haswell/native_raminit/raminit_native.h   |  11 +
- .../intel/haswell/registers/mchbar.h          |   3 +
- 6 files changed, 249 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/init_mpll.c
- create mode 100644 src/northbridge/intel/haswell/native_raminit/io_comp_control.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index ebf7abc6ec..c125d84f0b 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -1,5 +1,7 @@
- ## SPDX-License-Identifier: GPL-2.0-or-later
- 
-+romstage-y += init_mpll.c
-+romstage-y += io_comp_control.c
- romstage-y += raminit_main.c
- romstage-y += raminit_native.c
- romstage-y += spd_bitmunching.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
-new file mode 100644
-index 0000000000..2faa183724
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
-@@ -0,0 +1,210 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <commonlib/clamp.h>
-+#include <console/console.h>
-+#include <delay.h>
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+static uint32_t get_mem_multiplier(const struct sysinfo *ctrl)
-+{
-+	const uint32_t mult = NS2MHZ_DIV256 / (ctrl->tCK * ctrl->base_freq);
-+
-+	if (ctrl->base_freq == 100)
-+		return clamp_u32(7, mult, 12);
-+
-+	if (ctrl->base_freq == 133)
-+		return clamp_u32(3, mult, 10);
-+
-+	die("Unsupported base frequency\n");
-+}
-+
-+static void normalize_tck(struct sysinfo *ctrl, const bool pll_ref100)
-+{
-+	/** TODO: Haswell supports up to DDR3-2600 **/
-+	if (ctrl->tCK <= TCK_1200MHZ) {
-+		ctrl->tCK = TCK_1200MHZ;
-+		ctrl->base_freq = 133;
-+		ctrl->mem_clock_mhz = 1200;
-+
-+	} else if (ctrl->tCK <= TCK_1100MHZ) {
-+		ctrl->tCK = TCK_1100MHZ;
-+		ctrl->base_freq = 100;
-+		ctrl->mem_clock_mhz = 1100;
-+
-+	} else if (ctrl->tCK <= TCK_1066MHZ) {
-+		ctrl->tCK = TCK_1066MHZ;
-+		ctrl->base_freq = 133;
-+		ctrl->mem_clock_mhz = 1066;
-+
-+	} else if (ctrl->tCK <= TCK_1000MHZ) {
-+		ctrl->tCK = TCK_1000MHZ;
-+		ctrl->base_freq = 100;
-+		ctrl->mem_clock_mhz = 1000;
-+
-+	} else if (ctrl->tCK <= TCK_933MHZ) {
-+		ctrl->tCK = TCK_933MHZ;
-+		ctrl->base_freq = 133;
-+		ctrl->mem_clock_mhz = 933;
-+
-+	} else if (ctrl->tCK <= TCK_900MHZ) {
-+		ctrl->tCK = TCK_900MHZ;
-+		ctrl->base_freq = 100;
-+		ctrl->mem_clock_mhz = 900;
-+
-+	} else if (ctrl->tCK <= TCK_800MHZ) {
-+		ctrl->tCK = TCK_800MHZ;
-+		ctrl->base_freq = 133;
-+		ctrl->mem_clock_mhz = 800;
-+
-+	} else if (ctrl->tCK <= TCK_700MHZ) {
-+		ctrl->tCK = TCK_700MHZ;
-+		ctrl->base_freq = 100;
-+		ctrl->mem_clock_mhz = 700;
-+
-+	} else if (ctrl->tCK <= TCK_666MHZ) {
-+		ctrl->tCK = TCK_666MHZ;
-+		ctrl->base_freq = 133;
-+		ctrl->mem_clock_mhz = 666;
-+
-+	} else if (ctrl->tCK <= TCK_533MHZ) {
-+		ctrl->tCK = TCK_533MHZ;
-+		ctrl->base_freq = 133;
-+		ctrl->mem_clock_mhz = 533;
-+
-+	} else if (ctrl->tCK <= TCK_400MHZ) {
-+		ctrl->tCK = TCK_400MHZ;
-+		ctrl->base_freq = 133;
-+		ctrl->mem_clock_mhz = 400;
-+
-+	} else {
-+		ctrl->tCK = 0;
-+		ctrl->base_freq = 1;
-+		ctrl->mem_clock_mhz = 0;
-+		return;
-+	}
-+	if (!pll_ref100 && ctrl->base_freq == 100) {
-+		/* Skip unsupported frequency */
-+		ctrl->tCK++;
-+		normalize_tck(ctrl, pll_ref100);
-+	}
-+}
-+
-+#define MIN_CAS	4
-+#define MAX_CAS	24
-+
-+static uint8_t find_compatible_cas(struct sysinfo *ctrl)
-+{
-+	printk(RAM_DEBUG, "With tCK %u, try CAS: ", ctrl->tCK);
-+	const uint8_t cas_lower = MAX(MIN_CAS, DIV_ROUND_UP(ctrl->tAA, ctrl->tCK));
-+	const uint8_t cas_upper = MIN(MAX_CAS, 19); /* JEDEC MR0 limit */
-+
-+	if (!(ctrl->cas_supported >> (cas_lower - MIN_CAS))) {
-+		printk(RAM_DEBUG, "DIMMs do not support CAS >= %u\n", cas_lower);
-+		ctrl->tCK++;
-+		return 0;
-+	}
-+	for (uint8_t cas = cas_lower; cas <= cas_upper; cas++) {
-+		printk(RAM_DEBUG, "%u ", cas);
-+		if (ctrl->cas_supported & BIT(cas - MIN_CAS)) {
-+			printk(RAM_DEBUG, "OK\n");
-+			return cas;
-+		}
-+	}
-+	return 0;
-+}
-+
-+static enum raminit_status find_cas_tck(struct sysinfo *ctrl)
-+{
-+	/** TODO: Honor all possible PLL_REF100_CFG values **/
-+	uint8_t pll_ref100 = (pci_read_config32(HOST_BRIDGE, CAPID0_B) >> 21) & 0x7;
-+	printk(RAM_DEBUG, "PLL_REF100_CFG value: 0x%x\n", pll_ref100);
-+	printk(RAM_DEBUG, "100MHz reference clock support: %s\n", pll_ref100 ? "yes" : "no");
-+
-+	uint8_t selected_cas;
-+	while (true) {
-+		/* Round tCK up so that it is a multiple of either 133 or 100 MHz */
-+		normalize_tck(ctrl, pll_ref100);
-+		if (!ctrl->tCK) {
-+			printk(BIOS_ERR, "Couldn't find compatible clock / CAS settings\n");
-+			return RAMINIT_STATUS_MPLL_INIT_FAILURE;
-+		}
-+		selected_cas = find_compatible_cas(ctrl);
-+		if (selected_cas)
-+			break;
-+
-+		ctrl->tCK++;
-+	}
-+	printk(BIOS_DEBUG, "Found compatible clock / CAS settings\n");
-+	printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK);
-+	printk(BIOS_DEBUG, "Selected CAS latency   : %uT\n", selected_cas);
-+	ctrl->multiplier = get_mem_multiplier(ctrl);
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
-+enum raminit_status initialise_mpll(struct sysinfo *ctrl)
-+{
-+	if (ctrl->tCK > TCK_400MHZ) {
-+		printk(BIOS_ERR, "tCK is too slow. Increasing to 400 MHz as last resort\n");
-+		ctrl->tCK = TCK_400MHZ;
-+	}
-+	while (true) {
-+		if (!ctrl->qclkps) {
-+			const enum raminit_status status = find_cas_tck(ctrl);
-+			if (status)
-+				return status;
-+		}
-+
-+		/*
-+		 * Unlike previous generations, Haswell's MPLL won't shut down if the
-+		 * requested frequency isn't supported. But we cannot reinitialize it.
-+		 * Another different thing: MPLL registers are 4-bit instead of 8-bit.
-+		 */
-+
-+		/** FIXME: Obtain current clock frequency if we want to skip this **/
-+		//if (mchbar_read32(MC_BIOS_DATA) != 0)
-+		//	break;
-+
-+		uint32_t mc_bios_req = ctrl->multiplier;
-+		if (ctrl->base_freq == 100) {
-+			/* Use 100 MHz reference clock */
-+			mc_bios_req |= BIT(4);
-+		}
-+		mc_bios_req |= BIT(31);
-+		printk(RAM_DEBUG, "MC_BIOS_REQ = 0x%08x\n", mc_bios_req);
-+		printk(BIOS_DEBUG, "MPLL busy... ");
-+		mchbar_write32(MC_BIOS_REQ, mc_bios_req);
-+
-+		for (unsigned int i = 0; i <= 5000; i++) {
-+			if (!(mchbar_read32(MC_BIOS_REQ) & BIT(31))) {
-+				printk(BIOS_DEBUG, "done in %u us\n", i);
-+				break;
-+			}
-+			udelay(1);
-+		}
-+		if (mchbar_read32(MC_BIOS_REQ) & BIT(31))
-+			printk(BIOS_DEBUG, "did not lock\n");
-+
-+		/* Verify locked frequency */
-+		const uint32_t mc_bios_data = mchbar_read32(MC_BIOS_DATA);
-+		printk(RAM_DEBUG, "MC_BIOS_DATA = 0x%08x\n", mc_bios_data);
-+		if ((mc_bios_data & 0xf) >= ctrl->multiplier)
-+			break;
-+
-+		printk(BIOS_DEBUG, "Retrying at a lower frequency\n\n");
-+		ctrl->tCK++;
-+	}
-+	if (!ctrl->mem_clock_mhz) {
-+		printk(BIOS_ERR, "Could not program MPLL frequency\n");
-+		return RAMINIT_STATUS_MPLL_INIT_FAILURE;
-+	}
-+	printk(BIOS_DEBUG, "MPLL frequency is set to: %u MHz ", ctrl->mem_clock_mhz);
-+	ctrl->mem_clock_fs = 1000000000 / ctrl->mem_clock_mhz;
-+	printk(BIOS_DEBUG, "(period: %u femtoseconds)\n", ctrl->mem_clock_fs);
-+	ctrl->qclkps = ctrl->mem_clock_fs / 2000;
-+	printk(BIOS_DEBUG, "Quadrature clock period: %u picoseconds\n", ctrl->qclkps);
-+	return wait_for_first_rcomp();
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
-new file mode 100644
-index 0000000000..7e96c08938
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
-@@ -0,0 +1,22 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <commonlib/clamp.h>
-+#include <console/console.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <timer.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+enum raminit_status wait_for_first_rcomp(void)
-+{
-+	struct stopwatch timer;
-+	stopwatch_init_msecs_expire(&timer, 2000);
-+	do {
-+		if (mchbar_read32(RCOMP_TIMER) & BIT(16))
-+			return RAMINIT_STATUS_SUCCESS;
-+
-+	} while (!stopwatch_expired(&timer));
-+	printk(BIOS_ERR, "Timed out waiting for RCOMP to complete\n");
-+	return RAMINIT_STATUS_POLL_TIMEOUT;
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 2d2cfa48bb..09545422c0 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -21,6 +21,7 @@ struct task_entry {
- 
- static const struct task_entry cold_boot[] = {
- 	{ collect_spd_info,                                       true, "PROCSPD",    },
-+	{ initialise_mpll,                                        true, "INITMPLL",   },
- };
- 
- /* Return a generic stepping value to make stepping checks simpler */
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 1a0793947e..a54581abc7 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -23,6 +23,8 @@ enum raminit_status {
- 	RAMINIT_STATUS_SUCCESS = 0,
- 	RAMINIT_STATUS_NO_MEMORY_INSTALLED,
- 	RAMINIT_STATUS_UNSUPPORTED_MEMORY,
-+	RAMINIT_STATUS_MPLL_INIT_FAILURE,
-+	RAMINIT_STATUS_POLL_TIMEOUT,
- 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
- };
- 
-@@ -82,10 +84,19 @@ struct sysinfo {
- 	uint8_t rankmap[NUM_CHANNELS];
- 	uint8_t rank_mirrored[NUM_CHANNELS];
- 	uint32_t channel_size_mb[NUM_CHANNELS];
-+
-+	uint8_t base_freq;		/* Memory base frequency, either 100 or 133 MHz */
-+	uint32_t multiplier;
-+	uint32_t mem_clock_mhz;
-+	uint32_t mem_clock_fs;		/* Memory clock period in femtoseconds */
-+	uint32_t qclkps;		/* Quadrature clock period in picoseconds */
- };
- 
- void raminit_main(enum raminit_boot_mode bootmode);
- 
- enum raminit_status collect_spd_info(struct sysinfo *ctrl);
-+enum raminit_status initialise_mpll(struct sysinfo *ctrl);
-+
-+enum raminit_status wait_for_first_rcomp(void);
- 
- #endif
-diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
-index 5610e7089a..45f8174995 100644
---- a/src/northbridge/intel/haswell/registers/mchbar.h
-+++ b/src/northbridge/intel/haswell/registers/mchbar.h
-@@ -13,6 +13,8 @@
- #define MC_INIT_STATE_G		0x5030
- #define MRC_REVISION		0x5034 /* MRC Revision */
- 
-+#define RCOMP_TIMER		0x5084
-+
- #define MC_LOCK			0x50fc /* Memory Controller Lock register */
- 
- #define GFXVTBAR		0x5400 /* Base address for IGD */
-@@ -61,6 +63,7 @@
- 
- #define BIOS_RESET_CPL		0x5da8 /* 8-bit */
- 
-+#define MC_BIOS_REQ		0x5e00 /* Memory frequency request register */
- #define MC_BIOS_DATA		0x5e04 /* Miscellaneous information for BIOS */
- #define SAPMCTL			0x5f00
- 
--- 
-2.39.2
-

config/coreboot/haswell/patches/0012-haswell-NRI-Post-process-selected-timings.patch

@@ -1,249 +0,0 @@
-From faabed9ca8974b2e7192c55b59a9d28d75e72df6 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 16:29:55 +0200
-Subject: [PATCH 12/26] haswell NRI: Post-process selected timings
-
-Once the MPLL has been initialised, convert the timings from the SPD to
-be in DCLKs, which is what the hardware expects. In addition, calculate
-the values for tREFI and tXP.
-
-Change-Id: Id02caf858f75b9e08016762b3aefda282b274386
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/lookup_timings.c   |  62 +++++++++++
- .../haswell/native_raminit/raminit_main.c     |   1 +
- .../haswell/native_raminit/raminit_native.h   |   8 ++
- .../haswell/native_raminit/spd_bitmunching.c  | 100 ++++++++++++++++++
- 5 files changed, 172 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/lookup_timings.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index c125d84f0b..2769e0bbb4 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -1,5 +1,6 @@
- ## SPDX-License-Identifier: GPL-2.0-or-later
- 
-+romstage-y += lookup_timings.c
- romstage-y += init_mpll.c
- romstage-y += io_comp_control.c
- romstage-y += raminit_main.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
-new file mode 100644
-index 0000000000..038686c844
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
-@@ -0,0 +1,62 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <commonlib/clamp.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+struct timing_lookup {
-+	uint32_t clock;
-+	uint32_t value;
-+};
-+
-+static uint32_t lookup_timing(
-+	const uint32_t mem_clock_mhz,
-+	const struct timing_lookup *const lookup,
-+	const size_t length)
-+{
-+	/* Fall back to the last index */
-+	size_t i;
-+	for (i = 0; i < length - 1; i++) {
-+		/* Account for imprecise frequency values */
-+		if ((mem_clock_mhz - 5) <= lookup[i].clock)
-+			break;
-+	}
-+	return lookup[i].value;
-+}
-+
-+static const uint32_t fmax = UINT32_MAX;
-+
-+uint8_t get_tCWL(const uint32_t mem_clock_mhz)
-+{
-+	const struct timing_lookup lut[] = {
-+		{  400,  5 },
-+		{  533,  6 },
-+		{  666,  7 },
-+		{  800,  8 },
-+		{  933,  9 },
-+		{ 1066, 10 },
-+		{ 1200, 11 },
-+		{ fmax, 12 },
-+	};
-+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
-+}
-+
-+/* tREFI = 7800 ns * DDR MHz */
-+uint32_t get_tREFI(const uint32_t mem_clock_mhz)
-+{
-+	return (mem_clock_mhz * 7800) / 1000;
-+}
-+
-+uint32_t get_tXP(const uint32_t mem_clock_mhz)
-+{
-+	const struct timing_lookup lut[] = {
-+		{  400,  3 },
-+		{  666,  4 },
-+		{  800,  5 },
-+		{  933,  6 },
-+		{ 1066,  7 },
-+		{ fmax,  8 },
-+	};
-+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 09545422c0..5f2be980d4 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -22,6 +22,7 @@ struct task_entry {
- static const struct task_entry cold_boot[] = {
- 	{ collect_spd_info,                                       true, "PROCSPD",    },
- 	{ initialise_mpll,                                        true, "INITMPLL",   },
-+	{ convert_timings,                                        true, "CONVTIM",    },
- };
- 
- /* Return a generic stepping value to make stepping checks simpler */
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index a54581abc7..01e5ed1bd6 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -78,6 +78,9 @@ struct sysinfo {
- 	uint32_t tCWL;
- 	uint32_t tCMD;
- 
-+	uint32_t tREFI;
-+	uint32_t tXP;
-+
- 	uint8_t lanes;			/* 8 or 9 */
- 	uint8_t chanmap;
- 	uint8_t dpc[NUM_CHANNELS];	/* DIMMs per channel */
-@@ -96,7 +99,12 @@ void raminit_main(enum raminit_boot_mode bootmode);
- 
- enum raminit_status collect_spd_info(struct sysinfo *ctrl);
- enum raminit_status initialise_mpll(struct sysinfo *ctrl);
-+enum raminit_status convert_timings(struct sysinfo *ctrl);
- 
- enum raminit_status wait_for_first_rcomp(void);
- 
-+uint8_t get_tCWL(uint32_t mem_clock_mhz);
-+uint32_t get_tREFI(uint32_t mem_clock_mhz);
-+uint32_t get_tXP(uint32_t mem_clock_mhz);
-+
- #endif
-diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-index dbe02c72d0..becbea0725 100644
---- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
-@@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl)
- 	get_spd_data(ctrl);
- 	return find_common_spd_parameters(ctrl);
- }
-+
-+#define MIN_CWL		5
-+#define MAX_CWL		12
-+
-+/* Except for tCK, hardware expects all timing values in DCLKs, not nanoseconds */
-+enum raminit_status convert_timings(struct sysinfo *ctrl)
-+{
-+	/*
-+	 * Obtain all required timing values, in DCLKs.
-+	 */
-+
-+	/* Convert primary timings from nanoseconds to DCLKs */
-+	ctrl->tAA  = DIV_ROUND_UP(ctrl->tAA,  ctrl->tCK);
-+	ctrl->tWR  = DIV_ROUND_UP(ctrl->tWR,  ctrl->tCK);
-+	ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
-+	ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
-+	ctrl->tRP  = DIV_ROUND_UP(ctrl->tRP,  ctrl->tCK);
-+	ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
-+	ctrl->tRC  = DIV_ROUND_UP(ctrl->tRC,  ctrl->tCK);
-+	ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
-+	ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
-+	ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
-+	ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
-+	ctrl->tCWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
-+	ctrl->tCMD = DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK);
-+
-+	/* Constrain primary timings to hardware limits */
-+	/** TODO: complain when clamping? **/
-+	ctrl->tAA  = clamp_u32(4,  ctrl->tAA,  24);
-+	ctrl->tWR  = clamp_u32(5,  ctrl->tWR,  16);
-+	ctrl->tRCD = clamp_u32(4,  ctrl->tRCD, 20);
-+	ctrl->tRRD = clamp_u32(4,  ctrl->tRRD, 65535);
-+	ctrl->tRP  = clamp_u32(4,  ctrl->tRP,  15);
-+	ctrl->tRAS = clamp_u32(10, ctrl->tRAS, 40);
-+	ctrl->tRC  = clamp_u32(1,  ctrl->tRC,  4095);
-+	ctrl->tRFC = clamp_u32(1,  ctrl->tRFC, 511);
-+	ctrl->tWTR = clamp_u32(4,  ctrl->tWTR, 10);
-+	ctrl->tRTP = clamp_u32(4,  ctrl->tRTP, 15);
-+	ctrl->tFAW = clamp_u32(10, ctrl->tFAW, 54);
-+
-+	/** TODO: Honor tREFI from XMP **/
-+	ctrl->tREFI = get_tREFI(ctrl->mem_clock_mhz);
-+	ctrl->tXP   =   get_tXP(ctrl->mem_clock_mhz);
-+
-+	/*
-+	 * Check some values, and adjust them if necessary.
-+	 */
-+
-+	/* If tWR cannot be written into DDR3 MR0, adjust it */
-+	switch (ctrl->tWR) {
-+	case  9:
-+	case 11:
-+	case 13:
-+	case 15:
-+		ctrl->tWR++;
-+	}
-+
-+	/* If tCWL is not supported or unspecified, look up a reasonable default */
-+	if (ctrl->tCWL < MIN_CWL || ctrl->tCWL > MAX_CWL)
-+		ctrl->tCWL = get_tCWL(ctrl->mem_clock_mhz);
-+
-+	/* This is needed to support ODT properly on 2DPC */
-+	if (ctrl->tAA - ctrl->tCWL > 4)
-+		ctrl->tCWL = ctrl->tAA - 4;
-+
-+	/* If tCMD is invalid, use a guesstimate default */
-+	if (!ctrl->tCMD) {
-+		ctrl->tCMD = MAX(ctrl->dpc[0], ctrl->dpc[1]);
-+		printk(RAM_DEBUG, "tCMD was zero, picking a guesstimate value\n");
-+	}
-+	ctrl->tCMD = clamp_u32(1, ctrl->tCMD, 3);
-+
-+	/*
-+	 * Print final timings.
-+	 */
-+
-+	/* tCK is special */
-+	printk(BIOS_DEBUG, "Selected tCK          : %u ns\n", ctrl->tCK / 256);
-+
-+	/* Primary timings */
-+	printk(BIOS_DEBUG, "Selected tAA          : %uT\n", ctrl->tAA);
-+	printk(BIOS_DEBUG, "Selected tWR          : %uT\n", ctrl->tWR);
-+	printk(BIOS_DEBUG, "Selected tRCD         : %uT\n", ctrl->tRCD);
-+	printk(BIOS_DEBUG, "Selected tRRD         : %uT\n", ctrl->tRRD);
-+	printk(BIOS_DEBUG, "Selected tRP          : %uT\n", ctrl->tRP);
-+	printk(BIOS_DEBUG, "Selected tRAS         : %uT\n", ctrl->tRAS);
-+	printk(BIOS_DEBUG, "Selected tRC          : %uT\n", ctrl->tRC);
-+	printk(BIOS_DEBUG, "Selected tRFC         : %uT\n", ctrl->tRFC);
-+	printk(BIOS_DEBUG, "Selected tWTR         : %uT\n", ctrl->tWTR);
-+	printk(BIOS_DEBUG, "Selected tRTP         : %uT\n", ctrl->tRTP);
-+	printk(BIOS_DEBUG, "Selected tFAW         : %uT\n", ctrl->tFAW);
-+	printk(BIOS_DEBUG, "Selected tCWL         : %uT\n", ctrl->tCWL);
-+	printk(BIOS_DEBUG, "Selected tCMD         : %uT\n", ctrl->tCMD);
-+
-+	/* Derived timings */
-+	printk(BIOS_DEBUG, "Selected tREFI        : %uT\n", ctrl->tREFI);
-+	printk(BIOS_DEBUG, "Selected tXP          : %uT\n", ctrl->tXP);
-+
-+	return RAMINIT_STATUS_SUCCESS;
-+}
--- 
-2.39.2
-

config/coreboot/haswell/patches/0014-haswell-NRI-Add-timings-refresh-programming.patch

@@ -1,541 +0,0 @@
-From b64d728bfe7c8ee44af252338257e95d87864659 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 20:59:58 +0200
-Subject: [PATCH 14/26] haswell NRI: Add timings/refresh programming
-
-Program the registers with timing and refresh parameters.
-
-Change-Id: Id2ea339d2c9ea8b56c71d6e88ec76949653ff5c2
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../haswell/native_raminit/lookup_timings.c   | 102 ++++++++
- .../haswell/native_raminit/raminit_native.h   |  14 ++
- .../haswell/native_raminit/reg_structs.h      |  93 +++++++
- .../haswell/native_raminit/timings_refresh.c  | 233 +++++++++++++++++-
- .../intel/haswell/registers/mchbar.h          |  12 +
- 5 files changed, 452 insertions(+), 2 deletions(-)
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
-index 038686c844..afe2c615d2 100644
---- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
-+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
-@@ -60,3 +60,105 @@ uint32_t get_tXP(const uint32_t mem_clock_mhz)
- 	};
- 	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
- }
-+
-+static uint32_t get_lpddr_tCKE(const uint32_t mem_clock_mhz)
-+{
-+	const struct timing_lookup lut[] = {
-+		{  533,  4 },
-+		{  666,  5 },
-+		{ fmax,  6 },
-+	};
-+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
-+}
-+
-+static uint32_t get_ddr_tCKE(const uint32_t mem_clock_mhz)
-+{
-+	const struct timing_lookup lut[] = {
-+		{  533,  3 },
-+		{  800,  4 },
-+		{  933,  5 },
-+		{ 1200,  6 },
-+		{ fmax,  7 },
-+	};
-+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
-+}
-+
-+uint32_t get_tCKE(const uint32_t mem_clock_mhz, const bool lpddr)
-+{
-+	return lpddr ? get_lpddr_tCKE(mem_clock_mhz) : get_ddr_tCKE(mem_clock_mhz);
-+}
-+
-+uint32_t get_tXPDLL(const uint32_t mem_clock_mhz)
-+{
-+	const struct timing_lookup lut[] = {
-+		{  400, 10 },
-+		{  533, 13 },
-+		{  666, 16 },
-+		{  800, 20 },
-+		{  933, 23 },
-+		{ 1066, 26 },
-+		{ 1200, 29 },
-+		{ fmax, 32 },
-+	};
-+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
-+}
-+
-+uint32_t get_tAONPD(const uint32_t mem_clock_mhz)
-+{
-+	const struct timing_lookup lut[] = {
-+		{  400,  4 },
-+		{  533,  5 },
-+		{  666,  6 },
-+		{  800,  7 }, /* SNB had 8 */
-+		{  933,  8 },
-+		{ 1066, 10 },
-+		{ 1200, 11 },
-+		{ fmax, 12 },
-+	};
-+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
-+}
-+
-+uint32_t get_tMOD(const uint32_t mem_clock_mhz)
-+{
-+	const struct timing_lookup lut[] = {
-+		{  800, 12 },
-+		{  933, 14 },
-+		{ 1066, 16 },
-+		{ 1200, 18 },
-+		{ fmax, 20 },
-+	};
-+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
-+}
-+
-+uint32_t get_tXS_offset(const uint32_t mem_clock_mhz)
-+{
-+	return DIV_ROUND_UP(mem_clock_mhz, 100);
-+}
-+
-+static uint32_t get_lpddr_tZQOPER(const uint32_t mem_clock_mhz)
-+{
-+	return (mem_clock_mhz * 360) / 1000;
-+}
-+
-+static uint32_t get_ddr_tZQOPER(const uint32_t mem_clock_mhz)
-+{
-+	const struct timing_lookup lut[] = {
-+		{  800, 256 },
-+		{  933, 299 },
-+		{ 1066, 342 },
-+		{ 1200, 384 },
-+		{ fmax, 427 },
-+	};
-+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
-+}
-+
-+/* tZQOPER defines the period required for ZQCL after SR exit */
-+uint32_t get_tZQOPER(const uint32_t mem_clock_mhz, const bool lpddr)
-+{
-+	return lpddr ? get_lpddr_tZQOPER(mem_clock_mhz) : get_ddr_tZQOPER(mem_clock_mhz);
-+}
-+
-+uint32_t get_tZQCS(const uint32_t mem_clock_mhz, const bool lpddr)
-+{
-+	return DIV_ROUND_UP(get_tZQOPER(mem_clock_mhz, lpddr), 4);
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index aa86b9aa39..cd1f2eb2a5 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -155,6 +155,12 @@ struct sysinfo {
- 	uint8_t cke_cmd_pi_code[NUM_CHANNELS][NUM_GROUPS];
- 	uint8_t cmd_north_pi_code[NUM_CHANNELS][NUM_GROUPS];
- 	uint8_t cmd_south_pi_code[NUM_CHANNELS][NUM_GROUPS];
-+
-+	union tc_bank_reg tc_bank[NUM_CHANNELS];
-+	union tc_bank_rank_a_reg tc_bankrank_a[NUM_CHANNELS];
-+	union tc_bank_rank_b_reg tc_bankrank_b[NUM_CHANNELS];
-+	union tc_bank_rank_c_reg tc_bankrank_c[NUM_CHANNELS];
-+	union tc_bank_rank_d_reg tc_bankrank_d[NUM_CHANNELS];
- };
- 
- static inline bool is_hsw_ult(void)
-@@ -200,6 +206,14 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
- void configure_timings(struct sysinfo *ctrl);
- void configure_refresh(struct sysinfo *ctrl);
- 
-+uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
-+uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
-+uint32_t get_tAONPD(uint32_t mem_clock_mhz);
-+uint32_t get_tMOD(uint32_t mem_clock_mhz);
-+uint32_t get_tXS_offset(uint32_t mem_clock_mhz);
-+uint32_t get_tZQOPER(uint32_t mem_clock_mhz, bool lpddr);
-+uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr);
-+
- enum raminit_status wait_for_first_rcomp(void);
- 
- uint8_t get_rx_bias(const struct sysinfo *ctrl);
-diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-index d11cda4b3d..70487e1640 100644
---- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-@@ -335,6 +335,99 @@ union mcscheds_cbit_reg {
- 	uint32_t raw;
- };
- 
-+union tc_bank_reg {
-+	struct __packed {
-+		uint32_t tRCD      : 5; // Bits  4:0
-+		uint32_t tRP       : 5; // Bits  9:5
-+		uint32_t tRAS      : 6; // Bits 15:10
-+		uint32_t tRDPRE    : 4; // Bits 19:16
-+		uint32_t tWRPRE    : 6; // Bits 25:20
-+		uint32_t tRRD      : 4; // Bits 29:26
-+		uint32_t tRPab_ext : 2; // Bits 31:30
-+	};
-+	uint32_t raw;
-+};
-+
-+union tc_bank_rank_a_reg {
-+	struct __packed {
-+		uint32_t tCKE        : 4; // Bits  3:0
-+		uint32_t tFAW        : 8; // Bits 11:4
-+		uint32_t tRDRD_sr    : 3; // Bits 14:12
-+		uint32_t tRDRD_dr    : 4; // Bits 18:15
-+		uint32_t tRDRD_dd    : 4; // Bits 22:19
-+		uint32_t tRDPDEN     : 5; // Bits 27:23
-+		uint32_t             : 1; // Bits 28:28
-+		uint32_t cmd_3st_dis : 1; // Bits 29:29
-+		uint32_t cmd_stretch : 2; // Bits 31:30
-+	};
-+	uint32_t raw;
-+};
-+
-+union tc_bank_rank_b_reg {
-+	struct __packed {
-+		uint32_t tWRRD_sr : 6; // Bits  5:0
-+		uint32_t tWRRD_dr : 4; // Bits  9:6
-+		uint32_t tWRRD_dd : 4; // Bits 13:10
-+		uint32_t tWRWR_sr : 3; // Bits 16:14
-+		uint32_t tWRWR_dr : 4; // Bits 20:17
-+		uint32_t tWRWR_dd : 4; // Bits 24:21
-+		uint32_t tWRPDEN  : 6; // Bits 30:25
-+		uint32_t dec_wrd  : 1; // Bits 31:31
-+	};
-+	uint32_t raw;
-+};
-+
-+union tc_bank_rank_c_reg {
-+	struct __packed {
-+		uint32_t tXPDLL   : 6; // Bits  5:0
-+		uint32_t tXP      : 4; // Bits  9:6
-+		uint32_t tAONPD   : 4; // Bits 13:10
-+		uint32_t tRDWR_sr : 5; // Bits 18:14
-+		uint32_t tRDWR_dr : 5; // Bits 23:19
-+		uint32_t tRDWR_dd : 5; // Bits 28:24
-+		uint32_t          : 3; // Bits 31:29
-+	};
-+	uint32_t raw;
-+};
-+
-+/* NOTE: Non-ULT only implements the lower 21 bits (odt_write_delay is 2 bits) */
-+union tc_bank_rank_d_reg {
-+	struct __packed {
-+		uint32_t tAA                : 5; // Bits  4:0
-+		uint32_t tCWL               : 5; // Bits  9:5
-+		uint32_t tCPDED             : 2; // Bits 11:10
-+		uint32_t tPRPDEN            : 2; // Bits 13:12
-+		uint32_t odt_read_delay     : 3; // Bits 16:14
-+		uint32_t odt_read_duration  : 2; // Bits 18:17
-+		uint32_t odt_write_duration : 3; // Bits 21:19
-+		uint32_t odt_write_delay    : 3; // Bits 24:22
-+		uint32_t odt_always_rank_0  : 1; // Bits 25:25
-+		uint32_t cmd_delay          : 2; // Bits 27:26
-+		uint32_t                    : 4; // Bits 31:28
-+	};
-+	uint32_t raw;
-+};
-+
-+union tc_rftp_reg {
-+	struct __packed {
-+		uint32_t tREFI   : 16; // Bits 15:0
-+		uint32_t tRFC    :  9; // Bits 24:16
-+		uint32_t tREFIx9 :  7; // Bits 31:25
-+	};
-+	uint32_t raw;
-+};
-+
-+union tc_srftp_reg {
-+	struct __packed {
-+		uint32_t tXSDLL     : 12; // Bits 11:0
-+		uint32_t tXS_offset :  4; // Bits 15:12
-+		uint32_t tZQOPER    : 10; // Bits 25:16
-+		uint32_t            :  2; // Bits 27:26
-+		uint32_t tMOD       :  4; // Bits 31:28
-+	};
-+	uint32_t raw;
-+};
-+
- union mcmain_command_rate_limit_reg {
- 	struct __packed {
- 		uint32_t enable_cmd_limit :  1; // Bits  0:0
-diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
-index a9d960f31b..20a05b359b 100644
---- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
-+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
-@@ -1,13 +1,242 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
-+#include <assert.h>
-+#include <commonlib/clamp.h>
-+#include <console/console.h>
-+#include <delay.h>
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+
- #include "raminit_native.h"
- 
-+#define BL		8	/* Burst length */
-+#define tCCD		4
-+#define tRPRE		1
-+#define tWPRE		1
-+#define tDLLK		512
-+
-+static bool is_sodimm(const enum spd_dimm_type_ddr3 type)
-+{
-+	return type == SPD_DDR3_DIMM_TYPE_SO_DIMM || type == SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM;
-+}
-+
-+static uint8_t get_odt_stretch(const struct sysinfo *const ctrl)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		/* Only stretch with 2 DIMMs per channel */
-+		if (ctrl->dpc[channel] != 2)
-+			continue;
-+
-+		const struct raminit_dimm_info *dimms = ctrl->dimms[channel];
-+
-+		/* Only stretch when using SO-DIMMs */
-+		if (!is_sodimm(dimms[0].data.dimm_type) || !is_sodimm(dimms[1].data.dimm_type))
-+			continue;
-+
-+		/* Only stretch with mismatched card types */
-+		if (dimms[0].data.reference_card == dimms[1].data.reference_card)
-+			continue;
-+
-+		/* Stretch if one SO-DIMM is card F */
-+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
-+			if (dimms[slot].data.reference_card == 5)
-+				return 1;
-+		}
-+	}
-+	return 0;
-+}
-+
-+static union tc_bank_reg make_tc_bank(struct sysinfo *const ctrl)
-+{
-+	return (union tc_bank_reg) {
-+		.tRCD      = ctrl->tRCD,
-+		.tRP       = ctrl->tRP,
-+		.tRAS      = ctrl->tRAS,
-+		.tRDPRE    = ctrl->tRTP,
-+		.tWRPRE    = 4 + ctrl->tCWL + ctrl->tWR,
-+		.tRRD      = ctrl->tRRD,
-+		.tRPab_ext = 0,	/** TODO: For LPDDR, this is ctrl->tRPab - ctrl->tRP **/
-+	};
-+}
-+
-+static union tc_bank_rank_a_reg make_tc_bankrank_a(struct sysinfo *ctrl, uint8_t odt_stretch)
-+{
-+	/* Use 3N mode for DDR during training, but always use 1N mode for LPDDR */
-+	const uint32_t tCMD = ctrl->lpddr ? 0 : 3;
-+	const uint32_t tRDRD_drdd = BL / 2 + 1 + tRPRE + odt_stretch + !!ctrl->lpddr;
-+
-+	return (union tc_bank_rank_a_reg) {
-+		.tCKE        = get_tCKE(ctrl->mem_clock_mhz, ctrl->lpddr),
-+		.tFAW        = ctrl->tFAW,
-+		.tRDRD_sr    = tCCD,
-+		.tRDRD_dr    = tRDRD_drdd,
-+		.tRDRD_dd    = tRDRD_drdd,
-+		.tRDPDEN     = ctrl->tAA + BL / 2 + 1,
-+		.cmd_3st_dis = 1,	/* Disable command tri-state before training */
-+		.cmd_stretch = tCMD,
-+	};
-+}
-+
-+static union tc_bank_rank_b_reg make_tc_bankrank_b(struct sysinfo *const ctrl)
-+{
-+	const uint8_t tWRRD_drdd = ctrl->tCWL - ctrl->tAA + BL / 2 + 2 + tRPRE;
-+	const uint8_t tWRWR_drdd = BL / 2 + 2 + tWPRE;
-+
-+	return (union tc_bank_rank_b_reg) {
-+		.tWRRD_sr = tCCD + ctrl->tCWL + ctrl->tWTR + 2,
-+		.tWRRD_dr = ctrl->lpddr ? 8 : tWRRD_drdd,
-+		.tWRRD_dd = ctrl->lpddr ? 8 : tWRRD_drdd,
-+		.tWRWR_sr = tCCD,
-+		.tWRWR_dr = tWRWR_drdd,
-+		.tWRWR_dd = tWRWR_drdd,
-+		.tWRPDEN  = ctrl->tWR + ctrl->tCWL + BL / 2,
-+		.dec_wrd  = ctrl->tCWL >= 6,
-+	};
-+}
-+
-+static uint32_t get_tRDWR_sr(const struct sysinfo *ctrl)
-+{
-+	if (ctrl->lpddr) {
-+		const uint32_t tdqsck_max = DIV_ROUND_UP(5500, ctrl->qclkps * 2);
-+		return ctrl->tAA - ctrl->tCWL + tCCD + tWPRE + tdqsck_max + 1;
-+	} else {
-+		const bool fast_clock = ctrl->mem_clock_mhz > 666;
-+		return ctrl->tAA - ctrl->tCWL + tCCD + tWPRE + 2 + fast_clock;
-+	}
-+}
-+
-+static union tc_bank_rank_c_reg make_tc_bankrank_c(struct sysinfo *ctrl, uint8_t odt_stretch)
-+{
-+	const uint32_t tRDWR_sr = get_tRDWR_sr(ctrl);
-+	const uint32_t tRDWR_drdd = tRDWR_sr + odt_stretch;
-+
-+	return (union tc_bank_rank_c_reg) {
-+		.tXPDLL   = get_tXPDLL(ctrl->mem_clock_mhz),
-+		.tXP      = MAX(ctrl->tXP, 7),	/* Use a higher tXP for training */
-+		.tAONPD   = get_tAONPD(ctrl->mem_clock_mhz),
-+		.tRDWR_sr = tRDWR_sr,
-+		.tRDWR_dr = tRDWR_drdd,
-+		.tRDWR_dd = tRDWR_drdd,
-+	};
-+}
-+
-+static union tc_bank_rank_d_reg make_tc_bankrank_d(struct sysinfo *ctrl, uint8_t odt_stretch)
-+{
-+	const uint32_t odt_rd_delay = ctrl->tAA - ctrl->tCWL;
-+	if (!ctrl->lpddr) {
-+		return (union tc_bank_rank_d_reg) {
-+			.tAA               = ctrl->tAA,
-+			.tCWL              = ctrl->tCWL,
-+			.tCPDED            = 1,
-+			.tPRPDEN           = 1,
-+			.odt_read_delay    = odt_rd_delay,
-+			.odt_read_duration = odt_stretch,
-+		};
-+	}
-+
-+	/* tCWL has 1 extra clock because of tDQSS, subtract it here */
-+	const uint32_t tCWL_lpddr = ctrl->tCWL - 1;
-+	const uint32_t odt_wr_delay = tCWL_lpddr + DIV_ROUND_UP(3500, ctrl->qclkps * 2);
-+	const uint32_t odt_wr_duration = DIV_ROUND_UP(3500 - 1750, ctrl->qclkps * 2) + 1;
-+
-+	return (union tc_bank_rank_d_reg) {
-+		.tAA                = ctrl->tAA,
-+		.tCWL               = tCWL_lpddr,
-+		.tCPDED             = 2,	/* Required by JEDEC LPDDR3 spec */
-+		.tPRPDEN            = 1,
-+		.odt_read_delay     = odt_rd_delay,
-+		.odt_read_duration  = odt_stretch,
-+		.odt_write_delay    = odt_wr_delay,
-+		.odt_write_duration = odt_wr_duration,
-+		.odt_always_rank_0  = ctrl->lpddr_dram_odt
-+	};
-+}
-+
-+/* ZQCS period values, in (tREFI * 128) units */
-+#define ZQCS_PERIOD_DDR3	128	/* tREFI * 128 = 7.8 us * 128 = 1ms */
-+#define ZQCS_PERIOD_LPDDR3	256	/* tREFI * 128 = 3.9 us * 128 = 0.5ms */
-+
-+static uint32_t make_tc_zqcal(const struct sysinfo *const ctrl)
-+{
-+	const uint32_t zqcs_period = ctrl->lpddr ? ZQCS_PERIOD_LPDDR3 : ZQCS_PERIOD_DDR3;
-+	const uint32_t tZQCS = get_tZQCS(ctrl->mem_clock_mhz, ctrl->lpddr);
-+	return tZQCS << (is_hsw_ult() ? 10 : 8) | zqcs_period;
-+}
-+
-+static union tc_rftp_reg make_tc_rftp(const struct sysinfo *const ctrl)
-+{
-+	/*
-+	 * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow
-+	 * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024.
-+	 */
-+	return (union tc_rftp_reg) {
-+		.tREFI   = ctrl->tREFI,
-+		.tRFC    = ctrl->tRFC,
-+		.tREFIx9 = ctrl->tREFI * 89 / 10240,
-+	};
-+}
-+
-+static union tc_srftp_reg make_tc_srftp(const struct sysinfo *const ctrl)
-+{
-+	return (union tc_srftp_reg) {
-+		.tXSDLL     = tDLLK,
-+		.tXS_offset = get_tXS_offset(ctrl->mem_clock_mhz),
-+		.tZQOPER    = get_tZQOPER(ctrl->mem_clock_mhz, ctrl->lpddr),
-+		.tMOD       = get_tMOD(ctrl->mem_clock_mhz) - 8,
-+	};
-+}
-+
- void configure_timings(struct sysinfo *ctrl)
- {
--	/** TODO: Stub **/
-+	if (ctrl->lpddr)
-+		die("%s: Missing support for LPDDR\n");
-+
-+	const uint8_t odt_stretch = get_odt_stretch(ctrl);
-+	const union tc_bank_reg tc_bank = make_tc_bank(ctrl);
-+	const union tc_bank_rank_a_reg tc_bank_rank_a = make_tc_bankrank_a(ctrl, odt_stretch);
-+	const union tc_bank_rank_b_reg tc_bank_rank_b = make_tc_bankrank_b(ctrl);
-+	const union tc_bank_rank_c_reg tc_bank_rank_c = make_tc_bankrank_c(ctrl, odt_stretch);
-+	const union tc_bank_rank_d_reg tc_bank_rank_d = make_tc_bankrank_d(ctrl, odt_stretch);
-+
-+	const uint8_t wr_delay = tc_bank_rank_b.dec_wrd + 1;
-+	uint8_t sc_wr_add_delay = 0;
-+	sc_wr_add_delay |= wr_delay << 0;
-+	sc_wr_add_delay |= wr_delay << 2;
-+	sc_wr_add_delay |= wr_delay << 4;
-+	sc_wr_add_delay |= wr_delay << 6;
-+
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		ctrl->tc_bank[channel] = tc_bank;
-+		ctrl->tc_bankrank_a[channel] = tc_bank_rank_a;
-+		ctrl->tc_bankrank_b[channel] = tc_bank_rank_b;
-+		ctrl->tc_bankrank_c[channel] = tc_bank_rank_c;
-+		ctrl->tc_bankrank_d[channel] = tc_bank_rank_d;
-+
-+		mchbar_write32(TC_BANK_ch(channel), ctrl->tc_bank[channel].raw);
-+		mchbar_write32(TC_BANK_RANK_A_ch(channel), ctrl->tc_bankrank_a[channel].raw);
-+		mchbar_write32(TC_BANK_RANK_B_ch(channel), ctrl->tc_bankrank_b[channel].raw);
-+		mchbar_write32(TC_BANK_RANK_C_ch(channel), ctrl->tc_bankrank_c[channel].raw);
-+		mchbar_write32(TC_BANK_RANK_D_ch(channel), ctrl->tc_bankrank_d[channel].raw);
-+		mchbar_write8(SC_WR_ADD_DELAY_ch(channel), sc_wr_add_delay);
-+	}
- }
- 
- void configure_refresh(struct sysinfo *ctrl)
- {
--	/** TODO: Stub **/
-+	const union tc_srftp_reg tc_srftp = make_tc_srftp(ctrl);
-+	const union tc_rftp_reg  tc_rftp  = make_tc_rftp(ctrl);
-+	const uint32_t tc_zqcal = make_tc_zqcal(ctrl);
-+
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		mchbar_setbits32(TC_RFP_ch(channel), 0xff);
-+		mchbar_write32(TC_RFTP_ch(channel),  tc_rftp.raw);
-+		mchbar_write32(TC_SRFTP_ch(channel), tc_srftp.raw);
-+		mchbar_write32(TC_ZQCAL_ch(channel), tc_zqcal);
-+	}
- }
-diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
-index 4c3f399b5d..2acc5cbbc8 100644
---- a/src/northbridge/intel/haswell/registers/mchbar.h
-+++ b/src/northbridge/intel/haswell/registers/mchbar.h
-@@ -86,9 +86,21 @@
- #define DDR_COMP_VSSHI_CONTROL			0x3a24
- 
- /* MCMAIN per-channel */
-+#define TC_BANK_ch(ch)				_MCMAIN_C(0x4000, ch)
-+#define TC_BANK_RANK_A_ch(ch)			_MCMAIN_C(0x4004, ch)
-+#define TC_BANK_RANK_B_ch(ch)			_MCMAIN_C(0x4008, ch)
-+#define TC_BANK_RANK_C_ch(ch)			_MCMAIN_C(0x400c, ch)
- #define COMMAND_RATE_LIMIT_ch(ch)		_MCMAIN_C(0x4010, ch)
-+#define TC_BANK_RANK_D_ch(ch)			_MCMAIN_C(0x4014, ch)
-+#define SC_ROUNDT_LAT_ch(ch)			_MCMAIN_C(0x4024, ch)
- 
-+#define SC_WR_ADD_DELAY_ch(ch)			_MCMAIN_C(0x40d0, ch)
-+
-+#define TC_ZQCAL_ch(ch)				_MCMAIN_C(0x4290, ch)
-+#define TC_RFP_ch(ch)				_MCMAIN_C(0x4294, ch)
-+#define TC_RFTP_ch(ch)				_MCMAIN_C(0x4298, ch)
- #define MC_INIT_STATE_ch(ch)			_MCMAIN_C(0x42a0, ch)
-+#define TC_SRFTP_ch(ch)				_MCMAIN_C(0x42a4, ch)
- 
- /* MCMAIN broadcast */
- #define MCSCHEDS_CBIT		0x4c20
--- 
-2.39.2
-

config/coreboot/haswell/patches/0015-haswell-NRI-Program-memory-map.patch

@@ -1,263 +0,0 @@
-From 89ff35083af68d1b24c1633886202ecc153af67d Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 21:24:50 +0200
-Subject: [PATCH 15/26] haswell NRI: Program memory map
-
-This is very similar to Sandy/Ivy Bridge, except that there's several
-registers to program in GDXCBAR. One of these GDXCBAR registers has a
-lock bit that must be set in order for the memory controller to allow
-normal access to DRAM. And it took me four months to realize this one
-bit was the only reason why native raminit did not work.
-
-Change-Id: I3af73a018a7ba948701a542e661e7fefd57591fe
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../intel/haswell/native_raminit/memory_map.c | 183 ++++++++++++++++++
- .../haswell/native_raminit/raminit_main.c     |   1 +
- .../haswell/native_raminit/raminit_native.h   |   1 +
- .../intel/haswell/registers/host_bridge.h     |   2 +
- 5 files changed, 188 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/memory_map.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index fc55277a65..37d527e972 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -4,6 +4,7 @@ romstage-y += configure_mc.c
- romstage-y += lookup_timings.c
- romstage-y += init_mpll.c
- romstage-y += io_comp_control.c
-+romstage-y += memory_map.c
- romstage-y += raminit_main.c
- romstage-y += raminit_native.c
- romstage-y += spd_bitmunching.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/memory_map.c b/src/northbridge/intel/haswell/native_raminit/memory_map.c
-new file mode 100644
-index 0000000000..e3aded2b37
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/memory_map.c
-@@ -0,0 +1,183 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <southbridge/intel/lynxpoint/me.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+/* GDXCBAR */
-+#define MPCOHTRK_GDXC_MOT_ADDRESS_LO		0x10
-+#define MPCOHTRK_GDXC_MOT_ADDRESS_HI		0x14
-+#define MPCOHTRK_GDXC_MOT_REGION		0x18
-+
-+#define MPCOHTRK_GDXC_OCLA_ADDRESS_LO		0x20
-+#define MPCOHTRK_GDXC_OCLA_ADDRESS_HI		0x24
-+#define MPCOHTRK_GDXC_OCLA_REGION		0x28
-+
-+/* This lock bit made me lose what little sanity I had left. - Angel Pons */
-+#define MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK	BIT(2)
-+
-+static inline uint32_t gdxcbar_read32(const uintptr_t offset)
-+{
-+	return read32p((mchbar_read32(GDXCBAR) & ~1) + offset);
-+}
-+
-+static inline void gdxcbar_write32(const uintptr_t offset, const uint32_t value)
-+{
-+	write32p((mchbar_read32(GDXCBAR) & ~1) + offset, value);
-+}
-+
-+static inline void gdxcbar_clrsetbits32(const uintptr_t offset, uint32_t clear, uint32_t set)
-+{
-+	const uintptr_t address = (mchbar_read32(GDXCBAR) & ~1) + offset;
-+	clrsetbits32((void *)address, clear, set);
-+}
-+
-+#define gdxcbar_setbits32(offset, set)		gdxcbar_clrsetbits32(offset, 0, set)
-+#define gdxcbar_clrbits32(offset, clear)	gdxcbar_clrsetbits32(offset, clear, 0)
-+
-+/* All values stored in here (except the bool) are specified in MiB */
-+struct memory_map_data {
-+	uint32_t dpr_size;
-+	uint32_t tseg_size;
-+	uint32_t gtt_size;
-+	uint32_t gms_size;
-+	uint32_t me_stolen_size;
-+	uint32_t mmio_size;
-+	uint32_t touud;
-+	uint32_t remaplimit;
-+	uint32_t remapbase;
-+	uint32_t tom;
-+	uint32_t tom_minus_me;
-+	uint32_t tolud;
-+	uint32_t bdsm_base;
-+	uint32_t gtt_base;
-+	uint32_t tseg_base;
-+	bool reclaim_possible;
-+};
-+
-+static void compute_memory_map(struct memory_map_data *map)
-+{
-+	map->tom_minus_me = map->tom - map->me_stolen_size;
-+
-+	/*
-+	 * MMIO size will actually be slightly smaller than computed,
-+	 * but matches what MRC does and is more MTRR-friendly given
-+	 * that TSEG is treated as WB, but SMRR makes TSEG UC anyway.
-+	 */
-+	const uint32_t mmio_size = MIN(map->tom_minus_me, 4096) / 2;
-+	map->gtt_base = ALIGN_DOWN(mmio_size, map->tseg_size);
-+	map->tseg_base = map->gtt_base - map->tseg_size;
-+	map->bdsm_base = map->gtt_base + map->gtt_size;
-+	map->tolud = map->bdsm_base + map->gms_size;
-+	map->reclaim_possible = map->tom_minus_me > map->tolud;
-+
-+	if (map->reclaim_possible) {
-+		map->remapbase  = MAX(4096, map->tom_minus_me);
-+		map->touud      = MIN(4096, map->tom_minus_me) + map->remapbase - map->tolud;
-+		map->remaplimit = map->touud - 1;
-+	} else {
-+		map->remapbase  = 0;
-+		map->remaplimit = 0;
-+		map->touud = map->tom_minus_me;
-+	}
-+}
-+
-+static void display_memory_map(const struct memory_map_data *map)
-+{
-+	if (!CONFIG(DEBUG_RAM_SETUP))
-+		return;
-+
-+	printk(BIOS_DEBUG, "============ MEMORY MAP ============\n");
-+	printk(BIOS_DEBUG, "\n");
-+	printk(BIOS_DEBUG, "dpr_size       = %u MiB\n", map->dpr_size);
-+	printk(BIOS_DEBUG, "tseg_size      = %u MiB\n", map->tseg_size);
-+	printk(BIOS_DEBUG, "gtt_size       = %u MiB\n", map->gtt_size);
-+	printk(BIOS_DEBUG, "gms_size       = %u MiB\n", map->gms_size);
-+	printk(BIOS_DEBUG, "me_stolen_size = %u MiB\n", map->me_stolen_size);
-+	printk(BIOS_DEBUG, "\n");
-+	printk(BIOS_DEBUG, "touud          = %u MiB\n", map->touud);
-+	printk(BIOS_DEBUG, "remaplimit     = %u MiB\n", map->remaplimit);
-+	printk(BIOS_DEBUG, "remapbase      = %u MiB\n", map->remapbase);
-+	printk(BIOS_DEBUG, "tom            = %u MiB\n", map->tom);
-+	printk(BIOS_DEBUG, "tom_minus_me   = %u MiB\n", map->tom_minus_me);
-+	printk(BIOS_DEBUG, "tolud          = %u MiB\n", map->tolud);
-+	printk(BIOS_DEBUG, "bdsm_base      = %u MiB\n", map->bdsm_base);
-+	printk(BIOS_DEBUG, "gtt_base       = %u MiB\n", map->gtt_base);
-+	printk(BIOS_DEBUG, "tseg_base      = %u MiB\n", map->tseg_base);
-+	printk(BIOS_DEBUG, "\n");
-+	printk(BIOS_DEBUG, "reclaim_possible = %s\n", map->reclaim_possible ? "Yes" : "No");
-+}
-+
-+static void map_write_reg64(const uint16_t reg, const uint64_t size)
-+{
-+	const uint64_t value = size << 20;
-+	pci_write_config32(HOST_BRIDGE, reg + 4, value >> 32);
-+	pci_write_config32(HOST_BRIDGE, reg + 0, value >>  0);
-+}
-+
-+static void map_write_reg32(const uint16_t reg, const uint32_t size)
-+{
-+	const uint32_t value = size << 20;
-+	pci_write_config32(HOST_BRIDGE, reg, value);
-+}
-+
-+static void program_memory_map(const struct memory_map_data *map)
-+{
-+	map_write_reg64(TOUUD, map->touud);
-+	map_write_reg64(TOM,   map->tom);
-+	if (map->reclaim_possible) {
-+		map_write_reg64(REMAPBASE,  map->remapbase);
-+		map_write_reg64(REMAPLIMIT, map->remaplimit);
-+	}
-+	if (map->me_stolen_size) {
-+		map_write_reg64(MESEG_LIMIT, 0x80000 - map->me_stolen_size);
-+		map_write_reg64(MESEG_BASE, map->tom_minus_me);
-+		pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, ME_STLEN_EN);
-+	}
-+	map_write_reg32(TOLUD, map->tolud);
-+	map_write_reg32(BDSM,  map->bdsm_base);
-+	map_write_reg32(BGSM,  map->gtt_base);
-+	map_write_reg32(TSEG,  map->tseg_base);
-+
-+	const uint32_t dpr_reg = map->tseg_base << 20 | map->dpr_size << 4;
-+	pci_write_config32(HOST_BRIDGE, DPR, dpr_reg);
-+
-+	const uint16_t gfx_stolen_size = GGC_IGD_MEM_IN_32MB_UNITS(map->gms_size / 32);
-+	const uint16_t ggc = map->gtt_size << 8 | gfx_stolen_size;
-+	pci_write_config16(HOST_BRIDGE, GGC, ggc);
-+
-+	/** TODO: Do not hardcode these? GDXC has weird alignment requirements, though. **/
-+	gdxcbar_write32(MPCOHTRK_GDXC_MOT_ADDRESS_LO, 0);
-+	gdxcbar_write32(MPCOHTRK_GDXC_MOT_ADDRESS_HI, 0);
-+	gdxcbar_write32(MPCOHTRK_GDXC_MOT_REGION, 0);
-+
-+	gdxcbar_write32(MPCOHTRK_GDXC_OCLA_ADDRESS_LO, 0);
-+	gdxcbar_write32(MPCOHTRK_GDXC_OCLA_ADDRESS_HI, 0);
-+	gdxcbar_write32(MPCOHTRK_GDXC_OCLA_REGION, 0);
-+
-+	gdxcbar_setbits32(MPCOHTRK_GDXC_OCLA_ADDRESS_HI, MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK);
-+}
-+
-+enum raminit_status configure_memory_map(struct sysinfo *ctrl)
-+{
-+	struct memory_map_data memory_map = {
-+		.tom            = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1],
-+		.dpr_size       = CONFIG_INTEL_TXT_DPR_SIZE,
-+		.tseg_size      = CONFIG_SMM_TSEG_SIZE >> 20,
-+		.me_stolen_size = intel_early_me_uma_size(),
-+	};
-+	/** FIXME: MRC hardcodes iGPU parameters, but we should not **/
-+	const bool igpu_on = pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN;
-+	if (CONFIG(ONBOARD_VGA_IS_PRIMARY) || igpu_on) {
-+		memory_map.gtt_size = 2;
-+		memory_map.gms_size = 64;
-+		pci_or_config32(HOST_BRIDGE, DEVEN, DEVEN_D2EN);
-+	}
-+	compute_memory_map(&memory_map);
-+	display_memory_map(&memory_map);
-+	program_memory_map(&memory_map);
-+	return 0;
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 3a773cfa19..136a8ba989 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -24,6 +24,7 @@ static const struct task_entry cold_boot[] = {
- 	{ initialise_mpll,                                        true, "INITMPLL",   },
- 	{ convert_timings,                                        true, "CONVTIM",    },
- 	{ configure_mc,                                           true, "CONFMC",     },
-+	{ configure_memory_map,                                   true, "MEMMAP",     },
- };
- 
- /* Return a generic stepping value to make stepping checks simpler */
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index cd1f2eb2a5..4763b25e8d 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -202,6 +202,7 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl);
- enum raminit_status initialise_mpll(struct sysinfo *ctrl);
- enum raminit_status convert_timings(struct sysinfo *ctrl);
- enum raminit_status configure_mc(struct sysinfo *ctrl);
-+enum raminit_status configure_memory_map(struct sysinfo *ctrl);
- 
- void configure_timings(struct sysinfo *ctrl);
- void configure_refresh(struct sysinfo *ctrl);
-diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h
-index 1ee0ab2890..0228cf6bb9 100644
---- a/src/northbridge/intel/haswell/registers/host_bridge.h
-+++ b/src/northbridge/intel/haswell/registers/host_bridge.h
-@@ -34,6 +34,8 @@
- 
- #define MESEG_BASE	0x70	/* Management Engine Base */
- #define MESEG_LIMIT	0x78	/* Management Engine Limit */
-+#define  MELCK		(1 << 10)	/* ME Range Lock */
-+#define  ME_STLEN_EN	(1 << 11)	/* ME Stolen Memory Enable */
- 
- #define PAM0		0x80
- #define PAM1		0x81
--- 
-2.39.2
-

config/coreboot/haswell/patches/0017-haswell-NRI-Add-pre-training-steps.patch

@@ -1,384 +0,0 @@
-From 42e43eb210bbb172af8e5ad064326c4570be8654 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 7 May 2022 23:12:18 +0200
-Subject: [PATCH 17/26] haswell NRI: Add pre-training steps
-
-Implement pre-training steps, which consist of enabling ECC I/O and
-filling the WDB (Write Data Buffer, stores test patterns) through a
-magic LDAT port.
-
-Change-Id: Ie2e09e3b218c4569ed8de5c5e1b05d491032e0f1
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/raminit_main.c     |  34 ++++
- .../haswell/native_raminit/raminit_native.h   |  24 +++
- .../haswell/native_raminit/reg_structs.h      |  45 +++++
- .../intel/haswell/native_raminit/setup_wdb.c  | 159 ++++++++++++++++++
- .../intel/haswell/registers/mchbar.h          |   9 +
- 6 files changed, 272 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/setup_wdb.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index e9212df9e6..8d7d4e4db0 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -10,5 +10,6 @@ romstage-y += memory_map.c
- romstage-y += raminit_main.c
- romstage-y += raminit_native.c
- romstage-y += reut.c
-+romstage-y += setup_wdb.c
- romstage-y += spd_bitmunching.c
- romstage-y += timings_refresh.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 73ff180b8c..5e4674957d 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -13,6 +13,39 @@
- 
- #include "raminit_native.h"
- 
-+static enum raminit_status pre_training(struct sysinfo *ctrl)
-+{
-+	/* Skip on S3 resume */
-+	if (ctrl->bootmode == BOOTMODE_S3)
-+		return RAMINIT_STATUS_SUCCESS;
-+
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
-+			if (!rank_in_ch(ctrl, slot + slot, channel))
-+				continue;
-+
-+			printk(RAM_DEBUG, "C%uS%u:\n", channel, slot);
-+			printk(RAM_DEBUG, "\tMR0: 0x%04x\n", ctrl->mr0[channel][slot]);
-+			printk(RAM_DEBUG, "\tMR1: 0x%04x\n", ctrl->mr1[channel][slot]);
-+			printk(RAM_DEBUG, "\tMR2: 0x%04x\n", ctrl->mr2[channel][slot]);
-+			printk(RAM_DEBUG, "\tMR3: 0x%04x\n", ctrl->mr3[channel][slot]);
-+			printk(RAM_DEBUG, "\n");
-+		}
-+		if (ctrl->is_ecc) {
-+			union mad_dimm_reg mad_dimm = {
-+				.raw = mchbar_read32(MAD_DIMM(channel)),
-+			};
-+			/* Enable ECC I/O */
-+			mad_dimm.ecc_mode = 1;
-+			mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
-+			/* Wait 4 usec after enabling the ECC I/O, needed by HW */
-+			udelay(4);
-+		}
-+	}
-+	setup_wdb(ctrl);
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
- struct task_entry {
- 	enum raminit_status (*task)(struct sysinfo *);
- 	bool is_enabled;
-@@ -26,6 +59,7 @@ static const struct task_entry cold_boot[] = {
- 	{ configure_mc,                                           true, "CONFMC",     },
- 	{ configure_memory_map,                                   true, "MEMMAP",     },
- 	{ do_jedec_init,                                          true, "JEDECINIT",  },
-+	{ pre_training,                                           true, "PRETRAIN",   },
- };
- 
- /* Return a generic stepping value to make stepping checks simpler */
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index e3cf4254a0..f29c2ec366 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -35,6 +35,13 @@
- 
- #define RTTNOM_MASK		(BIT(9) | BIT(6) | BIT(2))
- 
-+#define BASIC_VA_PAT_SPREAD_8	0x01010101
-+
-+#define WDB_CACHE_LINE_SIZE	8
-+
-+#define NUM_WDB_CL_MUX_SEEDS	3
-+#define NUM_CADB_MUX_SEEDS	3
-+
- /* ZQ calibration types */
- enum {
- 	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
-@@ -318,6 +325,23 @@ void reut_issue_mrs_all(
- 
- enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type);
- 
-+void write_wdb_fixed_pat(
-+	const struct sysinfo *ctrl,
-+	const uint8_t patterns[],
-+	const uint8_t pat_mask[],
-+	uint8_t spread,
-+	uint16_t start);
-+
-+void write_wdb_va_pat(
-+	const struct sysinfo *ctrl,
-+	uint32_t agg_mask,
-+	uint32_t vic_mask,
-+	uint8_t vic_rot,
-+	uint16_t start);
-+
-+void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup);
-+void setup_wdb(const struct sysinfo *ctrl);
-+
- uint8_t get_rx_bias(const struct sysinfo *ctrl);
- 
- uint8_t get_tCWL(uint32_t mem_clock_mhz);
-diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-index 9929f617fe..7aa8d8c8b2 100644
---- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-@@ -335,6 +335,18 @@ union mcscheds_cbit_reg {
- 	uint32_t raw;
- };
- 
-+union reut_pat_cl_mux_lmn_reg {
-+	struct __packed {
-+		uint32_t l_data_select : 1; // Bits  0:0
-+		uint32_t en_sweep_freq : 1; // Bits  1:1
-+		uint32_t               : 6; // Bits  7:2
-+		uint32_t l_counter     : 8; // Bits 15:8
-+		uint32_t m_counter     : 8; // Bits 23:16
-+		uint32_t n_counter     : 8; // Bits 31:24
-+	};
-+	uint32_t raw;
-+};
-+
- union reut_pat_cadb_prog_reg {
- 	struct __packed {
- 		uint32_t addr : 16; // Bits 15:0
-@@ -439,6 +451,39 @@ union reut_misc_odt_ctrl_reg {
- 	uint32_t raw;
- };
- 
-+union ldat_pdat_reg {
-+	struct __packed {
-+		uint32_t fast_addr : 12; // Bits 11:0
-+		uint32_t           :  4; // Bits 15:12
-+		uint32_t addr_en   :  1; // Bits 16:16
-+		uint32_t seq_en    :  1; // Bits 17:17
-+		uint32_t pol_0     :  1; // Bits 18:18
-+		uint32_t pol_1     :  1; // Bits 19:19
-+		uint32_t cmd_a     :  4; // Bits 23:20
-+		uint32_t cmd_b     :  4; // Bits 27:24
-+		uint32_t cmd_c     :  4; // Bits 31:28
-+	};
-+	uint32_t raw;
-+};
-+
-+union ldat_sdat_reg {
-+	struct __packed {
-+		uint32_t bank_sel   : 4; // Bits  3:0
-+		uint32_t            : 1; // Bits  4:4
-+		uint32_t array_sel  : 5; // Bits  9:5
-+		uint32_t cmp        : 1; // Bits 10:10
-+		uint32_t replicate  : 1; // Bits 11:11
-+		uint32_t dword      : 4; // Bits 15:12
-+		uint32_t mode       : 2; // Bits 17:16
-+		uint32_t mpmap      : 6; // Bits 23:18
-+		uint32_t mpb_offset : 4; // Bits 27:24
-+		uint32_t stage_en   : 1; // Bits 28:28
-+		uint32_t shadow     : 2; // Bits 30:29
-+		uint32_t            : 1; // Bits 31:31
-+	};
-+	uint32_t raw;
-+};
-+
- union mcscheds_dft_misc_reg {
- 	struct __packed {
- 		uint32_t wdar                 :  1; // Bits  0:0
-diff --git a/src/northbridge/intel/haswell/native_raminit/setup_wdb.c b/src/northbridge/intel/haswell/native_raminit/setup_wdb.c
-new file mode 100644
-index 0000000000..ec37c48415
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/setup_wdb.c
-@@ -0,0 +1,159 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+static void ldat_write_cacheline(
-+	const struct sysinfo *const ctrl,
-+	const uint8_t chunk,
-+	const uint16_t start,
-+	const uint64_t data)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		/*
-+		 * Do not do a 64-bit write here. The register is not aligned
-+		 * to a 64-bit boundary, which could potentially cause issues.
-+		 */
-+		mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 0), data & UINT32_MAX);
-+		mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 1), data >> 32);
-+		/*
-+		 * Set REPLICATE = 0 as you don't want to replicate the data.
-+		 * Set BANK_SEL to the chunk you want to write the 64 bits to.
-+		 * Set ARRAY_SEL = 0 (the MC WDB) and MODE = 1.
-+		 */
-+		const union ldat_sdat_reg ldat_sdat = {
-+			.bank_sel = chunk,
-+			.mode     = 1,
-+		};
-+		mchbar_write32(QCLK_ch_LDAT_SDAT(channel), ldat_sdat.raw);
-+		/*
-+		 * Finally, write the PDAT register indicating which cacheline
-+		 * of the WDB you want to write to by setting FAST_ADDR field
-+		 * to one of the 64 cache lines. Also set CMD_B in the PDAT
-+		 * register to 4'b1000, indicating that this is a LDAT write.
-+		 */
-+		const union ldat_pdat_reg ldat_pdat = {
-+			.fast_addr = MIN(start, 0xfff),
-+			.cmd_b     = 8,
-+		};
-+		mchbar_write32(QCLK_ch_LDAT_PDAT(channel), ldat_pdat.raw);
-+	}
-+}
-+
-+static void clear_ldat_mode(const struct sysinfo *const ctrl)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
-+		mchbar_write32(QCLK_ch_LDAT_SDAT(channel), 0);
-+}
-+
-+void write_wdb_fixed_pat(
-+	const struct sysinfo *const ctrl,
-+	const uint8_t patterns[],
-+	const uint8_t pat_mask[],
-+	const uint8_t spread,
-+	const uint16_t start)
-+{
-+	for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
-+		uint64_t data = 0;
-+		for (uint8_t b = 0; b < 64; b++) {
-+			const uint8_t beff  = b % spread;
-+			const uint8_t burst = patterns[pat_mask[beff]];
-+			if (burst & BIT(chunk))
-+				data |= 1ULL << b;
-+		}
-+		ldat_write_cacheline(ctrl, chunk, start, data);
-+	}
-+	clear_ldat_mode(ctrl);
-+}
-+
-+static inline uint32_t rol_u32(const uint32_t val)
-+{
-+	return (val << 1) | ((val >> 31) & 1);
-+}
-+
-+void write_wdb_va_pat(
-+	const struct sysinfo *const ctrl,
-+	const uint32_t agg_mask,
-+	const uint32_t vic_mask,
-+	const uint8_t vic_rot,
-+	const uint16_t start)
-+{
-+	static const uint8_t va_mask_to_compressed[4] = {0xaa, 0xc0, 0xcc, 0xf0};
-+	uint32_t v_mask = vic_mask;
-+	uint32_t a_mask = agg_mask;
-+	for (uint8_t v = 0; v < vic_rot; v++) {
-+		uint8_t compressed[32] = {0};
-+		/* Iterate through all 32 bits and create a compressed version of cacheline */
-+		for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++) {
-+			const uint8_t vic = !!(v_mask & BIT(b));
-+			const uint8_t agg = !!(a_mask & BIT(b));
-+			const uint8_t index = !vic << 1 | agg << 0;
-+			compressed[b] = va_mask_to_compressed[index];
-+		}
-+		for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
-+			uint32_t data = 0;
-+			for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++)
-+				data |= !!(compressed[b] & BIT(chunk)) << b;
-+
-+			const uint64_t data64 = (uint64_t)data << 32 | data;
-+			ldat_write_cacheline(ctrl, chunk, start + v, data64);
-+		}
-+		v_mask = rol_u32(v_mask);
-+		a_mask = rol_u32(a_mask);
-+	}
-+	clear_ldat_mode(ctrl);
-+}
-+
-+void program_wdb_lfsr(const struct sysinfo *ctrl, const bool cleanup)
-+{
-+	/* Cleanup LFSR seeds are sequential */
-+	const uint32_t cleanup_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xaaaaaa, 0xcccccc, 0xf0f0f0 };
-+	const uint32_t regular_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xa10ca1, 0xef0d08, 0xad0a1e };
-+	const uint32_t *seeds = cleanup ? cleanup_seeds : regular_seeds;
-+
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		for (uint8_t i = 0; i < NUM_WDB_CL_MUX_SEEDS; i++) {
-+			mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_RD_x(channel, i), seeds[i]);
-+			mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_WR_x(channel, i), seeds[i]);
-+		}
-+	}
-+}
-+
-+void setup_wdb(const struct sysinfo *ctrl)
-+{
-+	const uint32_t amask[9] = {
-+		0x86186186, 0x18618618, 0x30c30c30,
-+		0xa28a28a2, 0x8a28a28a, 0x14514514,
-+		0x28a28a28, 0x92492492, 0x24924924,
-+	};
-+	const uint32_t vmask = 0x41041041;
-+
-+	/* Fill first 8 entries with simple 2-LFSR VA pattern */
-+	write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
-+
-+	/* Fill next 54 entries with 3-LFSR VA pattern */
-+	for (uint8_t a = 0; a < ARRAY_SIZE(amask); a++)
-+		write_wdb_va_pat(ctrl, amask[a], vmask, 6, 8 + a * 6);
-+
-+	program_wdb_lfsr(ctrl, false);
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		const union reut_pat_cl_mux_lmn_reg wdb_cl_mux_lmn = {
-+			.en_sweep_freq = 1,
-+			.l_counter     = 1,
-+			.m_counter     = 1,
-+			.n_counter     = 10,
-+		};
-+		mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_LMN(channel), wdb_cl_mux_lmn.raw);
-+	}
-+}
-diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
-index 4fc78a7f43..f8408e51a0 100644
---- a/src/northbridge/intel/haswell/registers/mchbar.h
-+++ b/src/northbridge/intel/haswell/registers/mchbar.h
-@@ -94,6 +94,11 @@
- #define TC_BANK_RANK_D_ch(ch)			_MCMAIN_C(0x4014, ch)
- #define SC_ROUNDT_LAT_ch(ch)			_MCMAIN_C(0x4024, ch)
- 
-+#define REUT_ch_PAT_WDB_CL_MUX_WR_x(ch, x)	_MCMAIN_C_X(0x4048, ch, x) /* x in 0 .. 2 */
-+#define REUT_ch_PAT_WDB_CL_MUX_RD_x(ch, x)	_MCMAIN_C_X(0x4054, ch, x) /* x in 0 .. 2 */
-+
-+#define REUT_ch_PAT_WDB_CL_MUX_LMN(ch)		_MCMAIN_C(0x4078, ch)
-+
- #define SC_WR_ADD_DELAY_ch(ch)			_MCMAIN_C(0x40d0, ch)
- 
- #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
-@@ -110,6 +115,10 @@
- #define MC_INIT_STATE_ch(ch)			_MCMAIN_C(0x42a0, ch)
- #define TC_SRFTP_ch(ch)				_MCMAIN_C(0x42a4, ch)
- 
-+#define QCLK_ch_LDAT_PDAT(ch)			_MCMAIN_C(0x42d0, ch)
-+#define QCLK_ch_LDAT_SDAT(ch)			_MCMAIN_C(0x42d4, ch)
-+#define QCLK_ch_LDAT_DATA_IN_x(ch, x)		_MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
-+
- #define REUT_GLOBAL_ERR				0x4804
- 
- #define REUT_ch_SEQ_CFG(ch)			(0x48a8 + 8 * (ch))
--- 
-2.39.2
-

config/coreboot/haswell/patches/0019-haswell-NRI-Add-range-tracking-library.patch

@@ -1,222 +0,0 @@
-From 9fba0468e75877cbda62f5eaeef1946d6489a8f9 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sun, 8 May 2022 00:56:00 +0200
-Subject: [PATCH 19/26] haswell NRI: Add range tracking library
-
-Implement a small library used to keep track of passing ranges. This
-will be used by 1D training algorithms when margining some parameter.
-
-Change-Id: I8718e85165160afd7c0c8e730b5ce6c9c00f8a60
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../intel/haswell/native_raminit/ranges.c     | 109 ++++++++++++++++++
- .../intel/haswell/native_raminit/ranges.h     |  68 +++++++++++
- 3 files changed, 178 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.c
- create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.h
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index 6e1b365602..2da950771d 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -9,6 +9,7 @@ romstage-y += io_comp_control.c
- romstage-y += memory_map.c
- romstage-y += raminit_main.c
- romstage-y += raminit_native.c
-+romstage-y += ranges.c
- romstage-y += reut.c
- romstage-y += setup_wdb.c
- romstage-y += spd_bitmunching.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/ranges.c b/src/northbridge/intel/haswell/native_raminit/ranges.c
-new file mode 100644
-index 0000000000..cdebc1fa66
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/ranges.c
-@@ -0,0 +1,109 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <types.h>
-+
-+#include "ranges.h"
-+
-+void linear_record_pass(
-+	struct linear_train_data *const data,
-+	const bool pass,
-+	const int32_t value,
-+	const int32_t start,
-+	const int32_t step)
-+{
-+	/* If this is the first time, initialize all values */
-+	if (value == start) {
-+		/*
-+		 * If value passed, create a zero-length region for the current value,
-+		 * which may be extended as long as the successive values are passing.
-+		 *
-+		 * Otherwise, create a zero-length range for the preceding value. This
-+		 * range cannot be extended by other passing values, which is desired.
-+		 */
-+		data->current.start = start - (pass ? 0 : step);
-+		data->current.end   = data->current.start;
-+		data->largest       = data->current;
-+	} else if (pass) {
-+		/* If this pass is not contiguous, it belongs to a new region */
-+		if (data->current.end != (value - step))
-+			data->current.start = value;
-+
-+		/* Update end of current region */
-+		data->current.end = value;
-+
-+		/* Update largest region */
-+		if (range_width(data->current) > range_width(data->largest))
-+			data->largest = data->current;
-+	}
-+}
-+
-+void phase_record_pass(
-+	struct phase_train_data *const data,
-+	const bool pass,
-+	const int32_t value,
-+	const int32_t start,
-+	const int32_t step)
-+{
-+	/* If this is the first time, initialize all values */
-+	if (value == start) {
-+		/*
-+		 * If value passed, create a zero-length region for the current value,
-+		 * which may be extended as long as the successive values are passing.
-+		 *
-+		 * Otherwise, create a zero-length range for the preceding value. This
-+		 * range cannot be extended by other passing values, which is desired.
-+		 */
-+		data->current.start = start - (pass ? 0 : step);
-+		data->current.end   = data->current.start;
-+		data->largest       = data->current;
-+		data->initial       = data->current;
-+		return;
-+	}
-+	if (!pass)
-+		return;
-+
-+	/* Update initial region */
-+	if (data->initial.end == (value - step))
-+		data->initial.end = value;
-+
-+	/* If this pass is not contiguous, it belongs to a new region */
-+	if (data->current.end != (value - step))
-+		data->current.start = value;
-+
-+	/* Update end of current region */
-+	data->current.end = value;
-+
-+	/* Update largest region */
-+	if (range_width(data->current) > range_width(data->largest))
-+		data->largest = data->current;
-+}
-+
-+void phase_append_initial_to_current(
-+	struct phase_train_data *const data,
-+	const int32_t start,
-+	const int32_t step)
-+{
-+	/* If initial region is valid and does not overlap, append it */
-+	if (data->initial.start == start && data->initial.end != data->current.end)
-+		data->current.end += step + range_width(data->initial);
-+
-+	/* Update largest region */
-+	if (range_width(data->current) > range_width(data->largest))
-+		data->largest = data->current;
-+}
-+
-+void phase_append_current_to_initial(
-+	struct phase_train_data *const data,
-+	const int32_t start,
-+	const int32_t step)
-+{
-+	/* If initial region is valid and does not overlap, append it */
-+	if (data->initial.start == start && data->initial.end != data->current.end) {
-+		data->initial.start -= (step + range_width(data->current));
-+		data->current = data->initial;
-+	}
-+
-+	/* Update largest region */
-+	if (range_width(data->current) > range_width(data->largest))
-+		data->largest = data->current;
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/ranges.h b/src/northbridge/intel/haswell/native_raminit/ranges.h
-new file mode 100644
-index 0000000000..235392df96
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/ranges.h
-@@ -0,0 +1,68 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#ifndef HASWELL_RAMINIT_RANGES_H
-+#define HASWELL_RAMINIT_RANGES_H
-+
-+#include <types.h>
-+
-+/*
-+ * Many algorithms shmoo some parameter to determine the largest passing
-+ * range. Provide a common implementation to avoid redundant boilerplate.
-+ */
-+struct passing_range {
-+	int32_t start;
-+	int32_t end;
-+};
-+
-+/* Structure for linear parameters, such as roundtrip delays */
-+struct linear_train_data {
-+	struct passing_range current;
-+	struct passing_range largest;
-+};
-+
-+/*
-+ * Phase ranges are "circular": the first and last indices are contiguous.
-+ * To correctly determine the largest passing range, one has to combine
-+ * the initial range and the current range when processing the last index.
-+ */
-+struct phase_train_data {
-+	struct passing_range initial;
-+	struct passing_range current;
-+	struct passing_range largest;
-+};
-+
-+static inline int32_t range_width(const struct passing_range range)
-+{
-+	return range.end - range.start;
-+}
-+
-+static inline int32_t range_center(const struct passing_range range)
-+{
-+	return range.start + range_width(range) / 2;
-+}
-+
-+void linear_record_pass(
-+	struct linear_train_data *data,
-+	bool pass,
-+	int32_t value,
-+	int32_t start,
-+	int32_t step);
-+
-+void phase_record_pass(
-+	struct phase_train_data *data,
-+	bool pass,
-+	int32_t value,
-+	int32_t start,
-+	int32_t step);
-+
-+void phase_append_initial_to_current(
-+	struct phase_train_data *data,
-+	int32_t start,
-+	int32_t step);
-+
-+void phase_append_current_to_initial(
-+	struct phase_train_data *data,
-+	int32_t start,
-+	int32_t step);
-+
-+#endif
--- 
-2.39.2
-

config/coreboot/haswell/patches/0020-haswell-NRI-Add-library-to-change-margins.patch

@@ -1,294 +0,0 @@
-From 54cfbe4cf53d16f747bfcfadd20445a0f5f1e5db Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sun, 8 May 2022 01:11:03 +0200
-Subject: [PATCH 20/26] haswell NRI: Add library to change margins
-
-Implement a library to change Rx/Tx margins. It will be expanded later.
-
-Change-Id: I0b55aba428d8b4d4e16d2fbdec57235ce3ce8adf
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/change_margin.c    | 154 ++++++++++++++++++
- .../haswell/native_raminit/raminit_native.h   |  50 ++++++
- .../intel/haswell/registers/mchbar.h          |   9 +
- 4 files changed, 214 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/change_margin.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index 2da950771d..ebe9e9b762 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -1,5 +1,6 @@
- ## SPDX-License-Identifier: GPL-2.0-or-later
- 
-+romstage-y += change_margin.c
- romstage-y += configure_mc.c
- romstage-y += ddr3.c
- romstage-y += jedec_reset.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
-new file mode 100644
-index 0000000000..12da59580f
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
-@@ -0,0 +1,154 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <commonlib/clamp.h>
-+#include <console/console.h>
-+#include <delay.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <timer.h>
-+
-+#include "raminit_native.h"
-+
-+void update_rxt(
-+	struct sysinfo *ctrl,
-+	const uint8_t channel,
-+	const uint8_t rank,
-+	const uint8_t byte,
-+	const enum rxt_subfield subfield,
-+	const int32_t value)
-+{
-+	union ddr_data_rx_train_rank_reg rxt = {
-+		.rcven =  ctrl->rcven[channel][rank][byte],
-+		.dqs_p = ctrl->rxdqsp[channel][rank][byte],
-+		.rx_eq =  ctrl->rx_eq[channel][rank][byte],
-+		.dqs_n = ctrl->rxdqsn[channel][rank][byte],
-+		.vref  = ctrl->rxvref[channel][rank][byte],
-+	};
-+	int32_t new_value;
-+	switch (subfield) {
-+	case RXT_RCVEN:
-+		new_value = clamp_s32(0, value, 511);
-+		rxt.rcven = new_value;
-+		break;
-+	case RXT_RXDQS_P:
-+		new_value = clamp_s32(0, value, 63);
-+		rxt.dqs_p = new_value;
-+		break;
-+	case RXT_RX_EQ:
-+		new_value = clamp_s32(0, value, 31);
-+		rxt.rx_eq = new_value;
-+		break;
-+	case RXT_RXDQS_N:
-+		new_value = clamp_s32(0, value, 63);
-+		rxt.dqs_n = new_value;
-+		break;
-+	case RXT_RX_VREF:
-+		new_value = clamp_s32(-32, value, 31);
-+		rxt.vref = new_value;
-+		break;
-+	case RXT_RXDQS_BOTH:
-+		new_value = clamp_s32(0, value, 63);
-+		rxt.dqs_p = new_value;
-+		rxt.dqs_n = new_value;
-+		break;
-+	case RXT_RESTORE:
-+		new_value = value;
-+		break;
-+	default:
-+		die("%s: Unhandled subfield index %u\n", __func__, subfield);
-+	}
-+
-+	if (new_value != value) {
-+		printk(BIOS_ERR, "%s: Overflow for subfield %u: %d ---> %d\n",
-+			__func__, subfield, value, new_value);
-+	}
-+	mchbar_write32(RX_TRAIN_ch_r_b(channel, rank, byte), rxt.raw);
-+	download_regfile(ctrl, channel, false, rank, REG_FILE_USE_RANK, byte, true, false);
-+}
-+
-+void update_txt(
-+	struct sysinfo *ctrl,
-+	const uint8_t channel,
-+	const uint8_t rank,
-+	const uint8_t byte,
-+	const enum txt_subfield subfield,
-+	const int32_t value)
-+{
-+	union ddr_data_tx_train_rank_reg txt = {
-+		.dq_delay  = ctrl->tx_dq[channel][rank][byte],
-+		.dqs_delay = ctrl->txdqs[channel][rank][byte],
-+		.tx_eq     = ctrl->tx_eq[channel][rank][byte],
-+	};
-+	int32_t new_value;
-+	switch (subfield) {
-+	case TXT_TX_DQ:
-+		new_value = clamp_s32(0, value, 511);
-+		txt.dq_delay = new_value;
-+		break;
-+	case TXT_TXDQS:
-+		new_value = clamp_s32(0, value, 511);
-+		txt.dqs_delay = new_value;
-+		break;
-+	case TXT_TX_EQ:
-+		new_value = clamp_s32(0, value, 63);
-+		txt.tx_eq = new_value;
-+		break;
-+	case TXT_DQDQS_OFF:
-+		new_value = value;
-+		txt.dqs_delay += new_value;
-+		txt.dq_delay  += new_value;
-+		break;
-+	case TXT_RESTORE:
-+		new_value = value;
-+		break;
-+	default:
-+		die("%s: Unhandled subfield index %u\n", __func__, subfield);
-+	}
-+	if (new_value != value) {
-+		printk(BIOS_ERR, "%s: Overflow for subfield %u: %d ---> %d\n",
-+			__func__, subfield, value, new_value);
-+	}
-+	mchbar_write32(TX_TRAIN_ch_r_b(channel, rank, byte), txt.raw);
-+	download_regfile(ctrl, channel, false, rank, REG_FILE_USE_RANK, byte, false, true);
-+}
-+
-+void download_regfile(
-+	struct sysinfo *ctrl,
-+	const uint8_t channel,
-+	const bool multicast,
-+	const uint8_t rank,
-+	const enum regfile_mode regfile,
-+	const uint8_t byte,
-+	const bool read_rf_rd,
-+	const bool read_rf_wr)
-+{
-+	union reut_seq_base_addr_reg reut_seq_base_addr;
-+	switch (regfile) {
-+	case REG_FILE_USE_START:
-+		reut_seq_base_addr.raw = mchbar_read64(REUT_ch_SEQ_ADDR_START(channel));
-+		break;
-+	case REG_FILE_USE_CURRENT:
-+		reut_seq_base_addr.raw = mchbar_read64(REUT_ch_SEQ_ADDR_CURRENT(channel));
-+		break;
-+	case REG_FILE_USE_RANK:
-+		reut_seq_base_addr.raw = 0;
-+		if (rank >= NUM_SLOTRANKS)
-+			die("%s: bad rank %u\n", __func__, rank);
-+		break;
-+	default:
-+		die("%s: Invalid regfile param %u\n", __func__, regfile);
-+	}
-+	uint8_t phys_rank = rank;
-+	if (reut_seq_base_addr.raw != 0) {
-+		/* Map REUT logical rank to physical rank */
-+		const uint32_t log_to_phys = mchbar_read32(REUT_ch_RANK_LOG_TO_PHYS(channel));
-+		phys_rank = log_to_phys >> (reut_seq_base_addr.rank_addr * 4) & 0x3;
-+	}
-+	uint32_t reg = multicast ? DDR_DATA_ch_CONTROL_0(channel) : DQ_CONTROL_0(channel, byte);
-+	union ddr_data_control_0_reg ddr_data_control_0 = {
-+		.raw = mchbar_read32(reg),
-+	};
-+	ddr_data_control_0.read_rf_rd   = read_rf_rd;
-+	ddr_data_control_0.read_rf_wr   = read_rf_wr;
-+	ddr_data_control_0.read_rf_rank = phys_rank;
-+	mchbar_write32(reg, ddr_data_control_0.raw);
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 56df36ca8d..7c1a786780 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -117,6 +117,30 @@ enum test_stop {
- 	ALSOE  = 3,	/* Stop on all lanes error */
- };
- 
-+enum rxt_subfield {
-+	RXT_RCVEN	= 0,
-+	RXT_RXDQS_P	= 1,
-+	RXT_RX_EQ	= 2,
-+	RXT_RXDQS_N	= 3,
-+	RXT_RX_VREF	= 4,
-+	RXT_RXDQS_BOTH	= 5,
-+	RXT_RESTORE	= 255,
-+};
-+
-+enum txt_subfield {
-+	TXT_TX_DQ	= 0,
-+	TXT_TXDQS	= 1,
-+	TXT_TX_EQ	= 2,
-+	TXT_DQDQS_OFF	= 3,
-+	TXT_RESTORE	= 255,
-+};
-+
-+enum regfile_mode {
-+	REG_FILE_USE_RANK,	/* Used when changing parameters for each rank */
-+	REG_FILE_USE_START,	/* Used when changing parameters before the test */
-+	REG_FILE_USE_CURRENT,	/* Used when changing parameters after the test */
-+};
-+
- struct wdb_pat {
- 	uint32_t start_ptr;	/* Starting pointer in WDB */
- 	uint32_t stop_ptr;	/* Stopping pointer in WDB */
-@@ -452,6 +476,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas
- void run_mpr_io_test(bool clear_errors);
- uint8_t run_io_test(struct sysinfo *ctrl, uint8_t chanmask, uint8_t dq_pat, bool clear_errors);
- 
-+void update_rxt(
-+	struct sysinfo *ctrl,
-+	uint8_t channel,
-+	uint8_t rank,
-+	uint8_t byte,
-+	enum rxt_subfield subfield,
-+	int32_t value);
-+
-+void update_txt(
-+	struct sysinfo *ctrl,
-+	uint8_t channel,
-+	uint8_t rank,
-+	uint8_t byte,
-+	enum txt_subfield subfield,
-+	int32_t value);
-+
-+void download_regfile(
-+	struct sysinfo *ctrl,
-+	uint8_t channel,
-+	bool multicast,
-+	uint8_t rank,
-+	enum regfile_mode regfile,
-+	uint8_t byte,
-+	bool read_rf_rd,
-+	bool read_rf_wr);
-+
- uint8_t get_rx_bias(const struct sysinfo *ctrl);
- 
- uint8_t get_tCWL(uint32_t mem_clock_mhz);
-diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
-index 817a9f8bf8..a81559bb1e 100644
---- a/src/northbridge/intel/haswell/registers/mchbar.h
-+++ b/src/northbridge/intel/haswell/registers/mchbar.h
-@@ -15,7 +15,11 @@
- /* Register definitions */
- 
- /* DDR DATA per-channel per-bytelane */
-+#define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
-+#define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
-+
- #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
-+#define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
- 
- /* DDR CKE per-channel */
- #define DDR_CKE_ch_CMD_COMP_OFFSET(ch)		_DDRIO_C_R_B(0x1204, ch, 0, 0)
-@@ -38,6 +42,9 @@
- #define DDR_SCRAMBLE_ch(ch)			(0x2000 + 4 * (ch))
- #define DDR_SCRAM_MISC_CONTROL			0x2008
- 
-+/* DDR DATA per-channel multicast */
-+#define DDR_DATA_ch_CONTROL_0(ch)		_DDRIO_C_R_B(0x3074, ch, 0, 0)
-+
- /* DDR CMDN/CMDS per-channel (writes go to both CMDN and CMDS fubs) */
- #define DDR_CMD_ch_COMP_OFFSET(ch)		_DDRIO_C_R_B(0x3204, ch, 0, 0)
- #define DDR_CMD_ch_PI_CODING(ch)		_DDRIO_C_R_B(0x3208, ch, 0, 0)
-@@ -147,6 +154,8 @@
- 
- #define REUT_ch_SEQ_ADDR_WRAP(ch)		(0x48e8 + 8 * (ch))
- 
-+#define REUT_ch_SEQ_ADDR_CURRENT(ch)		(0x48f8 + 8 * (ch))
-+
- #define REUT_ch_SEQ_MISC_CTL(ch)		(0x4908 + 4 * (ch))
- 
- #define REUT_ch_SEQ_ADDR_INC_CTL(ch)		(0x4910 + 8 * (ch))
--- 
-2.39.2
-

config/coreboot/haswell/patches/0021-haswell-NRI-Add-RcvEn-training.patch

@@ -1,708 +0,0 @@
-From ac8843553af34855d0331554c03280e66c4ea582 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sun, 8 May 2022 00:05:41 +0200
-Subject: [PATCH 21/26] haswell NRI: Add RcvEn training
-
-Implement the RcvEn (Receive Enable) calibration procedure.
-
-Change-Id: Ifbfa520f3e0486c56d0988ce67af2ddb9cf29888
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/raminit_main.c     |   1 +
- .../haswell/native_raminit/raminit_native.h   |  14 +
- .../haswell/native_raminit/reg_structs.h      |  13 +
- .../native_raminit/train_receive_enable.c     | 561 ++++++++++++++++++
- .../intel/haswell/registers/mchbar.h          |   3 +
- 6 files changed, 593 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index ebe9e9b762..e2fbfb4211 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -16,3 +16,4 @@ romstage-y += setup_wdb.c
- romstage-y += spd_bitmunching.c
- romstage-y += testing_io.c
- romstage-y += timings_refresh.c
-+romstage-y += train_receive_enable.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 5e4674957d..7d444659c3 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = {
- 	{ configure_memory_map,                                   true, "MEMMAP",     },
- 	{ do_jedec_init,                                          true, "JEDECINIT",  },
- 	{ pre_training,                                           true, "PRETRAIN",   },
-+	{ train_receive_enable,                                   true, "RCVET",      },
- };
- 
- /* Return a generic stepping value to make stepping checks simpler */
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 7c1a786780..a36ebfacd1 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -42,6 +42,9 @@
- #define NUM_WDB_CL_MUX_SEEDS	3
- #define NUM_CADB_MUX_SEEDS	3
- 
-+/* Specified in PI ticks. 64 PI ticks == 1 qclk */
-+#define tDQSCK_DRIFT		64
-+
- /* ZQ calibration types */
- enum {
- 	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
-@@ -188,6 +191,7 @@ enum raminit_status {
- 	RAMINIT_STATUS_MPLL_INIT_FAILURE,
- 	RAMINIT_STATUS_POLL_TIMEOUT,
- 	RAMINIT_STATUS_REUT_ERROR,
-+	RAMINIT_STATUS_RCVEN_FAILURE,
- 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
- };
- 
-@@ -270,6 +274,10 @@ struct sysinfo {
- 
- 	union ddr_data_vref_adjust_reg dimm_vref;
- 
-+	uint8_t io_latency[NUM_CHANNELS][NUM_SLOTRANKS];
-+	uint8_t rt_latency[NUM_CHANNELS][NUM_SLOTRANKS];
-+	uint32_t rt_io_comp[NUM_CHANNELS];
-+
- 	uint32_t data_offset_train[NUM_CHANNELS][NUM_LANES];
- 	uint32_t data_offset_comp[NUM_CHANNELS][NUM_LANES];
- 
-@@ -344,6 +352,11 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl)
- 	memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train));
- }
- 
-+static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint8_t byte)
-+{
-+	return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte));
-+}
-+
- /* Number of ticks to wait in units of 69.841279 ns (citation needed) */
- static inline void tick_delay(const uint32_t delay)
- {
-@@ -401,6 +414,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
- enum raminit_status configure_mc(struct sysinfo *ctrl);
- enum raminit_status configure_memory_map(struct sysinfo *ctrl);
- enum raminit_status do_jedec_init(struct sysinfo *ctrl);
-+enum raminit_status train_receive_enable(struct sysinfo *ctrl);
- 
- void configure_timings(struct sysinfo *ctrl);
- void configure_refresh(struct sysinfo *ctrl);
-diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-index b943259b91..b099f4bb82 100644
---- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-@@ -297,6 +297,19 @@ union ddr_scram_misc_control_reg {
- 	uint32_t raw;
- };
- 
-+union sc_io_latency_reg {
-+	struct __packed {
-+		uint32_t iolat_rank0     : 4; // Bits  3:0
-+		uint32_t iolat_rank1     : 4; // Bits  7:4
-+		uint32_t iolat_rank2     : 4; // Bits 11:8
-+		uint32_t iolat_rank3     : 4; // Bits 15:12
-+		uint32_t rt_iocomp       : 6; // Bits 21:16
-+		uint32_t                 : 9; // Bits 30:22
-+		uint32_t dis_rt_clk_gate : 1; // Bits 31:31
-+	};
-+	uint32_t raw;
-+};
-+
- union mcscheds_cbit_reg {
- 	struct __packed {
- 		uint32_t dis_opp_cas    : 1; // Bits  0:0
-diff --git a/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
-new file mode 100644
-index 0000000000..576c6bc21e
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
-@@ -0,0 +1,561 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+#include "ranges.h"
-+
-+#define RCVEN_PLOT	RAM_DEBUG
-+
-+static enum raminit_status change_rcven_timing(struct sysinfo *ctrl, const uint8_t channel)
-+{
-+	int16_t max_rcven = -4096;
-+	int16_t min_rcven = 4096;
-+	int16_t max_rcven_rank[NUM_SLOTRANKS];
-+	int16_t min_rcven_rank[NUM_SLOTRANKS];
-+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+		max_rcven_rank[rank] = max_rcven;
-+		min_rcven_rank[rank] = min_rcven;
-+	}
-+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+		if (!rank_in_ch(ctrl, rank, channel))
-+			continue;
-+
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			int16_t new_rcven = ctrl->rcven[channel][rank][byte];
-+			new_rcven -= ctrl->io_latency[channel][rank] * 64;
-+			if (max_rcven_rank[rank] < new_rcven)
-+				max_rcven_rank[rank] = new_rcven;
-+
-+			if (min_rcven_rank[rank] > new_rcven)
-+				min_rcven_rank[rank] = new_rcven;
-+		}
-+		if (max_rcven < max_rcven_rank[rank])
-+			max_rcven = max_rcven_rank[rank];
-+
-+		if (min_rcven > min_rcven_rank[rank])
-+			min_rcven = min_rcven_rank[rank];
-+	}
-+
-+	/*
-+	 * Determine how far we are from the ideal center point for RcvEn timing.
-+	 * (PiIdeal - AveRcvEn) / 64 is the ideal number of cycles we should have
-+	 * for IO latency. command training will reduce this by 64, so plan for
-+	 * that now in the ideal value. Round to closest integer.
-+	 */
-+	const int16_t rre_pi_ideal = 256 + 64;
-+	const int16_t pi_reserve = 64;
-+	const int16_t rcven_center = (max_rcven + min_rcven) / 2;
-+	const int8_t iolat_target = DIV_ROUND_CLOSEST(rre_pi_ideal - rcven_center, 64);
-+
-+	int8_t io_g_offset = 0;
-+	int8_t io_lat[NUM_SLOTRANKS] = { 0 };
-+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+		if (!rank_in_ch(ctrl, rank, channel))
-+			continue;
-+
-+		io_lat[rank] = iolat_target;
-+
-+		/* Check for RcvEn underflow/overflow */
-+		const int16_t rcven_lower = 64 * io_lat[rank] + min_rcven_rank[rank];
-+		if (rcven_lower < pi_reserve)
-+			io_lat[rank] += DIV_ROUND_UP(pi_reserve - rcven_lower, 64);
-+
-+		const int16_t rcven_upper = 64 * io_lat[rank] + max_rcven_rank[rank];
-+		if (rcven_upper > 511 - pi_reserve)
-+			io_lat[rank] -= DIV_ROUND_UP(rcven_upper - (511 - pi_reserve), 64);
-+
-+		/* Check for IO latency over/underflow */
-+		if (io_lat[rank] - io_g_offset > 14)
-+			io_g_offset = io_lat[rank] - 14;
-+
-+		if (io_lat[rank] - io_g_offset < 1)
-+			io_g_offset = io_lat[rank] - 1;
-+
-+		const int8_t cycle_offset = io_lat[rank] - ctrl->io_latency[channel][rank];
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			ctrl->rcven[channel][rank][byte] += 64 * cycle_offset;
-+			update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
-+		}
-+	}
-+
-+	/* Calculate new IO comp latency */
-+	union sc_io_latency_reg sc_io_lat = {
-+		.raw = mchbar_read32(SC_IO_LATENCY_ch(channel)),
-+	};
-+
-+	/* Check if we are underflowing or overflowing this field */
-+	if (io_g_offset < 0 && sc_io_lat.rt_iocomp < -io_g_offset) {
-+		printk(BIOS_ERR, "%s: IO COMP underflow\n", __func__);
-+		printk(BIOS_ERR, "io_g_offset: %d\n", io_g_offset);
-+		printk(BIOS_ERR, "rt_iocomp: %u\n", sc_io_lat.rt_iocomp);
-+		return RAMINIT_STATUS_RCVEN_FAILURE;
-+	}
-+	if (io_g_offset > 0 && io_g_offset > 0x3f - sc_io_lat.rt_iocomp) {
-+		printk(BIOS_ERR, "%s: IO COMP overflow\n", __func__);
-+		printk(BIOS_ERR, "io_g_offset: %d\n", io_g_offset);
-+		printk(BIOS_ERR, "rt_iocomp: %u\n", sc_io_lat.rt_iocomp);
-+		return RAMINIT_STATUS_RCVEN_FAILURE;
-+	}
-+	sc_io_lat.rt_iocomp += io_g_offset;
-+	ctrl->rt_io_comp[channel] = sc_io_lat.rt_iocomp;
-+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+		if (ctrl->rankmap[channel] & BIT(rank))
-+			ctrl->io_latency[channel][rank] = io_lat[rank] - io_g_offset;
-+
-+		const uint8_t shift = rank * 4;
-+		sc_io_lat.raw &= ~(0xf << shift);
-+		sc_io_lat.raw |= ctrl->io_latency[channel][rank] << shift;
-+	}
-+	mchbar_write32(SC_IO_LATENCY_ch(channel), sc_io_lat.raw);
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
-+#define RL_START (256 + 24)
-+#define RL_STOP  (384 + 24)
-+#define RL_STEP  8
-+
-+#define RE_NUM_SAMPLES	6
-+
-+static enum raminit_status verify_high_region(const int32_t center, const int32_t lwidth)
-+{
-+	if (center > RL_STOP) {
-+		/* Check if center of high was found where it should be */
-+		printk(BIOS_ERR, "RcvEn: Center of high (%d) higher than expected\n", center);
-+		return RAMINIT_STATUS_RCVEN_FAILURE;
-+	}
-+	if (lwidth <= 32) {
-+		/* Check if width is large enough */
-+		printk(BIOS_ERR, "RcvEn: Width of high region (%d) too small\n", lwidth);
-+		return RAMINIT_STATUS_RCVEN_FAILURE;
-+	}
-+	if (lwidth >= 96) {
-+		/* Since we're calibrating a phase, a too large region is a problem */
-+		printk(BIOS_ERR, "RcvEn: Width of high region (%d) too large\n", lwidth);
-+		return RAMINIT_STATUS_RCVEN_FAILURE;
-+	}
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
-+static void program_io_latency(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
-+{
-+	const uint8_t shift = rank * 4;
-+	const uint8_t iolat = ctrl->io_latency[channel][rank];
-+	mchbar_clrsetbits32(SC_IO_LATENCY_ch(channel), 0xf << shift, iolat << shift);
-+}
-+
-+static void program_rl_delays(struct sysinfo *ctrl, const uint8_t rank, const uint16_t rl_delay)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!rank_in_ch(ctrl, rank, channel))
-+			continue;
-+
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+			update_rxt(ctrl, channel, rank, byte, RXT_RCVEN, rl_delay);
-+	}
-+}
-+
-+static bool sample_dqs(const uint8_t channel, const uint8_t byte)
-+{
-+	return (get_data_train_feedback(channel, byte) & 0x1ff) >= BIT(RE_NUM_SAMPLES - 1);
-+}
-+
-+enum raminit_status train_receive_enable(struct sysinfo *ctrl)
-+{
-+	const struct reut_box reut_addr = {
-+		.col = {
-+			.start    = 0,
-+			.stop     = 1023,
-+			.inc_rate = 0,
-+			.inc_val  = 1,
-+		},
-+	};
-+	const struct wdb_pat wdb_pattern = {
-+		.start_ptr  = 0,
-+		.stop_ptr   = 9,
-+		.inc_rate   = 32,
-+		.dq_pattern = BASIC_VA,
-+	};
-+
-+	const uint16_t bytemask = BIT(ctrl->lanes) - 1;
-+	const uint8_t fine_step = 1;
-+
-+	const uint8_t rt_delta = is_hsw_ult() ? 4 : 2;
-+	const uint8_t rt_io_comp = 21 + rt_delta;
-+	const uint8_t rt_latency = 16 + rt_delta;
-+	setup_io_test(
-+		ctrl,
-+		ctrl->chanmap,
-+		PAT_RD,
-+		2,
-+		RE_NUM_SAMPLES + 1,
-+		&reut_addr,
-+		0,
-+		&wdb_pattern,
-+		0,
-+		8);
-+
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			union ddr_data_control_2_reg data_control_2 = {
-+				.raw = ctrl->dq_control_2[channel][byte],
-+			};
-+			data_control_2.force_rx_on = 1;
-+			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
-+		}
-+		union ddr_data_control_0_reg data_control_0 = {
-+			.raw = ctrl->dq_control_0[channel],
-+		};
-+		if (ctrl->lpddr) {
-+			/**
-+			 * W/A for b4618574 - @todo: remove for HSW ULT C0
-+			 * Can't have force_odt_on together with leaker, disable LPDDR
-+			 * mode during this training step. lpddr_mode is restored
-+			 * at the end of this function from the host structure.
-+			 */
-+			data_control_0.lpddr_mode = 0;
-+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+		}
-+		data_control_0.force_odt_on     = 1;
-+		data_control_0.rl_training_mode = 1;
-+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+		mchbar_write32(SC_IO_LATENCY_ch(channel), (union sc_io_latency_reg) {
-+			.rt_iocomp = rt_io_comp,
-+		}.raw);
-+	}
-+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
-+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+		if (!does_rank_exist(ctrl, rank))
-+			continue;
-+
-+		/*
-+		 * Set initial roundtrip latency values. Assume -4 QCLK for worst board
-+		 * layout. This is calculated as HW_ROUNDT_LAT_DEFAULT_VALUE plus:
-+		 *
-+		 *   DDR3: Default + (2 * tAA) + 4 QCLK + PI_CLK + N-mode value * 2
-+		 * LPDDR3: Default + (2 * tAA) + 4 QCLK + PI_CLK + tDQSCK_max
-+		 *
-+		 * N-mode is 3 during training mode. Both channels use the same timings.
-+		 */
-+		/** TODO: differs for LPDDR **/
-+		const uint32_t tmp = MAX(ctrl->multiplier, 4) + 5 + 2 * ctrl->tAA;
-+		const uint32_t initial_rt_latency = MIN(rt_latency + tmp, 0x3f);
-+
-+		uint8_t chanmask = 0;
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			ctrl->io_latency[channel][rank] = 0;
-+			mchbar_write8(SC_ROUNDT_LAT_ch(channel) + rank, initial_rt_latency);
-+			ctrl->rt_latency[channel][rank] = initial_rt_latency;
-+		}
-+
-+		printk(BIOS_DEBUG, "Rank %u\n", rank);
-+		printk(BIOS_DEBUG, "Steps 1 and 2: Find middle of high region\n");
-+		printk(RCVEN_PLOT, "Byte");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(RCVEN_PLOT, "\t");
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+				printk(RCVEN_PLOT, "%u ", byte);
-+		}
-+		printk(RCVEN_PLOT, "\nRcvEn\n");
-+		struct phase_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
-+		for (uint16_t rl_delay = RL_START; rl_delay < RL_STOP; rl_delay += RL_STEP) {
-+			printk(RCVEN_PLOT, " % 3d", rl_delay);
-+			program_rl_delays(ctrl, rank, rl_delay);
-+			run_io_test(ctrl, chanmask, BASIC_VA, true);
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				printk(RCVEN_PLOT, "\t");
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					const bool high = sample_dqs(channel, byte);
-+					printk(RCVEN_PLOT, high ? ". " : "# ");
-+					phase_record_pass(
-+						&region_data[channel][byte],
-+						high,
-+						rl_delay,
-+						RL_START,
-+						RL_STEP);
-+				}
-+			}
-+			printk(RCVEN_PLOT, "\n");
-+		}
-+		printk(RCVEN_PLOT, "\n");
-+		printk(BIOS_DEBUG, "Update RcvEn timing to be in the center of high region\n");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(BIOS_DEBUG, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\n",
-+				channel, rank);
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				struct phase_train_data *const curr_data =
-+						&region_data[channel][byte];
-+				phase_append_current_to_initial(curr_data, RL_START, RL_STEP);
-+				const int32_t lwidth = range_width(curr_data->largest);
-+				const int32_t center = range_center(curr_data->largest);
-+				printk(BIOS_DEBUG, "   B%u: \t%d\t%d\t%d\t%d\n",
-+					byte,
-+					curr_data->largest.start,
-+					curr_data->largest.end,
-+					lwidth,
-+					center);
-+
-+				status = verify_high_region(center, lwidth);
-+				if (status) {
-+					printk(BIOS_ERR,
-+						"RcvEn problems on channel %u, byte %u\n",
-+						channel, byte);
-+					goto clean_up;
-+				}
-+				ctrl->rcven[channel][rank][byte] = center;
-+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
-+			}
-+			printk(BIOS_DEBUG, "\n");
-+		}
-+
-+		printk(BIOS_DEBUG, "Step 3: Quarter preamble - Walk backwards\n");
-+		printk(RCVEN_PLOT, "Byte");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(RCVEN_PLOT, "\t");
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+				printk(RCVEN_PLOT, "%u ", byte);
-+		}
-+		printk(RCVEN_PLOT, "\nIOLAT\n");
-+		bool done = false;
-+		while (!done) {
-+			run_io_test(ctrl, chanmask, BASIC_VA, true);
-+			done = true;
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				printk(RCVEN_PLOT, "  %2u\t", ctrl->io_latency[channel][rank]);
-+				uint16_t highs = 0;
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					const bool high = sample_dqs(channel, byte);
-+					printk(RCVEN_PLOT, high ? "H " : "L ");
-+					if (high)
-+						highs |= BIT(byte);
-+				}
-+				if (!highs)
-+					continue;
-+
-+				done = false;
-+
-+				/* If all bytes sample high, adjust timing globally */
-+				if (highs == bytemask && ctrl->io_latency[channel][rank] < 14) {
-+					ctrl->io_latency[channel][rank] += 2;
-+					ctrl->io_latency[channel][rank] %= 16;
-+					program_io_latency(ctrl, channel, rank);
-+					continue;
-+				}
-+
-+				/* Otherwise, adjust individual bytes */
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					if (!(highs & BIT(byte)))
-+						continue;
-+
-+					if (ctrl->rcven[channel][rank][byte] < 128) {
-+						printk(BIOS_ERR,
-+							"RcvEn underflow: walking backwards\n");
-+						printk(BIOS_ERR,
-+							"For channel %u, rank %u, byte %u\n",
-+							channel, rank, byte);
-+						status = RAMINIT_STATUS_RCVEN_FAILURE;
-+						goto clean_up;
-+					}
-+					ctrl->rcven[channel][rank][byte] -= 128;
-+					update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
-+				}
-+			}
-+			printk(RCVEN_PLOT, "\n");
-+		}
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(BIOS_DEBUG, "\nC%u:  Preamble\n", channel);
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				printk(BIOS_DEBUG,
-+					" B%u: %u\n", byte, ctrl->rcven[channel][rank][byte]);
-+			}
-+		}
-+		printk(BIOS_DEBUG, "\n");
-+
-+		printk(BIOS_DEBUG, "Step 4: Add 1 qclk\n");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				ctrl->rcven[channel][rank][byte] += 64;
-+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
-+			}
-+		}
-+		printk(BIOS_DEBUG, "\n");
-+
-+		printk(BIOS_DEBUG, "Step 5: Walk forward to find rising edge\n");
-+		printk(RCVEN_PLOT, "Byte");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(RCVEN_PLOT, "\t");
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+				printk(RCVEN_PLOT, "%u ", byte);
-+		}
-+		printk(RCVEN_PLOT, "\n inc\n");
-+		uint16_t ch_result[NUM_CHANNELS] = { 0 };
-+		uint8_t inc_preamble[NUM_CHANNELS][NUM_LANES] = { 0 };
-+		for (uint8_t inc = 0; inc < 64; inc += fine_step) {
-+			printk(RCVEN_PLOT, " %2u\t", inc);
-+			run_io_test(ctrl, chanmask, BASIC_VA, true);
-+			done = true;
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					if (ch_result[channel] & BIT(byte)) {
-+						/* Skip bytes that are already done */
-+						printk(RCVEN_PLOT, ". ");
-+						continue;
-+					}
-+					const bool pass = sample_dqs(channel, byte);
-+					printk(RCVEN_PLOT, pass ? ". " : "# ");
-+					if (pass) {
-+						ch_result[channel] |= BIT(byte);
-+						continue;
-+					}
-+					ctrl->rcven[channel][rank][byte] += fine_step;
-+					update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
-+					inc_preamble[channel][byte] = inc;
-+				}
-+				printk(RCVEN_PLOT, "\t");
-+				if (ch_result[channel] != bytemask)
-+					done = false;
-+			}
-+			printk(RCVEN_PLOT, "\n");
-+			if (done)
-+				break;
-+		}
-+		printk(BIOS_DEBUG, "\n");
-+		if (!done) {
-+			printk(BIOS_ERR, "Error: Preamble edge not found for all bytes\n");
-+			printk(BIOS_ERR, "The final RcvEn results are as follows:\n");
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				printk(BIOS_ERR, "Channel %u Rank %u:  preamble\n",
-+					channel, rank);
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					printk(BIOS_ERR, " Byte %u: %u%s\n", byte,
-+						ctrl->rcven[channel][rank][byte],
-+						(ch_result[channel] ^ bytemask) & BIT(byte)
-+							? ""
-+							: " *** Check this byte! ***");
-+				}
-+			}
-+			status = RAMINIT_STATUS_RCVEN_FAILURE;
-+			goto clean_up;
-+		}
-+
-+		printk(BIOS_DEBUG, "Step 6: center on preamble and clean up rank\n");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(BIOS_DEBUG, "C%u:  Preamble increment\n", channel);
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				/*
-+				 * For Traditional, pull in RcvEn by 64. For ULT, take the DQS
-+				 * drift into account to the specified guardband: tDQSCK_DRIFT.
-+				 */
-+				ctrl->rcven[channel][rank][byte] -= tDQSCK_DRIFT;
-+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
-+				printk(BIOS_DEBUG, " B%u: %u      %u\n", byte,
-+					ctrl->rcven[channel][rank][byte],
-+					inc_preamble[channel][byte]);
-+			}
-+			printk(BIOS_DEBUG, "\n");
-+		}
-+		printk(BIOS_DEBUG, "\n");
-+	}
-+
-+clean_up:
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		if (ctrl->lpddr) {
-+			/**
-+			 * W/A for b4618574 - @todo: remove for HSW ULT C0
-+			 * Can't have force_odt_on together with leaker, disable LPDDR mode for
-+			 * this training step. This write will disable force_odt_on while still
-+			 * keeping LPDDR mode disabled. Second write will restore LPDDR mode.
-+			 */
-+			union ddr_data_control_0_reg data_control_0 = {
-+				.raw = ctrl->dq_control_0[channel],
-+			};
-+			data_control_0.lpddr_mode = 0;
-+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+		}
-+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			mchbar_write32(DQ_CONTROL_2(channel, byte),
-+					ctrl->dq_control_2[channel][byte]);
-+		}
-+	}
-+	io_reset();
-+	if (status)
-+		return status;
-+
-+	printk(BIOS_DEBUG, "Step 7: Sync IO latency across all ranks\n");
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		status = change_rcven_timing(ctrl, channel);
-+		if (status)
-+			return status;
-+	}
-+	printk(BIOS_DEBUG, "\nFinal Receive Enable and IO latency settings:\n");
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			const union sc_io_latency_reg sc_io_latency = {
-+				.raw = mchbar_read32(SC_IO_LATENCY_ch(channel)),
-+			};
-+			printk(BIOS_DEBUG, "  C%u.R%u: IOLAT = %u  rt_iocomp = %u\n", channel,
-+				rank, ctrl->io_latency[channel][rank], sc_io_latency.rt_iocomp);
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				printk(BIOS_DEBUG, "   B%u:   %u\n", byte,
-+					ctrl->rcven[channel][rank][byte]);
-+			}
-+			printk(BIOS_DEBUG, "\n");
-+		}
-+	}
-+	return status;
-+}
-diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
-index a81559bb1e..9172d4f2b0 100644
---- a/src/northbridge/intel/haswell/registers/mchbar.h
-+++ b/src/northbridge/intel/haswell/registers/mchbar.h
-@@ -18,6 +18,8 @@
- #define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
- #define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
- 
-+#define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
-+
- #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
- #define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
- 
-@@ -100,6 +102,7 @@
- #define COMMAND_RATE_LIMIT_ch(ch)		_MCMAIN_C(0x4010, ch)
- #define TC_BANK_RANK_D_ch(ch)			_MCMAIN_C(0x4014, ch)
- #define SC_ROUNDT_LAT_ch(ch)			_MCMAIN_C(0x4024, ch)
-+#define SC_IO_LATENCY_ch(ch)			_MCMAIN_C(0x4028, ch)
- 
- #define REUT_ch_PAT_WDB_CL_MUX_CFG(ch)		_MCMAIN_C(0x4040, ch)
- 
--- 
-2.39.2
-

config/coreboot/haswell/patches/0022-haswell-NRI-Add-function-to-change-margins.patch

@@ -1,272 +0,0 @@
-From 8c3874195c0fc1af9d0b84611496689da1c19d8c Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sun, 8 May 2022 11:58:59 +0200
-Subject: [PATCH 22/26] haswell NRI: Add function to change margins
-
-Implement a function to change margin parameters. Haswell provides a
-register to apply an offset to margin parameters during training, so
-make use of it. There are other margin parameters that have not been
-implemented yet, as they are not needed for now and special handling
-is needed to provide offset training functionality.
-
-Change-Id: I5392380e13de3c44e77b7bc9f3b819e2661d1e2d
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../haswell/native_raminit/change_margin.c    | 136 ++++++++++++++++++
- .../haswell/native_raminit/raminit_native.h   |  39 +++++
- .../haswell/native_raminit/reg_structs.h      |  12 ++
- .../intel/haswell/registers/mchbar.h          |   1 +
- 4 files changed, 188 insertions(+)
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
-index 12da59580f..4ba9cfa5c6 100644
---- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
-+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
-@@ -1,5 +1,6 @@
- /* SPDX-License-Identifier: GPL-2.0-or-later */
- 
-+#include <assert.h>
- #include <commonlib/clamp.h>
- #include <console/console.h>
- #include <delay.h>
-@@ -152,3 +153,138 @@ void download_regfile(
- 	ddr_data_control_0.read_rf_rank = phys_rank;
- 	mchbar_write32(reg, ddr_data_control_0.raw);
- }
-+
-+static void update_data_offset_train(
-+	struct sysinfo *ctrl,
-+	const uint8_t param,
-+	const uint8_t en_multicast,
-+	const uint8_t channel_in,
-+	const uint8_t rank,
-+	const uint8_t byte_in,
-+	const bool update_ctrl,
-+	const enum regfile_mode regfile,
-+	const uint32_t value)
-+{
-+	bool is_rd = false;
-+	bool is_wr = false;
-+	switch (param) {
-+	case RdT:
-+	case RdV:
-+	case RcvEna:
-+		is_rd = true;
-+		break;
-+	case WrT:
-+	case WrDqsT:
-+		is_wr = true;
-+		break;
-+	default:
-+		die("%s: Invalid margin parameter %u\n", __func__, param);
-+	}
-+	if (en_multicast) {
-+		mchbar_write32(DDR_DATA_OFFSET_TRAIN, value);
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!does_ch_exist(ctrl, channel))
-+				continue;
-+
-+			download_regfile(ctrl, channel, true, rank, regfile, 0, is_rd, is_wr);
-+			if (update_ctrl) {
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+					ctrl->data_offset_train[channel][byte] = value;
-+			}
-+		}
-+	} else {
-+		mchbar_write32(DDR_DATA_OFFSET_TRAIN_ch_b(channel_in, byte_in), value);
-+		download_regfile(ctrl, channel_in, false, rank, regfile, byte_in, is_rd, is_wr);
-+		if (update_ctrl)
-+			ctrl->data_offset_train[channel_in][byte_in] = value;
-+	}
-+}
-+
-+static uint32_t get_max_margin(const enum margin_parameter param)
-+{
-+	switch (param) {
-+	case RcvEna:
-+	case RdT:
-+	case WrT:
-+	case WrDqsT:
-+		return MAX_POSSIBLE_TIME;
-+	case RdV:
-+		return MAX_POSSIBLE_VREF;
-+	default:
-+		die("%s: Invalid margin parameter %u\n", __func__, param);
-+	}
-+}
-+
-+void change_margin(
-+	struct sysinfo *ctrl,
-+	const enum margin_parameter param,
-+	const int32_t value0,
-+	const bool en_multicast,
-+	const uint8_t channel,
-+	const uint8_t rank,
-+	const uint8_t byte,
-+	const bool update_ctrl,
-+	const enum regfile_mode regfile)
-+{
-+	/** FIXME: Remove this **/
-+	if (rank == 0xff)
-+		die("%s: rank is 0xff\n", __func__);
-+
-+	if (!en_multicast && !does_ch_exist(ctrl, channel))
-+		die("%s: Tried to change margin of empty channel %u\n", __func__, channel);
-+
-+	const uint32_t max_value = get_max_margin(param);
-+	const int32_t v0 = clamp_s32(-max_value, value0, max_value);
-+
-+	union ddr_data_offset_train_reg ddr_data_offset_train = {
-+		.raw = en_multicast ? 0 : ctrl->data_offset_train[channel][byte],
-+	};
-+	bool update_offset_train = false;
-+	switch (param) {
-+	case RcvEna:
-+		ddr_data_offset_train.rcven = v0;
-+		update_offset_train = true;
-+		break;
-+	case RdT:
-+		ddr_data_offset_train.rx_dqs = v0;
-+		update_offset_train = true;
-+		break;
-+	case WrT:
-+		ddr_data_offset_train.tx_dq = v0;
-+		update_offset_train = true;
-+		break;
-+	case WrDqsT:
-+		ddr_data_offset_train.tx_dqs = v0;
-+		update_offset_train = true;
-+		break;
-+	case RdV:
-+		ddr_data_offset_train.vref = v0;
-+		update_offset_train = true;
-+		break;
-+	default:
-+		die("%s: Invalid margin parameter %u\n", __func__, param);
-+	}
-+	if (update_offset_train) {
-+		update_data_offset_train(
-+			ctrl,
-+			param,
-+			en_multicast,
-+			channel,
-+			rank,
-+			byte,
-+			update_ctrl,
-+			regfile,
-+			ddr_data_offset_train.raw);
-+	}
-+}
-+
-+void change_1d_margin_multicast(
-+	struct sysinfo *ctrl,
-+	const enum margin_parameter param,
-+	const int32_t value0,
-+	const uint8_t rank,
-+	const bool update_ctrl,
-+	const enum regfile_mode regfile)
-+{
-+	change_margin(ctrl, param, value0, true, 0, rank, 0, update_ctrl, regfile);
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index a36ebfacd1..500fc28909 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -35,6 +35,18 @@
- 
- #define RTTNOM_MASK		(BIT(9) | BIT(6) | BIT(2))
- 
-+/* Margin parameter limits */
-+#define MAX_POSSIBLE_TIME	31
-+#define MAX_POSSIBLE_VREF	54
-+
-+#define MAX_POSSIBLE_BOTH	MAX_POSSIBLE_VREF
-+
-+#define MIN_TIME		(-MAX_POSSIBLE_TIME)
-+#define MAX_TIME		(MAX_POSSIBLE_TIME)
-+
-+#define MIN_VREF		(-MAX_POSSIBLE_VREF)
-+#define MAX_VREF		(MAX_POSSIBLE_VREF)
-+
- #define BASIC_VA_PAT_SPREAD_8	0x01010101
- 
- #define WDB_CACHE_LINE_SIZE	8
-@@ -45,6 +57,14 @@
- /* Specified in PI ticks. 64 PI ticks == 1 qclk */
- #define tDQSCK_DRIFT		64
- 
-+enum margin_parameter {
-+	RcvEna,
-+	RdT,
-+	WrT,
-+	WrDqsT,
-+	RdV,
-+};
-+
- /* ZQ calibration types */
- enum {
- 	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
-@@ -516,6 +536,25 @@ void download_regfile(
- 	bool read_rf_rd,
- 	bool read_rf_wr);
- 
-+void change_margin(
-+	struct sysinfo *ctrl,
-+	const enum margin_parameter param,
-+	const int32_t value0,
-+	const bool en_multicast,
-+	const uint8_t channel,
-+	const uint8_t rank,
-+	const uint8_t byte,
-+	const bool update_ctrl,
-+	const enum regfile_mode regfile);
-+
-+void change_1d_margin_multicast(
-+	struct sysinfo *ctrl,
-+	const enum margin_parameter param,
-+	const int32_t value0,
-+	const uint8_t rank,
-+	const bool update_ctrl,
-+	const enum regfile_mode regfile);
-+
- uint8_t get_rx_bias(const struct sysinfo *ctrl);
- 
- uint8_t get_tCWL(uint32_t mem_clock_mhz);
-diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-index b099f4bb82..a0e36ed082 100644
---- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-@@ -25,6 +25,18 @@ union ddr_data_tx_train_rank_reg {
- 	uint32_t raw;
- };
- 
-+union ddr_data_offset_train_reg {
-+	struct __packed {
-+		int32_t rcven  : 6; // Bits  5:0
-+		int32_t rx_dqs : 6; // Bits 11:6
-+		int32_t tx_dq  : 6; // Bits 17:12
-+		int32_t tx_dqs : 6; // Bits 23:18
-+		int32_t vref   : 7; // Bits 30:24
-+		int32_t        : 1; // Bits 31:31
-+	};
-+	uint32_t raw;
-+};
-+
- union ddr_data_control_0_reg {
- 	struct __packed {
- 		uint32_t rx_training_mode      : 1; // Bits  0:0
-diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
-index 9172d4f2b0..0acafbc826 100644
---- a/src/northbridge/intel/haswell/registers/mchbar.h
-+++ b/src/northbridge/intel/haswell/registers/mchbar.h
-@@ -21,6 +21,7 @@
- #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
- 
- #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
-+#define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte)	_DDRIO_C_R_B(0x0070, ch, 0, byte)
- #define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
- 
- /* DDR CKE per-channel */
--- 
-2.39.2
-

config/coreboot/haswell/patches/0023-haswell-NRI-Add-read-MPR-training.patch

@@ -1,331 +0,0 @@
-From 6781cec818501f7afd6ee26464fd4556ac3068cb Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sun, 8 May 2022 11:35:49 +0200
-Subject: [PATCH 23/26] haswell NRI: Add read MPR training
-
-Implement read training using DDR3 MPR (Multi-Purpose Register).
-
-Change-Id: Id17cb2c4c399ac9bcc937b595b58f863c152461b
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/raminit_main.c     |   1 +
- .../haswell/native_raminit/raminit_native.h   |   4 +
- .../haswell/native_raminit/train_read_mpr.c   | 240 ++++++++++++++++++
- .../intel/haswell/registers/mchbar.h          |   2 +-
- 5 files changed, 247 insertions(+), 1 deletion(-)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index e2fbfb4211..c442be0728 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -16,4 +16,5 @@ romstage-y += setup_wdb.c
- romstage-y += spd_bitmunching.c
- romstage-y += testing_io.c
- romstage-y += timings_refresh.c
-+romstage-y += train_read_mpr.c
- romstage-y += train_receive_enable.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 7d444659c3..264d1468f5 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -61,6 +61,7 @@ static const struct task_entry cold_boot[] = {
- 	{ do_jedec_init,                                          true, "JEDECINIT",  },
- 	{ pre_training,                                           true, "PRETRAIN",   },
- 	{ train_receive_enable,                                   true, "RCVET",      },
-+	{ train_read_mpr,                                         true, "RDMPRT",     },
- };
- 
- /* Return a generic stepping value to make stepping checks simpler */
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 500fc28909..a7551ad63c 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -27,6 +27,8 @@
- /* Always use 12 legs for emphasis (not trained) */
- #define TXEQFULLDRV		(3 << 4)
- 
-+#define LOOPCOUNT_INFINITE	0xff
-+
- /* DDR3 mode register bits */
- #define MR0_DLL_RESET		BIT(8)
- 
-@@ -212,6 +214,7 @@ enum raminit_status {
- 	RAMINIT_STATUS_POLL_TIMEOUT,
- 	RAMINIT_STATUS_REUT_ERROR,
- 	RAMINIT_STATUS_RCVEN_FAILURE,
-+	RAMINIT_STATUS_RMPR_FAILURE,
- 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
- };
- 
-@@ -435,6 +438,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
- enum raminit_status configure_memory_map(struct sysinfo *ctrl);
- enum raminit_status do_jedec_init(struct sysinfo *ctrl);
- enum raminit_status train_receive_enable(struct sysinfo *ctrl);
-+enum raminit_status train_read_mpr(struct sysinfo *ctrl);
- 
- void configure_timings(struct sysinfo *ctrl);
- void configure_refresh(struct sysinfo *ctrl);
-diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
-new file mode 100644
-index 0000000000..0225e1a384
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
-@@ -0,0 +1,240 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <commonlib/clamp.h>
-+#include <console/console.h>
-+#include <delay.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+#include "ranges.h"
-+
-+#define RMPR_START	(-32)
-+#define RMPR_STOP	(32)
-+#define RMPR_STEP	1
-+
-+#define RMPR_MIN_WIDTH	12
-+
-+#define RMPR_PLOT	RAM_DEBUG
-+
-+/*
-+ * Clear rx_training_mode. For LPDDR, we first need to disable odt_samp_extend_en,
-+ * then disable rx_training_mode, and finally re-enable odt_samp_extend_en.
-+ */
-+static void clear_rx_training_mode(struct sysinfo *ctrl, const uint8_t channel)
-+{
-+	for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+		mchbar_write32(DQ_CONTROL_2(channel, byte), ctrl->dq_control_2[channel][byte]);
-+
-+	if (ctrl->lpddr) {
-+		union ddr_data_control_0_reg data_control_0 = {
-+			.raw = mchbar_read32(DDR_DATA_ch_CONTROL_0(channel)),
-+		};
-+		data_control_0.odt_samp_extend_en = 0;
-+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+		tick_delay(1);
-+		data_control_0.rx_training_mode = 0;
-+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+		tick_delay(1);
-+	}
-+	mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
-+}
-+
-+static void set_rxdqs_edges_to_midpoint(struct sysinfo *ctrl)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+				update_rxt(ctrl, channel, rank, byte, RXT_RXDQS_BOTH, 32);
-+		}
-+	}
-+}
-+
-+static void enter_mpr_train_ddr_mode(struct sysinfo *ctrl, const uint8_t rank)
-+{
-+	/* Program MR3 and mask RAS/WE to prevent scheduler from issuing non-read commands */
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!rank_in_ch(ctrl, rank, channel))
-+			continue;
-+
-+		if (!ctrl->lpddr)
-+			reut_issue_mrs(ctrl, channel, BIT(rank), 3, 1 << 2);
-+
-+		union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
-+			.raw = mchbar_read32(REUT_ch_MISC_ODT_CTRL(channel)),
-+		};
-+		reut_misc_odt_ctrl.mpr_train_ddr_on = 1;
-+		mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
-+	}
-+}
-+
-+static void leave_mpr_train_ddr_mode(struct sysinfo *ctrl, const uint8_t rank)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!rank_in_ch(ctrl, rank, channel))
-+			continue;
-+
-+		/*
-+		 * The mpr_train_ddr_on bit will force a special command.
-+		 * Therefore, clear it before issuing the MRS command.
-+		 */
-+		union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
-+			.raw = mchbar_read32(REUT_ch_MISC_ODT_CTRL(channel)),
-+		};
-+		reut_misc_odt_ctrl.mpr_train_ddr_on = 0;
-+		mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
-+		if (!ctrl->lpddr)
-+			reut_issue_mrs(ctrl, channel, BIT(rank), 3, 0 << 2);
-+	}
-+}
-+
-+enum raminit_status train_read_mpr(struct sysinfo *ctrl)
-+{
-+	set_rxdqs_edges_to_midpoint(ctrl);
-+	clear_data_offset_train_all(ctrl);
-+	setup_io_test_mpr(ctrl, ctrl->chanmap, LOOPCOUNT_INFINITE, NSOE);
-+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
-+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+		if (!does_rank_exist(ctrl, rank))
-+			continue;
-+
-+		printk(BIOS_DEBUG, "Rank %u\n", rank);
-+		printk(RMPR_PLOT, "Channel");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(RMPR_PLOT, "\t%u\t\t", channel);
-+		}
-+		printk(RMPR_PLOT, "\nByte");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(RMPR_PLOT, "\t");
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+				printk(RMPR_PLOT, "%u ", byte);
-+		}
-+		enter_mpr_train_ddr_mode(ctrl, rank);
-+		struct linear_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
-+			select_reut_ranks(ctrl, channel, BIT(rank));
-+
-+		printk(RMPR_PLOT, "\nDqsDelay\n");
-+		int8_t dqs_delay;
-+		for (dqs_delay = RMPR_START; dqs_delay < RMPR_STOP; dqs_delay += RMPR_STEP) {
-+			printk(RMPR_PLOT, "% 5d", dqs_delay);
-+			const enum regfile_mode regfile = REG_FILE_USE_START;
-+			change_1d_margin_multicast(ctrl, RdT, dqs_delay, 0, false, regfile);
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					union ddr_data_control_2_reg data_control_2 = {
-+						.raw = ctrl->dq_control_2[channel][byte],
-+					};
-+					data_control_2.force_bias_on = 1;
-+					data_control_2.force_rx_on   = 1;
-+					data_control_2.leaker_comp   = 0;
-+					mchbar_write32(DQ_CONTROL_2(channel, byte),
-+						data_control_2.raw);
-+				}
-+				union ddr_data_control_0_reg data_control_0 = {
-+					.raw = ctrl->dq_control_0[channel],
-+				};
-+				data_control_0.rx_training_mode   = 1;
-+				data_control_0.force_odt_on       = !ctrl->lpddr;
-+				data_control_0.en_read_preamble   = 0;
-+				data_control_0.odt_samp_extend_en = ctrl->lpddr;
-+				const uint32_t reg_offset = DDR_DATA_ch_CONTROL_0(channel);
-+				mchbar_write32(reg_offset, data_control_0.raw);
-+			}
-+			run_mpr_io_test(false);
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				printk(RMPR_PLOT, "\t");
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					uint32_t fb = get_data_train_feedback(channel, byte);
-+					const bool pass = fb == 1;
-+					printk(RMPR_PLOT, pass ? ". " : "# ");
-+					linear_record_pass(
-+						&region_data[channel][byte],
-+						pass,
-+						dqs_delay,
-+						RMPR_START,
-+						RMPR_STEP);
-+				}
-+			}
-+			printk(RMPR_PLOT, "\n");
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				clear_rx_training_mode(ctrl, channel);
-+			}
-+			io_reset();
-+		}
-+		printk(RMPR_PLOT, "\n");
-+		leave_mpr_train_ddr_mode(ctrl, rank);
-+		clear_data_offset_train_all(ctrl);
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(BIOS_DEBUG, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\tRxDqsPN\n",
-+				channel, rank);
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				struct linear_train_data *data = &region_data[channel][byte];
-+				const int32_t lwidth = range_width(data->largest);
-+				if (lwidth <= RMPR_MIN_WIDTH) {
-+					printk(BIOS_ERR,
-+						"Bad eye (lwidth %d <= min %d) for byte %u\n",
-+						lwidth, RMPR_MIN_WIDTH, byte);
-+					status = RAMINIT_STATUS_RMPR_FAILURE;
-+				}
-+				/*
-+				 * The MPR center may not be ideal on certain platforms for
-+				 * unknown reasons. If so, adjust it with a magical number.
-+				 * For Haswell, the magical number is zero. Hell knows why.
-+				 */
-+				const int32_t center = range_center(data->largest);
-+				ctrl->rxdqsp[channel][rank][byte] = center - RMPR_START;
-+				ctrl->rxdqsn[channel][rank][byte] = center - RMPR_START;
-+				printk(BIOS_DEBUG, "  B%u: \t%d\t%d\t%d\t%d\t%u\n", byte,
-+					data->largest.start, data->largest.end, lwidth,
-+					center, ctrl->rxdqsp[channel][rank][byte]);
-+			}
-+			printk(BIOS_DEBUG, "\n");
-+		}
-+	}
-+
-+	/*
-+	 * Now program the DQS center values on populated ranks. data is taken from
-+	 * the host struct. We need to do it after all ranks are trained, because we
-+	 * need to keep the same DQS value on all ranks during the training procedure.
-+	 */
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
-+		}
-+	}
-+	change_1d_margin_multicast(ctrl, RdT, 0, 0, false, REG_FILE_USE_CURRENT);
-+	io_reset();
-+	return status;
-+}
-diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
-index 0acafbc826..6a31d3a32c 100644
---- a/src/northbridge/intel/haswell/registers/mchbar.h
-+++ b/src/northbridge/intel/haswell/registers/mchbar.h
-@@ -122,7 +122,7 @@
- #define REUT_ch_ERR_DATA_MASK(ch)		_MCMAIN_C(0x40d8, ch)
- 
- #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
--
-+#define REUT_ch_MISC_ODT_CTRL(ch)		_MCMAIN_C(0x4194, ch)
- #define REUT_ch_MISC_PAT_CADB_CTRL(ch)		_MCMAIN_C(0x4198, ch)
- #define REUT_ch_PAT_CADB_MRS(ch)		_MCMAIN_C(0x419c, ch)
- #define REUT_ch_PAT_CADB_MUX_CTRL(ch)		_MCMAIN_C(0x41a0, ch)
--- 
-2.39.2
-

config/coreboot/haswell/patches/0024-haswell-NRI-Add-write-leveling.patch

@@ -1,688 +0,0 @@
-From 20fe4fa852d3e13851a01b51dc984ec5976c864e Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sun, 8 May 2022 12:56:04 +0200
-Subject: [PATCH 24/26] haswell NRI: Add write leveling
-
-Implement JEDEC write leveling, which is done in two steps. The first
-step uses the JEDEC procedure to do "fine" write leveling, i.e. align
-the DQS phase to the clock signal. The second step performs a regular
-read-write test to correct "coarse" cycle errors.
-
-Change-Id: I27678523fe22c38173a688e2a4751c259a20f009
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/raminit_main.c     |   1 +
- .../haswell/native_raminit/raminit_native.h   |  10 +
- .../train_jedec_write_leveling.c              | 580 ++++++++++++++++++
- .../intel/haswell/registers/mchbar.h          |   2 +
- 5 files changed, 594 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index c442be0728..40c2f5e014 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -16,5 +16,6 @@ romstage-y += setup_wdb.c
- romstage-y += spd_bitmunching.c
- romstage-y += testing_io.c
- romstage-y += timings_refresh.c
-+romstage-y += train_jedec_write_leveling.c
- romstage-y += train_read_mpr.c
- romstage-y += train_receive_enable.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 264d1468f5..1ff23be615 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -62,6 +62,7 @@ static const struct task_entry cold_boot[] = {
- 	{ pre_training,                                           true, "PRETRAIN",   },
- 	{ train_receive_enable,                                   true, "RCVET",      },
- 	{ train_read_mpr,                                         true, "RDMPRT",     },
-+	{ train_jedec_write_leveling,                             true, "JWRL",       },
- };
- 
- /* Return a generic stepping value to make stepping checks simpler */
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index a7551ad63c..666b233c45 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -59,6 +59,9 @@
- /* Specified in PI ticks. 64 PI ticks == 1 qclk */
- #define tDQSCK_DRIFT		64
- 
-+/* Maximum additional latency */
-+#define MAX_ADD_DELAY		2
-+
- enum margin_parameter {
- 	RcvEna,
- 	RdT,
-@@ -215,6 +218,7 @@ enum raminit_status {
- 	RAMINIT_STATUS_REUT_ERROR,
- 	RAMINIT_STATUS_RCVEN_FAILURE,
- 	RAMINIT_STATUS_RMPR_FAILURE,
-+	RAMINIT_STATUS_JWRL_FAILURE,
- 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
- };
- 
-@@ -380,6 +384,11 @@ static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint
- 	return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte));
- }
- 
-+static inline uint16_t get_byte_group_errors(const uint8_t channel)
-+{
-+	return mchbar_read32(4 + REUT_ch_ERR_MISC_STATUS(channel)) & 0x1ff;
-+}
-+
- /* Number of ticks to wait in units of 69.841279 ns (citation needed) */
- static inline void tick_delay(const uint32_t delay)
- {
-@@ -439,6 +448,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
- enum raminit_status do_jedec_init(struct sysinfo *ctrl);
- enum raminit_status train_receive_enable(struct sysinfo *ctrl);
- enum raminit_status train_read_mpr(struct sysinfo *ctrl);
-+enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
- 
- void configure_timings(struct sysinfo *ctrl);
- void configure_refresh(struct sysinfo *ctrl);
-diff --git a/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
-new file mode 100644
-index 0000000000..1ba28a3bd4
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
-@@ -0,0 +1,580 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <assert.h>
-+#include <console/console.h>
-+#include <delay.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+#include "ranges.h"
-+
-+#define JWLC_PLOT	RAM_DEBUG
-+#define JWRL_PLOT	RAM_DEBUG
-+
-+static void reset_dram_dll(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
-+{
-+	reut_issue_mrs(ctrl, channel, BIT(rank), 0, ctrl->mr0[channel][rank] | MR0_DLL_RESET);
-+}
-+
-+static void program_wdb_pattern(struct sysinfo *ctrl, const bool invert)
-+{
-+	/* Pattern to keep DQ-DQS simple but detect any failures. Same as NHM/WSM. */
-+	const uint8_t pat[4][2] = {
-+		{ 0x00, 0xff },
-+		{ 0xff, 0x00 },
-+		{ 0xc3, 0x3c },
-+		{ 0x3c, 0xc3 },
-+	};
-+	const uint8_t pmask[2][8] = {
-+		{ 0, 0, 1, 1, 1, 1, 0, 0 },
-+		{ 1, 1, 0, 0, 0, 0, 1, 1 },
-+	};
-+	for (uint8_t s = 0; s < ARRAY_SIZE(pat); s++)
-+		write_wdb_fixed_pat(ctrl, pat[s], pmask[invert], ARRAY_SIZE(pmask[invert]), s);
-+}
-+
-+static int16_t set_add_delay(uint32_t *add_delay, uint8_t rank, int8_t target_off)
-+{
-+	const uint8_t shift = rank * 2;
-+	if (target_off > MAX_ADD_DELAY) {
-+		*add_delay &= ~(3 << shift);
-+		*add_delay |= MAX_ADD_DELAY << shift;
-+		return 128 * (target_off - MAX_ADD_DELAY);
-+	} else if (target_off < 0) {
-+		*add_delay &= ~(3 << shift);
-+		*add_delay |= 0 << shift;
-+		return 128 * target_off;
-+	} else {
-+		*add_delay &= ~(3 << shift);
-+		*add_delay |= target_off << shift;
-+		return 0;
-+	}
-+}
-+
-+static enum raminit_status train_jedec_write_leveling_cleanup(struct sysinfo *ctrl)
-+{
-+	const struct reut_box reut_addr = {
-+		.col = {
-+			.start   = 0,
-+			.stop    = 1023,
-+			.inc_val = 1,
-+		},
-+	};
-+	const struct wdb_pat wdb_pattern = {
-+		.start_ptr  = 0,
-+		.stop_ptr   = 3,
-+		.inc_rate   = 1,
-+		.dq_pattern = BASIC_VA,
-+	};
-+	const int8_t offsets[] = { 0, 1, -1, 2, 3 };
-+	const int8_t dq_offsets[] = { 0, -10, 10, -5, 5, -15, 15 };
-+	const uint8_t dq_offset_max = ARRAY_SIZE(dq_offsets);
-+
-+	/* Set LFSR seeds to be sequential */
-+	program_wdb_lfsr(ctrl, true);
-+	setup_io_test(
-+		ctrl,
-+		ctrl->chanmap,
-+		PAT_WR_RD,
-+		2,
-+		4,
-+		&reut_addr,
-+		NSOE,
-+		&wdb_pattern,
-+		0,
-+		0);
-+
-+	const union reut_pat_wdb_cl_mux_cfg_reg reut_wdb_cl_mux_cfg = {
-+		.mux_0_control       = REUT_MUX_BTBUFFER,
-+		.mux_1_control       = REUT_MUX_BTBUFFER,
-+		.mux_2_control       = REUT_MUX_BTBUFFER,
-+		.ecc_data_source_sel = 1,
-+	};
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_CFG(channel), reut_wdb_cl_mux_cfg.raw);
-+	}
-+
-+	int8_t byte_off[NUM_CHANNELS][NUM_LANES] = { 0 };
-+	uint32_t add_delay[NUM_CHANNELS] = { 0 };
-+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
-+	bool invert = false;
-+	const uint16_t valid_byte_mask = BIT(ctrl->lanes) - 1;
-+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+		uint8_t chanmask = 0;
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
-+			chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
-+
-+		if (!chanmask)
-+			continue;
-+
-+		printk(BIOS_DEBUG, "Rank %u\n", rank);
-+		printk(JWLC_PLOT, "Channel");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(JWLC_PLOT, "\t\t%u\t", channel);
-+		}
-+		printk(JWLC_PLOT, "\nByte\t");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(JWLC_PLOT, "\t");
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+				printk(JWLC_PLOT, "%u ", byte);
-+		}
-+		printk(JWLC_PLOT, "\nDelay DqOffset");
-+		bool done = false;
-+		int8_t byte_sum[NUM_CHANNELS] = { 0 };
-+		uint16_t byte_pass[NUM_CHANNELS] = { 0 };
-+		for (uint8_t off = 0; off < ARRAY_SIZE(offsets); off++) {
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				const int16_t global_byte_off =
-+					set_add_delay(&add_delay[channel], rank, offsets[off]);
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					update_txt(ctrl, channel, rank, byte, TXT_DQDQS_OFF,
-+						global_byte_off);
-+				}
-+				mchbar_write32(SC_WR_ADD_DELAY_ch(channel),
-+						add_delay[channel]);
-+			}
-+			/* Reset FIFOs and DRAM DLL (Micron workaround) */
-+			if (!ctrl->lpddr) {
-+				io_reset();
-+				for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+					if (!rank_in_ch(ctrl, rank, channel))
-+						continue;
-+
-+					reset_dram_dll(ctrl, channel, rank);
-+				}
-+				udelay(1);
-+			}
-+			for (uint8_t dq_offset = 0; dq_offset < dq_offset_max; dq_offset++) {
-+				printk(JWLC_PLOT, "\n% 3d\t% 3d",
-+					offsets[off], dq_offsets[dq_offset]);
-+				change_1d_margin_multicast(
-+					ctrl,
-+					WrT,
-+					dq_offsets[dq_offset],
-+					rank,
-+					false,
-+					REG_FILE_USE_RANK);
-+
-+				/*
-+				 * Re-program the WDB pattern. Change the pattern
-+				 * for the next test to avoid false pass issues.
-+				 */
-+				program_wdb_pattern(ctrl, invert);
-+				invert = !invert;
-+				run_io_test(ctrl, chanmask, BASIC_VA, true);
-+				done = true;
-+				for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+					if (!rank_in_ch(ctrl, rank, channel))
-+						continue;
-+
-+					printk(JWLC_PLOT, "\t");
-+					uint16_t result = get_byte_group_errors(channel);
-+					result &= valid_byte_mask;
-+
-+					/* Skip bytes that have failed or already passed */
-+					const uint16_t skip_me = result | byte_pass[channel];
-+					for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+						const bool pass = result & BIT(byte);
-+						printk(JWLC_PLOT, pass ? "# " : ". ");
-+						if (skip_me & BIT(byte))
-+							continue;
-+
-+						byte_pass[channel] |= BIT(byte);
-+						byte_off[channel][byte] = offsets[off];
-+						byte_sum[channel] += offsets[off];
-+					}
-+					if (byte_pass[channel] != valid_byte_mask)
-+						done = false;
-+				}
-+				if (done)
-+					break;
-+			}
-+			if (done)
-+				break;
-+		}
-+		printk(BIOS_DEBUG, "\n\n");
-+		if (!done) {
-+			printk(BIOS_ERR, "JWLC: Could not find a pass for all bytes\n");
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				printk(BIOS_ERR, "Channel %u, rank %u fail:", channel, rank);
-+				const uint16_t passing_mask = byte_pass[channel];
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					if (BIT(byte) & passing_mask)
-+						continue;
-+
-+					printk(BIOS_ERR, " %u", byte);
-+				}
-+				printk(BIOS_ERR, "\n");
-+			}
-+			status = RAMINIT_STATUS_JWRL_FAILURE;
-+			break;
-+		}
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			/* Refine target offset to make sure it works for all bytes */
-+			int8_t target_off = DIV_ROUND_CLOSEST(byte_sum[channel], ctrl->lanes);
-+			int16_t global_byte_off = 0;
-+			uint8_t all_good_loops = 0;
-+			bool all_good = 0;
-+			while (!all_good) {
-+				global_byte_off =
-+					set_add_delay(&add_delay[channel], rank, target_off);
-+				all_good = true;
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					int16_t local_offset;
-+					local_offset = byte_off[channel][byte] - target_off;
-+					local_offset = local_offset * 128 + global_byte_off;
-+					const uint16_t tx_dq = ctrl->tx_dq[channel][rank][byte];
-+					if (tx_dq + local_offset >= (512 - 64)) {
-+						all_good = false;
-+						all_good_loops++;
-+						target_off++;
-+						break;
-+					}
-+					const uint16_t txdqs = ctrl->tx_dq[channel][rank][byte];
-+					if (txdqs + local_offset < 96) {
-+						all_good = false;
-+						all_good_loops++;
-+						target_off--;
-+						break;
-+					}
-+				}
-+				/* Avoid an infinite loop */
-+				if (all_good_loops > 3)
-+					break;
-+			}
-+			if (!all_good) {
-+				printk(BIOS_ERR, "JWLC: Target offset refining failed\n");
-+				status = RAMINIT_STATUS_JWRL_FAILURE;
-+				break;
-+			}
-+			printk(BIOS_DEBUG, "C%u.R%u:  Offset\tFinalEdge\n", channel, rank);
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				int16_t local_offset;
-+				local_offset = byte_off[channel][byte] - target_off;
-+				local_offset = local_offset * 128 + global_byte_off;
-+				ctrl->tx_dq[channel][rank][byte] += local_offset;
-+				ctrl->txdqs[channel][rank][byte] += local_offset;
-+				update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
-+				printk(BIOS_DEBUG, "  B%u:   %d\t%d\n", byte, local_offset,
-+					ctrl->txdqs[channel][rank][byte]);
-+			}
-+			mchbar_write32(SC_WR_ADD_DELAY_ch(channel), add_delay[channel]);
-+			if (!ctrl->lpddr) {
-+				reset_dram_dll(ctrl, channel, rank);
-+				udelay(1);
-+			}
-+			printk(BIOS_DEBUG, "\n");
-+		}
-+		printk(BIOS_DEBUG, "\n");
-+	}
-+
-+	/* Restore WDB after test */
-+	write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
-+	program_wdb_lfsr(ctrl, false);
-+	mchbar_write32(DDR_DATA_OFFSET_TRAIN, 0);
-+
-+	/** TODO: Do full JEDEC init instead? **/
-+	io_reset();
-+	return status;
-+}
-+
-+static enum raminit_status verify_wl_width(const int32_t lwidth)
-+{
-+	if (lwidth <= 32) {
-+		/* Check if width is valid */
-+		printk(BIOS_ERR, "WrLevel: Width region (%d) too small\n", lwidth);
-+		return RAMINIT_STATUS_JWRL_FAILURE;
-+	}
-+	if (lwidth >= 96) {
-+		/* Since we're calibrating a phase, a too large region is a problem */
-+		printk(BIOS_ERR, "WrLevel: Width region (%d) too large\n", lwidth);
-+		return RAMINIT_STATUS_JWRL_FAILURE;
-+	}
-+	return 0;
-+}
-+
-+enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl)
-+{
-+	/*
-+	 * Enabling WL mode causes DQS to toggle for 1024 QCLK.
-+	 * Wait for this to stop. Round up to nearest microsecond.
-+	 */
-+	const bool wl_long_delay = ctrl->lpddr;
-+	const uint32_t dqs_toggle_time = wl_long_delay ? 2048 : 1024;
-+	const uint32_t wait_time_us = DIV_ROUND_UP(ctrl->qclkps * dqs_toggle_time, 1000 * 1000);
-+
-+	const uint16_t wl_start = 192;
-+	const uint16_t wl_stop  = 192 + 128;
-+	const uint16_t wl_step  = 2;
-+
-+	/* Do not use cached MR values */
-+	const bool save_restore_mrs = ctrl->restore_mrs;
-+	ctrl->restore_mrs = 0;
-+
-+	/* Propagate delay values (without a write command) */
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		/* Propagate delay values from rank 0 to prevent assertion failures in RTL */
-+		union ddr_data_control_0_reg data_control_0 = {
-+			.raw = ctrl->dq_control_0[channel],
-+		};
-+		data_control_0.read_rf_rd   = 0;
-+		data_control_0.read_rf_wr   = 1;
-+		data_control_0.read_rf_rank = 0;
-+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			union ddr_data_control_2_reg data_control_2 = {
-+				.raw = ctrl->dq_control_2[channel][byte],
-+			};
-+			data_control_2.force_bias_on = 1;
-+			data_control_2.force_rx_on   = 0;
-+			data_control_2.wl_long_delay = wl_long_delay;
-+			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
-+		}
-+	}
-+
-+	if (ctrl->lpddr)
-+		die("%s: Missing LPDDR support\n", __func__);
-+
-+	if (!ctrl->lpddr)
-+		ddr3_program_mr1(ctrl, 0, 1);
-+
-+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
-+	struct phase_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
-+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+		if (!does_rank_exist(ctrl, rank))
-+			continue;
-+
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			/** TODO: Differs for LPDDR **/
-+			uint16_t mr1reg = ctrl->mr1[channel][rank];
-+			mr1reg &= ~MR1_QOFF_ENABLE;
-+			mr1reg |= MR1_WL_ENABLE;
-+			if (is_hsw_ult()) {
-+				mr1reg &= ~RTTNOM_MASK;
-+				mr1reg |= encode_ddr3_rttnom(120);
-+			} else if (ctrl->dpc[channel] == 2) {
-+				mr1reg &= ~RTTNOM_MASK;
-+				mr1reg |= encode_ddr3_rttnom(60);
-+			}
-+			reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
-+
-+			/* Assert ODT for myself */
-+			uint8_t odt_matrix = BIT(rank);
-+			if (ctrl->dpc[channel] == 2) {
-+				/* Assert ODT for non-target DIMM */
-+				const uint8_t other_dimm = ((rank + 2) / 2) & 1;
-+				odt_matrix |= BIT(2 * other_dimm);
-+			}
-+
-+			union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
-+				.raw = 0,
-+			};
-+			if (ctrl->lpddr) {
-+				/* Only one ODT pin for ULT */
-+				reut_misc_odt_ctrl.odt_on       = 1;
-+				reut_misc_odt_ctrl.odt_override = 1;
-+			} else if (!is_hsw_ult()) {
-+				reut_misc_odt_ctrl.odt_on       = odt_matrix;
-+				reut_misc_odt_ctrl.odt_override = 0xf;
-+			}
-+			mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
-+		}
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			/*
-+			 * Enable write leveling mode in DDR and propagate delay
-+			 * values (without a write command). Stay in WL mode.
-+			 */
-+			union ddr_data_control_0_reg data_control_0 = {
-+				.raw = ctrl->dq_control_0[channel],
-+			};
-+			data_control_0.wl_training_mode = 1;
-+			data_control_0.tx_pi_on         = 1;
-+			data_control_0.read_rf_rd       = 0;
-+			data_control_0.read_rf_wr       = 1;
-+			data_control_0.read_rf_rank     = rank;
-+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+		}
-+		printk(BIOS_DEBUG, "\nRank %u\n", rank);
-+		printk(JWRL_PLOT, "Channel\t");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(JWRL_PLOT, "%u", channel);
-+			if (channel > 0)
-+				continue;
-+
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+				printk(JWRL_PLOT, "\t");
-+		}
-+		printk(JWRL_PLOT, "\nByte");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+				printk(JWRL_PLOT, "\t%u", byte);
-+		}
-+		printk(JWRL_PLOT, "\nWlDelay");
-+		for (uint16_t wl_delay = wl_start; wl_delay < wl_stop; wl_delay += wl_step) {
-+			printk(JWRL_PLOT, "\n %3u:", wl_delay);
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					update_txt(ctrl, channel, rank, byte, TXT_TXDQS,
-+						wl_delay);
-+				}
-+			}
-+			/* Wait for the first burst to finish */
-+			if (wl_delay == wl_start)
-+				udelay(wait_time_us);
-+
-+			io_reset();
-+			udelay(wait_time_us);
-+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+					const uint32_t feedback =
-+						get_data_train_feedback(channel, byte);
-+					const bool pass = (feedback & 0x1ff) >= 16;
-+					printk(JWRL_PLOT, "\t%c%u", pass ? '.' : '#', feedback);
-+					phase_record_pass(
-+						&region_data[channel][byte],
-+						pass,
-+						wl_delay,
-+						wl_start,
-+						wl_step);
-+				}
-+			}
-+		}
-+		printk(JWRL_PLOT, "\n");
-+		printk(BIOS_DEBUG, "\n\tInitSt\tInitEn\tCurrSt\tCurrEn\tLargSt\tLargEn\n");
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			printk(BIOS_DEBUG, "C%u\n", channel);
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				struct phase_train_data *data = &region_data[channel][byte];
-+
-+				phase_append_initial_to_current(data, wl_start, wl_step);
-+				printk(BIOS_DEBUG, "   B%u:\t%d\t%d\t%d\t%d\t%d\t%d\n",
-+					byte,
-+					data->initial.start,
-+					data->initial.end,
-+					data->current.start,
-+					data->current.end,
-+					data->largest.start,
-+					data->largest.end);
-+			}
-+		}
-+
-+		/*
-+		 * Clean up after test. Very coarsely adjust for
-+		 * any cycle errors. Program values for TxDQS.
-+		 */
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			/* Clear ODT before MRS (JEDEC spec) */
-+			mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), 0);
-+
-+			/** TODO: Differs for LPDDR **/
-+			const uint16_t mr1reg = ctrl->mr1[channel][rank] | MR1_QOFF_ENABLE;
-+			reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
-+
-+			printk(BIOS_DEBUG, "\nC%u.R%u:  LftEdge Width\n", channel, rank);
-+			const bool rank_x16 = ctrl->dimms[channel][rank / 2].data.width == 16;
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				struct phase_train_data *data = &region_data[channel][byte];
-+				const int32_t lwidth = range_width(data->largest);
-+				int32_t tx_start = data->largest.start;
-+				printk(BIOS_DEBUG, "  B%u:   %d\t%d\n", byte, tx_start, lwidth);
-+				status = verify_wl_width(lwidth);
-+				if (status) {
-+					printk(BIOS_ERR,
-+						"WrLevel problems on channel %u, byte %u\n",
-+						channel, byte);
-+					goto clean_up;
-+				}
-+
-+				/* Align byte pairs if DIMM is x16 */
-+				if (rank_x16 && (byte & 1)) {
-+					const struct phase_train_data *const ref_data =
-+							&region_data[channel][byte - 1];
-+
-+					if (tx_start > ref_data->largest.start + 64)
-+						tx_start -= 128;
-+
-+					if (tx_start < ref_data->largest.start - 64)
-+						tx_start += 128;
-+				}
-+
-+				/* Fix for b4618067 - need to add 1 QCLK to DQS PI */
-+				if (is_hsw_ult())
-+					tx_start += 64;
-+
-+				assert(tx_start >= 0);
-+				ctrl->txdqs[channel][rank][byte] = tx_start;
-+				ctrl->tx_dq[channel][rank][byte] = tx_start + 32;
-+				update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
-+			}
-+		}
-+		printk(BIOS_DEBUG, "\n");
-+	}
-+
-+clean_up:
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			mchbar_write32(DQ_CONTROL_2(channel, byte),
-+				ctrl->dq_control_2[channel][byte]);
-+		}
-+	}
-+	if (!ctrl->lpddr)
-+		ddr3_program_mr1(ctrl, 0, 0);
-+
-+	ctrl->restore_mrs = save_restore_mrs;
-+
-+	if (status)
-+		return status;
-+
-+	/** TODO: If this step fails and dec_wrd is set, clear it and try again **/
-+	return train_jedec_write_leveling_cleanup(ctrl);
-+}
-diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
-index 6a31d3a32c..7c0b5a49de 100644
---- a/src/northbridge/intel/haswell/registers/mchbar.h
-+++ b/src/northbridge/intel/haswell/registers/mchbar.h
-@@ -121,6 +121,8 @@
- 
- #define REUT_ch_ERR_DATA_MASK(ch)		_MCMAIN_C(0x40d8, ch)
- 
-+#define REUT_ch_ERR_MISC_STATUS(ch)		_MCMAIN_C(0x40e8, ch)
-+
- #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
- #define REUT_ch_MISC_ODT_CTRL(ch)		_MCMAIN_C(0x4194, ch)
- #define REUT_ch_MISC_PAT_CADB_CTRL(ch)		_MCMAIN_C(0x4198, ch)
--- 
-2.39.2
-

config/coreboot/haswell/patches/0025-haswell-NRI-Add-final-raminit-steps.patch

@@ -1,570 +0,0 @@
-From d041b14f3af69db5f4598c84e3f53c9cd572ffb5 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sun, 8 May 2022 14:29:05 +0200
-Subject: [PATCH 25/26] haswell NRI: Add final raminit steps
-
-Implement the remaining raminit steps. Although many training steps are
-missing, this is enough to boot on the Asrock B85M Pro4.
-
-Change-Id: I94f3b65f0218d4da4fda4d84592dfd91f77f8f21
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- src/northbridge/intel/haswell/Kconfig         |   4 +-
- .../intel/haswell/native_raminit/Makefile.inc |   1 +
- .../haswell/native_raminit/activate_mc.c      | 388 ++++++++++++++++++
- .../haswell/native_raminit/raminit_main.c     |   5 +-
- .../haswell/native_raminit/raminit_native.c   |   5 +-
- .../haswell/native_raminit/raminit_native.h   |   2 +
- .../haswell/native_raminit/reg_structs.h      |  12 +
- .../intel/haswell/registers/mchbar.h          |   7 +
- 8 files changed, 416 insertions(+), 8 deletions(-)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/activate_mc.c
-
-diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
-index b659bf6d98..61f2a3c64c 100644
---- a/src/northbridge/intel/haswell/Kconfig
-+++ b/src/northbridge/intel/haswell/Kconfig
-@@ -10,12 +10,12 @@ config NORTHBRIDGE_INTEL_HASWELL
- if NORTHBRIDGE_INTEL_HASWELL
- 
- config USE_NATIVE_RAMINIT
--	bool "[NOT WORKING] Use native raminit"
-+	bool "[NOT COMPLETE] Use native raminit"
- 	default n
- 	select HAVE_DEBUG_RAM_SETUP
- 	help
- 	  Select if you want to use coreboot implementation of raminit rather than
--	  MRC.bin. Currently incomplete and does not boot.
-+	  MRC.bin. Currently incomplete and does not support S3 resume.
- 
- config HASWELL_VBOOT_IN_BOOTBLOCK
- 	depends on VBOOT
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-index 40c2f5e014..d97da72890 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
-@@ -1,5 +1,6 @@
- ## SPDX-License-Identifier: GPL-2.0-or-later
- 
-+romstage-y += activate_mc.c
- romstage-y += change_margin.c
- romstage-y += configure_mc.c
- romstage-y += ddr3.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
-new file mode 100644
-index 0000000000..78a7ad27ef
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
-@@ -0,0 +1,388 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <console/console.h>
-+#include <delay.h>
-+#include <device/pci_ops.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <timer.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+static void update_internal_clocks_on(struct sysinfo *ctrl)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		bool clocks_on = false;
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			const union ddr_data_control_1_reg data_control_1 = {
-+				.raw = ctrl->dq_control_1[channel][byte],
-+			};
-+			const int8_t o_on = data_control_1.odt_delay;
-+			const int8_t s_on = data_control_1.sense_amp_delay;
-+			const int8_t o_off = data_control_1.odt_duration;
-+			const int8_t s_off = data_control_1.sense_amp_duration;
-+			if (o_on + o_off >= 7 || s_on + s_off >= 7) {
-+				clocks_on = true;
-+				break;
-+			}
-+		}
-+		union ddr_data_control_0_reg data_control_0 = {
-+			.raw = ctrl->dq_control_0[channel],
-+		};
-+		data_control_0.internal_clocks_on = clocks_on;
-+		ctrl->dq_control_0[channel] = data_control_0.raw;
-+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+	}
-+}
-+
-+/* Switch off unused segments of the SDLL to save power */
-+static void update_sdll_length(struct sysinfo *ctrl)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			uint8_t max_pi = 0;
-+			for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				const uint8_t rx_dqs_p = ctrl->rxdqsp[channel][rank][byte];
-+				const uint8_t rx_dqs_n = ctrl->rxdqsn[channel][rank][byte];
-+				max_pi = MAX(max_pi, MAX(rx_dqs_p, rx_dqs_n));
-+			}
-+			/* Update SDLL length for power savings */
-+			union ddr_data_control_1_reg data_control_1 = {
-+				.raw = ctrl->dq_control_1[channel][byte],
-+			};
-+			/* Calculate which segments to turn off */
-+			data_control_1.sdll_segment_disable = (7 - (max_pi >> 3)) & ~1;
-+			ctrl->dq_control_1[channel][byte] = data_control_1.raw;
-+			mchbar_write32(DQ_CONTROL_1(channel, byte), data_control_1.raw);
-+		}
-+	}
-+}
-+
-+static void set_rx_clk_stg_num(struct sysinfo *ctrl, const uint8_t channel)
-+{
-+	const uint8_t rcven_drift = ctrl->lpddr ? DIV_ROUND_UP(tDQSCK_DRIFT, ctrl->qclkps) : 1;
-+	uint8_t max_rcven = 0;
-+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+		if (!rank_in_ch(ctrl, rank, channel))
-+			continue;
-+
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+			max_rcven = MAX(max_rcven, ctrl->rcven[channel][rank][byte] / 64);
-+	}
-+	const union ddr_data_control_1_reg ddr_data_control_1 = {
-+		.raw = ctrl->dq_control_1[channel][0],
-+	};
-+	const bool lpddr_long_odt = ddr_data_control_1.lpddr_long_odt_en;
-+	const uint8_t rcven_turnoff = max_rcven + 18 + 2 * rcven_drift + lpddr_long_odt;
-+	const union ddr_data_control_0_reg ddr_data_control_0 = {
-+		.raw = ctrl->dq_control_0[channel],
-+	};
-+	for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+		union ddr_data_control_2_reg ddr_data_control_2 = {
-+			.raw = ctrl->dq_control_2[channel][byte],
-+		};
-+		if (ddr_data_control_0.odt_samp_extend_en) {
-+			if (ddr_data_control_2.rx_clk_stg_num < rcven_turnoff)
-+				ddr_data_control_2.rx_clk_stg_num = rcven_turnoff;
-+		} else {
-+			const int8_t o_on = ddr_data_control_1.odt_delay;
-+			const int8_t o_off = ddr_data_control_1.odt_duration;
-+			ddr_data_control_2.rx_clk_stg_num = MAX(17, o_on + o_off + 14);
-+		}
-+		ctrl->dq_control_2[channel][byte] = ddr_data_control_2.raw;
-+		mchbar_write32(DQ_CONTROL_2(channel, byte), ddr_data_control_2.raw);
-+	}
-+}
-+
-+#define SELF_REFRESH_IDLE_COUNT 0x200
-+
-+static void enter_sr(void)
-+{
-+	mchbar_write32(PM_SREF_CONFIG, SELF_REFRESH_IDLE_COUNT | BIT(16));
-+	udelay(1);
-+}
-+
-+enum power_down_mode {
-+	PDM_NO_PD	= 0,
-+	PDM_APD		= 1,
-+	PDM_PPD		= 2,
-+	PDM_PPD_DLL_OFF	= 6,
-+};
-+
-+static void power_down_config(struct sysinfo *ctrl)
-+{
-+	const enum power_down_mode pd_mode = ctrl->lpddr ? PDM_PPD : PDM_PPD_DLL_OFF;
-+	mchbar_write32(PM_PDWN_CONFIG, pd_mode << 12 | 0x40);
-+}
-+
-+static void train_power_modes_post(struct sysinfo *ctrl)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		/* Adjust tCPDED and tPRPDEN */
-+		if (ctrl->mem_clock_mhz >= 933)
-+			ctrl->tc_bankrank_d[channel].tCPDED = 2;
-+
-+		if (ctrl->mem_clock_mhz >= 1066)
-+			ctrl->tc_bankrank_d[channel].tPRPDEN = 2;
-+
-+		mchbar_write32(TC_BANK_RANK_D_ch(channel), ctrl->tc_bankrank_d[channel].raw);
-+	}
-+	power_down_config(ctrl);
-+	mchbar_write32(MCDECS_CBIT, BIT(30));	/* dis_msg_clk_gate */
-+}
-+
-+static uint8_t compute_burst_end_odt_delay(const struct sysinfo *const ctrl)
-+{
-+	/* Must be disabled for LPDDR */
-+	if (ctrl->lpddr)
-+		return 0;
-+
-+	const uint8_t beod = MIN(7, DIV_ROUND_CLOSEST(14300 * 20 / 100, ctrl->qclkps));
-+	if (beod < 3)
-+		return 0;
-+
-+	if (beod < 4)
-+		return 4;
-+
-+	return beod;
-+}
-+
-+static void program_burst_end_odt_delay(struct sysinfo *ctrl)
-+{
-+	/* Program burst_end_odt_delay - it should be zero during training steps */
-+	const uint8_t beod = compute_burst_end_odt_delay(ctrl);
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			union ddr_data_control_1_reg ddr_data_control_1 = {
-+				.raw = ctrl->dq_control_1[channel][byte],
-+			};
-+			ddr_data_control_1.burst_end_odt_delay = beod;
-+			ctrl->dq_control_1[channel][byte] = ddr_data_control_1.raw;
-+			mchbar_write32(DQ_CONTROL_1(channel, byte), ddr_data_control_1.raw);
-+		}
-+	}
-+}
-+
-+/*
-+ * Return a random value to use for scrambler seeds. Try to use RDRAND
-+ * first and fall back to hardcoded values if RDRAND does not succeed.
-+ */
-+static uint16_t get_random_number(const uint8_t channel)
-+{
-+	/* The RDRAND instruction is only available 100k cycles after reset */
-+	for (size_t i = 0; i < 100000; i++) {
-+		uint32_t status;
-+		uint32_t random;
-+		/** TODO: Clean up asm **/
-+		__asm__ __volatile__(
-+			"\n\t .byte 0x0F, 0xC7, 0xF0"
-+			"\n\t movl %%eax, %0"
-+			"\n\t pushf"
-+			"\n\t pop %%eax"
-+			"\n\t movl %%eax, %1"
-+			: "=m"(random),
-+			  "=m"(status)
-+			: /* No inputs */
-+			: "eax", "cc");
-+
-+		/* Only consider non-zero random values as valid */
-+		if (status & 1 && random)
-+			return random;
-+	}
-+
-+	/* https://xkcd.com/221 */
-+	if (channel)
-+		return 0x28f4;
-+	else
-+		return 0x893e;
-+}
-+
-+/* Work around "error: 'typeof' applied to a bit-field" */
-+static inline uint32_t max(const uint32_t a, const uint32_t b)
-+{
-+	return MAX(a, b);
-+}
-+
-+enum raminit_status activate_mc(struct sysinfo *ctrl)
-+{
-+	const bool enable_scrambling = true;
-+	const bool enable_cmd_tristate = true;
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		if (enable_scrambling && ctrl->stepping < STEPPING_C0) {
-+			/* Make sure tRDRD_(sr, dr, dd) are at least 6 for scrambler W/A */
-+			union tc_bank_rank_a_reg tc_bank_rank_a = {
-+				.raw = mchbar_read32(TC_BANK_RANK_A_ch(channel)),
-+			};
-+			tc_bank_rank_a.tRDRD_sr = max(tc_bank_rank_a.tRDRD_sr, 6);
-+			tc_bank_rank_a.tRDRD_dr = max(tc_bank_rank_a.tRDRD_dr, 6);
-+			tc_bank_rank_a.tRDRD_dd = max(tc_bank_rank_a.tRDRD_dd, 6);
-+			mchbar_write32(TC_BANK_RANK_A_ch(channel), tc_bank_rank_a.raw);
-+		}
-+		if (enable_scrambling) {
-+			const union ddr_scramble_reg ddr_scramble = {
-+				.scram_key = get_random_number(channel),
-+				.scram_en  = 1,
-+			};
-+			mchbar_write32(DDR_SCRAMBLE_ch(channel), ddr_scramble.raw);
-+		}
-+		if (ctrl->tCMD == 1) {
-+			/* If we are in 1N mode, enable and set command rate limit to 3 */
-+			union mcmain_command_rate_limit_reg cmd_rate_limit = {
-+				.raw = mchbar_read32(COMMAND_RATE_LIMIT_ch(channel)),
-+			};
-+			cmd_rate_limit.enable_cmd_limit = 1;
-+			cmd_rate_limit.cmd_rate_limit   = 3;
-+			mchbar_write32(COMMAND_RATE_LIMIT_ch(channel), cmd_rate_limit.raw);
-+		}
-+		if (enable_cmd_tristate) {
-+			/* Enable command tri-state at the end of training */
-+			union tc_bank_rank_a_reg tc_bank_rank_a = {
-+				.raw = mchbar_read32(TC_BANK_RANK_A_ch(channel)),
-+			};
-+			tc_bank_rank_a.cmd_3st_dis = 0;
-+			mchbar_write32(TC_BANK_RANK_A_ch(channel), tc_bank_rank_a.raw);
-+		}
-+		/* Set MC to normal mode and clean the ODT and CKE */
-+		mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12);
-+		/* Set again the rank occupancy */
-+		mchbar_write8(MC_INIT_STATE_ch(channel), ctrl->rankmap[channel]);
-+		if (ctrl->is_ecc) {
-+			/* Enable ECC I/O and logic */
-+			union mad_dimm_reg mad_dimm = {
-+				.raw = mchbar_read32(MAD_DIMM(channel)),
-+			};
-+			mad_dimm.ecc_mode = 3;
-+			mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
-+		}
-+	}
-+
-+	if (!is_hsw_ult())
-+		update_internal_clocks_on(ctrl);
-+
-+	update_sdll_length(ctrl);
-+
-+	program_burst_end_odt_delay(ctrl);
-+
-+	if (is_hsw_ult()) {
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!does_ch_exist(ctrl, channel))
-+				continue;
-+
-+			set_rx_clk_stg_num(ctrl, channel);
-+		}
-+		/** TODO: Program DDRPL_CR_DDR_TX_DELAY if Memory Trace is enabled **/
-+	}
-+
-+	/* Enable periodic COMP */
-+	mchbar_write32(M_COMP, (union pcu_comp_reg) {
-+		.comp_interval = COMP_INT,
-+	}.raw);
-+
-+	/* Enable the power mode before PCU starts working */
-+	train_power_modes_post(ctrl);
-+
-+	/* Set idle timer and self refresh enable bits */
-+	enter_sr();
-+
-+	/** FIXME: Do not hardcode power weights and RAPL settings **/
-+	mchbar_write32(0x5888, 0x00000d0d);
-+	mchbar_write32(0x5884, 0x00000004);	/* 58.2 pJ */
-+
-+	mchbar_write32(0x58e0, 0);
-+	mchbar_write32(0x58e4, 0);
-+
-+	mchbar_write32(0x5890, 0xffff);
-+	mchbar_write32(0x5894, 0xffff);
-+	mchbar_write32(0x5898, 0xffff);
-+	mchbar_write32(0x589c, 0xffff);
-+	mchbar_write32(0x58d0, 0xffff);
-+	mchbar_write32(0x58d4, 0xffff);
-+	mchbar_write32(0x58d8, 0xffff);
-+	mchbar_write32(0x58dc, 0xffff);
-+
-+	/* Overwrite thermal parameters */
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		mchbar_write32(_MCMAIN_C(0x42ec, channel), 0x0000000f);
-+		mchbar_write32(_MCMAIN_C(0x42f0, channel), 0x00000009);
-+		mchbar_write32(_MCMAIN_C(0x42f4, channel), 0x00000093);
-+		mchbar_write32(_MCMAIN_C(0x42f8, channel), 0x00000087);
-+		mchbar_write32(_MCMAIN_C(0x42fc, channel), 0x000000de);
-+
-+		/** TODO: Differs for LPDDR **/
-+		mchbar_write32(PM_THRT_CKE_MIN_ch(channel), 0x30);
-+	}
-+	mchbar_write32(PCU_DDR_PTM_CTL, 0x40);
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
-+static void mc_lockdown(void)
-+{
-+	/* Lock memory controller registers */
-+	mchbar_write32(MC_LOCK, 0x8f);
-+
-+	/* MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK is set when programming the memory map */
-+
-+	/* Lock memory map registers */
-+	pci_or_config16(HOST_BRIDGE, GGC,         1 <<  0);
-+	pci_or_config32(HOST_BRIDGE, DPR,         1 <<  0);
-+	pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, 1 << 10);
-+	pci_or_config32(HOST_BRIDGE, REMAPBASE,   1 <<  0);
-+	pci_or_config32(HOST_BRIDGE, REMAPLIMIT,  1 <<  0);
-+	pci_or_config32(HOST_BRIDGE, TOM,         1 <<  0);
-+	pci_or_config32(HOST_BRIDGE, TOUUD,       1 <<  0);
-+	pci_or_config32(HOST_BRIDGE, BDSM,        1 <<  0);
-+	pci_or_config32(HOST_BRIDGE, BGSM,        1 <<  0);
-+	pci_or_config32(HOST_BRIDGE, TOLUD,       1 <<  0);
-+}
-+
-+enum raminit_status raminit_done(struct sysinfo *ctrl)
-+{
-+	union mc_init_state_g_reg mc_init_state_g = {
-+		.raw = mchbar_read32(MC_INIT_STATE_G),
-+	};
-+	mc_init_state_g.refresh_enable = 1;
-+	mc_init_state_g.pu_mrc_done    = 1;
-+	mc_init_state_g.mrc_done       = 1;
-+	mchbar_write32(MC_INIT_STATE_G, mc_init_state_g.raw);
-+
-+	/* Lock the memory controller to enable normal operation */
-+	mc_lockdown();
-+
-+	/* Poll for mc_init_done_ack to make sure memory initialization is complete */
-+	printk(BIOS_DEBUG, "Waiting for mc_init_done acknowledgement... ");
-+
-+	struct stopwatch timer;
-+	stopwatch_init_msecs_expire(&timer, 2000);
-+	do {
-+		mc_init_state_g.raw = mchbar_read32(MC_INIT_STATE_G);
-+
-+		/* DRAM will NOT work without the acknowledgement. There is no hope. */
-+		if (stopwatch_expired(&timer))
-+			die("\nTimed out waiting for mc_init_done acknowledgement\n");
-+
-+	} while (mc_init_state_g.mc_init_done_ack == 0);
-+	printk(BIOS_DEBUG, "DONE!\n");
-+
-+	/* Provide some data for the graphics driver. Yes, it's hardcoded. */
-+	mchbar_write32(SSKPD + 0, 0x05a2404f);
-+	mchbar_write32(SSKPD + 4, 0x140000a0);
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 1ff23be615..3a65fb01fb 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -63,6 +63,8 @@ static const struct task_entry cold_boot[] = {
- 	{ train_receive_enable,                                   true, "RCVET",      },
- 	{ train_read_mpr,                                         true, "RDMPRT",     },
- 	{ train_jedec_write_leveling,                             true, "JWRL",       },
-+	{ activate_mc,                                            true, "ACTIVATE",   },
-+	{ raminit_done,                                           true, "RAMINITEND", },
- };
- 
- /* Return a generic stepping value to make stepping checks simpler */
-@@ -143,7 +145,4 @@ void raminit_main(const enum raminit_boot_mode bootmode)
- 
- 	if (status != RAMINIT_STATUS_SUCCESS)
- 		die("Memory initialization was met with utmost failure and misery\n");
--
--	/** TODO: Implement the required magic **/
--	die("NATIVE RAMINIT: More Magic (tm) required.\n");
- }
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index bd9bc8e692..1ea729b23d 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -200,8 +200,6 @@ void perform_raminit(const int s3resume)
- 		else
- 			me_status = ME_INIT_STATUS_SUCCESS;
- 
--		/** TODO: Remove this once raminit is implemented **/
--		me_status = ME_INIT_STATUS_ERROR;
- 		intel_early_me_init_done(me_status);
- 	}
- 
-@@ -217,7 +215,8 @@ void perform_raminit(const int s3resume)
- 	}
- 
- 	/* Save training data on non-S3 resumes */
--	if (!s3resume)
-+	/** TODO: Enable this once training data is populated **/
-+	if (0 && !s3resume)
- 		save_mrc_data(&md);
- 
- 	/** TODO: setup_sdram_meminfo **/
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 666b233c45..98e39cb76e 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -449,6 +449,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
- enum raminit_status train_receive_enable(struct sysinfo *ctrl);
- enum raminit_status train_read_mpr(struct sysinfo *ctrl);
- enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
-+enum raminit_status activate_mc(struct sysinfo *ctrl);
-+enum raminit_status raminit_done(struct sysinfo *ctrl);
- 
- void configure_timings(struct sysinfo *ctrl);
- void configure_refresh(struct sysinfo *ctrl);
-diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-index a0e36ed082..0d9aaa1f7c 100644
---- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
-@@ -294,6 +294,18 @@ union ddr_cke_ctl_controls_reg {
- 	uint32_t raw;
- };
- 
-+union ddr_scramble_reg {
-+	struct __packed {
-+		uint32_t scram_en    :  1; // Bits  0:0
-+		uint32_t scram_key   : 16; // Bits 16:1
-+		uint32_t clk_gate_ab :  2; // Bits 18:17
-+		uint32_t clk_gate_c  :  2; // Bits 20:19
-+		uint32_t en_dbi_ab   :  1; // Bits 21:21
-+		uint32_t             : 10; // Bits 31:17
-+	};
-+	uint32_t raw;
-+};
-+
- union ddr_scram_misc_control_reg {
- 	struct __packed {
- 		uint32_t wl_wake_cycles       :  2; // Bits  1:0
-diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
-index 7c0b5a49de..49a215aa71 100644
---- a/src/northbridge/intel/haswell/registers/mchbar.h
-+++ b/src/northbridge/intel/haswell/registers/mchbar.h
-@@ -20,6 +20,7 @@
- 
- #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
- 
-+#define DQ_CONTROL_1(ch, byte)			_DDRIO_C_R_B(0x0060, ch, 0, byte)
- #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
- #define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte)	_DDRIO_C_R_B(0x0070, ch, 0, byte)
- #define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
-@@ -147,6 +148,8 @@
- #define QCLK_ch_LDAT_SDAT(ch)			_MCMAIN_C(0x42d4, ch)
- #define QCLK_ch_LDAT_DATA_IN_x(ch, x)		_MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
- 
-+#define PM_THRT_CKE_MIN_ch(ch)			_MCMAIN_C(0x4328, ch)
-+
- #define REUT_GLOBAL_CTL				0x4800
- #define REUT_GLOBAL_ERR				0x4804
- 
-@@ -175,6 +178,8 @@
- 
- #define MCSCHEDS_DFT_MISC	0x4c30
- 
-+#define PM_PDWN_CONFIG		0x4cb0
-+
- #define REUT_ERR_DATA_STATUS	0x4ce0
- 
- #define REUT_MISC_CKE_CTRL	0x4d90
-@@ -186,8 +191,10 @@
- #define MAD_CHNL		0x5000 /* Address Decoder Channel Configuration */
- #define MAD_DIMM(ch)		(0x5004 + (ch) * 4)
- #define MAD_ZR			0x5014
-+#define MCDECS_CBIT		0x501c
- #define MC_INIT_STATE_G		0x5030
- #define MRC_REVISION		0x5034 /* MRC Revision */
-+#define PM_SREF_CONFIG		0x5060
- 
- #define RCOMP_TIMER		0x5084
- 
--- 
-2.39.2
-

config/coreboot/haswell/patches/0026-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -1,38 +0,0 @@
-From 1ce4f118b024a6367382b46016781f30fe622e3e Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH] Remove warning for coreboot images built without a payload
-
-I added this in upstream to prevent people from accidentally flashing
-roms without a payload resulting in a no boot situation, but in
-libreboot lbmk handles the payload and thus this warning always comes
-up. This has caused confusion and concern so just patch it out.
----
- payloads/Makefile.inc | 13 +------------
- 1 file changed, 1 insertion(+), 12 deletions(-)
-
-diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
-index e735443a76..4f1692a873 100644
---- a/payloads/Makefile.inc
-+++ b/payloads/Makefile.inc
-@@ -49,16 +49,5 @@ distclean-payloads:
- print-repo-info-payloads:
- 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
- 
--ifeq ($(CONFIG_PAYLOAD_NONE),y)
--files_added:: warn_no_payload
--endif
--
--warn_no_payload:
--	printf "\n\t** WARNING **\n"
--	printf "coreboot has been built without a payload. Writing\n"
--	printf "a coreboot image without a payload to your board's\n"
--	printf "flash chip will result in a non-booting system. You\n"
--	printf "can use cbfstool to add a payload to the image.\n\n"
--
- .PHONY: force-payload coreinfo nvramcui
--.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
-+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--- 
-2.40.1
-

config/coreboot/haswell/patches/0027-coreboot-haswell-fix-acpica-downloads.patch

@@ -1,30 +0,0 @@
-From 29c1116ebd5879568010a8386e4838294a78b408 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 16 Jul 2023 03:48:23 +0100
-Subject: [PATCH 1/1] coreboot/haswell: fix acpica downloads
-
-the upstream link died. i now host the relevant acpica
-tarball myself, on libreboot rsync. this patch makes
-coreboot crossgcc use that
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- util/crossgcc/buildgcc | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
-index 3c4b10cc92..0c4262b7b1 100755
---- a/util/crossgcc/buildgcc
-+++ b/util/crossgcc/buildgcc
-@@ -52,7 +52,7 @@ MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
- MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
- GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
- BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
--IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
-+IASL_ARCHIVE="https://mirror.math.princeton.edu/pub/libreboot/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
- # CLANG toolchain archive locations
- LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz"
- CLANG_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}/clang-${CLANG_VERSION}.src.tar.xz"
--- 
-2.40.1
-

config/coreboot/haswell/target.cfg

@@ -1,4 +0,0 @@
-tree="haswell"
-romtype="normal"
-rev="1411ecf6f0b2c7395bcb96b856dcfdddb1b0c81b"
-arch="x86_64"

config/coreboot/hp2170p_16mb/config/libgfxinit_corebootfb

@@ -1,664 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-CONFIG_VENDOR_HP=y
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_MAINBOARD_PART_NUMBER="EliteBook 2170p"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="hp/snb_ivb_laptops"
-CONFIG_VGA_BIOS_ID="8086,0166"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="HP"
-CONFIG_CBFS_SIZE=0xFE5000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_VARIANT_DIR="2170p"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="HP"
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=0
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_TPM_PIRQ=0x0
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_BOARD_HP_280_G2 is not set
-# CONFIG_BOARD_HP_COMPAQ_8200_ELITE_SFF_PC is not set
-# CONFIG_BOARD_HP_COMPAQ_ELITE_8300_USDT is not set
-# CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
-# CONFIG_BOARD_HP_FOLIO_9480M is not set
-CONFIG_BOARD_HP_2170P=y
-# CONFIG_BOARD_HP_2560P is not set
-# CONFIG_BOARD_HP_2570P is not set
-# CONFIG_BOARD_HP_2760P is not set
-# CONFIG_BOARD_HP_8460P is not set
-# CONFIG_BOARD_HP_8470P is not set
-# CONFIG_BOARD_HP_8770W is not set
-# CONFIG_BOARD_HP_FOLIO_9470M is not set
-# CONFIG_BOARD_HP_PROBOOK_6360B is not set
-# CONFIG_BOARD_HP_REVOLVE_810_G1 is not set
-# CONFIG_BOARD_HP_Z220_CMT_WORKSTATION is not set
-# CONFIG_BOARD_HP_Z220_SFF_WORKSTATION is not set
-CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS=y
-CONFIG_EC_HP_KBC1126_GPE=0x16
-CONFIG_BOARD_HP_SNB_IVB_LAPTOPS_COMMON=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="EliteBook 2170p"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_C216=y
-CONFIG_SOUTH_BRIDGE_OPTIONS=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_SMSC_LPC47N217=y
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_HP_KBC1126=y
-
-#
-# Please select the following otherwise your laptop cannot be powered on.
-#
-CONFIG_KBC1126_FIRMWARE=y
-CONFIG_ECFW_PTR_ADDR=0xffffff00
-CONFIG_ECFW_PTR_SIZE=8
-CONFIG_KBC1126_FW1="../../../ec/hp2170p/ec.bin.fw1"
-CONFIG_KBC1126_FW1_OFFSET=0xfffe8000
-CONFIG_KBC1126_FW2="../../../ec/hp2170p/ec.bin.fw2"
-CONFIG_KBC1126_FW2_OFFSET=0xfffd0000
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_TPM_INIT_RAMSTAGE=y
-# CONFIG_TPM_PPI is not set
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-# CONFIG_NO_TPM is not set
-CONFIG_TPM1=y
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM1=y
-# CONFIG_TPM_DEACTIVATE is not set
-# CONFIG_DEBUG_TPM is not set
-# CONFIG_TPM_RDRESP_NEED_DELAY is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_INTEL_TXT is not set
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/hp2170p_16mb/config/libgfxinit_txtmode

@@ -1,661 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-CONFIG_VENDOR_HP=y
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_MAINBOARD_PART_NUMBER="EliteBook 2170p"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="hp/snb_ivb_laptops"
-CONFIG_VGA_BIOS_ID="8086,0166"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="HP"
-CONFIG_CBFS_SIZE=0xFE5000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_VARIANT_DIR="2170p"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="HP"
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=0
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_TPM_PIRQ=0x0
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_BOARD_HP_280_G2 is not set
-# CONFIG_BOARD_HP_COMPAQ_8200_ELITE_SFF_PC is not set
-# CONFIG_BOARD_HP_COMPAQ_ELITE_8300_USDT is not set
-# CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
-# CONFIG_BOARD_HP_FOLIO_9480M is not set
-CONFIG_BOARD_HP_2170P=y
-# CONFIG_BOARD_HP_2560P is not set
-# CONFIG_BOARD_HP_2570P is not set
-# CONFIG_BOARD_HP_2760P is not set
-# CONFIG_BOARD_HP_8460P is not set
-# CONFIG_BOARD_HP_8470P is not set
-# CONFIG_BOARD_HP_8770W is not set
-# CONFIG_BOARD_HP_FOLIO_9470M is not set
-# CONFIG_BOARD_HP_PROBOOK_6360B is not set
-# CONFIG_BOARD_HP_REVOLVE_810_G1 is not set
-# CONFIG_BOARD_HP_Z220_CMT_WORKSTATION is not set
-# CONFIG_BOARD_HP_Z220_SFF_WORKSTATION is not set
-CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS=y
-CONFIG_EC_HP_KBC1126_GPE=0x16
-CONFIG_BOARD_HP_SNB_IVB_LAPTOPS_COMMON=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="EliteBook 2170p"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_C216=y
-CONFIG_SOUTH_BRIDGE_OPTIONS=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_SMSC_LPC47N217=y
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_HP_KBC1126=y
-
-#
-# Please select the following otherwise your laptop cannot be powered on.
-#
-CONFIG_KBC1126_FIRMWARE=y
-CONFIG_ECFW_PTR_ADDR=0xffffff00
-CONFIG_ECFW_PTR_SIZE=8
-CONFIG_KBC1126_FW1="../../../ec/hp2170p/ec.bin.fw1"
-CONFIG_KBC1126_FW1_OFFSET=0xfffe8000
-CONFIG_KBC1126_FW2="../../../ec/hp2170p/ec.bin.fw2"
-CONFIG_KBC1126_FW2_OFFSET=0xfffd0000
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_TPM_INIT_RAMSTAGE=y
-# CONFIG_TPM_PPI is not set
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-# CONFIG_NO_TPM is not set
-CONFIG_TPM1=y
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM1=y
-# CONFIG_TPM_DEACTIVATE is not set
-# CONFIG_DEBUG_TPM is not set
-# CONFIG_TPM_RDRESP_NEED_DELAY is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_INTEL_TXT is not set
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/hp2170p_16mb/target.cfg

@@ -1,9 +0,0 @@
-tree="default"
-romtype="normal"
-arch="x86_64"
-payload_grub="y"
-payload_grub_withseabios="y"
-payload_seabios="y"
-payload_memtest="y"
-grub_scan_disk="ahci"
-grub_timeout=10

config/coreboot/hp2560p_8mb/config/libgfxinit_corebootfb

@@ -1,640 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-CONFIG_VENDOR_HP=y
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_MAINBOARD_PART_NUMBER="EliteBook 2560p"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="hp/snb_ivb_laptops"
-CONFIG_VGA_BIOS_ID="8086,0116"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="HP"
-CONFIG_CBFS_SIZE=0x7E9000
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_VARIANT_DIR="2560p"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="HP"
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_TPM_PIRQ=0x0
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_sandybridge/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_sandybridge/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_sandybridge/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_BOARD_HP_280_G2 is not set
-# CONFIG_BOARD_HP_COMPAQ_8200_ELITE_SFF_PC is not set
-# CONFIG_BOARD_HP_COMPAQ_ELITE_8300_USDT is not set
-# CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
-# CONFIG_BOARD_HP_FOLIO_9480M is not set
-# CONFIG_BOARD_HP_2170P is not set
-CONFIG_BOARD_HP_2560P=y
-# CONFIG_BOARD_HP_2570P is not set
-# CONFIG_BOARD_HP_2760P is not set
-# CONFIG_BOARD_HP_8460P is not set
-# CONFIG_BOARD_HP_8470P is not set
-# CONFIG_BOARD_HP_8770W is not set
-# CONFIG_BOARD_HP_FOLIO_9470M is not set
-# CONFIG_BOARD_HP_PROBOOK_6360B is not set
-# CONFIG_BOARD_HP_REVOLVE_810_G1 is not set
-# CONFIG_BOARD_HP_Z220_CMT_WORKSTATION is not set
-# CONFIG_BOARD_HP_Z220_SFF_WORKSTATION is not set
-CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS=y
-CONFIG_EC_HP_KBC1126_GPE=0x16
-CONFIG_BOARD_HP_SNB_IVB_LAPTOPS_COMMON=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="EliteBook 2560p"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=8192
-CONFIG_ROM_SIZE=0x00800000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
-CONFIG_SOUTH_BRIDGE_OPTIONS=y
-CONFIG_HIDE_MEI_ON_ERROR=y
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_HP_KBC1126=y
-
-#
-# Please select the following otherwise your laptop cannot be powered on.
-#
-CONFIG_KBC1126_FIRMWARE=y
-CONFIG_ECFW_PTR_ADDR=0xffffff00
-CONFIG_ECFW_PTR_SIZE=8
-CONFIG_KBC1126_FW1="../../../ec/hp2560p/ec.bin.fw1"
-CONFIG_KBC1126_FW1_OFFSET=0xfffe8000
-CONFIG_KBC1126_FW2="../../../ec/hp2560p/ec.bin.fw2"
-CONFIG_KBC1126_FW2_OFFSET=0xfffd0000
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_TPM_INIT_RAMSTAGE=y
-# CONFIG_TPM_PPI is not set
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-# CONFIG_NO_TPM is not set
-CONFIG_TPM1=y
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM1=y
-# CONFIG_TPM_DEACTIVATE is not set
-# CONFIG_DEBUG_TPM is not set
-# CONFIG_TPM_RDRESP_NEED_DELAY is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_INTEL_TXT is not set
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/hp2560p_8mb/config/libgfxinit_txtmode

@@ -1,637 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-CONFIG_VENDOR_HP=y
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_MAINBOARD_PART_NUMBER="EliteBook 2560p"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="hp/snb_ivb_laptops"
-CONFIG_VGA_BIOS_ID="8086,0116"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="HP"
-CONFIG_CBFS_SIZE=0x7E9000
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_VARIANT_DIR="2560p"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="HP"
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_TPM_PIRQ=0x0
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_sandybridge/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_sandybridge/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_sandybridge/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_BOARD_HP_280_G2 is not set
-# CONFIG_BOARD_HP_COMPAQ_8200_ELITE_SFF_PC is not set
-# CONFIG_BOARD_HP_COMPAQ_ELITE_8300_USDT is not set
-# CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
-# CONFIG_BOARD_HP_FOLIO_9480M is not set
-# CONFIG_BOARD_HP_2170P is not set
-CONFIG_BOARD_HP_2560P=y
-# CONFIG_BOARD_HP_2570P is not set
-# CONFIG_BOARD_HP_2760P is not set
-# CONFIG_BOARD_HP_8460P is not set
-# CONFIG_BOARD_HP_8470P is not set
-# CONFIG_BOARD_HP_8770W is not set
-# CONFIG_BOARD_HP_FOLIO_9470M is not set
-# CONFIG_BOARD_HP_PROBOOK_6360B is not set
-# CONFIG_BOARD_HP_REVOLVE_810_G1 is not set
-# CONFIG_BOARD_HP_Z220_CMT_WORKSTATION is not set
-# CONFIG_BOARD_HP_Z220_SFF_WORKSTATION is not set
-CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS=y
-CONFIG_EC_HP_KBC1126_GPE=0x16
-CONFIG_BOARD_HP_SNB_IVB_LAPTOPS_COMMON=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="EliteBook 2560p"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=8192
-CONFIG_ROM_SIZE=0x00800000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
-CONFIG_SOUTH_BRIDGE_OPTIONS=y
-CONFIG_HIDE_MEI_ON_ERROR=y
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_HP_KBC1126=y
-
-#
-# Please select the following otherwise your laptop cannot be powered on.
-#
-CONFIG_KBC1126_FIRMWARE=y
-CONFIG_ECFW_PTR_ADDR=0xffffff00
-CONFIG_ECFW_PTR_SIZE=8
-CONFIG_KBC1126_FW1="../../../ec/hp2560p/ec.bin.fw1"
-CONFIG_KBC1126_FW1_OFFSET=0xfffe8000
-CONFIG_KBC1126_FW2="../../../ec/hp2560p/ec.bin.fw2"
-CONFIG_KBC1126_FW2_OFFSET=0xfffd0000
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_TPM_INIT_RAMSTAGE=y
-# CONFIG_TPM_PPI is not set
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-# CONFIG_NO_TPM is not set
-CONFIG_TPM1=y
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM1=y
-# CONFIG_TPM_DEACTIVATE is not set
-# CONFIG_DEBUG_TPM is not set
-# CONFIG_TPM_RDRESP_NEED_DELAY is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_INTEL_TXT is not set
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/hp2560p_8mb/target.cfg

@@ -1,9 +0,0 @@
-tree="default"
-romtype="normal"
-arch="x86_64"
-payload_grub="y"
-payload_grub_withseabios="y"
-payload_seabios="y"
-payload_memtest="y"
-grub_scan_disk="ahci"
-grub_timeout=10

config/coreboot/hp2570p_16mb/config/libgfxinit_corebootfb

@@ -1,638 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-CONFIG_VENDOR_HP=y
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_MAINBOARD_PART_NUMBER="EliteBook 2570p"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="hp/snb_ivb_laptops"
-CONFIG_VGA_BIOS_ID="8086,0166"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="HP"
-CONFIG_CBFS_SIZE=0xFE0000
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_VARIANT_DIR="2570p"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="HP"
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_TPM_PIRQ=0x0
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_BOARD_HP_280_G2 is not set
-# CONFIG_BOARD_HP_COMPAQ_8200_ELITE_SFF_PC is not set
-# CONFIG_BOARD_HP_COMPAQ_ELITE_8300_USDT is not set
-# CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
-# CONFIG_BOARD_HP_FOLIO_9480M is not set
-# CONFIG_BOARD_HP_2170P is not set
-# CONFIG_BOARD_HP_2560P is not set
-CONFIG_BOARD_HP_2570P=y
-# CONFIG_BOARD_HP_2760P is not set
-# CONFIG_BOARD_HP_8460P is not set
-# CONFIG_BOARD_HP_8470P is not set
-# CONFIG_BOARD_HP_8770W is not set
-# CONFIG_BOARD_HP_FOLIO_9470M is not set
-# CONFIG_BOARD_HP_PROBOOK_6360B is not set
-# CONFIG_BOARD_HP_REVOLVE_810_G1 is not set
-# CONFIG_BOARD_HP_Z220_CMT_WORKSTATION is not set
-# CONFIG_BOARD_HP_Z220_SFF_WORKSTATION is not set
-CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS=y
-CONFIG_EC_HP_KBC1126_GPE=0x16
-CONFIG_BOARD_HP_SNB_IVB_LAPTOPS_COMMON=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="EliteBook 2570p"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_C216=y
-CONFIG_SOUTH_BRIDGE_OPTIONS=y
-CONFIG_HIDE_MEI_ON_ERROR=y
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_HP_KBC1126=y
-
-#
-# Please select the following otherwise your laptop cannot be powered on.
-#
-CONFIG_KBC1126_FIRMWARE=y
-CONFIG_ECFW_PTR_ADDR=0xffffff00
-CONFIG_ECFW_PTR_SIZE=8
-CONFIG_KBC1126_FW1="../../../ec/hp2570p/ec.bin.fw1"
-CONFIG_KBC1126_FW1_OFFSET=0xfffe8000
-CONFIG_KBC1126_FW2="../../../ec/hp2570p/ec.bin.fw2"
-CONFIG_KBC1126_FW2_OFFSET=0xfffd0000
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-# CONFIG_INTEL_GMA_ADD_VBT is not set
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_TPM_INIT_RAMSTAGE=y
-# CONFIG_TPM_PPI is not set
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-# CONFIG_NO_TPM is not set
-CONFIG_TPM1=y
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM1=y
-# CONFIG_TPM_DEACTIVATE is not set
-# CONFIG_DEBUG_TPM is not set
-# CONFIG_TPM_RDRESP_NEED_DELAY is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_INTEL_TXT is not set
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/hp2570p_16mb/config/libgfxinit_txtmode

@@ -1,635 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_COREBOOT_BUILD=y
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-CONFIG_ARCH_SUPPORTS_CLANG=y
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-# CONFIG_FW_CONFIG is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_ADLINK is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-CONFIG_VENDOR_HP=y
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_UP is not set
-CONFIG_MAINBOARD_PART_NUMBER="EliteBook 2570p"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="hp/snb_ivb_laptops"
-CONFIG_VGA_BIOS_ID="8086,0166"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="HP"
-CONFIG_CBFS_SIZE=0xFE0000
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-CONFIG_VARIANT_DIR="2570p"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-# CONFIG_VGA_BIOS is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="HP"
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_CONSOLE_POST is not set
-CONFIG_TPM_PIRQ=0x0
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-# CONFIG_DRIVERS_INTEL_WIFI is not set
-CONFIG_IFD_BIN_PATH="../../../config/ifd/hp_ivybridge/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/hp_ivybridge/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/hp_ivybridge/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_VBT_DATA_SIZE_KB=8
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_BOARD_HP_280_G2 is not set
-# CONFIG_BOARD_HP_COMPAQ_8200_ELITE_SFF_PC is not set
-# CONFIG_BOARD_HP_COMPAQ_ELITE_8300_USDT is not set
-# CONFIG_BOARD_HP_ELITEBOOK_820_G2 is not set
-# CONFIG_BOARD_HP_FOLIO_9480M is not set
-# CONFIG_BOARD_HP_2170P is not set
-# CONFIG_BOARD_HP_2560P is not set
-CONFIG_BOARD_HP_2570P=y
-# CONFIG_BOARD_HP_2760P is not set
-# CONFIG_BOARD_HP_8460P is not set
-# CONFIG_BOARD_HP_8470P is not set
-# CONFIG_BOARD_HP_8770W is not set
-# CONFIG_BOARD_HP_FOLIO_9470M is not set
-# CONFIG_BOARD_HP_PROBOOK_6360B is not set
-# CONFIG_BOARD_HP_REVOLVE_810_G1 is not set
-# CONFIG_BOARD_HP_Z220_CMT_WORKSTATION is not set
-# CONFIG_BOARD_HP_Z220_SFF_WORKSTATION is not set
-CONFIG_EC_HP_KBC1126_ECFW_IN_CBFS=y
-CONFIG_EC_HP_KBC1126_GPE=0x16
-CONFIG_BOARD_HP_SNB_IVB_LAPTOPS_COMMON=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="EliteBook 2570p"
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
-# CONFIG_DRIVERS_UART_8250IO is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_EC_GPE_SCI=0x50
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-CONFIG_SYSTEM_TYPE_LAPTOP=y
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_EXP_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_C216=y
-CONFIG_SOUTH_BRIDGE_OPTIONS=y
-CONFIG_HIDE_MEI_ON_ERROR=y
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-CONFIG_EC_HP_KBC1126=y
-
-#
-# Please select the following otherwise your laptop cannot be powered on.
-#
-CONFIG_KBC1126_FIRMWARE=y
-CONFIG_ECFW_PTR_ADDR=0xffffff00
-CONFIG_ECFW_PTR_SIZE=8
-CONFIG_KBC1126_FW1="../../../ec/hp2570p/ec.bin.fw1"
-CONFIG_KBC1126_FW1_OFFSET=0xfffe8000
-CONFIG_KBC1126_FW2="../../../ec/hp2570p/ec.bin.fw2"
-CONFIG_KBC1126_FW2_OFFSET=0xfffd0000
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_EXP_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_PLUGIN_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x2000
-CONFIG_FIRMWARE_CONNECTION_MANAGER=y
-# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-# CONFIG_INTEL_GMA_ADD_VBT is not set
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_TPM_INIT_RAMSTAGE=y
-# CONFIG_TPM_PPI is not set
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-# CONFIG_NO_TPM is not set
-CONFIG_TPM1=y
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM1=y
-# CONFIG_TPM_DEACTIVATE is not set
-# CONFIG_DEBUG_TPM is not set
-# CONFIG_TPM_RDRESP_NEED_DELAY is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_INTEL_TXT is not set
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-CONFIG_HEAP_SIZE=0x100000
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_FATAL_ASSERTS is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/hp2570p_16mb/target.cfg

@@ -1,9 +0,0 @@
-tree="default"
-romtype="normal"
-arch="x86_64"
-payload_grub="y"
-payload_grub_withseabios="y"
-payload_seabios="y"
-payload_memtest="y"
-grub_scan_disk="ahci"
-grub_timeout=10