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delete all boards

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Signed-off-by: Leah Rowe <leah@libreboot.org>
This commit is contained in:
Leah Rowe
2023-11-10 17:27:44 +00:00
parent 47ef411efb
commit fcf27a5719
296 changed files with 0 additions and 101371 deletions
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config/coreboot/d510mo/config/libgfxinit_txtmode
-592
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@@ -1,592 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="intel/d510mo"
CONFIG_VGA_BIOS_ID="8086,a001"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Intel"
CONFIG_CBFS_SIZE=0x00100000
CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
# Coffeelake RVP
#
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_D945GCLF is not set
# CONFIG_BOARD_INTEL_DCP847SKE is not set
# CONFIG_BOARD_INTEL_DG41WV is not set
# CONFIG_BOARD_INTEL_DG43GT is not set
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
# CONFIG_BOARD_INTEL_LEAFHILL is not set
# CONFIG_BOARD_INTEL_MINNOW3 is not set
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
CONFIG_COREBOOT_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=1024
CONFIG_ROM_SIZE=0x00100000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x80000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_106CX=y
CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_CPU_HAS_L2_ENABLE_MSR=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
#
# Southbridge
#
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM=y
CONFIG_SUPERIO_WINBOND_W83627THG=y
#
# Embedded Controllers
#
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_CK505=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_EDID=y
CONFIG_INTEL_INT15=y
CONFIG_INTEL_GMA_ACPI=y
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_NULL=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/d510mo/target.cfg
-9
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@@ -1,9 +0,0 @@
tree="default"
romtype="normal"
arch="x86_64"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="y"
payload_memtest="y"
microcode_required="n"
vendorfiles="n"
config/coreboot/d510mo_16mb/config/libgfxinit_txtmode
-592
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@@ -1,592 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="intel/d510mo"
CONFIG_VGA_BIOS_ID="8086,a001"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Intel"
CONFIG_CBFS_SIZE=0x01000000
CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
# Coffeelake RVP
#
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
CONFIG_BOARD_INTEL_D510MO=y
# CONFIG_BOARD_INTEL_D945GCLF is not set
# CONFIG_BOARD_INTEL_DCP847SKE is not set
# CONFIG_BOARD_INTEL_DG41WV is not set
# CONFIG_BOARD_INTEL_DG43GT is not set
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
# CONFIG_BOARD_INTEL_LEAFHILL is not set
# CONFIG_BOARD_INTEL_MINNOW3 is not set
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=16384
CONFIG_ROM_SIZE=0x01000000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x80000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_106CX=y
CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_CPU_HAS_L2_ENABLE_MSR=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
#
# Southbridge
#
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM=y
CONFIG_SUPERIO_WINBOND_W83627THG=y
#
# Embedded Controllers
#
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_CK505=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_EDID=y
CONFIG_INTEL_INT15=y
CONFIG_INTEL_GMA_ACPI=y
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_NULL=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/d510mo_16mb/target.cfg
-8
View File
@@ -1,8 +0,0 @@
tree="default"
romtype="normal"
arch="x86_64"
payload_seabios="y"
payload_seabios_withgrub="y"
payload_memtest="y"
microcode_required="n"
vendorfiles="n"
config/coreboot/d945gclf_512kb/config/libgfxinit_txtmode
-591
View File
@@ -1,591 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
# CONFIG_NO_STAGE_CACHE is not set
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="intel/d945gclf"
CONFIG_VGA_BIOS_ID="8086,2772"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Intel"
CONFIG_CBFS_SIZE=0x00080000
CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
# Coffeelake RVP
#
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
# CONFIG_BOARD_INTEL_D510MO is not set
CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_DCP847SKE is not set
# CONFIG_BOARD_INTEL_DG41WV is not set
# CONFIG_BOARD_INTEL_DG43GT is not set
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
# CONFIG_BOARD_INTEL_LEAFHILL is not set
# CONFIG_BOARD_INTEL_MINNOW3 is not set
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
CONFIG_COREBOOT_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=512
CONFIG_ROM_SIZE=0x00080000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_106CX=y
CONFIG_CPU_INTEL_SOCKET_441=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_NORTHBRIDGE_INTEL_I945=y
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
#
# Southbridge
#
# CONFIG_PCIEXP_HOTPLUG is not set
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_SMSC_LPC47M15X=y
#
# Embedded Controllers
#
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_USE_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_EDID=y
CONFIG_INTEL_GMA_ACPI=y
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_NULL=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
CONFIG_HAVE_MP_TABLE=y
CONFIG_HAVE_PIRQ_TABLE=y
#
# System tables
#
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
# CONFIG_DEBUG_PIRQ is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/d945gclf_512kb/target.cfg
-9
View File
@@ -1,9 +0,0 @@
tree="default"
romtype="normal"
arch="x86_32"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="y"
payload_memtest="n"
vendorfiles="n"
microcode_required="n"
config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode
-591
View File
@@ -1,591 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
# CONFIG_NO_STAGE_CACHE is not set
CONFIG_TSEG_STAGE_CACHE=y
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
CONFIG_VENDOR_INTEL=y
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="intel/d945gclf"
CONFIG_VGA_BIOS_ID="8086,2772"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Intel"
CONFIG_CBFS_SIZE=0x00800000
CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_IRQ_SLOT_COUNT=18
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
#
# Coffeelake RVP
#
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
# CONFIG_BOARD_INTEL_D510MO is not set
CONFIG_BOARD_INTEL_D945GCLF=y
# CONFIG_BOARD_INTEL_DCP847SKE is not set
# CONFIG_BOARD_INTEL_DG41WV is not set
# CONFIG_BOARD_INTEL_DG43GT is not set
# CONFIG_BOARD_INTEL_DQ67SW is not set
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
# CONFIG_BOARD_INTEL_GLKRVP is not set
# CONFIG_BOARD_INTEL_HARCUVAR is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
# CONFIG_BOARD_INTEL_LEAFHILL is not set
# CONFIG_BOARD_INTEL_MINNOW3 is not set
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
# CONFIG_BOARD_INTEL_STRAGO is not set
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
# CONFIG_BOARD_INTEL_WTM2 is not set
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_512=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=8192
CONFIG_ROM_SIZE=0x00800000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_106CX=y
CONFIG_CPU_INTEL_SOCKET_441=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_NORTHBRIDGE_INTEL_I945=y
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
#
# Southbridge
#
# CONFIG_PCIEXP_HOTPLUG is not set
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_SMSC_LPC47M15X=y
#
# Embedded Controllers
#
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_USE_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_EDID=y
CONFIG_INTEL_GMA_ACPI=y
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_NULL=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
CONFIG_HAVE_MP_TABLE=y
CONFIG_HAVE_PIRQ_TABLE=y
#
# System tables
#
CONFIG_GENERATE_MP_TABLE=y
CONFIG_GENERATE_PIRQ_TABLE=y
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
# CONFIG_DEBUG_PIRQ is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/d945gclf_8mb/target.cfg
-9
View File
@@ -1,9 +0,0 @@
tree="default"
romtype="normal"
arch="x86_32"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="y"
payload_memtest="n"
vendorfiles="n"
microcode_required="n"
config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch
-23
View File
@@ -1,23 +0,0 @@
From e8f5f6c372152c7deddd3080954d0f4fdd39ae2b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@retroboot.org>
Date: Fri, 19 Mar 2021 05:54:58 +0000
Subject: [PATCH 01/22] apple/macbook21: Set default VRAM to 64MiB instead of
8MiB
---
src/mainboard/apple/macbook21/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
index cf1bc4566e..dc0df3b6d6 100644
--- a/src/mainboard/apple/macbook21/cmos.default
+++ b/src/mainboard/apple/macbook21/cmos.default
@@ -5,4 +5,4 @@ boot_devices=''
boot_default=0x40
cmos_defaults_loaded=Yes
lpt=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2
config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch
-68
View File
@@ -1,68 +0,0 @@
From fdd756a8217548981a1eb62e504cc37371c9fd51 Mon Sep 17 00:00:00 2001
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
Date: Wed, 27 Oct 2021 13:36:01 +0200
Subject: [PATCH 02/22] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +
src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++
src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++
3 files changed, 20 insertions(+)
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
index 5f5ffde588..27377b737c 100644
--- a/src/mainboard/apple/macbook21/Kconfig
+++ b/src/mainboard/apple/macbook21/Kconfig
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
select HAVE_ACPI_TABLES
select HAVE_ACPI_RESUME
select I945_LVDS
+ select DRIVERS_I2C_CK505
config MAINBOARD_DIR
default "apple/macbook21"
diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c
index 13d06f0839..88b8669c61 100644
--- a/src/mainboard/apple/macbook21/cstates.c
+++ b/src/mainboard/apple/macbook21/cstates.c
@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = {
.addrh = 0,
}
},
+ {
+ .ctype = 3,
+ .latency = 17,
+ .power = 250,
+ .resource = {
+ .space_id = ACPI_ADDRESS_SPACE_FIXED,
+ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
+ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
+ .access_size = ACPI_ACCESS_SIZE_UNDEFINED,
+ .addrl = 0x20,
+ .addrh = 0,
+ }
+ },
};
int get_cst_entries(const acpi_cstate_t **entries)
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
index fd86e939b9..263fbabcd1 100644
--- a/src/mainboard/apple/macbook21/devicetree.cb
+++ b/src/mainboard/apple/macbook21/devicetree.cb
@@ -100,7 +100,13 @@ chip northbridge/intel/i945
end
device pci 1f.3 on # SMBUS
subsystemid 0x8086 0x7270
+ chip drivers/i2c/ck505
+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }"
+ register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }"
+ device i2c 69 on end
+ end
end
+
end
end
end
--
2.39.2
config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch
-23
View File
@@ -1,23 +0,0 @@
From c8332a8bac4986afec6c639f55c5876f83e50b76 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Sun, 3 Jan 2021 03:34:01 +0000
Subject: [PATCH 03/22] lenovo/x60: 64MiB Video RAM changed to default
(previously it was 8MiB)
---
src/mainboard/lenovo/x60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
index 5c3576d1f3..88170a1aab 100644
--- a/src/mainboard/lenovo/x60/cmos.default
+++ b/src/mainboard/lenovo/x60/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2
config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch
-22
View File
@@ -1,22 +0,0 @@
From 2e3ad35c24a86cb3109f4e5139b9ffba931eb80b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Mon, 22 Feb 2021 22:16:59 +0000
Subject: [PATCH 04/22] lenovo/t60: make 64MiB VRAM the default in cmos.default
---
src/mainboard/lenovo/t60/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
index af865f16da..7f03157df7 100644
--- a/src/mainboard/lenovo/t60/cmos.default
+++ b/src/mainboard/lenovo/t60/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
-gfx_uma_size=8M
+gfx_uma_size=64M
--
2.39.2
config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch
-23
View File
@@ -1,23 +0,0 @@
From 5fc03fbf8c7fa30588dab93c76b5532ce03b1610 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:10:33 +0100
Subject: [PATCH 05/22] lenovo/t400: set VRAM to 256MiB VRAM by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/t400/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
index a326e315b1..b907a3e2df 100644
--- a/src/mainboard/lenovo/t400/cmos.default
+++ b/src/mainboard/lenovo/t400/cmos.default
@@ -13,4 +13,4 @@ power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
hybrid_graphics_mode=Integrated Only
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.2
config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch
-23
View File
@@ -1,23 +0,0 @@
From 93f607fed477b3e63b7929808937436ac2898b34 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:11:59 +0100
Subject: [PATCH 06/22] lenovo/x200: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/x200/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
index bb4323836e..458b3f19c5 100644
--- a/src/mainboard/lenovo/x200/cmos.default
+++ b/src/mainboard/lenovo/x200/cmos.default
@@ -12,4 +12,4 @@ sticky_fn=Disable
power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.2
config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch
-23
View File
@@ -1,23 +0,0 @@
From 9faa780b2ac45bc1bf61aa252364ee3158c4cb10 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:18:26 +0100
Subject: [PATCH 07/22] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
index 8372032119..bedad54d2a 100644
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
-gfx_uma_size=64M
+gfx_uma_size=256M
--
2.39.2
config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch
-23
View File
@@ -1,23 +0,0 @@
From f1c59cd67446303a5cdf9107461247a63f894de3 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:21:39 +0100
Subject: [PATCH 08/22] acer/g43t-am3: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/acer/g43t-am3/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
index 706f5dd551..e8b45ea22c 100644
--- a/src/mainboard/acer/g43t-am3/cmos.default
+++ b/src/mainboard/acer/g43t-am3/cmos.default
@@ -3,4 +3,4 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=64M
+gfx_uma_size=256M
--
2.39.2
config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch
-34
View File
@@ -1,34 +0,0 @@
From 75858ba200a2a5835bca0af9b5f508a52ed978de Mon Sep 17 00:00:00 2001
From: persmule <persmule@gmail.com>
Date: Sun, 31 Oct 2021 23:33:26 +0000
Subject: [PATCH 09/22] lenovo/t400: Enable all SATA ports
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
chassis, and another one on its dock.
They have to be unmasked via device tree to use.
This patch unmasked all SATA ports found within t400s with factory firmware.
---
src/mainboard/lenovo/t400/devicetree.cb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
index 259c3e1b21..3d007533a4 100644
--- a/src/mainboard/lenovo/t400/devicetree.cb
+++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
register "gpe0_en" = "0x01000000"
register "gpi1_routing" = "2"
- # Set AHCI mode, enable ports 1 and 2.
- register "sata_port_map" = "0x03"
+ # Set AHCI mode, enable ports 1, 2, 5 and 6.
+ register "sata_port_map" = "0x33"
register "sata_clock_request" = "0"
register "sata_traffic_monitor" = "0"
--
2.39.2
config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch
-22
View File
@@ -1,22 +0,0 @@
From 2c103a71a37eb4db9d33928b2371a682ca04e65f Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 20 Dec 2021 01:29:31 +0000
Subject: [PATCH 10/22] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
default
---
src/mainboard/lenovo/x230/cmos.default | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 7314066c2b..2e315d4521 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
me_state=Normal
+gfx_uma_size=224M
--
2.39.2
config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch
-38
View File
@@ -1,38 +0,0 @@
From 040f15039fa59d70cd54b8fff5d947e155666aa1 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 3 Jan 2022 19:06:22 +0000
Subject: [PATCH 11/22] lenovo/x230: set me_state=Disabled in cmos.default
I only recently found out about this. It's possible to use me_cleaner to
do the same thing, but some people might just flash coreboot and not do
anything with the ME region
With this change, the ME is set to disabled. It's my understanding that this
will accomplish more or less the same thing as me_cleaner, without actually
using that. Of course, I still recommend using me_cleaner
I saw this when I audited coreboot's git history, and saw this:
commit 833e9bad4762e0dca6c867d3a18dbaf6d5166be8
Author: Evgeny Zinoviev <me@ch1p.io>
Date: Thu Nov 21 21:47:31 2019 +0300
sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode
---
src/mainboard/lenovo/x230/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 2e315d4521..3585cbd58b 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -15,5 +15,5 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
gfx_uma_size=224M
--
2.39.2
config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch
-122
View File
@@ -1,122 +0,0 @@
From 81febff42c66bd53e44176f14b651339b503a9f3 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 2 Mar 2022 21:50:01 +0000
Subject: [PATCH 12/22] set me_state=Disabled on all cmos.default files!
yeah. why the hell isn't this the default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/lenovo/l520/cmos.default | 2 +-
src/mainboard/lenovo/t420/cmos.default | 2 +-
src/mainboard/lenovo/t420s/cmos.default | 2 +-
src/mainboard/lenovo/t430/cmos.default | 2 +-
src/mainboard/lenovo/t430s/cmos.default | 2 +-
src/mainboard/lenovo/t520/cmos.default | 2 +-
src/mainboard/lenovo/t530/cmos.default | 2 +-
src/mainboard/lenovo/x220/cmos.default | 2 +-
src/mainboard/protectli/vault_cml/cmos.default | 2 +-
src/mainboard/system76/tgl-u/cmos.default | 2 +-
10 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
index 681c40e78b..57cdcf9162 100644
--- a/src/mainboard/lenovo/l520/cmos.default
+++ b/src/mainboard/lenovo/l520/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
trackpoint=Enable
backlight=Both
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
index 8244071b8a..c011867916 100644
--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
index 8244071b8a..c011867916 100644
--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
index 26795fe5cf..55e1e6c04e 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
hybrid_graphics_mode=Integrated Only
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
index 52dbf70377..b16800ca9e 100644
--- a/src/mainboard/lenovo/t430s/cmos.default
+++ b/src/mainboard/lenovo/t430s/cmos.default
@@ -16,4 +16,4 @@ backlight=Both
enable_dual_graphics=Disable
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
index cf79b391e2..b66f7034dc 100644
--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
index cf79b391e2..b66f7034dc 100644
--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
index 6d1d57a795..52f303dfdb 100644
--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
@@ -13,4 +13,4 @@ usb_always_on=Disable
fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
index 62715bc6ba..129b5fd121 100644
--- a/src/mainboard/protectli/vault_cml/cmos.default
+++ b/src/mainboard/protectli/vault_cml/cmos.default
@@ -1,3 +1,3 @@
boot_option=Fallback
debug_level=Debug
-me_state=Enable
+me_state=Disabled
diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
index 62715bc6ba..129b5fd121 100644
--- a/src/mainboard/system76/tgl-u/cmos.default
+++ b/src/mainboard/system76/tgl-u/cmos.default
@@ -1,3 +1,3 @@
boot_option=Fallback
debug_level=Debug
-me_state=Enable
+me_state=Disabled
--
2.39.2
config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch
-198
View File
@@ -1,198 +0,0 @@
From c73269315626678c191ea494338581abdc417f21 Mon Sep 17 00:00:00 2001
From: Alexander Couzens <lynxis@fe80.eu>
Date: Sat, 19 Mar 2022 13:42:33 +0000
Subject: [PATCH 13/22] lenovo/x230: introduce FHD variant
There is a modification for the x230 which uses the 2nd DP from the dock
as the integrated panel's connection, which allows using a custom eDP
panel instead of the stock LVDS display.
There are several adapter boards present on the market and all of them
uses the same method of enabling the custom eDP panel.
To make this work with coreboot, the internal LVDS connector should be
disabled in libgfxinit. The VBT has been modified as well, which allows
brightness controls to work out of the box.
The modifications done to the VBT are:
- Remove the LVDS port entry.
- Move the DP-3 (which is the 2nd DP on the dock) entry to the first
position on the list.
- Set the DP-3 as internally connected.
This has been reported to work with the following panels:
- LP125WF2-SPB4 (1920*1080, 12.5")
- LQ125T1JW02 (2560*1440, 12.5")
- LQ133M1JW21 (1920*1080, 13.3")
- LTN133HL10-201 (1920*1080, 13.3")
- B133HAN04.6 (1920*1080, 13.3")
- B133QAN02.0 (2560*1600, 13.3")
Other eDP panels not on this list should work as well.
Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
---
src/mainboard/lenovo/x230/Kconfig | 15 ++++++++-----
src/mainboard/lenovo/x230/Kconfig.name | 3 +++
src/mainboard/lenovo/x230/Makefile.inc | 5 +++++
.../lenovo/x230/variants/x230_edp/data.vbt | Bin 0 -> 4281 bytes
.../x230/variants/x230_edp/gma-mainboard.ads | 21 ++++++++++++++++++
5 files changed, 38 insertions(+), 6 deletions(-)
create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
index 279095629b..acfd0ed561 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -1,4 +1,4 @@
-if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S
+if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
config BOARD_SPECIFIC_OPTIONS
def_bool y
@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
select H8_HAS_BAT_THRESHOLDS_IMPL
select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S
select NO_UART_ON_SUPERIO
- select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+ select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S
select HAVE_ACPI_TABLES
select HAVE_OPTION_TABLE
@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
select INTEL_INT15
select DRIVERS_RICOH_RCE822
select MEMORY_MAPPED_TPM
- select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+ select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
select MAINBOARD_HAS_LIBGFXINIT
select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
select INTEL_GMA_HAVE_VBT
@@ -47,17 +47,20 @@ config MAINBOARD_DIR
default "lenovo/x230"
config VARIANT_DIR
- default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+ default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
default "x230s" if BOARD_LENOVO_X230S
config MAINBOARD_PART_NUMBER
- default "ThinkPad X230" if BOARD_LENOVO_X230
+ default "ThinkPad X230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230_EDP
default "ThinkPad X230t" if BOARD_LENOVO_X230T
default "ThinkPad X230s" if BOARD_LENOVO_X230S
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+config INTEL_GMA_VBT_FILE
+ default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
+
config USBDEBUG_HCD_INDEX
int
default 2
@@ -79,4 +82,4 @@ config PS2M_EISAID
config THINKPADEC_HKEY_EISAID
default "LEN0068"
-endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S
+endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name
index 1a01436879..e7290a12dd 100644
--- a/src/mainboard/lenovo/x230/Kconfig.name
+++ b/src/mainboard/lenovo/x230/Kconfig.name
@@ -6,3 +6,6 @@ config BOARD_LENOVO_X230T
config BOARD_LENOVO_X230S
bool "ThinkPad X230s"
+
+config BOARD_LENOVO_X230_EDP
+ bool "ThinkPad X230 eDP Mod (2K/FHD)"
diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc
index 8e801f145d..6e6f9f90b9 100644
--- a/src/mainboard/lenovo/x230/Makefile.inc
+++ b/src/mainboard/lenovo/x230/Makefile.inc
@@ -5,4 +5,9 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
romstage-y += variants/$(VARIANT_DIR)/early_init.c
romstage-y += variants/$(VARIANT_DIR)/gpio.c
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
+
+ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y)
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads
+else
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+endif
diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt b/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
GIT binary patch
literal 4281
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zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT
zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
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zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
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z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
literal 0
HcmV?d00001
diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
new file mode 100644
index 0000000000..f7cf0bc264
--- /dev/null
+++ b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
@@ -0,0 +1,21 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP1,
+ DP2,
+ DP3,
+ HDMI1,
+ HDMI2,
+ HDMI3,
+ Analog,
+ others => Disabled);
+
+end GMA.Mainboard;
--
2.39.2
config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch
-25
View File
@@ -1,25 +0,0 @@
From c32229e3f82c00abb2bee4d0f7ddf33d4c7a04dc Mon Sep 17 00:00:00 2001
From: Alexei Sorokin <sor.alexei@meowr.ru>
Date: Sun, 27 Nov 2022 18:36:26 +0300
Subject: [PATCH 14/22] lenovo/x230: fix the data.vbt path for the EDP variant
---
src/mainboard/lenovo/x230/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
index acfd0ed561..34108c3c04 100644
--- a/src/mainboard/lenovo/x230/Kconfig
+++ b/src/mainboard/lenovo/x230/Kconfig
@@ -59,7 +59,7 @@ config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config INTEL_GMA_VBT_FILE
- default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
+ default "src/mainboard/\$(MAINBOARDDIR)/variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
config USBDEBUG_HCD_INDEX
int
--
2.39.2
config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
-205
View File
@@ -1,205 +0,0 @@
From 38c76afbea4abfed2976bfbe10977e41f21665b0 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
Subject: [PATCH 15/22] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
Example:
./ifdtool --nuke gbe coreboot.rom
./ifdtool --nuke bios coreboot.com
./ifdtool --nuke me coreboot.com
Rebased since the last revision update in lbmk.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
1 file changed, 83 insertions(+), 31 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index ddbc0fb91b..7af9235ae3 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1847,6 +1847,7 @@ static void print_usage(const char *name)
" wbg - Wellsburg\n"
" -S | --setpchstrap Write a PCH strap\n"
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
"<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
@@ -1854,6 +1855,60 @@ static void print_usage(const char *name)
"\n");
}
+static int
+get_region_type_string(const char *region_type_string)
+{
+ if (!strcasecmp("Descriptor", region_type_string))
+ return 0;
+ else if (!strcasecmp("BIOS", region_type_string))
+ return 1;
+ else if (!strcasecmp("ME", region_type_string))
+ return 2;
+ else if (!strcasecmp("GbE", region_type_string))
+ return 3;
+ else if (!strcasecmp("Platform Data", region_type_string))
+ return 4;
+ else if (!strcasecmp("Device Exp1", region_type_string))
+ return 5;
+ else if (!strcasecmp("Secondary BIOS", region_type_string))
+ return 6;
+ else if (!strcasecmp("Reserved", region_type_string))
+ return 7;
+ else if (!strcasecmp("EC", region_type_string))
+ return 8;
+ else if (!strcasecmp("Device Exp2", region_type_string))
+ return 9;
+ else if (!strcasecmp("IE", region_type_string))
+ return 10;
+ else if (!strcasecmp("10GbE_0", region_type_string))
+ return 11;
+ else if (!strcasecmp("10GbE_1", region_type_string))
+ return 12;
+ else if (!strcasecmp("PTT", region_type_string))
+ return 15;
+ return -1;
+}
+
+static void
+nuke(const char *filename, char *image, int size, int region_type)
+{
+ int i;
+ struct region region;
+ const struct frba *frba = find_frba(image, size);
+ if (!frba)
+ exit(EXIT_FAILURE);
+
+ region = get_region(frba, region_type);
+ if (region.size > 0) {
+ for (i = region.base; i <= region.limit; i++) {
+ if ((i + 1) > (size))
+ break;
+ image[i] = 0xFF;
+ }
+ write_image(filename, image, size);
+ }
+}
+
int main(int argc, char *argv[])
{
int opt, option_index = 0;
@@ -1861,6 +1916,7 @@ int main(int argc, char *argv[])
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
+ int mode_nuke = 0;
char *region_type_string = NULL, *region_fname = NULL;
const char *layout_fname = NULL;
char *new_filename = NULL;
@@ -1892,6 +1948,7 @@ int main(int argc, char *argv[])
{"validate", 0, NULL, 't'},
{"setpchstrap", 1, NULL, 'S'},
{"newvalue", 1, NULL, 'V'},
+ {"nuke", 1, NULL, 'N'},
{0, 0, 0, 0}
};
@@ -1941,35 +1998,8 @@ int main(int argc, char *argv[])
region_fname++;
// Descriptor, BIOS, ME, GbE, Platform
// valid type?
- if (!strcasecmp("Descriptor", region_type_string))
- region_type = 0;
- else if (!strcasecmp("BIOS", region_type_string))
- region_type = 1;
- else if (!strcasecmp("ME", region_type_string))
- region_type = 2;
- else if (!strcasecmp("GbE", region_type_string))
- region_type = 3;
- else if (!strcasecmp("Platform Data", region_type_string))
- region_type = 4;
- else if (!strcasecmp("Device Exp1", region_type_string))
- region_type = 5;
- else if (!strcasecmp("Secondary BIOS", region_type_string))
- region_type = 6;
- else if (!strcasecmp("Reserved", region_type_string))
- region_type = 7;
- else if (!strcasecmp("EC", region_type_string))
- region_type = 8;
- else if (!strcasecmp("Device Exp2", region_type_string))
- region_type = 9;
- else if (!strcasecmp("IE", region_type_string))
- region_type = 10;
- else if (!strcasecmp("10GbE_0", region_type_string))
- region_type = 11;
- else if (!strcasecmp("10GbE_1", region_type_string))
- region_type = 12;
- else if (!strcasecmp("PTT", region_type_string))
- region_type = 15;
- if (region_type == -1) {
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
fprintf(stderr, "No such region type: '%s'\n\n",
region_type_string);
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
@@ -2135,6 +2165,22 @@ int main(int argc, char *argv[])
case 't':
mode_validate = 1;
break;
+ case 'N':
+ region_type_string = strdup(optarg);
+ if (!region_type_string) {
+ fprintf(stderr, "No region specified\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
+ fprintf(stderr, "No such region type: '%s'\n\n",
+ region_type_string);
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ mode_nuke = 1;
+ break;
case 'v':
print_version();
exit(EXIT_SUCCESS);
@@ -2150,7 +2196,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
- mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) {
+ mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
+ mode_nuke) > 1) {
fprintf(stderr, "You may not specify more than one mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2158,7 +2205,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
- mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
+ mode_locked + mode_unlocked + mode_density + mode_altmedisable +
+ mode_validate + mode_nuke) == 0) {
fprintf(stderr, "You need to specify a mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2262,6 +2310,10 @@ int main(int argc, char *argv[])
write_image(new_filename, image, size);
}
+ if (mode_nuke) {
+ nuke(new_filename, image, size, region_type);
+ }
+
if (mode_altmedisable) {
struct fpsba *fpsba = find_fpsba(image, size);
struct fmsba *fmsba = find_fmsba(image, size);
--
2.39.2
config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
-47
View File
@@ -1,47 +0,0 @@
From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
Enabling PECI without microcode updates loaded causes the CPUID feature set
to become corrupted. And one consequence is broken SpeedStep. At least, that's
my understanding looking at Intel Errata. This revert is not a fix, because
upstream is correct (upstream assumes microcode updates). We will simply
maintain this revert patch in Libreboot, from now on.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 315e7c36fc..1423fd72bc 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
}
-#define IA32_PECI_CTL 0x5a0
-
static void configure_misc(const int eist, const int tm2, const int emttm)
{
msr_t msr;
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
}
-
- /* Enable PECI
- WARNING: due to Erratum AW67 described in Intel document #318733
- the microcode must be updated before this MSR is written to. */
- msr = rdmsr(IA32_PECI_CTL);
- msr.lo |= 1;
- wrmsr(IA32_PECI_CTL, msr);
}
#define PIC_SENS_CFG 0x1aa
--
2.39.2
config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
-173
View File
@@ -1,173 +0,0 @@
From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
While this fix is *technically correct*, the one in
coreboot, it breaks rebooting as tested on several
GM45 ThinkPads e.g. X200, T400, when microcode
updates are not applied.
Since November 2022, Libreboot includes microcode
updates by default, but it tells users how to remove
it from the ROM (with cbfstool) if they wish.
Well, with Libreboot 20221214, 20230319 and 20230413,
mitigations present in Libreboot 20220710 (which did
not have microcode updates) do not exist.
This patch, along with the other patch to remove PECI
support (which breaks speedstep when microcode updates
are not applied) have now been re-added to Libreboot.
It is still best to use microcode updates by default.
These patches in coreboot are not critically urgent,
and you can use the machines with or without them,
regardless of ucode.
I'll probably re-write this and the other patch at
some point, applying the change conditionally upon
whether or not microcode is applied.
Pragmatism is a good thing. I recommend it.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
5 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 1423fd72bc..d1f98ca43a 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -8,6 +8,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
#define MSR_BBL_CR_CTL3 0x11e
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states(quad);
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index bc53214310..72f40f6762 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
smm_initialize();
}
-#define SMRR_SUPPORTED (1 << 11)
-
static void per_cpu_smm_trigger(void)
{
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
- set_feature_ctrl_vmx();
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
- /* We don't care if the lock is already setting
- as our smm relocation handler is able to handle
- setups where SMRR is not enabled here. */
- if (ia32_ft_ctrl.lo & (1 << 0)) {
- /* IA32_FEATURE_CONTROL locked. If we set it again we
- get an illegal instruction. */
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
- } else {
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
- printk(BIOS_INFO,
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
- }
- } else {
- set_vmx_and_lock();
- }
-
/* Relocate the SMM handler. */
smm_relocate();
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 05f5f327cc..0450c2ad83 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 5bd1c32815..f3bb08cde3 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 535fb8fae7..f7b05facd2 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
--
2.39.2
config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
-28
View File
@@ -1,28 +0,0 @@
From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for
dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6400/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
index bb954cbd7b..e9f3915d17 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
+++ b/src/mainboard/dell/e6400/devicetree.cb
@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
ops gm45_pci_domain_ops
device pci 00.0 on end # host bridge
- device pci 01.0 off end
+ device pci 01.0 on end
device pci 02.0 on end # VGA
device pci 02.1 on end # Display
device pci 03.0 on end # ME
--
2.39.2
config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
-39
View File
@@ -1,39 +0,0 @@
From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 19/22] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
roms without a payload resulting in a no boot situation, but in
libreboot lbmk handles the payload and thus this warning always comes
up. This has caused confusion and concern so just patch it out.
---
payloads/Makefile.inc | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
index e735443a76..4f1692a873 100644
--- a/payloads/Makefile.inc
+++ b/payloads/Makefile.inc
@@ -49,16 +49,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
-files_added:: warn_no_payload
-endif
-
-warn_no_payload:
- printf "\n\t** WARNING **\n"
- printf "coreboot has been built without a payload. Writing\n"
- printf "a coreboot image without a payload to your board's\n"
- printf "flash chip will result in a non-booting system. You\n"
- printf "can use cbfstool to add a payload to the image.\n\n"
-
.PHONY: force-payload coreinfo nvramcui
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
2.39.2
config/coreboot/default/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch
-61
View File
@@ -1,61 +0,0 @@
From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 27 Aug 2023 17:36:36 -0600
Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios
These were determined by sniffing the LPC bus while toggling the
hardware wireless switch on the Latitude E6400. To differentiate devices
options in the vendor BIOS to change which radios the switch controlled
were used.
Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/mec5035.c | 9 +++++++++
src/ec/dell/mec5035/mec5035.h | 8 ++++++++
2 files changed, 17 insertions(+)
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index 8da11e5b1c..e0335a4635 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting)
return buf[0];
}
+void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on)
+{
+ /* From LPC traces and userspace testing with other values,
+ the second byte has to be 2 for an unknown reason. */
+ u8 buf[3] = {dev, 2, on};
+ write_mailbox_regs(buf, 2, 3);
+ ec_command(CMD_RADIO_EN);
+}
+
void mec5035_early_init(void)
{
/* If this isn't sent the EC shuts down the system after about 15
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index e7a05b64d4..16512e2cc2 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -16,8 +16,16 @@
#define CMD_CPU_OK 0xc2
+#define CMD_RADIO_EN 0x2b
+enum mec5035_radio_dev {
+ RADIO_WLAN = 0,
+ RADIO_WWAN = 1,
+ RADIO_WPAN = 2,
+};
+
u8 mec5035_mouse_touchpad(u8 setting);
void mec5035_cpu_ok(void);
void mec5035_early_init(void);
+void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on);
#endif /* _EC_DELL_MEC5035_H_ */
--
2.39.2
config/coreboot/default/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch
-37
View File
@@ -1,37 +0,0 @@
From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 27 Aug 2023 19:15:37 -0600
Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API
Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/mec5035.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index e0335a4635..20a33cc0ad 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -4,6 +4,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pnp.h>
+#include <option.h>
#include <pc80/keyboard.h>
#include <stdint.h>
#include "mec5035.h"
@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev)
mec5035_mouse_touchpad(TP_PS2_MOUSE);
pc_keyboard_init(NO_AUX_DEVICE);
+
+ mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1));
+ mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1));
+ mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1));
}
static struct device_operations ops = {
--
2.39.2
config/coreboot/default/patches/0022-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch
-821
View File
@@ -1,821 +0,0 @@
From b37175381a32d9d308b5c1d67e11cdc57a24c820 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 19 Aug 2023 16:19:10 -0600
Subject: [PATCH] mb/dell: Add Latitude E6430 (Ivy Bridge)
Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested.
This is based on the autoport output with some manual tweaks. The flash
is 8MiB + 4MiB, and is fairly easily accessed by removing the keyboard.
It can also be internally flashed by sending a command to the EC, which
causes the EC to pull the FDO pin low and the firmware to skip setting
up any chipset based write protections. [1] The EC is the SMSC MEC5055,
which seems to be compatible with the existing MEC5035 code.
Working:
- Libgfxinit
- USB EHCI debug (left side usb port is HCD index 2, middle port on the
right side is HCD index 1)
- Keyboard
- Touchpad/trackpoint
- ExpressCard
- Audio
- Ethernet
- SD card reader
- mPCIe WiFi
- SeaBIOS 1.16.2
- edk2 (MrChromebox' fork, uefipayload_202306)
- Internal flashing
Not working:
- S3 suspend: It seems like the EC also controls the DRAM reset gate so
there may be a command that needs to be implemented for this
- Physical Wireless switch
- Battery reporting
- Brightness hotkeys
Unknown/untested:
- Dock
- eSATA
- TPM
- dGPU on non-UMA model
[1] https://github.com/nic3-14159/e6400-flash-unlock
Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6430/Kconfig | 37 ++++
src/mainboard/dell/e6430/Kconfig.name | 2 +
src/mainboard/dell/e6430/Makefile.inc | 6 +
src/mainboard/dell/e6430/acpi/ec.asl | 9 +
src/mainboard/dell/e6430/acpi/platform.asl | 12 ++
src/mainboard/dell/e6430/acpi/superio.asl | 3 +
src/mainboard/dell/e6430/acpi_tables.c | 16 ++
src/mainboard/dell/e6430/board_info.txt | 6 +
src/mainboard/dell/e6430/cmos.default | 9 +
src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++
src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes
src/mainboard/dell/e6430/devicetree.cb | 68 ++++++++
src/mainboard/dell/e6430/dsdt.asl | 30 ++++
src/mainboard/dell/e6430/early_init.c | 38 ++++
src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++
src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++
src/mainboard/dell/e6430/hda_verb.c | 33 ++++
src/mainboard/dell/e6430/mainboard.c | 21 +++
18 files changed, 590 insertions(+)
create mode 100644 src/mainboard/dell/e6430/Kconfig
create mode 100644 src/mainboard/dell/e6430/Kconfig.name
create mode 100644 src/mainboard/dell/e6430/Makefile.inc
create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl
create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl
create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl
create mode 100644 src/mainboard/dell/e6430/acpi_tables.c
create mode 100644 src/mainboard/dell/e6430/board_info.txt
create mode 100644 src/mainboard/dell/e6430/cmos.default
create mode 100644 src/mainboard/dell/e6430/cmos.layout
create mode 100644 src/mainboard/dell/e6430/data.vbt
create mode 100644 src/mainboard/dell/e6430/devicetree.cb
create mode 100644 src/mainboard/dell/e6430/dsdt.asl
create mode 100644 src/mainboard/dell/e6430/early_init.c
create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e6430/gpio.c
create mode 100644 src/mainboard/dell/e6430/hda_verb.c
create mode 100644 src/mainboard/dell/e6430/mainboard.c
diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
new file mode 100644
index 0000000000..ea691aeb4e
--- /dev/null
+++ b/src/mainboard/dell/e6430/Kconfig
@@ -0,0 +1,37 @@
+if BOARD_DELL_LATITUDE_E6430
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+ default "dell/e6430"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E6430"
+
+config VGA_BIOS_ID
+ default "8086,0166"
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config USBDEBUG_HCD_INDEX
+ default 2
+endif
diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
new file mode 100644
index 0000000000..f866b03585
--- /dev/null
+++ b/src/mainboard/dell/e6430/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6430
+ bool "Latitude E6430"
diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e6430/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e6430/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt
new file mode 100644
index 0000000000..4601a4aaba
--- /dev/null
+++ b/src/mainboard/dell/e6430/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
new file mode 100644
index 0000000000..2a5b30f2b7
--- /dev/null
+++ b/src/mainboard/dell/e6430/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Normal
diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
new file mode 100644
index 0000000000..e85ea4c661
--- /dev/null
+++ b/src/mainboard/dell/e6430/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+415 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d
GIT binary patch
literal 6144
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zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;)
zjkMh#DR=zcpL5Use9xJ4?#x^=mKdcQb|t!Zj3v6R-<{Yod<{*&!ppI%xUMXT9lLMX
zn;IM)+?yEQoxF~o#5x>}{dfwPkR;RSiC=!jj_JAlRQpJWpd}$VY+XtFX9|?cO&y#m
z<SE`uGt*OdcG7S%MVsQ5GkI`wn)VeYZ#ytIou8d0Yb)J)AUAzmo)Vpuq&7;?RQ_;&
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zqL5SnLUq0r*kw>Q!0PGk>)$?LCsIS{ox_=t(Xs5!w-o>M=erl0apv_Z`-(^w_5@pz
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z0g?6TPW!DC<JKR&l%Knmp5z$x;*#X7@7xT>ql9>N1GN_$T-UVr&HErC5juykd~Sxy
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z7FKz(x)t4R_RHf7I)6EA!d)M`R($wttvJgMee=p9zrFL_EL#DYA0wUzD?Ryj%h>lB
ztg|e-5!;@t?uT+rR=1)e9yp?8gwNW88`Zyt!8rx=+B{i(4~DY`_-WO>sGeD;nsGcs
z7h1ZN6srJX#Uke;d$JhpccQxNhw2Qz?Zw91`@8IHm-n!7{19~*_}LvecV2YZ7%!rJ
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qS<b6g={WLAp3+&R^8(yo-t$_!=7BX2ta)I~18W{w^T5By1OEis_@J`@
literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
new file mode 100644
index 0000000000..56dd9e5fe2
--- /dev/null
+++ b/src/mainboard/dell/e6430/devicetree.cb
@@ -0,0 +1,68 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00001312"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x0534 inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 off end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x005c0921"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x007c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end # USB 3.0 Controller
+ device ref mei1 on end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+ device ref me_kt on end # Management Engine KT
+ device ref gbe on end # Intel Gigabit Ethernet
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda on end # High Definition Audio
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3
+ device ref pcie_rp4 on end # PCIe Port #4
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref ehci1 on end # USB2 EHCI #1
+ device ref pci_bridge off end # PCI bridge
+ device ref lpc on # LPC bridge
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end # SATA Controller 1
+ device ref smbus on end # SMBus
+ device ref sata2 off end # SATA Controller 2
+ device ref thermal off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/dell/e6430/dsdt.asl b/src/mainboard/dell/e6430/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e6430/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
new file mode 100644
index 0000000000..7944157f59
--- /dev/null
+++ b/src/mainboard/dell/e6430/early_init.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 0, 2 },
+ { 1, 1, 2 },
+ { 1, 1, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 2, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ mec5035_early_init();
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
new file mode 100644
index 0000000000..1310830c8e
--- /dev/null
+++ b/src/mainboard/dell/e6430/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, --mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c
new file mode 100644
index 0000000000..777570765a
--- /dev/null
+++ b/src/mainboard/dell/e6430/gpio.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c
new file mode 100644
index 0000000000..56ada95c58
--- /dev/null
+++ b/src/mainboard/dell/e6430/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x10280534, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280534),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e6430/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.42.0
config/coreboot/default/patches/0023-HACK-Disable-coreboot-related-BL31-features.patch
-28
View File
@@ -1,28 +0,0 @@
From 9f52555eac217623ad2edc72492f9ded6a5b538d Mon Sep 17 00:00:00 2001
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Date: Thu, 22 Jun 2023 16:44:27 +0300
Subject: [PATCH] HACK: Disable coreboot related BL31 features
I don't know why, but removing this BL31 make argument lets gru-kevin
power off properly when shut down from Linux. Needs investigation.
---
src/arch/arm64/Makefile.inc | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
index 6b49743633c3..e1982d92cc5c 100644
--- a/src/arch/arm64/Makefile.inc
+++ b/src/arch/arm64/Makefile.inc
@@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
# Always enable crash reporting, even on a release build
BL31_MAKEARGS += CRASH_REPORTING=1
-# Enable coreboot-specific features like CBMEM console support
-BL31_MAKEARGS += COREBOOT=1
-
# Avoid build/release|build/debug distinction by overriding BUILD_PLAT directly
BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
--
2.40.1
config/coreboot/default/patches/0024-don-t-use-github-for-the-acpica-download.patch
-39
View File
@@ -1,39 +0,0 @@
From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 22 Oct 2023 15:02:25 +0100
Subject: [PATCH 1/1] don't use github for the acpica download
i have the tarball from a previous download, and i placed
it on libreboot rsync, which then got mirrored to princeton.
today, github's ssl cert was b0rking the hell out and i really
really wanted to finish a build, and didn't want to wait for
github to fix their httpd.
so i'm now hosting this specific acpica tarball on rsync.
this patch makes that URL be used, instead of the github one.
that's the 2nd time i've had to patch coreboot's acpica download!
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index ebc9fcb49a..a857110b4b 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2
config/coreboot/default/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch
-341
View File
@@ -1,341 +0,0 @@
From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 29 Oct 2023 01:18:50 +0000
Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
value"
This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
NOTE:
this is done instead of merging:
https://review.coreboot.org/c/coreboot/+/78623
which is still under review for now
the patch i'm reverting is this one:
https://review.coreboot.org/c/coreboot/+/78270
this was actually only merged the day before i
updated coreboot revs in lbmk to the 12 october rev,
so there's no harm in quickly reverting this for now
however, later on, we will rely on the other patch
---
src/Kconfig | 3 ++-
src/cpu/qemu-x86/Kconfig | 3 +++
src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
src/northbridge/amd/pi/Kconfig | 4 ++++
src/soc/amd/picasso/Kconfig | 4 ++++
src/soc/amd/stoneyridge/Kconfig | 4 ++++
src/soc/cavium/cn81xx/Kconfig | 3 +++
src/soc/intel/alderlake/Kconfig | 5 +++++
src/soc/intel/apollolake/Kconfig | 4 ++++
src/soc/intel/cannonlake/Kconfig | 4 ++++
src/soc/intel/elkhartlake/Kconfig | 4 ++++
src/soc/intel/jasperlake/Kconfig | 4 ++++
src/soc/intel/meteorlake/Kconfig | 5 +++++
src/soc/intel/skylake/Kconfig | 4 ++++
src/soc/intel/tigerlake/Kconfig | 4 ++++
src/soc/intel/xeon_sp/Kconfig | 4 ++++
src/soc/intel/xeon_sp/cpx/Kconfig | 4 ++++
src/soc/intel/xeon_sp/skx/Kconfig | 4 ++++
src/soc/intel/xeon_sp/spr/Kconfig | 4 ++++
src/soc/qualcomm/ipq40xx/Kconfig | 4 ++++
20 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/src/Kconfig b/src/Kconfig
index ae8024089e..1549719dd0 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -751,7 +751,8 @@ config RTC
config HEAP_SIZE
hex
- default 0x100000
+ default 0x100000 if FLATTENED_DEVICE_TREE
+ default 0x4000
config STACK_SIZE
hex
diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
index 0fa999e1ac..f3e2c4cea9 100644
--- a/src/cpu/qemu-x86/Kconfig
+++ b/src/cpu/qemu-x86/Kconfig
@@ -35,4 +35,7 @@ config MAX_CPUS
default 32 if SMM_TSEG
default 4
+config HEAP_SIZE
+ default 0x8000
+
endif
diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
index 7bc3b0bcbb..7f9300f2a7 100644
--- a/src/mainboard/sifive/hifive-unleashed/Kconfig
+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
select FLATTENED_DEVICE_TREE
select SPI_SDCARD
+config HEAP_SIZE
+ default 0x10000
+
config MAINBOARD_DIR
default "sifive/hifive-unleashed"
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
index 4ffe82a15f..4518db149b 100644
--- a/src/northbridge/amd/pi/Kconfig
+++ b/src/northbridge/amd/pi/Kconfig
@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x200000
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
endif # NORTHBRIDGE_AMD_PI
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index c33f287067..796fe4eb13 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
bool
default n
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
config SERIRQ_CONTINUOUS_MODE
bool
default n
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 6ff135e6a8..9af7455bae 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
bool
default n
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
config EHCI_BAR
hex
default 0xfef00000
diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
index 77ca97202b..368581f8f1 100644
--- a/src/soc/cavium/cn81xx/Kconfig
+++ b/src/soc/cavium/cn81xx/Kconfig
@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
int
default 1
+config HEAP_SIZE
+ default 0x10000
+
config STACK_SIZE
default 0x2000
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 4b960c1d22..82ec8f263e 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -215,6 +215,11 @@ config IED_REGION_SIZE
hex
default 0x400000
+config HEAP_SIZE
+ hex
+ default 0x80000 if BMP_LOGO
+ default 0x10000
+
config GFX_GMA_DEFAULT_MMIO
default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 78ec2987ce..bce935d800 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
help
Name of file to store in the IFWI region.
+config HEAP_SIZE
+ hex
+ default 0x8000
+
config MAX_ROOT_PORTS
int
default 6
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index a42a3c365b..80237f9810 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -160,6 +160,10 @@ config IED_REGION_SIZE
hex
default 0x400000
+config HEAP_SIZE
+ hex
+ default 0x8000
+
config NHLT_DMIC_1CH_16B
bool
depends on ACPI_NHLT
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 3361c0ddb9..7f1c767379 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -104,6 +104,10 @@ config IED_REGION_SIZE
hex
default 0x0
+config HEAP_SIZE
+ hex
+ default 0x8000
+
config MAX_ROOT_PORTS
int
default 7
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 3d84991e09..ff5def3263 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -106,6 +106,10 @@ config IED_REGION_SIZE
hex
default 0x400000
+config HEAP_SIZE
+ hex
+ default 0x8000
+
config MAX_ROOT_PORTS
int
default 8
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 590e8b80e1..48030a1911 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -197,6 +197,11 @@ config IED_REGION_SIZE
hex
default 0x400000
+config HEAP_SIZE
+ hex
+ default 0x80000 if BMP_LOGO
+ default 0x10000
+
# Intel recommends reserving the PCIe TBT root port resources as below:
# - 42 buses
# - 194 MiB Non-prefetchable memory
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index e0df501460..d6a11363ee 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
help
If you set this option to n, will not use native SD controller.
+config HEAP_SIZE
+ hex
+ default 0x80000
+
config IED_REGION_SIZE
hex
default 0x400000
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index c07a0d8365..0a4b7bfdb8 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -152,6 +152,10 @@ config IED_REGION_SIZE
config INTEL_TME
default n
+config HEAP_SIZE
+ hex
+ default 0x10000
+
config MAX_ROOT_PORTS
int
default 24 if SOC_INTEL_TIGERLAKE_PCH_H
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index e63bee5451..63ced01067 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BUS_NUMBER
default 256
+config HEAP_SIZE
+ hex
+ default 0x80000
+
config HPET_MIN_TICKS
hex
default 0x80
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index ac166c3038..f54f7716b6 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
hex
default 0x7C00
+config HEAP_SIZE
+ hex
+ default 0x80000
+
config STACK_SIZE
hex
default 0x4000
diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
index 5d843878e1..c2c3d4e2e8 100644
--- a/src/soc/intel/xeon_sp/skx/Kconfig
+++ b/src/soc/intel/xeon_sp/skx/Kconfig
@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
hex
default 0x7C00
+config HEAP_SIZE
+ hex
+ default 0x80000
+
config IED_REGION_SIZE
hex
default 0x400000
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 43b87ade14..b1c4c783b7 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
hex
default 0x8c00
+config HEAP_SIZE
+ hex
+ default 0x80000
+
config STACK_SIZE
hex
default 0x4000
diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
index 0ce92731c0..0eabb00752 100644
--- a/src/soc/qualcomm/ipq40xx/Kconfig
+++ b/src/soc/qualcomm/ipq40xx/Kconfig
@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
help
Path for utils to combine SBL_ELF and bootblock
+config HEAP_SIZE
+ hex
+ default 0x8000
+
endif
--
2.39.2
config/coreboot/default/patches/0026-sb-intel-ibexpeak-setup_heci_uma.c-Add-timeouts-when.patch
-77
View File
@@ -1,77 +0,0 @@
From 27bf50138af0c5267581f8cc1f80676fb1836572 Mon Sep 17 00:00:00 2001
From: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
Date: Mon, 27 Mar 2017 22:05:16 +0200
Subject: [PATCH 1/1] sb/intel/ibexpeak/setup_heci_uma.c: Add timeouts when
waiting for heci
Since until now, the code running on the management engine is:
- Signed by its manufacturer
- Proprietary software, without corresponding source code
It can desirable to run the least ammount possible of such
code, which is what me_cleaner[1] enables.
It does it by removing partitions of the management engine
firmwares, however when doing so, the HECI interface might
not be present anymore.
So it is desirable not to have the RAM initialisation code
wait forever for the HECI interface to appear.
[1] https://github.com/corna/me_cleaner/
MERGENOTE: Adapted from this patch:
https://mail.coreboot.org/pipermail/coreboot/2017-March/083798.html
Author on this version of the patch set to same author as in the
linked one, with same date set, but the commit message is modified
to match the new code path. Patch author Denis Carikli, but this
versions of the patch was rebased from it by Leah Rowe on 29 Oct 2023.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/southbridge/intel/ibexpeak/setup_heci_uma.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/src/southbridge/intel/ibexpeak/setup_heci_uma.c b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
index 572e5e7a76..3a68344d97 100644
--- a/src/southbridge/intel/ibexpeak/setup_heci_uma.c
+++ b/src/southbridge/intel/ibexpeak/setup_heci_uma.c
@@ -8,28 +8,30 @@
#include <southbridge/intel/ibexpeak/me.h>
#include <southbridge/intel/ibexpeak/pch.h>
#include <types.h>
+#include <delay.h>
#define HECIDEV PCI_DEV(0, 0x16, 0)
-/* FIXME: add timeout. */
static void wait_heci_ready(void)
{
- while (!(read32(DEFAULT_HECIBAR + 0xc) & 8)) // = 0x8000000c
- ;
+ int i = 1000*1000;
+ while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8)) /* = 0x8000000c */
+ udelay(1);
write32((DEFAULT_HECIBAR + 0x4), (read32(DEFAULT_HECIBAR + 0x4) & ~0x10) | 0xc);
}
-/* FIXME: add timeout. */
static void wait_heci_cb_avail(int len)
{
+ int i = 1000*1000;
+
union {
struct mei_csr csr;
u32 raw;
} csr;
- while (!(read32(DEFAULT_HECIBAR + 0xc) & 8))
- ;
+ while (i-- && !(read32(DEFAULT_HECIBAR + 0xc) & 8))
+ udelay(1);
do {
csr.raw = read32(DEFAULT_HECIBAR + 0x4);
--
2.39.2
config/coreboot/default/patches/0030-crank-up-vram-allocation-on-more-intel-boards.patch
-142
View File
@@ -1,142 +0,0 @@
From 0721e7e984bc83861bce3d47632b717848673749 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Tue, 31 Oct 2023 18:24:39 +0000
Subject: [PATCH 1/1] crank up vram allocation on more intel boards
these were added to libreboot, and it's a policy of
libreboot to max out the vram settings. this was
overlooked, in prior revisions and releases.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6400/cmos.default | 2 +-
src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
src/mainboard/hp/compaq_8200_elite_sff/cmos.default | 2 +-
src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
src/mainboard/hp/snb_ivb_laptops/cmos.default | 1 +
src/mainboard/lenovo/t420/cmos.default | 1 +
src/mainboard/lenovo/t420s/cmos.default | 1 +
src/mainboard/lenovo/t430/cmos.default | 1 +
src/mainboard/lenovo/t520/cmos.default | 1 +
src/mainboard/lenovo/t530/cmos.default | 1 +
src/mainboard/lenovo/x201/cmos.default | 1 +
src/mainboard/lenovo/x220/cmos.default | 1 +
12 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
index eeb6f47364..25dfa38cb5 100644
--- a/src/mainboard/dell/e6400/cmos.default
+++ b/src/mainboard/dell/e6400/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Disable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
index ccc7e64625..7c97b84baf 100644
--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
+++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
@@ -3,5 +3,5 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=128M
+gfx_uma_size=224M
fan_full_speed=Disable
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
index 6d27a79c66..4517ffc7c2 100644
--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
@@ -3,5 +3,5 @@ debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=224M
psu_fan_lvl=3
diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
index 6f3cec735e..9fc4db2990 100644
--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
@@ -3,4 +3,4 @@ debug_level=Debug
power_on_after_fail=Enable
nmi=Enable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=224M
diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
index ad822d5043..89418a4cfc 100644
--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
+++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
@@ -3,3 +3,4 @@ debug_level=Debug
power_on_after_fail=Disable
nmi=Enable
sata_mode=AHCI
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
index c011867916..83f590d39d 100644
--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
@@ -15,3 +15,4 @@ trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
index c011867916..83f590d39d 100644
--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
@@ -15,3 +15,4 @@ trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
index 55e1e6c04e..a72108f47e 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
usb_always_on=Disable
hybrid_graphics_mode=Integrated Only
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
index b66f7034dc..a73ea6e9ee 100644
--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
index b66f7034dc..a73ea6e9ee 100644
--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
me_state=Disabled
+gfx_uma_size=224M
diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
index 2cf484fd5a..46294d91ca 100644
--- a/src/mainboard/lenovo/x201/cmos.default
+++ b/src/mainboard/lenovo/x201/cmos.default
@@ -15,3 +15,4 @@ power_management_beeps=Enable
low_battery_beep=Enable
sata_mode=AHCI
usb_always_on=Disable
+gfx_uma_size=128M
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
index 52f303dfdb..92a2026542 100644
--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
me_state=Disabled
+gfx_uma_size=224M
--
2.39.2
config/coreboot/default/patches/0031-dell-e6430-use-ME-Soft-Temporary-Disable.patch
-30
View File
@@ -1,30 +0,0 @@
From e712efdaf46a09a107c88a273d9b00effb4d977e Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 11:41:41 +0000
Subject: [PATCH 1/1] dell/e6430: use ME Soft Temporary Disable
i overlooked this. it's set on other boards.
we use me_cleaner anyway, and we set the hap bit, but
this additional setting takes effect even if the ME
region is unaltered. it's just another layer of
disablement, to absolutely ensure Intel ME is not alive
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6430/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
index 2a5b30f2b7..279415dfd1 100644
--- a/src/mainboard/dell/e6430/cmos.default
+++ b/src/mainboard/dell/e6430/cmos.default
@@ -6,4 +6,4 @@ bluetooth=Enable
wwan=Enable
wlan=Enable
sata_mode=AHCI
-me_state=Normal
+me_state=Disabled
--
2.39.2
config/coreboot/default/patches/0032-use-mirrorservice.org-for-gcc-downloads.patch
-36
View File
@@ -1,36 +0,0 @@
From 89c47fad6e97fc6a7113ebbdedfcc42ae2b6fc7f Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 22:57:08 +0000
Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 87f80ba7f6..b3aad5df7d 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
# to the jenkins build as well, or the builder won't download it.
# GCC toolchain archive locations
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2
config/coreboot/default/patches/0033-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch
-792
View File
@@ -1,792 +0,0 @@
From 823da59b0bdaeb20d5f22da65e736acaa70b301e Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 19 Aug 2023 16:19:10 -0600
Subject: [PATCH] mb/dell: Add Latitude E6530 (Ivy Bridge)
Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested. This
is based on the autoport output with some manual tweaks. The flash is
8MiB + 4MiB. It can be internally flashed by sending a command to the
EC, which causes the EC to pull the FDO pin low and the firmware to skip
setting up any chipset based write protections. [1] The EC is the SMSC
MEC5055, which seems to be compatible with the existing MEC5035 code.
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6530/Kconfig | 37 ++++
src/mainboard/dell/e6530/Kconfig.name | 2 +
src/mainboard/dell/e6530/Makefile.inc | 6 +
src/mainboard/dell/e6530/acpi/ec.asl | 9 +
src/mainboard/dell/e6530/acpi/platform.asl | 12 ++
src/mainboard/dell/e6530/acpi/superio.asl | 3 +
src/mainboard/dell/e6530/acpi_tables.c | 16 ++
src/mainboard/dell/e6530/board_info.txt | 6 +
src/mainboard/dell/e6530/cmos.default | 9 +
src/mainboard/dell/e6530/cmos.layout | 88 ++++++++++
src/mainboard/dell/e6530/data.vbt | Bin 0 -> 4280 bytes
src/mainboard/dell/e6530/devicetree.cb | 68 ++++++++
src/mainboard/dell/e6530/dsdt.asl | 30 ++++
src/mainboard/dell/e6530/early_init.c | 38 ++++
src/mainboard/dell/e6530/gma-mainboard.ads | 20 +++
src/mainboard/dell/e6530/gpio.c | 192 +++++++++++++++++++++
src/mainboard/dell/e6530/hda_verb.c | 33 ++++
src/mainboard/dell/e6530/mainboard.c | 21 +++
18 files changed, 590 insertions(+)
create mode 100644 src/mainboard/dell/e6530/Kconfig
create mode 100644 src/mainboard/dell/e6530/Kconfig.name
create mode 100644 src/mainboard/dell/e6530/Makefile.inc
create mode 100644 src/mainboard/dell/e6530/acpi/ec.asl
create mode 100644 src/mainboard/dell/e6530/acpi/platform.asl
create mode 100644 src/mainboard/dell/e6530/acpi/superio.asl
create mode 100644 src/mainboard/dell/e6530/acpi_tables.c
create mode 100644 src/mainboard/dell/e6530/board_info.txt
create mode 100644 src/mainboard/dell/e6530/cmos.default
create mode 100644 src/mainboard/dell/e6530/cmos.layout
create mode 100644 src/mainboard/dell/e6530/data.vbt
create mode 100644 src/mainboard/dell/e6530/devicetree.cb
create mode 100644 src/mainboard/dell/e6530/dsdt.asl
create mode 100644 src/mainboard/dell/e6530/early_init.c
create mode 100644 src/mainboard/dell/e6530/gma-mainboard.ads
create mode 100644 src/mainboard/dell/e6530/gpio.c
create mode 100644 src/mainboard/dell/e6530/hda_verb.c
create mode 100644 src/mainboard/dell/e6530/mainboard.c
diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
new file mode 100644
index 0000000000..582adddbd4
--- /dev/null
+++ b/src/mainboard/dell/e6530/Kconfig
@@ -0,0 +1,37 @@
+if BOARD_DELL_LATITUDE_E6530
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_12288
+ select EC_ACPI
+ select EC_DELL_MEC5035
+ select GFX_GMA_PANEL_1_ON_LVDS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select HAVE_CMOS_DEFAULT
+ select HAVE_OPTION_TABLE
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
+ select SERIRQ_CONTINUOUS_MODE
+ select SOUTHBRIDGE_INTEL_C216
+ select SYSTEM_TYPE_LAPTOP
+ select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+ default "dell/e6530"
+
+config MAINBOARD_PART_NUMBER
+ default "Latitude E6530"
+
+config VGA_BIOS_ID
+ default "8086,0166"
+
+config DRAM_RESET_GATE_GPIO
+ default 60
+
+config USBDEBUG_HCD_INDEX
+ default 2
+endif
diff --git a/src/mainboard/dell/e6530/Kconfig.name b/src/mainboard/dell/e6530/Kconfig.name
new file mode 100644
index 0000000000..01ed76d107
--- /dev/null
+++ b/src/mainboard/dell/e6530/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_DELL_LATITUDE_E6530
+ bool "Latitude E6530"
diff --git a/src/mainboard/dell/e6530/Makefile.inc b/src/mainboard/dell/e6530/Makefile.inc
new file mode 100644
index 0000000000..ba64e93eb8
--- /dev/null
+++ b/src/mainboard/dell/e6530/Makefile.inc
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0-only
+bootblock-y += early_init.c
+bootblock-y += gpio.c
+romstage-y += early_init.c
+romstage-y += gpio.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/dell/e6530/acpi/ec.asl b/src/mainboard/dell/e6530/acpi/ec.asl
new file mode 100644
index 0000000000..0d429410a9
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi/ec.asl
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Device(EC)
+{
+ Name (_HID, EISAID("PNP0C09"))
+ Name (_UID, 0)
+ Name (_GPE, 16)
+/* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6530/acpi/platform.asl b/src/mainboard/dell/e6530/acpi/platform.asl
new file mode 100644
index 0000000000..2d24bbd9b9
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi/platform.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+Method(_WAK, 1)
+{
+ /* FIXME: EC support */
+ Return(Package() {0, 0})
+}
+
+Method(_PTS,1)
+{
+ /* FIXME: EC support */
+}
diff --git a/src/mainboard/dell/e6530/acpi/superio.asl b/src/mainboard/dell/e6530/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/dell/e6530/acpi_tables.c b/src/mainboard/dell/e6530/acpi_tables.c
new file mode 100644
index 0000000000..e2759659bf
--- /dev/null
+++ b/src/mainboard/dell/e6530/acpi_tables.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi_gnvs.h>
+#include <soc/nvs.h>
+
+/* FIXME: check this function. */
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
+{
+ /* The lid is open by default. */
+ gnvs->lids = 1;
+
+ /* Temperature at which OS will shutdown */
+ gnvs->tcrt = 100;
+ /* Temperature at which OS will throttle CPU */
+ gnvs->tpsv = 90;
+}
diff --git a/src/mainboard/dell/e6530/board_info.txt b/src/mainboard/dell/e6530/board_info.txt
new file mode 100644
index 0000000000..4601a4aaba
--- /dev/null
+++ b/src/mainboard/dell/e6530/board_info.txt
@@ -0,0 +1,6 @@
+Category: laptop
+ROM package: SOIC-8
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
+Release year: 2012
diff --git a/src/mainboard/dell/e6530/cmos.default b/src/mainboard/dell/e6530/cmos.default
new file mode 100644
index 0000000000..279415dfd1
--- /dev/null
+++ b/src/mainboard/dell/e6530/cmos.default
@@ -0,0 +1,9 @@
+boot_option=Fallback
+debug_level=Debug
+power_on_after_fail=Disable
+nmi=Enable
+bluetooth=Enable
+wwan=Enable
+wlan=Enable
+sata_mode=AHCI
+me_state=Disabled
diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
new file mode 100644
index 0000000000..e85ea4c661
--- /dev/null
+++ b/src/mainboard/dell/e6530/cmos.layout
@@ -0,0 +1,88 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+
+#400 8 r 0 reserved for century byte
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+411 1 e 9 sata_mode
+
+# coreboot config options: EC
+412 1 e 1 bluetooth
+413 1 e 1 wwan
+415 1 e 1 wlan
+
+# coreboot config options: ME
+424 1 e 14 me_state
+425 2 h 0 me_state_prev
+
+# coreboot config options: northbridge
+432 3 e 11 gfx_uma_size
+435 2 e 12 hybrid_graphics_mode
+440 8 h 0 volume
+
+# VBOOT
+448 128 r 0 vbnv
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+960 16 r 0 mrc_scrambler_seed_chk
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+9 0 AHCI
+9 1 Compatible
+11 0 32M
+11 1 64M
+11 2 96M
+11 3 128M
+11 4 160M
+11 5 192M
+11 6 224M
+14 0 Normal
+14 1 Disabled
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 447 984
diff --git a/src/mainboard/dell/e6530/data.vbt b/src/mainboard/dell/e6530/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
GIT binary patch
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diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
new file mode 100644
index 0000000000..96eed178c5
--- /dev/null
+++ b/src/mainboard/dell/e6530/devicetree.cb
@@ -0,0 +1,68 @@
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
+ register "gpu_cpu_backlight" = "0x00000251"
+ register "gpu_dp_b_hotplug" = "4"
+ register "gpu_dp_c_hotplug" = "4"
+ register "gpu_dp_d_hotplug" = "4"
+ register "gpu_panel_port_select" = "0"
+ register "gpu_panel_power_backlight_off_delay" = "2300"
+ register "gpu_panel_power_backlight_on_delay" = "2300"
+ register "gpu_panel_power_cycle_delay" = "6"
+ register "gpu_panel_power_down_delay" = "400"
+ register "gpu_panel_power_up_delay" = "400"
+ register "gpu_pch_backlight" = "0x13121312"
+
+ device domain 0x0 on
+ subsystemid 0x1028 0x0535 inherit
+
+ device ref host_bridge on end # Host bridge
+ device ref peg10 off end # PEG
+ device ref igd on end # iGPU
+
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
+ register "docking_supported" = "1"
+ register "gen1_dec" = "0x007c0681"
+ register "gen2_dec" = "0x005c0921"
+ register "gen3_dec" = "0x003c07e1"
+ register "gen4_dec" = "0x007c0901"
+ register "gpi0_routing" = "2"
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ register "pcie_port_coalesce" = "1"
+ register "sata_interface_speed_support" = "0x3"
+ register "sata_port_map" = "0x33"
+ register "spi_lvscc" = "0x2005"
+ register "spi_uvscc" = "0x2005"
+ register "superspeed_capable_ports" = "0x0000000f"
+ register "xhci_overcurrent_mapping" = "0x00000c03"
+ register "xhci_switchable_ports" = "0x0000000f"
+
+ device ref xhci on end # USB 3.0 Controller
+ device ref mei1 off end # Management Engine Interface 1
+ device ref mei2 off end # Management Engine Interface 2
+ device ref me_ide_r off end # Management Engine IDE-R
+ device ref me_kt on end # Management Engine KT
+ device ref gbe on end # Intel Gigabit Ethernet
+ device ref ehci2 on end # USB2 EHCI #2
+ device ref hda on end # High Definition Audio
+ device ref pcie_rp1 on end # PCIe Port #1
+ device ref pcie_rp2 on end # PCIe Port #2
+ device ref pcie_rp3 on end # PCIe Port #3
+ device ref pcie_rp4 on end # PCIe Port #4
+ device ref pcie_rp5 off end # PCIe Port #5
+ device ref pcie_rp6 on end # PCIe Port #6
+ device ref pcie_rp7 off end # PCIe Port #7
+ device ref pcie_rp8 off end # PCIe Port #8
+ device ref ehci1 on end # USB2 EHCI #1
+ device ref pci_bridge off end # PCI bridge
+ device ref lpc on # LPC bridge
+ chip ec/dell/mec5035
+ device pnp ff.0 on end
+ end
+ end
+ device ref sata1 on end # SATA Controller 1
+ device ref smbus on end # SMBus
+ device ref sata2 off end # SATA Controller 2
+ device ref thermal off end # Thermal
+ end
+ end
+end
diff --git a/src/mainboard/dell/e6530/dsdt.asl b/src/mainboard/dell/e6530/dsdt.asl
new file mode 100644
index 0000000000..7d13c55b08
--- /dev/null
+++ b/src/mainboard/dell/e6530/dsdt.asl
@@ -0,0 +1,30 @@
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20141018 /* OEM revision */
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include "acpi/platform.asl"
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <southbridge/intel/common/acpi/platform.asl>
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
+ }
+}
diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
new file mode 100644
index 0000000000..d57f48e7f1
--- /dev/null
+++ b/src/mainboard/dell/e6530/early_init.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+ { 1, 1, 0 },
+ { 1, 1, 0 },
+ { 1, 1, 1 },
+ { 1, 1, 1 },
+ { 1, 1, 2 },
+ { 1, 1, 2 },
+ { 1, 0, 3 },
+ { 1, 1, 3 },
+ { 1, 1, 4 },
+ { 1, 1, 4 },
+ { 1, 1, 5 },
+ { 1, 1, 5 },
+ { 1, 2, 6 },
+ { 1, 2, 6 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
+ mec5035_early_init();
+}
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+ read_spd(&spd[0], 0x50, id_only);
+ read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/dell/e6530/gma-mainboard.ads b/src/mainboard/dell/e6530/gma-mainboard.ads
new file mode 100644
index 0000000000..1310830c8e
--- /dev/null
+++ b/src/mainboard/dell/e6530/gma-mainboard.ads
@@ -0,0 +1,20 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (
+ HDMI1, -- mainboard HDMI
+ DP2, -- dock DP
+ DP3, -- dock DP
+ Analog, --mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/e6530/gpio.c b/src/mainboard/dell/e6530/gpio.c
new file mode 100644
index 0000000000..777570765a
--- /dev/null
+++ b/src/mainboard/dell/e6530/gpio.c
@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_GPIO,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_NATIVE,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_GPIO,
+ .gpio16 = GPIO_MODE_GPIO,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_NATIVE,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_NATIVE,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_GPIO,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio0 = GPIO_DIR_INPUT,
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio15 = GPIO_DIR_INPUT,
+ .gpio16 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_OUTPUT,
+ .gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+ .gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+ .gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio0 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+ .gpio13 = GPIO_INVERT,
+ .gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_GPIO,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_GPIO,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_GPIO,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_NATIVE,
+ .gpio54 = GPIO_MODE_GPIO,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_NATIVE,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+ .gpio61 = GPIO_MODE_NATIVE,
+ .gpio62 = GPIO_MODE_NATIVE,
+ .gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_OUTPUT,
+ .gpio35 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio45 = GPIO_DIR_OUTPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio51 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio54 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ .gpio34 = GPIO_LEVEL_HIGH,
+ .gpio45 = GPIO_LEVEL_LOW,
+ .gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+ .gpio64 = GPIO_MODE_NATIVE,
+ .gpio65 = GPIO_MODE_NATIVE,
+ .gpio66 = GPIO_MODE_NATIVE,
+ .gpio67 = GPIO_MODE_NATIVE,
+ .gpio68 = GPIO_MODE_GPIO,
+ .gpio69 = GPIO_MODE_GPIO,
+ .gpio70 = GPIO_MODE_GPIO,
+ .gpio71 = GPIO_MODE_GPIO,
+ .gpio72 = GPIO_MODE_NATIVE,
+ .gpio73 = GPIO_MODE_NATIVE,
+ .gpio74 = GPIO_MODE_NATIVE,
+ .gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+ .gpio68 = GPIO_DIR_INPUT,
+ .gpio69 = GPIO_DIR_INPUT,
+ .gpio70 = GPIO_DIR_INPUT,
+ .gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ .reset = &pch_gpio_set1_reset,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ .reset = &pch_gpio_set2_reset,
+ },
+ .set3 = {
+ .mode = &pch_gpio_set3_mode,
+ .direction = &pch_gpio_set3_direction,
+ .level = &pch_gpio_set3_level,
+ .reset = &pch_gpio_set3_reset,
+ },
+};
diff --git a/src/mainboard/dell/e6530/hda_verb.c b/src/mainboard/dell/e6530/hda_verb.c
new file mode 100644
index 0000000000..9de7e34311
--- /dev/null
+++ b/src/mainboard/dell/e6530/hda_verb.c
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
+ 0x10280535, /* Subsystem ID */
+ 11, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(0, 0x10280535),
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
+ 0x80860101, /* Subsystem ID */
+ 4, /* Number of 4 dword sets */
+ AZALIA_SUBVENDOR(3, 0x80860101),
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/e6530/mainboard.c b/src/mainboard/dell/e6530/mainboard.c
new file mode 100644
index 0000000000..31e49802fc
--- /dev/null
+++ b/src/mainboard/dell/e6530/mainboard.c
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+#include <ec/acpi/ec.h>
+#include <console/console.h>
+#include <pc80/keyboard.h>
+
+static void mainboard_enable(struct device *dev)
+{
+
+ /* FIXME: fix these values. */
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
--
2.42.1
config/coreboot/dell/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch
-205
View File
@@ -1,205 +0,0 @@
From 38c76afbea4abfed2976bfbe10977e41f21665b0 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
Subject: [PATCH 15/22] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
Example:
./ifdtool --nuke gbe coreboot.rom
./ifdtool --nuke bios coreboot.com
./ifdtool --nuke me coreboot.com
Rebased since the last revision update in lbmk.
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
1 file changed, 83 insertions(+), 31 deletions(-)
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index ddbc0fb91b..7af9235ae3 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -1847,6 +1847,7 @@ static void print_usage(const char *name)
" wbg - Wellsburg\n"
" -S | --setpchstrap Write a PCH strap\n"
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
" -v | --version: print the version\n"
" -h | --help: print this help\n\n"
"<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
@@ -1854,6 +1855,60 @@ static void print_usage(const char *name)
"\n");
}
+static int
+get_region_type_string(const char *region_type_string)
+{
+ if (!strcasecmp("Descriptor", region_type_string))
+ return 0;
+ else if (!strcasecmp("BIOS", region_type_string))
+ return 1;
+ else if (!strcasecmp("ME", region_type_string))
+ return 2;
+ else if (!strcasecmp("GbE", region_type_string))
+ return 3;
+ else if (!strcasecmp("Platform Data", region_type_string))
+ return 4;
+ else if (!strcasecmp("Device Exp1", region_type_string))
+ return 5;
+ else if (!strcasecmp("Secondary BIOS", region_type_string))
+ return 6;
+ else if (!strcasecmp("Reserved", region_type_string))
+ return 7;
+ else if (!strcasecmp("EC", region_type_string))
+ return 8;
+ else if (!strcasecmp("Device Exp2", region_type_string))
+ return 9;
+ else if (!strcasecmp("IE", region_type_string))
+ return 10;
+ else if (!strcasecmp("10GbE_0", region_type_string))
+ return 11;
+ else if (!strcasecmp("10GbE_1", region_type_string))
+ return 12;
+ else if (!strcasecmp("PTT", region_type_string))
+ return 15;
+ return -1;
+}
+
+static void
+nuke(const char *filename, char *image, int size, int region_type)
+{
+ int i;
+ struct region region;
+ const struct frba *frba = find_frba(image, size);
+ if (!frba)
+ exit(EXIT_FAILURE);
+
+ region = get_region(frba, region_type);
+ if (region.size > 0) {
+ for (i = region.base; i <= region.limit; i++) {
+ if ((i + 1) > (size))
+ break;
+ image[i] = 0xFF;
+ }
+ write_image(filename, image, size);
+ }
+}
+
int main(int argc, char *argv[])
{
int opt, option_index = 0;
@@ -1861,6 +1916,7 @@ int main(int argc, char *argv[])
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
+ int mode_nuke = 0;
char *region_type_string = NULL, *region_fname = NULL;
const char *layout_fname = NULL;
char *new_filename = NULL;
@@ -1892,6 +1948,7 @@ int main(int argc, char *argv[])
{"validate", 0, NULL, 't'},
{"setpchstrap", 1, NULL, 'S'},
{"newvalue", 1, NULL, 'V'},
+ {"nuke", 1, NULL, 'N'},
{0, 0, 0, 0}
};
@@ -1941,35 +1998,8 @@ int main(int argc, char *argv[])
region_fname++;
// Descriptor, BIOS, ME, GbE, Platform
// valid type?
- if (!strcasecmp("Descriptor", region_type_string))
- region_type = 0;
- else if (!strcasecmp("BIOS", region_type_string))
- region_type = 1;
- else if (!strcasecmp("ME", region_type_string))
- region_type = 2;
- else if (!strcasecmp("GbE", region_type_string))
- region_type = 3;
- else if (!strcasecmp("Platform Data", region_type_string))
- region_type = 4;
- else if (!strcasecmp("Device Exp1", region_type_string))
- region_type = 5;
- else if (!strcasecmp("Secondary BIOS", region_type_string))
- region_type = 6;
- else if (!strcasecmp("Reserved", region_type_string))
- region_type = 7;
- else if (!strcasecmp("EC", region_type_string))
- region_type = 8;
- else if (!strcasecmp("Device Exp2", region_type_string))
- region_type = 9;
- else if (!strcasecmp("IE", region_type_string))
- region_type = 10;
- else if (!strcasecmp("10GbE_0", region_type_string))
- region_type = 11;
- else if (!strcasecmp("10GbE_1", region_type_string))
- region_type = 12;
- else if (!strcasecmp("PTT", region_type_string))
- region_type = 15;
- if (region_type == -1) {
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
fprintf(stderr, "No such region type: '%s'\n\n",
region_type_string);
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
@@ -2135,6 +2165,22 @@ int main(int argc, char *argv[])
case 't':
mode_validate = 1;
break;
+ case 'N':
+ region_type_string = strdup(optarg);
+ if (!region_type_string) {
+ fprintf(stderr, "No region specified\n");
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ if ((region_type =
+ get_region_type_string(region_type_string)) == -1) {
+ fprintf(stderr, "No such region type: '%s'\n\n",
+ region_type_string);
+ print_usage(argv[0]);
+ exit(EXIT_FAILURE);
+ }
+ mode_nuke = 1;
+ break;
case 'v':
print_version();
exit(EXIT_SUCCESS);
@@ -2150,7 +2196,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
- mode_unlocked | mode_locked) + mode_altmedisable + mode_validate) > 1) {
+ mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
+ mode_nuke) > 1) {
fprintf(stderr, "You may not specify more than one mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2158,7 +2205,8 @@ int main(int argc, char *argv[])
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
- mode_locked + mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
+ mode_locked + mode_unlocked + mode_density + mode_altmedisable +
+ mode_validate + mode_nuke) == 0) {
fprintf(stderr, "You need to specify a mode.\n\n");
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
exit(EXIT_FAILURE);
@@ -2262,6 +2310,10 @@ int main(int argc, char *argv[])
write_image(new_filename, image, size);
}
+ if (mode_nuke) {
+ nuke(new_filename, image, size, region_type);
+ }
+
if (mode_altmedisable) {
struct fpsba *fpsba = find_fpsba(image, size);
struct fmsba *fmsba = find_fmsba(image, size);
--
2.39.2
config/coreboot/dell/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
-47
View File
@@ -1,47 +0,0 @@
From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
Enabling PECI without microcode updates loaded causes the CPUID feature set
to become corrupted. And one consequence is broken SpeedStep. At least, that's
my understanding looking at Intel Errata. This revert is not a fix, because
upstream is correct (upstream assumes microcode updates). We will simply
maintain this revert patch in Libreboot, from now on.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 315e7c36fc..1423fd72bc 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
}
-#define IA32_PECI_CTL 0x5a0
-
static void configure_misc(const int eist, const int tm2, const int emttm)
{
msr_t msr;
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
}
-
- /* Enable PECI
- WARNING: due to Erratum AW67 described in Intel document #318733
- the microcode must be updated before this MSR is written to. */
- msr = rdmsr(IA32_PECI_CTL);
- msr.lo |= 1;
- wrmsr(IA32_PECI_CTL, msr);
}
#define PIC_SENS_CFG 0x1aa
--
2.39.2
config/coreboot/dell/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch
-173
View File
@@ -1,173 +0,0 @@
From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
While this fix is *technically correct*, the one in
coreboot, it breaks rebooting as tested on several
GM45 ThinkPads e.g. X200, T400, when microcode
updates are not applied.
Since November 2022, Libreboot includes microcode
updates by default, but it tells users how to remove
it from the ROM (with cbfstool) if they wish.
Well, with Libreboot 20221214, 20230319 and 20230413,
mitigations present in Libreboot 20220710 (which did
not have microcode updates) do not exist.
This patch, along with the other patch to remove PECI
support (which breaks speedstep when microcode updates
are not applied) have now been re-added to Libreboot.
It is still best to use microcode updates by default.
These patches in coreboot are not critically urgent,
and you can use the machines with or without them,
regardless of ucode.
I'll probably re-write this and the other patch at
some point, applying the change conditionally upon
whether or not microcode is applied.
Pragmatism is a good thing. I recommend it.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
5 files changed, 16 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 1423fd72bc..d1f98ca43a 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -8,6 +8,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
#define MSR_BBL_CR_CTL3 0x11e
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states(quad);
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index bc53214310..72f40f6762 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
smm_initialize();
}
-#define SMRR_SUPPORTED (1 << 11)
-
static void per_cpu_smm_trigger(void)
{
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
- set_feature_ctrl_vmx();
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
- /* We don't care if the lock is already setting
- as our smm relocation handler is able to handle
- setups where SMRR is not enabled here. */
- if (ia32_ft_ctrl.lo & (1 << 0)) {
- /* IA32_FEATURE_CONTROL locked. If we set it again we
- get an illegal instruction. */
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
- } else {
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
- printk(BIOS_INFO,
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
- }
- } else {
- set_vmx_and_lock();
- }
-
/* Relocate the SMM handler. */
smm_relocate();
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 05f5f327cc..0450c2ad83 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
fill_processor_name(processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 5bd1c32815..f3bb08cde3 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 535fb8fae7..f7b05facd2 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -7,6 +7,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
/* Setup Page Attribute Tables (PAT) */
// TODO set up PAT
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
--
2.39.2
config/coreboot/dell/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch
-28
View File
@@ -1,28 +0,0 @@
From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for
dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/e6400/devicetree.cb | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
index bb954cbd7b..e9f3915d17 100644
--- a/src/mainboard/dell/e6400/devicetree.cb
+++ b/src/mainboard/dell/e6400/devicetree.cb
@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
ops gm45_pci_domain_ops
device pci 00.0 on end # host bridge
- device pci 01.0 off end
+ device pci 01.0 on end
device pci 02.0 on end # VGA
device pci 02.1 on end # Display
device pci 03.0 on end # ME
--
2.39.2
config/coreboot/dell/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch
-39
View File
@@ -1,39 +0,0 @@
From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 19/22] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
roms without a payload resulting in a no boot situation, but in
libreboot lbmk handles the payload and thus this warning always comes
up. This has caused confusion and concern so just patch it out.
---
payloads/Makefile.inc | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
index e735443a76..4f1692a873 100644
--- a/payloads/Makefile.inc
+++ b/payloads/Makefile.inc
@@ -49,16 +49,5 @@ distclean-payloads:
print-repo-info-payloads:
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
-files_added:: warn_no_payload
-endif
-
-warn_no_payload:
- printf "\n\t** WARNING **\n"
- printf "coreboot has been built without a payload. Writing\n"
- printf "a coreboot image without a payload to your board's\n"
- printf "flash chip will result in a non-booting system. You\n"
- printf "can use cbfstool to add a payload to the image.\n\n"
-
.PHONY: force-payload coreinfo nvramcui
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
--
2.39.2
config/coreboot/dell/patches/0020-ec-dell-mec5035-Add-command-to-enable-disable-radios.patch
-61
View File
@@ -1,61 +0,0 @@
From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 27 Aug 2023 17:36:36 -0600
Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios
These were determined by sniffing the LPC bus while toggling the
hardware wireless switch on the Latitude E6400. To differentiate devices
options in the vendor BIOS to change which radios the switch controlled
were used.
Change-Id: I173dc197d63cda232dd7ede0cb798ab0a364482b
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/mec5035.c | 9 +++++++++
src/ec/dell/mec5035/mec5035.h | 8 ++++++++
2 files changed, 17 insertions(+)
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index 8da11e5b1c..e0335a4635 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -84,6 +84,15 @@ u8 mec5035_mouse_touchpad(u8 setting)
return buf[0];
}
+void mec5035_radio_enable(enum mec5035_radio_dev dev, u8 on)
+{
+ /* From LPC traces and userspace testing with other values,
+ the second byte has to be 2 for an unknown reason. */
+ u8 buf[3] = {dev, 2, on};
+ write_mailbox_regs(buf, 2, 3);
+ ec_command(CMD_RADIO_EN);
+}
+
void mec5035_early_init(void)
{
/* If this isn't sent the EC shuts down the system after about 15
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
index e7a05b64d4..16512e2cc2 100644
--- a/src/ec/dell/mec5035/mec5035.h
+++ b/src/ec/dell/mec5035/mec5035.h
@@ -16,8 +16,16 @@
#define CMD_CPU_OK 0xc2
+#define CMD_RADIO_EN 0x2b
+enum mec5035_radio_dev {
+ RADIO_WLAN = 0,
+ RADIO_WWAN = 1,
+ RADIO_WPAN = 2,
+};
+
u8 mec5035_mouse_touchpad(u8 setting);
void mec5035_cpu_ok(void);
void mec5035_early_init(void);
+void mec5035_radio_enable(enum mec5035_radio_dev device, u8 on);
#endif /* _EC_DELL_MEC5035_H_ */
--
2.39.2
config/coreboot/dell/patches/0021-ec-dell-mec5035-Hook-up-radio-enables-to-option-API.patch
-37
View File
@@ -1,37 +0,0 @@
From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 27 Aug 2023 19:15:37 -0600
Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API
Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/ec/dell/mec5035/mec5035.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
index e0335a4635..20a33cc0ad 100644
--- a/src/ec/dell/mec5035/mec5035.c
+++ b/src/ec/dell/mec5035/mec5035.c
@@ -4,6 +4,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pnp.h>
+#include <option.h>
#include <pc80/keyboard.h>
#include <stdint.h>
#include "mec5035.h"
@@ -108,6 +109,10 @@ static void mec5035_init(struct device *dev)
mec5035_mouse_touchpad(TP_PS2_MOUSE);
pc_keyboard_init(NO_AUX_DEVICE);
+
+ mec5035_radio_enable(RADIO_WLAN, get_uint_option("wlan", 1));
+ mec5035_radio_enable(RADIO_WWAN, get_uint_option("wwan", 1));
+ mec5035_radio_enable(RADIO_WPAN, get_uint_option("bluetooth", 1));
}
static struct device_operations ops = {
--
2.39.2
config/coreboot/dell/patches/0024-don-t-use-github-for-the-acpica-download.patch
-39
View File
@@ -1,39 +0,0 @@
From cddb709fd01e3e93a7879488d0d4024360e1e3d9 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 22 Oct 2023 15:02:25 +0100
Subject: [PATCH 1/1] don't use github for the acpica download
i have the tarball from a previous download, and i placed
it on libreboot rsync, which then got mirrored to princeton.
today, github's ssl cert was b0rking the hell out and i really
really wanted to finish a build, and didn't want to wait for
github to fix their httpd.
so i'm now hosting this specific acpica tarball on rsync.
this patch makes that URL be used, instead of the github one.
that's the 2nd time i've had to patch coreboot's acpica download!
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index ebc9fcb49a..a857110b4b 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2
config/coreboot/dell/patches/0025-Revert-Kconfig-Bring-HEAP_SIZE-to-a-common-large-val.patch
-341
View File
@@ -1,341 +0,0 @@
From f1b5b0051718139cf59ad047d42d1360b8452ec5 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 29 Oct 2023 01:18:50 +0000
Subject: [PATCH 1/1] Revert "Kconfig: Bring HEAP_SIZE to a common, large
value"
This reverts commit 44a48ce7a46c36df69f7b2cf3552bf10fa5f61b6.
NOTE:
this is done instead of merging:
https://review.coreboot.org/c/coreboot/+/78623
which is still under review for now
the patch i'm reverting is this one:
https://review.coreboot.org/c/coreboot/+/78270
this was actually only merged the day before i
updated coreboot revs in lbmk to the 12 october rev,
so there's no harm in quickly reverting this for now
however, later on, we will rely on the other patch
---
src/Kconfig | 3 ++-
src/cpu/qemu-x86/Kconfig | 3 +++
src/mainboard/sifive/hifive-unleashed/Kconfig | 3 +++
src/northbridge/amd/pi/Kconfig | 4 ++++
src/soc/amd/picasso/Kconfig | 4 ++++
src/soc/amd/stoneyridge/Kconfig | 4 ++++
src/soc/cavium/cn81xx/Kconfig | 3 +++
src/soc/intel/alderlake/Kconfig | 5 +++++
src/soc/intel/apollolake/Kconfig | 4 ++++
src/soc/intel/cannonlake/Kconfig | 4 ++++
src/soc/intel/elkhartlake/Kconfig | 4 ++++
src/soc/intel/jasperlake/Kconfig | 4 ++++
src/soc/intel/meteorlake/Kconfig | 5 +++++
src/soc/intel/skylake/Kconfig | 4 ++++
src/soc/intel/tigerlake/Kconfig | 4 ++++
src/soc/intel/xeon_sp/Kconfig | 4 ++++
src/soc/intel/xeon_sp/cpx/Kconfig | 4 ++++
src/soc/intel/xeon_sp/skx/Kconfig | 4 ++++
src/soc/intel/xeon_sp/spr/Kconfig | 4 ++++
src/soc/qualcomm/ipq40xx/Kconfig | 4 ++++
20 files changed, 77 insertions(+), 1 deletion(-)
diff --git a/src/Kconfig b/src/Kconfig
index ae8024089e..1549719dd0 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -751,7 +751,8 @@ config RTC
config HEAP_SIZE
hex
- default 0x100000
+ default 0x100000 if FLATTENED_DEVICE_TREE
+ default 0x4000
config STACK_SIZE
hex
diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig
index 0fa999e1ac..f3e2c4cea9 100644
--- a/src/cpu/qemu-x86/Kconfig
+++ b/src/cpu/qemu-x86/Kconfig
@@ -35,4 +35,7 @@ config MAX_CPUS
default 32 if SMM_TSEG
default 4
+config HEAP_SIZE
+ default 0x8000
+
endif
diff --git a/src/mainboard/sifive/hifive-unleashed/Kconfig b/src/mainboard/sifive/hifive-unleashed/Kconfig
index 7bc3b0bcbb..7f9300f2a7 100644
--- a/src/mainboard/sifive/hifive-unleashed/Kconfig
+++ b/src/mainboard/sifive/hifive-unleashed/Kconfig
@@ -10,6 +10,9 @@ config BOARD_SPECIFIC_OPTIONS
select FLATTENED_DEVICE_TREE
select SPI_SDCARD
+config HEAP_SIZE
+ default 0x10000
+
config MAINBOARD_DIR
default "sifive/hifive-unleashed"
diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig
index 4ffe82a15f..4518db149b 100644
--- a/src/northbridge/amd/pi/Kconfig
+++ b/src/northbridge/amd/pi/Kconfig
@@ -29,4 +29,8 @@ config HW_MEM_HOLE_SIZEK
hex
default 0x200000
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
endif # NORTHBRIDGE_AMD_PI
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index c33f287067..796fe4eb13 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -264,6 +264,10 @@ config S3_VGA_ROM_RUN
bool
default n
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
config SERIRQ_CONTINUOUS_MODE
bool
default n
diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig
index 6ff135e6a8..9af7455bae 100644
--- a/src/soc/amd/stoneyridge/Kconfig
+++ b/src/soc/amd/stoneyridge/Kconfig
@@ -152,6 +152,10 @@ config S3_VGA_ROM_RUN
bool
default n
+config HEAP_SIZE
+ hex
+ default 0xc0000
+
config EHCI_BAR
hex
default 0xfef00000
diff --git a/src/soc/cavium/cn81xx/Kconfig b/src/soc/cavium/cn81xx/Kconfig
index 77ca97202b..368581f8f1 100644
--- a/src/soc/cavium/cn81xx/Kconfig
+++ b/src/soc/cavium/cn81xx/Kconfig
@@ -30,6 +30,9 @@ config ARCH_ARMV8_EXTENSION
int
default 1
+config HEAP_SIZE
+ default 0x10000
+
config STACK_SIZE
default 0x2000
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
index 4b960c1d22..82ec8f263e 100644
--- a/src/soc/intel/alderlake/Kconfig
+++ b/src/soc/intel/alderlake/Kconfig
@@ -215,6 +215,11 @@ config IED_REGION_SIZE
hex
default 0x400000
+config HEAP_SIZE
+ hex
+ default 0x80000 if BMP_LOGO
+ default 0x10000
+
config GFX_GMA_DEFAULT_MMIO
default 0xaf000000 if MAINBOARD_HAS_EARLY_LIBGFXINIT
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig
index 78ec2987ce..bce935d800 100644
--- a/src/soc/intel/apollolake/Kconfig
+++ b/src/soc/intel/apollolake/Kconfig
@@ -252,6 +252,10 @@ config IFWI_FILE_NAME
help
Name of file to store in the IFWI region.
+config HEAP_SIZE
+ hex
+ default 0x8000
+
config MAX_ROOT_PORTS
int
default 6
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index a42a3c365b..80237f9810 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -160,6 +160,10 @@ config IED_REGION_SIZE
hex
default 0x400000
+config HEAP_SIZE
+ hex
+ default 0x8000
+
config NHLT_DMIC_1CH_16B
bool
depends on ACPI_NHLT
diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig
index 3361c0ddb9..7f1c767379 100644
--- a/src/soc/intel/elkhartlake/Kconfig
+++ b/src/soc/intel/elkhartlake/Kconfig
@@ -104,6 +104,10 @@ config IED_REGION_SIZE
hex
default 0x0
+config HEAP_SIZE
+ hex
+ default 0x8000
+
config MAX_ROOT_PORTS
int
default 7
diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig
index 3d84991e09..ff5def3263 100644
--- a/src/soc/intel/jasperlake/Kconfig
+++ b/src/soc/intel/jasperlake/Kconfig
@@ -106,6 +106,10 @@ config IED_REGION_SIZE
hex
default 0x400000
+config HEAP_SIZE
+ hex
+ default 0x8000
+
config MAX_ROOT_PORTS
int
default 8
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig
index 590e8b80e1..48030a1911 100644
--- a/src/soc/intel/meteorlake/Kconfig
+++ b/src/soc/intel/meteorlake/Kconfig
@@ -197,6 +197,11 @@ config IED_REGION_SIZE
hex
default 0x400000
+config HEAP_SIZE
+ hex
+ default 0x80000 if BMP_LOGO
+ default 0x10000
+
# Intel recommends reserving the PCIe TBT root port resources as below:
# - 42 buses
# - 194 MiB Non-prefetchable memory
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index e0df501460..d6a11363ee 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -151,6 +151,10 @@ config EXCLUDE_NATIVE_SD_INTERFACE
help
If you set this option to n, will not use native SD controller.
+config HEAP_SIZE
+ hex
+ default 0x80000
+
config IED_REGION_SIZE
hex
default 0x400000
diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index c07a0d8365..0a4b7bfdb8 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -152,6 +152,10 @@ config IED_REGION_SIZE
config INTEL_TME
default n
+config HEAP_SIZE
+ hex
+ default 0x10000
+
config MAX_ROOT_PORTS
int
default 24 if SOC_INTEL_TIGERLAKE_PCH_H
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig
index e63bee5451..63ced01067 100644
--- a/src/soc/intel/xeon_sp/Kconfig
+++ b/src/soc/intel/xeon_sp/Kconfig
@@ -91,6 +91,10 @@ config ECAM_MMCONF_BASE_ADDRESS
config ECAM_MMCONF_BUS_NUMBER
default 256
+config HEAP_SIZE
+ hex
+ default 0x80000
+
config HPET_MIN_TICKS
hex
default 0x80
diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index ac166c3038..f54f7716b6 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -71,6 +71,10 @@ config CPU_MICROCODE_CBFS_LEN
hex
default 0x7C00
+config HEAP_SIZE
+ hex
+ default 0x80000
+
config STACK_SIZE
hex
default 0x4000
diff --git a/src/soc/intel/xeon_sp/skx/Kconfig b/src/soc/intel/xeon_sp/skx/Kconfig
index 5d843878e1..c2c3d4e2e8 100644
--- a/src/soc/intel/xeon_sp/skx/Kconfig
+++ b/src/soc/intel/xeon_sp/skx/Kconfig
@@ -55,6 +55,10 @@ config CPU_MICROCODE_CBFS_LEN
hex
default 0x7C00
+config HEAP_SIZE
+ hex
+ default 0x80000
+
config IED_REGION_SIZE
hex
default 0x400000
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 43b87ade14..b1c4c783b7 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -79,6 +79,10 @@ config CPU_MICROCODE_CBFS_LEN
hex
default 0x8c00
+config HEAP_SIZE
+ hex
+ default 0x80000
+
config STACK_SIZE
hex
default 0x4000
diff --git a/src/soc/qualcomm/ipq40xx/Kconfig b/src/soc/qualcomm/ipq40xx/Kconfig
index 0ce92731c0..0eabb00752 100644
--- a/src/soc/qualcomm/ipq40xx/Kconfig
+++ b/src/soc/qualcomm/ipq40xx/Kconfig
@@ -57,4 +57,8 @@ config SBL_UTIL_PATH
help
Path for utils to combine SBL_ELF and bootblock
+config HEAP_SIZE
+ hex
+ default 0x8000
+
endif
--
2.39.2
config/coreboot/dell/patches/0027-nb-intel-gm45-Make-DDR2-raminit-work.patch
-216
View File
@@ -1,216 +0,0 @@
From e047dc3c95063f27517cd6754e9cbe496ac9313d Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Mon, 10 May 2021 22:40:59 +0200
Subject: [PATCH] [NOT FOR MERGE] nb/intel/gm45: Make DDR2 raminit work
List of changes:
- Update some timing and ODT values
- Patch RCOMP calibration to better match what MRC binaries do
- Replay a hardcoded list of RCOMP codes after RcvEn
This makes raminit work at DDR2-800 speeds and fixes S3 resume as well.
Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs.
Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
index f28c6d1..bdf0432 100644
--- a/src/northbridge/intel/gm45/gm45.h
+++ b/src/northbridge/intel/gm45/gm45.h
@@ -419,7 +419,7 @@
int raminit_read_vco_index(void);
u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
-void raminit_rcomp_calibration(stepping_t stepping);
+void raminit_rcomp_calibration(int ddr_type, stepping_t stepping);
void raminit_reset_readwrite_pointers(void);
void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
index ecada7b..2b8c44e 100644
--- a/src/northbridge/intel/gm45/raminit.c
+++ b/src/northbridge/intel/gm45/raminit.c
@@ -1049,7 +1049,7 @@
}
/* Perform RCOMP calibration for DDR3. */
- raminit_rcomp_calibration(stepping);
+ raminit_rcomp_calibration(spd_type, stepping);
/* Run initial RCOMP. */
mchbar_setbits32(0x418, 1 << 17);
@@ -1119,7 +1119,7 @@
reg = (reg & ~(0xf << 10)) | (2 << 10);
else
reg = (reg & ~(0xf << 10)) | (3 << 10);
- reg = (reg & ~(0x7 << 5)) | (3 << 5);
+ reg = (reg & ~(0x7 << 5)) | (2 << 5);
} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
@@ -1288,11 +1288,11 @@
reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32));
reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32));
if (timings->mem_clock == MEM_CLOCK_667MT) {
- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32));
- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32));
+ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32));
+ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32));
} else {
- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32));
- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32));
+ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32));
+ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32));
}
mchbar_write32(CxODT_HIGH(ch), reg);
@@ -2217,6 +2217,84 @@
raminit_write_training(timings->mem_clock, dimms, s3resume);
}
+ /*
+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
+ * after receiver enable calibration, otherwise raminit sometimes
+ * completes with non-working memory.
+ */
+ mchbar_write32(0x0530, 0x06060005);
+ mchbar_write32(0x0680, 0x06060606);
+ mchbar_write32(0x0684, 0x08070606);
+ mchbar_write32(0x0688, 0x0e0e0c0a);
+ mchbar_write32(0x068c, 0x0e0e0e0e);
+ mchbar_write32(0x0698, 0x06060606);
+ mchbar_write32(0x069c, 0x08070606);
+ mchbar_write32(0x06a0, 0x0c0c0b0a);
+ mchbar_write32(0x06a4, 0x0c0c0c0c);
+
+ mchbar_write32(0x06c0, 0x02020202);
+ mchbar_write32(0x06c4, 0x03020202);
+ mchbar_write32(0x06c8, 0x04040403);
+ mchbar_write32(0x06cc, 0x04040404);
+ mchbar_write32(0x06d8, 0x02020202);
+ mchbar_write32(0x06dc, 0x03020202);
+ mchbar_write32(0x06e0, 0x04040403);
+ mchbar_write32(0x06e4, 0x04040404);
+
+ mchbar_write32(0x0700, 0x02020202);
+ mchbar_write32(0x0704, 0x03020202);
+ mchbar_write32(0x0708, 0x04040403);
+ mchbar_write32(0x070c, 0x04040404);
+ mchbar_write32(0x0718, 0x02020202);
+ mchbar_write32(0x071c, 0x03020202);
+ mchbar_write32(0x0720, 0x04040403);
+ mchbar_write32(0x0724, 0x04040404);
+
+ mchbar_write32(0x0740, 0x02020202);
+ mchbar_write32(0x0744, 0x03020202);
+ mchbar_write32(0x0748, 0x04040403);
+ mchbar_write32(0x074c, 0x04040404);
+ mchbar_write32(0x0758, 0x02020202);
+ mchbar_write32(0x075c, 0x03020202);
+ mchbar_write32(0x0760, 0x04040403);
+ mchbar_write32(0x0764, 0x04040404);
+
+ mchbar_write32(0x0780, 0x06060606);
+ mchbar_write32(0x0784, 0x09070606);
+ mchbar_write32(0x0788, 0x0e0e0c0b);
+ mchbar_write32(0x078c, 0x0e0e0e0e);
+ mchbar_write32(0x0798, 0x06060606);
+ mchbar_write32(0x079c, 0x09070606);
+ mchbar_write32(0x07a0, 0x0d0d0c0b);
+ mchbar_write32(0x07a4, 0x0d0d0d0d);
+
+ mchbar_write32(0x07c0, 0x06060606);
+ mchbar_write32(0x07c4, 0x09070606);
+ mchbar_write32(0x07c8, 0x0e0e0c0b);
+ mchbar_write32(0x07cc, 0x0e0e0e0e);
+ mchbar_write32(0x07d8, 0x06060606);
+ mchbar_write32(0x07dc, 0x09070606);
+ mchbar_write32(0x07e0, 0x0d0d0c0b);
+ mchbar_write32(0x07e4, 0x0d0d0d0d);
+
+ mchbar_write32(0x0840, 0x06060606);
+ mchbar_write32(0x0844, 0x08070606);
+ mchbar_write32(0x0848, 0x0e0e0c0a);
+ mchbar_write32(0x084c, 0x0e0e0e0e);
+ mchbar_write32(0x0858, 0x06060606);
+ mchbar_write32(0x085c, 0x08070606);
+ mchbar_write32(0x0860, 0x0c0c0b0a);
+ mchbar_write32(0x0864, 0x0c0c0c0c);
+
+ mchbar_write32(0x0880, 0x02020202);
+ mchbar_write32(0x0884, 0x03020202);
+ mchbar_write32(0x0888, 0x04040403);
+ mchbar_write32(0x088c, 0x04040404);
+ mchbar_write32(0x0898, 0x02020202);
+ mchbar_write32(0x089c, 0x03020202);
+ mchbar_write32(0x08a0, 0x04040403);
+ mchbar_write32(0x08a4, 0x04040404);
+
igd_compute_ggc(sysinfo);
/* Program final memory map (with real values). */
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
index aef863f..b74765f 100644
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
@@ -161,11 +161,13 @@
mchbar += 4;
}
}
-void raminit_rcomp_calibration(const stepping_t stepping) {
+void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
const int a1step = stepping >= STEPPING_CONVERSION_A1;
int i;
+ char magic_comp[2] = {0};
+
enum {
PULL_UP = 0,
PULL_DOWN = 1,
@@ -196,6 +198,10 @@
reg = mchbar_read32(0x518);
lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
+ if (i == 1) {
+ magic_comp[0] = (reg >> 8) & 0x3f;
+ magic_comp[1] = (reg >> 0) & 0x3f;
+ }
}
/* Cleanup? */
mchbar_setbits32(0x400, 1 << 3);
@@ -216,13 +222,19 @@
for (channel = 0; channel < 2; ++channel) {
for (group = 0; group < 6; ++group) {
for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) {
- lookup_and_write(
- a1step,
- lut_idx[channel][group][pu_pd] - 7,
- ddr3_lookup_schedule[group][pu_pd],
- mchbar);
+ if (ddr_type == DDR3) {
+ lookup_and_write(
+ a1step,
+ lut_idx[channel][group][pu_pd] - 7,
+ ddr3_lookup_schedule[group][pu_pd],
+ mchbar);
+ }
mchbar += 0x0018;
}
+ if (ddr_type == DDR2) {
+ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24);
+ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0);
+ }
mchbar += 0x0010;
/* Channel B knows only the first two groups. */
if ((1 == channel) && (1 == group))
@@ -230,4 +242,7 @@
}
mchbar += 0x0040;
}
+
+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
}
config/coreboot/dell/patches/0028-dell-e6400-crank-up-vram-to-256MB-max.patch
-23
View File
@@ -1,23 +0,0 @@
From 1116145917035a92cc92a34e6a914a9506d17680 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Nov 2023 16:33:11 +0000
Subject: [PATCH 1/1] dell/e6400: crank up vram to 256MB (max)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
src/mainboard/dell/e6400/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
index eeb6f47364..25dfa38cb5 100644
--- a/src/mainboard/dell/e6400/cmos.default
+++ b/src/mainboard/dell/e6400/cmos.default
@@ -2,4 +2,4 @@ boot_option=Fallback
debug_level=Debug
power_on_after_fail=Disable
sata_mode=AHCI
-gfx_uma_size=32M
+gfx_uma_size=256M
--
2.39.2
config/coreboot/dell/patches/0029-use-mirrorservice.org-for-gcc-downloads.patch
-36
View File
@@ -1,36 +0,0 @@
From 89c47fad6e97fc6a7113ebbdedfcc42ae2b6fc7f Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 22:57:08 +0000
Subject: [PATCH 1/1] use mirrorservice.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 87f80ba7f6..b3aad5df7d 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
# to the jenkins build as well, or the builder won't download it.
# GCC toolchain archive locations
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
# CLANG toolchain archive locations
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
--
2.39.2
config/coreboot/dell/target.cfg
-4
View File
@@ -1,4 +0,0 @@
tree="dell"
romtype="normal"
rev="d862695f5f432b5c78dada5f16c293a4c3f9fce6"
arch="x86_64"
config/coreboot/e6400_4mb/config/libgfxinit_corebootfb
-585
View File
@@ -1,585 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="Latitude E6400"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/e6400"
CONFIG_VGA_BIOS_ID="10de,06eb"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
CONFIG_CBFS_SIZE=0x3FD000
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_VGA_BIOS=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USBDEBUG_HCD_INDEX=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_BOARD_DELL_E6400=y
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x10000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom"
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6400"
CONFIG_HAVE_IFD_BIN=y
CONFIG_PCIEXP_HOTPLUG_BUSES=8
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
CONFIG_COREBOOT_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=4096
CONFIG_ROM_SIZE=0x00400000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
CONFIG_SYSTEM_TYPE_LAPTOP=y
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
# CONFIG_VGA_BIOS_SECOND is not set
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_INTEL_GMA_BCLV_OFFSET=0x61254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_6FX=y
CONFIG_CPU_INTEL_MODEL_1067X=y
CONFIG_CPU_INTEL_SOCKET_P=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_NORTHBRIDGE_INTEL_GM45=y
#
# Southbridge
#
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
#
# Embedded Controllers
#
CONFIG_EC_DELL_MEC5035=y
#
# Intel Firmware
#
# CONFIG_HAVE_ME_BIN is not set
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
CONFIG_HAVE_GBE_BIN=y
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
CONFIG_UNLOCK_FLASH_REGIONS=y
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_VGA_ROM_RUN_DEFAULT=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y
# CONFIG_BOOTSPLASH is not set
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
# CONFIG_VGA_BIOS_DGPU is not set
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_EDID=y
CONFIG_INTEL_INT15=y
CONFIG_INTEL_GMA_ACPI=y
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="G45"
CONFIG_GFX_GMA_PCH="No_PCH"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_NULL=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/e6400_4mb/config/libgfxinit_txtmode
-581
View File
@@ -1,581 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="Latitude E6400"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/e6400"
CONFIG_VGA_BIOS_ID="10de,06eb"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
CONFIG_CBFS_SIZE=0x3FD000
CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_VGA_BIOS=y
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USBDEBUG_HCD_INDEX=1
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_BOARD_DELL_E6400=y
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfefc0000
CONFIG_DCACHE_RAM_SIZE=0x10000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_VGA_BIOS_FILE="../../../pciroms/pci10de,06eb.rom"
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6400"
CONFIG_HAVE_IFD_BIN=y
CONFIG_PCIEXP_HOTPLUG_BUSES=8
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_ASPM is not set
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
CONFIG_COREBOOT_ROMSIZE_KB_4096=y
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=4096
CONFIG_ROM_SIZE=0x00400000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
CONFIG_SYSTEM_TYPE_LAPTOP=y
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
# CONFIG_VGA_BIOS_SECOND is not set
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_INTEL_GMA_BCLV_OFFSET=0x61254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_6FX=y
CONFIG_CPU_INTEL_MODEL_1067X=y
CONFIG_CPU_INTEL_SOCKET_P=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_NORTHBRIDGE_INTEL_GM45=y
#
# Southbridge
#
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
#
# Embedded Controllers
#
CONFIG_EC_DELL_MEC5035=y
#
# Intel Firmware
#
# CONFIG_HAVE_ME_BIN is not set
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
CONFIG_HAVE_GBE_BIN=y
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
CONFIG_UNLOCK_FLASH_REGIONS=y
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_VGA_ROM_RUN_DEFAULT=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
# CONFIG_VGA_BIOS_DGPU is not set
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_EDID=y
CONFIG_INTEL_INT15=y
CONFIG_INTEL_GMA_ACPI=y
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="G45"
CONFIG_GFX_GMA_PCH="No_PCH"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_NULL=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/e6400_4mb/target.cfg
-11
View File
@@ -1,11 +0,0 @@
tree="dell"
romtype="4MiB ICH9 IFD NOR flash"
arch="x86_64"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="y"
payload_memtest="y"
payload_seabios_withgrub="y"
payload_seabios_grubonly="y"
grub_scan_disk="ahci"
microcode_required="n"
config/coreboot/e6430_12mb/config/libgfxinit_corebootfb
-603
View File
@@ -1,603 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="Latitude E6430"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/e6430"
CONFIG_VGA_BIOS_ID="8086,0166"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
CONFIG_CBFS_SIZE=0xBE5000
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
CONFIG_MAX_CPUS=8
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_DRAM_RESET_GATE_GPIO=60
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USBDEBUG_HCD_INDEX=2
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
# CONFIG_BOARD_DELL_E6400 is not set
CONFIG_BOARD_DELL_LATITUDE_E6430=y
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfefe0000
CONFIG_DCACHE_RAM_SIZE=0x20000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_ivybridge/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_ivybridge/me.bin"
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell_ivybridge/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6430"
CONFIG_HAVE_IFD_BIN=y
CONFIG_PCIEXP_HOTPLUG_BUSES=8
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
CONFIG_D3COLD_SUPPORT=y
CONFIG_PCIEXP_ASPM=y
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_12288=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=12288
CONFIG_ROM_SIZE=0x00c00000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
CONFIG_SYSTEM_TYPE_LAPTOP=y
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
CONFIG_SERIRQ_CONTINUOUS_MODE=y
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_IED_REGION_SIZE=0x400000
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_206AX=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_USE_NATIVE_RAMINIT=y
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
CONFIG_RAMINIT_ENABLE_ECC=y
#
# Southbridge
#
CONFIG_SOUTHBRIDGE_INTEL_C216=y
CONFIG_SOUTH_BRIDGE_OPTIONS=y
# CONFIG_HIDE_MEI_ON_ERROR is not set
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
#
# Embedded Controllers
#
CONFIG_EC_ACPI=y
CONFIG_EC_DELL_MEC5035=y
#
# Intel Firmware
#
CONFIG_HAVE_ME_BIN=y
# CONFIG_STITCH_ME_BIN is not set
# CONFIG_CHECK_ME is not set
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
# CONFIG_USE_ME_CLEANER is not set
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
CONFIG_HAVE_GBE_BIN=y
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
CONFIG_UNLOCK_FLASH_REGIONS=y
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y
# CONFIG_BOOTSPLASH is not set
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x800
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_USE_DDR3=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_CACHE_MRC_SETTINGS=y
# CONFIG_MRC_SETTINGS_PROTECT is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_INT15=y
CONFIG_INTEL_GMA_ACPI=y
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="Ironlake"
CONFIG_GFX_GMA_PCH="Cougar_Point"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
CONFIG_USE_PC_CMOS_ALTCENTURY=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_CB=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/e6430_12mb/config/libgfxinit_txtmode
-600
View File
@@ -1,600 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="Latitude E6430"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/e6430"
CONFIG_VGA_BIOS_ID="8086,0166"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
CONFIG_CBFS_SIZE=0xBE5000
CONFIG_MAX_CPUS=8
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_DRAM_RESET_GATE_GPIO=60
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USBDEBUG_HCD_INDEX=2
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
# CONFIG_BOARD_DELL_E6400 is not set
CONFIG_BOARD_DELL_LATITUDE_E6430=y
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfefe0000
CONFIG_DCACHE_RAM_SIZE=0x20000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_ivybridge/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_ivybridge/me.bin"
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell_ivybridge/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6430"
CONFIG_HAVE_IFD_BIN=y
CONFIG_PCIEXP_HOTPLUG_BUSES=8
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
CONFIG_D3COLD_SUPPORT=y
CONFIG_PCIEXP_ASPM=y
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_12288=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=12288
CONFIG_ROM_SIZE=0x00c00000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
CONFIG_SYSTEM_TYPE_LAPTOP=y
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
CONFIG_SERIRQ_CONTINUOUS_MODE=y
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_IED_REGION_SIZE=0x400000
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_206AX=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_USE_NATIVE_RAMINIT=y
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
CONFIG_RAMINIT_ENABLE_ECC=y
#
# Southbridge
#
CONFIG_SOUTHBRIDGE_INTEL_C216=y
CONFIG_SOUTH_BRIDGE_OPTIONS=y
# CONFIG_HIDE_MEI_ON_ERROR is not set
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
#
# Embedded Controllers
#
CONFIG_EC_ACPI=y
CONFIG_EC_DELL_MEC5035=y
#
# Intel Firmware
#
CONFIG_HAVE_ME_BIN=y
# CONFIG_STITCH_ME_BIN is not set
# CONFIG_CHECK_ME is not set
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
# CONFIG_USE_ME_CLEANER is not set
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
CONFIG_HAVE_GBE_BIN=y
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
CONFIG_UNLOCK_FLASH_REGIONS=y
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x800
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_USE_DDR3=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_CACHE_MRC_SETTINGS=y
# CONFIG_MRC_SETTINGS_PROTECT is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_INT15=y
CONFIG_INTEL_GMA_ACPI=y
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="Ironlake"
CONFIG_GFX_GMA_PCH="Cougar_Point"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
CONFIG_USE_PC_CMOS_ALTCENTURY=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_CB=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/e6430_12mb/target.cfg
-11
View File
@@ -1,11 +0,0 @@
tree="default"
romtype="normal"
arch="x86_64"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="y"
payload_memtest="y"
payload_seabios_withgrub="y"
payload_seabios_grubonly="y"
grub_scan_disk="ahci"
microcode_required="n"
config/coreboot/e6530_12mb/config/libgfxinit_corebootfb
-603
View File
@@ -1,603 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="Latitude E6530"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/e6530"
CONFIG_VGA_BIOS_ID="8086,0166"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
CONFIG_CBFS_SIZE=0xBE5000
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
CONFIG_MAX_CPUS=8
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_DRAM_RESET_GATE_GPIO=60
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USBDEBUG_HCD_INDEX=2
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
# CONFIG_BOARD_DELL_E6400 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
CONFIG_BOARD_DELL_LATITUDE_E6530=y
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfefe0000
CONFIG_DCACHE_RAM_SIZE=0x20000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_ivybridge/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_ivybridge/me.bin"
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell_ivybridge/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6530"
CONFIG_HAVE_IFD_BIN=y
CONFIG_PCIEXP_HOTPLUG_BUSES=8
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
CONFIG_D3COLD_SUPPORT=y
CONFIG_PCIEXP_ASPM=y
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_12288=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=12288
CONFIG_ROM_SIZE=0x00c00000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
CONFIG_SYSTEM_TYPE_LAPTOP=y
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
CONFIG_SERIRQ_CONTINUOUS_MODE=y
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_IED_REGION_SIZE=0x400000
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_206AX=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_USE_NATIVE_RAMINIT=y
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
CONFIG_RAMINIT_ENABLE_ECC=y
#
# Southbridge
#
CONFIG_SOUTHBRIDGE_INTEL_C216=y
CONFIG_SOUTH_BRIDGE_OPTIONS=y
# CONFIG_HIDE_MEI_ON_ERROR is not set
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
#
# Embedded Controllers
#
CONFIG_EC_ACPI=y
CONFIG_EC_DELL_MEC5035=y
#
# Intel Firmware
#
CONFIG_HAVE_ME_BIN=y
# CONFIG_STITCH_ME_BIN is not set
# CONFIG_CHECK_ME is not set
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
# CONFIG_USE_ME_CLEANER is not set
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
CONFIG_HAVE_GBE_BIN=y
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
CONFIG_UNLOCK_FLASH_REGIONS=y
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y
# CONFIG_BOOTSPLASH is not set
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x800
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_USE_DDR3=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_CACHE_MRC_SETTINGS=y
# CONFIG_MRC_SETTINGS_PROTECT is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_INT15=y
CONFIG_INTEL_GMA_ACPI=y
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="Ironlake"
CONFIG_GFX_GMA_PCH="Cougar_Point"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
CONFIG_USE_PC_CMOS_ALTCENTURY=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_CB=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/e6530_12mb/config/libgfxinit_txtmode
-600
View File
@@ -1,600 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
CONFIG_VENDOR_DELL=y
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="Latitude E6530"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="dell/e6530"
CONFIG_VGA_BIOS_ID="8086,0166"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Dell Inc."
CONFIG_CBFS_SIZE=0xBE5000
CONFIG_MAX_CPUS=8
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
CONFIG_DRAM_RESET_GATE_GPIO=60
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_USBDEBUG_HCD_INDEX=2
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
# CONFIG_BOARD_DELL_E6400 is not set
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
CONFIG_BOARD_DELL_LATITUDE_E6530=y
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfefe0000
CONFIG_DCACHE_RAM_SIZE=0x20000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
CONFIG_DRIVERS_INTEL_WIFI=y
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_ivybridge/ifd"
CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_ivybridge/me.bin"
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell_ivybridge/gbe"
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6530"
CONFIG_HAVE_IFD_BIN=y
CONFIG_PCIEXP_HOTPLUG_BUSES=8
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
CONFIG_D3COLD_SUPPORT=y
CONFIG_PCIEXP_ASPM=y
# CONFIG_PCIEXP_L1_SUB_STATE is not set
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_12288=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=12288
CONFIG_ROM_SIZE=0x00c00000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
CONFIG_SYSTEM_TYPE_LAPTOP=y
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_TSEG_SIZE=0x800000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
CONFIG_SERIRQ_CONTINUOUS_MODE=y
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_IED_REGION_SIZE=0x400000
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
CONFIG_PCIEXP_COMMON_CLOCK=y
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_206AX=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_USE_NATIVE_RAMINIT=y
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
CONFIG_RAMINIT_ENABLE_ECC=y
#
# Southbridge
#
CONFIG_SOUTHBRIDGE_INTEL_C216=y
CONFIG_SOUTH_BRIDGE_OPTIONS=y
# CONFIG_HIDE_MEI_ON_ERROR is not set
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
#
# Embedded Controllers
#
CONFIG_EC_ACPI=y
CONFIG_EC_DELL_MEC5035=y
#
# Intel Firmware
#
CONFIG_HAVE_ME_BIN=y
# CONFIG_STITCH_ME_BIN is not set
# CONFIG_CHECK_ME is not set
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
# CONFIG_USE_ME_CLEANER is not set
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
CONFIG_HAVE_GBE_BIN=y
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
CONFIG_UNLOCK_FLASH_REGIONS=y
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x800
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
CONFIG_USE_DDR3=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_CACHE_MRC_SETTINGS=y
# CONFIG_MRC_SETTINGS_PROTECT is not set
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_INT15=y
CONFIG_INTEL_GMA_ACPI=y
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="Ironlake"
CONFIG_GFX_GMA_PCH="Cougar_Point"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
CONFIG_USE_PC_CMOS_ALTCENTURY=y
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
CONFIG_DRIVERS_WIFI_GENERIC=y
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_CB=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
CONFIG_HAVE_EM100_SUPPORT=y
# CONFIG_EM100 is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/e6530_12mb/target.cfg
-11
View File
@@ -1,11 +0,0 @@
tree="default"
romtype="normal"
arch="x86_64"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="y"
payload_memtest="y"
payload_seabios_withgrub="y"
payload_seabios_grubonly="y"
grub_scan_disk="ahci"
microcode_required="n"
config/coreboot/fam15h_rdimm/patches/0003-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch
-38
View File
@@ -1,38 +0,0 @@
From 7a00638cea41ad939a59fc0e5996959435fbdb7f Mon Sep 17 00:00:00 2001
From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
Date: Sun, 7 Feb 2021 16:40:05 +0100
Subject: [PATCH 3/6] Tweak cmos defaults for KCMA-D8 (for a little speed
boost)
63xx CPUs have the option to use a reduced latency value inside the crossbar.
Setting "experimental_memory_speed_boost=Enable" aparently only has an effect
on 63xx CPUs and may, in certain cases, yield a slight memory bandwidth
increase (according to Timothy Pearson), but maybe it also works for
43xx CPUs.
Setting "l3_cache_partitioning=Enable" will increase performance in certain
situations. See:
https://developer.arm.com/documentation/100453/0401/functional-description/l3-cache/l3-cache-partitioning?lang=en
---
src/mainboard/asus/kcma-d8/cmos.default | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default
index 306687157f..4e033d756f 100644
--- a/src/mainboard/asus/kcma-d8/cmos.default
+++ b/src/mainboard/asus/kcma-d8/cmos.default
@@ -21,9 +21,9 @@ sata_ahci_mode=Enable
sata_alpm=Disable
maximum_p_state_limit=0xf
probe_filter=Auto
-l3_cache_partitioning=Disable
+l3_cache_partitioning=Enable
gart=Enable
ehci_async_data_cache=Enable
-experimental_memory_speed_boost=Disable
+experimental_memory_speed_boost=Enable
power_on_after_fail=On
boot_option=Fallback
--
2.25.1
config/coreboot/fam15h_rdimm/patches/0006-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch
-32
View File
@@ -1,32 +0,0 @@
From f0aac7261e16adc8e61eca7a506ff2de5112be47 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 7 May 2021 19:43:32 +0100
Subject: [PATCH 6/6] asus/kgpe-d16: enable lc_cache_partitioning and
experimental_memory_speed_boost
This really only benefits 63xx opterons which are less reliable in libreboot due
to lack of CPU microcode updates, but we might aswell enable this anyway.
---
src/mainboard/asus/kgpe-d16/cmos.default | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
index 7c496a50d7..8a25620e1d 100644
--- a/src/mainboard/asus/kgpe-d16/cmos.default
+++ b/src/mainboard/asus/kgpe-d16/cmos.default
@@ -21,10 +21,10 @@ sata_ahci_mode=Enable
sata_alpm=Disable
maximum_p_state_limit=0xf
probe_filter=Auto
-l3_cache_partitioning=Disable
+l3_cache_partitioning=Enable
ieee1394_controller=Enable
gart=Enable
ehci_async_data_cache=Enable
-experimental_memory_speed_boost=Disable
+experimental_memory_speed_boost=Enable
power_on_after_fail=On
boot_option=Fallback
--
2.25.1
config/coreboot/fam15h_rdimm/patches/0007-util-cbfstool-Makefile-support-distclean.patch
-41
View File
@@ -1,41 +0,0 @@
From d5dc3f23eb546cf328fdfe1e918afa028fb9cd8c Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 9 Jul 2023 04:13:52 +0100
Subject: [PATCH 1/1] util/cbfstool Makefile: support distclean
it just does make-clean
this is so that this super-old coreboot revision
interfaces well with lbmk, which runs distclean
on cbfstool (which is supported, on modern cbfstool)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/cbfstool/Makefile | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index d5321f6959..b8424d7d87 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -26,7 +26,7 @@ ifittool: $(objutil)/cbfstool/ifittool
cbfs-compression-tool: $(objutil)/cbfstool/cbfs-compression-tool
-.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool
+.PHONY: distclean clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool
clean:
$(RM) fmd_parser.c fmd_parser.h fmd_scanner.c fmd_scanner.h
$(RM) $(objutil)/cbfstool/cbfstool $(cbfsobj)
@@ -55,6 +55,8 @@ install: all
$(INSTALL) ifittool $(DESTDIR)$(BINDIR)
$(INSTALL) cbfs-compression-tool $(DESTDIR)$(BINDIR)
+distclean: clean
+
ifneq ($(V),1)
.SILENT:
endif
--
2.40.1
config/coreboot/fam15h_rdimm/patches/0008-crossgcc-patch-binutils-2.32-for-newer-hostcc.patch
-37
View File
@@ -1,37 +0,0 @@
From 4b4b2bdc2cedb3e219c6f90809e5684441b1dafa Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 9 Jul 2023 04:54:19 +0100
Subject: [PATCH 1/1] crossgcc: patch binutils 2.32 for newer hostcc
tested on debian sid as of 9 July 2023
implicit string declaration
easy peasy
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/patches/binutils-2.32_stringfix.patch | 11 +++++++++++
1 file changed, 11 insertions(+)
create mode 100644 util/crossgcc/patches/binutils-2.32_stringfix.patch
diff --git a/util/crossgcc/patches/binutils-2.32_stringfix.patch b/util/crossgcc/patches/binutils-2.32_stringfix.patch
new file mode 100644
index 0000000000..de27a2752a
--- /dev/null
+++ b/util/crossgcc/patches/binutils-2.32_stringfix.patch
@@ -0,0 +1,11 @@
+diff -u binutils-2.32/gold/errors.h binutils-2.32.patched/gold/errors.h
+--- binutils-2.32/gold/errors.h
++++ binutils-2.32.patched/gold/errors.h
+@@ -24,6 +24,7 @@
+ #define GOLD_ERRORS_H
+
+ #include <cstdarg>
++#include <string>
+
+ #include "gold-threads.h"
+
--
2.40.1
config/coreboot/fam15h_rdimm/patches/0009-fix-crossgcc-acpica-build-on-newer-hostcc.patch
-108
View File
@@ -1,108 +0,0 @@
From 373dd351e374f391c9e2048e5f3e535267a04719 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 9 Jul 2023 19:37:39 +0100
Subject: [PATCH 1/1] fix crossgcc/acpica build on newer hostcc
Changes made to acpica/iasl:
remove superfluous YYSTYPE declaration
make LuxBuffer variables static, to avoid warnings
treated as errors about multiple definitions
AcpiGbl_DbOpt_NoRegionSupport - remove this definition
in source/tools/acpiexec/aemain.c because it's already
re-defined by acpiexec. otherwise the linker complains
about multiple definitions
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
.../acpica-unix2-20190703_mitigategcc.patch | 76 +++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
diff --git a/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch b/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
new file mode 100644
index 0000000000..8de47245bd
--- /dev/null
+++ b/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
@@ -0,0 +1,76 @@
+From 66b927d923183ff62c9a757fafdeca9d1ac3fa87 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 9 Jul 2023 18:58:11 +0100
+Subject: [PATCH 1/1] fix building on newer hostcc (debian sid tested)
+
+remove superfluous YYSTYPE declaration
+
+make LuxBuffer variables static, to avoid warnings
+treated as errors about multiple definitions
+
+AcpiGbl_DbOpt_NoRegionSupport - remove this definition
+in source/tools/acpiexec/aemain.c because it's already
+re-defined by acpiexec. otherwise the linker complains
+about multiple definitions
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ source/compiler/aslcompiler.l | 1 -
+ source/compiler/dtparser.l | 2 +-
+ source/compiler/prparser.l | 2 +-
+ source/tools/acpiexec/aemain.c | 1 -
+ 4 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/source/compiler/aslcompiler.l b/source/compiler/aslcompiler.l
+index 1949b32..a24f028 100644
+--- a/source/compiler/aslcompiler.l
++++ b/source/compiler/aslcompiler.l
+@@ -48,7 +48,6 @@
+
+ #include <stdlib.h>
+ #include <string.h>
+-YYSTYPE AslCompilerlval;
+
+ /*
+ * Generation: Use the following command line:
+diff --git a/source/compiler/dtparser.l b/source/compiler/dtparser.l
+index 6517e52..d35181c 100644
+--- a/source/compiler/dtparser.l
++++ b/source/compiler/dtparser.l
+@@ -100,7 +100,7 @@ NewLine [\n]
+ /*
+ * Local support functions
+ */
+-YY_BUFFER_STATE LexBuffer;
++static YY_BUFFER_STATE LexBuffer;
+
+ /******************************************************************************
+ *
+diff --git a/source/compiler/prparser.l b/source/compiler/prparser.l
+index bcdef14..5a1b848 100644
+--- a/source/compiler/prparser.l
++++ b/source/compiler/prparser.l
+@@ -116,7 +116,7 @@ Identifier [a-zA-Z][0-9a-zA-Z]*
+ /*
+ * Local support functions
+ */
+-YY_BUFFER_STATE LexBuffer;
++static YY_BUFFER_STATE LexBuffer;
+
+
+ /******************************************************************************
+diff --git a/source/tools/acpiexec/aemain.c b/source/tools/acpiexec/aemain.c
+index 58640dd..cd0add6 100644
+--- a/source/tools/acpiexec/aemain.c
++++ b/source/tools/acpiexec/aemain.c
+@@ -84,7 +84,6 @@ BOOLEAN AcpiGbl_VerboseHandlers = FALSE;
+ UINT8 AcpiGbl_RegionFillValue = 0;
+ BOOLEAN AcpiGbl_IgnoreErrors = FALSE;
+ BOOLEAN AcpiGbl_AbortLoopOnTimeout = FALSE;
+-BOOLEAN AcpiGbl_DbOpt_NoRegionSupport = FALSE;
+ UINT8 AcpiGbl_UseHwReducedFadt = FALSE;
+ BOOLEAN AcpiGbl_DoInterfaceTests = FALSE;
+ BOOLEAN AcpiGbl_LoadTestTables = FALSE;
+--
+2.40.1
+
--
2.40.1
config/coreboot/fam15h_rdimm/patches/0010-coreboot-fam15h-use-new-upstream-for-acpica.patch
-38
View File
@@ -1,38 +0,0 @@
From ba94a3f27a26d181291b5908bdd627be375eb606 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 16 Jul 2023 00:44:22 +0100
Subject: [PATCH 1/1] coreboot/fam15h: use new upstream for acpica
the original upstream died
i decided to host it myself, on libreboot rsync,
for use by mirrors.
this is also useful for GNU Boot, when downloading
acpica on coreboot 4.11_branch, for fam15h boards
this change is not necessary on other coreboot trees,
which adhere to new coreboot policy (newer coreboot
pulls acpica from github, which is fairly reliable)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index b75b90a877..e3efa722f1 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -73,7 +73,7 @@ MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
-IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
# CLANG toolchain archive locations
--
2.40.1
config/coreboot/fam15h_rdimm/patches/0011-use-mirrorservire.org-for-gcc-downloads.patch
-47
View File
@@ -1,47 +0,0 @@
From 5358f0adc28bb1300162aa6bcfaa45aea69970d0 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 23:08:43 +0000
Subject: [PATCH 1/1] use mirrorservire.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 4b838208bb..438fb5a59f 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,12 +67,12 @@ NASM_VERSION=2.14.02
# These are sanitized by the jenkins toolchain test builder, so if
# a completely new URL is added here, it probably needs to be added
# to the jenkins build as well, or the builder won't download it.
-GMP_ARCHIVE="https://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz"
-MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
-MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
-GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
-BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
-GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
+GMP_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp/gmp-${GMP_VERSION}.tar.xz"
+MPFR_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
+MPC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc/mpc-${MPC_VERSION}.tar.gz"
+GCC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
+BINUTILS_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
+GDB_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.xz"
IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
@@ -81,7 +81,7 @@ LLVM_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/llvm-${CLANG_VERSION}.s
CFE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz"
CRT_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.tar.xz"
CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION}.src.tar.xz"
-MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2"
+MAKE_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/make/make-${MAKE_VERSION}.tar.bz2"
CMAKE_ARCHIVE="https://cmake.org/files/v3.15/cmake-${CMAKE_VERSION}.tar.gz"
NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERSION}.tar.bz2"
--
2.39.2
config/coreboot/fam15h_rdimm/target.cfg
-9
View File
@@ -1,9 +0,0 @@
tree="fam15h_rdimm"
romtype="normal"
rev="1c13f8d85c7306213cd525308ee8973e5663a3f8"
arch="x86_64"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="n"
payload_memtest="n"
crossgcc_ada="n"
config/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch
-31
View File
@@ -1,31 +0,0 @@
From 8f2988cba4fffef1bd4f65e123c76bf4b7a18672 Mon Sep 17 00:00:00 2001
From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
Date: Sun, 7 Feb 2021 15:29:40 +0100
Subject: [PATCH 1/6] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training
failure on Fam15h" (fixes a bug that prevent certain RAM modules from
booting)
This reverts commit 610d1c67b2298a9840681c2b4492b6d3fdf44a46.
After 610d1c67b2298a9840681c2b4492b6d3fdf44a46 many RAM modules wouldn't work and you couldn't even see any output on the screen.
---
src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
index ddaaaab8d5..3b07786b91 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
@@ -71,6 +71,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
misc2 |= ((cs_mux_67 & 0x1) << 27);
misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */
misc2 |= ((cs_mux_45 & 0x1) << 26);
+
+ if (pDCTstat->Status & (1 << SB_Registered))
+ misc2 |= 1 << SubMemclkRegDly;
} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
if (pDCTstat->Status & (1 << SB_Registered)) {
misc2 |= 1 << SubMemclkRegDly;
--
2.25.1
config/coreboot/fam15h_udimm/patches/0003-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch
-38
View File
@@ -1,38 +0,0 @@
From 7a00638cea41ad939a59fc0e5996959435fbdb7f Mon Sep 17 00:00:00 2001
From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
Date: Sun, 7 Feb 2021 16:40:05 +0100
Subject: [PATCH 3/6] Tweak cmos defaults for KCMA-D8 (for a little speed
boost)
63xx CPUs have the option to use a reduced latency value inside the crossbar.
Setting "experimental_memory_speed_boost=Enable" aparently only has an effect
on 63xx CPUs and may, in certain cases, yield a slight memory bandwidth
increase (according to Timothy Pearson), but maybe it also works for
43xx CPUs.
Setting "l3_cache_partitioning=Enable" will increase performance in certain
situations. See:
https://developer.arm.com/documentation/100453/0401/functional-description/l3-cache/l3-cache-partitioning?lang=en
---
src/mainboard/asus/kcma-d8/cmos.default | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default
index 306687157f..4e033d756f 100644
--- a/src/mainboard/asus/kcma-d8/cmos.default
+++ b/src/mainboard/asus/kcma-d8/cmos.default
@@ -21,9 +21,9 @@ sata_ahci_mode=Enable
sata_alpm=Disable
maximum_p_state_limit=0xf
probe_filter=Auto
-l3_cache_partitioning=Disable
+l3_cache_partitioning=Enable
gart=Enable
ehci_async_data_cache=Enable
-experimental_memory_speed_boost=Disable
+experimental_memory_speed_boost=Enable
power_on_after_fail=On
boot_option=Fallback
--
2.25.1
config/coreboot/fam15h_udimm/patches/0006-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch
-32
View File
@@ -1,32 +0,0 @@
From f0aac7261e16adc8e61eca7a506ff2de5112be47 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 7 May 2021 19:43:32 +0100
Subject: [PATCH 6/6] asus/kgpe-d16: enable lc_cache_partitioning and
experimental_memory_speed_boost
This really only benefits 63xx opterons which are less reliable in libreboot due
to lack of CPU microcode updates, but we might aswell enable this anyway.
---
src/mainboard/asus/kgpe-d16/cmos.default | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
index 7c496a50d7..8a25620e1d 100644
--- a/src/mainboard/asus/kgpe-d16/cmos.default
+++ b/src/mainboard/asus/kgpe-d16/cmos.default
@@ -21,10 +21,10 @@ sata_ahci_mode=Enable
sata_alpm=Disable
maximum_p_state_limit=0xf
probe_filter=Auto
-l3_cache_partitioning=Disable
+l3_cache_partitioning=Enable
ieee1394_controller=Enable
gart=Enable
ehci_async_data_cache=Enable
-experimental_memory_speed_boost=Disable
+experimental_memory_speed_boost=Enable
power_on_after_fail=On
boot_option=Fallback
--
2.25.1
config/coreboot/fam15h_udimm/patches/0007-util-cbfstool-Makefile-support-distclean.patch
-41
View File
@@ -1,41 +0,0 @@
From d5dc3f23eb546cf328fdfe1e918afa028fb9cd8c Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 9 Jul 2023 04:13:52 +0100
Subject: [PATCH 1/1] util/cbfstool Makefile: support distclean
it just does make-clean
this is so that this super-old coreboot revision
interfaces well with lbmk, which runs distclean
on cbfstool (which is supported, on modern cbfstool)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/cbfstool/Makefile | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/util/cbfstool/Makefile b/util/cbfstool/Makefile
index d5321f6959..b8424d7d87 100644
--- a/util/cbfstool/Makefile
+++ b/util/cbfstool/Makefile
@@ -26,7 +26,7 @@ ifittool: $(objutil)/cbfstool/ifittool
cbfs-compression-tool: $(objutil)/cbfstool/cbfs-compression-tool
-.PHONY: clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool
+.PHONY: distclean clean cbfstool ifittool fmaptool rmodtool ifwitool cbfs-compression-tool
clean:
$(RM) fmd_parser.c fmd_parser.h fmd_scanner.c fmd_scanner.h
$(RM) $(objutil)/cbfstool/cbfstool $(cbfsobj)
@@ -55,6 +55,8 @@ install: all
$(INSTALL) ifittool $(DESTDIR)$(BINDIR)
$(INSTALL) cbfs-compression-tool $(DESTDIR)$(BINDIR)
+distclean: clean
+
ifneq ($(V),1)
.SILENT:
endif
--
2.40.1
config/coreboot/fam15h_udimm/patches/0008-crossgcc-patch-binutils-2.32-for-newer-hostcc.patch
-37
View File
@@ -1,37 +0,0 @@
From 4b4b2bdc2cedb3e219c6f90809e5684441b1dafa Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 9 Jul 2023 04:54:19 +0100
Subject: [PATCH 1/1] crossgcc: patch binutils 2.32 for newer hostcc
tested on debian sid as of 9 July 2023
implicit string declaration
easy peasy
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/patches/binutils-2.32_stringfix.patch | 11 +++++++++++
1 file changed, 11 insertions(+)
create mode 100644 util/crossgcc/patches/binutils-2.32_stringfix.patch
diff --git a/util/crossgcc/patches/binutils-2.32_stringfix.patch b/util/crossgcc/patches/binutils-2.32_stringfix.patch
new file mode 100644
index 0000000000..de27a2752a
--- /dev/null
+++ b/util/crossgcc/patches/binutils-2.32_stringfix.patch
@@ -0,0 +1,11 @@
+diff -u binutils-2.32/gold/errors.h binutils-2.32.patched/gold/errors.h
+--- binutils-2.32/gold/errors.h
++++ binutils-2.32.patched/gold/errors.h
+@@ -24,6 +24,7 @@
+ #define GOLD_ERRORS_H
+
+ #include <cstdarg>
++#include <string>
+
+ #include "gold-threads.h"
+
--
2.40.1
config/coreboot/fam15h_udimm/patches/0009-fix-crossgcc-acpica-build-on-newer-hostcc.patch
-108
View File
@@ -1,108 +0,0 @@
From 373dd351e374f391c9e2048e5f3e535267a04719 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 9 Jul 2023 19:37:39 +0100
Subject: [PATCH 1/1] fix crossgcc/acpica build on newer hostcc
Changes made to acpica/iasl:
remove superfluous YYSTYPE declaration
make LuxBuffer variables static, to avoid warnings
treated as errors about multiple definitions
AcpiGbl_DbOpt_NoRegionSupport - remove this definition
in source/tools/acpiexec/aemain.c because it's already
re-defined by acpiexec. otherwise the linker complains
about multiple definitions
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
.../acpica-unix2-20190703_mitigategcc.patch | 76 +++++++++++++++++++
1 file changed, 76 insertions(+)
create mode 100644 util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
diff --git a/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch b/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
new file mode 100644
index 0000000000..8de47245bd
--- /dev/null
+++ b/util/crossgcc/patches/acpica-unix2-20190703_mitigategcc.patch
@@ -0,0 +1,76 @@
+From 66b927d923183ff62c9a757fafdeca9d1ac3fa87 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 9 Jul 2023 18:58:11 +0100
+Subject: [PATCH 1/1] fix building on newer hostcc (debian sid tested)
+
+remove superfluous YYSTYPE declaration
+
+make LuxBuffer variables static, to avoid warnings
+treated as errors about multiple definitions
+
+AcpiGbl_DbOpt_NoRegionSupport - remove this definition
+in source/tools/acpiexec/aemain.c because it's already
+re-defined by acpiexec. otherwise the linker complains
+about multiple definitions
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ source/compiler/aslcompiler.l | 1 -
+ source/compiler/dtparser.l | 2 +-
+ source/compiler/prparser.l | 2 +-
+ source/tools/acpiexec/aemain.c | 1 -
+ 4 files changed, 2 insertions(+), 4 deletions(-)
+
+diff --git a/source/compiler/aslcompiler.l b/source/compiler/aslcompiler.l
+index 1949b32..a24f028 100644
+--- a/source/compiler/aslcompiler.l
++++ b/source/compiler/aslcompiler.l
+@@ -48,7 +48,6 @@
+
+ #include <stdlib.h>
+ #include <string.h>
+-YYSTYPE AslCompilerlval;
+
+ /*
+ * Generation: Use the following command line:
+diff --git a/source/compiler/dtparser.l b/source/compiler/dtparser.l
+index 6517e52..d35181c 100644
+--- a/source/compiler/dtparser.l
++++ b/source/compiler/dtparser.l
+@@ -100,7 +100,7 @@ NewLine [\n]
+ /*
+ * Local support functions
+ */
+-YY_BUFFER_STATE LexBuffer;
++static YY_BUFFER_STATE LexBuffer;
+
+ /******************************************************************************
+ *
+diff --git a/source/compiler/prparser.l b/source/compiler/prparser.l
+index bcdef14..5a1b848 100644
+--- a/source/compiler/prparser.l
++++ b/source/compiler/prparser.l
+@@ -116,7 +116,7 @@ Identifier [a-zA-Z][0-9a-zA-Z]*
+ /*
+ * Local support functions
+ */
+-YY_BUFFER_STATE LexBuffer;
++static YY_BUFFER_STATE LexBuffer;
+
+
+ /******************************************************************************
+diff --git a/source/tools/acpiexec/aemain.c b/source/tools/acpiexec/aemain.c
+index 58640dd..cd0add6 100644
+--- a/source/tools/acpiexec/aemain.c
++++ b/source/tools/acpiexec/aemain.c
+@@ -84,7 +84,6 @@ BOOLEAN AcpiGbl_VerboseHandlers = FALSE;
+ UINT8 AcpiGbl_RegionFillValue = 0;
+ BOOLEAN AcpiGbl_IgnoreErrors = FALSE;
+ BOOLEAN AcpiGbl_AbortLoopOnTimeout = FALSE;
+-BOOLEAN AcpiGbl_DbOpt_NoRegionSupport = FALSE;
+ UINT8 AcpiGbl_UseHwReducedFadt = FALSE;
+ BOOLEAN AcpiGbl_DoInterfaceTests = FALSE;
+ BOOLEAN AcpiGbl_LoadTestTables = FALSE;
+--
+2.40.1
+
--
2.40.1
config/coreboot/fam15h_udimm/patches/0010-coreboot-fam15h-use-new-upstream-for-acpica.patch
-38
View File
@@ -1,38 +0,0 @@
From ba94a3f27a26d181291b5908bdd627be375eb606 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 16 Jul 2023 00:44:22 +0100
Subject: [PATCH 1/1] coreboot/fam15h: use new upstream for acpica
the original upstream died
i decided to host it myself, on libreboot rsync,
for use by mirrors.
this is also useful for GNU Boot, when downloading
acpica on coreboot 4.11_branch, for fam15h boards
this change is not necessary on other coreboot trees,
which adhere to new coreboot policy (newer coreboot
pulls acpica from github, which is fairly reliable)
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index b75b90a877..e3efa722f1 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -73,7 +73,7 @@ MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
-IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz"
+IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
# CLANG toolchain archive locations
--
2.40.1
config/coreboot/fam15h_udimm/patches/0011-use-mirrorservire.org-for-gcc-downloads.patch
-47
View File
@@ -1,47 +0,0 @@
From 5358f0adc28bb1300162aa6bcfaa45aea69970d0 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 5 Nov 2023 23:08:43 +0000
Subject: [PATCH 1/1] use mirrorservire.org for gcc downloads
the gnu.org 302 redirect often fails
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
util/crossgcc/buildgcc | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
index 4b838208bb..438fb5a59f 100755
--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
@@ -67,12 +67,12 @@ NASM_VERSION=2.14.02
# These are sanitized by the jenkins toolchain test builder, so if
# a completely new URL is added here, it probably needs to be added
# to the jenkins build as well, or the builder won't download it.
-GMP_ARCHIVE="https://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz"
-MPFR_ARCHIVE="https://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
-MPC_ARCHIVE="https://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz"
-GCC_ARCHIVE="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
-BINUTILS_ARCHIVE="https://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
-GDB_ARCHIVE="https://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz"
+GMP_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp/gmp-${GMP_VERSION}.tar.xz"
+MPFR_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr/mpfr-${MPFR_VERSION}.tar.xz"
+MPC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc/mpc-${MPC_VERSION}.tar.gz"
+GCC_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.xz"
+BINUTILS_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.xz"
+GDB_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.xz"
IASL_ARCHIVE="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica/acpica-unix2-${IASL_VERSION}.tar.gz"
PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}.tar.xz"
EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.tar.bz2"
@@ -81,7 +81,7 @@ LLVM_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/llvm-${CLANG_VERSION}.s
CFE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz"
CRT_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.tar.xz"
CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION}.src.tar.xz"
-MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2"
+MAKE_ARCHIVE="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/make/make-${MAKE_VERSION}.tar.bz2"
CMAKE_ARCHIVE="https://cmake.org/files/v3.15/cmake-${CMAKE_VERSION}.tar.gz"
NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERSION}.tar.bz2"
--
2.39.2
config/coreboot/fam15h_udimm/target.cfg
-9
View File
@@ -1,9 +0,0 @@
tree="fam15h_udimm"
romtype="normal"
rev="1c13f8d85c7306213cd525308ee8973e5663a3f8"
arch="x86_64"
payload_grub="n"
payload_grub_withseabios="n"
payload_seabios="n"
payload_memtest="n"
crossgcc_ada="n"
config/coreboot/g43t-am3/config/libgfxinit_txtmode
-571
View File
@@ -1,571 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
CONFIG_VENDOR_ACER=y
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="G43T-AM3"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="acer/g43t-am3"
CONFIG_VGA_BIOS_ID="8086,2e22"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Acer"
# CONFIG_BOARD_ACER_VN7_572G is not set
CONFIG_BOARD_ACER_G43T_AM3=y
CONFIG_CBFS_SIZE=0x200000
CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Acer"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfeff8000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="G43T-AM3"
# CONFIG_HAVE_IFD_BIN is not set
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
CONFIG_D3COLD_SUPPORT=y
CONFIG_PCIEXP_ASPM=y
# CONFIG_PCIEXP_L1_SUB_STATE is not set
CONFIG_PCIEXP_CLK_PM=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_2048=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
CONFIG_COREBOOT_ROMSIZE_KB_2048=y
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=2048
CONFIG_ROM_SIZE=0x00200000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_6FX=y
CONFIG_CPU_INTEL_MODEL_1067X=y
CONFIG_CPU_INTEL_MODEL_F3X=y
CONFIG_CPU_INTEL_MODEL_F4X=y
CONFIG_CPU_INTEL_SOCKET_LGA775=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_NORTHBRIDGE_INTEL_X4X=y
#
# Southbridge
#
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
CONFIG_SUPERIO_ITE_ENV_CTRL=y
CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
CONFIG_SUPERIO_ITE_IT8720F=y
#
# Embedded Controllers
#
#
# Intel Firmware
#
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_CACHE_MRC_SETTINGS=y
# CONFIG_MRC_SETTINGS_PROTECT is not set
CONFIG_MRC_STASH_TO_CBMEM=y
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_CK505=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_GMA_ACPI=y
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="G45"
CONFIG_GFX_GMA_PCH="No_PCH"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_NULL=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/g43t-am3/target.cfg
-8
View File
@@ -1,8 +0,0 @@
tree="default"
romtype="normal"
arch="x86_64"
payload_seabios="y"
payload_memtest="y"
microcode_required="n"
vendorfiles="n"
grub_timeout=10
config/coreboot/g43t-am3_16mb/config/libgfxinit_txtmode
-571
View File
@@ -1,571 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
CONFIG_VENDOR_ACER=y
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="G43T-AM3"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="acer/g43t-am3"
CONFIG_VGA_BIOS_ID="8086,2e22"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Acer"
# CONFIG_BOARD_ACER_VN7_572G is not set
CONFIG_BOARD_ACER_G43T_AM3=y
CONFIG_CBFS_SIZE=0x1000000
CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Acer"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfeff8000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_HAVE_INTEL_FIRMWARE=y
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="G43T-AM3"
# CONFIG_HAVE_IFD_BIN is not set
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
CONFIG_D3COLD_SUPPORT=y
CONFIG_PCIEXP_ASPM=y
# CONFIG_PCIEXP_L1_SUB_STATE is not set
CONFIG_PCIEXP_CLK_PM=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_2048=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=16384
CONFIG_ROM_SIZE=0x01000000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_6FX=y
CONFIG_CPU_INTEL_MODEL_1067X=y
CONFIG_CPU_INTEL_MODEL_F3X=y
CONFIG_CPU_INTEL_MODEL_F4X=y
CONFIG_CPU_INTEL_SOCKET_LGA775=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_NORTHBRIDGE_INTEL_X4X=y
#
# Southbridge
#
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
CONFIG_SUPERIO_ITE_ENV_CTRL=y
CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
CONFIG_SUPERIO_ITE_IT8720F=y
#
# Embedded Controllers
#
#
# Intel Firmware
#
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_CACHE_MRC_SETTINGS=y
# CONFIG_MRC_SETTINGS_PROTECT is not set
CONFIG_MRC_STASH_TO_CBMEM=y
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
CONFIG_HAVE_USBDEBUG_OPTIONS=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_DRIVERS_I2C_CK505=y
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_GMA_ACPI=y
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="G45"
CONFIG_GFX_GMA_PCH="No_PCH"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_NULL=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/g43t-am3_16mb/target.cfg
-8
View File
@@ -1,8 +0,0 @@
tree="default"
romtype="normal"
arch="x86_64"
payload_seabios="y"
payload_memtest="y"
microcode_required="n"
vendorfiles="n"
grub_timeout=10
config/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode
-578
View File
@@ -1,578 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_COMPILER_LLVM_CLANG is not set
CONFIG_ARCH_SUPPORTS_CLANG=y
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
# CONFIG_OPTION_BACKEND_NONE is not set
CONFIG_USE_OPTION_TABLE=y
CONFIG_STATIC_OPTION_TABLE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_INCLUDE_CONFIG_FILE=y
CONFIG_COLLECT_TIMESTAMPS=y
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
CONFIG_USE_BLOBS=y
# CONFIG_USE_AMD_BLOBS is not set
# CONFIG_USE_QC_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_TSEG_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
CONFIG_VENDOR_GIGABYTE=y
# CONFIG_VENDOR_GOOGLE is not set
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="GA-G41M-ES2L"
CONFIG_MAINBOARD_VERSION="1.0"
CONFIG_MAINBOARD_DIR="gigabyte/ga-g41m-es2l"
CONFIG_VGA_BIOS_ID="8086,2e32"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="GIGABYTE"
CONFIG_CBFS_SIZE=0x00100000
CONFIG_MAX_CPUS=4
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
CONFIG_POST_DEVICE=y
CONFIG_POST_IO=y
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
CONFIG_OVERRIDE_DEVICETREE=""
# CONFIG_VGA_BIOS is not set
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="GIGABYTE"
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
# CONFIG_CONSOLE_POST is not set
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
CONFIG_DCACHE_RAM_BASE=0xfeff8000
CONFIG_DCACHE_RAM_SIZE=0x8000
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_WINBOND=y
# CONFIG_DRIVERS_INTEL_WIFI is not set
# CONFIG_BOARD_GIGABYTE_GA_945GCM_S2L is not set
# CONFIG_BOARD_GIGABYTE_GA_945GCM_S2C is not set
# CONFIG_BOARD_GIGABYTE_GA_B75M_D3H is not set
# CONFIG_BOARD_GIGABYTE_GA_B75M_D3V is not set
# CONFIG_BOARD_GIGABYTE_GA_B75_D3V is not set
# CONFIG_BOARD_GIGABYTE_GA_D510UD is not set
CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y
# CONFIG_BOARD_GIGABYTE_GA_H61M_S2PV is not set
# CONFIG_BOARD_GIGABYTE_GA_H61M_DS2 is not set
# CONFIG_BOARD_GIGABYTE_GA_H61M_DS2V is not set
# CONFIG_BOARD_GIGABYTE_GA_H61MA_D3V is not set
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_SPI_FLASH_STMICRO=y
# CONFIG_DEBUG_SMI is not set
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="GA-G41M-ES2L"
CONFIG_PCIEXP_HOTPLUG_BUSES=32
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
CONFIG_D3COLD_SUPPORT=y
CONFIG_PCIEXP_ASPM=y
CONFIG_PCIEXP_L1_SUB_STATE=y
CONFIG_PCIEXP_CLK_PM=y
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
CONFIG_COREBOOT_ROMSIZE_KB_1024=y
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=1024
CONFIG_ROM_SIZE=0x00100000
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_CBFS_MCACHE_SIZE=0x4000
CONFIG_ROMSTAGE_ADDR=0x2000000
CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_BOOTBLOCK_IN_CBFS=y
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
# CONFIG_PCIEXP_COMMON_CLOCK is not set
CONFIG_FIXED_SMBUS_IO_BASE=0x400
CONFIG_HPET_MIN_TICKS=0x80
CONFIG_CBFS_CACHE_ALIGN=8
CONFIG_INTEL_HAS_TOP_SWAP=y
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
#
# CPU
#
CONFIG_CPU_INTEL_MODEL_6FX=y
CONFIG_CPU_INTEL_MODEL_1067X=y
CONFIG_CPU_INTEL_MODEL_F3X=y
CONFIG_CPU_INTEL_MODEL_F4X=y
CONFIG_CPU_INTEL_SOCKET_LGA775=y
CONFIG_CPU_INTEL_COMMON=y
CONFIG_ENABLE_VMX=y
CONFIG_SET_IA32_FC_LOCK_BIT=y
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
CONFIG_CPU_INTEL_COMMON_SMM=y
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
CONFIG_PARALLEL_MP=y
CONFIG_XAPIC_ONLY=y
# CONFIG_X2APIC_ONLY is not set
# CONFIG_X2APIC_RUNTIME is not set
# CONFIG_X2APIC_LATE_WORKAROUND is not set
CONFIG_UDELAY_TSC=y
CONFIG_TSC_MONOTONIC_TIMER=y
CONFIG_TSC_SYNC_MFENCE=y
CONFIG_SETUP_XIP_CACHE=y
CONFIG_HAVE_SMI_HANDLER=y
CONFIG_SMM_TSEG=y
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
CONFIG_AP_STACK_SIZE=0x800
CONFIG_SMP=y
CONFIG_SSE=y
CONFIG_SSE2=y
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
#
# Northbridge
#
CONFIG_NORTHBRIDGE_INTEL_X4X=y
#
# Southbridge
#
CONFIG_PCIEXP_HOTPLUG=y
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
CONFIG_SUPERIO_ITE_ENV_CTRL=y
CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
CONFIG_SUPERIO_ITE_IT8718F=y
#
# Embedded Controllers
#
CONFIG_ARCH_X86=y
CONFIG_ARCH_BOOTBLOCK_X86_32=y
CONFIG_ARCH_VERSTAGE_X86_32=y
CONFIG_ARCH_ROMSTAGE_X86_32=y
CONFIG_ARCH_POSTCAR_X86_32=y
CONFIG_ARCH_RAMSTAGE_X86_32=y
CONFIG_ARCH_ALL_STAGES_X86_32=y
CONFIG_HAVE_EXP_X86_64_SUPPORT=y
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
CONFIG_AP_IN_SIPI_WAIT=y
CONFIG_SIPI_VECTOR_IN_ROM=y
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
CONFIG_PC80_SYSTEM=y
CONFIG_HAVE_CMOS_DEFAULT=y
CONFIG_POSTCAR_STAGE=y
CONFIG_BOOTBLOCK_SIMPLE=y
# CONFIG_BOOTBLOCK_NORMAL is not set
CONFIG_COLLECT_TIMESTAMPS_TSC=y
CONFIG_HAVE_CF9_RESET=y
CONFIG_DEBUG_HW_BREAKPOINTS=y
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
# end of Chipset
#
# Devices
#
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
# CONFIG_VGA_ROM_RUN is not set
# CONFIG_NO_GFX_INIT is not set
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_VGA_TEXT_FRAMEBUFFER=y
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
# end of Display
CONFIG_PCI=y
CONFIG_ECAM_MMCONF_SUPPORT=y
CONFIG_PCIX_PLUGIN_SUPPORT=y
CONFIG_AZALIA_PLUGIN_SUPPORT=y
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
CONFIG_PCI_ALLOW_BUS_MASTER=y
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_EARLY_PCI_BRIDGE is not set
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
CONFIG_INTEL_GMA_HAVE_VBT=y
CONFIG_INTEL_GMA_ADD_VBT=y
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
CONFIG_USE_DDR3=y
CONFIG_USE_DDR2=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_CACHE_MRC_SETTINGS=y
# CONFIG_MRC_SETTINGS_PROTECT is not set
CONFIG_MRC_STASH_TO_CBMEM=y
CONFIG_REALTEK_8168_RESET=y
CONFIG_REALTEK_8168_MACADDRESS="00:e0:4c:00:c0:b0"
# CONFIG_SMMSTORE is not set
CONFIG_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_SPI_FLASH_ADESTO=y
CONFIG_SPI_FLASH_AMIC=y
CONFIG_SPI_FLASH_ATMEL=y
CONFIG_SPI_FLASH_EON=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_SST=y
# CONFIG_DRIVERS_UART_OXPCIE is not set
CONFIG_HAVE_USBDEBUG=y
# CONFIG_USBDEBUG is not set
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
# CONFIG_DRIVERS_I2C_MAX98396 is not set
CONFIG_INTEL_GMA_ACPI=y
CONFIG_GFX_GMA=y
CONFIG_GFX_GMA_DYN_CPU=y
CONFIG_GFX_GMA_GENERATION="G45"
CONFIG_GFX_GMA_PCH="No_PCH"
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
CONFIG_DRIVERS_MC146818=y
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_VGA=y
# CONFIG_DRIVERS_SIL_3114 is not set
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
CONFIG_NO_TPM=y
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
#
# Memory initialization
#
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
# end of Memory initialization
# CONFIG_STM is not set
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# CONFIG_BOOTMEDIA_SMM_BWP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
CONFIG_ACPI_SOC_NVS=y
CONFIG_ACPI_NO_CUSTOM_MADT=y
CONFIG_ACPI_COMMON_MADT_LAPIC=y
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
CONFIG_HAVE_ACPI_TABLES=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
CONFIG_POSTCAR_CONSOLE=y
CONFIG_SQUELCH_EARLY_SMP=y
# CONFIG_SPKMODEM is not set
# CONFIG_CONSOLE_NE2K is not set
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_CONSOLE_I2C_SMBUS is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
# CONFIG_CMOS_POST is not set
CONFIG_POST_DEVICE_NONE=y
# CONFIG_POST_DEVICE_LPC is not set
# CONFIG_POST_DEVICE_PCI_PCIE is not set
CONFIG_POST_IO_PORT=0x80
CONFIG_HWBASE_DEBUG_NULL=y
# end of Console
CONFIG_HAVE_ACPI_RESUME=y
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
CONFIG_HAVE_MONOTONIC_TIMER=y
CONFIG_HAVE_OPTION_TABLE=y
CONFIG_IOAPIC=y
CONFIG_USE_WATCHDOG_ON_BOOT=y
#
# System tables
#
CONFIG_GENERATE_SMBIOS_TABLES=y
CONFIG_BIOS_VENDOR="coreboot"
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
# CONFIG_DISPLAY_MTRRS is not set
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
CONFIG_HAVE_DEBUG_RAM_SETUP=y
# CONFIG_DEBUG_RAM_SETUP is not set
CONFIG_HAVE_DEBUG_SMBUS=y
# CONFIG_DEBUG_SMBUS is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
# end of Debugging
CONFIG_RAMSTAGE_ADA=y
CONFIG_RAMSTAGE_LIBHWBASE=y
CONFIG_HWBASE_DYNAMIC_MMIO=y
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
CONFIG_HWBASE_DIRECT_PCIDEV=y
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_RELOCATABLE_MODULES=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/ga-g41m-es2l/target.cfg
-9
View File
@@ -1,9 +0,0 @@
tree="default"
romtype="normal"
arch="x86_64"
payload_seabios="y"
payload_memtest="y"
grub_scan_disk="ata"
microcode_required="n"
vendorfiles="n"
grub_timeout=10
config/coreboot/gru_bob/config/libgfxinit_corebootfb
-950
View File
@@ -1,950 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_ALLOW_EXPERIMENTAL_CLANG is not set
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
CONFIG_OPTION_BACKEND_NONE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_COMPRESS_PRERAM_STAGES=y
CONFIG_COMPRESS_BOOTBLOCK=y
CONFIG_INCLUDE_CONFIG_FILE=y
# CONFIG_COLLECT_TIMESTAMPS is not set
# CONFIG_USE_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_CBMEM_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
CONFIG_VENDOR_GOOGLE=y
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="Bob"
CONFIG_MAINBOARD_DIR="google/gru"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Google"
CONFIG_CBFS_SIZE=0x00800000
CONFIG_CONSOLE_SERIAL=y
CONFIG_MAX_CPUS=1
CONFIG_POST_DEVICE=y
CONFIG_UART_FOR_CONSOLE=0
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
# CONFIG_CHROMEOS is not set
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=1
CONFIG_CONSOLE_SERIAL_UART_ADDRESS=0xFF1A0000
# CONFIG_CONSOLE_POST is not set
CONFIG_MEMLAYOUT_LD_FILE="src/soc/rockchip/rk3399/memlayout.ld"
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_SPI_FLASH_WINBOND=y
#
# Asurada
#
# CONFIG_BOARD_GOOGLE_ASURADA is not set
# CONFIG_BOARD_GOOGLE_HAYATO is not set
# CONFIG_BOARD_GOOGLE_SPHERION is not set
#
# Auron
#
# CONFIG_BOARD_GOOGLE_AURON_PAINE is not set
# CONFIG_BOARD_GOOGLE_AURON_YUNA is not set
# CONFIG_BOARD_GOOGLE_BUDDY is not set
# CONFIG_BOARD_GOOGLE_GANDOF is not set
# CONFIG_BOARD_GOOGLE_LULU is not set
# CONFIG_BOARD_GOOGLE_SAMUS is not set
#
# Beltino
#
# CONFIG_BOARD_GOOGLE_MCCLOUD is not set
# CONFIG_BOARD_GOOGLE_MONROE is not set
# CONFIG_BOARD_GOOGLE_PANTHER is not set
# CONFIG_BOARD_GOOGLE_TRICKY is not set
# CONFIG_BOARD_GOOGLE_ZAKO is not set
#
# Brya
#
# CONFIG_BOARD_GOOGLE_AGAH is not set
# CONFIG_BOARD_GOOGLE_ANAHERA is not set
# CONFIG_BOARD_GOOGLE_ANAHERA4ES is not set
# CONFIG_BOARD_GOOGLE_AURASH is not set
# CONFIG_BOARD_GOOGLE_BANSHEE is not set
# CONFIG_BOARD_GOOGLE_BRASK is not set
# CONFIG_BOARD_GOOGLE_BRYA0 is not set
# CONFIG_BOARD_GOOGLE_CRAASK is not set
# CONFIG_BOARD_GOOGLE_CRAASKOV is not set
# CONFIG_BOARD_GOOGLE_CONSTITUTION is not set
# CONFIG_BOARD_GOOGLE_CROTA is not set
# CONFIG_BOARD_GOOGLE_FELWINTER is not set
# CONFIG_BOARD_GOOGLE_GAELIN is not set
# CONFIG_BOARD_GOOGLE_GIMBLE is not set
# CONFIG_BOARD_GOOGLE_GIMBLE4ES is not set
# CONFIG_BOARD_GOOGLE_GLADIOS is not set
# CONFIG_BOARD_GOOGLE_GOTHRAX is not set
# CONFIG_BOARD_GOOGLE_HADES is not set
# CONFIG_BOARD_GOOGLE_KANO is not set
# CONFIG_BOARD_GOOGLE_KINOX is not set
# CONFIG_BOARD_GOOGLE_KULDAX is not set
# CONFIG_BOARD_GOOGLE_JOXER is not set
# CONFIG_BOARD_GOOGLE_LISBON is not set
# CONFIG_BOARD_GOOGLE_MARASOV is not set
# CONFIG_BOARD_GOOGLE_MITHRAX is not set
# CONFIG_BOARD_GOOGLE_MOLI is not set
# CONFIG_BOARD_GOOGLE_NIVVIKS is not set
# CONFIG_BOARD_GOOGLE_NEREID is not set
# CONFIG_BOARD_GOOGLE_OMNIGUL is not set
# CONFIG_BOARD_GOOGLE_OSIRIS is not set
# CONFIG_BOARD_GOOGLE_PIRRHA is not set
# CONFIG_BOARD_GOOGLE_PRIMUS is not set
# CONFIG_BOARD_GOOGLE_PRIMUS4ES is not set
# CONFIG_BOARD_GOOGLE_PUJJO is not set
# CONFIG_BOARD_GOOGLE_QUANDISO is not set
# CONFIG_BOARD_GOOGLE_REDRIX is not set
# CONFIG_BOARD_GOOGLE_REDRIX4ES is not set
# CONFIG_BOARD_GOOGLE_SKOLAS is not set
# CONFIG_BOARD_GOOGLE_SKOLAS4ES is not set
# CONFIG_BOARD_GOOGLE_TAEKO is not set
# CONFIG_BOARD_GOOGLE_TAEKO4ES is not set
# CONFIG_BOARD_GOOGLE_TANIKS is not set
# CONFIG_BOARD_GOOGLE_ULDREN is not set
# CONFIG_BOARD_GOOGLE_VELL is not set
# CONFIG_BOARD_GOOGLE_VOLMAR is not set
# CONFIG_BOARD_GOOGLE_XIVU is not set
# CONFIG_BOARD_GOOGLE_YAVIKS is not set
# CONFIG_BOARD_GOOGLE_YAVILLA is not set
# CONFIG_BOARD_GOOGLE_ZYDRON is not set
# CONFIG_BOARD_GOOGLE_NOKRIS is not set
# CONFIG_BOARD_GOOGLE_DOCHI is not set
#
# Butterfly
#
# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set
#
# Cherry
#
# CONFIG_BOARD_GOOGLE_CHERRY is not set
# CONFIG_BOARD_GOOGLE_DOJO is not set
# CONFIG_BOARD_GOOGLE_TOMATO is not set
#
# Kingler
#
# CONFIG_BOARD_GOOGLE_KINGLER is not set
# CONFIG_BOARD_GOOGLE_STEELIX is not set
# CONFIG_BOARD_GOOGLE_VOLTORB is not set
# CONFIG_BOARD_GOOGLE_PONYTA is not set
#
# Krabby
#
# CONFIG_BOARD_GOOGLE_KRABBY is not set
# CONFIG_BOARD_GOOGLE_TENTACRUEL is not set
# CONFIG_BOARD_GOOGLE_MAGIKARP is not set
#
# Staryu
#
# CONFIG_BOARD_GOOGLE_STARMIE is not set
#
# Cyan
#
# CONFIG_BOARD_GOOGLE_BANON is not set
# CONFIG_BOARD_GOOGLE_CELES is not set
# CONFIG_BOARD_GOOGLE_CYAN is not set
# CONFIG_BOARD_GOOGLE_EDGAR is not set
# CONFIG_BOARD_GOOGLE_KEFKA is not set
# CONFIG_BOARD_GOOGLE_REKS is not set
# CONFIG_BOARD_GOOGLE_RELM is not set
# CONFIG_BOARD_GOOGLE_SETZER is not set
# CONFIG_BOARD_GOOGLE_TERRA is not set
# CONFIG_BOARD_GOOGLE_ULTIMA is not set
# CONFIG_BOARD_GOOGLE_WIZPIG is not set
#
# Daisy
#
# CONFIG_BOARD_GOOGLE_DAISY is not set
#
# Dedede
#
# CONFIG_BOARD_GOOGLE_BOTEN is not set
# CONFIG_BOARD_GOOGLE_DIBBI is not set
# CONFIG_BOARD_GOOGLE_DEDEDE is not set
# CONFIG_BOARD_GOOGLE_DRAWCIA is not set
# CONFIG_BOARD_GOOGLE_HABOKI is not set
# CONFIG_BOARD_GOOGLE_MADOO is not set
# CONFIG_BOARD_GOOGLE_WADDLEDOO is not set
# CONFIG_BOARD_GOOGLE_WADDLEDEE is not set
# CONFIG_BOARD_GOOGLE_LALALA is not set
# CONFIG_BOARD_GOOGLE_MAGOLOR is not set
# CONFIG_BOARD_GOOGLE_METAKNIGHT is not set
# CONFIG_BOARD_GOOGLE_LANTIS is not set
# CONFIG_BOARD_GOOGLE_GALTIC is not set
# CONFIG_BOARD_GOOGLE_SASUKE is not set
# CONFIG_BOARD_GOOGLE_STORO is not set
# CONFIG_BOARD_GOOGLE_SASUKETTE is not set
# CONFIG_BOARD_GOOGLE_KRACKO is not set
# CONFIG_BOARD_GOOGLE_BLIPPER is not set
# CONFIG_BOARD_GOOGLE_CRET is not set
# CONFIG_BOARD_GOOGLE_PIRIKA is not set
# CONFIG_BOARD_GOOGLE_CAPPY2 is not set
# CONFIG_BOARD_GOOGLE_BUGZZY is not set
# CONFIG_BOARD_GOOGLE_CORORI is not set
# CONFIG_BOARD_GOOGLE_DRIBLEE is not set
# CONFIG_BOARD_GOOGLE_GOOEY is not set
# CONFIG_BOARD_GOOGLE_BEADRIX is not set
# CONFIG_BOARD_GOOGLE_SHOTZO is not set
# CONFIG_BOARD_GOOGLE_TARANZA is not set
# CONFIG_BOARD_GOOGLE_BOXY is not set
# CONFIG_BOARD_GOOGLE_DEXI is not set
#
# Drallion
#
# CONFIG_BOARD_GOOGLE_DRALLION is not set
#
# Eve
#
# CONFIG_BOARD_GOOGLE_EVE is not set
#
# Fizz
#
# CONFIG_BOARD_GOOGLE_FIZZ is not set
# CONFIG_BOARD_GOOGLE_KARMA is not set
# CONFIG_BOARD_GOOGLE_ENDEAVOUR is not set
#
# Foster
#
# CONFIG_BOARD_GOOGLE_FOSTER is not set
#
# Gale
#
# CONFIG_BOARD_GOOGLE_GALE is not set
#
# Geralt
#
# CONFIG_BOARD_GOOGLE_GERALT is not set
#
# Glados
#
# CONFIG_BOARD_GOOGLE_ASUKA is not set
# CONFIG_BOARD_GOOGLE_CAROLINE is not set
# CONFIG_BOARD_GOOGLE_CAVE is not set
# CONFIG_BOARD_GOOGLE_CHELL is not set
# CONFIG_BOARD_GOOGLE_GLADOS is not set
# CONFIG_BOARD_GOOGLE_LARS is not set
# CONFIG_BOARD_GOOGLE_SENTRY is not set
#
# Gru
#
# CONFIG_BOARD_GOOGLE_KEVIN is not set
# CONFIG_BOARD_GOOGLE_GRU is not set
CONFIG_BOARD_GOOGLE_BOB=y
# CONFIG_BOARD_GOOGLE_SCARLET is not set
# CONFIG_BOARD_GOOGLE_NEFARIO is not set
# CONFIG_BOARD_GOOGLE_RAINIER is not set
#
# Guybrush
#
# CONFIG_BOARD_GOOGLE_GUYBRUSH is not set
# CONFIG_BOARD_GOOGLE_NIPPERKIN is not set
# CONFIG_BOARD_GOOGLE_DEWATT is not set
#
# Hatch
#
# CONFIG_BOARD_GOOGLE_AKEMI is not set
# CONFIG_BOARD_GOOGLE_DRATINI is not set
# CONFIG_BOARD_GOOGLE_HATCH is not set
# CONFIG_BOARD_GOOGLE_HELIOS is not set
# CONFIG_BOARD_GOOGLE_HELIOS_DISKSWAP is not set
# CONFIG_BOARD_GOOGLE_JINLON is not set
# CONFIG_BOARD_GOOGLE_KINDRED is not set
# CONFIG_BOARD_GOOGLE_KOHAKU is not set
# CONFIG_BOARD_GOOGLE_MUSHU is not set
# CONFIG_BOARD_GOOGLE_NIGHTFURY is not set
# CONFIG_BOARD_GOOGLE_PALKIA is not set
#
# Herobrine
#
#
# (Herobrine requires 'Allow QC blobs repository')
#
#
# Jecht
#
# CONFIG_BOARD_GOOGLE_GUADO is not set
# CONFIG_BOARD_GOOGLE_JECHT is not set
# CONFIG_BOARD_GOOGLE_RIKKU is not set
# CONFIG_BOARD_GOOGLE_TIDUS is not set
#
# Kahlee
#
# CONFIG_BOARD_GOOGLE_ALEENA is not set
# CONFIG_BOARD_GOOGLE_CAREENA is not set
# CONFIG_BOARD_GOOGLE_GRUNT is not set
# CONFIG_BOARD_GOOGLE_LIARA is not set
# CONFIG_BOARD_GOOGLE_NUWANI is not set
# CONFIG_BOARD_GOOGLE_TREEYA is not set
#
# Kukui
#
# CONFIG_BOARD_GOOGLE_KUKUI is not set
# CONFIG_BOARD_GOOGLE_KRANE is not set
# CONFIG_BOARD_GOOGLE_KODAMA is not set
# CONFIG_BOARD_GOOGLE_KAKADU is not set
# CONFIG_BOARD_GOOGLE_FLAPJACK is not set
# CONFIG_BOARD_GOOGLE_KATSU is not set
#
# Jacuzzi
#
# CONFIG_BOARD_GOOGLE_JACUZZI is not set
# CONFIG_BOARD_GOOGLE_JUNIPER is not set
# CONFIG_BOARD_GOOGLE_KAPPA is not set
# CONFIG_BOARD_GOOGLE_DAMU is not set
# CONFIG_BOARD_GOOGLE_CERISE is not set
# CONFIG_BOARD_GOOGLE_STERN is not set
# CONFIG_BOARD_GOOGLE_WILLOW is not set
# CONFIG_BOARD_GOOGLE_ESCHE is not set
# CONFIG_BOARD_GOOGLE_BURNET is not set
# CONFIG_BOARD_GOOGLE_FENNEL is not set
# CONFIG_BOARD_GOOGLE_COZMO is not set
# CONFIG_BOARD_GOOGLE_MAKOMO is not set
# CONFIG_BOARD_GOOGLE_MUNNA is not set
# CONFIG_BOARD_GOOGLE_PICO is not set
#
# Link
#
# CONFIG_BOARD_GOOGLE_LINK is not set
#
# Mistral
#
# CONFIG_BOARD_GOOGLE_MISTRAL is not set
#
# Myst
#
# CONFIG_BOARD_GOOGLE_MYST is not set
#
# Nyan
#
# CONFIG_BOARD_GOOGLE_NYAN is not set
#
# Nyan Big
#
# CONFIG_BOARD_GOOGLE_NYAN_BIG is not set
#
# Nyan Blaze
#
# CONFIG_BOARD_GOOGLE_NYAN_BLAZE is not set
#
# Oak
#
# CONFIG_BOARD_GOOGLE_OAK is not set
# CONFIG_BOARD_GOOGLE_ELM is not set
# CONFIG_BOARD_GOOGLE_HANA is not set
#
# Octopus
#
# CONFIG_BOARD_GOOGLE_AMPTON is not set
# CONFIG_BOARD_GOOGLE_BLOOG is not set
# CONFIG_BOARD_GOOGLE_BOBBA is not set
# CONFIG_BOARD_GOOGLE_CASTA is not set
# CONFIG_BOARD_GOOGLE_DOOD is not set
# CONFIG_BOARD_GOOGLE_FLEEX is not set
# CONFIG_BOARD_GOOGLE_FOOB is not set
# CONFIG_BOARD_GOOGLE_GARG is not set
# CONFIG_BOARD_GOOGLE_LICK is not set
# CONFIG_BOARD_GOOGLE_MEEP is not set
# CONFIG_BOARD_GOOGLE_OCTOPUS is not set
# CONFIG_BOARD_GOOGLE_PHASER is not set
# CONFIG_BOARD_GOOGLE_YORP is not set
#
# Parrot
#
# CONFIG_BOARD_GOOGLE_PARROT is not set
#
# Peach Pit
#
# CONFIG_BOARD_GOOGLE_PEACH_PIT is not set
#
# Poppy
#
# CONFIG_BOARD_GOOGLE_ATLAS is not set
# CONFIG_BOARD_GOOGLE_POPPY is not set
# CONFIG_BOARD_GOOGLE_NAMI is not set
# CONFIG_BOARD_GOOGLE_NAUTILUS is not set
# CONFIG_BOARD_GOOGLE_NOCTURNE is not set
# CONFIG_BOARD_GOOGLE_RAMMUS is not set
# CONFIG_BOARD_GOOGLE_SORAKA is not set
#
# Puff
#
# CONFIG_BOARD_GOOGLE_AMBASSADOR is not set
# CONFIG_BOARD_GOOGLE_DOOLY is not set
# CONFIG_BOARD_GOOGLE_DUFFY_LEGACY is not set
# CONFIG_BOARD_GOOGLE_DUFFY is not set
# CONFIG_BOARD_GOOGLE_FAFFY is not set
# CONFIG_BOARD_GOOGLE_GENESIS is not set
# CONFIG_BOARD_GOOGLE_KAISA_LEGACY is not set
# CONFIG_BOARD_GOOGLE_KAISA is not set
# CONFIG_BOARD_GOOGLE_MOONBUGGY is not set
# CONFIG_BOARD_GOOGLE_NOIBAT is not set
# CONFIG_BOARD_GOOGLE_PUFF is not set
# CONFIG_BOARD_GOOGLE_SCOUT is not set
# CONFIG_BOARD_GOOGLE_WYVERN is not set
#
# Rambi
#
# CONFIG_BOARD_GOOGLE_BANJO is not set
# CONFIG_BOARD_GOOGLE_CANDY is not set
# CONFIG_BOARD_GOOGLE_CLAPPER is not set
# CONFIG_BOARD_GOOGLE_ENGUARDE is not set
# CONFIG_BOARD_GOOGLE_EXPRESSO is not set
# CONFIG_BOARD_GOOGLE_GLIMMER is not set
# CONFIG_BOARD_GOOGLE_GNAWTY is not set
# CONFIG_BOARD_GOOGLE_HELI is not set
# CONFIG_BOARD_GOOGLE_KIP is not set
# CONFIG_BOARD_GOOGLE_NINJA is not set
# CONFIG_BOARD_GOOGLE_ORCO is not set
# CONFIG_BOARD_GOOGLE_QUAWKS is not set
# CONFIG_BOARD_GOOGLE_SQUAWKS is not set
# CONFIG_BOARD_GOOGLE_RAMBI is not set
# CONFIG_BOARD_GOOGLE_SUMO is not set
# CONFIG_BOARD_GOOGLE_SWANKY is not set
# CONFIG_BOARD_GOOGLE_WINKY is not set
#
# Reef
#
# CONFIG_BOARD_GOOGLE_REEF is not set
# CONFIG_BOARD_GOOGLE_PYRO is not set
# CONFIG_BOARD_GOOGLE_SAND is not set
# CONFIG_BOARD_GOOGLE_SNAPPY is not set
# CONFIG_BOARD_GOOGLE_CORAL is not set
#
# Rex
#
# CONFIG_BOARD_GOOGLE_REX0 is not set
# CONFIG_BOARD_GOOGLE_SCREEBO is not set
# CONFIG_BOARD_GOOGLE_SCREEBO4ES is not set
# CONFIG_BOARD_GOOGLE_KARIS is not set
# CONFIG_BOARD_GOOGLE_KARIS4ES is not set
# CONFIG_BOARD_GOOGLE_REX_EC_ISH is not set
# CONFIG_BOARD_GOOGLE_OVIS is not set
# CONFIG_BOARD_GOOGLE_OVIS4ES is not set
# CONFIG_BOARD_GOOGLE_REX4ES is not set
# CONFIG_BOARD_GOOGLE_REX4ES_EC_ISH is not set
#
# Sarien
#
# CONFIG_BOARD_GOOGLE_ARCADA is not set
# CONFIG_BOARD_GOOGLE_SARIEN is not set
#
# Skyrim
#
# CONFIG_BOARD_GOOGLE_SKYRIM is not set
# CONFIG_BOARD_GOOGLE_WINTERHOLD is not set
# CONFIG_BOARD_GOOGLE_FROSTFLOW is not set
# CONFIG_BOARD_GOOGLE_CRYSTALDRIFT is not set
# CONFIG_BOARD_GOOGLE_MARKARTH is not set
#
# Slippy
#
# CONFIG_BOARD_GOOGLE_FALCO is not set
# CONFIG_BOARD_GOOGLE_LEON is not set
# CONFIG_BOARD_GOOGLE_PEPPY is not set
# CONFIG_BOARD_GOOGLE_WOLF is not set
#
# Smaug
#
# CONFIG_BOARD_GOOGLE_SMAUG is not set
#
# Storm
#
# CONFIG_BOARD_GOOGLE_STORM is not set
#
# Stout
#
# CONFIG_BOARD_GOOGLE_STOUT is not set
#
# Trogdor
#
#
# (Trogdor requires 'Allow QC blobs repository')
#
#
# Veyron
#
# CONFIG_BOARD_GOOGLE_VEYRON_JAQ is not set
# CONFIG_BOARD_GOOGLE_VEYRON_JERRY is not set
# CONFIG_BOARD_GOOGLE_VEYRON_MIGHTY is not set
# CONFIG_BOARD_GOOGLE_VEYRON_MINNIE is not set
# CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY is not set
#
# Veyron Mickey
#
# CONFIG_BOARD_GOOGLE_VEYRON_MICKEY is not set
#
# Veyron Rialto
#
# CONFIG_BOARD_GOOGLE_VEYRON_RIALTO is not set
#
# Volteer
#
# CONFIG_BOARD_GOOGLE_CHRONICLER is not set
# CONFIG_BOARD_GOOGLE_COLLIS is not set
# CONFIG_BOARD_GOOGLE_COPANO is not set
# CONFIG_BOARD_GOOGLE_DELBIN is not set
# CONFIG_BOARD_GOOGLE_DROBIT is not set
# CONFIG_BOARD_GOOGLE_ELDRID is not set
# CONFIG_BOARD_GOOGLE_ELEMI is not set
# CONFIG_BOARD_GOOGLE_HALVOR is not set
# CONFIG_BOARD_GOOGLE_LINDAR is not set
# CONFIG_BOARD_GOOGLE_MALEFOR is not set
# CONFIG_BOARD_GOOGLE_TERRADOR is not set
# CONFIG_BOARD_GOOGLE_TODOR is not set
# CONFIG_BOARD_GOOGLE_TRONDO is not set
# CONFIG_BOARD_GOOGLE_VOEMA is not set
# CONFIG_BOARD_GOOGLE_VOLET is not set
# CONFIG_BOARD_GOOGLE_VOLTEER is not set
# CONFIG_BOARD_GOOGLE_VOLTEER2 is not set
# CONFIG_BOARD_GOOGLE_VOLTEER2_TI50 is not set
# CONFIG_BOARD_GOOGLE_VOXEL is not set
#
# Zork
#
# CONFIG_BOARD_GOOGLE_DALBOZ is not set
# CONFIG_BOARD_GOOGLE_VILBOZ is not set
# CONFIG_BOARD_GOOGLE_EZKINIL is not set
# CONFIG_BOARD_GOOGLE_MORPHIUS is not set
# CONFIG_BOARD_GOOGLE_TREMBYLE is not set
# CONFIG_BOARD_GOOGLE_BERKNIP is not set
# CONFIG_BOARD_GOOGLE_WOOMAX is not set
# CONFIG_BOARD_GOOGLE_DIRINBOZ is not set
# CONFIG_BOARD_GOOGLE_SHUBOZ is not set
# CONFIG_BOARD_GOOGLE_GUMBOZ is not set
CONFIG_DRIVER_TPM_SPI_BUS=0x0
CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x5
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_DRIVER_TPM_I2C_BUS=0x0
CONFIG_DRIVER_TPM_I2C_ADDR=0x20
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_PMIC_BUS=-1
CONFIG_BOARD_GOOGLE_GRU_COMMON=y
CONFIG_GRU_HAS_TPM2=y
CONFIG_GRU_HAS_CENTERLOG_PWM=y
CONFIG_GRU_HAS_WLAN_RESET=y
CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME=""
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US=0
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_TTYS0_BAUD=115200
CONFIG_D3COLD_SUPPORT=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_DRIVER_TPM_SPI_CHIP=0
# CONFIG_TPM_MEASURED_BOOT is not set
CONFIG_BOARD_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=8192
CONFIG_ROM_SIZE=0x00800000
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_ARM64_BL31_EXTERNAL_FILE=""
CONFIG_ARCH_ARMV8_EXTENSION=0
CONFIG_STACK_SIZE=0x0
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_GENERIC_UDELAY=y
CONFIG_SOC_ROCKCHIP_RK3399=y
CONFIG_RK3399_SPREAD_SPECTRUM_DDR=y
CONFIG_CBFS_CACHE_ALIGN=8
#
# CPU
#
#
# Northbridge
#
#
# Southbridge
#
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
#
# Embedded Controllers
#
CONFIG_EC_SUPPORTS_DPTF_TEVT=y
CONFIG_EC_GOOGLE_CHROMEEC=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP=0x0
CONFIG_EC_GOOGLE_CHROMEEC_RTC=y
CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_NONE=y
# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL is not set
# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN is not set
CONFIG_MAINBOARD_HAS_CHROMEOS=y
#
# ChromeOS
#
# end of ChromeOS
CONFIG_ARCH_ARM64=y
CONFIG_ARCH_BOOTBLOCK_ARM64=y
CONFIG_ARCH_VERSTAGE_ARM64=y
CONFIG_ARCH_ROMSTAGE_ARM64=y
CONFIG_ARCH_RAMSTAGE_ARM64=y
CONFIG_ARCH_BOOTBLOCK_ARMV8_64=y
CONFIG_ARCH_VERSTAGE_ARMV8_64=y
CONFIG_ARCH_ROMSTAGE_ARMV8_64=y
CONFIG_ARCH_RAMSTAGE_ARMV8_64=y
CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE=y
# end of Chipset
#
# Devices
#
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y
# CONFIG_BOOTSPLASH is not set
# end of Display
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_COMMON_CBFS_SPI_WRAPPER=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_TPM_INIT_RAMSTAGE=y
CONFIG_DRIVERS_UART=y
CONFIG_UART_OVERRIDE_REFCLK=y
CONFIG_DRIVERS_UART_8250MEM=y
CONFIG_DRIVERS_UART_8250MEM_32=y
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
CONFIG_SPI_TPM=y
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
CONFIG_TPM_GOOGLE=y
CONFIG_TPM_GOOGLE_CR50=y
CONFIG_TPM_GOOGLE_IMMEDIATELY_COMMIT_FW_SECDATA=y
CONFIG_GOOGLE_TPM_IRQ_TIMEOUT_MS=10
CONFIG_CR50_RESET_CLEAR_EC_AP_IDLE_FLAG=y
#
# Trusted Platform Module
#
# CONFIG_NO_TPM is not set
CONFIG_TPM2=y
CONFIG_TPM=y
CONFIG_MAINBOARD_HAS_TPM2=y
# CONFIG_DEBUG_TPM is not set
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
CONFIG_TPM_SETUP_HIBERNATE_ON_ERR=y
#
# Memory initialization
#
# end of Memory initialization
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_CUSTOM_MADT=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
#
# memory mapped, 8250-compatible
#
CONFIG_TTYS0_BASE=0x3f8
# CONFIG_CONSOLE_SERIAL_921600 is not set
# CONFIG_CONSOLE_SERIAL_460800 is not set
# CONFIG_CONSOLE_SERIAL_230400 is not set
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_CONSOLE_SERIAL_57600 is not set
# CONFIG_CONSOLE_SERIAL_38400 is not set
# CONFIG_CONSOLE_SERIAL_19200 is not set
# CONFIG_CONSOLE_SERIAL_9600 is not set
CONFIG_TTYS0_LCS=3
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
CONFIG_POST_DEVICE_NONE=y
CONFIG_HWBASE_DEBUG_CB=y
# end of Console
CONFIG_HAVE_MONOTONIC_TIMER=y
#
# System tables
#
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_GDB_STUB is not set
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_NO_XIP_EARLY_STAGES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/gru_bob/target.cfg
-6
View File
@@ -1,6 +0,0 @@
tree="default"
romtype="normal"
arch="AArch64"
payload_uboot="y"
vendorfiles="n"
microcode_required="n"
config/coreboot/gru_kevin/config/libgfxinit_corebootfb
-947
View File
@@ -1,947 +0,0 @@
#
# Automatically generated file; DO NOT EDIT.
# coreboot configuration
#
#
# General setup
#
CONFIG_COREBOOT_BUILD=y
CONFIG_LOCALVERSION=""
CONFIG_CBFS_PREFIX="fallback"
CONFIG_COMPILER_GCC=y
# CONFIG_ALLOW_EXPERIMENTAL_CLANG is not set
# CONFIG_ANY_TOOLCHAIN is not set
# CONFIG_CCACHE is not set
# CONFIG_IWYU is not set
# CONFIG_FMD_GENPARSER is not set
# CONFIG_UTIL_GENPARSER is not set
CONFIG_OPTION_BACKEND_NONE=y
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
CONFIG_COMPRESS_PRERAM_STAGES=y
CONFIG_COMPRESS_BOOTBLOCK=y
CONFIG_INCLUDE_CONFIG_FILE=y
# CONFIG_COLLECT_TIMESTAMPS is not set
# CONFIG_USE_BLOBS is not set
# CONFIG_COVERAGE is not set
# CONFIG_UBSAN is not set
# CONFIG_ASAN is not set
CONFIG_NO_STAGE_CACHE=y
# CONFIG_CBMEM_STAGE_CACHE is not set
# CONFIG_UPDATE_IMAGE is not set
# CONFIG_BOOTSPLASH_IMAGE is not set
# CONFIG_FW_CONFIG is not set
#
# Software Bill Of Materials (SBOM)
#
# CONFIG_SBOM is not set
# end of Software Bill Of Materials (SBOM)
# end of General setup
#
# Mainboard
#
#
# Important: Run 'make distclean' before switching boards
#
# CONFIG_VENDOR_51NB is not set
# CONFIG_VENDOR_ACER is not set
# CONFIG_VENDOR_ADLINK is not set
# CONFIG_VENDOR_AMD is not set
# CONFIG_VENDOR_AOPEN is not set
# CONFIG_VENDOR_APPLE is not set
# CONFIG_VENDOR_ASROCK is not set
# CONFIG_VENDOR_ASUS is not set
# CONFIG_VENDOR_BIOSTAR is not set
# CONFIG_VENDOR_BOSTENTECH is not set
# CONFIG_VENDOR_BYTEDANCE is not set
# CONFIG_VENDOR_CAVIUM is not set
# CONFIG_VENDOR_CLEVO is not set
# CONFIG_VENDOR_COMPULAB is not set
# CONFIG_VENDOR_DELL is not set
# CONFIG_VENDOR_EMULATION is not set
# CONFIG_VENDOR_EXAMPLE is not set
# CONFIG_VENDOR_FACEBOOK is not set
# CONFIG_VENDOR_FOXCONN is not set
# CONFIG_VENDOR_GETAC is not set
# CONFIG_VENDOR_GIGABYTE is not set
CONFIG_VENDOR_GOOGLE=y
# CONFIG_VENDOR_HP is not set
# CONFIG_VENDOR_IBASE is not set
# CONFIG_VENDOR_IBM is not set
# CONFIG_VENDOR_INTEL is not set
# CONFIG_VENDOR_INVENTEC is not set
# CONFIG_VENDOR_KONTRON is not set
# CONFIG_VENDOR_LENOVO is not set
# CONFIG_VENDOR_LIBRETREND is not set
# CONFIG_VENDOR_MSI is not set
# CONFIG_VENDOR_OCP is not set
# CONFIG_VENDOR_OPENCELLULAR is not set
# CONFIG_VENDOR_PACKARDBELL is not set
# CONFIG_VENDOR_PCENGINES is not set
# CONFIG_VENDOR_PINE64 is not set
# CONFIG_VENDOR_PORTWELL is not set
# CONFIG_VENDOR_PRODRIVE is not set
# CONFIG_VENDOR_PROTECTLI is not set
# CONFIG_VENDOR_PURISM is not set
# CONFIG_VENDOR_RAZER is not set
# CONFIG_VENDOR_RODA is not set
# CONFIG_VENDOR_SAMSUNG is not set
# CONFIG_VENDOR_SAPPHIRE is not set
# CONFIG_VENDOR_SIEMENS is not set
# CONFIG_VENDOR_SIFIVE is not set
# CONFIG_VENDOR_STARLABS is not set
# CONFIG_VENDOR_SUPERMICRO is not set
# CONFIG_VENDOR_SYSTEM76 is not set
# CONFIG_VENDOR_TI is not set
# CONFIG_VENDOR_UP is not set
CONFIG_BOARD_SPECIFIC_OPTIONS=y
CONFIG_MAINBOARD_PART_NUMBER="Kevin"
CONFIG_MAINBOARD_DIR="google/gru"
CONFIG_DIMM_MAX=4
CONFIG_DIMM_SPD_SIZE=256
CONFIG_FMDFILE=""
# CONFIG_NO_POST is not set
CONFIG_MAINBOARD_VENDOR="Google"
CONFIG_CBFS_SIZE=0x00800000
CONFIG_CONSOLE_SERIAL=y
CONFIG_MAX_CPUS=1
CONFIG_POST_DEVICE=y
CONFIG_UART_FOR_CONSOLE=0
CONFIG_DEVICETREE="devicetree.cb"
# CONFIG_VBOOT is not set
# CONFIG_CHROMEOS is not set
CONFIG_OVERRIDE_DEVICETREE=""
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=1
CONFIG_CONSOLE_SERIAL_UART_ADDRESS=0xFF1A0000
# CONFIG_CONSOLE_POST is not set
CONFIG_MEMLAYOUT_LD_FILE="src/soc/rockchip/rk3399/memlayout.ld"
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
CONFIG_SPI_FLASH_WINBOND=y
#
# Asurada
#
# CONFIG_BOARD_GOOGLE_ASURADA is not set
# CONFIG_BOARD_GOOGLE_HAYATO is not set
# CONFIG_BOARD_GOOGLE_SPHERION is not set
#
# Auron
#
# CONFIG_BOARD_GOOGLE_AURON_PAINE is not set
# CONFIG_BOARD_GOOGLE_AURON_YUNA is not set
# CONFIG_BOARD_GOOGLE_BUDDY is not set
# CONFIG_BOARD_GOOGLE_GANDOF is not set
# CONFIG_BOARD_GOOGLE_LULU is not set
# CONFIG_BOARD_GOOGLE_SAMUS is not set
#
# Beltino
#
# CONFIG_BOARD_GOOGLE_MCCLOUD is not set
# CONFIG_BOARD_GOOGLE_MONROE is not set
# CONFIG_BOARD_GOOGLE_PANTHER is not set
# CONFIG_BOARD_GOOGLE_TRICKY is not set
# CONFIG_BOARD_GOOGLE_ZAKO is not set
#
# Brya
#
# CONFIG_BOARD_GOOGLE_AGAH is not set
# CONFIG_BOARD_GOOGLE_ANAHERA is not set
# CONFIG_BOARD_GOOGLE_ANAHERA4ES is not set
# CONFIG_BOARD_GOOGLE_AURASH is not set
# CONFIG_BOARD_GOOGLE_BANSHEE is not set
# CONFIG_BOARD_GOOGLE_BRASK is not set
# CONFIG_BOARD_GOOGLE_BRYA0 is not set
# CONFIG_BOARD_GOOGLE_CRAASK is not set
# CONFIG_BOARD_GOOGLE_CRAASKOV is not set
# CONFIG_BOARD_GOOGLE_CONSTITUTION is not set
# CONFIG_BOARD_GOOGLE_CROTA is not set
# CONFIG_BOARD_GOOGLE_FELWINTER is not set
# CONFIG_BOARD_GOOGLE_GAELIN is not set
# CONFIG_BOARD_GOOGLE_GIMBLE is not set
# CONFIG_BOARD_GOOGLE_GIMBLE4ES is not set
# CONFIG_BOARD_GOOGLE_GLADIOS is not set
# CONFIG_BOARD_GOOGLE_GOTHRAX is not set
# CONFIG_BOARD_GOOGLE_HADES is not set
# CONFIG_BOARD_GOOGLE_KANO is not set
# CONFIG_BOARD_GOOGLE_KINOX is not set
# CONFIG_BOARD_GOOGLE_KULDAX is not set
# CONFIG_BOARD_GOOGLE_JOXER is not set
# CONFIG_BOARD_GOOGLE_LISBON is not set
# CONFIG_BOARD_GOOGLE_MARASOV is not set
# CONFIG_BOARD_GOOGLE_MITHRAX is not set
# CONFIG_BOARD_GOOGLE_MOLI is not set
# CONFIG_BOARD_GOOGLE_NIVVIKS is not set
# CONFIG_BOARD_GOOGLE_NEREID is not set
# CONFIG_BOARD_GOOGLE_OMNIGUL is not set
# CONFIG_BOARD_GOOGLE_OSIRIS is not set
# CONFIG_BOARD_GOOGLE_PIRRHA is not set
# CONFIG_BOARD_GOOGLE_PRIMUS is not set
# CONFIG_BOARD_GOOGLE_PRIMUS4ES is not set
# CONFIG_BOARD_GOOGLE_PUJJO is not set
# CONFIG_BOARD_GOOGLE_QUANDISO is not set
# CONFIG_BOARD_GOOGLE_REDRIX is not set
# CONFIG_BOARD_GOOGLE_REDRIX4ES is not set
# CONFIG_BOARD_GOOGLE_SKOLAS is not set
# CONFIG_BOARD_GOOGLE_SKOLAS4ES is not set
# CONFIG_BOARD_GOOGLE_TAEKO is not set
# CONFIG_BOARD_GOOGLE_TAEKO4ES is not set
# CONFIG_BOARD_GOOGLE_TANIKS is not set
# CONFIG_BOARD_GOOGLE_ULDREN is not set
# CONFIG_BOARD_GOOGLE_VELL is not set
# CONFIG_BOARD_GOOGLE_VOLMAR is not set
# CONFIG_BOARD_GOOGLE_XIVU is not set
# CONFIG_BOARD_GOOGLE_YAVIKS is not set
# CONFIG_BOARD_GOOGLE_YAVILLA is not set
# CONFIG_BOARD_GOOGLE_ZYDRON is not set
# CONFIG_BOARD_GOOGLE_NOKRIS is not set
# CONFIG_BOARD_GOOGLE_DOCHI is not set
#
# Butterfly
#
# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set
#
# Cherry
#
# CONFIG_BOARD_GOOGLE_CHERRY is not set
# CONFIG_BOARD_GOOGLE_DOJO is not set
# CONFIG_BOARD_GOOGLE_TOMATO is not set
#
# Kingler
#
# CONFIG_BOARD_GOOGLE_KINGLER is not set
# CONFIG_BOARD_GOOGLE_STEELIX is not set
# CONFIG_BOARD_GOOGLE_VOLTORB is not set
# CONFIG_BOARD_GOOGLE_PONYTA is not set
#
# Krabby
#
# CONFIG_BOARD_GOOGLE_KRABBY is not set
# CONFIG_BOARD_GOOGLE_TENTACRUEL is not set
# CONFIG_BOARD_GOOGLE_MAGIKARP is not set
#
# Staryu
#
# CONFIG_BOARD_GOOGLE_STARMIE is not set
#
# Cyan
#
# CONFIG_BOARD_GOOGLE_BANON is not set
# CONFIG_BOARD_GOOGLE_CELES is not set
# CONFIG_BOARD_GOOGLE_CYAN is not set
# CONFIG_BOARD_GOOGLE_EDGAR is not set
# CONFIG_BOARD_GOOGLE_KEFKA is not set
# CONFIG_BOARD_GOOGLE_REKS is not set
# CONFIG_BOARD_GOOGLE_RELM is not set
# CONFIG_BOARD_GOOGLE_SETZER is not set
# CONFIG_BOARD_GOOGLE_TERRA is not set
# CONFIG_BOARD_GOOGLE_ULTIMA is not set
# CONFIG_BOARD_GOOGLE_WIZPIG is not set
#
# Daisy
#
# CONFIG_BOARD_GOOGLE_DAISY is not set
#
# Dedede
#
# CONFIG_BOARD_GOOGLE_BOTEN is not set
# CONFIG_BOARD_GOOGLE_DIBBI is not set
# CONFIG_BOARD_GOOGLE_DEDEDE is not set
# CONFIG_BOARD_GOOGLE_DRAWCIA is not set
# CONFIG_BOARD_GOOGLE_HABOKI is not set
# CONFIG_BOARD_GOOGLE_MADOO is not set
# CONFIG_BOARD_GOOGLE_WADDLEDOO is not set
# CONFIG_BOARD_GOOGLE_WADDLEDEE is not set
# CONFIG_BOARD_GOOGLE_LALALA is not set
# CONFIG_BOARD_GOOGLE_MAGOLOR is not set
# CONFIG_BOARD_GOOGLE_METAKNIGHT is not set
# CONFIG_BOARD_GOOGLE_LANTIS is not set
# CONFIG_BOARD_GOOGLE_GALTIC is not set
# CONFIG_BOARD_GOOGLE_SASUKE is not set
# CONFIG_BOARD_GOOGLE_STORO is not set
# CONFIG_BOARD_GOOGLE_SASUKETTE is not set
# CONFIG_BOARD_GOOGLE_KRACKO is not set
# CONFIG_BOARD_GOOGLE_BLIPPER is not set
# CONFIG_BOARD_GOOGLE_CRET is not set
# CONFIG_BOARD_GOOGLE_PIRIKA is not set
# CONFIG_BOARD_GOOGLE_CAPPY2 is not set
# CONFIG_BOARD_GOOGLE_BUGZZY is not set
# CONFIG_BOARD_GOOGLE_CORORI is not set
# CONFIG_BOARD_GOOGLE_DRIBLEE is not set
# CONFIG_BOARD_GOOGLE_GOOEY is not set
# CONFIG_BOARD_GOOGLE_BEADRIX is not set
# CONFIG_BOARD_GOOGLE_SHOTZO is not set
# CONFIG_BOARD_GOOGLE_TARANZA is not set
# CONFIG_BOARD_GOOGLE_BOXY is not set
# CONFIG_BOARD_GOOGLE_DEXI is not set
#
# Drallion
#
# CONFIG_BOARD_GOOGLE_DRALLION is not set
#
# Eve
#
# CONFIG_BOARD_GOOGLE_EVE is not set
#
# Fizz
#
# CONFIG_BOARD_GOOGLE_FIZZ is not set
# CONFIG_BOARD_GOOGLE_KARMA is not set
# CONFIG_BOARD_GOOGLE_ENDEAVOUR is not set
#
# Foster
#
# CONFIG_BOARD_GOOGLE_FOSTER is not set
#
# Gale
#
# CONFIG_BOARD_GOOGLE_GALE is not set
#
# Geralt
#
# CONFIG_BOARD_GOOGLE_GERALT is not set
#
# Glados
#
# CONFIG_BOARD_GOOGLE_ASUKA is not set
# CONFIG_BOARD_GOOGLE_CAROLINE is not set
# CONFIG_BOARD_GOOGLE_CAVE is not set
# CONFIG_BOARD_GOOGLE_CHELL is not set
# CONFIG_BOARD_GOOGLE_GLADOS is not set
# CONFIG_BOARD_GOOGLE_LARS is not set
# CONFIG_BOARD_GOOGLE_SENTRY is not set
#
# Gru
#
CONFIG_BOARD_GOOGLE_KEVIN=y
# CONFIG_BOARD_GOOGLE_GRU is not set
# CONFIG_BOARD_GOOGLE_BOB is not set
# CONFIG_BOARD_GOOGLE_SCARLET is not set
# CONFIG_BOARD_GOOGLE_NEFARIO is not set
# CONFIG_BOARD_GOOGLE_RAINIER is not set
#
# Guybrush
#
# CONFIG_BOARD_GOOGLE_GUYBRUSH is not set
# CONFIG_BOARD_GOOGLE_NIPPERKIN is not set
# CONFIG_BOARD_GOOGLE_DEWATT is not set
#
# Hatch
#
# CONFIG_BOARD_GOOGLE_AKEMI is not set
# CONFIG_BOARD_GOOGLE_DRATINI is not set
# CONFIG_BOARD_GOOGLE_HATCH is not set
# CONFIG_BOARD_GOOGLE_HELIOS is not set
# CONFIG_BOARD_GOOGLE_HELIOS_DISKSWAP is not set
# CONFIG_BOARD_GOOGLE_JINLON is not set
# CONFIG_BOARD_GOOGLE_KINDRED is not set
# CONFIG_BOARD_GOOGLE_KOHAKU is not set
# CONFIG_BOARD_GOOGLE_MUSHU is not set
# CONFIG_BOARD_GOOGLE_NIGHTFURY is not set
# CONFIG_BOARD_GOOGLE_PALKIA is not set
#
# Herobrine
#
#
# (Herobrine requires 'Allow QC blobs repository')
#
#
# Jecht
#
# CONFIG_BOARD_GOOGLE_GUADO is not set
# CONFIG_BOARD_GOOGLE_JECHT is not set
# CONFIG_BOARD_GOOGLE_RIKKU is not set
# CONFIG_BOARD_GOOGLE_TIDUS is not set
#
# Kahlee
#
# CONFIG_BOARD_GOOGLE_ALEENA is not set
# CONFIG_BOARD_GOOGLE_CAREENA is not set
# CONFIG_BOARD_GOOGLE_GRUNT is not set
# CONFIG_BOARD_GOOGLE_LIARA is not set
# CONFIG_BOARD_GOOGLE_NUWANI is not set
# CONFIG_BOARD_GOOGLE_TREEYA is not set
#
# Kukui
#
# CONFIG_BOARD_GOOGLE_KUKUI is not set
# CONFIG_BOARD_GOOGLE_KRANE is not set
# CONFIG_BOARD_GOOGLE_KODAMA is not set
# CONFIG_BOARD_GOOGLE_KAKADU is not set
# CONFIG_BOARD_GOOGLE_FLAPJACK is not set
# CONFIG_BOARD_GOOGLE_KATSU is not set
#
# Jacuzzi
#
# CONFIG_BOARD_GOOGLE_JACUZZI is not set
# CONFIG_BOARD_GOOGLE_JUNIPER is not set
# CONFIG_BOARD_GOOGLE_KAPPA is not set
# CONFIG_BOARD_GOOGLE_DAMU is not set
# CONFIG_BOARD_GOOGLE_CERISE is not set
# CONFIG_BOARD_GOOGLE_STERN is not set
# CONFIG_BOARD_GOOGLE_WILLOW is not set
# CONFIG_BOARD_GOOGLE_ESCHE is not set
# CONFIG_BOARD_GOOGLE_BURNET is not set
# CONFIG_BOARD_GOOGLE_FENNEL is not set
# CONFIG_BOARD_GOOGLE_COZMO is not set
# CONFIG_BOARD_GOOGLE_MAKOMO is not set
# CONFIG_BOARD_GOOGLE_MUNNA is not set
# CONFIG_BOARD_GOOGLE_PICO is not set
#
# Link
#
# CONFIG_BOARD_GOOGLE_LINK is not set
#
# Mistral
#
# CONFIG_BOARD_GOOGLE_MISTRAL is not set
#
# Myst
#
# CONFIG_BOARD_GOOGLE_MYST is not set
#
# Nyan
#
# CONFIG_BOARD_GOOGLE_NYAN is not set
#
# Nyan Big
#
# CONFIG_BOARD_GOOGLE_NYAN_BIG is not set
#
# Nyan Blaze
#
# CONFIG_BOARD_GOOGLE_NYAN_BLAZE is not set
#
# Oak
#
# CONFIG_BOARD_GOOGLE_OAK is not set
# CONFIG_BOARD_GOOGLE_ELM is not set
# CONFIG_BOARD_GOOGLE_HANA is not set
#
# Octopus
#
# CONFIG_BOARD_GOOGLE_AMPTON is not set
# CONFIG_BOARD_GOOGLE_BLOOG is not set
# CONFIG_BOARD_GOOGLE_BOBBA is not set
# CONFIG_BOARD_GOOGLE_CASTA is not set
# CONFIG_BOARD_GOOGLE_DOOD is not set
# CONFIG_BOARD_GOOGLE_FLEEX is not set
# CONFIG_BOARD_GOOGLE_FOOB is not set
# CONFIG_BOARD_GOOGLE_GARG is not set
# CONFIG_BOARD_GOOGLE_LICK is not set
# CONFIG_BOARD_GOOGLE_MEEP is not set
# CONFIG_BOARD_GOOGLE_OCTOPUS is not set
# CONFIG_BOARD_GOOGLE_PHASER is not set
# CONFIG_BOARD_GOOGLE_YORP is not set
#
# Parrot
#
# CONFIG_BOARD_GOOGLE_PARROT is not set
#
# Peach Pit
#
# CONFIG_BOARD_GOOGLE_PEACH_PIT is not set
#
# Poppy
#
# CONFIG_BOARD_GOOGLE_ATLAS is not set
# CONFIG_BOARD_GOOGLE_POPPY is not set
# CONFIG_BOARD_GOOGLE_NAMI is not set
# CONFIG_BOARD_GOOGLE_NAUTILUS is not set
# CONFIG_BOARD_GOOGLE_NOCTURNE is not set
# CONFIG_BOARD_GOOGLE_RAMMUS is not set
# CONFIG_BOARD_GOOGLE_SORAKA is not set
#
# Puff
#
# CONFIG_BOARD_GOOGLE_AMBASSADOR is not set
# CONFIG_BOARD_GOOGLE_DOOLY is not set
# CONFIG_BOARD_GOOGLE_DUFFY_LEGACY is not set
# CONFIG_BOARD_GOOGLE_DUFFY is not set
# CONFIG_BOARD_GOOGLE_FAFFY is not set
# CONFIG_BOARD_GOOGLE_GENESIS is not set
# CONFIG_BOARD_GOOGLE_KAISA_LEGACY is not set
# CONFIG_BOARD_GOOGLE_KAISA is not set
# CONFIG_BOARD_GOOGLE_MOONBUGGY is not set
# CONFIG_BOARD_GOOGLE_NOIBAT is not set
# CONFIG_BOARD_GOOGLE_PUFF is not set
# CONFIG_BOARD_GOOGLE_SCOUT is not set
# CONFIG_BOARD_GOOGLE_WYVERN is not set
#
# Rambi
#
# CONFIG_BOARD_GOOGLE_BANJO is not set
# CONFIG_BOARD_GOOGLE_CANDY is not set
# CONFIG_BOARD_GOOGLE_CLAPPER is not set
# CONFIG_BOARD_GOOGLE_ENGUARDE is not set
# CONFIG_BOARD_GOOGLE_EXPRESSO is not set
# CONFIG_BOARD_GOOGLE_GLIMMER is not set
# CONFIG_BOARD_GOOGLE_GNAWTY is not set
# CONFIG_BOARD_GOOGLE_HELI is not set
# CONFIG_BOARD_GOOGLE_KIP is not set
# CONFIG_BOARD_GOOGLE_NINJA is not set
# CONFIG_BOARD_GOOGLE_ORCO is not set
# CONFIG_BOARD_GOOGLE_QUAWKS is not set
# CONFIG_BOARD_GOOGLE_SQUAWKS is not set
# CONFIG_BOARD_GOOGLE_RAMBI is not set
# CONFIG_BOARD_GOOGLE_SUMO is not set
# CONFIG_BOARD_GOOGLE_SWANKY is not set
# CONFIG_BOARD_GOOGLE_WINKY is not set
#
# Reef
#
# CONFIG_BOARD_GOOGLE_REEF is not set
# CONFIG_BOARD_GOOGLE_PYRO is not set
# CONFIG_BOARD_GOOGLE_SAND is not set
# CONFIG_BOARD_GOOGLE_SNAPPY is not set
# CONFIG_BOARD_GOOGLE_CORAL is not set
#
# Rex
#
# CONFIG_BOARD_GOOGLE_REX0 is not set
# CONFIG_BOARD_GOOGLE_SCREEBO is not set
# CONFIG_BOARD_GOOGLE_SCREEBO4ES is not set
# CONFIG_BOARD_GOOGLE_KARIS is not set
# CONFIG_BOARD_GOOGLE_KARIS4ES is not set
# CONFIG_BOARD_GOOGLE_REX_EC_ISH is not set
# CONFIG_BOARD_GOOGLE_OVIS is not set
# CONFIG_BOARD_GOOGLE_OVIS4ES is not set
# CONFIG_BOARD_GOOGLE_REX4ES is not set
# CONFIG_BOARD_GOOGLE_REX4ES_EC_ISH is not set
#
# Sarien
#
# CONFIG_BOARD_GOOGLE_ARCADA is not set
# CONFIG_BOARD_GOOGLE_SARIEN is not set
#
# Skyrim
#
# CONFIG_BOARD_GOOGLE_SKYRIM is not set
# CONFIG_BOARD_GOOGLE_WINTERHOLD is not set
# CONFIG_BOARD_GOOGLE_FROSTFLOW is not set
# CONFIG_BOARD_GOOGLE_CRYSTALDRIFT is not set
# CONFIG_BOARD_GOOGLE_MARKARTH is not set
#
# Slippy
#
# CONFIG_BOARD_GOOGLE_FALCO is not set
# CONFIG_BOARD_GOOGLE_LEON is not set
# CONFIG_BOARD_GOOGLE_PEPPY is not set
# CONFIG_BOARD_GOOGLE_WOLF is not set
#
# Smaug
#
# CONFIG_BOARD_GOOGLE_SMAUG is not set
#
# Storm
#
# CONFIG_BOARD_GOOGLE_STORM is not set
#
# Stout
#
# CONFIG_BOARD_GOOGLE_STOUT is not set
#
# Trogdor
#
#
# (Trogdor requires 'Allow QC blobs repository')
#
#
# Veyron
#
# CONFIG_BOARD_GOOGLE_VEYRON_JAQ is not set
# CONFIG_BOARD_GOOGLE_VEYRON_JERRY is not set
# CONFIG_BOARD_GOOGLE_VEYRON_MIGHTY is not set
# CONFIG_BOARD_GOOGLE_VEYRON_MINNIE is not set
# CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY is not set
#
# Veyron Mickey
#
# CONFIG_BOARD_GOOGLE_VEYRON_MICKEY is not set
#
# Veyron Rialto
#
# CONFIG_BOARD_GOOGLE_VEYRON_RIALTO is not set
#
# Volteer
#
# CONFIG_BOARD_GOOGLE_CHRONICLER is not set
# CONFIG_BOARD_GOOGLE_COLLIS is not set
# CONFIG_BOARD_GOOGLE_COPANO is not set
# CONFIG_BOARD_GOOGLE_DELBIN is not set
# CONFIG_BOARD_GOOGLE_DROBIT is not set
# CONFIG_BOARD_GOOGLE_ELDRID is not set
# CONFIG_BOARD_GOOGLE_ELEMI is not set
# CONFIG_BOARD_GOOGLE_HALVOR is not set
# CONFIG_BOARD_GOOGLE_LINDAR is not set
# CONFIG_BOARD_GOOGLE_MALEFOR is not set
# CONFIG_BOARD_GOOGLE_TERRADOR is not set
# CONFIG_BOARD_GOOGLE_TODOR is not set
# CONFIG_BOARD_GOOGLE_TRONDO is not set
# CONFIG_BOARD_GOOGLE_VOEMA is not set
# CONFIG_BOARD_GOOGLE_VOLET is not set
# CONFIG_BOARD_GOOGLE_VOLTEER is not set
# CONFIG_BOARD_GOOGLE_VOLTEER2 is not set
# CONFIG_BOARD_GOOGLE_VOLTEER2_TI50 is not set
# CONFIG_BOARD_GOOGLE_VOXEL is not set
#
# Zork
#
# CONFIG_BOARD_GOOGLE_DALBOZ is not set
# CONFIG_BOARD_GOOGLE_VILBOZ is not set
# CONFIG_BOARD_GOOGLE_EZKINIL is not set
# CONFIG_BOARD_GOOGLE_MORPHIUS is not set
# CONFIG_BOARD_GOOGLE_TREMBYLE is not set
# CONFIG_BOARD_GOOGLE_BERKNIP is not set
# CONFIG_BOARD_GOOGLE_WOOMAX is not set
# CONFIG_BOARD_GOOGLE_DIRINBOZ is not set
# CONFIG_BOARD_GOOGLE_SHUBOZ is not set
# CONFIG_BOARD_GOOGLE_GUMBOZ is not set
CONFIG_DRIVER_TPM_SPI_BUS=0x0
CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x5
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
CONFIG_DRIVER_TPM_I2C_BUS=0x0
CONFIG_DRIVER_TPM_I2C_ADDR=0x20
CONFIG_VBT_DATA_SIZE_KB=8
CONFIG_PMIC_BUS=-1
CONFIG_BOARD_GOOGLE_GRU_COMMON=y
# CONFIG_GRU_HAS_TPM2 is not set
CONFIG_GRU_HAS_CENTERLOG_PWM=y
CONFIG_GRU_HAS_WLAN_RESET=y
CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME=""
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
CONFIG_SPI_FLASH_GIGADEVICE=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US=0
CONFIG_PS2K_EISAID="PNP0303"
CONFIG_PS2M_EISAID="PNP0F13"
CONFIG_TTYS0_BAUD=115200
CONFIG_D3COLD_SUPPORT=y
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
# CONFIG_TPM_MEASURED_BOOT is not set
CONFIG_BOARD_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
CONFIG_COREBOOT_ROMSIZE_KB=8192
CONFIG_ROM_SIZE=0x00800000
# end of Mainboard
#
# Chipset
#
#
# SoC
#
CONFIG_CHIPSET_DEVICETREE=""
CONFIG_ARM64_BL31_EXTERNAL_FILE=""
CONFIG_ARCH_ARMV8_EXTENSION=0
CONFIG_STACK_SIZE=0x0
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
CONFIG_INTEL_GMA_BCLV_WIDTH=16
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
CONFIG_INTEL_GMA_BCLM_WIDTH=16
CONFIG_GENERIC_UDELAY=y
CONFIG_SOC_ROCKCHIP_RK3399=y
# CONFIG_RK3399_SPREAD_SPECTRUM_DDR is not set
CONFIG_CBFS_CACHE_ALIGN=8
#
# CPU
#
#
# Northbridge
#
#
# Southbridge
#
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
CONFIG_RCBA_LENGTH=0x4000
#
# Super I/O
#
#
# Embedded Controllers
#
CONFIG_EC_SUPPORTS_DPTF_TEVT=y
CONFIG_EC_GOOGLE_CHROMEEC=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI=y
CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP=0x0
CONFIG_EC_GOOGLE_CHROMEEC_RTC=y
CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_NONE=y
# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL is not set
# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN is not set
CONFIG_MAINBOARD_HAS_CHROMEOS=y
#
# ChromeOS
#
# end of ChromeOS
CONFIG_ARCH_ARM64=y
CONFIG_ARCH_BOOTBLOCK_ARM64=y
CONFIG_ARCH_VERSTAGE_ARM64=y
CONFIG_ARCH_ROMSTAGE_ARM64=y
CONFIG_ARCH_RAMSTAGE_ARM64=y
CONFIG_ARCH_BOOTBLOCK_ARMV8_64=y
CONFIG_ARCH_VERSTAGE_ARMV8_64=y
CONFIG_ARCH_ROMSTAGE_ARMV8_64=y
CONFIG_ARCH_RAMSTAGE_ARMV8_64=y
CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE=y
# end of Chipset
#
# Devices
#
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
CONFIG_NO_EARLY_GFX_INIT=y
#
# Display
#
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
CONFIG_LINEAR_FRAMEBUFFER=y
# CONFIG_BOOTSPLASH is not set
# end of Display
CONFIG_FIRMWARE_CONNECTION_MANAGER=y
# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
# CONFIG_SOFTWARE_I2C is not set
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
# end of Devices
#
# Generic Drivers
#
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
# CONFIG_ELOG is not set
CONFIG_COMMON_CBFS_SPI_WRAPPER=y
CONFIG_SPI_FLASH=y
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
CONFIG_TPM_INIT_RAMSTAGE=y
CONFIG_DRIVERS_UART=y
CONFIG_UART_OVERRIDE_REFCLK=y
CONFIG_DRIVERS_UART_8250MEM=y
CONFIG_DRIVERS_UART_8250MEM_32=y
# CONFIG_VPD is not set
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
CONFIG_I2C_TPM=y
CONFIG_DRIVER_TIS_DEFAULT=y
# CONFIG_DRIVER_I2C_TPM_ACPI is not set
# CONFIG_DRIVER_TPM_DISPLAY_TIS_BYTES is not set
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
# end of Generic Drivers
#
# Security
#
#
# CBFS verification
#
# CONFIG_CBFS_VERIFICATION is not set
# end of CBFS verification
#
# Verified Boot (vboot)
#
# end of Verified Boot (vboot)
#
# Trusted Platform Module
#
# CONFIG_NO_TPM is not set
CONFIG_TPM1=y
CONFIG_TPM=y
CONFIG_MAINBOARD_HAS_TPM1=y
# CONFIG_TPM_DEACTIVATE is not set
# CONFIG_DEBUG_TPM is not set
CONFIG_PCR_BOOT_MODE=1
CONFIG_PCR_HWID=1
CONFIG_PCR_SRTM=2
CONFIG_PCR_RUNTIME_DATA=3
# end of Trusted Platform Module
CONFIG_TPM_SETUP_HIBERNATE_ON_ERR=y
#
# Memory initialization
#
# end of Memory initialization
CONFIG_BOOTMEDIA_LOCK_NONE=y
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
# end of Security
CONFIG_ACPI_HAVE_PCAT_8259=y
CONFIG_ACPI_CUSTOM_MADT=y
CONFIG_BOOT_DEVICE_SPI_FLASH=y
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
CONFIG_RTC=y
#
# Console
#
CONFIG_BOOTBLOCK_CONSOLE=y
#
# memory mapped, 8250-compatible
#
CONFIG_TTYS0_BASE=0x3f8
# CONFIG_CONSOLE_SERIAL_921600 is not set
# CONFIG_CONSOLE_SERIAL_460800 is not set
# CONFIG_CONSOLE_SERIAL_230400 is not set
CONFIG_CONSOLE_SERIAL_115200=y
# CONFIG_CONSOLE_SERIAL_57600 is not set
# CONFIG_CONSOLE_SERIAL_38400 is not set
# CONFIG_CONSOLE_SERIAL_19200 is not set
# CONFIG_CONSOLE_SERIAL_9600 is not set
CONFIG_TTYS0_LCS=3
CONFIG_CONSOLE_CBMEM=y
# CONFIG_CONSOLE_SPI_FLASH is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
CONFIG_POST_DEVICE_NONE=y
CONFIG_HWBASE_DEBUG_CB=y
# end of Console
CONFIG_HAVE_MONOTONIC_TIMER=y
#
# System tables
#
# end of System tables
#
# Payload
#
CONFIG_PAYLOAD_NONE=y
# end of Payload
#
# Debugging
#
#
# CPU Debug Settings
#
#
# BLOB Debug Settings
#
#
# General Debug Settings
#
# CONFIG_GDB_STUB is not set
# CONFIG_FATAL_ASSERTS is not set
# CONFIG_DEBUG_CBFS is not set
# CONFIG_DEBUG_MALLOC is not set
# CONFIG_DEBUG_CONSOLE_INIT is not set
# CONFIG_DEBUG_SPI_FLASH is not set
# CONFIG_DEBUG_BOOT_STATE is not set
# CONFIG_DEBUG_ADA_CODE is not set
# end of Debugging
CONFIG_DECOMPRESS_OFAST=y
CONFIG_WARNINGS_ARE_ERRORS=y
CONFIG_MAX_REBOOT_CNT=3
CONFIG_NO_XIP_EARLY_STAGES=y
CONFIG_GENERIC_GPIO_LIB=y
CONFIG_HAVE_BOOTBLOCK=y
CONFIG_HAVE_ROMSTAGE=y
CONFIG_HAVE_RAMSTAGE=y
config/coreboot/gru_kevin/target.cfg
-6
View File
@@ -1,6 +0,0 @@
tree="default"
romtype="normal"
arch="AArch64"
payload_uboot="y"
vendorfiles="n"
microcode_required="n"
config/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch
-54
View File
@@ -1,54 +0,0 @@
From dd58f5e9108bc596c93071705d2b53233d13ade6 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 20:36:10 +0200
Subject: [PATCH 01/26] commonlib/clamp.h: Add more clamping functions
Add more clamping functions that work with different types.
Change-Id: I14cf335d5a54f769f8fd9184450957e876affd6b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
src/commonlib/include/commonlib/clamp.h | 26 +++++++++++++++++--------
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/src/commonlib/include/commonlib/clamp.h b/src/commonlib/include/commonlib/clamp.h
index e01a107ed4..526185195c 100644
--- a/src/commonlib/include/commonlib/clamp.h
+++ b/src/commonlib/include/commonlib/clamp.h
@@ -8,15 +8,25 @@
/*
* Clamp a value, so that it is between a lower and an upper bound.
*/
-static inline u32 clamp_u32(const u32 min, const u32 val, const u32 max)
-{
- if (val > max)
- return max;
+#define __MAKE_CLAMP_FUNC(type) \
+ static inline type clamp_##type(const type min, const type val, const type max) \
+ { \
+ if (val > max) \
+ return max; \
+ if (val < min) \
+ return min; \
+ return val; \
+ } \
- if (val < min)
- return min;
+__MAKE_CLAMP_FUNC(s8) /* clamp_s8 */
+__MAKE_CLAMP_FUNC(u8) /* clamp_u8 */
+__MAKE_CLAMP_FUNC(s16) /* clamp_s16 */
+__MAKE_CLAMP_FUNC(u16) /* clamp_u16 */
+__MAKE_CLAMP_FUNC(s32) /* clamp_s32 */
+__MAKE_CLAMP_FUNC(u32) /* clamp_u32 */
+__MAKE_CLAMP_FUNC(s64) /* clamp_s64 */
+__MAKE_CLAMP_FUNC(u64) /* clamp_u64 */
- return val;
-}
+#undef __MAKE_CLAMP_FUNC
#endif /* COMMONLIB_CLAMP_H */
--
2.39.2
config/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch
-143
View File
@@ -1,143 +0,0 @@
From c07391821c32cafea950574b85468f5b3284b6df Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 6 May 2022 21:12:14 +0200
Subject: [PATCH 02/26] nb/intel/haswell: Introduce option to not use MRC.bin
Introduce the `USE_NATIVE_RAMINIT` Kconfig option, which should allow
booting coreboot on Haswell mainboards without the need of the closed
source MRC.bin. For now, this option does not work at all; the needed
magic will be implemented in subsequent commits. Add a config file to
make sure the newly-introduced option gets build-tested.
Change-Id: I46c77586f9b5771624082e07c60c205e578edd8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
configs/config.asrock_b85m_pro4.native_raminit | 5 +++++
src/northbridge/intel/haswell/Kconfig | 13 +++++++++++++
src/northbridge/intel/haswell/Makefile.inc | 7 ++++++-
.../intel/haswell/native_raminit/Makefile.inc | 3 +++
.../intel/haswell/native_raminit/raminit_native.c | 15 +++++++++++++++
5 files changed, 42 insertions(+), 1 deletion(-)
create mode 100644 configs/config.asrock_b85m_pro4.native_raminit
create mode 100644 src/northbridge/intel/haswell/native_raminit/Makefile.inc
create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.c
diff --git a/configs/config.asrock_b85m_pro4.native_raminit b/configs/config.asrock_b85m_pro4.native_raminit
new file mode 100644
index 0000000000..2de538926f
--- /dev/null
+++ b/configs/config.asrock_b85m_pro4.native_raminit
@@ -0,0 +1,5 @@
+# Configuration used to build-test native raminit
+CONFIG_VENDOR_ASROCK=y
+CONFIG_BOARD_ASROCK_B85M_PRO4=y
+CONFIG_USE_NATIVE_RAMINIT=y
+CONFIG_DEBUG_RAM_SETUP=y
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
index 50acb09a91..b659bf6d98 100644
--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
@@ -9,6 +9,14 @@ config NORTHBRIDGE_INTEL_HASWELL
if NORTHBRIDGE_INTEL_HASWELL
+config USE_NATIVE_RAMINIT
+ bool "[NOT WORKING] Use native raminit"
+ default n
+ select HAVE_DEBUG_RAM_SETUP
+ help
+ Select if you want to use coreboot implementation of raminit rather than
+ MRC.bin. Currently incomplete and does not boot.
+
config HASWELL_VBOOT_IN_BOOTBLOCK
depends on VBOOT
bool "Start verstage in bootblock"
@@ -45,6 +53,7 @@ config DCACHE_RAM_BASE
config DCACHE_RAM_SIZE
hex
+ default 0x40000 if USE_NATIVE_RAMINIT
default 0x10000
help
The size of the cache-as-ram region required during bootblock
@@ -53,12 +62,14 @@ config DCACHE_RAM_SIZE
config DCACHE_RAM_MRC_VAR_SIZE
hex
+ default 0x0 if USE_NATIVE_RAMINIT
default 0x30000
help
The amount of cache-as-ram region required by the reference code.
config DCACHE_BSP_STACK_SIZE
hex
+ default 0x20000 if USE_NATIVE_RAMINIT
default 0x2000
help
The amount of anticipated stack usage in CAR by bootblock and
@@ -66,6 +77,7 @@ config DCACHE_BSP_STACK_SIZE
config HAVE_MRC
bool "Add a System Agent binary"
+ depends on !USE_NATIVE_RAMINIT
help
Select this option to add a System Agent binary to
the resulting coreboot image.
@@ -82,6 +94,7 @@ config MRC_FILE
config HASWELL_HIDE_PEG_FROM_MRC
bool "Hide PEG devices from MRC to work around hardcoded MRC behavior"
+ depends on !USE_NATIVE_RAMINIT
default y
help
If set, hides all PEG devices from MRC. This allows the iGPU
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 2d1532be05..329f1f7ffe 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -19,6 +19,11 @@ romstage-y += report_platform.c
postcar-y += memmap.c
-subdirs-y += haswell_mrc
+ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
+subdirs-y += native_raminit
+
+else
+subdirs-y += haswell_mrc
+endif
endif
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
new file mode 100644
index 0000000000..8cfb4fb33e
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
@@ -0,0 +1,3 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+romstage-y += raminit_native.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
new file mode 100644
index 0000000000..1aafdf8659
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <northbridge/intel/haswell/raminit.h>
+
+void perform_raminit(const int s3resume)
+{
+ /*
+ * See, this function's name is a lie. There are more things to
+ * do that memory initialisation, but they are relatively easy.
+ */
+
+ /** TODO: Implement the required magic **/
+ die("NATIVE RAMINIT: More Magic (tm) required.\n");
+}
--
2.39.2
config/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch
-615
View File
@@ -1,615 +0,0 @@
From 6ec71c6df97eded010e96c4ea2bd37cc6a13849d Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 6 May 2022 21:56:48 +0200
Subject: [PATCH 03/26] haswell/lynxpoint: Add native DMI init
Implement native DMI init for Haswell and Lynx Point. This is only
needed on non-ULT platforms, and only when MRC.bin is not used.
TEST=Verify DMI initialises correctly on Asrock B85M Pro4.
Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
src/northbridge/intel/haswell/Makefile.inc | 1 +
src/northbridge/intel/haswell/early_dmi.c | 96 ++++++++++++
src/northbridge/intel/haswell/early_pcie.c | 121 ++++++++++++++
src/northbridge/intel/haswell/haswell.h | 3 +
.../haswell/native_raminit/raminit_native.c | 15 ++
src/northbridge/intel/haswell/vcu_mailbox.c | 147 ++++++++++++++++++
src/northbridge/intel/haswell/vcu_mailbox.h | 16 ++
src/southbridge/intel/lynxpoint/Makefile.inc | 2 +
.../intel/lynxpoint/early_pch_native.c | 52 +++++++
src/southbridge/intel/lynxpoint/pch.h | 20 ++-
10 files changed, 472 insertions(+), 1 deletion(-)
create mode 100644 src/northbridge/intel/haswell/early_dmi.c
create mode 100644 src/northbridge/intel/haswell/early_pcie.c
create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.c
create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.h
create mode 100644 src/southbridge/intel/lynxpoint/early_pch_native.c
diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
index 329f1f7ffe..df0b097296 100644
--- a/src/northbridge/intel/haswell/Makefile.inc
+++ b/src/northbridge/intel/haswell/Makefile.inc
@@ -20,6 +20,7 @@ romstage-y += report_platform.c
postcar-y += memmap.c
ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
+romstage-y += early_dmi.c early_pcie.c vcu_mailbox.c
subdirs-y += native_raminit
else
diff --git a/src/northbridge/intel/haswell/early_dmi.c b/src/northbridge/intel/haswell/early_dmi.c
new file mode 100644
index 0000000000..9941242fd5
--- /dev/null
+++ b/src/northbridge/intel/haswell/early_dmi.c
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <types.h>
+
+static void dmi_print_link_status(int loglevel)
+{
+ const uint16_t dmilsts = dmibar_read16(DMILSTS);
+ printk(loglevel, "DMI: Running at Gen%u x%u\n", dmilsts & 0xf, dmilsts >> 4 & 0x1f);
+}
+
+#define RETRAIN (1 << 5)
+
+#define LTRN (1 << 11)
+
+static void dmi_setup_physical_layer(void)
+{
+ /* Program DMI AFE settings, which are needed for DMI to work */
+ peg_dmi_recipe(false, 0);
+
+ /* Additional DMI programming steps */
+ dmibar_setbits32(0x258, 1 << 29);
+ dmibar_clrsetbits32(0x208, 0x7ff, 0x6b5);
+ dmibar_clrsetbits32(0x22c, 0xffff, 0x2020);
+
+ /* Write SA reference code version */
+ dmibar_write32(0x71c, 0x0000000f);
+ dmibar_write32(0x720, 0x01060200);
+
+ /* We also have to bring up the PCH side of the DMI link */
+ pch_dmi_setup_physical_layer();
+
+ /* Write-once settings */
+ dmibar_clrsetbits32(DMILCAP, 0x3f00f, 2 << 0);
+
+ printk(BIOS_DEBUG, "Retraining DMI at Gen2 speeds...\n");
+ dmi_print_link_status(BIOS_DEBUG);
+
+ /* Retrain link */
+ dmibar_setbits16(DMILCTL, RETRAIN);
+ do {} while (dmibar_read16(DMILSTS) & LTRN);
+ dmi_print_link_status(BIOS_DEBUG);
+
+ /* Retrain link again for DMI Gen2 speeds */
+ dmibar_setbits16(DMILCTL, RETRAIN);
+ do {} while (dmibar_read16(DMILSTS) & LTRN);
+ dmi_print_link_status(BIOS_INFO);
+}
+
+#define VC_ACTIVE (1U << 31)
+
+#define VCNEGPND (1 << 1)
+
+#define DMI_VC_CFG(vcid, tcmap) (VC_ACTIVE | ((vcid) << 24) | (tcmap))
+
+static void dmi_tc_vc_mapping(void)
+{
+ printk(BIOS_DEBUG, "Programming SA DMI VC/TC mappings...\n");
+
+ if (CONFIG(INTEL_LYNXPOINT_LP))
+ dmibar_setbits8(0xa78, 1 << 1);
+
+ /* Each TC is mapped to one and only one VC */
+ const u32 vc0 = DMI_VC_CFG(0, (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 0));
+ const u32 vc1 = DMI_VC_CFG(1, (1 << 1));
+ const u32 vcp = DMI_VC_CFG(2, (1 << 2));
+ const u32 vcm = DMI_VC_CFG(7, (1 << 7));
+ dmibar_write32(DMIVC0RCTL, vc0);
+ dmibar_write32(DMIVC1RCTL, vc1);
+ dmibar_write32(DMIVCPRCTL, vcp);
+ dmibar_write32(DMIVCMRCTL, vcm);
+
+ /* Set Extended VC Count (EVCC) to 1 if VC1 is active */
+ dmibar_clrsetbits8(DMIPVCCAP1, 7, !!(vc1 & VC_ACTIVE));
+
+ /*
+ * We also have to program the PCH side of the DMI link. Since both ends
+ * must use the same Virtual Channel settings, we pass them as arguments.
+ */
+ pch_dmi_tc_vc_mapping(vc0, vc1, vcp, vcm);
+
+ printk(BIOS_DEBUG, "Waiting for SA DMI VC negotiation... ");
+ do {} while (dmibar_read16(DMIVC0RSTS) & VCNEGPND);
+ do {} while (dmibar_read16(DMIVC1RSTS) & VCNEGPND);
+ do {} while (dmibar_read16(DMIVCPRSTS) & VCNEGPND);
+ do {} while (dmibar_read16(DMIVCMRSTS) & VCNEGPND);
+ printk(BIOS_DEBUG, "done!\n");
+}
+
+void dmi_early_init(void)
+{
+ dmi_setup_physical_layer();
+ dmi_tc_vc_mapping();
+}
diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c
new file mode 100644
index 0000000000..d3940e3fac
--- /dev/null
+++ b/src/northbridge/intel/haswell/early_pcie.c
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <device/pci_def.h>
+#include <device/pci_mmio_cfg.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/vcu_mailbox.h>
+#include <types.h>
+
+#define PEG_DEV(func) PCI_DEV(0, 1, func)
+
+#define MAX_PEG_FUNC 3
+
+static void peg_dmi_unset_and_set_mask_pcicfg(
+ volatile union pci_bank *const bank,
+ const uint32_t offset,
+ const uint32_t unset_mask,
+ const uint32_t set_mask,
+ const uint32_t shift,
+ const bool valid)
+{
+ if (!valid)
+ return;
+
+ volatile uint32_t *const addr = &bank->reg32[offset / sizeof(uint32_t)];
+ clrsetbits32(addr, unset_mask << shift, set_mask << shift);
+}
+
+static void peg_dmi_unset_and_set_mask_common(
+ const bool is_peg,
+ const uint32_t offset,
+ const uint32_t unset,
+ const uint32_t set,
+ const uint32_t shift,
+ const bool valid)
+{
+ const uint32_t unset_mask = unset << shift;
+ const uint32_t set_mask = set << shift;
+ if (is_peg) {
+ for (uint8_t i = 0; i < MAX_PEG_FUNC; i++)
+ pci_update_config32(PEG_DEV(i), offset, ~unset_mask, set_mask);
+ } else {
+ dmibar_clrsetbits32(offset, unset_mask, set_mask);
+ }
+}
+
+static void peg_dmi_unset_and_set_mask_vcu_mmio(
+ const uint32_t addr,
+ const uint32_t unset_mask,
+ const uint32_t set_mask,
+ const uint32_t shift,
+ const bool valid)
+{
+ if (!valid)
+ return;
+
+ vcu_update_mmio(addr, ~(unset_mask << shift), set_mask << shift);
+}
+
+#define BUNDLE_STEP 0x20
+
+static void *const dmibar = (void *)(uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE;
+
+void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev)
+{
+ const bool always = true;
+ const bool is_dmi = !is_peg;
+
+ /* Treat DMIBAR and PEG devices the same way */
+ volatile union pci_bank *const bank = is_peg ? pci_map_bus(dev) : dmibar;
+
+ const size_t bundles = (is_peg ? 8 : 2) * BUNDLE_STEP;
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP) {
+ /* These are actually per-lane */
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa00 + i, 0x1f, 0x0c, 0, always);
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa10 + i, 0x1f, 0x0c, 0, always);
+ }
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x02, 0, is_peg);
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x03, 5, is_peg);
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x3f, 0x09, 5, always);
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x0f, 0x05, 21, is_peg);
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x08, 6, is_peg);
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x00, 10, always);
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x07, 0x00, 18, always);
+
+ peg_dmi_unset_and_set_mask_vcu_mmio(0x0c008001, 0x1f, 0x03, 25, is_peg);
+ peg_dmi_unset_and_set_mask_vcu_mmio(0x0c0c8001, 0x3f, 0x00, 23, is_dmi);
+
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0xc28, 0x1f, 0x13, 18, always);
+
+ peg_dmi_unset_and_set_mask_common(is_peg, 0xc38, 0x01, 0x00, 6, always);
+ peg_dmi_unset_and_set_mask_common(is_peg, 0x260, 0x03, 0x02, 0, always);
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x900 + i, 0x03, 0x00, 26, always);
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x03, 0x03, 10, always);
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x1f, 0x07, 25, is_peg);
+
+ for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
+ peg_dmi_unset_and_set_mask_pcicfg(bank, 0x91c + i, 0x07, 0x05, 27, is_peg);
+}
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 1b29f6baf0..30b4abd0a7 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -34,6 +34,9 @@ void haswell_early_initialization(void);
void haswell_late_initialization(void);
void haswell_unhide_peg(void);
+void dmi_early_init(void);
+void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev);
+
void report_platform_info(void);
struct acpi_rsdp;
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index 1aafdf8659..0938e026e3 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -1,7 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
+#include <types.h>
+
+static bool early_init_native(int s3resume)
+{
+ printk(BIOS_DEBUG, "Starting native platform initialisation\n");
+
+ if (!CONFIG(INTEL_LYNXPOINT_LP))
+ dmi_early_init();
+
+ return false;
+}
void perform_raminit(const int s3resume)
{
@@ -9,6 +21,9 @@ void perform_raminit(const int s3resume)
* See, this function's name is a lie. There are more things to
* do that memory initialisation, but they are relatively easy.
*/
+ const bool cpu_replaced = early_init_native(s3resume);
+
+ (void)cpu_replaced;
/** TODO: Implement the required magic **/
die("NATIVE RAMINIT: More Magic (tm) required.\n");
diff --git a/src/northbridge/intel/haswell/vcu_mailbox.c b/src/northbridge/intel/haswell/vcu_mailbox.c
new file mode 100644
index 0000000000..aead144023
--- /dev/null
+++ b/src/northbridge/intel/haswell/vcu_mailbox.c
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/vcu_mailbox.h>
+#include <stdint.h>
+
+/*
+ * This is a library for the VCU (Validation Control Unit) mailbox. This
+ * mailbox is primarily used to adjust some magic PCIe tuning parameters.
+ *
+ * There are two revisions of the VCU mailbox. Rev1 is specific to Haswell
+ * stepping A0, and all other steppings use Rev2. Haswell stepping A0 CPUs
+ * are early Engineering Samples with undocumented errata, and most likely
+ * need special microcode updates to boot. Thus, the code does not support
+ * VCU mailbox Rev1, because no one should need it anymore.
+ */
+
+#define VCU_MAILBOX_INTERFACE 0x6c00
+#define VCU_MAILBOX_DATA 0x6c04
+
+#define VCU_RUN_BUSY (1 << 31)
+
+enum vcu_opcode {
+ VCU_OPCODE_READ_VCU_API_VER_ID = 0x01,
+ VCU_OPCODE_OPEN_SEQ = 0x02,
+ VCU_OPCODE_CLOSE_SEQ = 0x03,
+ VCU_OPCODE_READ_DATA = 0x07,
+ VCU_OPCODE_WRITE_DATA = 0x08,
+ VCU_OPCODE_READ_CSR = 0x13,
+ VCU_OPCODE_WRITE_CSR = 0x14,
+ VCU_OPCODE_READ_MMIO = 0x15,
+ VCU_OPCODE_WRITE_MMIO = 0x16,
+};
+
+enum vcu_sequence {
+ SEQ_ID_READ_CSR = 0x1,
+ SEQ_ID_WRITE_CSR = 0x2,
+ SEQ_ID_READ_MMIO = 0x3,
+ SEQ_ID_WRITE_MMIO = 0x4,
+};
+
+#define VCU_RESPONSE_MASK 0xffff
+#define VCU_RESPONSE_SUCCESS 0x40
+#define VCU_RESPONSE_BUSY 0x80
+#define VCU_RESPONSE_THREAD_UNAVAILABLE 0x82
+#define VCU_RESPONSE_ILLEGAL 0x90
+
+/* FIXME: Use timer API */
+static void send_vcu_command(const enum vcu_opcode opcode, const uint32_t data)
+{
+ for (unsigned int i = 0; i < 10; i++) {
+ mchbar_write32(VCU_MAILBOX_DATA, data);
+ mchbar_write32(VCU_MAILBOX_INTERFACE, opcode | VCU_RUN_BUSY);
+ uint32_t vcu_interface;
+ for (unsigned int j = 0; j < 100; j++) {
+ vcu_interface = mchbar_read32(VCU_MAILBOX_INTERFACE);
+ if (!(vcu_interface & VCU_RUN_BUSY))
+ break;
+
+ udelay(10);
+ }
+ if (vcu_interface & VCU_RUN_BUSY)
+ continue;
+
+ if ((vcu_interface & VCU_RESPONSE_MASK) == VCU_RESPONSE_SUCCESS)
+ return;
+ }
+ printk(BIOS_ERR, "VCU: Failed to send command\n");
+}
+
+static enum vcu_opcode get_register_opcode(enum vcu_sequence seq)
+{
+ switch (seq) {
+ case SEQ_ID_READ_CSR:
+ return VCU_OPCODE_READ_CSR;
+ case SEQ_ID_WRITE_CSR:
+ return VCU_OPCODE_WRITE_CSR;
+ case SEQ_ID_READ_MMIO:
+ return VCU_OPCODE_READ_MMIO;
+ case SEQ_ID_WRITE_MMIO:
+ return VCU_OPCODE_WRITE_MMIO;
+ default:
+ return dead_code_t(enum vcu_opcode);
+ }
+}
+
+static enum vcu_opcode get_data_opcode(enum vcu_sequence seq)
+{
+ switch (seq) {
+ case SEQ_ID_READ_CSR:
+ case SEQ_ID_READ_MMIO:
+ return VCU_OPCODE_READ_DATA;
+ case SEQ_ID_WRITE_CSR:
+ case SEQ_ID_WRITE_MMIO:
+ return VCU_OPCODE_WRITE_DATA;
+ default:
+ return dead_code_t(enum vcu_opcode);
+ }
+}
+
+static uint32_t send_vcu_sequence(uint32_t addr, enum vcu_sequence seq, uint32_t wr_data)
+{
+ send_vcu_command(VCU_OPCODE_OPEN_SEQ, seq);
+
+ send_vcu_command(get_register_opcode(seq), addr);
+
+ send_vcu_command(get_data_opcode(seq), wr_data);
+
+ const uint32_t rd_data = mchbar_read32(VCU_MAILBOX_DATA);
+
+ send_vcu_command(VCU_OPCODE_CLOSE_SEQ, seq);
+
+ return rd_data;
+}
+
+uint32_t vcu_read_csr(uint32_t addr)
+{
+ return send_vcu_sequence(addr, SEQ_ID_READ_CSR, 0);
+}
+
+void vcu_write_csr(uint32_t addr, uint32_t data)
+{
+ send_vcu_sequence(addr, SEQ_ID_WRITE_CSR, data);
+}
+
+void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue)
+{
+ vcu_write_csr(addr, (vcu_read_csr(addr) & andvalue) | orvalue);
+}
+
+uint32_t vcu_read_mmio(uint32_t addr)
+{
+ return send_vcu_sequence(addr, SEQ_ID_READ_MMIO, 0);
+}
+
+void vcu_write_mmio(uint32_t addr, uint32_t data)
+{
+ send_vcu_sequence(addr, SEQ_ID_WRITE_MMIO, data);
+}
+
+void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue)
+{
+ vcu_write_mmio(addr, (vcu_read_mmio(addr) & andvalue) | orvalue);
+}
diff --git a/src/northbridge/intel/haswell/vcu_mailbox.h b/src/northbridge/intel/haswell/vcu_mailbox.h
new file mode 100644
index 0000000000..ba0a62e486
--- /dev/null
+++ b/src/northbridge/intel/haswell/vcu_mailbox.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef HASWELL_VCU_MAILBOX_H
+#define HASWELL_VCU_MAILBOX_H
+
+#include <stdint.h>
+
+uint32_t vcu_read_csr(uint32_t addr);
+void vcu_write_csr(uint32_t addr, uint32_t data);
+void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue);
+
+uint32_t vcu_read_mmio(uint32_t addr);
+void vcu_write_mmio(uint32_t addr, uint32_t data);
+void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue);
+
+#endif /* HASWELL_VCU_MAILBOX_H */
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 02022d348d..b8503ac8bc 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -37,6 +37,8 @@ bootblock-y += early_pch.c
romstage-y += early_usb.c early_me.c me_status.c early_pch.c
romstage-y += pmutil.c
+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c
+
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
romstage-y += lp_gpio.c
ramstage-y += lp_gpio.c
diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c
new file mode 100644
index 0000000000..c28ddfcf5d
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <device/pci_ops.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <types.h>
+
+void pch_dmi_setup_physical_layer(void)
+{
+ /* FIXME: We need to make sure the SA supports Gen2 as well */
+ if ((RCBA32(0x21a4) & 0x0f) == 0x02) {
+ /* Set Gen 2 Common Clock N_FTS */
+ RCBA32_AND_OR(0x2340, ~0x00ff0000, 0x3a << 16);
+
+ /* Set Target Link Speed to DMI Gen2 */
+ RCBA8_AND_OR(DLCTL2, ~0x07, 0x02);
+ }
+}
+
+#define VC_ACTIVE (1U << 31)
+
+#define VCNEGPND (1 << 1)
+
+void pch_dmi_tc_vc_mapping(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm)
+{
+ printk(BIOS_DEBUG, "Programming PCH DMI VC/TC mappings...\n");
+
+ RCBA32_AND_OR(CIR0050, ~(0xf << 20), 2 << 20);
+ if (vcp & VC_ACTIVE)
+ RCBA32_OR(CIR0050, 1 << 19 | 1 << 17);
+
+ RCBA32(CIR0050); /* Posted Write */
+
+ /* Use the same virtual channel mapping on both ends of the DMI link */
+ RCBA32(V0CTL) = vc0;
+ RCBA32(V1CTL) = vc1;
+ RCBA32(V1CTL); /* Posted Write */
+ RCBA32(VPCTL) = vcp;
+ RCBA32(VPCTL); /* Posted Write */
+ RCBA32(VMCTL) = vcm;
+
+ /* Lock the registers */
+ RCBA32_OR(CIR0050, 1U << 31);
+ RCBA32(CIR0050); /* Posted Write */
+
+ printk(BIOS_DEBUG, "Waiting for PCH DMI VC negotiation... ");
+ do {} while (RCBA16(V0STS) & VCNEGPND);
+ do {} while (RCBA16(V1STS) & VCNEGPND);
+ do {} while (RCBA16(VPSTS) & VCNEGPND);
+ do {} while (RCBA16(VMSTS) & VCNEGPND);
+ printk(BIOS_DEBUG, "done!\n");
+}
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 7d9fc6d6af..b5e0c2a830 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -113,6 +113,9 @@ enum pch_platform_type {
PCH_TYPE_ULT = 5,
};
+void pch_dmi_setup_physical_layer(void);
+void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
+
void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
void usb_ehci_disable(pci_devfn_t dev);
void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
@@ -406,9 +409,10 @@ void mainboard_config_rcba(void);
/* Southbridge IO BARs */
+#define PMBASE 0x40
#define GPIOBASE 0x48
-#define PMBASE 0x40
+#define CIR0050 0x0050 /* 32bit */
#define RPC 0x0400 /* 32bit */
#define RPFN 0x0404 /* 32bit */
@@ -431,6 +435,20 @@ void mainboard_config_rcba(void);
#define IOTR2 0x1e90 /* 64bit */
#define IOTR3 0x1e98 /* 64bit */
+#define V0CTL 0x2014 /* 32bit */
+#define V0STS 0x201a /* 16bit */
+
+#define V1CTL 0x2020 /* 32bit */
+#define V1STS 0x2026 /* 16bit */
+
+#define VPCTL 0x2030 /* 32bit */
+#define VPSTS 0x2038 /* 16bit */
+
+#define VMCTL 0x2040 /* 32bit */
+#define VMSTS 0x2048 /* 16bit */
+
+#define DLCTL2 0x21b0
+
#define TCTL 0x3000 /* 8bit */
#define NOINT 0
--
2.39.2
config/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch
-148
View File
@@ -1,148 +0,0 @@
From 98142e01fc8ebb3b762974e9e4de75e7f5c073b4 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 6 May 2022 22:18:21 +0200
Subject: [PATCH 04/26] haswell/lynxpoint: Add native early ME init
Implement native early ME init for Lynx Point. This is only needed when
MRC.bin is not used.
Change-Id: If416e2078f139f26b4742c564b70e018725bf003
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../haswell/native_raminit/raminit_native.c | 17 ++++++++++-
src/southbridge/intel/lynxpoint/early_me.c | 30 ++++++++++++++++++-
src/southbridge/intel/lynxpoint/me.h | 7 +++--
3 files changed, 50 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index 0938e026e3..6a002548c1 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -1,18 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <console/console.h>
+#include <delay.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/me.h>
#include <types.h>
static bool early_init_native(int s3resume)
{
printk(BIOS_DEBUG, "Starting native platform initialisation\n");
+ intel_early_me_init();
+ /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
+ const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
+
if (!CONFIG(INTEL_LYNXPOINT_LP))
dmi_early_init();
- return false;
+ return cpu_replaced;
}
void perform_raminit(const int s3resume)
@@ -25,6 +31,15 @@ void perform_raminit(const int s3resume)
(void)cpu_replaced;
+ /** TODO: Move after raminit */
+ if (intel_early_me_uma_size() > 0) {
+ /** TODO: Update status once raminit is implemented **/
+ uint8_t me_status = ME_INIT_STATUS_ERROR;
+ intel_early_me_init_done(me_status);
+ }
+
+ intel_early_me_status();
+
/** TODO: Implement the required magic **/
die("NATIVE RAMINIT: More Magic (tm) required.\n");
}
diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
index 947c570e16..07013c5539 100644
--- a/src/southbridge/intel/lynxpoint/early_me.c
+++ b/src/southbridge/intel/lynxpoint/early_me.c
@@ -1,11 +1,12 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/io.h>
+#include <cf9_reset.h>
#include <device/pci_ops.h>
#include <console/console.h>
#include <delay.h>
#include <halt.h>
-
+#include <timer.h>
#include "me.h"
#include "pch.h"
@@ -60,6 +61,33 @@ int intel_early_me_init(void)
return 0;
}
+bool intel_early_me_cpu_replacement_check(void)
+{
+ printk(BIOS_DEBUG, "ME: Checking whether CPU was replaced... ");
+
+ struct stopwatch timer;
+ stopwatch_init_msecs_expire(&timer, 50);
+
+ union me_hfs2 hfs2;
+ do {
+ hfs2.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2);
+ if (stopwatch_expired(&timer)) {
+ /* Assume CPU was replaced just in case */
+ printk(BIOS_DEBUG, "timed out, assuming CPU was replaced\n");
+ return true;
+ }
+ udelay(ME_DELAY);
+ } while (!hfs2.cpu_replaced_valid);
+
+ if (hfs2.warm_reset_request) {
+ printk(BIOS_DEBUG, "warm reset needed for dynamic fusing\n");
+ system_reset();
+ }
+
+ printk(BIOS_DEBUG, "%sreplaced\n", hfs2.cpu_replaced_sts ? "" : "not ");
+ return hfs2.cpu_replaced_sts;
+}
+
int intel_early_me_uma_size(void)
{
union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) };
diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h
index fe8b0260c4..6990322651 100644
--- a/src/southbridge/intel/lynxpoint/me.h
+++ b/src/southbridge/intel/lynxpoint/me.h
@@ -177,14 +177,16 @@ union me_did {
union me_hfs2 {
struct __packed {
u32 bist_in_progress: 1;
- u32 reserved1: 2;
+ u32 icc_prog_sts: 2;
u32 invoke_mebx: 1;
u32 cpu_replaced_sts: 1;
u32 mbp_rdy: 1;
u32 mfs_failure: 1;
u32 warm_reset_request: 1;
u32 cpu_replaced_valid: 1;
- u32 reserved2: 4;
+ u32 reserved: 2;
+ u32 fw_upd_ipu: 1;
+ u32 reserved2: 1;
u32 mbp_cleared: 1;
u32 reserved3: 2;
u32 current_state: 8;
@@ -338,6 +340,7 @@ void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2);
void intel_early_me_status(void);
int intel_early_me_init(void);
+bool intel_early_me_cpu_replacement_check(void);
int intel_early_me_uma_size(void);
int intel_early_me_init_done(u8 status);
--
2.39.2
config/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch
-783
View File
@@ -1,783 +0,0 @@
From 9bfb8614dbf1d9800ef8251cb3d839bcdbe5577f Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 6 May 2022 23:17:39 +0200
Subject: [PATCH 05/26] sb/intel/lynxpoint: Add native USB init
Implement native USB initialisation for Lynx Point. This is only needed
when MRC.bin is not used.
TO DO: Figure out how to deal with the FIXME's and TODO's lying around.
Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../haswell/native_raminit/raminit_native.c | 3 +
src/southbridge/intel/lynxpoint/Makefile.inc | 2 +-
src/southbridge/intel/lynxpoint/early_usb.c | 11 -
.../intel/lynxpoint/early_usb_native.c | 584 ++++++++++++++++++
src/southbridge/intel/lynxpoint/pch.h | 49 ++
5 files changed, 637 insertions(+), 12 deletions(-)
create mode 100644 src/southbridge/intel/lynxpoint/early_usb_native.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index 6a002548c1..ef61d4ee09 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -5,6 +5,7 @@
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/me.h>
+#include <southbridge/intel/lynxpoint/pch.h>
#include <types.h>
static bool early_init_native(int s3resume)
@@ -15,6 +16,8 @@ static bool early_init_native(int s3resume)
/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
+ early_usb_init();
+
if (!CONFIG(INTEL_LYNXPOINT_LP))
dmi_early_init();
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index b8503ac8bc..0e1f2fe4eb 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -37,7 +37,7 @@ bootblock-y += early_pch.c
romstage-y += early_usb.c early_me.c me_status.c early_pch.c
romstage-y += pmutil.c
-romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c
+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
romstage-y += lp_gpio.c
diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
index a753681ce0..52e8ac17f8 100644
--- a/src/southbridge/intel/lynxpoint/early_usb.c
+++ b/src/southbridge/intel/lynxpoint/early_usb.c
@@ -4,17 +4,6 @@
#include <device/pci_def.h>
#include "pch.h"
-/* HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index
- * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
- */
-#if CONFIG_USBDEBUG_HCD_INDEX != 2
-#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
-#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
-#else
-#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
-#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
-#endif
-
/*
* Setup USB controller MMIO BAR to prevent the
* reference code from resetting the controller.
diff --git a/src/southbridge/intel/lynxpoint/early_usb_native.c b/src/southbridge/intel/lynxpoint/early_usb_native.c
new file mode 100644
index 0000000000..cb6f6ee8e6
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/early_usb_native.c
@@ -0,0 +1,584 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/mmio.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <southbridge/intel/lynxpoint/iobp.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <timer.h>
+#include <types.h>
+
+static unsigned int is_usbr_enabled(void)
+{
+ return !!(pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) & BIT(5));
+}
+
+static char *const xhci_bar = (char *)PCH_XHCI_TEMP_BAR0;
+
+static void ehci_hcs_init(const pci_devfn_t dev, const uintptr_t ehci_bar)
+{
+ pci_write_config32(dev, PCI_BASE_ADDRESS_0, ehci_bar);
+
+ /** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/
+ pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+
+ char *const mem_bar = (char *)ehci_bar;
+
+ /**
+ * Shared EHCI/XHCI ports w/a.
+ * This step is required when some of the ports are routed to EHCI
+ * and other ports are routed XHCI at the same time.
+ *
+ * FIXME: Under which conditions should this be done?
+ */
+ pci_and_config16(dev, 0x78, ~0x03);
+
+ /* Skip reset if usbdebug is enabled */
+ if (!CONFIG(USBDEBUG_IN_PRE_RAM))
+ setbits32(mem_bar + EHCI_USB_CMD, EHCI_USB_CMD_HCRESET);
+
+ /* 2: Configure number of controllers and ports */
+ pci_or_config16(dev, EHCI_ACCESS_CNTL, ACCESS_CNTL_ENABLE);
+ clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf << 12, 0);
+ clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf << 0, 2 + is_usbr_enabled());
+ pci_and_config16(dev, EHCI_ACCESS_CNTL, ~ACCESS_CNTL_ENABLE);
+
+ pci_or_config16(dev, 0x78, BIT(2));
+ pci_or_config16(dev, 0x7c, BIT(14) | BIT(7));
+ pci_update_config32(dev, 0x8c, ~(0xf << 8), (4 << 8));
+ pci_update_config32(dev, 0x8c, ~BIT(26), BIT(17));
+}
+
+static inline unsigned int physical_port_count(void)
+{
+ return MAX_USB2_PORTS;
+}
+
+static unsigned int hs_port_count(void)
+{
+ /** TODO: Apparently, WPT-LP has 10 USB2 ports **/
+ if (CONFIG(INTEL_LYNXPOINT_LP))
+ return 8;
+
+ switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 1) & 3) {
+ case 3:
+ return 8;
+ case 2:
+ return 10;
+ case 1:
+ return 12;
+ case 0:
+ default:
+ return 14;
+ }
+}
+
+static unsigned int ss_port_count(void)
+{
+ if (CONFIG(INTEL_LYNXPOINT_LP))
+ return 4;
+
+ switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 3) & 3) {
+ case 3:
+ return 0;
+ case 2:
+ return 2;
+ case 1:
+ return 4;
+ case 0:
+ default:
+ return 6;
+ }
+}
+
+static void common_ehci_hcs_init(void)
+{
+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
+
+ ehci_hcs_init(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0);
+ if (!is_lp)
+ ehci_hcs_init(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0);
+
+ pch_iobp_update(0xe5007f04, 0, 0x00004481);
+
+ for (unsigned int port = 0; port < physical_port_count(); port++)
+ pch_iobp_update(0xe500400f + port * 0x100, ~(1 << 0), 0 << 0);
+
+ pch_iobp_update(0xe5007f14, ~(3 << 19), (3 << 19));
+
+ if (is_lp)
+ pch_iobp_update(0xe5007f02, ~(3 << 22), (0 << 22));
+}
+
+static void xhci_open_memory_space(void)
+{
+ /** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/
+ pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, (uintptr_t)xhci_bar);
+ pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
+}
+
+static void xhci_close_memory_space(void)
+{
+ pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
+ pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, 0);
+}
+
+static void common_xhci_hc_init(void)
+{
+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
+
+ if (!is_lp) {
+ const unsigned int max_ports = 15 + ss_port_count();
+ clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_1, 0xf << 28, max_ports << 28);
+ }
+
+ clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_3, 0xffff << 16 | 0xff, 0x200 << 16 | 0x0a);
+ clrsetbits32(xhci_bar + XHCI_HCC_PARAMS, BIT(5), BIT(10) | BIT(9));
+
+ if (!is_lp)
+ clrsetbits32(xhci_bar + 0x8008, BIT(19), 0);
+
+ if (is_lp)
+ clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16));
+ else
+ clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16) | BIT(20));
+
+ clrsetbits32(xhci_bar + 0x8060, 0, BIT(25) | BIT(18));
+ clrsetbits32(xhci_bar + 0x8090, 0, BIT(14) | BIT(8));
+ clrsetbits32(xhci_bar + 0x8094, 0, BIT(23) | BIT(21) | BIT(14));
+ clrsetbits32(xhci_bar + 0x80e0, BIT(16), BIT(6));
+ clrsetbits32(xhci_bar + 0x80ec, (7 << 12) | (7 << 9), (0 << 12) | (6 << 9));
+ clrsetbits32(xhci_bar + 0x80f0, BIT(20), 0);
+
+ if (is_lp)
+ clrsetbits32(xhci_bar + 0x80fc, 0, BIT(25));
+
+ if (is_lp)
+ clrsetbits32(xhci_bar + 0x8110, BIT(8) | BIT(2), BIT(20) | BIT(11));
+ else
+ clrsetbits32(xhci_bar + 0x8110, BIT(2), BIT(20) | BIT(11));
+
+ if (is_lp)
+ write32(xhci_bar + 0x8140, 0xff00f03c);
+ else
+ write32(xhci_bar + 0x8140, 0xff03c132);
+
+ if (is_lp)
+ clrsetbits32(xhci_bar + 0x8154, BIT(21), BIT(13));
+ else
+ clrsetbits32(xhci_bar + 0x8154, BIT(21) | BIT(13), 0);
+
+ clrsetbits32(xhci_bar + 0x8154, BIT(3), 0);
+
+ if (is_lp) {
+ clrsetbits32(xhci_bar + 0x8164, 0, BIT(1) | BIT(0));
+ write32(xhci_bar + 0x8174, 0x01400c0a);
+ write32(xhci_bar + 0x817c, 0x033200a3);
+ write32(xhci_bar + 0x8180, 0x00cb0028);
+ write32(xhci_bar + 0x8184, 0x0064001e);
+ }
+
+ /*
+ * Note: Register at offset 0x44 is 32-bit, but bit 31 is write-once.
+ * We use these weird partial accesses here to avoid locking bit 31.
+ */
+ pci_or_config16(PCH_XHCI_DEV, 0x44, BIT(15) | BIT(14) | BIT(10) | BIT(0));
+ pci_or_config8(PCH_XHCI_DEV, 0x44 + 2, 0x0f);
+
+ /* LPT-LP >= B0 */
+ if (is_lp)
+ clrsetbits32(xhci_bar + 0x8188, 0, BIT(26) | BIT(24));
+
+ /* LPT-H >= C0 */
+ if (!is_lp)
+ clrsetbits32(xhci_bar + 0x8188, 0, BIT(24));
+}
+
+static inline bool is_mem_sr(void)
+{
+ return pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2) & GEN_PMCON_2_MEM_SR;
+}
+
+static bool should_restore_xhci_smart_auto(void)
+{
+ if (!is_mem_sr())
+ return false;
+
+ return pci_read_config32(PCH_LPC_DEV, PMIR) & PMIR_XHCI_SMART_AUTO;
+}
+
+enum usb_port_route {
+ ROUTE_TO_EHCI,
+ ROUTE_TO_XHCI,
+};
+
+/* Returns whether port reset was successful */
+static bool reset_usb2_ports(const unsigned int ehci_ports)
+{
+ for (unsigned int port = 0; port < ehci_ports; port++) {
+ /* Initiate port reset for all USB2 ports */
+ clrsetbits32(
+ xhci_bar + XHCI_USB2_PORTSC(port),
+ XHCI_USB2_PORTSC_PED,
+ XHCI_USB2_PORTSC_PR);
+ }
+ /* Poll for port reset bit to be cleared or time out at 100ms */
+ struct stopwatch timer;
+ stopwatch_init_msecs_expire(&timer, 100);
+ uint32_t reg32;
+ do {
+ reg32 = 0;
+ for (unsigned int port = 0; port < ehci_ports; port++)
+ reg32 |= read32(xhci_bar + XHCI_USB2_PORTSC(port));
+
+ reg32 &= XHCI_USB2_PORTSC_PR;
+ if (!reg32) {
+ const long elapsed_time = stopwatch_duration_usecs(&timer);
+ printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time);
+ return true;
+ }
+ /* Reference code has a 10 ms delay here, but a smaller delay works too */
+ udelay(100);
+ } while (!stopwatch_expired(&timer));
+ printk(BIOS_ERR, "%s: timed out\n", __func__);
+ return !reg32;
+}
+
+/* Returns whether warm reset was successful */
+static bool warm_reset_usb3_ports(const unsigned int xhci_ports)
+{
+ for (unsigned int port = 0; port < xhci_ports; port++) {
+ /* Initiate warm reset for all USB3 ports */
+ clrsetbits32(
+ xhci_bar + XHCI_USB3_PORTSC(port),
+ XHCI_USB3_PORTSC_PED,
+ XHCI_USB3_PORTSC_WPR);
+ }
+ /* Poll for port reset bit to be cleared or time out at 100ms */
+ struct stopwatch timer;
+ stopwatch_init_msecs_expire(&timer, 100);
+ uint32_t reg32;
+ do {
+ reg32 = 0;
+ for (unsigned int port = 0; port < xhci_ports; port++)
+ reg32 |= read32(xhci_bar + XHCI_USB3_PORTSC(port));
+
+ reg32 &= XHCI_USB3_PORTSC_PR;
+ if (!reg32) {
+ const long elapsed_time = stopwatch_duration_usecs(&timer);
+ printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time);
+ return true;
+ }
+ /* Reference code has a 10 ms delay here, but a smaller delay works too */
+ udelay(100);
+ } while (!stopwatch_expired(&timer));
+ printk(BIOS_ERR, "%s: timed out\n", __func__);
+ return !reg32;
+}
+
+static void perform_xhci_ehci_switching_flow(const enum usb_port_route usb_route)
+{
+ const pci_devfn_t dev = PCH_XHCI_DEV;
+
+ const unsigned int ehci_ports = hs_port_count() + is_usbr_enabled();
+ const unsigned int xhci_ports = ss_port_count();
+
+ const uint32_t ehci_mask = BIT(ehci_ports) - 1;
+ const uint32_t xhci_mask = BIT(xhci_ports) - 1;
+
+ /** TODO: Handle USBr port? How, though? **/
+ pci_update_config32(dev, XHCI_USB2PRM, ~XHCI_USB2PR_HCSEL, ehci_mask);
+ pci_update_config32(dev, XHCI_USB3PRM, ~XHCI_USB3PR_SSEN, xhci_mask);
+
+ /*
+ * Workaround for USB2PR / USB3PR value not surviving warm reset.
+ * Restore USB Port Routing registers if OS HC Switch driver has been executed.
+ */
+ if (should_restore_xhci_smart_auto()) {
+ /** FIXME: Derive values from mainboard code instead? **/
+ pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_mask);
+ pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN, xhci_mask);
+ }
+
+ /* Later stages shouldn't need the value of this bit */
+ pci_and_config32(PCH_LPC_DEV, PMIR, ~PMIR_XHCI_SMART_AUTO);
+
+ /**
+ * FIXME: Things here depend on the chosen routing mode.
+ * For now, implement both functions.
+ */
+
+ /* Route to EHCI if xHCI disabled or auto mode */
+ if (usb_route == ROUTE_TO_EHCI) {
+ if (!reset_usb2_ports(ehci_ports))
+ printk(BIOS_ERR, "USB2 port reset timed out\n");
+
+ pci_and_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL);
+
+ for (unsigned int port = 0; port < ehci_ports; port++) {
+ clrsetbits32(
+ xhci_bar + XHCI_USB2_PORTSC(port),
+ XHCI_USB2_PORTSC_PED,
+ XHCI_USB2_PORTSC_CHST);
+ }
+
+ if (!warm_reset_usb3_ports(xhci_ports))
+ printk(BIOS_ERR, "USB3 warm reset timed out\n");
+
+ /* FIXME: BWG says this should be inside the warm reset function */
+ pci_and_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN);
+
+ for (unsigned int port = 0; port < ehci_ports; port++) {
+ clrsetbits32(
+ xhci_bar + XHCI_USB3_PORTSC(port),
+ XHCI_USB3_PORTSC_PED,
+ XHCI_USB3_PORTSC_CHST);
+ }
+
+ setbits32(xhci_bar + XHCI_USBCMD, BIT(0));
+ clrbits32(xhci_bar + XHCI_USBCMD, BIT(0));
+ }
+
+ /* Route to xHCI if xHCI enabled */
+ if (usb_route == ROUTE_TO_XHCI) {
+ if (is_mem_sr()) {
+ if (!warm_reset_usb3_ports(xhci_ports))
+ printk(BIOS_ERR, "USB3 warm reset timed out\n");
+ }
+
+ const uint32_t xhci_port_mask = pci_read_config32(dev, XHCI_USB3PRM) & 0x3f;
+ pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN, xhci_port_mask);
+
+ const uint32_t ehci_port_mask = pci_read_config32(dev, XHCI_USB2PRM) & 0x7fff;
+ pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_port_mask);
+ }
+}
+
+/* Do not shift in this macro, as it can cause undefined behaviour for bad port/oc values */
+#define PORT_TO_OC_SHIFT(port, oc) ((oc) * 8 + (port))
+
+/* Avoid shifting into undefined behaviour */
+static inline bool shift_ok(const int shift)
+{
+ return shift >= 0 && shift < 32;
+}
+
+static void usb_overcurrent_mapping(void)
+{
+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
+
+ uint32_t ehci_1_ocmap = 0;
+ uint32_t ehci_2_ocmap = 0;
+ uint32_t xhci_1_ocmap = 0;
+ uint32_t xhci_2_ocmap = 0;
+
+ /*
+ * EHCI
+ */
+ for (unsigned int idx = 0; idx < physical_port_count(); idx++) {
+ const struct usb2_port_config *const port = &mainboard_usb2_ports[idx];
+ printk(BIOS_DEBUG, "USB2 port %u => ", idx);
+ if (!port->enable) {
+ printk(BIOS_DEBUG, "disabled\n");
+ continue;
+ }
+ const unsigned short oc_pin = port->oc_pin;
+ if (oc_pin == USB_OC_PIN_SKIP) {
+ printk(BIOS_DEBUG, "not mapped to OC pin\n");
+ continue;
+ }
+ /* Ports 0 .. 7 => OC 0 .. 3 */
+ if (idx < 8 && oc_pin <= 3) {
+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin);
+ if (shift_ok(shift)) {
+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
+ ehci_1_ocmap |= 1 << shift;
+ continue;
+ }
+ }
+ /* Ports 8 .. 13 => OC 4 .. 7 (LPT-H only) */
+ if (!is_lp && idx >= 8 && oc_pin >= 4) {
+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4);
+ if (shift_ok(shift)) {
+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
+ ehci_2_ocmap |= 1 << shift;
+ continue;
+ }
+ }
+ printk(BIOS_ERR, "Invalid OC pin %u for USB2 port %u\n", oc_pin, idx);
+ }
+ printk(BIOS_DEBUG, "\n");
+ pci_write_config32(PCH_EHCI1_DEV, EHCI_OCMAP, ehci_1_ocmap);
+ if (!is_lp)
+ pci_write_config32(PCH_EHCI2_DEV, EHCI_OCMAP, ehci_2_ocmap);
+
+ /*
+ * xHCI
+ */
+ for (unsigned int idx = 0; idx < ss_port_count(); idx++) {
+ const struct usb3_port_config *const port = &mainboard_usb3_ports[idx];
+ printk(BIOS_DEBUG, "USB3 port %u => ", idx);
+ if (!port->enable) {
+ printk(BIOS_DEBUG, "disabled\n");
+ continue;
+ }
+ const unsigned short oc_pin = port->oc_pin;
+ if (oc_pin == USB_OC_PIN_SKIP) {
+ printk(BIOS_DEBUG, "not mapped to OC pin\n");
+ continue;
+ }
+ /* Ports 0 .. 5 => OC 0 .. 3 */
+ if (oc_pin <= 3) {
+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin);
+ if (shift_ok(shift)) {
+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
+ xhci_1_ocmap |= 1 << shift;
+ continue;
+ }
+ }
+ /* Ports 0 .. 5 => OC 4 .. 7 (LPT-H only) */
+ if (!is_lp && oc_pin >= 4) {
+ const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4);
+ if (shift_ok(shift)) {
+ printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
+ xhci_2_ocmap |= 1 << shift;
+ continue;
+ }
+ }
+ printk(BIOS_ERR, "Invalid OC pin %u for USB3 port %u\n", oc_pin, idx);
+ }
+ printk(BIOS_DEBUG, "\n");
+ pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM1, ehci_1_ocmap);
+ pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM1, xhci_1_ocmap);
+ if (!is_lp) {
+ pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM2, ehci_2_ocmap);
+ pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM2, xhci_2_ocmap);
+ }
+}
+
+static uint8_t get_ehci_tune_param_1(const struct usb2_port_config *const port)
+{
+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
+
+ const enum pch_platform_type plat_type = get_pch_platform_type();
+ const enum usb2_port_location location = port->location;
+ const uint16_t length = port->length;
+ if (!is_lp) {
+ if (plat_type == PCH_TYPE_DESKTOP) {
+ if (location == USB_PORT_BACK_PANEL)
+ return 4; /* Back Panel */
+ else
+ return 3; /* Front Panel */
+
+ } else if (plat_type == PCH_TYPE_MOBILE) {
+ if (location == USB_PORT_INTERNAL)
+ return 5; /* Internal Topology */
+ else if (location == USB_PORT_DOCK)
+ return 4; /* Dock */
+ else if (length < 0x70)
+ return 5; /* Back Panel, less than 7" */
+ else
+ return 6; /* Back Panel, 7" or more */
+ }
+ } else {
+ if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) {
+ if (length < 0x70)
+ return 5; /* Back Panel, less than 7" */
+ else
+ return 6; /* Back Panel, 7" or more */
+ } else if (location == USB_PORT_DOCK) {
+ return 4; /* Dock */
+ } else {
+ return 5; /* Internal Topology */
+ }
+ }
+ printk(BIOS_ERR, "%s: Unhandled case\n", __func__);
+ return 0;
+}
+
+static uint8_t get_ehci_tune_param_2(const struct usb2_port_config *const port)
+{
+ const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
+
+ const enum pch_platform_type plat_type = get_pch_platform_type();
+ const enum usb2_port_location location = port->location;
+ const uint16_t length = port->length;
+ if (!is_lp) {
+ if (plat_type == PCH_TYPE_DESKTOP) {
+ if (location == USB_PORT_BACK_PANEL) {
+ if (length < 0x80)
+ return 2; /* Back Panel, less than 8" */
+ else if (length < 0x130)
+ return 3; /* Back Panel, 8"-13" */
+ else
+ return 4; /* Back Panel, 13" or more */
+ } else {
+ return 2; /* Front Panel */
+ }
+
+ } else if (plat_type == PCH_TYPE_MOBILE) {
+ if (location == USB_PORT_INTERNAL) {
+ return 2; /* Internal Topology */
+ } else if (location == USB_PORT_DOCK) {
+ if (length < 0x50)
+ return 1; /* Dock, less than 5" */
+ else
+ return 2; /* Dock, 5" or more */
+ } else {
+ if (length < 0x100)
+ return 2; /* Back Panel, less than 10" */
+ else
+ return 3; /* Back Panel, 10" or more */
+ }
+ }
+ } else {
+ if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) {
+ if (length < 0x100)
+ return 2; /* Back Panel, less than 10" */
+ else
+ return 3; /* Back Panel, 10" or more */
+ } else if (location == USB_PORT_DOCK) {
+ if (length < 0x50)
+ return 1; /* Dock, less than 5" */
+ else
+ return 2; /* Dock, 5" or more */
+ } else {
+ return 2; /* Internal Topology */
+ }
+ }
+ printk(BIOS_ERR, "%s: Unhandled case\n", __func__);
+ return 0;
+}
+
+static void program_ehci_port_length(void)
+{
+ for (unsigned int port = 0; port < physical_port_count(); port++) {
+ if (!mainboard_usb2_ports[port].enable)
+ continue;
+ const uint32_t addr = 0xe5004000 + (port + 1) * 0x100;
+ const uint8_t param_1 = get_ehci_tune_param_1(&mainboard_usb2_ports[port]);
+ const uint8_t param_2 = get_ehci_tune_param_2(&mainboard_usb2_ports[port]);
+ pch_iobp_update(addr, ~0x7f00, param_2 << 11 | param_1 << 8);
+ }
+}
+
+void early_usb_init(void)
+{
+ /** TODO: Make this configurable? How do the modes affect usbdebug? **/
+ const enum usb_port_route usb_route = ROUTE_TO_XHCI;
+ ///(pd->boot_mode == 2 && pd->usb_xhci_on_resume) ? ROUTE_TO_XHCI : ROUTE_TO_EHCI;
+
+ common_ehci_hcs_init();
+ xhci_open_memory_space();
+ common_xhci_hc_init();
+ perform_xhci_ehci_switching_flow(usb_route);
+ usb_overcurrent_mapping();
+ program_ehci_port_length();
+ /** FIXME: USB per port control is missing, is it needed? **/
+ xhci_close_memory_space();
+ /** TODO: Close EHCI memory space? **/
+}
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index b5e0c2a830..ad983d86cf 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -115,6 +115,7 @@ enum pch_platform_type {
void pch_dmi_setup_physical_layer(void);
void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
+void early_usb_init(void);
void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
void usb_ehci_disable(pci_devfn_t dev);
@@ -202,6 +203,8 @@ void mainboard_config_rcba(void);
#define GEN_PMCON_1 0xa0
#define SMI_LOCK (1 << 4)
#define GEN_PMCON_2 0xa2
+#define GEN_PMCON_2_DISB (1 << 7)
+#define GEN_PMCON_2_MEM_SR (1 << 5)
#define SYSTEM_RESET_STS (1 << 4)
#define THERMTRIP_STS (1 << 3)
#define SYSPWR_FLR (1 << 1)
@@ -215,6 +218,7 @@ void mainboard_config_rcba(void);
#define PMIR 0xac
#define PMIR_CF9LOCK (1 << 31)
#define PMIR_CF9GR (1 << 20)
+#define PMIR_XHCI_SMART_AUTO (1 << 16) /* c.f. LPT BWG or WPT-LP BIOS spec */
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)
@@ -282,6 +286,20 @@ void mainboard_config_rcba(void);
#define SATA_DTLE_DATA_SHIFT 24
#define SATA_DTLE_EDGE_SHIFT 16
+/*
+ * HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index
+ * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
+ */
+#if CONFIG_USBDEBUG_HCD_INDEX != 2
+#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
+#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
+#else
+#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
+#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
+#endif
+
+#define PCH_XHCI_TEMP_BAR0 0xe8100000
+
/* EHCI PCI Registers */
#define EHCI_PWR_CTL_STS 0x54
#define PWR_CTL_SET_MASK 0x3
@@ -289,10 +307,15 @@ void mainboard_config_rcba(void);
#define PWR_CTL_SET_D3 0x3
#define PWR_CTL_ENABLE_PME (1 << 8)
#define PWR_CTL_STATUS_PME (1 << 15)
+#define EHCI_OCMAP 0x74
+#define EHCI_ACCESS_CNTL 0x80
+#define ACCESS_CNTL_ENABLE (1 << 0)
/* EHCI Memory Registers */
+#define EHCI_HCS_PARAMS 0x04
#define EHCI_USB_CMD 0x20
#define EHCI_USB_CMD_RUN (1 << 0)
+#define EHCI_USB_CMD_HCRESET (1 << 1)
#define EHCI_USB_CMD_PSE (1 << 4)
#define EHCI_USB_CMD_ASE (1 << 5)
#define EHCI_PORTSC(port) (0x64 + (port) * 4)
@@ -301,6 +324,10 @@ void mainboard_config_rcba(void);
/* XHCI PCI Registers */
#define XHCI_PWR_CTL_STS 0x74
+#define XHCI_U2OCM1 0xc0
+#define XHCI_U2OCM2 0xc4
+#define XHCI_U3OCM1 0xc8
+#define XHCI_U3OCM2 0xcc
#define XHCI_USB2PR 0xd0
#define XHCI_USB2PRM 0xd4
#define XHCI_USB2PR_HCSEL 0x7fff
@@ -313,6 +340,27 @@ void mainboard_config_rcba(void);
#define XHCI_USB3PDO 0xe8
/* XHCI Memory Registers */
+#define XHCI_HCS_PARAMS_1 0x04
+#define XHCI_HCS_PARAMS_2 0x08
+#define XHCI_HCS_PARAMS_3 0x0c
+#define XHCI_HCC_PARAMS 0x10
+#define XHCI_USBCMD 0x80
+#define XHCI_USB2_PORTSC(port) (0x480 + ((port) * 0x10))
+#define XHCI_USB2_PORTSC_WPR (1 << 31) /* Warm Port Reset */
+#define XHCI_USB2_PORTSC_CEC (1 << 23) /* Port Config Error Change */
+#define XHCI_USB2_PORTSC_PLC (1 << 22) /* Port Link State Change */
+#define XHCI_USB2_PORTSC_PRC (1 << 21) /* Port Reset Change */
+#define XHCI_USB2_PORTSC_OCC (1 << 20) /* Over-current Change */
+#define XHCI_USB2_PORTSC_WRC (1 << 19) /* Warm Port Reset Change */
+#define XHCI_USB2_PORTSC_PEC (1 << 18) /* Port Enabled Disabled Change */
+#define XHCI_USB2_PORTSC_CSC (1 << 17) /* Connect Status Change */
+#define XHCI_USB2_PORTSC_CHST (0x7f << 17)
+#define XHCI_USB2_PORTSC_LWS (1 << 16) /* Port Link State Write Strobe */
+#define XHCI_USB2_PORTSC_PP (1 << 9)
+#define XHCI_USB2_PORTSC_PR (1 << 4) /* Port Reset */
+#define XHCI_USB2_PORTSC_PED (1 << 1) /* Port Enable/Disabled */
+#define XHCI_USB2_PORTSC_CCS (1 << 0) /* Current Connect Status */
+
#define XHCI_USB3_PORTSC(port) ((pch_is_lp() ? 0x510 : 0x570) + ((port) * 0x10))
#define XHCI_USB3_PORTSC_CHST (0x7f << 17)
#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */
@@ -320,6 +368,7 @@ void mainboard_config_rcba(void);
#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */
#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */
#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */
+#define XHCI_USB3_PORTSC_PR (1 << 4) /* Port Reset */
#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */
#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */
#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */
--
2.39.2
config/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch
-128
View File
@@ -1,128 +0,0 @@
From 92be49d8422b4bc1c89bb49535f4dc6a01d47295 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 6 May 2022 23:22:11 +0200
Subject: [PATCH 06/26] sb/intel/lynxpoint: Add native thermal init
Implement native thermal initialisation for Lynx Point. This is only
needed when MRC.bin is not used.
Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../haswell/native_raminit/raminit_native.c | 1 +
src/southbridge/intel/lynxpoint/Makefile.inc | 2 +-
src/southbridge/intel/lynxpoint/pch.h | 1 +
src/southbridge/intel/lynxpoint/thermal.c | 64 +++++++++++++++++++
4 files changed, 67 insertions(+), 1 deletion(-)
create mode 100644 src/southbridge/intel/lynxpoint/thermal.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index ef61d4ee09..dd1f1ec14e 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -16,6 +16,7 @@ static bool early_init_native(int s3resume)
/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
+ early_thermal_init();
early_usb_init();
if (!CONFIG(INTEL_LYNXPOINT_LP))
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index 0e1f2fe4eb..a9a9b153d6 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -37,7 +37,7 @@ bootblock-y += early_pch.c
romstage-y += early_usb.c early_me.c me_status.c early_pch.c
romstage-y += pmutil.c
-romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c
+romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
romstage-y += lp_gpio.c
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index ad983d86cf..38a9349220 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -116,6 +116,7 @@ enum pch_platform_type {
void pch_dmi_setup_physical_layer(void);
void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
void early_usb_init(void);
+void early_thermal_init(void);
void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
void usb_ehci_disable(pci_devfn_t dev);
diff --git a/src/southbridge/intel/lynxpoint/thermal.c b/src/southbridge/intel/lynxpoint/thermal.c
new file mode 100644
index 0000000000..e71969ea0c
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/thermal.c
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/mmio.h>
+#include <device/pci_ops.h>
+#include <southbridge/intel/lynxpoint/pch.h>
+#include <types.h>
+
+#define TBARB_TEMP 0x40000000
+
+#define THERMAL_DEV PCI_DEV(0, 0x1f, 6)
+
+/* Early thermal init, it may need to be done prior to giving ME its memory */
+void early_thermal_init(void)
+{
+ /* Program address for temporary BAR */
+ pci_write_config32(THERMAL_DEV, 0x40, TBARB_TEMP);
+ pci_write_config32(THERMAL_DEV, 0x44, 0);
+
+ /* Activate temporary BAR */
+ pci_or_config32(THERMAL_DEV, 0x40, 1);
+
+ /*
+ * BWG section 17.3.1 says:
+ *
+ * ### Initializing Lynx Point Thermal Sensors ###
+ *
+ * The System BIOS must perform the following steps to initialize the Lynx
+ * Point thermal subsystem device, D31:F6. The System BIOS is required to
+ * repeat this process on a resume from Sx. BIOS may enable any or all of
+ * the registers below based on OEM's platform configuration. Intel does
+ * not recommend a value on some of the registers, since each platform has
+ * different temperature trip points and one may enable a trip to cause an
+ * SMI while another platform would cause an interrupt instead.
+ *
+ * The recommended flow for enabling thermal sensor is by setting up various
+ * temperature trip points first, followed by enabling the desired trip
+ * alert method and then enable the actual sensors from TSEL registers.
+ * If this flow is not followed, software will need to take special care
+ * to handle false events during setting up those registers.
+ */
+
+ /* Step 1: Program CTT */
+ write16p(TBARB_TEMP + 0x10, 0x0154);
+
+ /* Step 2: Clear trip status from TSS and TAS */
+ write8p(TBARB_TEMP + 0x06, 0xff);
+ write8p(TBARB_TEMP + 0x80, 0xff);
+
+ /* Step 3: Program TSGPEN and TSPIEN to zero */
+ write8p(TBARB_TEMP + 0x84, 0x00);
+ write8p(TBARB_TEMP + 0x82, 0x00);
+
+ /*
+ * Step 4: If thermal reporting to an EC over SMBus is supported,
+ * then write 0x01 to TSREL, else leave at default.
+ */
+ write8p(TBARB_TEMP + 0x0a, 0x01);
+
+ /* Disable temporary BAR */
+ pci_and_config32(THERMAL_DEV, 0x40, ~1);
+
+ /* Clear temporary BAR address */
+ pci_write_config32(THERMAL_DEV, 0x40, 0);
+}
--
2.39.2
config/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch
-785
View File
@@ -1,785 +0,0 @@
From 7378cb4fefc87b9a096bb14820a44f26f3a628f5 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Fri, 6 May 2022 23:43:46 +0200
Subject: [PATCH 07/26] sb/intel/lynxpoint: Add native PCH init
Implement native PCH initialisation for Lynx Point. This is only needed
when MRC.bin is not used.
Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../haswell/native_raminit/raminit_native.c | 3 +-
src/southbridge/intel/lynxpoint/Makefile.inc | 1 +
.../intel/lynxpoint/early_pch_native.c | 123 +++++++++
.../intel/lynxpoint/hsio/Makefile.inc | 8 +
src/southbridge/intel/lynxpoint/hsio/common.c | 52 ++++
src/southbridge/intel/lynxpoint/hsio/hsio.h | 46 ++++
.../intel/lynxpoint/hsio/lpt_h_cx.c | 244 ++++++++++++++++++
.../intel/lynxpoint/hsio/lpt_lp_bx.c | 180 +++++++++++++
src/southbridge/intel/lynxpoint/pch.h | 6 +
9 files changed, 661 insertions(+), 2 deletions(-)
create mode 100644 src/southbridge/intel/lynxpoint/hsio/Makefile.inc
create mode 100644 src/southbridge/intel/lynxpoint/hsio/common.c
create mode 100644 src/southbridge/intel/lynxpoint/hsio/hsio.h
create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index dd1f1ec14e..b6efb6b40d 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -16,8 +16,7 @@ static bool early_init_native(int s3resume)
/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
- early_thermal_init();
- early_usb_init();
+ early_pch_init_native(s3resume);
if (!CONFIG(INTEL_LYNXPOINT_LP))
dmi_early_init();
diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
index a9a9b153d6..63243ecc86 100644
--- a/src/southbridge/intel/lynxpoint/Makefile.inc
+++ b/src/southbridge/intel/lynxpoint/Makefile.inc
@@ -38,6 +38,7 @@ romstage-y += early_usb.c early_me.c me_status.c early_pch.c
romstage-y += pmutil.c
romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c
+subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio
ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
romstage-y += lp_gpio.c
diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c
index c28ddfcf5d..421821fa5d 100644
--- a/src/southbridge/intel/lynxpoint/early_pch_native.c
+++ b/src/southbridge/intel/lynxpoint/early_pch_native.c
@@ -1,10 +1,133 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <console/console.h>
+#include <device/pci_def.h>
#include <device/pci_ops.h>
+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <types.h>
+static void early_sata_init(const uint8_t pch_revision)
+{
+ const bool is_mobile = get_pch_platform_type() != PCH_TYPE_DESKTOP;
+
+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
+ printk(BIOS_DEBUG, "HSIO lane owner: 0x%02x\n", lane_owner);
+
+ /* BWG Step 2 */
+ pci_update_config32(PCH_SATA_DEV, SATA_SCLKG, ~0x1ff, 0x183);
+
+ /* BWG Step 3: Set OOB Retry Mode */
+ pci_or_config16(PCH_SATA_DEV, SATA_PCS, 1 << 15);
+
+ /* BWG Step 4: Program the SATA mPHY tables */
+ if (pch_is_lp()) {
+ if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) {
+ program_hsio_sata_lpt_lp_bx(is_mobile);
+ } else {
+ printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision);
+ }
+ } else {
+ if (pch_revision >= LPT_H_STEP_C0) {
+ program_hsio_sata_lpt_h_cx(is_mobile);
+ } else {
+ printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision);
+ }
+ }
+
+ /** FIXME: Program SATA RxEq tables **/
+
+ /* BWG Step 5 */
+ /** FIXME: Only for desktop and mobile (skip this on workstation and server) **/
+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(22));
+
+ /* BWG Step 6 */
+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(19));
+
+ /* BWG Step 7 */
+ pci_update_config32(PCH_SATA_DEV, 0x98, ~(0x3f << 7), 0x04 << 7);
+
+ /* BWG Step 8 */
+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(20));
+
+ /* BWG Step 9 */
+ pci_update_config32(PCH_SATA_DEV, 0x98, ~(3 << 5), 1 << 5);
+
+ /* BWG Step 10 */
+ pci_or_config32(PCH_SATA_DEV, 0x98, BIT(18));
+
+ /* Enable SATA ports */
+ uint8_t sata_pcs = 0;
+ if (CONFIG(INTEL_LYNXPOINT_LP)) {
+ for (uint8_t i = 0; i < 4; i++) {
+ if ((lane_owner & BIT(7 - i)) == 0) {
+ sata_pcs |= BIT(i);
+ }
+ }
+ } else {
+ sata_pcs |= 0x0f;
+ for (uint8_t i = 4; i < 6; i++) {
+ if ((lane_owner & BIT(i)) == 0) {
+ sata_pcs |= BIT(i);
+ }
+ }
+ }
+ printk(BIOS_DEBUG, "SATA port enables: 0x%02x\n", sata_pcs);
+ pci_or_config8(PCH_SATA_DEV, SATA_PCS, sata_pcs);
+}
+
+void early_pch_init_native(int s3resume)
+{
+ const uint8_t pch_revision = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
+
+ RCBA16(DISPBDF) = 0x0010;
+ RCBA32_OR(FD2, PCH_ENABLE_DBDF);
+
+ /** FIXME: Check GEN_PMCON_3 and handle RTC failure? **/
+
+ RCBA32(PRSTS) = BIT(4);
+
+ early_sata_init(pch_revision);
+
+ pci_or_config8(PCH_LPC_DEV, 0xa6, 1 << 1);
+ pci_and_config8(PCH_LPC_DEV, 0xdc, ~(1 << 5 | 1 << 1));
+
+ /** TODO: Send GET HSIO VER and update ChipsetInit table? Is it needed? **/
+
+ /** FIXME: GbE handling? **/
+
+ pci_update_config32(PCH_LPC_DEV, 0xac, ~(1 << 20), 0);
+
+ for (uint8_t i = 0; i < 8; i++)
+ pci_update_config32(PCI_DEV(0, 0x1c, i), 0x338, ~(1 << 26), 0);
+
+ pci_update_config8(PCI_DEV(0, 0x1c, 0), 0xf4, ~(3 << 5), 1 << 7);
+
+ pci_update_config8(PCI_DEV(0, 26, 0), 0x88, ~(1 << 2), 0);
+ pci_update_config8(PCI_DEV(0, 29, 0), 0x88, ~(1 << 2), 0);
+
+ /** FIXME: Disable SATA2 device? **/
+
+ if (pch_is_lp()) {
+ if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) {
+ program_hsio_xhci_lpt_lp_bx();
+ program_hsio_igbe_lpt_lp_bx();
+ } else {
+ printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision);
+ }
+ } else {
+ if (pch_revision >= LPT_H_STEP_C0) {
+ program_hsio_xhci_lpt_h_cx();
+ program_hsio_igbe_lpt_h_cx();
+ } else {
+ printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision);
+ }
+ }
+
+ early_thermal_init();
+ early_usb_init();
+}
+
void pch_dmi_setup_physical_layer(void)
{
/* FIXME: We need to make sure the SA supports Gen2 as well */
diff --git a/src/southbridge/intel/lynxpoint/hsio/Makefile.inc b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc
new file mode 100644
index 0000000000..6b74997511
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+romstage-y += common.c
+ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
+romstage-y += lpt_lp_bx.c
+else
+romstage-y += lpt_h_cx.c
+endif
diff --git a/src/southbridge/intel/lynxpoint/hsio/common.c b/src/southbridge/intel/lynxpoint/hsio/common.c
new file mode 100644
index 0000000000..9935ca347a
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/hsio/common.c
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/pci_ops.h>
+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
+#include <types.h>
+
+/*
+ * FIXME: Ask Intel whether all lanes need to be programmed as specified
+ * in the PCH BWG. If not, make separate tables and only check this once.
+ */
+void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or)
+{
+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
+
+ if ((addr & 0xfe00) == 0x2000 && (lane_owner & (1 << 4)))
+ return;
+
+ if ((addr & 0xfe00) == 0x2200 && (lane_owner & (1 << 5)))
+ return;
+
+ if (CONFIG(INTEL_LYNXPOINT_LP)) {
+ if ((addr & 0xfe00) == 0x2400 && (lane_owner & (1 << 6)))
+ return;
+
+ if ((addr & 0xfe00) == 0x2600 && (lane_owner & (1 << 7)))
+ return;
+ }
+ hsio_update(addr, and, or);
+}
+
+/*
+ * FIXME: Ask Intel whether all lanes need to be programmed as specified
+ * in the PCH BWG. If not, make separate tables and only check this once.
+ */
+void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or)
+{
+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
+ if (CONFIG(INTEL_LYNXPOINT_LP)) {
+ if ((addr & 0xfe00) == 0x2400 && ((lane_owner >> 0) & 3) != 2)
+ return;
+
+ if ((addr & 0xfe00) == 0x2600 && ((lane_owner >> 2) & 3) != 2)
+ return;
+ } else {
+ if ((addr & 0xfe00) == 0x2c00 && ((lane_owner >> 2) & 3) != 2)
+ return;
+
+ if ((addr & 0xfe00) == 0x2e00 && ((lane_owner >> 0) & 3) != 2)
+ return;
+ }
+ hsio_update(addr, and, or);
+}
diff --git a/src/southbridge/intel/lynxpoint/hsio/hsio.h b/src/southbridge/intel/lynxpoint/hsio/hsio.h
new file mode 100644
index 0000000000..689ef4a05b
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/hsio/hsio.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H
+#define SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H
+
+#include <southbridge/intel/lynxpoint/iobp.h>
+#include <types.h>
+
+struct hsio_table_row {
+ uint32_t addr;
+ uint32_t and;
+ uint32_t or;
+};
+
+static inline void hsio_update(const uint32_t addr, const uint32_t and, const uint32_t or)
+{
+ pch_iobp_update(addr, and, or);
+}
+
+static inline void hsio_update_row(const struct hsio_table_row row)
+{
+ hsio_update(row.addr, row.and, row.or);
+}
+
+void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or);
+void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or);
+
+static inline void hsio_sata_shared_update_row(const struct hsio_table_row row)
+{
+ hsio_sata_shared_update(row.addr, row.and, row.or);
+}
+
+static inline void hsio_xhci_shared_update_row(const struct hsio_table_row row)
+{
+ hsio_xhci_shared_update(row.addr, row.and, row.or);
+}
+
+void program_hsio_sata_lpt_h_cx(const bool is_mobile);
+void program_hsio_xhci_lpt_h_cx(void);
+void program_hsio_igbe_lpt_h_cx(void);
+
+void program_hsio_sata_lpt_lp_bx(const bool is_mobile);
+void program_hsio_xhci_lpt_lp_bx(void);
+void program_hsio_igbe_lpt_lp_bx(void);
+
+#endif
diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
new file mode 100644
index 0000000000..b5dd402742
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/pci_ops.h>
+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
+#include <types.h>
+
+const struct hsio_table_row hsio_sata_shared_lpt_h_cx[] = {
+ { 0xea002008, ~0xfffc6108, 0xea6c6108 },
+ { 0xea002208, ~0xfffc6108, 0xea6c6108 },
+ { 0xea002038, ~0x3f00000f, 0x0700000d },
+ { 0xea002238, ~0x3f00000f, 0x0700000d },
+ { 0xea00202c, ~0x00020f00, 0x00020100 },
+ { 0xea00222c, ~0x00020f00, 0x00020100 },
+ { 0xea002040, ~0x1f000000, 0x01000000 },
+ { 0xea002240, ~0x1f000000, 0x01000000 },
+ { 0xea002010, ~0xffff0000, 0x0d510000 },
+ { 0xea002210, ~0xffff0000, 0x0d510000 },
+ { 0xea002018, ~0xffff0300, 0x38250100 },
+ { 0xea002218, ~0xffff0300, 0x38250100 },
+ { 0xea002000, ~0xcf030000, 0xcf030000 },
+ { 0xea002200, ~0xcf030000, 0xcf030000 },
+ { 0xea002028, ~0xff1f0000, 0x580e0000 },
+ { 0xea002228, ~0xff1f0000, 0x580e0000 },
+ { 0xea00201c, ~0x00007c00, 0x00002400 },
+ { 0xea00221c, ~0x00007c00, 0x00002400 },
+ { 0xea00208c, ~0x00ff0000, 0x00800000 },
+ { 0xea00228c, ~0x00ff0000, 0x00800000 },
+ { 0xea0020a4, ~0x0030ff00, 0x00308300 },
+ { 0xea0022a4, ~0x0030ff00, 0x00308300 },
+ { 0xea0020ac, ~0x00000030, 0x00000020 },
+ { 0xea0022ac, ~0x00000030, 0x00000020 },
+ { 0xea002140, ~0x00ffffff, 0x00140718 },
+ { 0xea002340, ~0x00ffffff, 0x00140718 },
+ { 0xea002144, ~0x00ffffff, 0x00140998 },
+ { 0xea002344, ~0x00ffffff, 0x00140998 },
+ { 0xea002148, ~0x00ffffff, 0x00140998 },
+ { 0xea002348, ~0x00ffffff, 0x00140998 },
+ { 0xea00217c, ~0x03000000, 0x03000000 },
+ { 0xea00237c, ~0x03000000, 0x03000000 },
+ { 0xea002178, ~0x00001f00, 0x00001800 },
+ { 0xea002378, ~0x00001f00, 0x00001800 },
+ { 0xea00210c, ~0x0038000f, 0x00000005 },
+ { 0xea00230c, ~0x0038000f, 0x00000005 },
+};
+
+const struct hsio_table_row hsio_sata_lpt_h_cx[] = {
+ { 0xea008008, ~0xff000000, 0x1c000000 },
+ { 0xea002408, ~0xfffc6108, 0xea6c6108 },
+ { 0xea002608, ~0xfffc6108, 0xea6c6108 },
+ { 0xea000808, ~0xfffc6108, 0xea6c6108 },
+ { 0xea000a08, ~0xfffc6108, 0xea6c6108 },
+ { 0xea002438, ~0x3f00000f, 0x0700000d },
+ { 0xea002638, ~0x3f00000f, 0x0700000d },
+ { 0xea000838, ~0x3f00000f, 0x0700000d },
+ { 0xea000a38, ~0x3f00000f, 0x0700000d },
+ { 0xea002440, ~0x1f000000, 0x01000000 },
+ { 0xea002640, ~0x1f000000, 0x01000000 },
+ { 0xea000840, ~0x1f000000, 0x01000000 },
+ { 0xea000a40, ~0x1f000000, 0x01000000 },
+ { 0xea002410, ~0xffff0000, 0x0d510000 },
+ { 0xea002610, ~0xffff0000, 0x0d510000 },
+ { 0xea000810, ~0xffff0000, 0x0d510000 },
+ { 0xea000a10, ~0xffff0000, 0x0d510000 },
+ { 0xea00242c, ~0x00020800, 0x00020000 },
+ { 0xea00262c, ~0x00020800, 0x00020000 },
+ { 0xea00082c, ~0x00020800, 0x00020000 },
+ { 0xea000a2c, ~0x00020800, 0x00020000 },
+ { 0xea002418, ~0xffff0300, 0x38250100 },
+ { 0xea002618, ~0xffff0300, 0x38250100 },
+ { 0xea000818, ~0xffff0300, 0x38250100 },
+ { 0xea000a18, ~0xffff0300, 0x38250100 },
+ { 0xea002400, ~0xcf030000, 0xcf030000 },
+ { 0xea002600, ~0xcf030000, 0xcf030000 },
+ { 0xea000800, ~0xcf030000, 0xcf030000 },
+ { 0xea000a00, ~0xcf030000, 0xcf030000 },
+ { 0xea002428, ~0xff1f0000, 0x580e0000 },
+ { 0xea002628, ~0xff1f0000, 0x580e0000 },
+ { 0xea000828, ~0xff1f0000, 0x580e0000 },
+ { 0xea000a28, ~0xff1f0000, 0x580e0000 },
+ { 0xea00241c, ~0x00007c00, 0x00002400 },
+ { 0xea00261c, ~0x00007c00, 0x00002400 },
+ { 0xea00081c, ~0x00007c00, 0x00002400 },
+ { 0xea000a1c, ~0x00007c00, 0x00002400 },
+ { 0xea00248c, ~0x00ff0000, 0x00800000 },
+ { 0xea00268c, ~0x00ff0000, 0x00800000 },
+ { 0xea00088c, ~0x00ff0000, 0x00800000 },
+ { 0xea000a8c, ~0x00ff0000, 0x00800000 },
+ { 0xea0024a4, ~0x0030ff00, 0x00308300 },
+ { 0xea0026a4, ~0x0030ff00, 0x00308300 },
+ { 0xea0008a4, ~0x0030ff00, 0x00308300 },
+ { 0xea000aa4, ~0x0030ff00, 0x00308300 },
+ { 0xea0024ac, ~0x00000030, 0x00000020 },
+ { 0xea0026ac, ~0x00000030, 0x00000020 },
+ { 0xea0008ac, ~0x00000030, 0x00000020 },
+ { 0xea000aac, ~0x00000030, 0x00000020 },
+ { 0xea002540, ~0x00ffffff, 0x00140718 },
+ { 0xea002740, ~0x00ffffff, 0x00140718 },
+ { 0xea000940, ~0x00ffffff, 0x00140718 },
+ { 0xea000b40, ~0x00ffffff, 0x00140718 },
+ { 0xea002544, ~0x00ffffff, 0x00140998 },
+ { 0xea002744, ~0x00ffffff, 0x00140998 },
+ { 0xea000944, ~0x00ffffff, 0x00140998 },
+ { 0xea000b44, ~0x00ffffff, 0x00140998 },
+ { 0xea002548, ~0x00ffffff, 0x00140998 },
+ { 0xea002748, ~0x00ffffff, 0x00140998 },
+ { 0xea000948, ~0x00ffffff, 0x00140998 },
+ { 0xea000b48, ~0x00ffffff, 0x00140998 },
+ { 0xea00257c, ~0x03000000, 0x03000000 },
+ { 0xea00277c, ~0x03000000, 0x03000000 },
+ { 0xea00097c, ~0x03000000, 0x03000000 },
+ { 0xea000b7c, ~0x03000000, 0x03000000 },
+ { 0xea002578, ~0x00001f00, 0x00001800 },
+ { 0xea002778, ~0x00001f00, 0x00001800 },
+ { 0xea000978, ~0x00001f00, 0x00001800 },
+ { 0xea000b78, ~0x00001f00, 0x00001800 },
+ { 0xea00250c, ~0x0038000f, 0x00000005 },
+ { 0xea00270c, ~0x0038000f, 0x00000005 },
+ { 0xea00090c, ~0x0038000f, 0x00000005 },
+ { 0xea000b0c, ~0x0038000f, 0x00000005 },
+};
+
+const struct hsio_table_row hsio_xhci_shared_lpt_h_cx[] = {
+ { 0xe9002c2c, ~0x00000700, 0x00000100 },
+ { 0xe9002e2c, ~0x00000700, 0x00000100 },
+ { 0xe9002dcc, ~0x00001407, 0x00001407 },
+ { 0xe9002fcc, ~0x00001407, 0x00001407 },
+ { 0xe9002d68, ~0x01000f3c, 0x00000a28 },
+ { 0xe9002f68, ~0x01000f3c, 0x00000a28 },
+ { 0xe9002d6c, ~0x000000ff, 0x0000003f },
+ { 0xe9002f6c, ~0x000000ff, 0x0000003f },
+ { 0xe9002d4c, ~0x00ffff00, 0x00120500 },
+ { 0xe9002f4c, ~0x00ffff00, 0x00120500 },
+ { 0xe9002d14, ~0x38000700, 0x00000100 },
+ { 0xe9002f14, ~0x38000700, 0x00000100 },
+ { 0xe9002d64, ~0x0000f000, 0x00005000 },
+ { 0xe9002f64, ~0x0000f000, 0x00005000 },
+ { 0xe9002d70, ~0x00000018, 0x00000000 },
+ { 0xe9002f70, ~0x00000018, 0x00000000 },
+ { 0xe9002c38, ~0x3f00000f, 0x0700000b },
+ { 0xe9002e38, ~0x3f00000f, 0x0700000b },
+ { 0xe9002d40, ~0x00800000, 0x00000000 },
+ { 0xe9002f40, ~0x00800000, 0x00000000 },
+};
+
+const struct hsio_table_row hsio_xhci_lpt_h_cx[] = {
+ { 0xe90031cc, ~0x00001407, 0x00001407 },
+ { 0xe90033cc, ~0x00001407, 0x00001407 },
+ { 0xe90015cc, ~0x00001407, 0x00001407 },
+ { 0xe90017cc, ~0x00001407, 0x00001407 },
+ { 0xe9003168, ~0x01000f3c, 0x00000a28 },
+ { 0xe9003368, ~0x01000f3c, 0x00000a28 },
+ { 0xe9001568, ~0x01000f3c, 0x00000a28 },
+ { 0xe9001768, ~0x01000f3c, 0x00000a28 },
+ { 0xe900316c, ~0x000000ff, 0x0000003f },
+ { 0xe900336c, ~0x000000ff, 0x0000003f },
+ { 0xe900156c, ~0x000000ff, 0x0000003f },
+ { 0xe900176c, ~0x000000ff, 0x0000003f },
+ { 0xe900314c, ~0x00ffff00, 0x00120500 },
+ { 0xe900334c, ~0x00ffff00, 0x00120500 },
+ { 0xe900154c, ~0x00ffff00, 0x00120500 },
+ { 0xe900174c, ~0x00ffff00, 0x00120500 },
+ { 0xe9003114, ~0x38000700, 0x00000100 },
+ { 0xe9003314, ~0x38000700, 0x00000100 },
+ { 0xe9001514, ~0x38000700, 0x00000100 },
+ { 0xe9001714, ~0x38000700, 0x00000100 },
+ { 0xe9003164, ~0x0000f000, 0x00005000 },
+ { 0xe9003364, ~0x0000f000, 0x00005000 },
+ { 0xe9001564, ~0x0000f000, 0x00005000 },
+ { 0xe9001764, ~0x0000f000, 0x00005000 },
+ { 0xe9003170, ~0x00000018, 0x00000000 },
+ { 0xe9003370, ~0x00000018, 0x00000000 },
+ { 0xe9001570, ~0x00000018, 0x00000000 },
+ { 0xe9001770, ~0x00000018, 0x00000000 },
+ { 0xe9003038, ~0x3f00000f, 0x0700000b },
+ { 0xe9003238, ~0x3f00000f, 0x0700000b },
+ { 0xe9001438, ~0x3f00000f, 0x0700000b },
+ { 0xe9001638, ~0x3f00000f, 0x0700000b },
+ { 0xe9003140, ~0x00800000, 0x00000000 },
+ { 0xe9003340, ~0x00800000, 0x00000000 },
+ { 0xe9001540, ~0x00800000, 0x00000000 },
+ { 0xe9001740, ~0x00800000, 0x00000000 },
+};
+
+void program_hsio_sata_lpt_h_cx(const bool is_mobile)
+{
+ const struct hsio_table_row *pch_hsio_table;
+ size_t len;
+
+ pch_hsio_table = hsio_sata_lpt_h_cx;
+ len = ARRAY_SIZE(hsio_sata_lpt_h_cx);
+ for (size_t i = 0; i < len; i++)
+ hsio_update_row(pch_hsio_table[i]);
+
+ pch_hsio_table = hsio_sata_shared_lpt_h_cx;
+ len = ARRAY_SIZE(hsio_sata_shared_lpt_h_cx);
+ for (size_t i = 0; i < len; i++)
+ hsio_sata_shared_update_row(pch_hsio_table[i]);
+
+ const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67;
+
+ hsio_update(0xea002490, ~0x0000ffff, hsio_sata_value);
+ hsio_update(0xea002690, ~0x0000ffff, hsio_sata_value);
+ hsio_update(0xea000890, ~0x0000ffff, hsio_sata_value);
+ hsio_update(0xea000a90, ~0x0000ffff, hsio_sata_value);
+
+ hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value);
+ hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value);
+}
+
+void program_hsio_xhci_lpt_h_cx(void)
+{
+ const struct hsio_table_row *pch_hsio_table;
+ size_t len;
+
+ pch_hsio_table = hsio_xhci_lpt_h_cx;
+ len = ARRAY_SIZE(hsio_xhci_lpt_h_cx);
+
+ for (size_t i = 0; i < len; i++)
+ hsio_update_row(pch_hsio_table[i]);
+
+ pch_hsio_table = hsio_xhci_shared_lpt_h_cx;
+ len = ARRAY_SIZE(hsio_xhci_shared_lpt_h_cx);
+
+ for (size_t i = 0; i < len; i++)
+ hsio_xhci_shared_update_row(pch_hsio_table[i]);
+}
+
+void program_hsio_igbe_lpt_h_cx(void)
+{
+ const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc);
+ if (!(strpfusecfg1 & (1 << 19)))
+ return;
+
+ const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7;
+ const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
+ if (gbe_port == 0 && ((lane_owner >> 0) & 3) != 1)
+ return;
+
+ if (gbe_port == 1 && ((lane_owner >> 2) & 3) != 1)
+ return;
+
+ const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x2e - 2 * gbe_port) << 8;
+ hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100);
+}
diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
new file mode 100644
index 0000000000..24679e791a
--- /dev/null
+++ b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/pci_ops.h>
+#include <southbridge/intel/lynxpoint/iobp.h>
+#include <southbridge/intel/lynxpoint/hsio/hsio.h>
+#include <types.h>
+
+const struct hsio_table_row hsio_sata_shared_lpt_lp_bx[] = {
+ { 0xea008008, ~0xff000000, 0x1c000000 },
+ { 0xea002008, ~0xfffc6108, 0xea6c6108 },
+ { 0xea002208, ~0xfffc6108, 0xea6c6108 },
+ { 0xea002408, ~0xfffc6108, 0xea6c6108 },
+ { 0xea002608, ~0xfffc6108, 0xea6c6108 },
+ { 0xea002038, ~0x0000000f, 0x0000000d },
+ { 0xea002238, ~0x0000000f, 0x0000000d },
+ { 0xea002438, ~0x0000000f, 0x0000000d },
+ { 0xea002638, ~0x0000000f, 0x0000000d },
+ { 0xea00202c, ~0x00020f00, 0x00020100 },
+ { 0xea00222c, ~0x00020f00, 0x00020100 },
+ { 0xea00242c, ~0x00020f00, 0x00020100 },
+ { 0xea00262c, ~0x00020f00, 0x00020100 },
+ { 0xea002040, ~0x1f000000, 0x01000000 },
+ { 0xea002240, ~0x1f000000, 0x01000000 },
+ { 0xea002440, ~0x1f000000, 0x01000000 },
+ { 0xea002640, ~0x1f000000, 0x01000000 },
+ { 0xea002010, ~0xffff0000, 0x55510000 },
+ { 0xea002210, ~0xffff0000, 0x55510000 },
+ { 0xea002410, ~0xffff0000, 0x55510000 },
+ { 0xea002610, ~0xffff0000, 0x55510000 },
+ { 0xea002140, ~0x00ffffff, 0x00140718 },
+ { 0xea002340, ~0x00ffffff, 0x00140718 },
+ { 0xea002540, ~0x00ffffff, 0x00140718 },
+ { 0xea002740, ~0x00ffffff, 0x00140718 },
+ { 0xea002144, ~0x00ffffff, 0x00140998 },
+ { 0xea002344, ~0x00ffffff, 0x00140998 },
+ { 0xea002544, ~0x00ffffff, 0x00140998 },
+ { 0xea002744, ~0x00ffffff, 0x00140998 },
+ { 0xea002148, ~0x00ffffff, 0x00140998 },
+ { 0xea002348, ~0x00ffffff, 0x00140998 },
+ { 0xea002548, ~0x00ffffff, 0x00140998 },
+ { 0xea002748, ~0x00ffffff, 0x00140998 },
+ { 0xea00217c, ~0x03000000, 0x03000000 },
+ { 0xea00237c, ~0x03000000, 0x03000000 },
+ { 0xea00257c, ~0x03000000, 0x03000000 },
+ { 0xea00277c, ~0x03000000, 0x03000000 },
+ { 0xea00208c, ~0x00ff0000, 0x00800000 },
+ { 0xea00228c, ~0x00ff0000, 0x00800000 },
+ { 0xea00248c, ~0x00ff0000, 0x00800000 },
+ { 0xea00268c, ~0x00ff0000, 0x00800000 },
+ { 0xea0020a4, ~0x0030ff00, 0x00308300 },
+ { 0xea0022a4, ~0x0030ff00, 0x00308300 },
+ { 0xea0024a4, ~0x0030ff00, 0x00308300 },
+ { 0xea0026a4, ~0x0030ff00, 0x00308300 },
+ { 0xea0020ac, ~0x00000030, 0x00000020 },
+ { 0xea0022ac, ~0x00000030, 0x00000020 },
+ { 0xea0024ac, ~0x00000030, 0x00000020 },
+ { 0xea0026ac, ~0x00000030, 0x00000020 },
+ { 0xea002018, ~0xffff0300, 0x38250100 },
+ { 0xea002218, ~0xffff0300, 0x38250100 },
+ { 0xea002418, ~0xffff0300, 0x38250100 },
+ { 0xea002618, ~0xffff0300, 0x38250100 },
+ { 0xea002000, ~0xcf030000, 0xcf030000 },
+ { 0xea002200, ~0xcf030000, 0xcf030000 },
+ { 0xea002400, ~0xcf030000, 0xcf030000 },
+ { 0xea002600, ~0xcf030000, 0xcf030000 },
+ { 0xea002028, ~0xff1f0000, 0x580e0000 },
+ { 0xea002228, ~0xff1f0000, 0x580e0000 },
+ { 0xea002428, ~0xff1f0000, 0x580e0000 },
+ { 0xea002628, ~0xff1f0000, 0x580e0000 },
+ { 0xea00201c, ~0x00007c00, 0x00002400 },
+ { 0xea00221c, ~0x00007c00, 0x00002400 },
+ { 0xea00241c, ~0x00007c00, 0x00002400 },
+ { 0xea00261c, ~0x00007c00, 0x00002400 },
+ { 0xea002178, ~0x00001f00, 0x00001800 },
+ { 0xea002378, ~0x00001f00, 0x00001800 },
+ { 0xea002578, ~0x00001f00, 0x00001800 },
+ { 0xea002778, ~0x00001f00, 0x00001800 },
+ { 0xea00210c, ~0x0038000f, 0x00000005 },
+ { 0xea00230c, ~0x0038000f, 0x00000005 },
+ { 0xea00250c, ~0x0038000f, 0x00000005 },
+ { 0xea00270c, ~0x0038000f, 0x00000005 },
+};
+
+const struct hsio_table_row hsio_xhci_shared_lpt_lp_bx[] = {
+ { 0xe90025cc, ~0x00001407, 0x00001407 },
+ { 0xe90027cc, ~0x00001407, 0x00001407 },
+ { 0xe9002568, ~0x01000f3c, 0x00000a28 },
+ { 0xe9002768, ~0x01000f3c, 0x00000a28 },
+ { 0xe900242c, ~0x00000700, 0x00000100 },
+ { 0xe900262c, ~0x00000700, 0x00000100 },
+ { 0xe900256c, ~0x000000ff, 0x0000003f },
+ { 0xe900276c, ~0x000000ff, 0x0000003f },
+ { 0xe900254c, ~0x00ffff00, 0x00120500 },
+ { 0xe900274c, ~0x00ffff00, 0x00120500 },
+ { 0xe9002564, ~0x0000f000, 0x00005000 },
+ { 0xe9002764, ~0x0000f000, 0x00005000 },
+ { 0xe9002570, ~0x00000018, 0x00000000 },
+ { 0xe9002770, ~0x00000018, 0x00000000 },
+ { 0xe9002514, ~0x38000700, 0x00000100 },
+ { 0xe9002714, ~0x38000700, 0x00000100 },
+ { 0xe9002438, ~0x0000000f, 0x0000000b },
+ { 0xe9002638, ~0x0000000f, 0x0000000b },
+ { 0xe9002414, ~0x0000fe00, 0x00006600 },
+ { 0xe9002614, ~0x0000fe00, 0x00006600 },
+ { 0xe9002540, ~0x00800000, 0x00000000 },
+ { 0xe9002740, ~0x00800000, 0x00000000 },
+};
+
+const struct hsio_table_row hsio_xhci_lpt_lp_bx[] = {
+ { 0xe90021cc, ~0x00001407, 0x00001407 },
+ { 0xe90023cc, ~0x00001407, 0x00001407 },
+ { 0xe9002168, ~0x01000f3c, 0x00000a28 },
+ { 0xe9002368, ~0x01000f3c, 0x00000a28 },
+ { 0xe900216c, ~0x000000ff, 0x0000003f },
+ { 0xe900236c, ~0x000000ff, 0x0000003f },
+ { 0xe900214c, ~0x00ffff00, 0x00120500 },
+ { 0xe900234c, ~0x00ffff00, 0x00120500 },
+ { 0xe9002164, ~0x0000f000, 0x00005000 },
+ { 0xe9002364, ~0x0000f000, 0x00005000 },
+ { 0xe9002170, ~0x00000018, 0x00000000 },
+ { 0xe9002370, ~0x00000018, 0x00000000 },
+ { 0xe9002114, ~0x38000700, 0x00000100 },
+ { 0xe9002314, ~0x38000700, 0x00000100 },
+ { 0xe9002038, ~0x0000000f, 0x0000000b },
+ { 0xe9002238, ~0x0000000f, 0x0000000b },
+ { 0xe9002014, ~0x0000fe00, 0x00006600 },
+ { 0xe9002214, ~0x0000fe00, 0x00006600 },
+ { 0xe9002140, ~0x00800000, 0x00000000 },
+ { 0xe9002340, ~0x00800000, 0x00000000 },
+};
+
+void program_hsio_sata_lpt_lp_bx(const bool is_mobile)
+{
+ const struct hsio_table_row *pch_hsio_table;
+ size_t len;
+
+ pch_hsio_table = hsio_sata_shared_lpt_lp_bx;
+ len = ARRAY_SIZE(hsio_sata_shared_lpt_lp_bx);
+ for (size_t i = 0; i < len; i++)
+ hsio_sata_shared_update_row(pch_hsio_table[i]);
+
+ const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67;
+
+ hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value);
+ hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value);
+ hsio_sata_shared_update(0xea002490, ~0x0000ffff, hsio_sata_value);
+ hsio_sata_shared_update(0xea002690, ~0x0000ffff, hsio_sata_value);
+}
+
+void program_hsio_xhci_lpt_lp_bx(void)
+{
+ const struct hsio_table_row *pch_hsio_table;
+ size_t len;
+
+ pch_hsio_table = hsio_xhci_lpt_lp_bx;
+ len = ARRAY_SIZE(hsio_xhci_lpt_lp_bx);
+
+ for (size_t i = 0; i < len; i++)
+ hsio_update_row(pch_hsio_table[i]);
+
+ pch_hsio_table = hsio_xhci_shared_lpt_lp_bx;
+ len = ARRAY_SIZE(hsio_xhci_shared_lpt_lp_bx);
+
+ for (size_t i = 0; i < len; i++)
+ hsio_xhci_shared_update_row(pch_hsio_table[i]);
+}
+
+void program_hsio_igbe_lpt_lp_bx(void)
+{
+ const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc);
+ if (!(strpfusecfg1 & (1 << 19)))
+ return;
+
+ const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7;
+ if (gbe_port > 5)
+ return;
+
+ const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x08 + 2 * gbe_port) << 8;
+ hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100);
+}
diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
index 38a9349220..74b4d50017 100644
--- a/src/southbridge/intel/lynxpoint/pch.h
+++ b/src/southbridge/intel/lynxpoint/pch.h
@@ -117,6 +117,7 @@ void pch_dmi_setup_physical_layer(void);
void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
void early_usb_init(void);
void early_thermal_init(void);
+void early_pch_init_native(int s3resume);
void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
void usb_ehci_disable(pci_devfn_t dev);
@@ -271,6 +272,10 @@ void mainboard_config_rcba(void);
#define IDE_DECODE_ENABLE (1 << 15)
#define IDE_TIM_SEC 0x42 /* IDE timings, secondary */
+#define SATA_MAP 0x90
+#define SATA_PCS 0x92
+#define SATA_SCLKG 0x94
+
#define SATA_SIRI 0xa0 /* SATA Indexed Register Index */
#define SATA_SIRD 0xa4 /* SATA Indexed Register Data */
#define SATA_SP 0xd0 /* Scratchpad */
@@ -580,6 +585,7 @@ void mainboard_config_rcba(void);
#define D19IR 0x3168 /* 16bit */
#define ACPIIRQEN 0x31e0 /* 32bit */
#define OIC 0x31fe /* 16bit */
+#define PRSTS 0x3310 /* 32bit */
#define PMSYNC_CONFIG 0x33c4 /* 32bit */
#define PMSYNC_CONFIG2 0x33cc /* 32bit */
#define SOFT_RESET_CTRL 0x38f4
--
2.39.2
config/coreboot/haswell/patches/0008-nb-intel-haswell-Add-native-raminit-scaffolding.patch
-407
View File
@@ -1,407 +0,0 @@
From 46cdec8cbce15ca11ad9a49a3ee415a78f781997 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 00:26:10 +0200
Subject: [PATCH 08/26] nb/intel/haswell: Add native raminit scaffolding
Implement some scaffolding for Haswell native raminit, like bootmode
selection, handling of MRC cache and CPU detection.
Change-Id: Icd96649fa045ea7f0f32ae9bfe1e60498d93975b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.inc | 1 +
.../haswell/native_raminit/raminit_main.c | 104 ++++++++++
.../haswell/native_raminit/raminit_native.c | 189 +++++++++++++++++-
.../haswell/native_raminit/raminit_native.h | 34 ++++
4 files changed, 322 insertions(+), 6 deletions(-)
create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_main.c
create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.h
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
index 8cfb4fb33e..90af951c5a 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
@@ -1,3 +1,4 @@
## SPDX-License-Identifier: GPL-2.0-or-later
+romstage-y += raminit_main.c
romstage-y += raminit_native.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
new file mode 100644
index 0000000000..9b42c25b40
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <console/console.h>
+#include <cpu/intel/haswell/haswell.h>
+#include <delay.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/chip.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <string.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+struct task_entry {
+ enum raminit_status (*task)(struct sysinfo *);
+ bool is_enabled;
+ const char *name;
+};
+
+static const struct task_entry cold_boot[] = {
+};
+
+/* Return a generic stepping value to make stepping checks simpler */
+static enum generic_stepping get_stepping(const uint32_t cpuid)
+{
+ switch (cpuid) {
+ case CPUID_HASWELL_A0:
+ die("Haswell stepping A0 is not supported\n");
+ case CPUID_HASWELL_B0:
+ case CPUID_HASWELL_ULT_B0:
+ case CPUID_CRYSTALWELL_B0:
+ return STEPPING_B0;
+ case CPUID_HASWELL_C0:
+ case CPUID_HASWELL_ULT_C0:
+ case CPUID_CRYSTALWELL_C0:
+ return STEPPING_C0;
+ default:
+ /** TODO: Add Broadwell support someday **/
+ die("Unknown CPUID 0x%x\n", cpuid);
+ }
+}
+
+static void initialize_ctrl(struct sysinfo *ctrl)
+{
+ const struct northbridge_intel_haswell_config *cfg = config_of_soc();
+ const enum raminit_boot_mode bootmode = ctrl->bootmode;
+
+ memset(ctrl, 0, sizeof(*ctrl));
+
+ ctrl->cpu = cpu_get_cpuid();
+ ctrl->stepping = get_stepping(ctrl->cpu);
+ ctrl->dq_pins_interleaved = cfg->dq_pins_interleaved;
+ ctrl->bootmode = bootmode;
+}
+
+static enum raminit_status try_raminit(struct sysinfo *ctrl)
+{
+ const struct task_entry *const schedule = cold_boot;
+ const size_t length = ARRAY_SIZE(cold_boot);
+
+ enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
+
+ for (size_t i = 0; i < length; i++) {
+ const struct task_entry *const entry = &schedule[i];
+ assert(entry);
+ assert(entry->name);
+ if (!entry->is_enabled)
+ continue;
+
+ assert(entry->task);
+ printk(RAM_DEBUG, "\nExecuting raminit task %s\n", entry->name);
+ status = entry->task(ctrl);
+ printk(RAM_DEBUG, "\n");
+ if (status) {
+ printk(BIOS_ERR, "raminit failed on step %s\n", entry->name);
+ break;
+ }
+ }
+
+ return status;
+}
+
+void raminit_main(const enum raminit_boot_mode bootmode)
+{
+ /*
+ * The mighty_ctrl struct. Will happily nuke the pre-RAM stack
+ * if left unattended. Make it static and pass pointers to it.
+ */
+ static struct sysinfo mighty_ctrl;
+
+ mighty_ctrl.bootmode = bootmode;
+ initialize_ctrl(&mighty_ctrl);
+
+ /** TODO: Try more than once **/
+ enum raminit_status status = try_raminit(&mighty_ctrl);
+
+ if (status != RAMINIT_STATUS_SUCCESS)
+ die("Memory initialization was met with utmost failure and misery\n");
+
+ /** TODO: Implement the required magic **/
+ die("NATIVE RAMINIT: More Magic (tm) required.\n");
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index b6efb6b40d..0869db3902 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -1,13 +1,45 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
+#include <arch/cpu.h>
+#include <assert.h>
+#include <cbmem.h>
+#include <cf9_reset.h>
#include <console/console.h>
+#include <cpu/x86/msr.h>
#include <delay.h>
+#include <device/pci_ops.h>
+#include <mrc_cache.h>
#include <northbridge/intel/haswell/haswell.h>
#include <northbridge/intel/haswell/raminit.h>
#include <southbridge/intel/lynxpoint/me.h>
#include <southbridge/intel/lynxpoint/pch.h>
#include <types.h>
+#include "raminit_native.h"
+
+static void wait_txt_clear(void)
+{
+ const struct cpuid_result cpuid = cpuid_ext(1, 0);
+
+ /* Check if TXT is supported */
+ if (!(cpuid.ecx & BIT(6)))
+ return;
+
+ /* Some TXT public bit */
+ if (!(read32p(0xfed30010) & 1))
+ return;
+
+ /* Wait for TXT clear */
+ do {} while (!(read8p(0xfed40000) & (1 << 7)));
+}
+
+static enum raminit_boot_mode get_boot_mode(void)
+{
+ const uint16_t pmcon_2 = pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2);
+ const uint16_t bitmask = GEN_PMCON_2_DISB | GEN_PMCON_2_MEM_SR;
+ return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD;
+}
+
static bool early_init_native(int s3resume)
{
printk(BIOS_DEBUG, "Starting native platform initialisation\n");
@@ -24,6 +56,120 @@ static bool early_init_native(int s3resume)
return cpu_replaced;
}
+#define MRC_CACHE_VERSION 1
+
+struct mrc_data {
+ const void *buffer;
+ size_t buffer_len;
+};
+
+static void save_mrc_data(struct mrc_data *md)
+{
+ mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len);
+}
+
+static struct mrc_data prepare_mrc_cache(void)
+{
+ struct mrc_data md = {0};
+ md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+ MRC_CACHE_VERSION,
+ &md.buffer_len);
+ return md;
+}
+
+static const char *const bm_names[] = {
+ "BOOTMODE_COLD",
+ "BOOTMODE_WARM",
+ "BOOTMODE_S3",
+ "BOOTMODE_FAST",
+};
+
+static void clear_disb(void)
+{
+ pci_and_config16(PCH_LPC_DEV, GEN_PMCON_2, ~GEN_PMCON_2_DISB);
+}
+
+static void raminit_reset(void)
+{
+ clear_disb();
+ system_reset();
+}
+
+static enum raminit_boot_mode do_actual_raminit(
+ struct mrc_data *md,
+ const bool s3resume,
+ const bool cpu_replaced,
+ const enum raminit_boot_mode orig_bootmode)
+{
+ enum raminit_boot_mode bootmode = orig_bootmode;
+
+ bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/
+
+ if (s3resume) {
+ if (bootmode == BOOTMODE_COLD) {
+ printk(BIOS_EMERG, "Memory may not be in self-refresh for S3 resume\n");
+ printk(BIOS_EMERG, "S3 resume and cold boot are mutually exclusive\n");
+ raminit_reset();
+ }
+ /* Only a true mad hatter would replace a CPU in S3 */
+ if (cpu_replaced) {
+ printk(BIOS_EMERG, "Oh no, CPU was replaced during S3\n");
+ /*
+ * No reason to continue, memory consistency is most likely lost
+ * and ME will probably request a reset through DID response too.
+ */
+ /** TODO: Figure out why past self commented this out **/
+ //raminit_reset();
+ }
+ bootmode = BOOTMODE_S3;
+ if (!save_data_valid) {
+ printk(BIOS_EMERG, "No training data, S3 resume is impossible\n");
+ /* Failed S3 resume, reset to come up cleanly */
+ raminit_reset();
+ }
+ }
+ if (!s3resume && cpu_replaced) {
+ printk(BIOS_NOTICE, "CPU was replaced, forcing a cold boot\n");
+ /*
+ * Looks like the ME will get angry if raminit takes too long.
+ * It will report that the CPU has been replaced on next boot.
+ * Try to continue anyway. This should not happen in most cases.
+ */
+ /** TODO: Figure out why past self commented this out **/
+ //save_data_valid = false;
+ }
+ if (bootmode == BOOTMODE_COLD) {
+ /* If possible, promote to a fast boot */
+ if (save_data_valid)
+ bootmode = BOOTMODE_FAST;
+
+ clear_disb();
+ } else if (bootmode == BOOTMODE_WARM) {
+ /* If a warm reset happened before raminit is done, force a cold boot */
+ if (mchbar_read32(SSKPD) == 0 && mchbar_read32(SSKPD + 4) == 0) {
+ printk(BIOS_NOTICE, "Warm reset occurred early in cold boot\n");
+ save_data_valid = false;
+ }
+ if (!save_data_valid)
+ bootmode = BOOTMODE_COLD;
+ }
+ assert(save_data_valid != (bootmode == BOOTMODE_COLD));
+ if (save_data_valid) {
+ printk(BIOS_INFO, "Using cached memory parameters\n");
+ die("RAMINIT: Fast boot is not yet implemented\n");
+ }
+ printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]);
+ printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]);
+
+ /*
+ * And now, the actual memory initialization thing.
+ */
+ printk(RAM_DEBUG, "\nStarting native raminit\n");
+ raminit_main(bootmode);
+
+ return bootmode;
+}
+
void perform_raminit(const int s3resume)
{
/*
@@ -32,17 +178,48 @@ void perform_raminit(const int s3resume)
*/
const bool cpu_replaced = early_init_native(s3resume);
- (void)cpu_replaced;
+ wait_txt_clear();
+ wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
+
+ const enum raminit_boot_mode orig_bootmode = get_boot_mode();
+
+ struct mrc_data md = prepare_mrc_cache();
+
+ const enum raminit_boot_mode bootmode =
+ do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode);
+
+ /** TODO: report_memory_config **/
- /** TODO: Move after raminit */
if (intel_early_me_uma_size() > 0) {
- /** TODO: Update status once raminit is implemented **/
- uint8_t me_status = ME_INIT_STATUS_ERROR;
+ /*
+ * The 'other' success value is to report loss of memory
+ * consistency to ME if warm boot was downgraded to cold.
+ */
+ uint8_t me_status;
+ if (BOOTMODE_WARM == orig_bootmode && BOOTMODE_COLD == bootmode)
+ me_status = ME_INIT_STATUS_SUCCESS_OTHER;
+ else
+ me_status = ME_INIT_STATUS_SUCCESS;
+
+ /** TODO: Remove this once raminit is implemented **/
+ me_status = ME_INIT_STATUS_ERROR;
intel_early_me_init_done(me_status);
}
+ post_code(0x3b);
+
intel_early_me_status();
- /** TODO: Implement the required magic **/
- die("NATIVE RAMINIT: More Magic (tm) required.\n");
+ const bool cbmem_was_initted = !cbmem_recovery(s3resume);
+ if (s3resume && !cbmem_was_initted) {
+ /* Failed S3 resume, reset to come up cleanly */
+ printk(BIOS_CRIT, "Failed to recover CBMEM in S3 resume.\n");
+ system_reset();
+ }
+
+ /* Save training data on non-S3 resumes */
+ if (!s3resume)
+ save_mrc_data(&md);
+
+ /** TODO: setup_sdram_meminfo **/
}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
new file mode 100644
index 0000000000..885f0184f4
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef HASWELL_RAMINIT_NATIVE_H
+#define HASWELL_RAMINIT_NATIVE_H
+
+enum raminit_boot_mode {
+ BOOTMODE_COLD,
+ BOOTMODE_WARM,
+ BOOTMODE_S3,
+ BOOTMODE_FAST,
+};
+
+enum raminit_status {
+ RAMINIT_STATUS_SUCCESS = 0,
+ RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
+};
+
+enum generic_stepping {
+ STEPPING_A0 = 1,
+ STEPPING_B0 = 2,
+ STEPPING_C0 = 3,
+};
+
+struct sysinfo {
+ enum raminit_boot_mode bootmode;
+ enum generic_stepping stepping;
+ uint32_t cpu; /* CPUID value */
+
+ bool dq_pins_interleaved;
+};
+
+void raminit_main(enum raminit_boot_mode bootmode);
+
+#endif
--
2.39.2
config/coreboot/haswell/patches/0009-nb-intel-haswell-nri-Only-do-CPU-replacement-check-o.patch
-57
View File
@@ -1,57 +0,0 @@
From 731216aef3129ae27ad5adc7266cb8a58090c9fc Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sun, 26 Jun 2022 10:32:12 +0200
Subject: [PATCH 09/26] nb/intel/haswell/nri: Only do CPU replacement check on
cold boots
CPU replacement check should only be done on cold boots.
Change-Id: I98efa105f4df755b23febe12dd7b356787847852
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/raminit_native.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
index 0869db3902..bd9bc8e692 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
@@ -40,15 +40,14 @@ static enum raminit_boot_mode get_boot_mode(void)
return (pmcon_2 & bitmask) == bitmask ? BOOTMODE_WARM : BOOTMODE_COLD;
}
-static bool early_init_native(int s3resume)
+static bool early_init_native(enum raminit_boot_mode bootmode)
{
printk(BIOS_DEBUG, "Starting native platform initialisation\n");
intel_early_me_init();
- /** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
- const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
+ bool cpu_replaced = bootmode == BOOTMODE_COLD && intel_early_me_cpu_replacement_check();
- early_pch_init_native(s3resume);
+ early_pch_init_native(bootmode == BOOTMODE_S3);
if (!CONFIG(INTEL_LYNXPOINT_LP))
dmi_early_init();
@@ -176,13 +175,13 @@ void perform_raminit(const int s3resume)
* See, this function's name is a lie. There are more things to
* do that memory initialisation, but they are relatively easy.
*/
- const bool cpu_replaced = early_init_native(s3resume);
+ const enum raminit_boot_mode orig_bootmode = get_boot_mode();
+
+ const bool cpu_replaced = early_init_native(s3resume ? BOOTMODE_S3 : orig_bootmode);
wait_txt_clear();
wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
- const enum raminit_boot_mode orig_bootmode = get_boot_mode();
-
struct mrc_data md = prepare_mrc_cache();
const enum raminit_boot_mode bootmode =
--
2.39.2
config/coreboot/haswell/patches/0010-haswell-NRI-Collect-SPD-info.patch
-344
View File
@@ -1,344 +0,0 @@
From 354969af4361bcc7dc240ef5871d169728f7f0cc Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 13:48:53 +0200
Subject: [PATCH 10/26] haswell NRI: Collect SPD info
Collect SPD data from DIMMs and memory-down, and find the common
supported settings.
Change-Id: I4e6a1408a638a463ecae37a447cfed1d6556e44a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.inc | 1 +
.../haswell/native_raminit/raminit_main.c | 1 +
.../haswell/native_raminit/raminit_native.h | 57 +++++
.../haswell/native_raminit/spd_bitmunching.c | 206 ++++++++++++++++++
4 files changed, 265 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
index 90af951c5a..ebf7abc6ec 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
@@ -2,3 +2,4 @@
romstage-y += raminit_main.c
romstage-y += raminit_native.c
+romstage-y += spd_bitmunching.c
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 9b42c25b40..2d2cfa48bb 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -20,6 +20,7 @@ struct task_entry {
};
static const struct task_entry cold_boot[] = {
+ { collect_spd_info, true, "PROCSPD", },
};
/* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 885f0184f4..1a0793947e 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -3,6 +3,15 @@
#ifndef HASWELL_RAMINIT_NATIVE_H
#define HASWELL_RAMINIT_NATIVE_H
+#include <device/dram/ddr3.h>
+#include <northbridge/intel/haswell/haswell.h>
+
+#define SPD_LEN 256
+
+/* 8 data lanes + 1 ECC lane */
+#define NUM_LANES 9
+#define NUM_LANES_NO_ECC 8
+
enum raminit_boot_mode {
BOOTMODE_COLD,
BOOTMODE_WARM,
@@ -12,6 +21,8 @@ enum raminit_boot_mode {
enum raminit_status {
RAMINIT_STATUS_SUCCESS = 0,
+ RAMINIT_STATUS_NO_MEMORY_INSTALLED,
+ RAMINIT_STATUS_UNSUPPORTED_MEMORY,
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
};
@@ -21,14 +32,60 @@ enum generic_stepping {
STEPPING_C0 = 3,
};
+struct raminit_dimm_info {
+ spd_raw_data raw_spd;
+ struct dimm_attr_ddr3_st data;
+ uint8_t spd_addr;
+ bool valid;
+};
+
struct sysinfo {
enum raminit_boot_mode bootmode;
enum generic_stepping stepping;
uint32_t cpu; /* CPUID value */
bool dq_pins_interleaved;
+
+ /** TODO: ECC support untested **/
+ bool is_ecc;
+
+ /**
+ * FIXME: LPDDR support is incomplete. The largest chunks are missing,
+ * but some LPDDR-specific variations in algorithms have been handled.
+ * LPDDR-specific functions have stubs which will halt upon execution.
+ */
+ bool lpddr;
+
+ struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS];
+ union dimm_flags_ddr3_st flags;
+ uint16_t cas_supported;
+
+ /* Except for tCK, everything is eventually stored in DCLKs */
+ uint32_t tCK;
+ uint32_t tAA; /* Also known as tCL */
+ uint32_t tWR;
+ uint32_t tRCD;
+ uint32_t tRRD;
+ uint32_t tRP;
+ uint32_t tRAS;
+ uint32_t tRC;
+ uint32_t tRFC;
+ uint32_t tWTR;
+ uint32_t tRTP;
+ uint32_t tFAW;
+ uint32_t tCWL;
+ uint32_t tCMD;
+
+ uint8_t lanes; /* 8 or 9 */
+ uint8_t chanmap;
+ uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */
+ uint8_t rankmap[NUM_CHANNELS];
+ uint8_t rank_mirrored[NUM_CHANNELS];
+ uint32_t channel_size_mb[NUM_CHANNELS];
};
void raminit_main(enum raminit_boot_mode bootmode);
+enum raminit_status collect_spd_info(struct sysinfo *ctrl);
+
#endif
diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
new file mode 100644
index 0000000000..dbe02c72d0
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cbfs.h>
+#include <commonlib/clamp.h>
+#include <console/console.h>
+#include <device/dram/ddr3.h>
+#include <device/smbus_host.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <northbridge/intel/haswell/raminit.h>
+#include <string.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static const uint8_t *get_spd_data_from_cbfs(struct spd_info *spdi)
+{
+ if (!CONFIG(HAVE_SPD_IN_CBFS))
+ return NULL;
+
+ printk(RAM_DEBUG, "SPD index %u\n", spdi->spd_index);
+
+ size_t spd_file_len;
+ uint8_t *spd_file = cbfs_map("spd.bin", &spd_file_len);
+
+ if (!spd_file) {
+ printk(BIOS_ERR, "SPD data not found in CBFS\n");
+ return NULL;
+ }
+
+ if (spd_file_len < ((spdi->spd_index + 1) * SPD_LEN)) {
+ printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n");
+ spdi->spd_index = 0;
+ }
+
+ if (spd_file_len < SPD_LEN) {
+ printk(BIOS_ERR, "Invalid SPD data in CBFS\n");
+ return NULL;
+ }
+
+ return spd_file + (spdi->spd_index * SPD_LEN);
+}
+
+static void get_spd_for_dimm(struct raminit_dimm_info *const dimm, const uint8_t *cbfs_spd)
+{
+ if (dimm->spd_addr == SPD_MEMORY_DOWN) {
+ if (cbfs_spd) {
+ memcpy(dimm->raw_spd, cbfs_spd, SPD_LEN);
+ dimm->valid = true;
+ printk(RAM_DEBUG, "memory-down\n");
+ return;
+ } else {
+ printk(RAM_DEBUG, "memory-down but no CBFS SPD data, ignoring\n");
+ return;
+ }
+ }
+ printk(RAM_DEBUG, "slotted ");
+ const uint8_t spd_mem_type = smbus_read_byte(dimm->spd_addr, SPD_MEMORY_TYPE);
+ if (spd_mem_type != SPD_MEMORY_TYPE_SDRAM_DDR3) {
+ printk(RAM_DEBUG, "and not DDR3, ignoring\n");
+ return;
+ }
+ printk(RAM_DEBUG, "and DDR3\n");
+ if (i2c_eeprom_read(dimm->spd_addr, 0, SPD_LEN, dimm->raw_spd) != SPD_LEN) {
+ printk(BIOS_WARNING, "I2C block read failed, trying SMBus byte reads\n");
+ for (uint32_t i = 0; i < SPD_LEN; i++)
+ dimm->raw_spd[i] = smbus_read_byte(dimm->spd_addr, i);
+ }
+ dimm->valid = true;
+}
+
+static void get_spd_data(struct sysinfo *ctrl)
+{
+ struct spd_info spdi = {0};
+ mb_get_spd_map(&spdi);
+ const uint8_t *cbfs_spd = get_spd_data_from_cbfs(&spdi);
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+ struct raminit_dimm_info *const dimm = &ctrl->dimms[channel][slot];
+ dimm->spd_addr = spdi.addresses[channel + channel + slot];
+ if (!dimm->spd_addr)
+ continue;
+
+ printk(RAM_DEBUG, "CH%uS%u is ", channel, slot);
+ get_spd_for_dimm(dimm, cbfs_spd);
+ }
+ }
+}
+
+static void decode_spd(struct raminit_dimm_info *const dimm)
+{
+ /** TODO: Hook up somewhere, and handle lack of XMP data **/
+ const bool enable_xmp = false;
+ memset(&dimm->data, 0, sizeof(dimm->data));
+ if (enable_xmp)
+ spd_xmp_decode_ddr3(&dimm->data, dimm->raw_spd, DDR3_XMP_PROFILE_1);
+ else
+ spd_decode_ddr3(&dimm->data, dimm->raw_spd);
+
+ if (CONFIG(DEBUG_RAM_SETUP))
+ dram_print_spd_ddr3(&dimm->data);
+}
+
+static enum raminit_status find_common_spd_parameters(struct sysinfo *ctrl)
+{
+ ctrl->cas_supported = 0xffff;
+ ctrl->flags.raw = 0xffffffff;
+
+ ctrl->tCK = 0;
+ ctrl->tAA = 0;
+ ctrl->tWR = 0;
+ ctrl->tRCD = 0;
+ ctrl->tRRD = 0;
+ ctrl->tRP = 0;
+ ctrl->tRAS = 0;
+ ctrl->tRC = 0;
+ ctrl->tRFC = 0;
+ ctrl->tWTR = 0;
+ ctrl->tRTP = 0;
+ ctrl->tFAW = 0;
+ ctrl->tCWL = 0;
+ ctrl->tCMD = 0;
+ ctrl->chanmap = 0;
+
+ bool yes_ecc = false;
+ bool not_ecc = false;
+
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+ ctrl->dpc[channel] = 0;
+ ctrl->rankmap[channel] = 0;
+ ctrl->rank_mirrored[channel] = 0;
+ ctrl->channel_size_mb[channel] = 0;
+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+ struct raminit_dimm_info *const dimm = &ctrl->dimms[channel][slot];
+ if (!dimm->valid)
+ continue;
+
+ printk(RAM_DEBUG, "\nCH%uS%u SPD:\n", channel, slot);
+ decode_spd(dimm);
+
+ ctrl->chanmap |= BIT(channel);
+ ctrl->dpc[channel]++;
+ ctrl->channel_size_mb[channel] += dimm->data.size_mb;
+
+ /* The first rank of a populated slot is always present */
+ const uint8_t rank = slot + slot;
+ assert(dimm->data.ranks);
+ ctrl->rankmap[channel] |= (BIT(dimm->data.ranks) - 1) << rank;
+
+ if (dimm->data.flags.pins_mirrored)
+ ctrl->rank_mirrored[channel] |= BIT(rank + 1);
+
+ /* Find common settings */
+ ctrl->cas_supported &= dimm->data.cas_supported;
+ ctrl->flags.raw &= dimm->data.flags.raw;
+ ctrl->tCK = MAX(ctrl->tCK, dimm->data.tCK);
+ ctrl->tAA = MAX(ctrl->tAA, dimm->data.tAA);
+ ctrl->tWR = MAX(ctrl->tWR, dimm->data.tWR);
+ ctrl->tRCD = MAX(ctrl->tRCD, dimm->data.tRCD);
+ ctrl->tRRD = MAX(ctrl->tRRD, dimm->data.tRRD);
+ ctrl->tRP = MAX(ctrl->tRP, dimm->data.tRP);
+ ctrl->tRAS = MAX(ctrl->tRAS, dimm->data.tRAS);
+ ctrl->tRC = MAX(ctrl->tRC, dimm->data.tRC);
+ ctrl->tRFC = MAX(ctrl->tRFC, dimm->data.tRFC);
+ ctrl->tWTR = MAX(ctrl->tWTR, dimm->data.tWTR);
+ ctrl->tRTP = MAX(ctrl->tRTP, dimm->data.tRTP);
+ ctrl->tFAW = MAX(ctrl->tFAW, dimm->data.tFAW);
+ ctrl->tCWL = MAX(ctrl->tCWL, dimm->data.tCWL);
+ ctrl->tCMD = MAX(ctrl->tCMD, dimm->data.tCMD);
+
+ yes_ecc |= dimm->data.flags.is_ecc;
+ not_ecc |= !dimm->data.flags.is_ecc;
+ }
+ }
+
+ if (!ctrl->chanmap) {
+ printk(BIOS_ERR, "No DIMMs were found\n");
+ return RAMINIT_STATUS_NO_MEMORY_INSTALLED;
+ }
+ if (!ctrl->cas_supported) {
+ printk(BIOS_ERR, "Could not resolve common CAS latency\n");
+ return RAMINIT_STATUS_UNSUPPORTED_MEMORY;
+ }
+ /** TODO: Properly handle ECC support and ECC forced **/
+ if (yes_ecc && not_ecc) {
+ /** TODO: Test if the ECC DIMMs can be operated as non-ECC DIMMs **/
+ printk(BIOS_ERR, "Both ECC and non-ECC DIMMs present, this is unsupported\n");
+ return RAMINIT_STATUS_UNSUPPORTED_MEMORY;
+ }
+ if (yes_ecc)
+ ctrl->lanes = NUM_LANES;
+ else
+ ctrl->lanes = NUM_LANES_NO_ECC;
+
+ ctrl->is_ecc = yes_ecc;
+
+ /** TODO: Complete LPDDR support **/
+ ctrl->lpddr = false;
+
+ return RAMINIT_STATUS_SUCCESS;
+}
+
+enum raminit_status collect_spd_info(struct sysinfo *ctrl)
+{
+ get_spd_data(ctrl);
+ return find_common_spd_parameters(ctrl);
+}
--
2.39.2
config/coreboot/haswell/patches/0011-haswell-NRI-Initialise-MPLL.patch
-346
View File
@@ -1,346 +0,0 @@
From 77a89d55ab7a715dc20c34a6edacaaf781b56087 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 14:36:10 +0200
Subject: [PATCH 11/26] haswell NRI: Initialise MPLL
Add code to initialise the MPLL (Memory PLL). The procedure is similar
to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.inc | 2 +
.../intel/haswell/native_raminit/init_mpll.c | 210 ++++++++++++++++++
.../haswell/native_raminit/io_comp_control.c | 22 ++
.../haswell/native_raminit/raminit_main.c | 1 +
.../haswell/native_raminit/raminit_native.h | 11 +
.../intel/haswell/registers/mchbar.h | 3 +
6 files changed, 249 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/init_mpll.c
create mode 100644 src/northbridge/intel/haswell/native_raminit/io_comp_control.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
index ebf7abc6ec..c125d84f0b 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
@@ -1,5 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-or-later
+romstage-y += init_mpll.c
+romstage-y += io_comp_control.c
romstage-y += raminit_main.c
romstage-y += raminit_native.c
romstage-y += spd_bitmunching.c
diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
new file mode 100644
index 0000000000..2faa183724
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static uint32_t get_mem_multiplier(const struct sysinfo *ctrl)
+{
+ const uint32_t mult = NS2MHZ_DIV256 / (ctrl->tCK * ctrl->base_freq);
+
+ if (ctrl->base_freq == 100)
+ return clamp_u32(7, mult, 12);
+
+ if (ctrl->base_freq == 133)
+ return clamp_u32(3, mult, 10);
+
+ die("Unsupported base frequency\n");
+}
+
+static void normalize_tck(struct sysinfo *ctrl, const bool pll_ref100)
+{
+ /** TODO: Haswell supports up to DDR3-2600 **/
+ if (ctrl->tCK <= TCK_1200MHZ) {
+ ctrl->tCK = TCK_1200MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 1200;
+
+ } else if (ctrl->tCK <= TCK_1100MHZ) {
+ ctrl->tCK = TCK_1100MHZ;
+ ctrl->base_freq = 100;
+ ctrl->mem_clock_mhz = 1100;
+
+ } else if (ctrl->tCK <= TCK_1066MHZ) {
+ ctrl->tCK = TCK_1066MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 1066;
+
+ } else if (ctrl->tCK <= TCK_1000MHZ) {
+ ctrl->tCK = TCK_1000MHZ;
+ ctrl->base_freq = 100;
+ ctrl->mem_clock_mhz = 1000;
+
+ } else if (ctrl->tCK <= TCK_933MHZ) {
+ ctrl->tCK = TCK_933MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 933;
+
+ } else if (ctrl->tCK <= TCK_900MHZ) {
+ ctrl->tCK = TCK_900MHZ;
+ ctrl->base_freq = 100;
+ ctrl->mem_clock_mhz = 900;
+
+ } else if (ctrl->tCK <= TCK_800MHZ) {
+ ctrl->tCK = TCK_800MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 800;
+
+ } else if (ctrl->tCK <= TCK_700MHZ) {
+ ctrl->tCK = TCK_700MHZ;
+ ctrl->base_freq = 100;
+ ctrl->mem_clock_mhz = 700;
+
+ } else if (ctrl->tCK <= TCK_666MHZ) {
+ ctrl->tCK = TCK_666MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 666;
+
+ } else if (ctrl->tCK <= TCK_533MHZ) {
+ ctrl->tCK = TCK_533MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 533;
+
+ } else if (ctrl->tCK <= TCK_400MHZ) {
+ ctrl->tCK = TCK_400MHZ;
+ ctrl->base_freq = 133;
+ ctrl->mem_clock_mhz = 400;
+
+ } else {
+ ctrl->tCK = 0;
+ ctrl->base_freq = 1;
+ ctrl->mem_clock_mhz = 0;
+ return;
+ }
+ if (!pll_ref100 && ctrl->base_freq == 100) {
+ /* Skip unsupported frequency */
+ ctrl->tCK++;
+ normalize_tck(ctrl, pll_ref100);
+ }
+}
+
+#define MIN_CAS 4
+#define MAX_CAS 24
+
+static uint8_t find_compatible_cas(struct sysinfo *ctrl)
+{
+ printk(RAM_DEBUG, "With tCK %u, try CAS: ", ctrl->tCK);
+ const uint8_t cas_lower = MAX(MIN_CAS, DIV_ROUND_UP(ctrl->tAA, ctrl->tCK));
+ const uint8_t cas_upper = MIN(MAX_CAS, 19); /* JEDEC MR0 limit */
+
+ if (!(ctrl->cas_supported >> (cas_lower - MIN_CAS))) {
+ printk(RAM_DEBUG, "DIMMs do not support CAS >= %u\n", cas_lower);
+ ctrl->tCK++;
+ return 0;
+ }
+ for (uint8_t cas = cas_lower; cas <= cas_upper; cas++) {
+ printk(RAM_DEBUG, "%u ", cas);
+ if (ctrl->cas_supported & BIT(cas - MIN_CAS)) {
+ printk(RAM_DEBUG, "OK\n");
+ return cas;
+ }
+ }
+ return 0;
+}
+
+static enum raminit_status find_cas_tck(struct sysinfo *ctrl)
+{
+ /** TODO: Honor all possible PLL_REF100_CFG values **/
+ uint8_t pll_ref100 = (pci_read_config32(HOST_BRIDGE, CAPID0_B) >> 21) & 0x7;
+ printk(RAM_DEBUG, "PLL_REF100_CFG value: 0x%x\n", pll_ref100);
+ printk(RAM_DEBUG, "100MHz reference clock support: %s\n", pll_ref100 ? "yes" : "no");
+
+ uint8_t selected_cas;
+ while (true) {
+ /* Round tCK up so that it is a multiple of either 133 or 100 MHz */
+ normalize_tck(ctrl, pll_ref100);
+ if (!ctrl->tCK) {
+ printk(BIOS_ERR, "Couldn't find compatible clock / CAS settings\n");
+ return RAMINIT_STATUS_MPLL_INIT_FAILURE;
+ }
+ selected_cas = find_compatible_cas(ctrl);
+ if (selected_cas)
+ break;
+
+ ctrl->tCK++;
+ }
+ printk(BIOS_DEBUG, "Found compatible clock / CAS settings\n");
+ printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK);
+ printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", selected_cas);
+ ctrl->multiplier = get_mem_multiplier(ctrl);
+ return RAMINIT_STATUS_SUCCESS;
+}
+
+enum raminit_status initialise_mpll(struct sysinfo *ctrl)
+{
+ if (ctrl->tCK > TCK_400MHZ) {
+ printk(BIOS_ERR, "tCK is too slow. Increasing to 400 MHz as last resort\n");
+ ctrl->tCK = TCK_400MHZ;
+ }
+ while (true) {
+ if (!ctrl->qclkps) {
+ const enum raminit_status status = find_cas_tck(ctrl);
+ if (status)
+ return status;
+ }
+
+ /*
+ * Unlike previous generations, Haswell's MPLL won't shut down if the
+ * requested frequency isn't supported. But we cannot reinitialize it.
+ * Another different thing: MPLL registers are 4-bit instead of 8-bit.
+ */
+
+ /** FIXME: Obtain current clock frequency if we want to skip this **/
+ //if (mchbar_read32(MC_BIOS_DATA) != 0)
+ // break;
+
+ uint32_t mc_bios_req = ctrl->multiplier;
+ if (ctrl->base_freq == 100) {
+ /* Use 100 MHz reference clock */
+ mc_bios_req |= BIT(4);
+ }
+ mc_bios_req |= BIT(31);
+ printk(RAM_DEBUG, "MC_BIOS_REQ = 0x%08x\n", mc_bios_req);
+ printk(BIOS_DEBUG, "MPLL busy... ");
+ mchbar_write32(MC_BIOS_REQ, mc_bios_req);
+
+ for (unsigned int i = 0; i <= 5000; i++) {
+ if (!(mchbar_read32(MC_BIOS_REQ) & BIT(31))) {
+ printk(BIOS_DEBUG, "done in %u us\n", i);
+ break;
+ }
+ udelay(1);
+ }
+ if (mchbar_read32(MC_BIOS_REQ) & BIT(31))
+ printk(BIOS_DEBUG, "did not lock\n");
+
+ /* Verify locked frequency */
+ const uint32_t mc_bios_data = mchbar_read32(MC_BIOS_DATA);
+ printk(RAM_DEBUG, "MC_BIOS_DATA = 0x%08x\n", mc_bios_data);
+ if ((mc_bios_data & 0xf) >= ctrl->multiplier)
+ break;
+
+ printk(BIOS_DEBUG, "Retrying at a lower frequency\n\n");
+ ctrl->tCK++;
+ }
+ if (!ctrl->mem_clock_mhz) {
+ printk(BIOS_ERR, "Could not program MPLL frequency\n");
+ return RAMINIT_STATUS_MPLL_INIT_FAILURE;
+ }
+ printk(BIOS_DEBUG, "MPLL frequency is set to: %u MHz ", ctrl->mem_clock_mhz);
+ ctrl->mem_clock_fs = 1000000000 / ctrl->mem_clock_mhz;
+ printk(BIOS_DEBUG, "(period: %u femtoseconds)\n", ctrl->mem_clock_fs);
+ ctrl->qclkps = ctrl->mem_clock_fs / 2000;
+ printk(BIOS_DEBUG, "Quadrature clock period: %u picoseconds\n", ctrl->qclkps);
+ return wait_for_first_rcomp();
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
new file mode 100644
index 0000000000..7e96c08938
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/clamp.h>
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+enum raminit_status wait_for_first_rcomp(void)
+{
+ struct stopwatch timer;
+ stopwatch_init_msecs_expire(&timer, 2000);
+ do {
+ if (mchbar_read32(RCOMP_TIMER) & BIT(16))
+ return RAMINIT_STATUS_SUCCESS;
+
+ } while (!stopwatch_expired(&timer));
+ printk(BIOS_ERR, "Timed out waiting for RCOMP to complete\n");
+ return RAMINIT_STATUS_POLL_TIMEOUT;
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 2d2cfa48bb..09545422c0 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -21,6 +21,7 @@ struct task_entry {
static const struct task_entry cold_boot[] = {
{ collect_spd_info, true, "PROCSPD", },
+ { initialise_mpll, true, "INITMPLL", },
};
/* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 1a0793947e..a54581abc7 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -23,6 +23,8 @@ enum raminit_status {
RAMINIT_STATUS_SUCCESS = 0,
RAMINIT_STATUS_NO_MEMORY_INSTALLED,
RAMINIT_STATUS_UNSUPPORTED_MEMORY,
+ RAMINIT_STATUS_MPLL_INIT_FAILURE,
+ RAMINIT_STATUS_POLL_TIMEOUT,
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
};
@@ -82,10 +84,19 @@ struct sysinfo {
uint8_t rankmap[NUM_CHANNELS];
uint8_t rank_mirrored[NUM_CHANNELS];
uint32_t channel_size_mb[NUM_CHANNELS];
+
+ uint8_t base_freq; /* Memory base frequency, either 100 or 133 MHz */
+ uint32_t multiplier;
+ uint32_t mem_clock_mhz;
+ uint32_t mem_clock_fs; /* Memory clock period in femtoseconds */
+ uint32_t qclkps; /* Quadrature clock period in picoseconds */
};
void raminit_main(enum raminit_boot_mode bootmode);
enum raminit_status collect_spd_info(struct sysinfo *ctrl);
+enum raminit_status initialise_mpll(struct sysinfo *ctrl);
+
+enum raminit_status wait_for_first_rcomp(void);
#endif
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
index 5610e7089a..45f8174995 100644
--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
@@ -13,6 +13,8 @@
#define MC_INIT_STATE_G 0x5030
#define MRC_REVISION 0x5034 /* MRC Revision */
+#define RCOMP_TIMER 0x5084
+
#define MC_LOCK 0x50fc /* Memory Controller Lock register */
#define GFXVTBAR 0x5400 /* Base address for IGD */
@@ -61,6 +63,7 @@
#define BIOS_RESET_CPL 0x5da8 /* 8-bit */
+#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */
#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */
#define SAPMCTL 0x5f00
--
2.39.2
config/coreboot/haswell/patches/0012-haswell-NRI-Post-process-selected-timings.patch
-249
View File
@@ -1,249 +0,0 @@
From faabed9ca8974b2e7192c55b59a9d28d75e72df6 Mon Sep 17 00:00:00 2001
From: Angel Pons <th3fanbus@gmail.com>
Date: Sat, 7 May 2022 16:29:55 +0200
Subject: [PATCH 12/26] haswell NRI: Post-process selected timings
Once the MPLL has been initialised, convert the timings from the SPD to
be in DCLKs, which is what the hardware expects. In addition, calculate
the values for tREFI and tXP.
Change-Id: Id02caf858f75b9e08016762b3aefda282b274386
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
.../intel/haswell/native_raminit/Makefile.inc | 1 +
.../haswell/native_raminit/lookup_timings.c | 62 +++++++++++
.../haswell/native_raminit/raminit_main.c | 1 +
.../haswell/native_raminit/raminit_native.h | 8 ++
.../haswell/native_raminit/spd_bitmunching.c | 100 ++++++++++++++++++
5 files changed, 172 insertions(+)
create mode 100644 src/northbridge/intel/haswell/native_raminit/lookup_timings.c
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
index c125d84f0b..2769e0bbb4 100644
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
@@ -1,5 +1,6 @@
## SPDX-License-Identifier: GPL-2.0-or-later
+romstage-y += lookup_timings.c
romstage-y += init_mpll.c
romstage-y += io_comp_control.c
romstage-y += raminit_main.c
diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
new file mode 100644
index 0000000000..038686c844
--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/clamp.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+struct timing_lookup {
+ uint32_t clock;
+ uint32_t value;
+};
+
+static uint32_t lookup_timing(
+ const uint32_t mem_clock_mhz,
+ const struct timing_lookup *const lookup,
+ const size_t length)
+{
+ /* Fall back to the last index */
+ size_t i;
+ for (i = 0; i < length - 1; i++) {
+ /* Account for imprecise frequency values */
+ if ((mem_clock_mhz - 5) <= lookup[i].clock)
+ break;
+ }
+ return lookup[i].value;
+}
+
+static const uint32_t fmax = UINT32_MAX;
+
+uint8_t get_tCWL(const uint32_t mem_clock_mhz)
+{
+ const struct timing_lookup lut[] = {
+ { 400, 5 },
+ { 533, 6 },
+ { 666, 7 },
+ { 800, 8 },
+ { 933, 9 },
+ { 1066, 10 },
+ { 1200, 11 },
+ { fmax, 12 },
+ };
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+/* tREFI = 7800 ns * DDR MHz */
+uint32_t get_tREFI(const uint32_t mem_clock_mhz)
+{
+ return (mem_clock_mhz * 7800) / 1000;
+}
+
+uint32_t get_tXP(const uint32_t mem_clock_mhz)
+{
+ const struct timing_lookup lut[] = {
+ { 400, 3 },
+ { 666, 4 },
+ { 800, 5 },
+ { 933, 6 },
+ { 1066, 7 },
+ { fmax, 8 },
+ };
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
index 09545422c0..5f2be980d4 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
@@ -22,6 +22,7 @@ struct task_entry {
static const struct task_entry cold_boot[] = {
{ collect_spd_info, true, "PROCSPD", },
{ initialise_mpll, true, "INITMPLL", },
+ { convert_timings, true, "CONVTIM", },
};
/* Return a generic stepping value to make stepping checks simpler */
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index a54581abc7..01e5ed1bd6 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -78,6 +78,9 @@ struct sysinfo {
uint32_t tCWL;
uint32_t tCMD;
+ uint32_t tREFI;
+ uint32_t tXP;
+
uint8_t lanes; /* 8 or 9 */
uint8_t chanmap;
uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */
@@ -96,7 +99,12 @@ void raminit_main(enum raminit_boot_mode bootmode);
enum raminit_status collect_spd_info(struct sysinfo *ctrl);
enum raminit_status initialise_mpll(struct sysinfo *ctrl);
+enum raminit_status convert_timings(struct sysinfo *ctrl);
enum raminit_status wait_for_first_rcomp(void);
+uint8_t get_tCWL(uint32_t mem_clock_mhz);
+uint32_t get_tREFI(uint32_t mem_clock_mhz);
+uint32_t get_tXP(uint32_t mem_clock_mhz);
+
#endif
diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
index dbe02c72d0..becbea0725 100644
--- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
@@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl)
get_spd_data(ctrl);
return find_common_spd_parameters(ctrl);
}
+
+#define MIN_CWL 5
+#define MAX_CWL 12
+
+/* Except for tCK, hardware expects all timing values in DCLKs, not nanoseconds */
+enum raminit_status convert_timings(struct sysinfo *ctrl)
+{
+ /*
+ * Obtain all required timing values, in DCLKs.
+ */
+
+ /* Convert primary timings from nanoseconds to DCLKs */
+ ctrl->tAA = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
+ ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK);
+ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
+ ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
+ ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK);
+ ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
+ ctrl->tRC = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK);
+ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
+ ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
+ ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
+ ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
+ ctrl->tCWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
+ ctrl->tCMD = DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK);
+
+ /* Constrain primary timings to hardware limits */
+ /** TODO: complain when clamping? **/
+ ctrl->tAA = clamp_u32(4, ctrl->tAA, 24);
+ ctrl->tWR = clamp_u32(5, ctrl->tWR, 16);
+ ctrl->tRCD = clamp_u32(4, ctrl->tRCD, 20);
+ ctrl->tRRD = clamp_u32(4, ctrl->tRRD, 65535);
+ ctrl->tRP = clamp_u32(4, ctrl->tRP, 15);
+ ctrl->tRAS = clamp_u32(10, ctrl->tRAS, 40);
+ ctrl->tRC = clamp_u32(1, ctrl->tRC, 4095);
+ ctrl->tRFC = clamp_u32(1, ctrl->tRFC, 511);
+ ctrl->tWTR = clamp_u32(4, ctrl->tWTR, 10);
+ ctrl->tRTP = clamp_u32(4, ctrl->tRTP, 15);
+ ctrl->tFAW = clamp_u32(10, ctrl->tFAW, 54);
+
+ /** TODO: Honor tREFI from XMP **/
+ ctrl->tREFI = get_tREFI(ctrl->mem_clock_mhz);
+ ctrl->tXP = get_tXP(ctrl->mem_clock_mhz);
+
+ /*
+ * Check some values, and adjust them if necessary.
+ */
+
+ /* If tWR cannot be written into DDR3 MR0, adjust it */
+ switch (ctrl->tWR) {
+ case 9:
+ case 11:
+ case 13:
+ case 15:
+ ctrl->tWR++;
+ }
+
+ /* If tCWL is not supported or unspecified, look up a reasonable default */
+ if (ctrl->tCWL < MIN_CWL || ctrl->tCWL > MAX_CWL)
+ ctrl->tCWL = get_tCWL(ctrl->mem_clock_mhz);
+
+ /* This is needed to support ODT properly on 2DPC */
+ if (ctrl->tAA - ctrl->tCWL > 4)
+ ctrl->tCWL = ctrl->tAA - 4;
+
+ /* If tCMD is invalid, use a guesstimate default */
+ if (!ctrl->tCMD) {
+ ctrl->tCMD = MAX(ctrl->dpc[0], ctrl->dpc[1]);
+ printk(RAM_DEBUG, "tCMD was zero, picking a guesstimate value\n");
+ }
+ ctrl->tCMD = clamp_u32(1, ctrl->tCMD, 3);
+
+ /*
+ * Print final timings.
+ */
+
+ /* tCK is special */
+ printk(BIOS_DEBUG, "Selected tCK : %u ns\n", ctrl->tCK / 256);
+
+ /* Primary timings */
+ printk(BIOS_DEBUG, "Selected tAA : %uT\n", ctrl->tAA);
+ printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR);
+ printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD);
+ printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD);
+ printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP);
+ printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS);
+ printk(BIOS_DEBUG, "Selected tRC : %uT\n", ctrl->tRC);
+ printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC);
+ printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR);
+ printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP);
+ printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW);
+ printk(BIOS_DEBUG, "Selected tCWL : %uT\n", ctrl->tCWL);
+ printk(BIOS_DEBUG, "Selected tCMD : %uT\n", ctrl->tCMD);
+
+ /* Derived timings */
+ printk(BIOS_DEBUG, "Selected tREFI : %uT\n", ctrl->tREFI);
+ printk(BIOS_DEBUG, "Selected tXP : %uT\n", ctrl->tXP);
+
+ return RAMINIT_STATUS_SUCCESS;
+}
--
2.39.2
config/coreboot/haswell/patches/0013-haswell-NRI-Configure-initial-MC-settings.patch
-1593
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