update .gitignore

Signed-off-by: Leah Rowe <leah@libreboot.org>

.gitcheck

@@ -0,0 +1,82 @@
+#!/usr/bin/env sh
+# SPDX-FileCopyrightText: 2022 Caleb La Grange <thonkpeasant@protonmail.com>
+# SPDX-FileCopyrightText: 2023 Leah Rowe <leah@libreboot.org>
+# SPDX-License-Identifier: GPL-3.0-only
+
+git_name="lbmkplaceholder"
+git_email="placeholder@lbmkplaceholder.com"
+
+main()
+{
+	if [ $# -gt 0 ]; then
+		if [ "${1}" = "clean" ]; then
+			clean > /dev/null 2> /dev/null
+		else
+			printf "%s: Unsupported argument\n" $0
+			exit 1
+		fi
+	else
+		set_placeholders > /dev/null 2> /dev/null
+	fi
+}
+
+set_placeholders()
+{
+	set_git_credentials
+
+	# Check coreboot as well to prevent errors during building
+	if [ ! -d coreboot ]; then
+		return
+	fi
+	for x in coreboot/*; do
+		if [ ! -d "${x}" ]; then
+			continue
+		fi
+		(
+		cd "${x}"
+		set_git_credentials
+		)
+	done
+}
+
+set_git_credentials()
+{
+	# Check if username and or email is set.
+	if ! git config user.name || git config user.email ; then
+		git config user.name \
+				|| git config user.name "${git_name}"
+		git config user.email \
+				|| git config user.email "${git_email}"
+	fi
+}
+
+clean()
+{
+	unset_placeholders
+
+	if [ ! -d coreboot ]; then
+		return
+	fi
+	for x in coreboot/*; do
+		if [ ! -d "${x}" ]; then
+			continue
+		fi
+		(
+		cd "${x}"
+		unset_placeholders
+		)
+	done
+}
+
+unset_placeholders()
+{
+	if [ "$(git config user.name)" = "${git_name}" ]; then
+		git config --unset user.name
+	fi
+
+	if [ "$(git config user.email)" = "${git_email}" ]; then
+		git config --unset user.email
+	fi
+}
+
+main $@

.gitignore

@@ -1,6 +1,17 @@
 *~
+*.o
+/lbmk.err.log
+/cbutils/
+/pciroms/
+/util/e6400-flash-unlock/e6400_flash_unlock
+/util/ich9utils/*.bin
+/util/ich9utils/demefactory
+/util/ich9utils/ich9deblob
+/util/ich9utils/ich9show
+/util/ich9utils/ich9gen
 /TODO
-/ich9utils/
+/bios_extract/
+/ec/
 /tmp/
 /payload/
 /me_cleaner/
@@ -21,6 +32,7 @@
 /grub/
 /memtest86plus/
 /seabios/
+/u-boot/
 /bin/
 /release/
 /descriptors/
@@ -28,3 +40,8 @@
 /push
 /version
 /versiondate
+/blobs/app/
+/blobs/cache/
+*me.bin
+/mrc/
+/util/nvmutil/nvm

Makefile

@@ -1,10 +1,13 @@
 # 
-# Makefile for compatibility purposes
-# You can use this, but it's recommended to run build system commands directly
+# Makefile for meme purposes
+# You can use this, but it just runs lbmk commands.
 #
-# See docs/maintain/ and docs/git/ for information about the build system
+# See docs/maintain/ and docs/git/ for information about the build system:
+# https://libreboot.org/docs/maintain/
+# https://libreboot.org/docs/build/
 #
-# Copyright (C) 2020, 2021 Leah Rowe <info@minifree.org>
+# Copyright (C) 2020, 2021, 2023 Leah Rowe <info@minifree.org>
+# Copyright (C) 2022 Ferass El Hafidi <vitali64pmemail@protonmail.com>
 #
 # This program is free software: you can redistribute it and/or modify
 # it under the terms of the GNU General Public License as published by
@@ -20,9 +23,13 @@
 # along with this program.  If not, see <http://www.gnu.org/licenses/>.
 #
 
-.PHONY: all download modules ich9m-descriptors payloads roms release clean \
-	crossgcc-clean install-dependencies-ubuntu install-dependencies-debian \
-	install-dependencies-arch install-dependencies-void
+.POSIX:
+
+#.PHONY: all check download modules ich9m-descriptors payloads roms release \
+#	clean crossgcc-clean install-dependencies-ubuntu \
+#	install-dependencies-debian install-dependencies-arch \
+#	install-dependencies-void install-dependencies-fedora38 \
+#	install-dependencies-parabola
 
 all: roms
 
@@ -54,6 +61,8 @@ clean:
 	./build clean grub
 	./build clean memtest86plus
 	./build clean rom_images
+	./build clean u-boot
+	./build clean bios_extract
 
 crossgcc-clean:
 	./build clean crossgcc
@@ -69,3 +78,9 @@ install-dependencies-arch:
 
 install-dependencies-void:
 	./build dependencies void
+
+install-dependencies-fedora38:
+	./build dependencies fedora38
+
+install-dependencies-parabola:
+	./build dependencies parabola

README.md

@@ -1,109 +1,85 @@
-Free your BIOS today! GNU GPL style
-===================================
+Libreboot
+=========
 
 Find libreboot documentation at <https://libreboot.org/>
 
-Libreboot is
-[freedom-respecting](https://www.gnu.org/philosophy/free-sw.html)
-*boot firmware* that initializes the hardware (e.g.
-memory controller, CPU, peripherals) in your computer so that software can run.
-Libreboot then starts a bootloader to load your operating system. It replaces the
-proprietary BIOS/UEFI firmware typically found on a computer. Libreboot is
-compatible with specific computer models that use the Intel/AMD x86
-architecture. Libreboot works well with GNU+Linux and BSD
-operating systems. User support is available
-at [\#libreboot](https://webchat.freenode.net/?channels=libreboot) on Freenode
-IRC.
-
-Libreboot is a *Free Software* project, but can be considered Open Source.
-[The GNU website](https://www.gnu.org/philosophy/open-source-misses-the-point.en.html)
-teaches why you should call it Free Software instead; alternatively, you may
-call it libre software.
-
-Libreboot uses [coreboot](https://www.coreboot.org/) for hardware initialization.
-However, *coreboot* is notoriously difficult to compile and install for most
-non-technical users. There are many complicated configuration steps required,
-and coreboot by itself is useless; coreboot only handles basic hardware
-initialization, and then jumps to a separate *payload* program. The payload
-program can be anything, for example a Linux kernel, bootloader (such as
-GNU GRUB), UEFI implementation (such as Tianocore) or BIOS implementation
-(such as SeaBIOS). While not quite as complicated as building a GNU+Linux
-distribution from scratch, it may aswell be as far as most non-technical users
-are concerned.
-
-Libreboot solves this problem in a novel way:
-Libreboot is a *coreboot distribution* much like Debian is a *GNU+Linux
-distribution*. Libreboot provides an *automated build system* that downloads,
-patches (where necessary) and compiles coreboot, GNU GRUB, various payloads and
-all other software components needed to build a complete, working *ROM image*
-that you can install to replace your current BIOS/UEFI firmware, much like a
-GNU+Linux distribution (e.g. Debian) provides an ISO image that you can use to
-replace your current operating system (e.g. Windows).
-
-Information about who works on Libreboot, and who runs the project, can be
-found on the [who page](https://libreboot.org/who.html) page.
+The `libreboot` project provides
+[libre](https://libreboot.org/freedom-status.html) *boot
+firmware* that initializes the hardware (e.g. memory controller, CPU,
+peripherals) on specific Intel/AMD x86 and ARM targets, which
+then starts a bootloader for your operating system. Linux/BSD are
+well-supported. It replaces proprietary BIOS/UEFI firmware. Help is available
+via [\#libreboot IRC](https://web.libera.chat/#libreboot)
+on [Libera](https://libera.chat/) IRC.
 
 Why use Libreboot?
 ==================
 
-[Free software](https://www.gnu.org/philosophy/free-sw.html) is important for
-the same reason that education is important.
-All children and adults alike should be entitled to a good education.
-Knowledge begs to be free! In the context of computing, this means that the
-source code should be fully available to study, and use in whatever way you
-see fit. In the context of computer hardware, this means that
-[Right to Repair](https://yewtu.be/watch?v=Npd_xDuNi9k)
-should be universal, with full access to documents such as the schematics and
-boardview files.
+Why should you use *libreboot*?
+----------------------------
 
-**[The four freedoms are paramount!](https://www.gnu.org/philosophy/free-sw.html)**
+Libreboot gives you freedoms that you otherwise can't get with most other
+boot firmware. It's extremely powerful and configurable for many use cases.
 
-You have rights. The right to privacy, freedom of thought, freedom
-of speech and the right to read. In the context of computing, that means anyone
-can use [free software](https://www.gnu.org/philosophy/free-sw.html). Simply
-speaking, free software is software that is under the direct sovereignty of the
-user and, more importantly, the collective that is the *community*. Libreboot
-is dedicated to the Free Software community, with the aim of making free software
-at a *low level* more accessible to non-technical people.
+You have rights. The right to privacy, freedom of thought, freedom of speech
+and the right to read. In this context, Libreboot gives you these rights.
+Your freedom matters.
+[Right to repair](https://vid.puffyan.us/watch?v=Npd_xDuNi9k) matters.
+Many people use proprietary (non-libre)
+boot firmware, even if they use [a libre OS](https://www.openbsd.org/).
+Proprietary firmware often contains backdoors (more info on the FAQ), and it
+and can be buggy. The libreboot project was founded in in December 2013,
+with the express purpose of making coreboot firmware accessible for
+non-technical users.
 
-Many people use [proprietary](https://www.gnu.org/philosophy/proprietary.html)
-boot firmware, even if they use GNU+Linux. Non-free boot firmware often
-contains backdoors, can be slow and have severe
-bugs. Development and support can be abandoned at any time. By contrast,
-Libreboot is a free software project, where anyone can contribute or inspect
-its code.
+The `libreboot` project uses [coreboot](https://www.coreboot.org/) for [hardware
+initialisation](https://doc.coreboot.org/getting_started/architecture.html).
+Coreboot is notoriously difficult to install for most non-technical users; it
+handles only basic initialization and jumps to a separate
+[payload](https://doc.coreboot.org/payloads.html) program (e.g.
+[GRUB](https://www.gnu.org/software/grub/),
+[Tianocore](https://www.tianocore.org/)), which must also be configured.
+*The libreboot software solves this problem*; it is a *coreboot distribution* with
+an automated build system (named *lbmk*) that builds complete *ROM images*, for
+more robust installation. Documentation is provided.
 
-Libreboot is faster, more secure and more reliable than most non-free
-firmware. Libreboot provides many advanced features, like encrypted
-/boot/, GPG signature checking before booting a Linux kernel and more!
-Libreboot gives *you* control over *your* computing.
+How does Libreboot differ from coreboot?
+========================================
+
+In the same way that *Debian* is a GNU+Linux distribution, `libreboot` is
+a *coreboot distribution*. If you want to build a ROM image from scratch, you
+otherwise have to perform expert-level configuration of coreboot, GRUB and
+whatever other software you need, to prepare the ROM image. With *libreboot*,
+you can literally download from Git or a source archive, and run `make`, and it
+will build entire ROM images. An automated build system, named `lbmk`
+(Libreboot MaKe), builds these ROM images automatically, without any user input
+or intervention required. Configuration has already been performed in advance.
+
+If you were to build regular coreboot, without using libreboot's automated
+build system, it would require a lot more intervention and decent technical
+knowledge to produce a working configuration.
+
+Regular binary releases of `libreboot` provide these
+ROM images pre-compiled, and you can simply install them, with no special
+knowledge or skill except the ability to follow installation instructions
+and run commands BSD/Linux.
 
 Project goals
--------------
+=============
 
--   *Recommend and distribute only free software*. Coreboot
-    distributes certain pieces of proprietary software which is needed
-    on some systems. Examples can include things like CPU microcode
-    updates, memory initialization blobs and so on. The coreboot project
-    sometimes recommends adding more blobs which it does not distribute,
-    such as the Video BIOS or Intel's *Management Engine*. However, a
-    lot of dedicated and talented individuals in coreboot work hard to
-    replace these blobs whenever possible.
--   *Support as much hardware as possible!* Libreboot supports less
-    hardware than coreboot, because most systems from coreboot still
-    require certain proprietary software to work properly. Libreboot is
-    an attempt to support as much hardware as possible, without any
-    proprietary software.
+-   *Support as much hardware as possible!* Libreboot aims to eventually
+    have *maintainers* for every board supported by coreboot, at every
+    point in time.
 -   *Make coreboot easy to use*. Coreboot is notoriously difficult
     to install, due to an overall lack of user-focused documentation
     and support. Most people will simply give up before attempting to
-    install coreboot.
+    install coreboot. Libreboot's automated build system and user-friendly
+    installation instructions solves this problem.
 
 Libreboot attempts to bridge this divide by providing a build system
 automating much of the coreboot image creation and customization.
 Secondly, the project produces documentation aimed at non-technical users.
-Thirdly, the project attempts to provide excellent user support via mailing
-lists and IRC.
+Thirdly, the project attempts to provide excellent user support via IRC.
 
 Libreboot already comes with a payload (GRUB), flashrom and other
 needed parts. Everything is fully integrated, in a way where most of
@@ -123,39 +99,25 @@ re-bases on the latest version of coreboot, with the number of custom
 patches in use minimized. Tested, *stable* (static) releases are then provided
 in Libreboot, based on specific coreboot revisions.
 
-Coreboot is not entirely free software. It has binary blobs in it for some
-platforms. What Libreboot does is download several revisions of coreboot, for
-different boards, and *de-blob* those coreboot revisions. This is done using
-the *linux-libre* deblob scripts, to find binary blobs in coreboot.
+How to help
+===========
 
-All new coreboot development should be done in coreboot (upstream), not
-libreboot! Libreboot is about deblobbing and packaging coreboot in a
-user-friendly way, where most work is already done for the user.
+You can check bugs listed on
+the [bug tracker](https://codeberg.org/libreboot/lbmk/issues).
 
-For example, if you wanted to add a new board to libreboot, you should
-add it to coreboot first. Libreboot will automatically receive your code
-at a later date, when it updates itself.
+If you spot a bug and have a fix, the website has instructions for how to send
+patches, and you can also report it. Also, this entire website is
+written in Markdown and hosted in a [separate
+repository](https://codeberg.org/libreboot/lbwww) where you can send patches.
 
-The deblobbed coreboot tree used in libreboot is referred to as
-*coreboot-libre*, to distinguish it as a component of *libreboot*.
+Any and all development discussion and user support are all done on the IRC
+channel. More information is on the contact page of libreboot.org.
 
-A coreboot *fork* is planned for the future. Nowadays, coreboot drops support
-for boards that are "unmaintained", which in some cases just means that nobody
-submitted a new status update (to the *board-status* repository), so nowadays
-Libreboot must maintain multiple versions of coreboot. This is unsustainable,
-so a fork is planned, re-adding all of the deleted boards, backporting newer
-coreboot features and, possibly, having support for those boards re-merged
-upstream, where coreboot and the fork will share code back and forth. As of
-27 April 2021, work on this fork has not yet begun.
+LICENSE FOR THIS README
+=======================
 
-LICENSE FOR THIS README:
-GNU Free Documentation License 1.3 as published by the Free Software Foundation,
-with no invariant sections, no front cover texts and no back cover texts. If
-you wish it, you may use a later version of the GNU Free Documentation License
-as published by the Free Software Foundation.
+It's just a README file. This README file is released under the terms of the
+Creative Commons Zero license, version 1.0 of the license, which you can
+read here:
 
-Copy of the GNU Free Documentation License v1.3 here:
-<https://www.gnu.org/licenses/fdl-1.3.en.html>
-
-Info about Free Software Foundation:
-<https://www.fsf.org/>
+<https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt>

blobutil

@@ -0,0 +1 @@
+lbmk

build

@@ -1,107 +0,0 @@
-#!/usr/bin/env bash
-
-#  generic build script, for building components (all of them)
-#
-#	Copyright (C) 2014, 2015, 2020, 2021 Leah Rowe <info@minifree.org>
-#	Copyright (C) 2015 Patrick "P. J." McDermott <pj@pehjota.net>
-#	Copyright (C) 2015, 2016 Klemens Nanni <contact@autoboot.org>
-#
-#	This program is free software: you can redistribute it and/or modify
-#	it under the terms of the GNU General Public License as published by
-#	the Free Software Foundation, either version 3 of the License, or
-#	(at your option) any later version.
-#
-#	This program is distributed in the hope that it will be useful,
-#	but WITHOUT ANY WARRANTY; without even the implied warranty of
-#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#	GNU General Public License for more details.
-#
-#	You should have received a copy of the GNU General Public License
-#	along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-[ "x${DEBUG+set}" = 'xset' ] && set -v
-set -u -e
-
-projectname="$(cat projectname)"
-
-build=./resources/scripts/build
-
-listmodes() {
-	for mode in "${build}"/*; do
-		printf '%s\n' "${mode##*/}"
-	done
-}
-
-# Takes exactly one mode as parameter
-listoptions() {
-	for option in "${build}"/"${1}"/*; do
-		printf '%s\n' "${option##*/}"
-	done
-}
-
-help() {
-	cat <<- EOF
-	USAGE:	./build <MODE> <OPTION>
-
-	possible values for 'mode':
-	$(listmodes)
-
-	Example:	./build module all
-	Example:	./build module flashrom [static]
-	Example:	./build roms withgrub
-	Example:	./build clean all
-
-	Refer to the ${projectname} documentation for more information.
-	EOF
-}
-
-die() {
-	printf 'Error: %s\n' "${@}" 1>&2
-	exit 1
-}
-
-if [ $# -lt 1 ]; then
-	die "Wrong number of arguments specified. See './build help'."
-fi
-
-mode="${1}"
-
-if [ "${mode}" != "dependencies" ]; then
-	./resources/scripts/misc/versioncheck
-fi
-
-[ "${mode}" = help ] && help && exit 0
-
-if [ $# -gt 1 ]; then
-
-	option="${2}"
-	shift 2
-
-	case "${option}" in
-		list)
-			printf "Available options for mode '%s':\n\n" "${mode}"
-			listoptions "${mode}"
-			;;  
-		all)
-			for option in $(listoptions "${mode}"); do
-				"${build}"/"${mode}"/"${option}" $@
-			done
-			;;
-		*)
-			if [ -d "${build}"/"${mode}"/ ]; then
-				if [ -f "${build}"/"${mode}"/"${option}" ]; then
-					"${build}"/"${mode}"/"${option}" $@
-				else
-					help
-					die "Invalid option for '${mode}'. See './build ${mode} list'."
-				fi
-			else
-				help
-				die "Invalid mode '${mode}'. See './build help'."
-			fi
-	esac
-else
-	help
-	exit 0
-fi

build

@@ -0,0 +1 @@
+lbmk

download

@@ -1,111 +0,0 @@
-#!/usr/bin/env bash
-
-# Generic script for downloading programs used by the build system
-#
-#	Copyright (C) 2014, 2015, 2020, 2021 Leah Rowe <info@minifree.org>
-#	Copyright (C) 2015 Patrick "P. J." McDermott <pj@pehjota.net>
-#	Copyright (C) 2015, 2016 Klemens Nanni <contact@autoboot.org>
-#
-#	This program is free software: you can redistribute it and/or modify
-#	it under the terms of the GNU General Public License as published by
-#	the Free Software Foundation, either version 3 of the License, or
-#	(at your option) any later version.
-#
-#	This program is distributed in the hope that it will be useful,
-#	but WITHOUT ANY WARRANTY; without even the implied warranty of
-#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-#	GNU General Public License for more details.
-#
-#	You should have received a copy of the GNU General Public License
-#	along with this program.  If not, see <http://www.gnu.org/licenses/>.
-#
-
-[ "x${DEBUG+set}" = 'xset' ] && set -v
-set -u -e
-
-./resources/scripts/misc/versioncheck
-
-# set this when you want to modify each coreboot tree
-# for example, you want to test custom patches
-# NODELETE= ./download coreboot
-deleteblobs="true"
-[ "x${NODELETE+set}" = 'xset' ] && deleteblobs="false"
-
-rm -f "build_error"
-
-download=resources/scripts/download
-
-listprograms() {
-	for program in "${download}"/*; do
-		printf '%s\n' "${program##*/}"
-	done
-}
-
-help() {
-	cat <<- EOF
-	USAGE:	./download <PROGRAM> <OPTIONS>
-
-	possible values for 'program':
-	$(listprograms)
-
-	Example:	./download flashrom
-	Example:	./download coreboot
-
-	Some program options allow for additional parameters:
-	Example:	./download coreboot default
-	Example:	./download coreboot x60
-
-	Each program download script should work without extra paramaters, but
-	they can use them. For instance, './download coreboot' will download all
-	coreboot trees by default, but './download coreboot x60' will only download
-	the coreboot tree required for the target: x60
-
-	Refer to the documentation for more information.
-	EOF
-}
-
-die() {
-	printf 'Error: %s\n' "${@}" 1>&2
-	exit 1
-}
-
-if [ $# -lt 1 ]; then
-	help
-	die "Please specify arguments."
-fi
-
-program="${1}"
-shift 1
-[ "${program}" = help ] && help && exit 0
-
-if [ "${program}" = "all" ]; then
-	for downloadProgram in ${download}/*; do
-		if [ -f "${downloadProgram}" ]; then
-			if [ "${deleteblobs}" = "false" ]; then
-				NODELETE= "${downloadProgram}"
-			else
-				"${downloadProgram}"
-			fi
-		fi
-	done
-	exit 0
-elif [ ! -f "${download}/${program}" ]; then
-	help
-	die "Invalid argument '${program}'. See: './download help'."
-fi
-
-if [ $# -lt 1 ]; then	
-	if [ "${deleteblobs}" = "false" ]; then
-		NODELETE= "${download}/${program}"
-	else
-		"${download}/${program}"
-	fi
-else	
-	if [ "${deleteblobs}" = "false" ]; then
-		NODELETE= "${download}/${program}" $@
-	else
-		"${download}/${program}" $@
-	fi
-fi
-
-exit 0

download

@@ -0,0 +1 @@
+lbmk

gitclone

@@ -0,0 +1,122 @@
+#!/usr/bin/env sh
+
+# SPDX-FileCopyrightText: 2022 Caleb La Grange <thonkpeasant@protonmail.com>
+# SPDX-FileCopyrightText: 2022 Ferass El Hafidi <vitali64pmemail@protonmail.com>
+# SPDX-FileCopyrightText: 2023 Leah Rowe <leah@libreboot.org>
+# SPDX-License-Identifier: GPL-3.0-only
+
+name=""
+revision=""
+location=""
+url=""
+bkup_url=""
+tmp_dir=""
+
+main()
+{
+	if [ -z "${1+x}" ]; then
+		err 'Error: name not set'
+	fi
+
+	name=${1}
+
+	read_config
+	verify_config
+
+	clone_project
+
+	# clean in case of failure
+	rm -rf ${tmp_dir} >/dev/null 2>&1 || exit 1
+}
+
+read_config()
+{
+	awkstr=" /\{.*${name}.*}{/ {flag=1;next} /\}/{flag=0} flag { print }"
+	while read -r line ; do
+		set ${line} >/dev/null 2>&1
+		case ${line} in
+			rev:*)
+			revision=${2}
+			;;
+			loc:*)
+			location=${2}
+			;;
+			url:*)
+			url=${2}
+			;;
+			bkup_url:*)
+			bkup_url=${2}
+			;;
+		esac
+	done << EOF
+	$(eval "awk '${awkstr}' resources/git/revisions")
+EOF
+}
+
+verify_config()
+{
+	if [ -z "${revision+x}" ]; then
+		err 'Error: revision not set'
+	elif [ -z "${location+x}" ]; then
+		err 'Error: location not set'
+	elif [ -z "${url+x}" ]; then
+		err 'Error: url not set'
+	fi
+}
+
+clone_project()
+{
+	tmp_dir=$(mktemp -dt "${name}_XXXXX")
+
+	git clone ${url} ${tmp_dir} || git clone ${bkup_url} ${tmp_dir} \
+			|| err "ERROR: could not download ${name}"
+
+	(
+	cd ${tmp_dir} || exit 1
+	git reset --hard ${revision} || err "Cannot reset revision"
+	)
+
+	patch_project
+
+	if [ -d "${location}" ]; then
+		rm -Rf ${location} || exit 1
+	fi
+	mv ${tmp_dir} ${location} && return 0
+
+	printf "ERROR: Could not copy temp file to destination.\n"
+	err " ${tmp_dir} > ${location} check permissions"
+}
+
+patch_project()
+{
+	patchdir="resources/${name}/patches"
+
+	for patchfile in ${PWD}/${patchdir}/*.patch ; do
+		if [ ! -f "${patchfile}" ]; then
+			continue
+		fi
+		(
+		cd ${tmp_dir} || exit 1
+		git am ${patchfile} || err "Cannot patch project: $name"
+		)
+	done
+}
+
+usage()
+{
+	cat <<- EOF
+	Usage: ./gitclone [name]
+
+	Options:
+	name: Module name as specified in resources/git/revisions
+	EOF
+}
+
+err()
+{
+	printf "${@}\n"
+	usage
+	exit 1
+}
+
+main $@

lbmk

@@ -0,0 +1,129 @@
+#!/usr/bin/env sh
+
+#  generic script for calling other scripts in lbmk
+#
+#	Copyright (C) 2014,2015,2020,2021,2023 Leah Rowe <info@minifree.org>
+#	Copyright (C) 2015 Patrick "P. J." McDermott <pj@pehjota.net>
+#	Copyright (C) 2015, 2016 Klemens Nanni <contact@autoboot.org>
+#	Copyright (C) 2022, Caleb La Grange <thonkpeasant@protonmail.com>
+#
+#	This program is free software: you can redistribute it and/or modify
+#	it under the terms of the GNU General Public License as published by
+#	the Free Software Foundation, either version 3 of the License, or
+#	(at your option) any later version.
+#
+#	This program is distributed in the hope that it will be useful,
+#	but WITHOUT ANY WARRANTY; without even the implied warranty of
+#	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#	GNU General Public License for more details.
+#
+#	You should have received a copy of the GNU General Public License
+#	along with this program.  If not, see <http://www.gnu.org/licenses/>.
+#
+
+[ "x${DEBUG+set}" = 'xset' ] && set -v
+set -u -e
+
+projectname="$(cat projectname)"
+buildpath=""
+mode=""
+option=""
+
+main()
+{
+	if [ "${0##*/}" = "lbmk" ]; then
+		die "Do not run the lbmk script directly!"
+	elif [ "${0##*/}" = "download" ]; then
+		./update module $@ || exit 1
+		exit 0
+	elif [ "${0##*/}" = "blobutil" ]; then
+		./update blobs $@ || exit 1
+		exit 0
+	elif [ $# -lt 1 ]; then
+		die "Too few arguments. Try: ${0} help"
+	fi
+
+	buildpath="./resources/scripts/${0##*/}"
+
+	mode="${1}"
+	./.gitcheck
+	if [ "${mode}" != "dependencies" ]; then
+		./resources/scripts/misc/versioncheck
+	fi
+	if [ "${mode}" = help ]; then
+		usage $0
+		exit 0
+	elif [ $# -lt 2 ]; then
+		usage $0
+		exit 0
+	fi
+
+	option="${2}"
+	shift 2
+
+	case "${option}" in
+	list)
+		printf "Options for mode '%s':\n\n" ${mode}
+		listoptions "${mode}"
+		;;
+	all)
+		for option in $(listoptions "${mode}"); do
+			"${buildpath}/${mode}/${option}" $@
+		done
+		;;
+	*)
+		if [ ! -d "${buildpath}/${mode}" ]; then
+			usage $0
+			die "Invalid mode '${mode}'. Run: ${0} help"
+		elif [ ! -f "${buildpath}/${mode}/${option}" ]; then
+			usage $0
+			printf "Invalid option for '%s'." ${mode}
+			die "Run: ${0} ${mode} list'."
+		fi
+		"${buildpath}/${mode}/${option}" $@ || die "lbmk error"
+	esac
+
+	./.gitcheck clean
+}
+
+# Takes exactly one mode as parameter
+listoptions()
+{
+	for option in "${buildpath}/${1}/"*; do
+		printf '%s\n' ${option##*/}
+	done
+}
+
+usage()
+{
+	progname=${0}
+	cat <<- EOF
+	USAGE:	${progname} <MODE> <OPTION>
+
+	possible values for 'mode':
+	$(listmodes)
+
+	Example:	${progname} module all
+	Example:	${progname} module flashrom [static]
+	Example:	${progname} roms withgrub
+	Example:	${progname} clean all
+
+	Refer to ${projectname} documentation for more info.
+	EOF
+}
+
+listmodes()
+{
+	for mode in "${buildpath}"/*; do
+		printf '%s\n' ${mode##*/}
+	done
+}
+
+die()
+{
+	./.gitcheck clean
+	printf "Error: %s\n" "${@}" 1>&2
+	exit 1
+}
+
+main $@

modify

@@ -0,0 +1 @@
+lbmk

resources/blobs/me7_update_parser.py

@@ -0,0 +1,616 @@
+#!/usr/bin/env python3
+
+"""ME7 Update binary parser."""
+
+# Copyright (C) 2020 Tom Hiller <thrilleratplay@gmail.com>
+# Copyright (C) 2016-2018 Nicola Corna <nicola@corna.info>
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 3 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+# Based on the amazing me_cleaner, https://github.com/corna/me_cleaner, parses
+# the required signed partition from an ME update file to generate a valid
+# flashable ME binary.
+#
+#  This was written for Heads ROM, https://github.com/osresearch/heads
+#  to allow continuous integration reproducible builds for Lenovo xx20 models
+#  (X220, T420, T520, etc).
+#
+#  A full model list can be found:
+#   https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.txt
+
+
+from struct import pack, unpack
+from typing import List
+import argparse
+import sys
+import hashlib
+import binascii
+import os.path
+
+#############################################################################
+
+FTPR_END = 0x76000
+MINIFIED_FTPR_OFFSET = 0x400  # offset start of Factory Partition (FTPR)
+ORIG_FTPR_OFFSET = 0xCC000
+PARTITION_HEADER_OFFSET = 0x30  # size of partition header
+
+DEFAULT_OUTPUT_FILE_NAME = "flashregion_2_intel_me.bin"
+
+#############################################################################
+
+
+class EntryFlags:
+    """EntryFlag bitmap values."""
+
+    ExclBlockUse = 8192
+    WOPDisable = 4096
+    Logical = 2048
+    Execute = 1024
+    Write = 512
+    Read = 256
+    DirectAccess = 128
+    Type = 64
+
+
+def generateHeader() -> bytes:
+    """Generate Header."""
+    ROM_BYPASS_INSTR_0 = binascii.unhexlify("2020800F")
+    ROM_BYPASS_INSTR_1 = binascii.unhexlify("40000010")
+    ROM_BYPASS_INSTR_2 = pack("<I", 0)
+    ROM_BYPASS_INSTR_3 = pack("<I", 0)
+
+    # $FPT Partition table header
+    HEADER_TAG = "$FPT".encode()
+    HEADER_NUM_PARTITIONS = pack("<I", 1)
+    HEADER_VERSION = b"\x20"  # version 2.0
+    HEADER_ENTRY_TYPE = b"\x10"
+    HEADER_LENGTH = b"\x30"
+    HEADER_CHECKSUM = pack("<B", 0)
+    HEADER_FLASH_CYCLE_LIFE = pack("<H", 7)
+    HEADER_FLASH_CYCLE_LIMIT = pack("<H", 100)
+    HEADER_UMA_SIZE = pack("<H", 32)
+    HEADER_FLAGS = binascii.unhexlify("000000FCFFFF")
+    HEADER_FITMAJOR = pack("<H", 0)
+    HEADER_FITMINOR = pack("<H", 0)
+    HEADER_FITHOTFIX = pack("<H", 0)
+    HEADER_FITBUILD = pack("<H", 0)
+
+    FTPR_header_layout = bytearray(
+        ROM_BYPASS_INSTR_0
+        + ROM_BYPASS_INSTR_1
+        + ROM_BYPASS_INSTR_2
+        + ROM_BYPASS_INSTR_3
+        + HEADER_TAG
+        + HEADER_NUM_PARTITIONS
+        + HEADER_VERSION
+        + HEADER_ENTRY_TYPE
+        + HEADER_LENGTH
+        + HEADER_CHECKSUM
+        + HEADER_FLASH_CYCLE_LIFE
+        + HEADER_FLASH_CYCLE_LIMIT
+        + HEADER_UMA_SIZE
+        + HEADER_FLAGS
+        + HEADER_FITMAJOR
+        + HEADER_FITMINOR
+        + HEADER_FITHOTFIX
+        + HEADER_FITBUILD
+    )
+
+    # Update checksum
+    FTPR_header_layout[27] = (0x100 - sum(FTPR_header_layout) & 0xFF) & 0xFF
+
+    return FTPR_header_layout
+
+
+def generateFtpPartition() -> bytes:
+    """Partition table entry."""
+    ENTRY_NAME = binascii.unhexlify("46545052")
+    ENTRY_OWNER = binascii.unhexlify("FFFFFFFF")  # "None"
+    ENTRY_OFFSET = binascii.unhexlify("00040000")
+    ENTRY_LENGTH = binascii.unhexlify("00600700")
+    ENTRY_START_TOKENS = pack("<I", 1)
+    ENTRY_MAX_TOKENS = pack("<I", 1)
+    ENTRY_SCRATCH_SECTORS = pack("<I", 0)
+    ENTRY_FLAGS = pack(
+        "<I",
+        (
+            EntryFlags.ExclBlockUse
+            + EntryFlags.Execute
+            + EntryFlags.Write
+            + EntryFlags.Read
+            + EntryFlags.DirectAccess
+        ),
+    )
+
+    partition = (
+        ENTRY_NAME
+        + ENTRY_OWNER
+        + ENTRY_OFFSET
+        + ENTRY_LENGTH
+        + ENTRY_START_TOKENS
+        + ENTRY_MAX_TOKENS
+        + ENTRY_SCRATCH_SECTORS
+        + ENTRY_FLAGS
+    )
+
+    # offset of the partition - length of partition entry -length of header
+    pad_len = MINIFIED_FTPR_OFFSET - (len(partition) + PARTITION_HEADER_OFFSET)
+    padding = b""
+
+    for i in range(0, pad_len):
+        padding += b"\xFF"
+
+    return partition + padding
+
+
+############################################################################
+
+
+class OutOfRegionException(Exception):
+    """Out of Region Exception."""
+
+    pass
+
+
+class clean_ftpr:
+    """Clean Factory Parition (FTPR)."""
+
+    UNREMOVABLE_MODULES = ("ROMP", "BUP")
+    COMPRESSION_TYPE_NAME = ("uncomp.", "Huffman", "LZMA")
+
+    def __init__(self, ftpr: bytes):
+        """Init."""
+        self.orig_ftpr = ftpr
+        self.ftpr = ftpr
+        self.mod_headers: List[bytes] = []
+        self.check_and_clean_ftpr()
+
+    #####################################################################
+    # tilities
+    #####################################################################
+    def slice(self, offset: int, size: int) -> bytes:
+        """Copy data of a given size from FTPR starting from offset."""
+        offset_end = offset + size
+        return self.ftpr[offset:offset_end]
+
+    def unpack_next_int(self, offset: int) -> int:
+        """Sugar syntax for unpacking a little-endian UINT at offset."""
+        return self.unpack_val(self.slice(offset, 4))
+
+    def unpack_val(self, data: bytes) -> int:
+        """Sugar syntax for unpacking a little-endian unsigned integer."""
+        return unpack("<I", data)[0]
+
+    def bytes_to_ascii(self, data: bytes) -> str:
+        """Decode bytes into ASCII."""
+        return data.rstrip(b"\x00").decode("ascii")
+
+    def clear_ftpr_data(self, start: int, end: int) -> None:
+        """Replace values in range with 0xFF."""
+        empty_data = bytes()
+
+        for i in range(0, end - start):
+            empty_data += b"\xff"
+        self.write_ftpr_data(start, empty_data)
+
+    def write_ftpr_data(self, start: int, data: bytes) -> None:
+        """Replace data in FTPR starting at a given offset."""
+        end = len(data) + start
+
+        new_partition = self.ftpr[:start]
+        new_partition += data
+
+        if end != FTPR_END:
+            new_partition += self.ftpr[end:]
+
+        self.ftpr = new_partition
+
+    ######################################################################
+    # FTPR cleanig/checking functions
+    ######################################################################
+    def get_chunks_offsets(self, llut: bytes):
+        """Calculate Chunk offsets from LLUT."""
+        chunk_count = self.unpack_val(llut[0x04:0x08])
+        huffman_stream_end = sum(unpack("<II", llut[0x10:0x18]))
+        nonzero_offsets = [huffman_stream_end]
+        offsets = []
+
+        for i in range(0, chunk_count):
+            llut_start = 0x40 + (i * 4)
+            llut_end = 0x44 + (i * 4)
+
+            chunk = llut[llut_start:llut_end]
+            offset = 0
+
+            if chunk[3] != 0x80:
+                offset = self.unpack_val(chunk[0:3] + b"\x00")
+
+            offsets.append([offset, 0])
+
+            if offset != 0:
+                nonzero_offsets.append(offset)
+
+        nonzero_offsets.sort()
+
+        for i in offsets:
+            if i[0] != 0:
+                i[1] = nonzero_offsets[nonzero_offsets.index(i[0]) + 1]
+
+        return offsets
+
+    def relocate_partition(self) -> int:
+        """Relocate partition."""
+        new_offset = MINIFIED_FTPR_OFFSET
+        name = self.bytes_to_ascii(self.slice(PARTITION_HEADER_OFFSET, 4))
+
+        old_offset, partition_size = unpack(
+            "<II", self.slice(PARTITION_HEADER_OFFSET + 0x8, 0x8)
+        )
+
+        llut_start = 0
+        for mod_header in self.mod_headers:
+            if (self.unpack_val(mod_header[0x50:0x54]) >> 4) & 7 == 0x01:
+                llut_start = self.unpack_val(mod_header[0x38:0x3C])
+                llut_start += old_offset
+                break
+
+        if self.mod_headers and llut_start != 0:
+            # Bytes 0x9:0xb of the LLUT (bytes 0x1:0x3 of the AddrBase) are
+            # added to the SpiBase (bytes 0xc:0x10 of the LLUT) to compute the
+            # final start of the LLUT. Since AddrBase is not modifiable, we can
+            # act only on SpiBase and here we compute the minimum allowed
+            # new_offset.
+            llut_start_corr = unpack("<H", self.slice(llut_start + 0x9, 2))[0]
+            new_offset = max(
+                new_offset, llut_start_corr - llut_start - 0x40 + old_offset
+            )
+            new_offset = ((new_offset + 0x1F) // 0x20) * 0x20
+        offset_diff = new_offset - old_offset
+
+        print(
+            "Relocating {} from {:#x} - {:#x} to {:#x} - {:#x}...".format(
+                name,
+                old_offset,
+                old_offset + partition_size,
+                new_offset,
+                new_offset + partition_size,
+            )
+        )
+
+        print(" Adjusting FPT entry...")
+        self.write_ftpr_data(
+            PARTITION_HEADER_OFFSET + 0x08,
+            pack("<I", new_offset),
+        )
+
+        if self.mod_headers:
+            if llut_start != 0:
+                if self.slice(llut_start, 4) == b"LLUT":
+                    print(" Adjusting LUT start offset...")
+                    llut_offset = pack(
+                        "<I", llut_start + offset_diff + 0x40 - llut_start_corr
+                    )
+                    self.write_ftpr_data(llut_start + 0x0C, llut_offset)
+
+                    print(" Adjusting Huffman start offset...")
+                    old_huff_offset = self.unpack_next_int(llut_start + 0x14)
+                    ftpr_offset_diff = MINIFIED_FTPR_OFFSET - ORIG_FTPR_OFFSET
+                    self.write_ftpr_data(
+                        llut_start + 0x14,
+                        pack("<I", old_huff_offset + ftpr_offset_diff),
+                    )
+
+                    print(" Adjusting chunks offsets...")
+                    chunk_count = self.unpack_next_int(llut_start + 0x4)
+                    offset = llut_start + 0x40
+                    offset_end = chunk_count * 4
+                    chunks = bytearray(self.slice(offset, offset_end))
+
+                    for i in range(0, offset_end, 4):
+                        i_plus_3 = i + 3
+
+                        if chunks[i_plus_3] != 0x80:
+                            chunks[i:i_plus_3] = pack(
+                                "<I",
+                                self.unpack_val(chunks[i:i_plus_3] + b"\x00")
+                                + (MINIFIED_FTPR_OFFSET - ORIG_FTPR_OFFSET),
+                            )[0:3]
+                    self.write_ftpr_data(offset, bytes(chunks))
+                else:
+                    sys.exit("Huffman modules present but no LLUT found!")
+            else:
+                print(" No Huffman modules found")
+
+        print(" Moving data...")
+        partition_size = min(partition_size, FTPR_END - old_offset)
+
+        if (
+            old_offset + partition_size <= FTPR_END
+            and new_offset + partition_size <= FTPR_END
+        ):
+            for i in range(0, partition_size, 4096):
+                block_length = min(partition_size - i, 4096)
+                block = self.slice(old_offset + i, block_length)
+                self.clear_ftpr_data(old_offset + i, len(block))
+
+                self.write_ftpr_data(new_offset + i, block)
+        else:
+            raise OutOfRegionException()
+
+        return new_offset
+
+    def remove_modules(self) -> int:
+        """Remove modules."""
+        unremovable_huff_chunks = []
+        chunks_offsets = []
+        base = 0
+        chunk_size = 0
+        end_addr = 0
+
+        for mod_header in self.mod_headers:
+            name = self.bytes_to_ascii(mod_header[0x04:0x14])
+            offset = self.unpack_val(mod_header[0x38:0x3C])
+            size = self.unpack_val(mod_header[0x40:0x44])
+            flags = self.unpack_val(mod_header[0x50:0x54])
+            comp_type = (flags >> 4) & 7
+            comp_type_name = self.COMPRESSION_TYPE_NAME[comp_type]
+
+            print(" {:<16} ({:<7}, ".format(name, comp_type_name), end="")
+
+            # If compresion type uncompressed or LZMA
+            if comp_type == 0x00 or comp_type == 0x02:
+                offset_end = offset + size
+                range_msg = "0x{:06x} - 0x{:06x}       ): "
+                print(range_msg.format(offset, offset_end), end="")
+
+                if name in self.UNREMOVABLE_MODULES:
+                    end_addr = max(end_addr, offset + size)
+                    print("NOT removed, essential")
+                else:
+                    offset_end = min(offset + size, FTPR_END)
+                    self.clear_ftpr_data(offset, offset_end)
+                    print("removed")
+
+            # Else if compression type huffman
+            elif comp_type == 0x01:
+                if not chunks_offsets:
+                    # Check if Local Look Up Table (LLUT) is present
+                    if self.slice(offset, 4) == b"LLUT":
+                        llut = self.slice(offset, 0x40)
+
+                        chunk_count = self.unpack_val(llut[0x4:0x8])
+                        base = self.unpack_val(llut[0x8:0xC]) + 0x10000000
+                        chunk_size = self.unpack_val(llut[0x30:0x34])
+
+                        llut = self.slice(offset, (chunk_count * 4) + 0x40)
+
+                        # calculate offsets of chunks from LLUT
+                        chunks_offsets = self.get_chunks_offsets(llut)
+                    else:
+                        no_llut_msg = "Huffman modules found,"
+                        no_llut_msg += "but LLUT is not present."
+                        sys.exit(no_llut_msg)
+
+                module_base = self.unpack_val(mod_header[0x34:0x38])
+                module_size = self.unpack_val(mod_header[0x3C:0x40])
+                first_chunk_num = (module_base - base) // chunk_size
+                last_chunk_num = first_chunk_num + module_size // chunk_size
+                huff_size = 0
+
+                chunk_length = last_chunk_num + 1
+                for chunk in chunks_offsets[first_chunk_num:chunk_length]:
+                    huff_size += chunk[1] - chunk[0]
+
+                size_in_kiB = "~" + str(int(round(huff_size / 1024))) + " KiB"
+                print(
+                    "fragmented data, {:<9}): ".format(size_in_kiB),
+                    end="",
+                )
+
+                # Check if module is in the unremovable list
+                if name in self.UNREMOVABLE_MODULES:
+                    print("NOT removed, essential")
+
+                    # add to list of unremovable chunks
+                    for x in chunks_offsets[first_chunk_num:chunk_length]:
+                        if x[0] != 0:
+                            unremovable_huff_chunks.append(x)
+                else:
+                    print("removed")
+
+            # Else unknown compression type
+            else:
+                unkwn_comp_msg = " 0x{:06x} - 0x{:06x}): "
+                unkwn_comp_msg += "unknown compression, skipping"
+                print(unkwn_comp_msg.format(offset, offset + size), end="")
+
+        if chunks_offsets:
+            removable_huff_chunks = []
+
+            for chunk in chunks_offsets:
+                # if chunk is not in a unremovable chunk, it must be removable
+                if all(
+                    not (
+                        unremovable_chk[0] <= chunk[0] < unremovable_chk[1]
+                        or unremovable_chk[0] < chunk[1] <= unremovable_chk[1]
+                    )
+                    for unremovable_chk in unremovable_huff_chunks
+                ):
+                    removable_huff_chunks.append(chunk)
+
+            for removable_chunk in removable_huff_chunks:
+                if removable_chunk[1] > removable_chunk[0]:
+                    chunk_start = removable_chunk[0] - ORIG_FTPR_OFFSET
+                    chunk_end = removable_chunk[1] - ORIG_FTPR_OFFSET
+                    self.clear_ftpr_data(chunk_start, chunk_end)
+
+            end_addr = max(
+                end_addr, max(unremovable_huff_chunks, key=lambda x: x[1])[1]
+            )
+            end_addr -= ORIG_FTPR_OFFSET
+
+        return end_addr
+
+    def find_mod_header_size(self) -> None:
+        """Find module header size."""
+        self.mod_header_size = 0
+        data = self.slice(0x290, 0x84)
+
+        # check header size
+        if data[0x0:0x4] == b"$MME":
+            if data[0x60:0x64] == b"$MME" or self.num_modules == 1:
+                self.mod_header_size = 0x60
+            elif data[0x80:0x84] == b"$MME":
+                self.mod_header_size = 0x80
+
+    def find_mod_headers(self) -> None:
+        """Find module headers."""
+        data = self.slice(0x290, self.mod_header_size * self.num_modules)
+
+        for i in range(0, self.num_modules):
+            header_start = i * self.mod_header_size
+            header_end = (i + 1) * self.mod_header_size
+            self.mod_headers.append(data[header_start:header_end])
+
+    def resize_partition(self, end_addr: int) -> None:
+        """Resize partition."""
+        spared_blocks = 4
+        if end_addr > 0:
+            end_addr = (end_addr // 0x1000 + 1) * 0x1000
+            end_addr += spared_blocks * 0x1000
+
+            # partition header not added yet
+            # remove  trailing data the same size as the header.
+            end_addr -= MINIFIED_FTPR_OFFSET
+
+            me_size_msg = "The ME minimum size should be {0} "
+            me_size_msg += "bytes ({0:#x} bytes)"
+            print(me_size_msg.format(end_addr))
+            print("Truncating file at {:#x}...".format(end_addr))
+            self.ftpr = self.ftpr[:end_addr]
+
+    def check_and_clean_ftpr(self) -> None:
+        """Check and clean FTPR (factory partition)."""
+        self.num_modules = self.unpack_next_int(0x20)
+        self.find_mod_header_size()
+
+        if self.mod_header_size != 0:
+            self.find_mod_headers()
+
+            # ensure all of the headers begin with b'$MME'
+            if all(hdr.startswith(b"$MME") for hdr in self.mod_headers):
+                end_addr = self.remove_modules()
+                new_offset = self.relocate_partition()
+                end_addr += new_offset
+
+                self.resize_partition(end_addr)
+
+                # flip bit
+                # XXX: I have no idea why this works and passes RSA signiture
+                self.write_ftpr_data(0x39, b"\x00")
+            else:
+                sys.exit(
+                    "Found less modules than expected in the FTPR "
+                    "partition; skipping modules removal and exiting."
+                )
+        else:
+            sys.exit(
+                "Can't find the module header size; skipping modules"
+                "removal and exiting."
+            )
+
+
+##########################################################################
+
+
+def check_partition_signature(f, offset) -> bool:
+    """check_partition_signature copied/shamelessly stolen from me_cleaner."""
+    f.seek(offset)
+    header = f.read(0x80)
+    modulus = int(binascii.hexlify(f.read(0x100)[::-1]), 16)
+    public_exponent = unpack("<I", f.read(4))[0]
+    signature = int(binascii.hexlify(f.read(0x100)[::-1]), 16)
+
+    header_len = unpack("<I", header[0x4:0x8])[0] * 4
+    manifest_len = unpack("<I", header[0x18:0x1C])[0] * 4
+    f.seek(offset + header_len)
+
+    sha256 = hashlib.sha256()
+    sha256.update(header)
+    tmp = f.read(manifest_len - header_len)
+    sha256.update(tmp)
+
+    decrypted_sig = pow(signature, public_exponent, modulus)
+    return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest())  # FIXME
+
+
+##########################################################################
+
+
+def generate_me_blob(input_file: str, output_file: str) -> None:
+    """Generate ME blob."""
+    print("Starting ME 7.x Update parser.")
+
+    orig_f = open(input_file, "rb")
+    cleaned_ftpr = clean_ftpr(orig_f.read(FTPR_END))
+    orig_f.close()
+
+    fo = open(output_file, "wb")
+    fo.write(generateHeader())
+    fo.write(generateFtpPartition())
+    fo.write(cleaned_ftpr.ftpr)
+    fo.close()
+
+
+def verify_output(output_file: str) -> None:
+    """Verify Generated ME file."""
+    file_verifiy = open(output_file, "rb")
+
+    if check_partition_signature(file_verifiy, MINIFIED_FTPR_OFFSET):
+        print(output_file + " is VALID")
+        file_verifiy.close()
+    else:
+        print(output_file + " is INVALID!!")
+        file_verifiy.close()
+        sys.exit("The FTPR partition signature is not valid.")
+
+
+if __name__ == "__main__":
+    parser = argparse.ArgumentParser(
+        description="Tool to remove as much code "
+        "as possible from Intel ME/TXE 7.x firmware "
+        "update and create paratition for a flashable ME parition."
+    )
+
+
+parser.add_argument("file", help="ME/TXE image or full dump")
+parser.add_argument(
+    "-O",
+    "--output",
+    metavar="output_file",
+    help="save "
+    "save file name other than the default '" + DEFAULT_OUTPUT_FILE_NAME + "'",
+)
+
+args = parser.parse_args()
+
+output_file_name = DEFAULT_OUTPUT_FILE_NAME if not args.output else args.output
+
+# Check if output file exists, ask to overwrite or exit
+if os.path.isfile(output_file_name):
+    input_msg = output_file_name
+    input_msg += " exists.  Do you want to overwrite? [y/N]: "
+    if not str(input(input_msg)).lower().startswith("y"):
+        sys.exit("Not overwriting file.  Exiting.")
+
+generate_me_blob(args.file, output_file_name)
+verify_output(output_file_name)

resources/blobs/sources

@@ -0,0 +1,76 @@
+# This file holds the download sources for various intel blobs
+# board shortnames are listed and enclosed by '{}' followed by an opening
+# and closing '{}' for all blobs available for the board.
+# The board shortname must be the name of the board minus the trailing rom size.
+# If you want to make additions, try to add a backup url for download links and 
+# list hashes as sha1 sums.
+
+{x230 x230t x230i x230edp t430 t530 w530}{
+	DL_hash 039c89c6d44ae11ae2510cbd5fed756e97ed9a31
+	DL_url https://download.lenovo.com/pccbbs/mobiles/g1rg24ww.exe
+	DL_url_bkup https://web.archive.org/web/20210706183911/https://download.lenovo.com/pccbbs/mobiles/g1rg24ww.exe
+}
+
+{x220 x220t t420 t520 t420s}{
+	DL_hash fa0f96c8f36646492fb8c57ad3296bf5f647d9c5
+	DL_url https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe
+	DL_url_bkup https://web.archive.org/web/20220202201637/https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe
+}
+
+{t440pmrc w541mrc t440plibremrc w541}{
+	DL_hash b2f2a1baa1f0c8139e46b0d3e206386ff197bed5
+	DL_url https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe
+	DL_url_bkup https://web.archive.org/web/20211120031520/https://download.lenovo.com/pccbbs/mobiles/glrg22ww.exe
+}
+
+{hp8200sff}{
+	DL_hash c59e693effc1862c38cc4caa15be0a6a92557e0b
+	DL_url https://ftp.ext.hp.com/pub/softpaq/sp96001-96500/sp96026.exe
+	DL_url_bkup https://web.archive.org/web/20220708171920/https://ftp.ext.hp.com/pub/softpaq/sp96001-96500/sp96026.exe
+}
+
+{hp8300usdt}{
+	DL_hash 039c89c6d44ae11ae2510cbd5fed756e97ed9a31
+	DL_url https://download.lenovo.com/pccbbs/mobiles/g1rg24ww.exe
+	DL_url_bkup https://web.archive.org/web/20210706183911/https://download.lenovo.com/pccbbs/mobiles/g1rg24ww.exe
+}
+
+{hp2560p}{
+	DL_hash fa0f96c8f36646492fb8c57ad3296bf5f647d9c5
+	DL_url https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe
+	DL_url_bkup https://web.archive.org/web/20220202201637/https://download.lenovo.com/ibmdl/pub/pc/pccbbs/mobiles/83rf46ww.exe
+
+	EC_hash c1b1fb0a525cf90459bf024f407e302314bd981b
+	EC_url https://ftp.hp.com/pub/softpaq/sp85501-86000/sp85526.exe
+	EC_url_bkup https://web.archive.org/web/20230416125725/https://ftp.hp.com/pub/softpaq/sp85501-86000/sp85526.exe
+}
+
+{hp2570p}{
+	DL_hash 039c89c6d44ae11ae2510cbd5fed756e97ed9a31
+	DL_url https://download.lenovo.com/pccbbs/mobiles/g1rg24ww.exe
+	DL_url_bkup https://web.archive.org/web/20210706183911/https://download.lenovo.com/pccbbs/mobiles/g1rg24ww.exe
+
+	EC_hash a896ef72799e8abd4d0601ec415a2113b2a7f240
+	EC_url https://ftp.hp.com/pub/softpaq/sp96001-96500/sp96085.exe
+	EC_url_bkup https://web.archive.org/web/20230610174558/https://ftp.hp.com/pub/softpaq/sp96001-96500/sp96085.exe
+}
+
+{hp9470m}{
+	DL_hash 039c89c6d44ae11ae2510cbd5fed756e97ed9a31
+	DL_url https://download.lenovo.com/pccbbs/mobiles/g1rg24ww.exe
+	DL_url_bkup https://web.archive.org/web/20210706183911/https://download.lenovo.com/pccbbs/mobiles/g1rg24ww.exe
+
+	EC_hash 1a03e985552060a9dfe7c40b5ea97ecfb2794583
+	EC_url https://ftp.hp.com/pub/softpaq/sp96001-96500/sp96090.exe
+	EC_url_bkup http://web.archive.org/web/20220504072602/https://ftp.ext.hp.com/pub/softpaq/sp96001-96500/sp96090.exe
+}
+
+# nvidia vga option rom for dgpu models of Dell Latitude E6400
+# for downloading the nvidia rom to pciroms/pci0x10de,0x06eb.rom
+{e6400nvidia}{
+	E6400_VGA_DL_hash a24ed919e80287b281e407d525af31f307746250
+	E6400_VGA_DL_url https://dl.dell.com/FOLDER01530530M/1/E6400A34.exe
+	E6400_VGA_DL_url_bkup https://web.archive.org/web/20230506014903/https://dl.dell.com/FOLDER01530530M/1/E6400A34.exe
+	E6400_VGA_offset 274451
+	E6400_VGA_romname mod_21.bin
+}

resources/coreboot/cros/board.cfg

@@ -0,0 +1,4 @@
+cbtree="cros"
+arch="spaghettimonster"
+cbrevision="8da4bfe5b573f395057fbfb5a9d99b376e25c2a4" # 4.17
+romtype="normal"

resources/coreboot/cros/patches/0001-fix-crossgcc-build-error.patch

@@ -0,0 +1,55 @@
+From 0d5a5f3ee1ee5d6f757d5877b7adbe9839487ccf Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sat, 19 Nov 2022 14:55:01 +0000
+Subject: [PATCH 1/1] fix crossgcc build error
+
+---
+ util/crossgcc/patches/gcc-11.2.0_gnat.patch | 32 ++++++++++++++++++++-
+ 1 file changed, 31 insertions(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/patches/gcc-11.2.0_gnat.patch b/util/crossgcc/patches/gcc-11.2.0_gnat.patch
+index 2d7cecee24..c22cec45d0 100644
+--- a/util/crossgcc/patches/gcc-11.2.0_gnat.patch
++++ b/util/crossgcc/patches/gcc-11.2.0_gnat.patch
+@@ -5,7 +5,37 @@
+  
+  # Extra flags to pass to recursive makes.
+ -COMMON_ADAFLAGS= -gnatpg
+-+COMMON_ADAFLAGS= -gnatpg -gnatwGUR
+++COMMON_ADAFLAGS= -gnatpg -gnatwn
+  ifeq ($(TREECHECKING),)
+  CHECKING_ADAFLAGS=
+  else
++diff -Nurp gcc-11.2.0/gcc/ada/gcc-interface/Make-lang.in gcc-11.2.0.new/gcc/ada/gcc-interface/Make-lang.in
++--- gcc-11.2.0/gcc/ada/gcc-interface/Make-lang.in	2022-06-03 00:31:57.993273717 +0200
+++++ gcc-11.2.0.new/gcc/ada/gcc-interface/Make-lang.in	2022-06-03 00:30:50.214166847 +0200
++@@ -334,6 +334,7 @@ GNAT_ADA_OBJS =	\
++  ada/hostparm.o	\
++  ada/impunit.o	\
++  ada/inline.o	\
+++ ada/libgnat/i-c.o	\
++  ada/libgnat/interfac.o	\
++  ada/itypes.o	\
++  ada/krunch.o	\
++@@ -364,7 +365,10 @@ GNAT_ADA_OBJS =	\
++  ada/rtsfind.o	\
++  ada/libgnat/s-addope.o	\
++  ada/libgnat/s-addima.o \
+++ ada/libgnat/s-aotase.o	\
++  ada/libgnat/s-assert.o	\
+++ ada/libgnat/s-atoope.o	\
+++ ada/libgnat/s-atopri.o	\
++  ada/libgnat/s-bitops.o	\
++  ada/libgnat/s-carun8.o	\
++  ada/libgnat/s-casuti.o	\
++@@ -548,6 +552,7 @@ GNATBIND_OBJS = \
++  ada/hostparm.o   \
++  ada/init.o       \
++  ada/initialize.o \
+++ ada/libgnat/i-c.o        \
++  ada/libgnat/interfac.o   \
++  ada/krunch.o     \
++  ada/lib.o        \
+-- 
+2.25.1
+

resources/coreboot/cros/patches/0002-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -0,0 +1,38 @@
+From 1ce4f118b024a6367382b46016781f30fe622e3e Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 12 May 2023 19:55:15 -0600
+Subject: [PATCH] Remove warning for coreboot images built without a payload
+
+I added this in upstream to prevent people from accidentally flashing
+roms without a payload resulting in a no boot situation, but in
+libreboot lbmk handles the payload and thus this warning always comes
+up. This has caused confusion and concern so just patch it out.
+---
+ payloads/Makefile.inc | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
+index e735443a76..4f1692a873 100644
+--- a/payloads/Makefile.inc
++++ b/payloads/Makefile.inc
+@@ -49,16 +49,5 @@ distclean-payloads:
+ print-repo-info-payloads:
+ 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
+ 
+-ifeq ($(CONFIG_PAYLOAD_NONE),y)
+-files_added:: warn_no_payload
+-endif
+-
+-warn_no_payload:
+-	printf "\n\t** WARNING **\n"
+-	printf "coreboot has been built without a payload. Writing\n"
+-	printf "a coreboot image without a payload to your board's\n"
+-	printf "flash chip will result in a non-booting system. You\n"
+-	printf "can use cbfstool to add a payload to the image.\n\n"
+-
+ .PHONY: force-payload coreinfo nvramcui
+-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
+-- 
+2.40.1
+

resources/coreboot/cros/patches/0003-HACK-Disable-coreboot-related-BL31-features.patch

@@ -0,0 +1,28 @@
+From 9f52555eac217623ad2edc72492f9ded6a5b538d Mon Sep 17 00:00:00 2001
+From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
+Date: Thu, 22 Jun 2023 16:44:27 +0300
+Subject: [PATCH] HACK: Disable coreboot related BL31 features
+
+I don't know why, but removing this BL31 make argument lets gru-kevin
+power off properly when shut down from Linux. Needs investigation.
+---
+ src/arch/arm64/Makefile.inc | 3 ---
+ 1 file changed, 3 deletions(-)
+
+diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc
+index 6b49743633c3..e1982d92cc5c 100644
+--- a/src/arch/arm64/Makefile.inc
++++ b/src/arch/arm64/Makefile.inc
+@@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
+ # Always enable crash reporting, even on a release build
+ BL31_MAKEARGS += CRASH_REPORTING=1
+ 
+-# Enable coreboot-specific features like CBMEM console support
+-BL31_MAKEARGS += COREBOOT=1
+-
+ # Avoid build/release|build/debug distinction by overriding BUILD_PLAT directly
+ BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
+ 
+-- 
+2.40.1
+

resources/coreboot/d510mo/board.cfg

@@ -1,6 +1,8 @@
 cbtree="default"
 romtype="normal"
 arch="x86_64"
-payload_grub="y"
-payload_grub_withseabios="y"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
+microcode_required="n"
+blobs_required="n"

resources/coreboot/d510mo/config/libgfxinit_txtmode

@@ -11,14 +11,17 @@ CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -34,6 +37,12 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
 # CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
 # end of General setup
 
 #
@@ -51,30 +60,25 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BAP is not set
 # CONFIG_VENDOR_BIOSTAR is not set
 # CONFIG_VENDOR_BOSTENTECH is not set
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
 # CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_ELMEX is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GIZMOSPHERE is not set
 # CONFIG_VENDOR_GOOGLE is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 CONFIG_VENDOR_INTEL=y
-# CONFIG_VENDOR_JETWAY is not set
 # CONFIG_VENDOR_KONTRON is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_LIPPERT is not set
 # CONFIG_VENDOR_MSI is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
@@ -89,9 +93,9 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
 # CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SCALEWAY is not set
 # CONFIG_VENDOR_SIEMENS is not set
 # CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
@@ -107,25 +111,24 @@ CONFIG_FMDFILE=""
 # CONFIG_NO_POST is not set
 CONFIG_MAINBOARD_VENDOR="Intel"
 CONFIG_CBFS_SIZE=0x00100000
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_MAX_CPUS=4
-# CONFIG_VBOOT is not set
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
 CONFIG_DEVICETREE="devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-CONFIG_UART_FOR_CONSOLE=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_POST_DEVICE=y
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 CONFIG_DCACHE_RAM_BASE=0xfefc0000
-CONFIG_DCACHE_RAM_SIZE=0x4000
+CONFIG_DCACHE_RAM_SIZE=0x8000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
@@ -133,14 +136,16 @@ CONFIG_ECAM_MMCONF_BUS_NUMBER=256
 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CONSOLE_SERIAL=y
 # CONFIG_BOARD_INTEL_ADLRVP_P is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
 # CONFIG_BOARD_INTEL_ADLRVP_M is not set
 # CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
+# CONFIG_BOARD_INTEL_ADLRVP_N is not set
+# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
+# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
 # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
@@ -164,8 +169,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_GALILEO is not set
 # CONFIG_BOARD_INTEL_GLKRVP is not set
 # CONFIG_BOARD_INTEL_HARCUVAR is not set
-# CONFIG_BOARD_INTEL_ICELAKE_RVPU is not set
-# CONFIG_BOARD_INTEL_ICELAKE_RVPY is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
 # CONFIG_BOARD_INTEL_KBLRVP3 is not set
@@ -175,6 +178,8 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_KUNIMITSU is not set
 # CONFIG_BOARD_INTEL_LEAFHILL is not set
 # CONFIG_BOARD_INTEL_MINNOW3 is not set
+# CONFIG_BOARD_INTEL_MTLRVP_P is not set
+# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
 # CONFIG_BOARD_INTEL_STRAGO is not set
@@ -182,12 +187,17 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
 # CONFIG_BOARD_INTEL_WTM2 is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
+CONFIG_PCIEXP_HOTPLUG_BUSES=32
+CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
 CONFIG_PS2K_EISAID="PNP0303"
 CONFIG_PS2M_EISAID="PNP0F13"
+# CONFIG_DEBUG_SMI is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
-CONFIG_DRIVERS_UART_8250IO=y
+# CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_HEAP_SIZE=0x4000
+CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -219,31 +229,29 @@ CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
 #
 # SoC
 #
-CONFIG_ARCH_ALL_STAGES_X86=y
 CONFIG_CHIPSET_DEVICETREE=""
+CONFIG_CBFS_MCACHE_SIZE=0x4000
 CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_RAMBASE=0xe00000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d"
+CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X"
 CONFIG_EHCI_BAR=0xfef00000
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_STACK_SIZE=0x1000
+CONFIG_STACK_SIZE=0x2000
 CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_BOOTBLOCK_IN_CBFS=y
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_AZALIA_MAX_CODECS=3
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_TTYS0_BASE=0x3f8
-CONFIG_TTYS0_LCS=3
-CONFIG_UART_PCI_ADDR=0x0
+CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
@@ -252,9 +260,8 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
 # CPU
 #
 CONFIG_CPU_INTEL_MODEL_106CX=y
-CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
 CONFIG_SOCKET_SPECIFIC_OPTIONS=y
-CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
 CONFIG_CPU_INTEL_COMMON=y
 CONFIG_ENABLE_VMX=y
 CONFIG_SET_IA32_FC_LOCK_BIT=y
@@ -267,36 +274,35 @@ CONFIG_PARALLEL_MP=y
 CONFIG_XAPIC_ONLY=y
 # CONFIG_X2APIC_ONLY is not set
 # CONFIG_X2APIC_RUNTIME is not set
+# CONFIG_X2APIC_LATE_WORKAROUND is not set
 CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
 CONFIG_LOGICAL_CPUS=y
 CONFIG_HAVE_SMI_HANDLER=y
 CONFIG_SMM_TSEG=y
-CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
-CONFIG_SMM_STUB_STACK_SIZE=0x400
-CONFIG_SERIALIZED_SMM_INITIALIZATION=y
-CONFIG_CPU_INFO_V2=y
+CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
+CONFIG_AP_STACK_SIZE=0x800
 CONFIG_SMP=y
 CONFIG_MMX=y
 CONFIG_SSE=y
+CONFIG_SSE2=y
 CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-# CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS is not set
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
 
 #
 # Northbridge
 #
-CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y
 CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
 
 #
 # Southbridge
 #
-CONFIG_HPET_MIN_TICKS=0x80
-# CONFIG_PCIEXP_HOTPLUG is not set
+CONFIG_PCIEXP_HOTPLUG=y
 CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
@@ -314,10 +320,10 @@ CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
 CONFIG_INTEL_CHIPSET_LOCKDOWN=y
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
 CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
 CONFIG_RCBA_LENGTH=0x4000
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
 
 #
 # Super I/O
@@ -337,17 +343,16 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y
 CONFIG_ARCH_ALL_STAGES_X86_32=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_RAMTOP=0x1000000
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_NUM_IPI_STARTS=2
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_HPET_ADDRESS=0xfed00000
 CONFIG_POSTCAR_STAGE=y
 CONFIG_BOOTBLOCK_SIMPLE=y
 # CONFIG_BOOTBLOCK_NORMAL is not set
 CONFIG_COLLECT_TIMESTAMPS_TSC=y
 CONFIG_HAVE_CF9_RESET=y
+CONFIG_DEBUG_HW_BREAKPOINTS=y
+CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # end of Chipset
 
 #
@@ -358,6 +363,7 @@ CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
 CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
 # CONFIG_VGA_ROM_RUN is not set
 # CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
 
 #
 # Display
@@ -375,13 +381,26 @@ CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
 CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
+# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
+# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
+CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
-CONFIG_RESOURCE_ALLOCATOR_V4=y
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_NO_DDR5=y
+CONFIG_NO_LPDDR4=y
+CONFIG_NO_DDR4=y
+CONFIG_USE_DDR3=y
+CONFIG_USE_DDR2=y
 # end of Devices
 
 #
@@ -403,30 +422,39 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DRIVERS_UART=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
 CONFIG_DRIVERS_I2C_CK505=y
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_EDID=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_INTEL_GMA_OPREGION_2_0=y
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
 # end of Generic Drivers
 
 #
 # Security
 #
 
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
 #
 # Verified Boot (vboot)
 #
@@ -466,27 +494,12 @@ CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_BOOTBLOCK_CONSOLE=y
 CONFIG_POSTCAR_CONSOLE=y
 CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_BAUD=115200
 # CONFIG_SPKMODEM is not set
 # CONFIG_CONSOLE_NE2K is not set
 CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
 # CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
@@ -497,6 +510,8 @@ CONFIG_CONSOLE_CBMEM=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
 # CONFIG_CMOS_POST is not set
 CONFIG_POST_DEVICE_NONE=y
 # CONFIG_POST_DEVICE_LPC is not set
@@ -523,28 +538,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # Payload
 #
 CONFIG_PAYLOAD_NONE=y
-# CONFIG_PAYLOAD_ELF is not set
-# CONFIG_PAYLOAD_BOOTBOOT is not set
-# CONFIG_PAYLOAD_FILO is not set
-# CONFIG_PAYLOAD_GRUB2 is not set
-# CONFIG_PAYLOAD_LINUXBOOT is not set
-# CONFIG_PAYLOAD_SEABIOS is not set
-# CONFIG_PAYLOAD_UBOOT is not set
-# CONFIG_PAYLOAD_YABITS is not set
-# CONFIG_PAYLOAD_LINUX is not set
-# CONFIG_PAYLOAD_TIANOCORE is not set
-CONFIG_PAYLOAD_OPTIONS=""
-# CONFIG_PXE is not set
-CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
-
-#
-# Secondary Payloads
-#
-# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
-# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
-# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
-# CONFIG_TINT_SECONDARY_PAYLOAD is not set
-# end of Secondary Payloads
 # end of Payload
 
 #
@@ -563,22 +556,19 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
 #
 # General Debug Settings
 #
-# CONFIG_GDB_STUB is not set
 # CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_SMI is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set
 # CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_HAVE_EM100_SUPPORT is not set
 # end of Debugging
 
-CONFIG_NO_CBFS_MCACHE=y
+CONFIG_DECOMPRESS_OFAST=y
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

resources/coreboot/d510mo_16mb/board.cfg

@@ -5,3 +5,5 @@ payload_grub="y"
 payload_grub_withseabios="y"
 payload_seabios="y"
 payload_memtest="y"
+microcode_required="n"
+blobs_required="n"

resources/coreboot/d510mo_16mb/config/libgfxinit_txtmode

@@ -11,14 +11,17 @@ CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -34,6 +37,12 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
 # CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
 # end of General setup
 
 #
@@ -51,30 +60,25 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BAP is not set
 # CONFIG_VENDOR_BIOSTAR is not set
 # CONFIG_VENDOR_BOSTENTECH is not set
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
 # CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_ELMEX is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GIZMOSPHERE is not set
 # CONFIG_VENDOR_GOOGLE is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 CONFIG_VENDOR_INTEL=y
-# CONFIG_VENDOR_JETWAY is not set
 # CONFIG_VENDOR_KONTRON is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_LIPPERT is not set
 # CONFIG_VENDOR_MSI is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
@@ -89,9 +93,9 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
 # CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SCALEWAY is not set
 # CONFIG_VENDOR_SIEMENS is not set
 # CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
@@ -107,25 +111,24 @@ CONFIG_FMDFILE=""
 # CONFIG_NO_POST is not set
 CONFIG_MAINBOARD_VENDOR="Intel"
 CONFIG_CBFS_SIZE=0x01000000
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_MAX_CPUS=4
-# CONFIG_VBOOT is not set
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
 CONFIG_DEVICETREE="devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-CONFIG_UART_FOR_CONSOLE=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_POST_DEVICE=y
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 CONFIG_DCACHE_RAM_BASE=0xfefc0000
-CONFIG_DCACHE_RAM_SIZE=0x4000
+CONFIG_DCACHE_RAM_SIZE=0x8000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
 CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
@@ -133,14 +136,16 @@ CONFIG_ECAM_MMCONF_BUS_NUMBER=256
 CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CONSOLE_SERIAL=y
 # CONFIG_BOARD_INTEL_ADLRVP_P is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
 # CONFIG_BOARD_INTEL_ADLRVP_M is not set
 # CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
+# CONFIG_BOARD_INTEL_ADLRVP_N is not set
+# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
+# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
 # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
@@ -164,8 +169,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_GALILEO is not set
 # CONFIG_BOARD_INTEL_GLKRVP is not set
 # CONFIG_BOARD_INTEL_HARCUVAR is not set
-# CONFIG_BOARD_INTEL_ICELAKE_RVPU is not set
-# CONFIG_BOARD_INTEL_ICELAKE_RVPY is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
 # CONFIG_BOARD_INTEL_KBLRVP3 is not set
@@ -175,6 +178,8 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_KUNIMITSU is not set
 # CONFIG_BOARD_INTEL_LEAFHILL is not set
 # CONFIG_BOARD_INTEL_MINNOW3 is not set
+# CONFIG_BOARD_INTEL_MTLRVP_P is not set
+# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
 # CONFIG_BOARD_INTEL_STRAGO is not set
@@ -182,12 +187,17 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
 # CONFIG_BOARD_INTEL_WTM2 is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
+CONFIG_PCIEXP_HOTPLUG_BUSES=32
+CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
 CONFIG_PS2K_EISAID="PNP0303"
 CONFIG_PS2M_EISAID="PNP0F13"
+# CONFIG_DEBUG_SMI is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
-CONFIG_DRIVERS_UART_8250IO=y
+# CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_HEAP_SIZE=0x4000
+CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -219,31 +229,29 @@ CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
 #
 # SoC
 #
-CONFIG_ARCH_ALL_STAGES_X86=y
 CONFIG_CHIPSET_DEVICETREE=""
+CONFIG_CBFS_MCACHE_SIZE=0x4000
 CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_RAMBASE=0xe00000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d"
+CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X"
 CONFIG_EHCI_BAR=0xfef00000
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_STACK_SIZE=0x1000
+CONFIG_STACK_SIZE=0x2000
 CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_BOOTBLOCK_IN_CBFS=y
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_AZALIA_MAX_CODECS=3
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_TTYS0_BASE=0x3f8
-CONFIG_TTYS0_LCS=3
-CONFIG_UART_PCI_ADDR=0x0
+CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
@@ -252,9 +260,8 @@ CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
 # CPU
 #
 CONFIG_CPU_INTEL_MODEL_106CX=y
-CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
 CONFIG_SOCKET_SPECIFIC_OPTIONS=y
-CONFIG_SSE2=y
+CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
 CONFIG_CPU_INTEL_COMMON=y
 CONFIG_ENABLE_VMX=y
 CONFIG_SET_IA32_FC_LOCK_BIT=y
@@ -267,36 +274,35 @@ CONFIG_PARALLEL_MP=y
 CONFIG_XAPIC_ONLY=y
 # CONFIG_X2APIC_ONLY is not set
 # CONFIG_X2APIC_RUNTIME is not set
+# CONFIG_X2APIC_LATE_WORKAROUND is not set
 CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
 CONFIG_LOGICAL_CPUS=y
 CONFIG_HAVE_SMI_HANDLER=y
 CONFIG_SMM_TSEG=y
-CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
-CONFIG_SMM_STUB_STACK_SIZE=0x400
-CONFIG_SERIALIZED_SMM_INITIALIZATION=y
-CONFIG_CPU_INFO_V2=y
+CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
+CONFIG_AP_STACK_SIZE=0x800
 CONFIG_SMP=y
 CONFIG_MMX=y
 CONFIG_SSE=y
+CONFIG_SSE2=y
 CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-# CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS is not set
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
 
 #
 # Northbridge
 #
-CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y
 CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
 
 #
 # Southbridge
 #
-CONFIG_HPET_MIN_TICKS=0x80
-# CONFIG_PCIEXP_HOTPLUG is not set
+CONFIG_PCIEXP_HOTPLUG=y
 CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
@@ -314,10 +320,10 @@ CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
 CONFIG_INTEL_CHIPSET_LOCKDOWN=y
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
 CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
 CONFIG_RCBA_LENGTH=0x4000
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
 
 #
 # Super I/O
@@ -337,17 +343,16 @@ CONFIG_ARCH_RAMSTAGE_X86_32=y
 CONFIG_ARCH_ALL_STAGES_X86_32=y
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_RAMTOP=0x1000000
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_NUM_IPI_STARTS=2
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_HPET_ADDRESS=0xfed00000
 CONFIG_POSTCAR_STAGE=y
 CONFIG_BOOTBLOCK_SIMPLE=y
 # CONFIG_BOOTBLOCK_NORMAL is not set
 CONFIG_COLLECT_TIMESTAMPS_TSC=y
 CONFIG_HAVE_CF9_RESET=y
+CONFIG_DEBUG_HW_BREAKPOINTS=y
+CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # end of Chipset
 
 #
@@ -358,6 +363,7 @@ CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
 CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
 # CONFIG_VGA_ROM_RUN is not set
 # CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
 
 #
 # Display
@@ -375,13 +381,26 @@ CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
 CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
+# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
+# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
+CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
-CONFIG_RESOURCE_ALLOCATOR_V4=y
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_NO_DDR5=y
+CONFIG_NO_LPDDR4=y
+CONFIG_NO_DDR4=y
+CONFIG_USE_DDR3=y
+CONFIG_USE_DDR2=y
 # end of Devices
 
 #
@@ -403,30 +422,39 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DRIVERS_UART=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
 CONFIG_DRIVERS_I2C_CK505=y
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_EDID=y
 CONFIG_INTEL_INT15=y
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_INTEL_GMA_OPREGION_2_0=y
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
 # end of Generic Drivers
 
 #
 # Security
 #
 
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
 #
 # Verified Boot (vboot)
 #
@@ -466,27 +494,12 @@ CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_BOOTBLOCK_CONSOLE=y
 CONFIG_POSTCAR_CONSOLE=y
 CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_BAUD=115200
 # CONFIG_SPKMODEM is not set
 # CONFIG_CONSOLE_NE2K is not set
 CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
 # CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
@@ -497,6 +510,8 @@ CONFIG_CONSOLE_CBMEM=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
 # CONFIG_CMOS_POST is not set
 CONFIG_POST_DEVICE_NONE=y
 # CONFIG_POST_DEVICE_LPC is not set
@@ -523,28 +538,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # Payload
 #
 CONFIG_PAYLOAD_NONE=y
-# CONFIG_PAYLOAD_ELF is not set
-# CONFIG_PAYLOAD_BOOTBOOT is not set
-# CONFIG_PAYLOAD_FILO is not set
-# CONFIG_PAYLOAD_GRUB2 is not set
-# CONFIG_PAYLOAD_LINUXBOOT is not set
-# CONFIG_PAYLOAD_SEABIOS is not set
-# CONFIG_PAYLOAD_UBOOT is not set
-# CONFIG_PAYLOAD_YABITS is not set
-# CONFIG_PAYLOAD_LINUX is not set
-# CONFIG_PAYLOAD_TIANOCORE is not set
-CONFIG_PAYLOAD_OPTIONS=""
-# CONFIG_PXE is not set
-CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
-
-#
-# Secondary Payloads
-#
-# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
-# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
-# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
-# CONFIG_TINT_SECONDARY_PAYLOAD is not set
-# end of Secondary Payloads
 # end of Payload
 
 #
@@ -563,22 +556,19 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
 #
 # General Debug Settings
 #
-# CONFIG_GDB_STUB is not set
 # CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_SMI is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set
 # CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_HAVE_EM100_SUPPORT is not set
 # end of Debugging
 
-CONFIG_NO_CBFS_MCACHE=y
+CONFIG_DECOMPRESS_OFAST=y
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

resources/coreboot/d945gclf/board.cfg

@@ -1,7 +0,0 @@
-cbtree="default"
-romtype="normal"
-arch="x86_32"
-payload_grub="n"
-payload_grub_withseabios="n"
-payload_seabios="y"
-payload_memtest="y"

resources/coreboot/default/blobs.list

@@ -1,22 +0,0 @@
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
-3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
-3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
-3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
-3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
-3rdparty/chromeec/test/legacy_nvmem_dump.h
-3rdparty/vboot/tests/futility/data/bios_link_mp.bin
-3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
-src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
-src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
-src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
-src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
-src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
-src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
-src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h
-3rdparty/chromeec/third_party/bmi260/accelgyro_bmi260_config_tbin.h

resources/coreboot/default/board.cfg

@@ -1,4 +1,4 @@
 cbtree="default"
 romtype="normal"
-cbrevision="b2e8bd83647f664260120fdfc7d07cba694dd89e"
+cbrevision="e70bc423f9a2e1d13827f2703efe1f9c72549f20"
 arch="x86_64"

resources/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch

@@ -1,7 +1,7 @@
-From 4df63d823092dc06e3cfc27165a4850b996af90d Mon Sep 17 00:00:00 2001
+From 4c5971a6fcf7e948f7df4d0ce2ab0751060cb2ca Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@retroboot.org>
 Date: Fri, 19 Mar 2021 05:54:58 +0000
-Subject: [PATCH 01/11] apple/macbook21: Set default VRAM to 64MiB instead of
+Subject: [PATCH 01/18] apple/macbook21: Set default VRAM to 64MiB instead of
  8MiB
 
 ---
@@ -19,5 +19,5 @@ index cf1bc4566e..dc0df3b6d6 100644
 -gfx_uma_size=8M
 +gfx_uma_size=64M
 -- 
-2.25.1
+2.39.2
 

resources/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch

@@ -1,7 +1,7 @@
-From a43fee19b7a4615aceb9bdf96afda980c106445e Mon Sep 17 00:00:00 2001
+From ff523fd40649b72512b0f1253701509d83ca4a8d Mon Sep 17 00:00:00 2001
 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
 Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 02/11] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 02/18] add c3 and clockgen to apple/macbook21
 
 ---
  src/mainboard/apple/macbook21/Kconfig       |  1 +
@@ -46,10 +46,10 @@ index 13d06f0839..88b8669c61 100644
  
  int get_cst_entries(const acpi_cstate_t **entries)
 diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
-index bcce778cb1..16025d6fbb 100644
+index dd701da7ed..5587c48d1f 100644
 --- a/src/mainboard/apple/macbook21/devicetree.cb
 +++ b/src/mainboard/apple/macbook21/devicetree.cb
-@@ -104,7 +104,13 @@ chip northbridge/intel/i945
+@@ -100,7 +100,13 @@ chip northbridge/intel/i945
  			end
  			device pci 1f.3 on # SMBUS
  				subsystemid 0x8086 0x7270
@@ -64,5 +64,5 @@ index bcce778cb1..16025d6fbb 100644
  	end
  end
 -- 
-2.25.1
+2.39.2
 

resources/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch

@@ -1,7 +1,7 @@
-From 6302d89dfd785330944ad091767c7e7eb8da4aed Mon Sep 17 00:00:00 2001
+From fe79712702002bf2044227d6c3cef7ae022e3539 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@osboot.org>
 Date: Sun, 3 Jan 2021 03:34:01 +0000
-Subject: [PATCH 03/11] lenovo/x60: 64MiB Video RAM changed to default
+Subject: [PATCH 03/18] lenovo/x60: 64MiB Video RAM changed to default
  (previously it was 8MiB)
 
 ---
@@ -19,5 +19,5 @@ index 5c3576d1f3..88170a1aab 100644
 -gfx_uma_size=8M
 +gfx_uma_size=64M
 -- 
-2.25.1
+2.39.2
 

resources/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch

@@ -1,7 +1,7 @@
-From f13f10f6b61d0581970a508b626cd63adf607eff Mon Sep 17 00:00:00 2001
+From 79440902866bdafeec651476a5a0e51d42b43b21 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@osboot.org>
 Date: Mon, 22 Feb 2021 22:16:59 +0000
-Subject: [PATCH 04/11] lenovo/t60: make 64MiB VRAM the default in cmos.default
+Subject: [PATCH 04/18] lenovo/t60: make 64MiB VRAM the default in cmos.default
 
 ---
  src/mainboard/lenovo/t60/cmos.default | 2 +-
@@ -18,5 +18,5 @@ index af865f16da..7f03157df7 100644
 -gfx_uma_size=8M
 +gfx_uma_size=64M
 -- 
-2.25.1
+2.39.2
 

resources/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-352MiB-VRAM-by-default.patch

@@ -1,7 +1,7 @@
-From e3b971134ffc2f52e575efe53a571978ed291dc6 Mon Sep 17 00:00:00 2001
+From 73ca2562e77c971c2e581a414dc57b4b9aa544d7 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:10:33 +0100
-Subject: [PATCH 05/11] lenovo/t400: set VRAM to 352MiB VRAM by default
+Subject: [PATCH 05/18] lenovo/t400: set VRAM to 352MiB VRAM by default
 
 In the past, this caused stability issues so we set it to 256MiB. Nowadays,
 coreboot has fixed the issue preventing this. See:
@@ -23,5 +23,5 @@ index a326e315b1..e74d15d030 100644
 -gfx_uma_size=32M
 +gfx_uma_size=352M
 -- 
-2.25.1
+2.39.2
 

resources/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-352MiB-by-default.patch

@@ -1,7 +1,7 @@
-From 383c273f0c44eec93cd55c3d21d6c1a8316d8dbe Mon Sep 17 00:00:00 2001
+From badcbb2f07ac0e3d8b53a23e324f709bf93c3dd5 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:11:59 +0100
-Subject: [PATCH 06/11] lenovo/x200: set VRAM to 352MiB by default
+Subject: [PATCH 06/18] lenovo/x200: set VRAM to 352MiB by default
 
 This fix makes it possible:
 https://review.coreboot.org/c/coreboot/+/16831
@@ -20,5 +20,5 @@ index bb4323836e..33a6a69f59 100644
 -gfx_uma_size=32M
 +gfx_uma_size=352M
 -- 
-2.25.1
+2.39.2
 

resources/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-352MiB-by-default.patch

@@ -1,7 +1,7 @@
-From 4f4f957ea967cc94841746821144ee807747f540 Mon Sep 17 00:00:00 2001
+From 59e14decddd3a3d0eb9905196df045e34b7ce035 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:18:26 +0100
-Subject: [PATCH 07/11] gigabyte/ga-g41m-es2l: set VRAM to 352MiB by default
+Subject: [PATCH 07/18] gigabyte/ga-g41m-es2l: set VRAM to 352MiB by default
 
 ---
  src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
@@ -18,5 +18,5 @@ index 8372032119..3a9a8e2d72 100644
 -gfx_uma_size=64M
 +gfx_uma_size=352M
 -- 
-2.25.1
+2.39.2
 

resources/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-352MiB-by-default.patch

@@ -1,7 +1,7 @@
-From 1ee893f9fc5251968500695824ab9fd39461d318 Mon Sep 17 00:00:00 2001
+From 794e082e64558678fe245c86a2c81b4edc582795 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Fri, 14 May 2021 13:21:39 +0100
-Subject: [PATCH 08/11] acer/g43t-am3: set VRAM to 352MiB by default
+Subject: [PATCH 08/18] acer/g43t-am3: set VRAM to 352MiB by default
 
 ---
  src/mainboard/acer/g43t-am3/cmos.default | 2 +-
@@ -18,5 +18,5 @@ index 706f5dd551..98899e8bf5 100644
 -gfx_uma_size=64M
 +gfx_uma_size=352M
 -- 
-2.25.1
+2.39.2
 

resources/coreboot/default/patches/0009-Revert-cpu-intel-Configure-IA32_FEATURE_CONTROL-for-.patch

@@ -1,115 +0,0 @@
-From 8e8704050aec67490a6d1f272840e5a04ee1bcff Mon Sep 17 00:00:00 2001
-From: Rodrigo <rm@firemail.cc>
-Date: Mon, 23 Aug 2021 02:20:32 -0300
-Subject: [PATCH 09/11] Revert "cpu/intel: Configure IA32_FEATURE_CONTROL for
- alternative SMRR"
-
-This rendered at least the x200 unable to reboot.
-
-This reverts commit df7aecd92643d207feaf7fd840f8835097346644.
----
- src/cpu/intel/model_1067x/model_1067x_init.c |  3 +++
- src/cpu/intel/model_1067x/mp_init.c          | 26 --------------------
- src/cpu/intel/model_106cx/model_106cx_init.c |  3 +++
- src/cpu/intel/model_6ex/model_6ex_init.c     |  3 +++
- src/cpu/intel/model_6fx/model_6fx_init.c     |  3 +++
- 5 files changed, 12 insertions(+), 26 deletions(-)
-
-diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
-index 3e4de1fa31..ca3ce274fc 100644
---- a/src/cpu/intel/model_1067x/model_1067x_init.c
-+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
-@@ -274,6 +274,9 @@ static void model_1067x_init(struct device *cpu)
- 	/* Initialize the APIC timer */
- 	init_timer();
- 
-+	/* Set virtualization based on Kconfig option */
-+	set_vmx_and_lock();
-+
- 	/* Configure C States */
- 	configure_c_states(quad);
- 
-diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
-index bc53214310..72f40f6762 100644
---- a/src/cpu/intel/model_1067x/mp_init.c
-+++ b/src/cpu/intel/model_1067x/mp_init.c
-@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
- 	smm_initialize();
- }
- 
--#define SMRR_SUPPORTED (1 << 11)
--
- static void per_cpu_smm_trigger(void)
- {
--	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
--	if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
--		set_feature_ctrl_vmx();
--		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
--		/* We don't care if the lock is already setting
--		   as our smm relocation handler is able to handle
--		   setups where SMRR is not enabled here. */
--		if (ia32_ft_ctrl.lo & (1 << 0)) {
--			/* IA32_FEATURE_CONTROL locked. If we set it again we
--			   get an illegal instruction. */
--			printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
--			printk(BIOS_DEBUG, "SMRR status: %senabled\n",
--			       ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
--		} else {
--			if (!CONFIG(SET_IA32_FC_LOCK_BIT))
--				printk(BIOS_INFO,
--				       "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
--			ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
--			wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
--		}
--	} else {
--		set_vmx_and_lock();
--	}
--
- 	/* Relocate the SMM handler. */
- 	smm_relocate();
- }
-diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
-index 278d8dea81..a0917045dd 100644
---- a/src/cpu/intel/model_106cx/model_106cx_init.c
-+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
-@@ -70,6 +70,9 @@ static void model_106cx_init(struct device *cpu)
- 	/* Enable the local CPU APICs */
- 	setup_lapic();
- 
-+	/* Set virtualization based on Kconfig option */
-+	set_vmx_and_lock();
-+
- 	/* Configure C States */
- 	configure_c_states();
- 
-diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
-index 34646ad5e9..36cfd51f01 100644
---- a/src/cpu/intel/model_6ex/model_6ex_init.c
-+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
-@@ -109,6 +109,9 @@ static void model_6ex_init(struct device *cpu)
- 	/* Enable the local CPU APICs */
- 	setup_lapic();
- 
-+	/* Set virtualization based on Kconfig option */
-+	set_vmx_and_lock();
-+
- 	/* Configure C States */
- 	configure_c_states();
- 
-diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
-index 72ece23935..6f2d6ef599 100644
---- a/src/cpu/intel/model_6fx/model_6fx_init.c
-+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
-@@ -123,6 +123,9 @@ static void model_6fx_init(struct device *cpu)
- 	/* Enable the local CPU APICs */
- 	setup_lapic();
- 
-+	/* Set virtualization based on Kconfig option */
-+	set_vmx_and_lock();
-+
- 	/* Configure C States */
- 	configure_c_states();
- 
--- 
-2.25.1
-

resources/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch

@@ -1,7 +1,7 @@
-From c4ab3bd4c88d83ca3ca391519cec31fa7b7a6c2a Mon Sep 17 00:00:00 2001
+From 62121b837771b0b05f6490943ff9f1ccaba45bdb Mon Sep 17 00:00:00 2001
 From: persmule <persmule@gmail.com>
 Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 11/11] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 09/18] lenovo/t400: Enable all SATA ports
 
 There are 2 SATA ports on the chassis of t400(s), but at least one dock for
 t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -15,10 +15,10 @@ This patch unmasked all SATA ports found within t400s with factory firmware.
  1 file changed, 2 insertions(+), 2 deletions(-)
 
 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
-index 670b4883f3..1fc60d9b24 100644
+index 1df350ab67..21c8e2c9a1 100644
 --- a/src/mainboard/lenovo/t400/devicetree.cb
 +++ b/src/mainboard/lenovo/t400/devicetree.cb
-@@ -59,8 +59,8 @@ chip northbridge/intel/gm45
+@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
  			register "gpe0_en" = "0x01000000"
  			register "gpi1_routing"  = "2"
  
@@ -30,5 +30,5 @@ index 670b4883f3..1fc60d9b24 100644
  			register "sata_traffic_monitor"		= "0"
  
 -- 
-2.25.1
+2.39.2
 

resources/coreboot/default/patches/0010-Fix-missing-include.patch

@@ -1,63 +0,0 @@
-From e6960dec197491941254af48b60f1cf1592bcb2b Mon Sep 17 00:00:00 2001
-From: Rodrigo <rm@firemail.cc>
-Date: Mon, 23 Aug 2021 03:51:21 -0300
-Subject: [PATCH 10/11] Fix missing include
-
----
- src/cpu/intel/model_1067x/model_1067x_init.c | 1 +
- src/cpu/intel/model_106cx/model_106cx_init.c | 1 +
- src/cpu/intel/model_6ex/model_6ex_init.c     | 1 +
- src/cpu/intel/model_6fx/model_6fx_init.c     | 1 +
- 4 files changed, 4 insertions(+)
-
-diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
-index ca3ce274fc..cc7a5edca9 100644
---- a/src/cpu/intel/model_1067x/model_1067x_init.c
-+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
-@@ -9,6 +9,7 @@
- #include <cpu/x86/cache.h>
- #include <cpu/x86/name.h>
- #include <cpu/intel/smm_reloc.h>
-+#include <cpu/intel/common/common.h>
- 
- #include "chip.h"
- 
-diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
-index a0917045dd..7b88f19ee0 100644
---- a/src/cpu/intel/model_106cx/model_106cx_init.c
-+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
-@@ -8,6 +8,7 @@
- #include <cpu/intel/speedstep.h>
- #include <cpu/x86/cache.h>
- #include <cpu/x86/name.h>
-+#include <cpu/intel/common/common.h>
- 
- #define HIGHEST_CLEVEL		3
- static void configure_c_states(void)
-diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
-index 36cfd51f01..793474ffa5 100644
---- a/src/cpu/intel/model_6ex/model_6ex_init.c
-+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
-@@ -8,6 +8,7 @@
- #include <cpu/intel/speedstep.h>
- #include <cpu/x86/cache.h>
- #include <cpu/x86/name.h>
-+#include <cpu/intel/common/common.h>
- 
- #define HIGHEST_CLEVEL		3
- static void configure_c_states(void)
-diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
-index 6f2d6ef599..d0031ad741 100644
---- a/src/cpu/intel/model_6fx/model_6fx_init.c
-+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
-@@ -8,6 +8,7 @@
- #include <cpu/intel/speedstep.h>
- #include <cpu/x86/cache.h>
- #include <cpu/x86/name.h>
-+#include <cpu/intel/common/common.h>
- 
- #define HIGHEST_CLEVEL		3
- static void configure_c_states(void)
--- 
-2.25.1
-

resources/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch

@@ -0,0 +1,22 @@
+From 13d95d2bf44e1c950e317e7c6fbbe5d96174c48a Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 20 Dec 2021 01:29:31 +0000
+Subject: [PATCH 10/18] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
+ default
+
+---
+ src/mainboard/lenovo/x230/cmos.default | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
+index 7314066c2b..2e315d4521 100644
+--- a/src/mainboard/lenovo/x230/cmos.default
++++ b/src/mainboard/lenovo/x230/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ usb_always_on=Disable
+ f1_to_f12_as_primary=Enable
+ me_state=Normal
++gfx_uma_size=224M
+-- 
+2.39.2
+

resources/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch

@@ -0,0 +1,38 @@
+From fa8113f64fe320e0e75f3e53ccfa9037d3bdd074 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 3 Jan 2022 19:06:22 +0000
+Subject: [PATCH 11/18] lenovo/x230: set me_state=Disabled in cmos.default
+
+I only recently found out about this. It's possible to use me_cleaner to
+do the same thing, but some people might just flash coreboot and not do
+anything with the ME region
+
+With this change, the ME is set to disabled. It's my understanding that this
+will accomplish more or less the same thing as me_cleaner, without actually
+using that. Of course, I still recommend using me_cleaner
+
+I saw this when I audited coreboot's git history, and saw this:
+
+commit 833e9bad4762e0dca6c867d3a18dbaf6d5166be8
+Author: Evgeny Zinoviev <me@ch1p.io>
+Date:   Thu Nov 21 21:47:31 2019 +0300
+
+    sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode
+---
+ src/mainboard/lenovo/x230/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
+index 2e315d4521..3585cbd58b 100644
+--- a/src/mainboard/lenovo/x230/cmos.default
++++ b/src/mainboard/lenovo/x230/cmos.default
+@@ -15,5 +15,5 @@ trackpoint=Enable
+ backlight=Both
+ usb_always_on=Disable
+ f1_to_f12_as_primary=Enable
+-me_state=Normal
++me_state=Disabled
+ gfx_uma_size=224M
+-- 
+2.39.2
+

resources/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch

@@ -0,0 +1,100 @@
+From 4bb3d60a1a1dfb2dac6320cef491a99b728ed25a Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Wed, 2 Mar 2022 21:50:01 +0000
+Subject: [PATCH 12/18] set me_state=Disabled on all cmos.default files!
+
+yeah. why the hell isn't this the default
+---
+ src/mainboard/lenovo/l520/cmos.default  | 2 +-
+ src/mainboard/lenovo/t420/cmos.default  | 2 +-
+ src/mainboard/lenovo/t420s/cmos.default | 2 +-
+ src/mainboard/lenovo/t430/cmos.default  | 2 +-
+ src/mainboard/lenovo/t430s/cmos.default | 2 +-
+ src/mainboard/lenovo/t520/cmos.default  | 2 +-
+ src/mainboard/lenovo/t530/cmos.default  | 2 +-
+ src/mainboard/lenovo/x220/cmos.default  | 2 +-
+ 8 files changed, 8 insertions(+), 8 deletions(-)
+
+diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
+index 681c40e78b..57cdcf9162 100644
+--- a/src/mainboard/lenovo/l520/cmos.default
++++ b/src/mainboard/lenovo/l520/cmos.default
+@@ -14,4 +14,4 @@ sticky_fn=Disable
+ trackpoint=Enable
+ backlight=Both
+ usb_always_on=Disable
+-me_state=Normal
++me_state=Disabled
+diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
+index 8244071b8a..c011867916 100644
+--- a/src/mainboard/lenovo/t420/cmos.default
++++ b/src/mainboard/lenovo/t420/cmos.default
+@@ -14,4 +14,4 @@ sticky_fn=Disable
+ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+-me_state=Normal
++me_state=Disabled
+diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
+index 8244071b8a..c011867916 100644
+--- a/src/mainboard/lenovo/t420s/cmos.default
++++ b/src/mainboard/lenovo/t420s/cmos.default
+@@ -14,4 +14,4 @@ sticky_fn=Disable
+ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+-me_state=Normal
++me_state=Disabled
+diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
+index 26795fe5cf..55e1e6c04e 100644
+--- a/src/mainboard/lenovo/t430/cmos.default
++++ b/src/mainboard/lenovo/t430/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ backlight=Both
+ usb_always_on=Disable
+ hybrid_graphics_mode=Integrated Only
+-me_state=Normal
++me_state=Disabled
+diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
+index 52dbf70377..b16800ca9e 100644
+--- a/src/mainboard/lenovo/t430s/cmos.default
++++ b/src/mainboard/lenovo/t430s/cmos.default
+@@ -16,4 +16,4 @@ backlight=Both
+ enable_dual_graphics=Disable
+ usb_always_on=Disable
+ f1_to_f12_as_primary=Enable
+-me_state=Normal
++me_state=Disabled
+diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
+index cf79b391e2..b66f7034dc 100644
+--- a/src/mainboard/lenovo/t520/cmos.default
++++ b/src/mainboard/lenovo/t520/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+-me_state=Normal
++me_state=Disabled
+diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
+index cf79b391e2..b66f7034dc 100644
+--- a/src/mainboard/lenovo/t530/cmos.default
++++ b/src/mainboard/lenovo/t530/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+-me_state=Normal
++me_state=Disabled
+diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
+index 6d1d57a795..52f303dfdb 100644
+--- a/src/mainboard/lenovo/x220/cmos.default
++++ b/src/mainboard/lenovo/x220/cmos.default
+@@ -13,4 +13,4 @@ usb_always_on=Disable
+ fn_ctrl_swap=Disable
+ sticky_fn=Disable
+ trackpoint=Enable
+-me_state=Normal
++me_state=Disabled
+-- 
+2.39.2
+

resources/coreboot/default/patches/0014-lenovo-x230-introduce-FHD-variant.patch

@@ -0,0 +1,198 @@
+From f60a7e12526ca254b1d98830ad1e31296984e815 Mon Sep 17 00:00:00 2001
+From: Alexander Couzens <lynxis@fe80.eu>
+Date: Sat, 19 Mar 2022 13:42:33 +0000
+Subject: [PATCH 14/18] lenovo/x230: introduce FHD variant
+
+There is a modification for the x230 which uses the 2nd DP from the dock
+as the integrated panel's connection, which allows using a custom eDP
+panel instead of the stock LVDS display.
+
+There are several adapter boards present on the market and all of them
+uses the same method of enabling the custom eDP panel.
+
+To make this work with coreboot, the internal LVDS connector should be
+disabled in libgfxinit. The VBT has been modified as well, which allows
+brightness controls to work out of the box.
+
+The modifications done to the VBT are:
+- Remove the LVDS port entry.
+- Move the DP-3 (which is the 2nd DP on the dock) entry to the first
+  position on the list.
+- Set the DP-3 as internally connected.
+
+This has been reported to work with the following panels:
+- LP125WF2-SPB4 (1920*1080, 12.5")
+- LQ125T1JW02 (2560*1440, 12.5")
+- LQ133M1JW21 (1920*1080, 13.3")
+- LTN133HL10-201 (1920*1080, 13.3")
+- B133HAN04.6 (1920*1080, 13.3")
+- B133QAN02.0 (2560*1600, 13.3")
+
+Other eDP panels not on this list should work as well.
+
+Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0
+Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
+Signed-off-by: Felix Singer <felixsinger@posteo.net>
+---
+ src/mainboard/lenovo/x230/Kconfig             |  15 ++++++++-----
+ src/mainboard/lenovo/x230/Kconfig.name        |   3 +++
+ src/mainboard/lenovo/x230/Makefile.inc        |   5 +++++
+ .../lenovo/x230/variants/x230_edp/data.vbt    | Bin 0 -> 4281 bytes
+ .../x230/variants/x230_edp/gma-mainboard.ads  |  21 ++++++++++++++++++
+ 5 files changed, 38 insertions(+), 6 deletions(-)
+ create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
+ create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
+
+diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
+index f9667267d5..4d8325ea43 100644
+--- a/src/mainboard/lenovo/x230/Kconfig
++++ b/src/mainboard/lenovo/x230/Kconfig
+@@ -1,4 +1,4 @@
+-if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S
++if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
+ 
+ config BOARD_SPECIFIC_OPTIONS
+ 	def_bool y
+@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select H8_HAS_BAT_THRESHOLDS_IMPL
+ 	select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S
+ 	select NO_UART_ON_SUPERIO
+-	select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
++	select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
+ 	select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S
+ 	select HAVE_ACPI_TABLES
+ 	select HAVE_OPTION_TABLE
+@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select INTEL_INT15
+ 	select DRIVERS_RICOH_RCE822
+ 	select MEMORY_MAPPED_TPM
+-	select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
++	select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
+ 	select MAINBOARD_HAS_LIBGFXINIT
+ 	select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+ 	select INTEL_GMA_HAVE_VBT
+@@ -51,17 +51,20 @@ config MAINBOARD_DIR
+ 	default "lenovo/x230"
+ 
+ config VARIANT_DIR
+-	default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
++	default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
+ 	default "x230s" if BOARD_LENOVO_X230S
+ 
+ config MAINBOARD_PART_NUMBER
+-	default "ThinkPad X230" if BOARD_LENOVO_X230
++	default "ThinkPad X230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230_EDP
+ 	default "ThinkPad X230t" if BOARD_LENOVO_X230T
+ 	default "ThinkPad X230s" if BOARD_LENOVO_X230S
+ 
+ config OVERRIDE_DEVICETREE
+ 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+ 
++config INTEL_GMA_VBT_FILE
++	default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
++
+ config USBDEBUG_HCD_INDEX
+ 	int
+ 	default 2
+@@ -83,4 +86,4 @@ config PS2M_EISAID
+ config THINKPADEC_HKEY_EISAID
+ 	default "LEN0068"
+ 
+-endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ||  BOARD_LENOVO_X230S
++endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ||  BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
+diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name
+index 1a01436879..e7290a12dd 100644
+--- a/src/mainboard/lenovo/x230/Kconfig.name
++++ b/src/mainboard/lenovo/x230/Kconfig.name
+@@ -6,3 +6,6 @@ config BOARD_LENOVO_X230T
+ 
+ config BOARD_LENOVO_X230S
+ 	bool "ThinkPad X230s"
++
++config BOARD_LENOVO_X230_EDP
++	bool "ThinkPad X230 eDP Mod (2K/FHD)"
+diff --git a/src/mainboard/lenovo/x230/Makefile.inc b/src/mainboard/lenovo/x230/Makefile.inc
+index 8e801f145d..6e6f9f90b9 100644
+--- a/src/mainboard/lenovo/x230/Makefile.inc
++++ b/src/mainboard/lenovo/x230/Makefile.inc
+@@ -5,4 +5,9 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
+ romstage-y += variants/$(VARIANT_DIR)/early_init.c
+ romstage-y += variants/$(VARIANT_DIR)/gpio.c
+ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
++
++ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y)
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads
++else
+ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
++endif
+diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt b/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
+GIT binary patch
+literal 4281
+zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^
+zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
+zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
+zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
+zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
+zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
+z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
+zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
+z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
+z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
+zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT
+zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
+z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}(
+z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg
+zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW>
+zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn
+zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L
+zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy;
+z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY
+zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
+zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
+zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
+z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
+zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
+zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
+zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
+z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
+zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
+zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH
+z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
+zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
+p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
+new file mode 100644
+index 0000000000..f7cf0bc264
+--- /dev/null
++++ b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
+@@ -0,0 +1,21 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (DP1,
++      DP2,
++      DP3,
++      HDMI1,
++      HDMI2,
++      HDMI3,
++      Analog,
++      others => Disabled);
++
++end GMA.Mainboard;
+-- 
+2.39.2
+

resources/coreboot/default/patches/0015-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch

@@ -0,0 +1,25 @@
+From b8bb450bef9f9a486917115bfe78519838558300 Mon Sep 17 00:00:00 2001
+From: Alexei Sorokin <sor.alexei@meowr.ru>
+Date: Sun, 27 Nov 2022 18:36:26 +0300
+Subject: [PATCH 15/18] lenovo/x230: fix the data.vbt path for the EDP variant
+
+---
+ src/mainboard/lenovo/x230/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
+index 4d8325ea43..409892f3ab 100644
+--- a/src/mainboard/lenovo/x230/Kconfig
++++ b/src/mainboard/lenovo/x230/Kconfig
+@@ -63,7 +63,7 @@ config OVERRIDE_DEVICETREE
+ 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+ 
+ config INTEL_GMA_VBT_FILE
+-	default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
++       default "src/mainboard/\$(MAINBOARDDIR)/variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
+ 
+ config USBDEBUG_HCD_INDEX
+ 	int
+-- 
+2.39.2
+

resources/coreboot/default/patches/0016-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch

@@ -0,0 +1,205 @@
+From 32a961895ed41cd2bb1f9ae00ab0200c4bfb0bf3 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 19 Feb 2023 18:21:43 +0000
+Subject: [PATCH 16/18] util/ifdtool: add --nuke flag (all 0xFF on region)
+
+When this option is used, the region's contents are overwritten
+with all ones (0xFF).
+
+Example:
+
+./ifdtool --nuke gbe coreboot.rom
+./ifdtool --nuke bios coreboot.com
+./ifdtool --nuke me coreboot.com
+
+Rebased since the last revision update in lbmk.
+---
+ util/ifdtool/ifdtool.c | 117 ++++++++++++++++++++++++++++++-----------
+ 1 file changed, 85 insertions(+), 32 deletions(-)
+
+diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
+index 98afa4bbcf..5509721018 100644
+--- a/util/ifdtool/ifdtool.c
++++ b/util/ifdtool/ifdtool.c
+@@ -1771,6 +1771,7 @@ static void print_usage(const char *name)
+ 	       "                                         wbg    - Wellsburg\n"
+ 	       "   -S | --setpchstrap                    Write a PCH strap\n"
+ 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
++	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
+ 	       "   -v | --version:                       print the version\n"
+ 	       "   -h | --help:                          print this help\n\n"
+ 	       "<region> is one of Descriptor, BIOS, ME, GbE, Platform Data, Secondary BIOS, "
+@@ -1778,13 +1779,70 @@ static void print_usage(const char *name)
+ 	       "\n");
+ }
+ 
++static int                                                                     
++get_region_type_string(const char *region_type_string)                         
++{                                                                              
++	if (region_type_string == NULL)
++		return -1;
++	else if (!strcasecmp("Descriptor", region_type_string))
++		region_type = 0;
++	else if (!strcasecmp("BIOS", region_type_string))
++		region_type = 1;
++	else if (!strcasecmp("ME", region_type_string))
++		region_type = 2;
++	else if (!strcasecmp("GbE", region_type_string))
++		region_type = 3;
++	else if (!strcasecmp("Platform Data", region_type_string))
++		region_type = 4;
++	else if (!strcasecmp("Device Exp1", region_type_string))
++		region_type = 5;
++	else if (!strcasecmp("Secondary BIOS", region_type_string))
++		region_type = 6;
++	else if (!strcasecmp("Reserved", region_type_string))
++		region_type = 7;
++	else if (!strcasecmp("EC", region_type_string))
++		region_type = 8;
++	else if (!strcasecmp("Device Exp2", region_type_string))
++		region_type = 9;
++	else if (!strcasecmp("IE", region_type_string))
++		region_type = 10;
++	else if (!strcasecmp("10GbE_0", region_type_string))
++		region_type = 11;
++	else if (!strcasecmp("10GbE_1", region_type_string))
++		region_type = 12;
++	else if (!strcasecmp("PTT", region_type_string))
++		region_type = 15;
++	else
++		return -1;
++}
++
++static void                                                                    
++nuke(const char *filename, char *image, int size, int region_type)             
++{                                                                              
++       int i;                                                                  
++       region_t region;                                                        
++       const frba_t *frba = find_frba(image, size);                            
++       if (!frba)                                                              
++               exit(EXIT_FAILURE);                                             
++                                                                               
++       region = get_region(frba, region_type);                                 
++       if (region.size > 0) {                                                  
++               for (i = region.base; i <= region.limit; i++) {                 
++                       if ((i + 1) > (size))                                   
++                               break;                                          
++                       image[i] = 0xFF;                                        
++               }                                                               
++               write_image(filename, image, size);                             
++       }                                                                       
++} 
++
+ int main(int argc, char *argv[])
+ {
+ 	int opt, option_index = 0;
+ 	int mode_dump = 0, mode_extract = 0, mode_inject = 0, mode_spifreq = 0;
+ 	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
+ 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
+-	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0;
++	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_nuke = 0;
+ 	char *region_type_string = NULL, *region_fname = NULL;
+ 	const char *layout_fname = NULL;
+ 	char *new_filename = NULL;
+@@ -1815,6 +1873,7 @@ int main(int argc, char *argv[])
+ 		{"validate", 0, NULL, 't'},
+ 		{"setpchstrap", 1, NULL, 'S'},
+ 		{"newvalue", 1, NULL, 'V'},
++		{"nuke", 1, NULL, 'N'},
+ 		{0, 0, 0, 0}
+ 	};
+ 
+@@ -1855,35 +1914,8 @@ int main(int argc, char *argv[])
+ 			region_fname++;
+ 			// Descriptor, BIOS, ME, GbE, Platform
+ 			// valid type?
+-			if (!strcasecmp("Descriptor", region_type_string))
+-				region_type = 0;
+-			else if (!strcasecmp("BIOS", region_type_string))
+-				region_type = 1;
+-			else if (!strcasecmp("ME", region_type_string))
+-				region_type = 2;
+-			else if (!strcasecmp("GbE", region_type_string))
+-				region_type = 3;
+-			else if (!strcasecmp("Platform Data", region_type_string))
+-				region_type = 4;
+-			else if (!strcasecmp("Device Exp1", region_type_string))
+-				region_type = 5;
+-			else if (!strcasecmp("Secondary BIOS", region_type_string))
+-				region_type = 6;
+-			else if (!strcasecmp("Reserved", region_type_string))
+-				region_type = 7;
+-			else if (!strcasecmp("EC", region_type_string))
+-				region_type = 8;
+-			else if (!strcasecmp("Device Exp2", region_type_string))
+-				region_type = 9;
+-			else if (!strcasecmp("IE", region_type_string))
+-				region_type = 10;
+-			else if (!strcasecmp("10GbE_0", region_type_string))
+-				region_type = 11;
+-			else if (!strcasecmp("10GbE_1", region_type_string))
+-				region_type = 12;
+-			else if (!strcasecmp("PTT", region_type_string))
+-				region_type = 15;
+-			if (region_type == -1) {
++			if ((region_type =
++			    get_region_type_string(region_type_string)) == -1) {
+ 				fprintf(stderr, "No such region type: '%s'\n\n",
+ 					region_type_string);
+ 				print_usage(argv[0]);
+@@ -2050,6 +2082,22 @@ int main(int argc, char *argv[])
+ 		case 't':
+ 			mode_validate = 1;
+ 			break;
++		case 'N':
++			region_type_string = strdup(optarg);
++			if (!region_type_string) {
++				fprintf(stderr, "No region specified\n");
++				print_usage(argv[0]);
++				exit(EXIT_FAILURE);
++			}
++			if ((region_type =
++			    get_region_type_string(region_type_string)) == -1) {
++				fprintf(stderr, "No such region type: '%s'\n\n",
++					region_type_string);
++				print_usage(argv[0]);
++				exit(EXIT_FAILURE);
++			}
++			mode_nuke = 1;
++			break;
+ 		case 'v':
+ 			print_version();
+ 			exit(EXIT_SUCCESS);
+@@ -2065,7 +2113,7 @@ int main(int argc, char *argv[])
+ 
+ 	if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_setstrap +
+ 		mode_newlayout + (mode_spifreq | mode_em100 | mode_unlocked |
+-		 mode_locked) + mode_altmedisable + mode_validate) > 1) {
++		 mode_locked) + mode_altmedisable + mode_validate + mode_nuke) > 1) {
+ 		fprintf(stderr, "You may not specify more than one mode.\n\n");
+ 		print_usage(argv[0]);
+ 		exit(EXIT_FAILURE);
+@@ -2073,7 +2121,8 @@ int main(int argc, char *argv[])
+ 
+ 	if ((mode_dump + mode_layout + mode_extract + mode_inject + mode_setstrap +
+ 	     mode_newlayout + mode_spifreq + mode_em100 + mode_locked +
+-	     mode_unlocked + mode_density + mode_altmedisable + mode_validate) == 0) {
++	     mode_unlocked + mode_density + mode_altmedisable + mode_validate +
++	     mode_nuke) == 0) {
+ 		fprintf(stderr, "You need to specify a mode.\n\n");
+ 		print_usage(argv[0]);
+ 		exit(EXIT_FAILURE);
+@@ -2171,6 +2220,10 @@ int main(int argc, char *argv[])
+ 		write_image(new_filename, image, size);
+ 	}
+ 
++	if (mode_nuke) {
++		nuke(new_filename, image, size, region_type);
++	}
++
+ 	if (mode_altmedisable) {
+ 		fpsba_t *fpsba = find_fpsba(image, size);
+ 		fmsba_t *fmsba = find_fmsba(image, size);
+-- 
+2.39.2
+

resources/coreboot/default/patches/0017-util-ifdtool-fix-bad-patch.patch

@@ -0,0 +1,65 @@
+From 05b8acae9a88b8dd13dd96facca30e4662399053 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 19 Feb 2023 23:20:10 +0000
+Subject: [PATCH 17/18] util/ifdtool: fix bad patch
+
+i messed up the "rebase" a few lbmk commits ago
+---
+ util/ifdtool/ifdtool.c | 28 ++++++++++++++--------------
+ 1 file changed, 14 insertions(+), 14 deletions(-)
+
+diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
+index 5509721018..89feb99536 100644
+--- a/util/ifdtool/ifdtool.c
++++ b/util/ifdtool/ifdtool.c
+@@ -1785,33 +1785,33 @@ get_region_type_string(const char *region_type_string)
+ 	if (region_type_string == NULL)
+ 		return -1;
+ 	else if (!strcasecmp("Descriptor", region_type_string))
+-		region_type = 0;
++		return 0;
+ 	else if (!strcasecmp("BIOS", region_type_string))
+-		region_type = 1;
++		return 1;
+ 	else if (!strcasecmp("ME", region_type_string))
+-		region_type = 2;
++		return 2;
+ 	else if (!strcasecmp("GbE", region_type_string))
+-		region_type = 3;
++		return 3;
+ 	else if (!strcasecmp("Platform Data", region_type_string))
+-		region_type = 4;
++		return 4;
+ 	else if (!strcasecmp("Device Exp1", region_type_string))
+-		region_type = 5;
++		return 5;
+ 	else if (!strcasecmp("Secondary BIOS", region_type_string))
+-		region_type = 6;
++		return 6;
+ 	else if (!strcasecmp("Reserved", region_type_string))
+-		region_type = 7;
++		return 7;
+ 	else if (!strcasecmp("EC", region_type_string))
+-		region_type = 8;
++		return 8;
+ 	else if (!strcasecmp("Device Exp2", region_type_string))
+-		region_type = 9;
++		return 9;
+ 	else if (!strcasecmp("IE", region_type_string))
+-		region_type = 10;
++		return 10;
+ 	else if (!strcasecmp("10GbE_0", region_type_string))
+-		region_type = 11;
++		return 11;
+ 	else if (!strcasecmp("10GbE_1", region_type_string))
+-		region_type = 12;
++		return 12;
+ 	else if (!strcasecmp("PTT", region_type_string))
+-		region_type = 15;
++		return 15;
+ 	else
+ 		return -1;
+ }
+-- 
+2.39.2
+

resources/coreboot/default/patches/0018-ich9m-boards-set-256MB-VRAM-instead.patch

@@ -0,0 +1,56 @@
+From 30d8dd45ab489bed21398b04bd03a54e08eafaf2 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sat, 4 Mar 2023 23:55:41 +0000
+Subject: [PATCH 18/18] ich9m boards: set 256MB VRAM instead
+
+352MB causes some stability issues reported by a few people
+---
+ src/mainboard/acer/g43t-am3/cmos.default         | 2 +-
+ src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
+ src/mainboard/lenovo/t400/cmos.default           | 2 +-
+ src/mainboard/lenovo/x200/cmos.default           | 2 +-
+ 4 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
+index 98899e8bf5..e8b45ea22c 100644
+--- a/src/mainboard/acer/g43t-am3/cmos.default
++++ b/src/mainboard/acer/g43t-am3/cmos.default
+@@ -3,4 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=352M
++gfx_uma_size=256M
+diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+index 3a9a8e2d72..bedad54d2a 100644
+--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
++++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+-gfx_uma_size=352M
++gfx_uma_size=256M
+diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
+index e74d15d030..b907a3e2df 100644
+--- a/src/mainboard/lenovo/t400/cmos.default
++++ b/src/mainboard/lenovo/t400/cmos.default
+@@ -13,4 +13,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ hybrid_graphics_mode=Integrated Only
+-gfx_uma_size=352M
++gfx_uma_size=256M
+diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
+index 33a6a69f59..458b3f19c5 100644
+--- a/src/mainboard/lenovo/x200/cmos.default
++++ b/src/mainboard/lenovo/x200/cmos.default
+@@ -12,4 +12,4 @@ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+-gfx_uma_size=352M
++gfx_uma_size=256M
+-- 
+2.39.2
+

resources/coreboot/default/patches/0019-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch

@@ -0,0 +1,47 @@
+From 3cf315fd59f1388d60cce9290eb52bccb7b29625 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Wed, 1 Dec 2021 02:53:00 +0000
+Subject: [PATCH 1/2] fix speedstep on x200/t400: Revert
+ "cpu/intel/model_1067x: enable PECI"
+
+This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
+
+Enabling PECI without microcode updates loaded causes the CPUID feature set
+to become corrupted. And one consequence is broken SpeedStep. At least, that's
+my understanding looking at Intel Errata. This revert is not a fix, because
+upstream is correct (upstream assumes microcode updates). We will simply
+maintain this revert patch in Libreboot, from now on.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 315e7c36fc..1423fd72bc 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
+ 	wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
+ }
+ 
+-#define IA32_PECI_CTL		0x5a0
+-
+ static void configure_misc(const int eist, const int tm2, const int emttm)
+ {
+ 	msr_t msr;
+@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
+ 		msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
+ 		wrmsr(IA32_MISC_ENABLE, msr);
+ 	}
+-
+-	/* Enable PECI
+-	   WARNING: due to Erratum AW67 described in Intel document #318733
+-	   the microcode must be updated before this MSR is written to. */
+-	msr = rdmsr(IA32_PECI_CTL);
+-	msr.lo |= 1;
+-	wrmsr(IA32_PECI_CTL, msr);
+ }
+ 
+ #define PIC_SENS_CFG	0x1aa
+-- 
+2.40.0
+

resources/coreboot/default/patches/0020-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch

@@ -0,0 +1,173 @@
+From 651292a204b00d7a39d8722f9d26fd9d7178fba2 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 17 Apr 2023 15:49:57 +0100
+Subject: [PATCH 1/1] GM45-type CPUs: don't enable alternative SMRR
+
+This reverts the changes in coreboot revision:
+df7aecd92643d207feaf7fd840f8835097346644
+
+While this fix is *technically correct*, the one in
+coreboot, it breaks rebooting as tested on several
+GM45 ThinkPads e.g. X200, T400, when microcode
+updates are not applied.
+
+Since November 2022, Libreboot includes microcode
+updates by default, but it tells users how to remove
+it from the ROM (with cbfstool) if they wish.
+
+Well, with Libreboot 20221214, 20230319 and 20230413,
+mitigations present in Libreboot 20220710 (which did
+not have microcode updates) do not exist.
+
+This patch, along with the other patch to remove PECI
+support (which breaks speedstep when microcode updates
+are not applied) have now been re-added to Libreboot.
+
+It is still best to use microcode updates by default.
+These patches in coreboot are not critically urgent,
+and you can use the machines with or without them,
+regardless of ucode.
+
+I'll probably re-write this and the other patch at
+some point, applying the change conditionally upon
+whether or not microcode is applied.
+
+Pragmatism is a good thing. I recommend it.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c |  4 +++
+ src/cpu/intel/model_1067x/mp_init.c          | 26 --------------------
+ src/cpu/intel/model_106cx/model_106cx_init.c |  4 +++
+ src/cpu/intel/model_6ex/model_6ex_init.c     |  4 +++
+ src/cpu/intel/model_6fx/model_6fx_init.c     |  4 +++
+ 5 files changed, 16 insertions(+), 26 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 1423fd72bc..d1f98ca43a 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -8,6 +8,7 @@
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
+ #include <cpu/intel/smm_reloc.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define MSR_BBL_CR_CTL3		0x11e
+ 
+@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states(quad);
+ 
+diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
+index bc53214310..72f40f6762 100644
+--- a/src/cpu/intel/model_1067x/mp_init.c
++++ b/src/cpu/intel/model_1067x/mp_init.c
+@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
+ 	smm_initialize();
+ }
+ 
+-#define SMRR_SUPPORTED (1 << 11)
+-
+ static void per_cpu_smm_trigger(void)
+ {
+-	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+-	if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
+-		set_feature_ctrl_vmx();
+-		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
+-		/* We don't care if the lock is already setting
+-		   as our smm relocation handler is able to handle
+-		   setups where SMRR is not enabled here. */
+-		if (ia32_ft_ctrl.lo & (1 << 0)) {
+-			/* IA32_FEATURE_CONTROL locked. If we set it again we
+-			   get an illegal instruction. */
+-			printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
+-			printk(BIOS_DEBUG, "SMRR status: %senabled\n",
+-			       ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
+-		} else {
+-			if (!CONFIG(SET_IA32_FC_LOCK_BIT))
+-				printk(BIOS_INFO,
+-				       "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
+-			ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
+-			wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
+-		}
+-	} else {
+-		set_vmx_and_lock();
+-	}
+-
+ 	/* Relocate the SMM handler. */
+ 	smm_relocate();
+ }
+diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
+index 05f5f327cc..0450c2ad83 100644
+--- a/src/cpu/intel/model_106cx/model_106cx_init.c
++++ b/src/cpu/intel/model_106cx/model_106cx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
+index 5bd1c32815..f3bb08cde3 100644
+--- a/src/cpu/intel/model_6ex/model_6ex_init.c
++++ b/src/cpu/intel/model_6ex/model_6ex_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
+index 535fb8fae7..f7b05facd2 100644
+--- a/src/cpu/intel/model_6fx/model_6fx_init.c
++++ b/src/cpu/intel/model_6fx/model_6fx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+-- 
+2.40.0
+

resources/coreboot/default/patches/0021-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch

@@ -0,0 +1,28 @@
+From 521a2edd13050fa39c896bf4f481ff0021c9213e Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sat, 6 May 2023 15:53:41 -0600
+Subject: [PATCH] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
+ models
+
+Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6400/devicetree.cb | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
+index bb954cbd7b..e9f3915d17 100644
+--- a/src/mainboard/dell/e6400/devicetree.cb
++++ b/src/mainboard/dell/e6400/devicetree.cb
+@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
+ 		ops gm45_pci_domain_ops
+ 
+ 		device pci 00.0 on end # host bridge
+-		device pci 01.0 off end
++		device pci 01.0 on end
+ 		device pci 02.0 on end # VGA
+ 		device pci 02.1 on end # Display
+ 		device pci 03.0 on end # ME
+-- 
+2.40.1
+

resources/coreboot/default/patches/0022-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -0,0 +1,38 @@
+From 1ce4f118b024a6367382b46016781f30fe622e3e Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 12 May 2023 19:55:15 -0600
+Subject: [PATCH] Remove warning for coreboot images built without a payload
+
+I added this in upstream to prevent people from accidentally flashing
+roms without a payload resulting in a no boot situation, but in
+libreboot lbmk handles the payload and thus this warning always comes
+up. This has caused confusion and concern so just patch it out.
+---
+ payloads/Makefile.inc | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/payloads/Makefile.inc b/payloads/Makefile.inc
+index e735443a76..4f1692a873 100644
+--- a/payloads/Makefile.inc
++++ b/payloads/Makefile.inc
+@@ -49,16 +49,5 @@ distclean-payloads:
+ print-repo-info-payloads:
+ 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
+ 
+-ifeq ($(CONFIG_PAYLOAD_NONE),y)
+-files_added:: warn_no_payload
+-endif
+-
+-warn_no_payload:
+-	printf "\n\t** WARNING **\n"
+-	printf "coreboot has been built without a payload. Writing\n"
+-	printf "a coreboot image without a payload to your board's\n"
+-	printf "flash chip will result in a non-booting system. You\n"
+-	printf "can use cbfstool to add a payload to the image.\n\n"
+-
+ .PHONY: force-payload coreinfo nvramcui
+-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
+-- 
+2.40.1
+

resources/coreboot/default/patches/0023-mb-dell-e6400-acpi-Route-Ricoh-R5C847-PCI-IRQ-lines-.patch

@@ -0,0 +1,125 @@
+From 5c1455495e8d2030473d8194fcf2e1d1111696b7 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Tue, 23 May 2023 20:59:56 -0600
+Subject: [PATCH] mb/dell/e6400/acpi: Route Ricoh R5C847 PCI IRQ lines as DBC
+
+Based on the schematic and vendor ASL code, PCI interrupt lines ABC of
+the Ricoh R5C847 PC Card/Media Card/FireWire controller are routed DBC.
+From lspci and the schematic this chip is PCI device 1. The original
+config copied from the T400 was routed ABCD->BCDA, causing Linux to
+issue an "irq 18: nobody cared" message when inserting an SD card.
+This is fixed by this patch and the SD card now works properly.
+
+Change-Id: Iede1de72d5369f1aebbac170792733739add3431
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/75411
+Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../dell/e6400/acpi/ich9_pci_irqs.asl         | 85 ++-----------------
+ 1 file changed, 8 insertions(+), 77 deletions(-)
+
+diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
+index 21066fbf3b..9a4cdfb75b 100644
+--- a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
++++ b/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
+@@ -4,87 +4,18 @@
+  * 0:1e.0 PCI bridge of the ICH9
+  */
+ 
+-/* TODO: which slots are actually relevant? */
+ If (PICM) {
+ 	Return (Package() {
+-		// PCI Slot 1 routes ABCD
+-		Package() { 0x0000ffff, 0, 0, 16},
+-		Package() { 0x0000ffff, 1, 0, 17},
+-		Package() { 0x0000ffff, 2, 0, 18},
+-		Package() { 0x0000ffff, 3, 0, 19},
+-
+-		// PCI Slot 2 routes BCDA
+-		Package() { 0x0001ffff, 0, 0, 17},
+-		Package() { 0x0001ffff, 1, 0, 18},
+-		Package() { 0x0001ffff, 2, 0, 19},
+-		Package() { 0x0001ffff, 3, 0, 16},
+-
+-		// PCI Slot 3 routes CDAB
+-		Package() { 0x0002ffff, 0, 0, 18},
+-		Package() { 0x0002ffff, 1, 0, 19},
+-		Package() { 0x0002ffff, 2, 0, 16},
+-		Package() { 0x0002ffff, 3, 0, 17},
+-
+-		// PCI Slot 4 routes ABCD
+-		Package() { 0x0003ffff, 0, 0, 16},
+-		Package() { 0x0003ffff, 1, 0, 17},
+-		Package() { 0x0003ffff, 2, 0, 18},
+-		Package() { 0x0003ffff, 3, 0, 19},
+-
+-		// PCI Slot 5 routes ABCD
+-		Package() { 0x0004ffff, 0, 0, 16},
+-		Package() { 0x0004ffff, 1, 0, 17},
+-		Package() { 0x0004ffff, 2, 0, 18},
+-		Package() { 0x0004ffff, 3, 0, 19},
+-
+-		// PCI Slot 6 routes BCDA
+-		Package() { 0x0005ffff, 0, 0, 17},
+-		Package() { 0x0005ffff, 1, 0, 18},
+-		Package() { 0x0005ffff, 2, 0, 19},
+-		Package() { 0x0005ffff, 3, 0, 16},
+-
+-		// FIXME: what's this supposed to mean? (adopted from ich7)
+-		//Package() { 0x0008ffff, 0, 0, 20},
++		// PCI Device 1, Ricoh R5C847 routes DBC
++		Package() { 0x0001ffff, 0, 0, 19},
++		Package() { 0x0001ffff, 1, 0, 17},
++		Package() { 0x0001ffff, 2, 0, 18},
+ 	})
+ } Else {
+ 	Return (Package() {
+-		// PCI Slot 1 routes ABCD
+-		Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+-		Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+-		Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+-		Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+-
+-		// PCI Slot 2 routes BCDA
+-		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+-		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+-		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+-		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+-
+-		// PCI Slot 3 routes CDAB
+-		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKC, 0},
+-		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKD, 0},
+-		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKA, 0},
+-		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKB, 0},
+-
+-		// PCI Slot 4 routes ABCD
+-		Package() { 0x0003ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+-		Package() { 0x0003ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+-		Package() { 0x0003ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+-		Package() { 0x0003ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+-
+-		// PCI Slot 5 routes ABCD
+-		Package() { 0x0004ffff, 0, \_SB.PCI0.LPCB.LNKA, 0},
+-		Package() { 0x0004ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
+-		Package() { 0x0004ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+-		Package() { 0x0004ffff, 3, \_SB.PCI0.LPCB.LNKD, 0},
+-
+-		// PCI Slot 6 routes BCDA
+-		Package() { 0x0005ffff, 0, \_SB.PCI0.LPCB.LNKB, 0},
+-		Package() { 0x0005ffff, 1, \_SB.PCI0.LPCB.LNKC, 0},
+-		Package() { 0x0005ffff, 2, \_SB.PCI0.LPCB.LNKD, 0},
+-		Package() { 0x0005ffff, 3, \_SB.PCI0.LPCB.LNKA, 0},
+-
+-		// FIXME
+-		// Package() { 0x0008ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
++		// PCI Device 1, Ricoh R5C847 routes DBC
++		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0},
++		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0},
++		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0},
+ 	})
+ }
+-- 
+2.41.0
+

resources/coreboot/default/patches/0024-Add-HP-8300-USDT-port.patch

@@ -0,0 +1,865 @@
+From c2bc778648e649cc6f0a60d51d1124c1741f35d7 Mon Sep 17 00:00:00 2001
+From: Riku Viitanen <riku.viitanen@protonmail.com>
+Date: Fri, 16 Jun 2023 23:03:43 +0300
+Subject: [PATCH] Add HP 8300 USDT port
+
+In Coreboot Gerrit:
+https://review.coreboot.org/c/coreboot/+/74906
+
+The following is tested and is working:
+* Native raminit with both DIMMs
+* Libgfxinit textmode and framebuffer on both DisplayPorts and VGA
+* External USB2 and USB3 ports: they all work
+* USB 3.0 SuperSpeed on Linux-libre (rear, 4 ports)
+* Ethernet
+* Mini-PCIe WLAN
+* SATA: 2.5" SSD and optical drive bay
+* Booting Live Linuxes from DVD and USB with SeaBIOS 1.16.1
+* PS/2 keyboard
+* S3 suspend and resume, wake using USB keyboard
+* Headphone output, line out, internal speaker
+* Wake on LAN
+* Rebooting
+* CMOS options & nvramcui
+
+Untested:
+* mSATA slot. The SATA port needs to be enabled on devicetree
+  too, but I'm unable to test due to lack of hardware
+* Line in, mic input
+* MXM graphics card
+* PS/2 mouse
+* EHCI debug
+
+Not working:
+* Mini-PCIe USB: I couldn't get it working on vendor BIOS either, so
+  maybe it just isn't present
+* PS/2 keyboard wake from S3
+---
+ .../hp/compaq_elite_8300_usdt/Kconfig         |  43 ++++
+ .../hp/compaq_elite_8300_usdt/Kconfig.name    |   2 +
+ .../hp/compaq_elite_8300_usdt/Makefile.inc    |   5 +
+ .../hp/compaq_elite_8300_usdt/acpi/ec.asl     |   1 +
+ .../compaq_elite_8300_usdt/acpi/platform.asl  |  10 +
+ .../compaq_elite_8300_usdt/acpi/superio.asl   |  29 +++
+ .../hp/compaq_elite_8300_usdt/acpi_tables.c   |  12 ++
+ .../hp/compaq_elite_8300_usdt/board_info.txt  |   6 +
+ .../hp/compaq_elite_8300_usdt/cmos.default    |   6 +
+ .../hp/compaq_elite_8300_usdt/cmos.layout     |  73 +++++++
+ .../hp/compaq_elite_8300_usdt/devicetree.cb   | 172 ++++++++++++++++
+ .../hp/compaq_elite_8300_usdt/dsdt.asl        |  30 +++
+ .../hp/compaq_elite_8300_usdt/early_init.c    |  39 ++++
+ .../compaq_elite_8300_usdt/gma-mainboard.ads  |  19 ++
+ .../hp/compaq_elite_8300_usdt/gpio.c          | 191 ++++++++++++++++++
+ .../hp/compaq_elite_8300_usdt/hda_verb.c      |  33 +++
+ .../hp/compaq_elite_8300_usdt/mainboard.c     |  16 ++
+ 17 files changed, 687 insertions(+)
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/Kconfig
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/Kconfig.name
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/Makefile.inc
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/acpi/ec.asl
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/acpi/platform.asl
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/acpi/superio.asl
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/acpi_tables.c
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/board_info.txt
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/cmos.layout
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/dsdt.asl
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/early_init.c
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/gma-mainboard.ads
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/gpio.c
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_usdt/mainboard.c
+
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig b/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig
+new file mode 100644
+index 0000000000..9450133065
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig
+@@ -0,0 +1,43 @@
++if BOARD_HP_COMPAQ_ELITE_8300_USDT
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_16384
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_C216
++	select USE_NATIVE_RAMINIT
++	select SUPERIO_NUVOTON_NPCD378
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select MAINBOARD_HAS_TPM1
++	select MEMORY_MAPPED_TPM
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++
++config CBFS_SIZE
++	default 0x570000
++
++config MAINBOARD_DIR
++	string
++	default "hp/compaq_elite_8300_usdt"
++
++config MAINBOARD_PART_NUMBER
++	string
++	default "HP Compaq Elite 8300 USDT"
++
++config VGA_BIOS_ID
++	string
++	default "8086,0152"
++
++config DRAM_RESET_GATE_GPIO
++	int
++	default 60
++
++config USBDEBUG_HCD_INDEX # FIXME: check this
++	int
++	default 2
++endif
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig.name b/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig.name
+new file mode 100644
+index 0000000000..030d8560ab
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_HP_COMPAQ_ELITE_8300_USDT
++	bool "Compaq Elite 8300 USDT"
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_usdt/Makefile.inc
+new file mode 100644
+index 0000000000..18391d8b18
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/Makefile.inc
+@@ -0,0 +1,5 @@
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/acpi/ec.asl b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/ec.asl
+new file mode 100644
+index 0000000000..73fa78ef14
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/ec.asl
+@@ -0,0 +1 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/acpi/platform.asl b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/platform.asl
+new file mode 100644
+index 0000000000..aff432b6f4
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/platform.asl
+@@ -0,0 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	Return(Package() {0, 0})
++}
++
++Method(_PTS, 1)
++{
++}
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/acpi/superio.asl b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/superio.asl
+new file mode 100644
+index 0000000000..54f8e3fe95
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/acpi/superio.asl
+@@ -0,0 +1,29 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */
++
++#include <superio/nuvoton/npcd378/acpi/superio.asl>
++
++Scope (\_GPE)
++{
++	Method (_L0D, 0, NotSerialized)
++	{
++		Notify (\_SB.PCI0.EHC1, 0x02)
++		Notify (\_SB.PCI0.EHC2, 0x02)
++		//FIXME: Add GBE device
++		//Notify (\_SB.PCI0.GBE, 0x02)
++	}
++
++	Method (_L09, 0, NotSerialized)
++	{
++		Notify (\_SB.PCI0.RP01, 0x02)
++		Notify (\_SB.PCI0.RP02, 0x02)
++		Notify (\_SB.PCI0.RP03, 0x02)
++		Notify (\_SB.PCI0.RP04, 0x02)
++		Notify (\_SB.PCI0.RP05, 0x02)
++		Notify (\_SB.PCI0.RP06, 0x02)
++		Notify (\_SB.PCI0.RP07, 0x02)
++		Notify (\_SB.PCI0.RP08, 0x02)
++		Notify (\_SB.PCI0.PEGP, 0x02)
++	}
++}
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/acpi_tables.c b/src/mainboard/hp/compaq_elite_8300_usdt/acpi_tables.c
+new file mode 100644
+index 0000000000..8f4f83b826
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/acpi_tables.c
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/board_info.txt b/src/mainboard/hp/compaq_elite_8300_usdt/board_info.txt
+new file mode 100644
+index 0000000000..f47ea980b1
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/board_info.txt
+@@ -0,0 +1,6 @@
++Category: mini
++ROM protocol: SPI
++ROM socketed: n
++ROM package: SOIC-16
++Flashrom support: y
++Release year: 2012
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+new file mode 100644
+index 0000000000..6f3cec735e
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+@@ -0,0 +1,6 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Enable
++nmi=Enable
++sata_mode=AHCI
++gfx_uma_size=32M
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.layout b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.layout
+new file mode 100644
+index 0000000000..bdc06faed6
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.layout
+@@ -0,0 +1,73 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++
++421	1	e	9	sata_mode
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	IDE
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 415 984
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb
+new file mode 100644
+index 0000000000..008429505e
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb
+@@ -0,0 +1,172 @@
++chip northbridge/intel/sandybridge
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "0"
++	device domain 0x0 on
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "0"
++			register "gen1_dec" = "0x00fc0a01"
++			register "gen2_dec" = "0x00fc0801"
++			register "gen3_dec" = "0x00000000"
++			register "gen4_dec" = "0x00000000"
++			register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x3"  # 0x1: 2.5" slot
++			                                  # 0x2: DVD
++			                                  # 0x?: mSATA
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++			register "superspeed_capable_ports" = "0x0000000f"
++			register "xhci_overcurrent_mapping" = "0x00000c03"
++			register "xhci_switchable_ports" = "0x0000000f"
++			device ref xhci on # USB 3.0 Controller
++				subsystemid 0x103c 0x3398
++			end
++			device ref mei1 off # Management Engine Interface 1
++			end
++			device ref mei2 off # Management Engine Interface 2
++			end
++			device ref me_ide_r off # Management Engine IDE-R
++			end
++			device ref me_kt off # Management Engine KT
++			end
++			device ref gbe on # Intel Gigabit Ethernet
++				subsystemid 0x103c 0x3398
++			end
++			device ref ehci2 on # USB2 EHCI #2
++				subsystemid 0x103c 0x3398
++			end
++			device ref hda on # High Definition Audio
++				subsystemid 0x103c 0x3398
++			end
++			device ref pcie_rp1 on # Mini-PCIe WLAN
++			end
++			device ref pcie_rp2 off # PCIe Port #2
++			end
++			device ref pcie_rp3 off # PCIe Port #3
++			end
++			device ref pcie_rp4 off # PCIe Port #4
++			end
++			device ref pcie_rp5 off # PCIe Port #5
++			end
++			device ref pcie_rp6 off # PCIe Port #6
++			end
++			device ref pcie_rp7 off # PCIe Port #7
++			end
++			device ref pcie_rp8 off # PCIe Port #8
++			end
++			device ref ehci1 on # USB2 EHCI #1
++				subsystemid 0x103c 0x3398
++			end
++			device ref pci_bridge on # PCI bridge
++				subsystemid 0x103c 0x3398
++			end
++			device ref lpc on # LPC bridge
++				chip superio/common		# Super I/O grabbed from 8200SFF devicetree
++					device pnp 2e.ff on # passes SIO base addr to SSDT gen
++						chip superio/nuvoton/npcd378
++							device pnp 2e.0 off end		# Floppy
++							device pnp 2e.1 off end		# Parallel
++							device pnp 2e.2 off		# COM1
++								io 0x60 = 0x2f8
++								irq 0x70 = 3
++							end
++							device pnp 2e.3 on		# COM2, IR
++								io 0x60 = 0x3f8
++								irq 0x70 = 4
++							end
++							device pnp 2e.4 on		# LED control
++								io 0x60 = 0x600
++								# IOBASE[0h] = bit0 LED red / green
++								# IOBASE[0h] = bit1-4 LED PWM duty cycle
++								# IOBASE[1h] = bit6 SWCC
++
++								io 0x62 = 0x610
++								# IOBASE [0h] = GPES
++								# IOBASE [1h] = GPEE
++								# IOBASE [4h:7h] = 32bit upcounter at 1Mhz
++								# IOBASE [8h:bh] = GPS
++								# IOBASE [ch:fh] = GPE
++							end
++							device pnp 2e.5 on		# Mouse
++								irq 0x70 = 0xc
++							end
++							device pnp 2e.6 on		# Keyboard
++								io 0x60 = 0x0060
++								io 0x62 = 0x0064
++								irq 0x70 = 0x01
++								# serialice: Vendor writes:
++								drq 0xf0 = 0x40
++							end
++							device pnp 2e.7 on		#  WDT ?
++								io 0x60 = 0x620
++							end
++							device pnp 2e.8 on		# HWM
++								io 0x60 = 0x800
++								# IOBASE[0h:feh] HWM page
++								# IOBASE[ffh] bit0-bit3 page selector
++
++								drq 0xf0 = 0x20
++								drq 0xf1 = 0x01
++								drq 0xf2 = 0x40
++								drq 0xf3 = 0x01
++
++								drq 0xf4 = 0x66
++								drq 0xf5 = 0x67
++								drq 0xf6 = 0x66
++								drq 0xf7 = 0x01
++							end
++							device pnp 2e.f on		# GPIO OD ?
++								drq 0xf1 = 0x97
++								drq 0xf2 = 0x01
++								drq 0xf5 = 0x08
++								drq 0xfe = 0x80
++							end
++							device pnp 2e.15 on		# BUS ?
++								io 0x60 = 0x0680
++								io 0x62 = 0x0690
++							end
++							device pnp 2e.1c on		# Suspend Control ?
++								io 0x60 = 0x640
++								# writing to IOBASE[5h]
++								#  0x0: Power off
++								#  0x9: Power off and bricked until CMOS battery removed
++							end
++							device pnp 2e.1e on		# GPIO ?
++								io 0x60 = 0x660
++								drq 0xf4 = 0x01
++								# skip the following, as it
++								# looks like remapped registers
++								#drq 0xf5 = 0x06
++								#drq 0xf6 = 0x60
++								#drq 0xfe = 0x03
++							end
++						end
++					end
++				end
++				chip drivers/pc80/tpm
++					device pnp 4e.0 on end          # TPM module
++				end
++			end
++			device ref sata1 on # SATA Controller 1
++				subsystemid 0x103c 0x3398
++			end
++			device ref smbus on # SMBus
++				subsystemid 0x103c 0x3398
++			end
++			device ref sata2 off # SATA Controller 2
++			end
++			device ref thermal off # Thermal
++			end
++		end
++		device ref host_bridge on # Host bridge Host bridge
++			subsystemid 0x103c 0x3398
++		end
++		device ref peg10 on # PEG
++		end
++		device ref igd on # iGPU
++			subsystemid 0x103c 0x3398
++		end
++	end
++end
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/dsdt.asl b/src/mainboard/hp/compaq_elite_8300_usdt/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c b/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c
+new file mode 100644
+index 0000000000..857c25dd19
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/early_init.c
+@@ -0,0 +1,39 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <superio/nuvoton/npcd378/npcd378.h>
++#include <superio/nuvoton/common/nuvoton.h>
++#include <device/pci_ops.h>
++#include <northbridge/intel/sandybridge/raminit_native.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 0, 0 },
++	{ 1, 0, 0 },
++	{ 1, 0, 1 },
++	{ 1, 0, 1 },
++	{ 1, 0, 2 },
++	{ 1, 0, 2 },
++	{ 1, 0, 3 },
++	{ 1, 0, 3 },
++	{ 1, 0, 4 },
++	{ 1, 0, 4 },
++	{ 1, 0, 6 },
++	{ 1, 0, 5 },
++	{ 1, 0, 5 },
++	{ 1, 0, 6 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1408);
++	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010);
++}
++
++void mainboard_get_spd(spd_raw_data *spd, bool id_only)
++{
++	read_spd(&spd[3], 0x50, id_only);
++	read_spd(&spd[1], 0x52, id_only);
++}
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/gma-mainboard.ads b/src/mainboard/hp/compaq_elite_8300_usdt/gma-mainboard.ads
+new file mode 100644
+index 0000000000..74b50645e6
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/gma-mainboard.ads
+@@ -0,0 +1,19 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (DP1,
++      DP2,
++      HDMI1,
++      HDMI2,
++      Analog,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/gpio.c b/src/mainboard/hp/compaq_elite_8300_usdt/gpio.c
+new file mode 100644
+index 0000000000..2ae852ae51
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/gpio.c
+@@ -0,0 +1,191 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_GPIO,
++	.gpio2 = GPIO_MODE_NATIVE,
++	.gpio3 = GPIO_MODE_NATIVE,
++	.gpio4 = GPIO_MODE_NATIVE,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_GPIO,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_NATIVE,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_NATIVE,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_NATIVE,
++	.gpio31 = GPIO_MODE_GPIO,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio1 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio11 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_OUTPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_OUTPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_OUTPUT,
++	.gpio29 = GPIO_DIR_OUTPUT,
++	.gpio31 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio15 = GPIO_LEVEL_LOW,
++	.gpio17 = GPIO_LEVEL_LOW,
++	.gpio28 = GPIO_LEVEL_LOW,
++	.gpio29 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio1 = GPIO_INVERT,
++	.gpio6 = GPIO_INVERT,
++	.gpio11 = GPIO_INVERT,
++	.gpio13 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_GPIO,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_GPIO,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_NATIVE,
++	.gpio46 = GPIO_MODE_GPIO,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_NATIVE,
++	.gpio52 = GPIO_MODE_NATIVE,
++	.gpio53 = GPIO_MODE_NATIVE,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_NATIVE,
++	.gpio61 = GPIO_MODE_GPIO,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio32 = GPIO_DIR_INPUT,
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_INPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio43 = GPIO_DIR_INPUT,
++	.gpio46 = GPIO_DIR_INPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio61 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_GPIO,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_NATIVE,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_OUTPUT,
++	.gpio72 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++	.gpio71 = GPIO_LEVEL_LOW,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c b/src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c
+new file mode 100644
+index 0000000000..9c0525b015
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x10ec0221,	/* Codec Vendor / Device ID: Realtek */
++	0x103c3398,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x103c3398),
++	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x14, 0x01014020),
++	AZALIA_PIN_CFG(0, 0x17, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f),
++	AZALIA_PIN_CFG(0, 0x1b, 0x01813c30),
++	AZALIA_PIN_CFG(0, 0x1d, 0x598301f0),
++	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
++
++	0x80862806,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x58560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/mainboard.c b/src/mainboard/hp/compaq_elite_8300_usdt/mainboard.c
+new file mode 100644
+index 0000000000..8dbd95ef96
+--- /dev/null
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/mainboard.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++static void mainboard_enable(struct device *dev)
++{
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.41.0
+

resources/coreboot/e6400_4mb/board.cfg

@@ -0,0 +1,10 @@
+cbtree="default"
+romtype="4MiB ICH9 IFD NOR flash"
+arch="x86_64"
+payload_grub="n"
+payload_grub_withseabios="n"
+payload_seabios="y"
+payload_memtest="y"
+grub_scan_disk="ahci"
+microcode_required="n"
+blobs_required="n"

resources/coreboot/e6400_4mb/config/libgfxinit_corebootfb

@@ -0,0 +1,559 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+# CONFIG_OPTION_BACKEND_NONE is not set
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_STATIC_OPTION_TABLE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_COLLECT_TIMESTAMPS=y
+# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
+CONFIG_USE_BLOBS=y
+# CONFIG_USE_AMD_BLOBS is not set
+# CONFIG_USE_QC_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
+# CONFIG_ASAN is not set
+# CONFIG_NO_STAGE_CACHE is not set
+CONFIG_TSEG_STAGE_CACHE=y
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
+# end of General setup
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_51NB is not set
+# CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BOSTENTECH is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_CLEVO is not set
+# CONFIG_VENDOR_COMPULAB is not set
+CONFIG_VENDOR_DELL=y
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EXAMPLE is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIBRETREND is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PINE64 is not set
+# CONFIG_VENDOR_PORTWELL is not set
+# CONFIG_VENDOR_PRODRIVE is not set
+# CONFIG_VENDOR_PROTECTLI is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RAZER is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_SYSTEM76 is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_UP is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_PART_NUMBER="Latitude E6400"
+CONFIG_MAINBOARD_VERSION="1.0"
+CONFIG_MAINBOARD_DIR="dell/e6400"
+CONFIG_VGA_BIOS_ID="8086,2a42"
+CONFIG_DIMM_MAX=4
+CONFIG_DIMM_SPD_SIZE=256
+CONFIG_FMDFILE=""
+# CONFIG_NO_POST is not set
+CONFIG_MAINBOARD_VENDOR="Dell Inc."
+CONFIG_CBFS_SIZE=0x3FD000
+CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
+CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
+CONFIG_MAX_CPUS=4
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
+CONFIG_DEVICETREE="devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
+# CONFIG_VGA_BIOS is not set
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_USBDEBUG_HCD_INDEX=1
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
+CONFIG_BOARD_DELL_E6400=y
+# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
+# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
+CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
+CONFIG_DCACHE_RAM_BASE=0xfefc0000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
+CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
+CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_ECAM_MMCONF_BUS_NUMBER=64
+CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
+CONFIG_HAVE_INTEL_FIRMWARE=y
+CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6400"
+# CONFIG_HAVE_IFD_BIN is not set
+CONFIG_PCIEXP_HOTPLUG_BUSES=8
+CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
+CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+# CONFIG_PCIEXP_CLK_PM is not set
+# CONFIG_DRIVERS_UART_8250IO is not set
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_EC_GPE_SCI=0x50
+CONFIG_BOARD_ROMSIZE_KB_4096=y
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_4096=y
+# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=4096
+CONFIG_ROM_SIZE=0x00400000
+CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
+CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
+CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
+# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
+# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
+CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
+# end of Mainboard
+
+CONFIG_SYSTEM_TYPE_LAPTOP=y
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_CHIPSET_DEVICETREE=""
+CONFIG_CBFS_MCACHE_SIZE=0x4000
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_SMM_RESERVED_SIZE=0x100000
+CONFIG_SMM_MODULE_STACK_SIZE=0x400
+CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X"
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_STACK_SIZE=0x2000
+CONFIG_VBT_DATA_SIZE_KB=8
+CONFIG_INTEL_GMA_BCLV_OFFSET=0x61254
+CONFIG_INTEL_GMA_BCLV_WIDTH=16
+CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
+CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
+CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
+CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_CBFS_CACHE_ALIGN=8
+
+#
+# CPU
+#
+CONFIG_CPU_INTEL_MODEL_6FX=y
+CONFIG_CPU_INTEL_MODEL_1067X=y
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_INTEL_SOCKET_P=y
+CONFIG_CPU_INTEL_COMMON=y
+CONFIG_ENABLE_VMX=y
+CONFIG_SET_IA32_FC_LOCK_BIT=y
+CONFIG_SET_MSR_AESNI_LOCK_BIT=y
+CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
+CONFIG_CPU_INTEL_COMMON_SMM=y
+CONFIG_MICROCODE_UPDATE_PRE_RAM=y
+CONFIG_PARALLEL_MP=y
+CONFIG_XAPIC_ONLY=y
+# CONFIG_X2APIC_ONLY is not set
+# CONFIG_X2APIC_RUNTIME is not set
+# CONFIG_X2APIC_LATE_WORKAROUND is not set
+CONFIG_UDELAY_TSC=y
+CONFIG_TSC_MONOTONIC_TIMER=y
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_SETUP_XIP_CACHE=y
+CONFIG_LOGICAL_CPUS=y
+CONFIG_HAVE_SMI_HANDLER=y
+CONFIG_SMM_TSEG=y
+CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
+CONFIG_AP_STACK_SIZE=0x800
+CONFIG_SMP=y
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_SSE2=y
+CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
+
+#
+# Northbridge
+#
+CONFIG_NORTHBRIDGE_INTEL_GM45=y
+
+#
+# Southbridge
+#
+CONFIG_PCIEXP_HOTPLUG=y
+CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
+CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
+# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
+CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
+CONFIG_RCBA_LENGTH=0x4000
+
+#
+# Super I/O
+#
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_DELL_MEC5035=y
+
+#
+# Intel Firmware
+#
+CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_POSTCAR_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+CONFIG_ARCH_ALL_STAGES_X86_32=y
+CONFIG_HAVE_EXP_X86_64_SUPPORT=y
+# CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_AP_IN_SIPI_WAIT=y
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_PC80_SYSTEM=y
+CONFIG_HAVE_CMOS_DEFAULT=y
+CONFIG_POSTCAR_STAGE=y
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_COLLECT_TIMESTAMPS_TSC=y
+CONFIG_HAVE_CF9_RESET=y
+CONFIG_DEBUG_HW_BREAKPOINTS=y
+CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
+# end of Chipset
+
+#
+# Devices
+#
+CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
+CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
+CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
+CONFIG_MAINBOARD_USE_LIBGFXINIT=y
+# CONFIG_VGA_ROM_RUN is not set
+# CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
+
+#
+# Display
+#
+# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
+CONFIG_LINEAR_FRAMEBUFFER=y
+# CONFIG_BOOTSPLASH is not set
+# end of Display
+
+CONFIG_PCI=y
+CONFIG_ECAM_MMCONF_SUPPORT=y
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_ECAM_MMCONF_LENGTH=0x04000000
+CONFIG_PCI_ALLOW_BUS_MASTER=y
+CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
+CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
+# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
+# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
+CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
+# CONFIG_EARLY_PCI_BRIDGE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_INTEL_GMA_HAVE_VBT=y
+CONFIG_INTEL_GMA_ADD_VBT=y
+# CONFIG_SOFTWARE_I2C is not set
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_NO_DDR5=y
+CONFIG_NO_LPDDR4=y
+CONFIG_NO_DDR4=y
+CONFIG_USE_DDR3=y
+CONFIG_USE_DDR2=y
+# end of Devices
+
+#
+# Generic Drivers
+#
+CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
+# CONFIG_ELOG is not set
+# CONFIG_SMMSTORE is not set
+CONFIG_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SPI_FLASH_AMIC=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
+# CONFIG_USBDEBUG is not set
+# CONFIG_VPD is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
+CONFIG_INTEL_EDID=y
+CONFIG_INTEL_INT15=y
+CONFIG_INTEL_GMA_ACPI=y
+CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
+CONFIG_GFX_GMA=y
+CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
+CONFIG_INTEL_GMA_OPREGION_2_0=y
+CONFIG_GFX_GMA_DYN_CPU=y
+CONFIG_GFX_GMA_GENERATION="G45"
+CONFIG_GFX_GMA_PCH="No_PCH"
+CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
+CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_DRIVERS_MC146818=y
+# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
+CONFIG_VGA=y
+# CONFIG_DRIVERS_SIL_3114 is not set
+# end of Generic Drivers
+
+#
+# Security
+#
+
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
+#
+# Verified Boot (vboot)
+#
+# end of Verified Boot (vboot)
+
+#
+# Trusted Platform Module
+#
+CONFIG_NO_TPM=y
+# end of Trusted Platform Module
+
+#
+# Memory initialization
+#
+CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
+CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
+# end of Memory initialization
+
+# CONFIG_STM is not set
+CONFIG_BOOTMEDIA_LOCK_NONE=y
+# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
+# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
+# CONFIG_BOOTMEDIA_SMM_BWP is not set
+# end of Security
+
+CONFIG_ACPI_HAVE_PCAT_8259=y
+CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
+CONFIG_ACPI_SOC_NVS=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+
+#
+# Console
+#
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_SQUELCH_EARLY_SMP=y
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
+# CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
+# CONFIG_CMOS_POST is not set
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO_PORT=0x80
+CONFIG_HWBASE_DEBUG_NULL=y
+# end of Console
+
+CONFIG_HAVE_ACPI_RESUME=y
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+CONFIG_HAVE_MONOTONIC_TIMER=y
+CONFIG_HAVE_OPTION_TABLE=y
+CONFIG_IOAPIC=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+
+#
+# System tables
+#
+CONFIG_GENERATE_SMBIOS_TABLES=y
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+# end of System tables
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# end of Payload
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+# CONFIG_DISPLAY_MTRRS is not set
+
+#
+# BLOB Debug Settings
+#
+
+#
+# General Debug Settings
+#
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
+CONFIG_HAVE_DEBUG_SMBUS=y
+# CONFIG_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+# end of Debugging
+
+CONFIG_RAMSTAGE_ADA=y
+CONFIG_RAMSTAGE_LIBHWBASE=y
+CONFIG_HWBASE_DYNAMIC_MMIO=y
+CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
+CONFIG_HWBASE_DIRECT_PCIDEV=y
+CONFIG_DECOMPRESS_OFAST=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_RELOCATABLE_MODULES=y
+CONFIG_HAVE_BOOTBLOCK=y
+CONFIG_HAVE_ROMSTAGE=y
+CONFIG_HAVE_RAMSTAGE=y

resources/coreboot/e6400_4mb/config/libgfxinit_txtmode

@@ -0,0 +1,555 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+# CONFIG_OPTION_BACKEND_NONE is not set
+CONFIG_USE_OPTION_TABLE=y
+CONFIG_STATIC_OPTION_TABLE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
+CONFIG_INCLUDE_CONFIG_FILE=y
+CONFIG_COLLECT_TIMESTAMPS=y
+# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
+CONFIG_USE_BLOBS=y
+# CONFIG_USE_AMD_BLOBS is not set
+# CONFIG_USE_QC_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
+# CONFIG_ASAN is not set
+# CONFIG_NO_STAGE_CACHE is not set
+CONFIG_TSEG_STAGE_CACHE=y
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
+# end of General setup
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_51NB is not set
+# CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BOSTENTECH is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_CLEVO is not set
+# CONFIG_VENDOR_COMPULAB is not set
+CONFIG_VENDOR_DELL=y
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EXAMPLE is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GOOGLE is not set
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIBRETREND is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PINE64 is not set
+# CONFIG_VENDOR_PORTWELL is not set
+# CONFIG_VENDOR_PRODRIVE is not set
+# CONFIG_VENDOR_PROTECTLI is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RAZER is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_SYSTEM76 is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_UP is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_PART_NUMBER="Latitude E6400"
+CONFIG_MAINBOARD_VERSION="1.0"
+CONFIG_MAINBOARD_DIR="dell/e6400"
+CONFIG_VGA_BIOS_ID="8086,2a42"
+CONFIG_DIMM_MAX=4
+CONFIG_DIMM_SPD_SIZE=256
+CONFIG_FMDFILE=""
+# CONFIG_NO_POST is not set
+CONFIG_MAINBOARD_VENDOR="Dell Inc."
+CONFIG_CBFS_SIZE=0x3FD000
+CONFIG_MAX_CPUS=4
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
+CONFIG_DEVICETREE="devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
+# CONFIG_VGA_BIOS is not set
+CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_USBDEBUG_HCD_INDEX=1
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
+CONFIG_BOARD_DELL_E6400=y
+# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
+# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
+CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
+CONFIG_DCACHE_RAM_BASE=0xfefc0000
+CONFIG_DCACHE_RAM_SIZE=0x10000
+CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
+CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
+CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
+CONFIG_ECAM_MMCONF_BUS_NUMBER=64
+CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
+CONFIG_HAVE_INTEL_FIRMWARE=y
+CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E6400"
+# CONFIG_HAVE_IFD_BIN is not set
+CONFIG_PCIEXP_HOTPLUG_BUSES=8
+CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
+CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
+# CONFIG_DEBUG_SMI is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+# CONFIG_PCIEXP_CLK_PM is not set
+# CONFIG_DRIVERS_UART_8250IO is not set
+CONFIG_HEAP_SIZE=0x4000
+CONFIG_EC_GPE_SCI=0x50
+CONFIG_BOARD_ROMSIZE_KB_4096=y
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_4096=y
+# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=4096
+CONFIG_ROM_SIZE=0x00400000
+CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
+CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
+CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
+# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
+# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
+CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
+# end of Mainboard
+
+CONFIG_SYSTEM_TYPE_LAPTOP=y
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_CHIPSET_DEVICETREE=""
+CONFIG_CBFS_MCACHE_SIZE=0x4000
+CONFIG_ROMSTAGE_ADDR=0x2000000
+CONFIG_VERSTAGE_ADDR=0x2000000
+CONFIG_SMM_RESERVED_SIZE=0x100000
+CONFIG_SMM_MODULE_STACK_SIZE=0x400
+CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X"
+CONFIG_EHCI_BAR=0xfef00000
+CONFIG_STACK_SIZE=0x2000
+CONFIG_VBT_DATA_SIZE_KB=8
+CONFIG_INTEL_GMA_BCLV_OFFSET=0x61254
+CONFIG_INTEL_GMA_BCLV_WIDTH=16
+CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
+CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
+CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
+CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_COMMON_CLOCK is not set
+CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_CBFS_CACHE_ALIGN=8
+
+#
+# CPU
+#
+CONFIG_CPU_INTEL_MODEL_6FX=y
+CONFIG_CPU_INTEL_MODEL_1067X=y
+CONFIG_SOCKET_SPECIFIC_OPTIONS=y
+CONFIG_CPU_INTEL_SOCKET_P=y
+CONFIG_CPU_INTEL_COMMON=y
+CONFIG_ENABLE_VMX=y
+CONFIG_SET_IA32_FC_LOCK_BIT=y
+CONFIG_SET_MSR_AESNI_LOCK_BIT=y
+CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
+CONFIG_CPU_INTEL_COMMON_SMM=y
+CONFIG_MICROCODE_UPDATE_PRE_RAM=y
+CONFIG_PARALLEL_MP=y
+CONFIG_XAPIC_ONLY=y
+# CONFIG_X2APIC_ONLY is not set
+# CONFIG_X2APIC_RUNTIME is not set
+# CONFIG_X2APIC_LATE_WORKAROUND is not set
+CONFIG_UDELAY_TSC=y
+CONFIG_TSC_MONOTONIC_TIMER=y
+CONFIG_TSC_SYNC_MFENCE=y
+CONFIG_SETUP_XIP_CACHE=y
+CONFIG_LOGICAL_CPUS=y
+CONFIG_HAVE_SMI_HANDLER=y
+CONFIG_SMM_TSEG=y
+CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
+CONFIG_AP_STACK_SIZE=0x800
+CONFIG_SMP=y
+CONFIG_MMX=y
+CONFIG_SSE=y
+CONFIG_SSE2=y
+CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
+# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
+
+#
+# Northbridge
+#
+CONFIG_NORTHBRIDGE_INTEL_GM45=y
+
+#
+# Southbridge
+#
+CONFIG_PCIEXP_HOTPLUG=y
+CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
+CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
+# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
+CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
+CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
+CONFIG_RCBA_LENGTH=0x4000
+
+#
+# Super I/O
+#
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_DELL_MEC5035=y
+
+#
+# Intel Firmware
+#
+CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
+CONFIG_ARCH_X86=y
+CONFIG_ARCH_BOOTBLOCK_X86_32=y
+CONFIG_ARCH_VERSTAGE_X86_32=y
+CONFIG_ARCH_ROMSTAGE_X86_32=y
+CONFIG_ARCH_POSTCAR_X86_32=y
+CONFIG_ARCH_RAMSTAGE_X86_32=y
+CONFIG_ARCH_ALL_STAGES_X86_32=y
+CONFIG_HAVE_EXP_X86_64_SUPPORT=y
+# CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_AP_IN_SIPI_WAIT=y
+CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
+CONFIG_PC80_SYSTEM=y
+CONFIG_HAVE_CMOS_DEFAULT=y
+CONFIG_POSTCAR_STAGE=y
+CONFIG_BOOTBLOCK_SIMPLE=y
+# CONFIG_BOOTBLOCK_NORMAL is not set
+CONFIG_COLLECT_TIMESTAMPS_TSC=y
+CONFIG_HAVE_CF9_RESET=y
+CONFIG_DEBUG_HW_BREAKPOINTS=y
+CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
+# end of Chipset
+
+#
+# Devices
+#
+CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
+CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
+CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
+CONFIG_MAINBOARD_USE_LIBGFXINIT=y
+# CONFIG_VGA_ROM_RUN is not set
+# CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
+
+#
+# Display
+#
+CONFIG_VGA_TEXT_FRAMEBUFFER=y
+# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
+# end of Display
+
+CONFIG_PCI=y
+CONFIG_ECAM_MMCONF_SUPPORT=y
+CONFIG_PCIX_PLUGIN_SUPPORT=y
+CONFIG_CARDBUS_PLUGIN_SUPPORT=y
+CONFIG_AZALIA_PLUGIN_SUPPORT=y
+CONFIG_PCIEXP_PLUGIN_SUPPORT=y
+CONFIG_ECAM_MMCONF_LENGTH=0x04000000
+CONFIG_PCI_ALLOW_BUS_MASTER=y
+CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
+CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
+# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
+# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
+CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
+# CONFIG_EARLY_PCI_BRIDGE is not set
+CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
+CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
+CONFIG_INTEL_GMA_HAVE_VBT=y
+CONFIG_INTEL_GMA_ADD_VBT=y
+# CONFIG_SOFTWARE_I2C is not set
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_NO_DDR5=y
+CONFIG_NO_LPDDR4=y
+CONFIG_NO_DDR4=y
+CONFIG_USE_DDR3=y
+CONFIG_USE_DDR2=y
+# end of Devices
+
+#
+# Generic Drivers
+#
+CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
+# CONFIG_ELOG is not set
+# CONFIG_SMMSTORE is not set
+CONFIG_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
+CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_ADESTO=y
+CONFIG_SPI_FLASH_AMIC=y
+CONFIG_SPI_FLASH_ATMEL=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_SST=y
+CONFIG_SPI_FLASH_STMICRO=y
+# CONFIG_DRIVERS_UART_OXPCIE is not set
+CONFIG_HAVE_USBDEBUG=y
+CONFIG_HAVE_USBDEBUG_OPTIONS=y
+# CONFIG_USBDEBUG is not set
+# CONFIG_VPD is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
+CONFIG_INTEL_EDID=y
+CONFIG_INTEL_INT15=y
+CONFIG_INTEL_GMA_ACPI=y
+CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
+CONFIG_GFX_GMA=y
+CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
+CONFIG_INTEL_GMA_OPREGION_2_0=y
+CONFIG_GFX_GMA_DYN_CPU=y
+CONFIG_GFX_GMA_GENERATION="G45"
+CONFIG_GFX_GMA_PCH="No_PCH"
+CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
+CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
+# CONFIG_DRIVERS_PS2_KEYBOARD is not set
+CONFIG_DRIVERS_MC146818=y
+# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
+CONFIG_VGA=y
+# CONFIG_DRIVERS_SIL_3114 is not set
+# end of Generic Drivers
+
+#
+# Security
+#
+
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
+#
+# Verified Boot (vboot)
+#
+# end of Verified Boot (vboot)
+
+#
+# Trusted Platform Module
+#
+CONFIG_NO_TPM=y
+# end of Trusted Platform Module
+
+#
+# Memory initialization
+#
+CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
+CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
+# end of Memory initialization
+
+# CONFIG_STM is not set
+CONFIG_BOOTMEDIA_LOCK_NONE=y
+# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
+# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
+# CONFIG_BOOTMEDIA_SMM_BWP is not set
+# end of Security
+
+CONFIG_ACPI_HAVE_PCAT_8259=y
+CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
+CONFIG_ACPI_SOC_NVS=y
+CONFIG_HAVE_ACPI_TABLES=y
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
+CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+
+#
+# Console
+#
+CONFIG_BOOTBLOCK_CONSOLE=y
+CONFIG_POSTCAR_CONSOLE=y
+CONFIG_SQUELCH_EARLY_SMP=y
+# CONFIG_SPKMODEM is not set
+# CONFIG_CONSOLE_NE2K is not set
+CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
+# CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
+# CONFIG_CMOS_POST is not set
+CONFIG_POST_DEVICE_NONE=y
+# CONFIG_POST_DEVICE_LPC is not set
+# CONFIG_POST_DEVICE_PCI_PCIE is not set
+CONFIG_POST_IO_PORT=0x80
+CONFIG_HWBASE_DEBUG_NULL=y
+# end of Console
+
+CONFIG_HAVE_ACPI_RESUME=y
+CONFIG_RESUME_PATH_SAME_AS_BOOT=y
+CONFIG_HAVE_MONOTONIC_TIMER=y
+CONFIG_HAVE_OPTION_TABLE=y
+CONFIG_IOAPIC=y
+CONFIG_USE_WATCHDOG_ON_BOOT=y
+
+#
+# System tables
+#
+CONFIG_GENERATE_SMBIOS_TABLES=y
+CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
+# end of System tables
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# end of Payload
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+# CONFIG_DISPLAY_MTRRS is not set
+
+#
+# BLOB Debug Settings
+#
+
+#
+# General Debug Settings
+#
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+CONFIG_HAVE_DEBUG_RAM_SETUP=y
+# CONFIG_DEBUG_RAM_SETUP is not set
+CONFIG_HAVE_DEBUG_SMBUS=y
+# CONFIG_DEBUG_SMBUS is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+# end of Debugging
+
+CONFIG_RAMSTAGE_ADA=y
+CONFIG_RAMSTAGE_LIBHWBASE=y
+CONFIG_HWBASE_DYNAMIC_MMIO=y
+CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
+CONFIG_HWBASE_DIRECT_PCIDEV=y
+CONFIG_DECOMPRESS_OFAST=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_RELOCATABLE_MODULES=y
+CONFIG_HAVE_BOOTBLOCK=y
+CONFIG_HAVE_ROMSTAGE=y
+CONFIG_HAVE_RAMSTAGE=y

resources/coreboot/fam15h_rdimm/blobs.list

@@ -1,21 +0,0 @@
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
-3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
-3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
-3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
-3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
-3rdparty/chromeec/test/legacy_nvmem_dump.h
-3rdparty/vboot/tests/futility/data/bios_link_mp.bin
-3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
-src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
-src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
-src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
-src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
-src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
-src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
-src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h

resources/coreboot/fam15h_rdimm/board.cfg

@@ -1,8 +0,0 @@
-cbtree="fam15h_rdimm"
-romtype="normal"
-cbrevision="ad983eeec76ecdb2aff4fb47baeee95ade012225"
-arch="x86_64"
-payload_grub="n"
-payload_grub_withseabios="n"
-payload_seabios="n"
-payload_memtest="n"

resources/coreboot/fam15h_rdimm/deblob-check.results.list

@@ -1,825 +0,0 @@
-./3rdparty/arm-trusted-firmware/docs/design/firmware-design.rst
-./3rdparty/arm-trusted-firmware/docs/getting_started/user-guide.rst
-./3rdparty/arm-trusted-firmware/drivers/marvell/comphy/phy-comphy-3700.c
-./3rdparty/arm-trusted-firmware/drivers/st/pmic/stpmic1.c
-./3rdparty/arm-trusted-firmware/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
-./3rdparty/arm-trusted-firmware/lib/romlib/gen_combined_bl1_romlib.sh
-./3rdparty/arm-trusted-firmware/lib/zlib/crc32.h
-./3rdparty/arm-trusted-firmware/lib/zlib/inffixed.h
-./3rdparty/arm-trusted-firmware/lib/zlib/inftrees.c
-./3rdparty/arm-trusted-firmware/plat/arm/board/fvp/fvp_io_storage.c
-./3rdparty/arm-trusted-firmware/plat/arm/css/sgi/sgi_topology.c
-./3rdparty/arm-trusted-firmware/plat/hisilicon/hikey/hisi_dvfs.c
-./3rdparty/arm-trusted-firmware/plat/hisilicon/poplar/include/platform_def.h
-./3rdparty/arm-trusted-firmware/plat/hisilicon/poplar/include/poplar_layout.h
-./3rdparty/arm-trusted-firmware/plat/intel/soc/agilex/soc/agilex_pinmux.c
-./3rdparty/arm-trusted-firmware/plat/intel/soc/stratix10/soc/s10_pinmux.c
-./3rdparty/arm-trusted-firmware/plat/marvell/a8k/a70x0/board/dram_port.c
-./3rdparty/arm-trusted-firmware/plat/marvell/a8k/a70x0_amc/board/dram_port.c
-./3rdparty/arm-trusted-firmware/plat/marvell/a8k/a80x0/board/dram_port.c
-./3rdparty/arm-trusted-firmware/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c
-./3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
-./3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
-./3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
-./3rdparty/arm-trusted-firmware/plat/qemu/common/qemu_io_storage.c
-./3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c
-./3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
-./3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dfs.c
-./3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/startup.c
-./3rdparty/arm-trusted-firmware/plat/rpi/common/rpi3_io_storage.c
-./3rdparty/arm-trusted-firmware/plat/socionext/synquacer/sq_spm.c
-./3rdparty/arm-trusted-firmware/plat/st/stm32mp1/platform.mk
-./3rdparty/arm-trusted-firmware/tools/amlogic/doimage.c
-./3rdparty/arm-trusted-firmware/tools/fiptool/fiptool.c
-./3rdparty/chromeec/board/bloog/board.c
-./3rdparty/chromeec/board/coffeecake/board.c
-./3rdparty/chromeec/board/cr50/tpm2/ecc.c
-./3rdparty/chromeec/board/cr50/tpm2/endorsement.c
-./3rdparty/chromeec/board/cr50/tpm2/rsa.c
-./3rdparty/chromeec/board/dingdong/board.c
-./3rdparty/chromeec/board/flapjack/battery.c
-./3rdparty/chromeec/board/hoho/board.c
-./3rdparty/chromeec/board/kukui_scp/update_scp
-./3rdparty/chromeec/board/meep/board.c
-./3rdparty/chromeec/chip/g/dcrypto/bn.c
-./3rdparty/chromeec/chip/g/dcrypto/hmac_drbg.c
-./3rdparty/chromeec/chip/mchp/util/pack_ec.py
-./3rdparty/chromeec/chip/mec1322/util/pack_ec.py
-./3rdparty/chromeec/chip/stm32/usb_hid_keyboard.c
-./3rdparty/chromeec/chip/stm32/usb_hid_touchpad.c
-./3rdparty/chromeec/common/crc.c
-./3rdparty/chromeec/common/ctz.c
-./3rdparty/chromeec/common/keyboard_8042_sharedlib.c
-./3rdparty/chromeec/common/lightbar.c
-./3rdparty/chromeec/common/mock/rollback_mock.c
-./3rdparty/chromeec/common/sha256.c
-./3rdparty/chromeec/core/riscv-rv32i/init.S
-./3rdparty/chromeec/driver/als_tcs3400.c
-./3rdparty/chromeec/driver/led/lm3509.c
-./3rdparty/chromeec/driver/regulator_ir357x.c
-./3rdparty/chromeec/driver/touchpad_elan.c
-./3rdparty/chromeec/extra/rma_reset/rma_reset.c
-./3rdparty/chromeec/extra/touchpad_updater/touchpad_updater.c
-./3rdparty/chromeec/extra/usb_updater/fw_update.py
-./3rdparty/chromeec/extra/usb_updater/servo_updater.py
-./3rdparty/chromeec/fuzz/nvmem_tpm2_mock.c
-./3rdparty/chromeec/setup.py
-./3rdparty/chromeec/test/aes.c
-./3rdparty/chromeec/test/fpsensor.c
-./3rdparty/chromeec/test/legacy_nvmem_dump.h
-./3rdparty/chromeec/test/nvmem_tpm2_mock.c
-./3rdparty/chromeec/test/pinweaver.c
-./3rdparty/chromeec/test/rsa2048-3.h
-./3rdparty/chromeec/test/rsa2048-F4.h
-./3rdparty/chromeec/test/sha256.c
-./3rdparty/chromeec/test/test_config.h
-./3rdparty/chromeec/test/thermal.c
-./3rdparty/chromeec/test/tpm_test/rsa_test.py
-./3rdparty/chromeec/test/usb_prl.c
-./3rdparty/chromeec/test/x25519.c
-./3rdparty/chromeec/third_party/boringssl/common/aes.c
-./3rdparty/chromeec/third_party/boringssl/core/cortex-m/aes.S
-./3rdparty/chromeec/util/ec_sb_firmware_update.c
-./3rdparty/chromeec/util/ectool_keyscan.c
-./3rdparty/chromeec/util/flash_ec
-./3rdparty/chromeec/util/flash_fp_mcu
-./3rdparty/chromeec/util/flash_pd.py
-./3rdparty/chromeec/util/signer/create_released_image.sh
-./3rdparty/chromeec/util/uut/lib_crc.c
-./3rdparty/libgfxinit/common/skylake/hw-gfx-gma-plls-dpll.adb
-./3rdparty/opensbi/Makefile
-./3rdparty/vboot/cgpt/cgpt_wrapper.c
-./3rdparty/vboot/firmware/2lib/2sha256.c
-./3rdparty/vboot/firmware/2lib/2sha512.c
-./3rdparty/vboot/firmware/lib/cgptlib/crc32.c
-./3rdparty/vboot/firmware/lib/tpm_lite/include/tlcl_structures.h
-./3rdparty/vboot/futility/cmd_gbb_utility.c
-./3rdparty/vboot/futility/file_type_rwsig.c
-./3rdparty/vboot/futility/updater.c
-./3rdparty/vboot/futility/updater_archive.c
-./3rdparty/vboot/scripts/image_signing/make_dev_firmware.sh
-./3rdparty/vboot/scripts/image_signing/make_dev_ssd.sh
-./3rdparty/vboot/scripts/image_signing/sign_android_image.sh
-./3rdparty/vboot/scripts/image_signing/sign_cr50_firmware.sh
-./3rdparty/vboot/scripts/image_signing/sign_nv_cbootimage.sh
-./3rdparty/vboot/scripts/image_signing/sign_official_build.sh
-./3rdparty/vboot/scripts/image_signing/strip_boot_from_image.sh
-./3rdparty/vboot/scripts/image_signing/tag_image.sh
-./3rdparty/vboot/scripts/image_signing/tofactory.sh
-./3rdparty/vboot/tests/cgptlib_test.c
-./3rdparty/vboot/tests/crc32_test.c
-./3rdparty/vboot/tests/futility/data/bios_link_mp.bin
-./3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
-./3rdparty/vboot/tests/futility/link_bios.manifest.json
-./3rdparty/vboot/tests/futility/link_image.manifest.json
-./3rdparty/vboot/tests/futility/models/link/setvars.sh
-./3rdparty/vboot/tests/futility/models/peppy/setvars.sh
-./3rdparty/vboot/tests/futility/models/whitetip/setvars.sh
-./3rdparty/vboot/tests/futility/test_dump_fmap.sh
-./3rdparty/vboot/tests/futility/test_file_types.c
-./3rdparty/vboot/tests/futility/test_file_types.sh
-./3rdparty/vboot/tests/futility/test_rwsig.sh
-./3rdparty/vboot/tests/futility/test_sign_firmware.sh
-./3rdparty/vboot/tests/futility/test_update.sh
-./3rdparty/vboot/tests/gen_preamble_testdata.sh
-./3rdparty/vboot/tests/load_kernel_tests.sh
-./3rdparty/vboot/tests/rsa_padding_test.h
-./3rdparty/vboot/tests/run_vbutil_kernel_arg_tests.sh
-./3rdparty/vboot/tests/sha_test_vectors.h
-./3rdparty/vboot/tests/testcases/padding_test_vectors.inc
-./3rdparty/vboot/tests/tlcl_tests.c
-./3rdparty/vboot/tests/vb21_host_misc_tests.c
-./3rdparty/vboot/tests/vb2_api_tests.c
-./3rdparty/vboot/tests/vb2_sha_tests.c
-./3rdparty/vboot/utility/vbutil_what_keys
-./Documentation/Intel/SoC/soc.html
-./Documentation/releases/coreboot-4.2-relnotes.md
-./Documentation/soc/intel/fit.md
-./Documentation/tutorial/part1.md
-./Documentation/codeflow.svg
-./Documentation/hypertransport.svg
-./configs/builder/config.lenovo_t420
-./configs/builder/config.lenovo_t420s
-./configs/builder/config.lenovo_t430s
-./configs/builder/config.lenovo_t520
-./configs/builder/config.lenovo_t530
-./configs/builder/config.lenovo_x220
-./configs/builder/config.lenovo_x220i
-./configs/builder/config.lenovo_x230
-./payloads/external/FILO/Kconfig
-./payloads/external/GRUB2/Kconfig
-./payloads/external/SeaBIOS/Kconfig
-./payloads/external/U-Boot/Kconfig
-./payloads/external/Yabits/Kconfig
-./payloads/external/depthcharge/Kconfig
-./payloads/libpayload/curses/PDCurses/demos/worm.c
-./payloads/libpayload/curses/PDCurses/sdl1/deffont.h
-./payloads/libpayload/curses/PDCurses/sdl1/deficon.h
-./payloads/libpayload/curses/PDCurses/win32/pdckbd.c
-./payloads/libpayload/curses/PDCurses/x11/big_icon.xbm
-./payloads/libpayload/curses/PDCurses/x11/little_icon.xbm
-./payloads/libpayload/curses/pdcurses-backend/pdcdisp.c
-./payloads/libpayload/curses/tinycurses.c
-./payloads/libpayload/drivers/i8042/keyboard.c
-./payloads/libpayload/drivers/usb/usbmsc.c
-./payloads/libpayload/tests/cbfs-x86-test.c
-./payloads/nvramcui/payload.sh
-./payloads/Kconfig
-./src/cpu/amd/pi/00730F01/Makefile.inc
-./src/cpu/amd/pi/00730F01/microcode_fam16h.c
-./src/cpu/amd/pi/00730F01/model_16_init.c
-./src/cpu/amd/pi/00730F01/update_microcode.c
-./src/cpu/amd/family_10h-family_15h/Makefile.inc
-./src/cpu/amd/family_10h-family_15h/init_cpus.c
-./src/cpu/amd/family_10h-family_15h/init_cpus.h
-./src/cpu/amd/family_10h-family_15h/processor_name.c
-./src/cpu/amd/family_10h-family_15h/update_microcode.c
-./src/cpu/amd/microcode/microcode.c
-./src/cpu/intel/car/non-evict/cache_as_ram.S
-./src/cpu/intel/car/p4-netburst/cache_as_ram.S
-./src/cpu/intel/haswell/acpi.c
-./src/cpu/intel/microcode/Kconfig
-./src/cpu/intel/microcode/microcode.c
-./src/cpu/intel/microcode/microcode_asm.S
-./src/cpu/intel/model_2065x/acpi.c
-./src/cpu/intel/model_206ax/acpi.c
-./src/cpu/intel/model_65x/model_65x_init.c
-./src/cpu/intel/model_67x/model_67x_init.c
-./src/cpu/intel/model_68x/model_68x_init.c
-./src/cpu/intel/model_6bx/model_6bx_init.c
-./src/cpu/intel/model_6xx/model_6xx_init.c
-./src/cpu/intel/model_f2x/model_f2x_init.c
-./src/cpu/intel/model_f3x/model_f3x_init.c
-./src/cpu/intel/fsp_model_406dx/acpi.c
-./src/cpu/intel/fsp_model_406dx/bootblock.c
-./src/cpu/intel/fsp_model_406dx/model_406dx_init.c
-./src/cpu/Kconfig
-./src/cpu/Makefile.inc
-./src/device/oprom/yabel/interrupt.c
-./src/device/Kconfig
-./src/drivers/aspeed/common/ast_dram_tables.h
-./src/drivers/aspeed/common/ast_tables.h
-./src/drivers/i2c/ww_ring/ww_ring_programs.c
-./src/drivers/intel/fsp1_1/cache_as_ram.S
-./src/drivers/intel/fsp1_1/car.c
-./src/drivers/intel/fsp1_1/ramstage.c
-./src/drivers/intel/fsp1_1/romstage.c
-./src/drivers/intel/fsp1_1/temp_ram_exit.c
-./src/drivers/intel/fsp2_0/Kconfig
-./src/drivers/intel/gma/opregion.c
-./src/drivers/intel/gma/opregion.h
-./src/drivers/intel/fsp1_0/fsp_util.c
-./src/drivers/pc80/rtc/mc146818rtc.c
-./src/drivers/pc80/vga/vga_palette.c
-./src/drivers/siemens/nc_fpga/nc_fpga.c
-./src/drivers/wifi/Kconfig
-./src/drivers/xgi/common/XGI_main.h
-./src/drivers/xgi/common/vb_setmode.c
-./src/drivers/xgi/common/vb_table.h
-./src/ec/hp/kbc1126/Kconfig
-./src/include/cpu/amd/microcode.h
-./src/include/cpu/intel/microcode.h
-./src/include/spd_bin.h
-./src/lib/coreboot_table.c
-./src/lib/jpeg.c
-./src/lib/spd_bin.c
-./src/mainboard/amd/gardenia/bootblock/OemCustomize.c
-./src/mainboard/amd/inagua/Kconfig
-./src/mainboard/amd/olivehill/mptable.c
-./src/mainboard/amd/parmer/mptable.c
-./src/mainboard/amd/persimmon/Kconfig
-./src/mainboard/amd/south_station/Kconfig
-./src/mainboard/amd/south_station/mptable.c
-./src/mainboard/amd/thatcher/mptable.c
-./src/mainboard/amd/union_station/Kconfig
-./src/mainboard/amd/union_station/mptable.c
-./src/mainboard/amd/bimini_fam10/mptable.c
-./src/mainboard/amd/bimini_fam10/romstage.c
-./src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex
-./src/mainboard/amd/lamar/Kconfig
-./src/mainboard/amd/mahogany_fam10/romstage.c
-./src/mainboard/amd/olivehillplus/mptable.c
-./src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
-./src/mainboard/amd/tilapia_fam10/romstage.c
-./src/mainboard/apple/macbookair4_2/early_init.c
-./src/mainboard/asrock/b75pro3-m/early_init.c
-./src/mainboard/asrock/e350m1/mptable.c
-./src/mainboard/asrock/imb-a180/mptable.c
-./src/mainboard/asus/f2a85-m/mptable.c
-./src/mainboard/asus/h61m-cs/early_init.c
-./src/mainboard/asus/maximus_iv_gene-z/early_init.c
-./src/mainboard/asus/p8h61-m_lx/early_init.c
-./src/mainboard/asus/p8h61-m_pro/early_init.c
-./src/mainboard/asus/kcma-d8/romstage.c
-./src/mainboard/asus/kfsn4-dre/romstage.c
-./src/mainboard/asus/kgpe-d16/romstage.c
-./src/mainboard/asus/m4a78-em/romstage.c
-./src/mainboard/asus/m4a785-m/romstage.c
-./src/mainboard/asus/m5a88-v/mptable.c
-./src/mainboard/asus/m5a88-v/romstage.c
-./src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex
-./src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex
-./src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
-./src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
-./src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
-./src/mainboard/bap/ode_e21XX/mptable.c
-./src/mainboard/biostar/a68n_5200/mptable.c
-./src/mainboard/compulab/intense_pc/early_init.c
-./src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex
-./src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex
-./src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
-./src/mainboard/facebook/fbg1701/board_mboot.h
-./src/mainboard/facebook/fbg1701/board_verified_boot.c
-./src/mainboard/facebook/fbg1701/onboard.h
-./src/mainboard/facebook/fbg1701/ramstage.c
-./src/mainboard/gigabyte/ga-b75m-d3h/early_init.c
-./src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c
-./src/mainboard/gigabyte/ma785gm/romstage.c
-./src/mainboard/gigabyte/ma785gmt/romstage.c
-./src/mainboard/gigabyte/ma78gm/romstage.c
-./src/mainboard/gizmosphere/gizmo/mptable.c
-./src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex
-./src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
-./src/mainboard/google/auron/variants/auron_paine/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/auron/variants/auron_paine/spd/empty.spd.hex
-./src/mainboard/google/auron/variants/auron_paine/spd/spd.c
-./src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
-./src/mainboard/google/auron/variants/auron_yuna/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/auron/variants/auron_yuna/spd/empty.spd.hex
-./src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
-./src/mainboard/google/auron/variants/buddy/variant.c
-./src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
-./src/mainboard/google/auron/variants/gandof/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/auron/variants/gandof/spd/Samsung_M471B5674EB0-YK0.spd.hex
-./src/mainboard/google/auron/variants/gandof/spd/empty.spd.hex
-./src/mainboard/google/auron/variants/gandof/spd/spd.c
-./src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/spd.c
-./src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/empty.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/spd.c
-./src/mainboard/google/beltino/lan.c
-./src/mainboard/google/butterfly/hda_verb.c
-./src/mainboard/google/butterfly/mainboard.c
-./src/mainboard/google/cyan/spd/empty.spd.hex
-./src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
-./src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD.spd.hex
-./src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
-./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex
-./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex
-./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
-./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex
-./src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex
-./src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-JD-F.spd.hex
-./src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex
-./src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex
-./src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF.spd.hex
-./src/mainboard/google/cyan/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex
-./src/mainboard/google/cyan/spd/nanya_dimm_NT6CL256T32CM-H1.spd.hex
-./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
-./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
-./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCE.spd.hex
-./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCF.spd.hex
-./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E324EB-EGCF.spd.hex
-./src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
-./src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex
-./src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
-./src/mainboard/google/cyan/spd/spd.c
-./src/mainboard/google/cyan/Kconfig
-./src/mainboard/google/drallion/spd/empty_ddr4.spd.hex
-./src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex
-./src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex
-./src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex
-./src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex
-./src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex
-./src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex
-./src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex
-./src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex
-./src/mainboard/google/drallion/variants/drallion/devicetree.cb
-./src/mainboard/google/drallion/variants/drallion/memory.c
-./src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb
-./src/mainboard/google/eve/spd/empty.spd.hex
-./src/mainboard/google/eve/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex
-./src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex
-./src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex
-./src/mainboard/google/eve/spd/samsung_dimm_K4E6E304EB.spd.hex
-./src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex
-./src/mainboard/google/eve/spd/samsung_dimm_K4EBE304EB.spd.hex
-./src/mainboard/google/eve/spd/spd.c
-./src/mainboard/google/glados/spd/empty.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTALAR.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLGALAR.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex
-./src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex
-./src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex
-./src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex
-./src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex
-./src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCF.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCG.spd.hex
-./src/mainboard/google/glados/spd/spd.c
-./src/mainboard/google/glados/Kconfig
-./src/mainboard/google/hatch/spd/16G_2400.spd.hex
-./src/mainboard/google/hatch/spd/16G_2666.spd.hex
-./src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex
-./src/mainboard/google/hatch/spd/16G_3200.spd.hex
-./src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex
-./src/mainboard/google/hatch/spd/4G_2400.spd.hex
-./src/mainboard/google/hatch/spd/8G_2400.spd.hex
-./src/mainboard/google/hatch/spd/8G_2666.spd.hex
-./src/mainboard/google/hatch/spd/8G_3200.spd.hex
-./src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex
-./src/mainboard/google/hatch/spd/LP_8G_2133.spd.hex
-./src/mainboard/google/hatch/spd/empty_ddr4.spd.hex
-./src/mainboard/google/hatch/variants/dratini/variant.c
-./src/mainboard/google/jecht/lan.c
-./src/mainboard/google/kahlee/spd/empty.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5AN8G6NAFR-UH.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-VKC.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5ANAG6NAMR-UH.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-VKC.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-XNC.spd.hex
-./src/mainboard/google/kahlee/spd/micron-MT40A1G16KNR-075-E.spd.hex
-./src/mainboard/google/kahlee/spd/micron-MT40A1G16RC-062E-B.spd.hex
-./src/mainboard/google/kahlee/spd/micron-MT40A512M16JY-083E-B.spd.hex
-./src/mainboard/google/kahlee/spd/micron-MT40A512M16LY-075-E.spd.hex
-./src/mainboard/google/kahlee/spd/micron-MT40A512M16TB-062E-J.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4A8G165WB-BCRC.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCTD.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCTD.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCWE.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCRC.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCTD.spd.hex
-./src/mainboard/google/kahlee/variants/baseboard/mainboard.c
-./src/mainboard/google/kahlee/Kconfig
-./src/mainboard/google/link/early_init.c
-./src/mainboard/google/link/elpida_4Gb_1600_x16.spd.hex
-./src/mainboard/google/link/hda_verb.c
-./src/mainboard/google/link/micron_4Gb_1600_1.35v_x16.spd.hex
-./src/mainboard/google/link/samsung_4Gb_1600_1.35v_x16.spd.hex
-./src/mainboard/google/octopus/variants/bloog/variant.c
-./src/mainboard/google/octopus/variants/bobba/variant.c
-./src/mainboard/google/octopus/variants/casta/variant.c
-./src/mainboard/google/octopus/variants/garg/variant.c
-./src/mainboard/google/octopus/variants/meep/variant.c
-./src/mainboard/google/octopus/variants/phaser/mainboard.c
-./src/mainboard/google/peach_pit/mainboard.c
-./src/mainboard/google/poppy/spd/empty.spd.hex
-./src/mainboard/google/poppy/spd/empty_ddr4.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H5AN4G6NAFR-UHC.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H5AN4G6NBJR-UHC.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NAFR-UHC.spd.hex
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-./src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAMR-UHC.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBJTALAR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBKTALBR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT40A256M16GE-083E.spd.hex
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-./src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16LY-075E.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-093.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L256M64D2PP-107.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-093.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex
-./src/mainboard/google/poppy/spd/nayna_dimm_NT6CL256T32CM-H1.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K3QF3F30BM-AGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K3QF4F40BM-AGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K3QFAFA0CM-AGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4A4G165WE-BCRC.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4A8G165WB-BCRC.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4AAG165WB-MCRC.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304EC-EGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EB-EGCG.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EC-EGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EC-EGCG.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex
-./src/mainboard/google/poppy/variants/nami/mainboard.c
-./src/mainboard/google/poppy/romstage.c
-./src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex
-./src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
-./src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex
-./src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex
-./src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex
-./src/mainboard/google/rambi/spd/empty.spd.hex
-./src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
-./src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
-./src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex
-./src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex
-./src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
-./src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
-./src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex
-./src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex
-./src/mainboard/google/rambi/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex
-./src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
-./src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
-./src/mainboard/google/rambi/variants/ninja/lan.c
-./src/mainboard/google/rambi/variants/sumo/lan.c
-./src/mainboard/google/rambi/romstage.c
-./src/mainboard/google/reef/variants/coral/mainboard.c
-./src/mainboard/google/sarien/variants/arcada/devicetree.cb
-./src/mainboard/google/slippy/variants/falco/spd/Elpida_EDJ4216EFBG.spd.hex
-./src/mainboard/google/slippy/variants/falco/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/slippy/variants/falco/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/slippy/variants/falco/spd/Samsung_M471B5674QH0.spd.hex
-./src/mainboard/google/slippy/variants/falco/romstage.c
-./src/mainboard/google/slippy/variants/leon/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/slippy/variants/leon/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/slippy/variants/leon/spd/Samsung_K4B4G1646Q.spd.hex
-./src/mainboard/google/slippy/variants/leon/romstage.c
-./src/mainboard/google/slippy/variants/peppy/spd/Elpida_EDJ4216EFBG.spd.hex
-./src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/slippy/variants/peppy/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/slippy/variants/peppy/romstage.c
-./src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex
-./src/mainboard/google/slippy/variants/wolf/romstage.c
-./src/mainboard/google/dragonegg/romstage_fsp_params.c
-./src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex
-./src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex
-./src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex
-./src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex
-./src/mainboard/hp/abm/mptable.c
-./src/mainboard/hp/pavilion_m6_1035dx/mptable.c
-./src/mainboard/hp/z220_sff_workstation/early_init.c
-./src/mainboard/hp/2760p/early_init.c
-./src/mainboard/hp/8470p/early_init.c
-./src/mainboard/hp/dl165_g6_fam10/romstage.c
-./src/mainboard/hp/revolve_810_g1/early_init.c
-./src/mainboard/hp/revolve_810_g1/spd/hynix_4g.spd.hex
-./src/mainboard/ibase/mb899/cmos.layout
-./src/mainboard/ibase/mb899/superio_hwm.c
-./src/mainboard/intel/apollolake_rvp/romstage.c
-./src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h
-./src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h
-./src/mainboard/intel/glkrvp/romstage.c
-./src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
-./src/mainboard/intel/harcuvar/spd/spd.c
-./src/mainboard/intel/icelake_rvp/spd/empty.spd.hex
-./src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex
-./src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h
-./src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h
-./src/mainboard/intel/kblrvp/spd/empty.spd.hex
-./src/mainboard/intel/kblrvp/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex
-./src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
-./src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h
-./src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h
-./src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h
-./src/mainboard/intel/kblrvp/Kconfig
-./src/mainboard/intel/kunimitsu/spd/empty.spd.hex
-./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTALAR-NUD-2G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E6E304EE-EGCF-2G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
-./src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCF-1G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/spd_util.c
-./src/mainboard/intel/leafhill/Kconfig
-./src/mainboard/intel/leafhill/romstage.c
-./src/mainboard/intel/minnow3/Kconfig
-./src/mainboard/intel/minnow3/romstage.c
-./src/mainboard/intel/strago/Kconfig
-./src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex
-./src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex
-./src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex
-./src/mainboard/intel/mohonpeak/Kconfig
-./src/mainboard/jetway/nf81-t56n-lf/Kconfig
-./src/mainboard/jetway/pa78vm5/romstage.c
-./src/mainboard/kontron/986lcd-m/cmos.layout
-./src/mainboard/kontron/986lcd-m/mainboard.c
-./src/mainboard/lenovo/g505s/mptable.c
-./src/mainboard/lenovo/s230u/spd/elpida_2gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/elpida_4gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/elpida_8gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/hynix_2gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/hynix_4gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/samsung_4gb.spd.hex
-./src/mainboard/lenovo/s230u/early_init.c
-./src/mainboard/lenovo/t430s/variants/t431s/spd/samsung_4gb.spd.hex
-./src/mainboard/lenovo/t430s/variants/t431s/romstage.c
-./src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.hex
-./src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.hex
-./src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.hex
-./src/mainboard/lenovo/x1_carbon_gen1/early_init.c
-./src/mainboard/lenovo/x220/variants/x1/romstage.c
-./src/mainboard/lenovo/x220/early_init.c
-./src/mainboard/lippert/frontrunner-af/Kconfig
-./src/mainboard/lippert/frontrunner-af/mptable.c
-./src/mainboard/lippert/toucan-af/Kconfig
-./src/mainboard/lippert/toucan-af/mptable.c
-./src/mainboard/msi/ms7707/Kconfig
-./src/mainboard/msi/ms7707/early_init.c
-./src/mainboard/msi/ms7721/mptable.c
-./src/mainboard/msi/ms9652_fam10/romstage.c
-./src/mainboard/opencellular/elgon/gbcv2.dts
-./src/mainboard/packardbell/ms2290/mainboard.c
-./src/mainboard/pcengines/apu1/Kconfig
-./src/mainboard/pcengines/apu2/Kconfig
-./src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex
-./src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex
-./src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
-./src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex
-./src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex
-./src/mainboard/samsung/lumpy/early_init.c
-./src/mainboard/sapphire/pureplatinumh61/early_init.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
-./src/mainboard/siemens/mc_apl1/mainboard.c
-./src/mainboard/siemens/mc_apl1/romstage.c
-./src/mainboard/siemens/mc_bdx1/mainboard.c
-./src/mainboard/siemens/mc_tcu3/lcd_panel.c
-./src/mainboard/siemens/mc_tcu3/mainboard.c
-./src/mainboard/siemens/mc_tcu3/romstage.c
-./src/mainboard/supermicro/h8dmr_fam10/romstage.c
-./src/mainboard/supermicro/h8qme_fam10/romstage.c
-./src/mainboard/supermicro/h8scm_fam10/romstage.c
-./src/mainboard/up/squared/romstage.c
-./src/mainboard/adi/rcc-dff/Kconfig
-./src/mainboard/advansus/a785e-i/mptable.c
-./src/mainboard/advansus/a785e-i/romstage.c
-./src/mainboard/avalue/eax-785e/mptable.c
-./src/mainboard/avalue/eax-785e/romstage.c
-./src/mainboard/iei/kino-780am2-fam10/romstage.c
-./src/mainboard/tyan/s2912_fam10/romstage.c
-./src/northbridge/amd/pi/00630F01/Kconfig
-./src/northbridge/amd/pi/00730F01/Kconfig
-./src/northbridge/amd/pi/00660F01/Kconfig
-./src/northbridge/amd/amdmct/mct/mctardk3.c
-./src/northbridge/amd/amdmct/mct/mctardk4.c
-./src/northbridge/amd/amdmct/mct/mcttmrl.c
-./src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
-./src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-./src/northbridge/intel/gm45/raminit_read_write_training.c
-./src/northbridge/intel/haswell/Kconfig
-./src/northbridge/intel/haswell/raminit.c
-./src/northbridge/intel/i945/raminit.c
-./src/northbridge/intel/pineview/raminit.c
-./src/northbridge/intel/sandybridge/Kconfig
-./src/northbridge/intel/sandybridge/gma.c
-./src/northbridge/intel/sandybridge/raminit.c
-./src/northbridge/intel/sandybridge/raminit_mrc.c
-./src/northbridge/intel/sandybridge/raminit_patterns.h
-./src/northbridge/intel/x4x/dq_dqs.c
-./src/northbridge/intel/x4x/raminit_ddr23.c
-./src/northbridge/intel/x4x/raminit_tables.c
-./src/northbridge/intel/fsp_rangeley/fsp/Kconfig
-./src/northbridge/intel/nehalem/raminit.c
-./src/northbridge/intel/nehalem/raminit_tables.c
-./src/security/intel/txt/Kconfig
-./src/security/tpm/tss/tcg-1.2/tss_commands.h
-./src/security/vboot/secdata_tpm.c
-./src/soc/amd/picasso/Kconfig
-./src/soc/amd/stoneyridge/Kconfig
-./src/soc/cavium/cn81xx/Kconfig
-./src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex
-./src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex
-./src/soc/intel/apollolake/Kconfig
-./src/soc/intel/apollolake/nhlt.c
-./src/soc/intel/baytrail/bootblock/bootblock.c
-./src/soc/intel/baytrail/romstage/raminit.c
-./src/soc/intel/baytrail/Kconfig
-./src/soc/intel/baytrail/acpi.c
-./src/soc/intel/braswell/acpi.c
-./src/soc/intel/braswell/gpio.c
-./src/soc/intel/broadwell/Kconfig
-./src/soc/intel/broadwell/acpi.c
-./src/soc/intel/broadwell/romstage/raminit.c
-./src/soc/intel/cannonlake/nhlt.c
-./src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
-./src/soc/intel/common/mma.c
-./src/soc/intel/denverton_ns/acpi.c
-./src/soc/intel/denverton_ns/chip.c
-./src/soc/intel/quark/romstage/romstage.c
-./src/soc/intel/quark/Kconfig
-./src/soc/intel/skylake/nhlt/da7219.c
-./src/soc/intel/skylake/nhlt/dmic.c
-./src/soc/intel/skylake/nhlt/max98357.c
-./src/soc/intel/skylake/nhlt/max98373.c
-./src/soc/intel/skylake/nhlt/max98927.c
-./src/soc/intel/skylake/nhlt/nau88l25.c
-./src/soc/intel/skylake/nhlt/rt5514.c
-./src/soc/intel/skylake/nhlt/rt5663.c
-./src/soc/intel/skylake/nhlt/ssm4567.c
-./src/soc/intel/fsp_baytrail/Kconfig
-./src/soc/intel/fsp_baytrail/acpi.c
-./src/soc/intel/fsp_baytrail/bootblock/bootblock.c
-./src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c
-./src/soc/intel/fsp_broadwell_de/fsp/Kconfig
-./src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
-./src/soc/mediatek/mt8183/spm.c
-./src/soc/mediatek/mt8183/sspm.c
-./src/soc/nvidia/tegra210/Kconfig
-./src/soc/nvidia/tegra210/mtc.c
-./src/soc/qualcomm/ipq40xx/Kconfig
-./src/soc/qualcomm/ipq40xx/lcc.c
-./src/soc/qualcomm/ipq806x/Kconfig
-./src/soc/qualcomm/ipq806x/blobs_init.c
-./src/soc/qualcomm/ipq806x/lcc.c
-./src/soc/samsung/exynos5250/clock.c
-./src/soc/samsung/exynos5420/clock.c
-./src/southbridge/amd/agesa/hudson/Kconfig
-./src/southbridge/amd/cimx/sb800/Kconfig
-./src/southbridge/amd/pi/hudson/Kconfig
-./src/southbridge/intel/bd82x6x/lpc.c
-./src/southbridge/intel/common/firmware/Kconfig
-./src/southbridge/intel/i82801ix/dmi_setup.c
-./src/southbridge/nvidia/ck804/early_setup_ss.h
-./src/southbridge/nvidia/mcp55/early_setup_ss.h
-./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
-./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
-./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
-./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
-./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
-./src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c
-./src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
-./src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
-./src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c
-./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
-./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
-./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
-./src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
-./src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c
-./src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mptn3.c
-./src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c
-./src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
-./src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c
-./src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c
-./src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h
-./src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c
-./src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpkb3.c
-./src/vendorcode/amd/cimx/sb800/SATA.c
-./src/vendorcode/amd/pi/Kconfig
-./src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c
-./src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c
-./src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse.c
-./src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c
-./src/vendorcode/eltan/security/verified_boot/vboot_check.c
-./src/vendorcode/google/chromeos/build-snow.sh
-./src/vendorcode/google/chromeos/sar.c
-./src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm12.h
-./src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiConfigAccess.h
-./src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
-./src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
-./util/amdtools/example_input/lspci-cb-48G-667MHz-18.2-20090909e
-./util/amdtools/example_input/lspci-prop-48G-667MHz-18.2
-./util/autoport/readme.md
-./util/bincfg/bincfg.lex.c_shipped
-./util/bincfg/bincfg.tab.c_shipped
-./util/cbfstool/lz4/lib/lz4.c
-./util/cbfstool/fit.c
-./util/cbfstool/fmd_parser.c_shipped
-./util/cbfstool/fmd_scanner.c_shipped
-./util/cbfstool/linux_trampoline.c
-./util/ifdtool/ifdtool.c
-./util/intelmetool/intelmetool.c
-./util/kbc1126/kbc1126_ec_dump.c
-./util/kconfig/zconf.hash.c_shipped
-./util/kconfig/zconf.lex.c_shipped
-./util/kconfig/zconf.tab.c_shipped
-./util/mma/mma_automated_test.sh
-./util/mtkheader/gen-bl-img.py
-./util/nvidia/cbootimage/samples/sign.sh
-./util/nvidia/cbootimage/src/aes_ref.c
-./util/nvramtool/accessors/layout-bin.c
-./util/qualcomm/scripts/cmm/debug_cb_common.cmm
-./util/qualcomm/createxbl.py
-./util/riscv/make-spike-elf.sh
-./util/riscv/sifive-gpt.py
-./util/rockchip/make_idb.py
-./util/sconfig/lex.yy.c_shipped
-./util/sconfig/sconfig.tab.c_shipped
-./util/spdtool/spdtool.py
-./util/superiotool/fintek.c
-./util/superiotool/ite.c
-./util/superiotool/nuvoton.c
-./util/superiotool/smsc.c
-./util/superiotool/winbond.c
-./util/xcompile/xcompile
-./util/genprof/genprof.c
-./util/romcc/test.sh
-./util/romcc/tests/include/linux_console.h
-./util/romcc/tests/linux_console.h
-./util/romcc/tests/linux_test5.c
-./util/romcc/tests/raminit_test6.c
-./util/romcc/tests/raminit_test7.c
-./util/romcc/tests/simple_test14.c
-./util/romcc/tests/simple_test30.c
-./util/romcc/tests/simple_test38.c
-./util/romcc/tests/simple_test39.c
-./util/romcc/tests/simple_test54.c
-./util/romcc/tests/simple_test59.c
-./util/romcc/tests/simple_test72.c
-./util/romcc/tests/simple_test73.c
-./Makefile.inc
-./deblob-check

resources/coreboot/fam15h_rdimm/patches/0003-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch

@@ -1,38 +0,0 @@
-From 7a00638cea41ad939a59fc0e5996959435fbdb7f Mon Sep 17 00:00:00 2001
-From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
-Date: Sun, 7 Feb 2021 16:40:05 +0100
-Subject: [PATCH 3/6] Tweak cmos defaults for KCMA-D8 (for a little speed
- boost)
-
-63xx CPUs have the option to use a reduced latency value inside the crossbar.
-Setting "experimental_memory_speed_boost=Enable" aparently only has an effect
-on 63xx CPUs and may, in certain cases, yield a slight memory bandwidth
-increase (according to Timothy Pearson), but maybe it also works for
-43xx CPUs.
-
-Setting "l3_cache_partitioning=Enable" will increase performance in certain
-situations. See:
-https://developer.arm.com/documentation/100453/0401/functional-description/l3-cache/l3-cache-partitioning?lang=en
----
- src/mainboard/asus/kcma-d8/cmos.default | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default
-index 306687157f..4e033d756f 100644
---- a/src/mainboard/asus/kcma-d8/cmos.default
-+++ b/src/mainboard/asus/kcma-d8/cmos.default
-@@ -21,9 +21,9 @@ sata_ahci_mode=Enable
- sata_alpm=Disable
- maximum_p_state_limit=0xf
- probe_filter=Auto
--l3_cache_partitioning=Disable
-+l3_cache_partitioning=Enable
- gart=Enable
- ehci_async_data_cache=Enable
--experimental_memory_speed_boost=Disable
-+experimental_memory_speed_boost=Enable
- power_on_after_fail=On
- boot_option=Fallback
--- 
-2.25.1
-

resources/coreboot/fam15h_rdimm/patches/0004-Do-not-use-microcode-updates-on-AMD-platforms.patch

@@ -1,108 +0,0 @@
-From 2b1d40b970d9cbbb4f8fe30679e9b6909aa3d99a Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Thu, 6 May 2021 17:07:06 +0100
-Subject: [PATCH 4/6] Do not use microcode updates on AMD platforms
-
-Coreboot is hardcoding the use of microcode updates on some platforms.
-
-Just nuke it from orbit. This is the libre branch of osboot, so microcode must
-not be used.
----
- src/cpu/Makefile.inc                          | 52 +------------------
- src/cpu/amd/family_10h-family_15h/Kconfig     |  1 -
- .../amd/family_10h-family_15h/Makefile.inc    | 10 +---
- 3 files changed, 2 insertions(+), 61 deletions(-)
-
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index b80c30d72b..e7909d32ed 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -14,54 +14,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
- ## Rules for building the microcode blob in CBFS
- ################################################################################
- 
--ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
--cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
--cbfs-files-y  += cpu_microcode_blob.bin
--cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
--
--$(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER_FILES))
--	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
--	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y)
--cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
--endif
--# otherwise `cpu_microcode_bins` should be filled by platform makefiles
--
--# We just mash all microcode binaries together into one binary to rule them all.
--# This approach assumes that the microcode binaries are properly padded, and
--# their headers specify the correct size. This works fairly well on isolatied
--# updates, such as Intel and some AMD microcode, but won't work very well if the
--# updates are wrapped in a container, like AMD's microcode update container. If
--# there is only one microcode binary (i.e. one container), then we don't have
--# this issue, and this rule will continue to work.
--$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))
--	for bin in $(cpu_microcode_bins); do \
--		if [ ! -f "$$bin" ]; then \
--			echo "Microcode error: $$bin does not exist"; \
--			NO_MICROCODE_FILE=1; \
--		fi; \
--	done; \
--	if [ -n "$$NO_MICROCODE_FILE" ]; then \
--		if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \
--			echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
--		fi; \
--		false; \
--	fi
--	$(if $^,,false) # fail if no file is given at all
--	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
--	@echo $(cpu_microcode_bins)
--	cat $^ > $@
--
--cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
--cpu_microcode_blob.bin-type := microcode
--
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
--cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
--else
--cpu_microcode_blob.bin-align := 16
--endif
-+# No microcode permitted in this version of coreboot.
-diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
-index ad4f5f4ba6..21150ab1a7 100644
---- a/src/cpu/amd/family_10h-family_15h/Kconfig
-+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
-@@ -8,7 +8,6 @@ config CPU_AMD_MODEL_10XXX
- 	select TSC_SYNC_LFENCE
- 	select UDELAY_LAPIC
- 	select SUPPORT_CPU_UCODE_IN_CBFS
--	select CPU_MICROCODE_MULTIPLE_FILES
- 	select CAR_GLOBAL_MIGRATION
- 
- if CPU_AMD_MODEL_10XXX
-diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-index 7035323026..e0029f562d 100644
---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
-+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-@@ -14,12 +14,4 @@ ramstage-y += ram_calc.c
- ramstage-y += monotonic_timer.c
- ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
- 
--# Microcode for Family 10h, 11h, 12h, and 14h
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin
--microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
--microcode_amd.bin-type := microcode
--
--# Microcode for Family 15h
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-type := microcode
-+# Microcode deleted in this version of coreboot.
--- 
-2.25.1
-

resources/coreboot/fam15h_rdimm/patches/0006-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch

@@ -1,32 +0,0 @@
-From f0aac7261e16adc8e61eca7a506ff2de5112be47 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Fri, 7 May 2021 19:43:32 +0100
-Subject: [PATCH 6/6] asus/kgpe-d16: enable lc_cache_partitioning and
- experimental_memory_speed_boost
-
-This really only benefits 63xx opterons which are less reliable in libreboot due
-to lack of CPU microcode updates, but we might aswell enable this anyway.
----
- src/mainboard/asus/kgpe-d16/cmos.default | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
-index 7c496a50d7..8a25620e1d 100644
---- a/src/mainboard/asus/kgpe-d16/cmos.default
-+++ b/src/mainboard/asus/kgpe-d16/cmos.default
-@@ -21,10 +21,10 @@ sata_ahci_mode=Enable
- sata_alpm=Disable
- maximum_p_state_limit=0xf
- probe_filter=Auto
--l3_cache_partitioning=Disable
-+l3_cache_partitioning=Enable
- ieee1394_controller=Enable
- gart=Enable
- ehci_async_data_cache=Enable
--experimental_memory_speed_boost=Disable
-+experimental_memory_speed_boost=Enable
- power_on_after_fail=On
- boot_option=Fallback
--- 
-2.25.1
-

resources/coreboot/fam15h_udimm/blobs.list

@@ -1,21 +0,0 @@
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
-3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
-3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
-3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
-3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
-3rdparty/chromeec/test/legacy_nvmem_dump.h
-3rdparty/vboot/tests/futility/data/bios_link_mp.bin
-3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
-src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
-src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
-src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
-src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
-src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
-src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
-src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
-src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
-src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h

resources/coreboot/fam15h_udimm/board.cfg

@@ -1,8 +0,0 @@
-cbtree="fam15h_udimm"
-romtype="normal"
-cbrevision="ad983eeec76ecdb2aff4fb47baeee95ade012225"
-arch="x86_64"
-payload_grub="n"
-payload_grub_withseabios="n"
-payload_seabios="n"
-payload_memtest="n"

resources/coreboot/fam15h_udimm/deblob-check.results.list

@@ -1,825 +0,0 @@
-./3rdparty/arm-trusted-firmware/docs/design/firmware-design.rst
-./3rdparty/arm-trusted-firmware/docs/getting_started/user-guide.rst
-./3rdparty/arm-trusted-firmware/drivers/marvell/comphy/phy-comphy-3700.c
-./3rdparty/arm-trusted-firmware/drivers/st/pmic/stpmic1.c
-./3rdparty/arm-trusted-firmware/drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
-./3rdparty/arm-trusted-firmware/lib/romlib/gen_combined_bl1_romlib.sh
-./3rdparty/arm-trusted-firmware/lib/zlib/crc32.h
-./3rdparty/arm-trusted-firmware/lib/zlib/inffixed.h
-./3rdparty/arm-trusted-firmware/lib/zlib/inftrees.c
-./3rdparty/arm-trusted-firmware/plat/arm/board/fvp/fvp_io_storage.c
-./3rdparty/arm-trusted-firmware/plat/arm/css/sgi/sgi_topology.c
-./3rdparty/arm-trusted-firmware/plat/hisilicon/hikey/hisi_dvfs.c
-./3rdparty/arm-trusted-firmware/plat/hisilicon/poplar/include/platform_def.h
-./3rdparty/arm-trusted-firmware/plat/hisilicon/poplar/include/poplar_layout.h
-./3rdparty/arm-trusted-firmware/plat/intel/soc/agilex/soc/agilex_pinmux.c
-./3rdparty/arm-trusted-firmware/plat/intel/soc/stratix10/soc/s10_pinmux.c
-./3rdparty/arm-trusted-firmware/plat/marvell/a8k/a70x0/board/dram_port.c
-./3rdparty/arm-trusted-firmware/plat/marvell/a8k/a70x0_amc/board/dram_port.c
-./3rdparty/arm-trusted-firmware/plat/marvell/a8k/a80x0/board/dram_port.c
-./3rdparty/arm-trusted-firmware/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c
-./3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
-./3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
-./3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
-./3rdparty/arm-trusted-firmware/plat/qemu/common/qemu_io_storage.c
-./3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/ddr_rk3368.c
-./3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
-./3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/dram/dfs.c
-./3rdparty/arm-trusted-firmware/plat/rockchip/rk3399/drivers/m0/src/startup.c
-./3rdparty/arm-trusted-firmware/plat/rpi/common/rpi3_io_storage.c
-./3rdparty/arm-trusted-firmware/plat/socionext/synquacer/sq_spm.c
-./3rdparty/arm-trusted-firmware/plat/st/stm32mp1/platform.mk
-./3rdparty/arm-trusted-firmware/tools/amlogic/doimage.c
-./3rdparty/arm-trusted-firmware/tools/fiptool/fiptool.c
-./3rdparty/chromeec/board/bloog/board.c
-./3rdparty/chromeec/board/coffeecake/board.c
-./3rdparty/chromeec/board/cr50/tpm2/ecc.c
-./3rdparty/chromeec/board/cr50/tpm2/endorsement.c
-./3rdparty/chromeec/board/cr50/tpm2/rsa.c
-./3rdparty/chromeec/board/dingdong/board.c
-./3rdparty/chromeec/board/flapjack/battery.c
-./3rdparty/chromeec/board/hoho/board.c
-./3rdparty/chromeec/board/kukui_scp/update_scp
-./3rdparty/chromeec/board/meep/board.c
-./3rdparty/chromeec/chip/g/dcrypto/bn.c
-./3rdparty/chromeec/chip/g/dcrypto/hmac_drbg.c
-./3rdparty/chromeec/chip/mchp/util/pack_ec.py
-./3rdparty/chromeec/chip/mec1322/util/pack_ec.py
-./3rdparty/chromeec/chip/stm32/usb_hid_keyboard.c
-./3rdparty/chromeec/chip/stm32/usb_hid_touchpad.c
-./3rdparty/chromeec/common/crc.c
-./3rdparty/chromeec/common/ctz.c
-./3rdparty/chromeec/common/keyboard_8042_sharedlib.c
-./3rdparty/chromeec/common/lightbar.c
-./3rdparty/chromeec/common/mock/rollback_mock.c
-./3rdparty/chromeec/common/sha256.c
-./3rdparty/chromeec/core/riscv-rv32i/init.S
-./3rdparty/chromeec/driver/als_tcs3400.c
-./3rdparty/chromeec/driver/led/lm3509.c
-./3rdparty/chromeec/driver/regulator_ir357x.c
-./3rdparty/chromeec/driver/touchpad_elan.c
-./3rdparty/chromeec/extra/rma_reset/rma_reset.c
-./3rdparty/chromeec/extra/touchpad_updater/touchpad_updater.c
-./3rdparty/chromeec/extra/usb_updater/fw_update.py
-./3rdparty/chromeec/extra/usb_updater/servo_updater.py
-./3rdparty/chromeec/fuzz/nvmem_tpm2_mock.c
-./3rdparty/chromeec/setup.py
-./3rdparty/chromeec/test/aes.c
-./3rdparty/chromeec/test/fpsensor.c
-./3rdparty/chromeec/test/legacy_nvmem_dump.h
-./3rdparty/chromeec/test/nvmem_tpm2_mock.c
-./3rdparty/chromeec/test/pinweaver.c
-./3rdparty/chromeec/test/rsa2048-3.h
-./3rdparty/chromeec/test/rsa2048-F4.h
-./3rdparty/chromeec/test/sha256.c
-./3rdparty/chromeec/test/test_config.h
-./3rdparty/chromeec/test/thermal.c
-./3rdparty/chromeec/test/tpm_test/rsa_test.py
-./3rdparty/chromeec/test/usb_prl.c
-./3rdparty/chromeec/test/x25519.c
-./3rdparty/chromeec/third_party/boringssl/common/aes.c
-./3rdparty/chromeec/third_party/boringssl/core/cortex-m/aes.S
-./3rdparty/chromeec/util/ec_sb_firmware_update.c
-./3rdparty/chromeec/util/ectool_keyscan.c
-./3rdparty/chromeec/util/flash_ec
-./3rdparty/chromeec/util/flash_fp_mcu
-./3rdparty/chromeec/util/flash_pd.py
-./3rdparty/chromeec/util/signer/create_released_image.sh
-./3rdparty/chromeec/util/uut/lib_crc.c
-./3rdparty/libgfxinit/common/skylake/hw-gfx-gma-plls-dpll.adb
-./3rdparty/opensbi/Makefile
-./3rdparty/vboot/cgpt/cgpt_wrapper.c
-./3rdparty/vboot/firmware/2lib/2sha256.c
-./3rdparty/vboot/firmware/2lib/2sha512.c
-./3rdparty/vboot/firmware/lib/cgptlib/crc32.c
-./3rdparty/vboot/firmware/lib/tpm_lite/include/tlcl_structures.h
-./3rdparty/vboot/futility/cmd_gbb_utility.c
-./3rdparty/vboot/futility/file_type_rwsig.c
-./3rdparty/vboot/futility/updater.c
-./3rdparty/vboot/futility/updater_archive.c
-./3rdparty/vboot/scripts/image_signing/make_dev_firmware.sh
-./3rdparty/vboot/scripts/image_signing/make_dev_ssd.sh
-./3rdparty/vboot/scripts/image_signing/sign_android_image.sh
-./3rdparty/vboot/scripts/image_signing/sign_cr50_firmware.sh
-./3rdparty/vboot/scripts/image_signing/sign_nv_cbootimage.sh
-./3rdparty/vboot/scripts/image_signing/sign_official_build.sh
-./3rdparty/vboot/scripts/image_signing/strip_boot_from_image.sh
-./3rdparty/vboot/scripts/image_signing/tag_image.sh
-./3rdparty/vboot/scripts/image_signing/tofactory.sh
-./3rdparty/vboot/tests/cgptlib_test.c
-./3rdparty/vboot/tests/crc32_test.c
-./3rdparty/vboot/tests/futility/data/bios_link_mp.bin
-./3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
-./3rdparty/vboot/tests/futility/link_bios.manifest.json
-./3rdparty/vboot/tests/futility/link_image.manifest.json
-./3rdparty/vboot/tests/futility/models/link/setvars.sh
-./3rdparty/vboot/tests/futility/models/peppy/setvars.sh
-./3rdparty/vboot/tests/futility/models/whitetip/setvars.sh
-./3rdparty/vboot/tests/futility/test_dump_fmap.sh
-./3rdparty/vboot/tests/futility/test_file_types.c
-./3rdparty/vboot/tests/futility/test_file_types.sh
-./3rdparty/vboot/tests/futility/test_rwsig.sh
-./3rdparty/vboot/tests/futility/test_sign_firmware.sh
-./3rdparty/vboot/tests/futility/test_update.sh
-./3rdparty/vboot/tests/gen_preamble_testdata.sh
-./3rdparty/vboot/tests/load_kernel_tests.sh
-./3rdparty/vboot/tests/rsa_padding_test.h
-./3rdparty/vboot/tests/run_vbutil_kernel_arg_tests.sh
-./3rdparty/vboot/tests/sha_test_vectors.h
-./3rdparty/vboot/tests/testcases/padding_test_vectors.inc
-./3rdparty/vboot/tests/tlcl_tests.c
-./3rdparty/vboot/tests/vb21_host_misc_tests.c
-./3rdparty/vboot/tests/vb2_api_tests.c
-./3rdparty/vboot/tests/vb2_sha_tests.c
-./3rdparty/vboot/utility/vbutil_what_keys
-./Documentation/Intel/SoC/soc.html
-./Documentation/releases/coreboot-4.2-relnotes.md
-./Documentation/soc/intel/fit.md
-./Documentation/tutorial/part1.md
-./Documentation/codeflow.svg
-./Documentation/hypertransport.svg
-./configs/builder/config.lenovo_t420
-./configs/builder/config.lenovo_t420s
-./configs/builder/config.lenovo_t430s
-./configs/builder/config.lenovo_t520
-./configs/builder/config.lenovo_t530
-./configs/builder/config.lenovo_x220
-./configs/builder/config.lenovo_x220i
-./configs/builder/config.lenovo_x230
-./payloads/external/FILO/Kconfig
-./payloads/external/GRUB2/Kconfig
-./payloads/external/SeaBIOS/Kconfig
-./payloads/external/U-Boot/Kconfig
-./payloads/external/Yabits/Kconfig
-./payloads/external/depthcharge/Kconfig
-./payloads/libpayload/curses/PDCurses/demos/worm.c
-./payloads/libpayload/curses/PDCurses/sdl1/deffont.h
-./payloads/libpayload/curses/PDCurses/sdl1/deficon.h
-./payloads/libpayload/curses/PDCurses/win32/pdckbd.c
-./payloads/libpayload/curses/PDCurses/x11/big_icon.xbm
-./payloads/libpayload/curses/PDCurses/x11/little_icon.xbm
-./payloads/libpayload/curses/pdcurses-backend/pdcdisp.c
-./payloads/libpayload/curses/tinycurses.c
-./payloads/libpayload/drivers/i8042/keyboard.c
-./payloads/libpayload/drivers/usb/usbmsc.c
-./payloads/libpayload/tests/cbfs-x86-test.c
-./payloads/nvramcui/payload.sh
-./payloads/Kconfig
-./src/cpu/amd/pi/00730F01/Makefile.inc
-./src/cpu/amd/pi/00730F01/microcode_fam16h.c
-./src/cpu/amd/pi/00730F01/model_16_init.c
-./src/cpu/amd/pi/00730F01/update_microcode.c
-./src/cpu/amd/family_10h-family_15h/Makefile.inc
-./src/cpu/amd/family_10h-family_15h/init_cpus.c
-./src/cpu/amd/family_10h-family_15h/init_cpus.h
-./src/cpu/amd/family_10h-family_15h/processor_name.c
-./src/cpu/amd/family_10h-family_15h/update_microcode.c
-./src/cpu/amd/microcode/microcode.c
-./src/cpu/intel/car/non-evict/cache_as_ram.S
-./src/cpu/intel/car/p4-netburst/cache_as_ram.S
-./src/cpu/intel/haswell/acpi.c
-./src/cpu/intel/microcode/Kconfig
-./src/cpu/intel/microcode/microcode.c
-./src/cpu/intel/microcode/microcode_asm.S
-./src/cpu/intel/model_2065x/acpi.c
-./src/cpu/intel/model_206ax/acpi.c
-./src/cpu/intel/model_65x/model_65x_init.c
-./src/cpu/intel/model_67x/model_67x_init.c
-./src/cpu/intel/model_68x/model_68x_init.c
-./src/cpu/intel/model_6bx/model_6bx_init.c
-./src/cpu/intel/model_6xx/model_6xx_init.c
-./src/cpu/intel/model_f2x/model_f2x_init.c
-./src/cpu/intel/model_f3x/model_f3x_init.c
-./src/cpu/intel/fsp_model_406dx/acpi.c
-./src/cpu/intel/fsp_model_406dx/bootblock.c
-./src/cpu/intel/fsp_model_406dx/model_406dx_init.c
-./src/cpu/Kconfig
-./src/cpu/Makefile.inc
-./src/device/oprom/yabel/interrupt.c
-./src/device/Kconfig
-./src/drivers/aspeed/common/ast_dram_tables.h
-./src/drivers/aspeed/common/ast_tables.h
-./src/drivers/i2c/ww_ring/ww_ring_programs.c
-./src/drivers/intel/fsp1_1/cache_as_ram.S
-./src/drivers/intel/fsp1_1/car.c
-./src/drivers/intel/fsp1_1/ramstage.c
-./src/drivers/intel/fsp1_1/romstage.c
-./src/drivers/intel/fsp1_1/temp_ram_exit.c
-./src/drivers/intel/fsp2_0/Kconfig
-./src/drivers/intel/gma/opregion.c
-./src/drivers/intel/gma/opregion.h
-./src/drivers/intel/fsp1_0/fsp_util.c
-./src/drivers/pc80/rtc/mc146818rtc.c
-./src/drivers/pc80/vga/vga_palette.c
-./src/drivers/siemens/nc_fpga/nc_fpga.c
-./src/drivers/wifi/Kconfig
-./src/drivers/xgi/common/XGI_main.h
-./src/drivers/xgi/common/vb_setmode.c
-./src/drivers/xgi/common/vb_table.h
-./src/ec/hp/kbc1126/Kconfig
-./src/include/cpu/amd/microcode.h
-./src/include/cpu/intel/microcode.h
-./src/include/spd_bin.h
-./src/lib/coreboot_table.c
-./src/lib/jpeg.c
-./src/lib/spd_bin.c
-./src/mainboard/amd/gardenia/bootblock/OemCustomize.c
-./src/mainboard/amd/inagua/Kconfig
-./src/mainboard/amd/olivehill/mptable.c
-./src/mainboard/amd/parmer/mptable.c
-./src/mainboard/amd/persimmon/Kconfig
-./src/mainboard/amd/south_station/Kconfig
-./src/mainboard/amd/south_station/mptable.c
-./src/mainboard/amd/thatcher/mptable.c
-./src/mainboard/amd/union_station/Kconfig
-./src/mainboard/amd/union_station/mptable.c
-./src/mainboard/amd/bimini_fam10/mptable.c
-./src/mainboard/amd/bimini_fam10/romstage.c
-./src/mainboard/amd/db-ft3b-lc/Memphis_MEM4G16D3EABG.spd.hex
-./src/mainboard/amd/lamar/Kconfig
-./src/mainboard/amd/mahogany_fam10/romstage.c
-./src/mainboard/amd/olivehillplus/mptable.c
-./src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
-./src/mainboard/amd/tilapia_fam10/romstage.c
-./src/mainboard/apple/macbookair4_2/early_init.c
-./src/mainboard/asrock/b75pro3-m/early_init.c
-./src/mainboard/asrock/e350m1/mptable.c
-./src/mainboard/asrock/imb-a180/mptable.c
-./src/mainboard/asus/f2a85-m/mptable.c
-./src/mainboard/asus/h61m-cs/early_init.c
-./src/mainboard/asus/maximus_iv_gene-z/early_init.c
-./src/mainboard/asus/p8h61-m_lx/early_init.c
-./src/mainboard/asus/p8h61-m_pro/early_init.c
-./src/mainboard/asus/kcma-d8/romstage.c
-./src/mainboard/asus/kfsn4-dre/romstage.c
-./src/mainboard/asus/kgpe-d16/romstage.c
-./src/mainboard/asus/m4a78-em/romstage.c
-./src/mainboard/asus/m4a785-m/romstage.c
-./src/mainboard/asus/m5a88-v/mptable.c
-./src/mainboard/asus/m5a88-v/romstage.c
-./src/mainboard/bap/ode_e20XX/BAP_Q7_1066.spd.hex
-./src/mainboard/bap/ode_e20XX/BAP_Q7_800.spd.hex
-./src/mainboard/bap/ode_e21XX/BAP_Q7_1066.spd.hex
-./src/mainboard/bap/ode_e21XX/BAP_Q7_1333.spd.hex
-./src/mainboard/bap/ode_e21XX/BAP_Q7_800.spd.hex
-./src/mainboard/bap/ode_e21XX/mptable.c
-./src/mainboard/biostar/a68n_5200/mptable.c
-./src/mainboard/compulab/intense_pc/early_init.c
-./src/mainboard/facebook/fbg1701/spd/KINGSTON_B5116ECMDXGGB.spd.hex
-./src/mainboard/facebook/fbg1701/spd/MICRON_MT41K512M16HA-125A.spd.hex
-./src/mainboard/facebook/fbg1701/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
-./src/mainboard/facebook/fbg1701/board_mboot.h
-./src/mainboard/facebook/fbg1701/board_verified_boot.c
-./src/mainboard/facebook/fbg1701/onboard.h
-./src/mainboard/facebook/fbg1701/ramstage.c
-./src/mainboard/gigabyte/ga-b75m-d3h/early_init.c
-./src/mainboard/gigabyte/ga-h61m-s2pv/early_init.c
-./src/mainboard/gigabyte/ma785gm/romstage.c
-./src/mainboard/gigabyte/ma785gmt/romstage.c
-./src/mainboard/gigabyte/ma78gm/romstage.c
-./src/mainboard/gizmosphere/gizmo/mptable.c
-./src/mainboard/gizmosphere/gizmo2/Micron_MT41J128M16JT.spd.hex
-./src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/auron/variants/auron_paine/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
-./src/mainboard/google/auron/variants/auron_paine/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/auron/variants/auron_paine/spd/empty.spd.hex
-./src/mainboard/google/auron/variants/auron_paine/spd/spd.c
-./src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/auron/variants/auron_yuna/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
-./src/mainboard/google/auron/variants/auron_yuna/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/auron/variants/auron_yuna/spd/empty.spd.hex
-./src/mainboard/google/auron/variants/auron_yuna/spd/spd.c
-./src/mainboard/google/auron/variants/buddy/variant.c
-./src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/auron/variants/gandof/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
-./src/mainboard/google/auron/variants/gandof/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/auron/variants/gandof/spd/Samsung_M471B5674EB0-YK0.spd.hex
-./src/mainboard/google/auron/variants/gandof/spd/empty.spd.hex
-./src/mainboard/google/auron/variants/gandof/spd/spd.c
-./src/mainboard/google/auron/variants/lulu/spd/empty.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/hynix_4GiB_dimm_H5TC8G63CMR-PBA.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/micron_4GiB_dimm_MT41K512M16TNA-125.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/samsung_4GiB_dimm_K4B8G1646Q-MYK0.spd.hex
-./src/mainboard/google/auron/variants/lulu/spd/spd.c
-./src/mainboard/google/auron/variants/samus/spd/elpida_16.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/elpida_4.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/elpida_8.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/empty.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/hynix_16.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/hynix_4.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/hynix_8.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/samsung_4.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/samsung_8.spd.hex
-./src/mainboard/google/auron/variants/samus/spd/spd.c
-./src/mainboard/google/beltino/lan.c
-./src/mainboard/google/butterfly/hda_verb.c
-./src/mainboard/google/butterfly/mainboard.c
-./src/mainboard/google/cyan/spd/empty.spd.hex
-./src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
-./src/mainboard/google/cyan/spd/hynix_2GiB_dimm_H9CCNNN8GTMLAR-NUD.spd.hex
-./src/mainboard/google/cyan/spd/hynix_2GiB_dimm_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
-./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex
-./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex
-./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
-./src/mainboard/google/cyan/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD.spd.hex
-./src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-GD-F-R.spd.hex
-./src/mainboard/google/cyan/spd/micron_2GiB_dimm_EDF8132A3MA-JD-F.spd.hex
-./src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex
-./src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF-107WT.spd.hex
-./src/mainboard/google/cyan/spd/micron_2GiB_dimm_MT52L256M32D1PF.spd.hex
-./src/mainboard/google/cyan/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex
-./src/mainboard/google/cyan/spd/nanya_dimm_NT6CL256T32CM-H1.spd.hex
-./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
-./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
-./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCE.spd.hex
-./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E304EE-EGCF.spd.hex
-./src/mainboard/google/cyan/spd/samsung_2GiB_dimm_K4E8E324EB-EGCF.spd.hex
-./src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
-./src/mainboard/google/cyan/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex
-./src/mainboard/google/cyan/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
-./src/mainboard/google/cyan/spd/spd.c
-./src/mainboard/google/cyan/Kconfig
-./src/mainboard/google/drallion/spd/empty_ddr4.spd.hex
-./src/mainboard/google/drallion/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex
-./src/mainboard/google/drallion/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex
-./src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KD-062EE.spd.hex
-./src/mainboard/google/drallion/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex
-./src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16LY-075E.spd.hex
-./src/mainboard/google/drallion/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex
-./src/mainboard/google/drallion/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex
-./src/mainboard/google/drallion/spd/samsung_dimm_K4AAG165WB-MCTD.spd.hex
-./src/mainboard/google/drallion/variants/drallion/devicetree.cb
-./src/mainboard/google/drallion/variants/drallion/memory.c
-./src/mainboard/google/drallion/variants/arcada_cml/devicetree.cb
-./src/mainboard/google/eve/spd/empty.spd.hex
-./src/mainboard/google/eve/spd/hynix_dimm_H9CCNNN8GTALAR.spd.hex
-./src/mainboard/google/eve/spd/hynix_dimm_H9CCNNNBJTALAR.spd.hex
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-./src/mainboard/google/eve/spd/samsung_dimm_K4E6E304EB.spd.hex
-./src/mainboard/google/eve/spd/samsung_dimm_K4E8E324EB.spd.hex
-./src/mainboard/google/eve/spd/samsung_dimm_K4EBE304EB.spd.hex
-./src/mainboard/google/eve/spd/spd.c
-./src/mainboard/google/glados/spd/empty.spd.hex
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-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR-NUD.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8GTMLAR.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNN8JTBLAR.spd.hex
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-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBJTMLAR-NUD.spd.hex
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-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLGALAR.spd.hex
-./src/mainboard/google/glados/spd/hynix_dimm_H9CCNNNCLTMLAR.spd.hex
-./src/mainboard/google/glados/spd/micron_16GiB_dimm_MT52L1G32D4PG.spd.hex
-./src/mainboard/google/glados/spd/micron_4GiB_dimm_MT52L256M32D1PF.spd.hex
-./src/mainboard/google/glados/spd/micron_8GiB_dimm_MT52L512M32D2PF.spd.hex
-./src/mainboard/google/glados/spd/micron_dimm_MT52L256M32D1PF-107-1G-1866.spd.hex
-./src/mainboard/google/glados/spd/micron_dimm_MT52L512M32D2PF-107-2G-1866.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF-2G-1866.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E6E304EE-EGCF.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E8E304EE-EGCF.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF-1G-1866.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCF.spd.hex
-./src/mainboard/google/glados/spd/samsung_dimm_K4EBE304EB-EGCG.spd.hex
-./src/mainboard/google/glados/spd/spd.c
-./src/mainboard/google/glados/Kconfig
-./src/mainboard/google/hatch/spd/16G_2400.spd.hex
-./src/mainboard/google/hatch/spd/16G_2666.spd.hex
-./src/mainboard/google/hatch/spd/16G_2666_2bg.spd.hex
-./src/mainboard/google/hatch/spd/16G_3200.spd.hex
-./src/mainboard/google/hatch/spd/16G_3200_4bg.spd.hex
-./src/mainboard/google/hatch/spd/4G_2400.spd.hex
-./src/mainboard/google/hatch/spd/8G_2400.spd.hex
-./src/mainboard/google/hatch/spd/8G_2666.spd.hex
-./src/mainboard/google/hatch/spd/8G_3200.spd.hex
-./src/mainboard/google/hatch/spd/LP_16G_2133.spd.hex
-./src/mainboard/google/hatch/spd/LP_8G_2133.spd.hex
-./src/mainboard/google/hatch/spd/empty_ddr4.spd.hex
-./src/mainboard/google/hatch/variants/dratini/variant.c
-./src/mainboard/google/jecht/lan.c
-./src/mainboard/google/kahlee/spd/empty.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5AN8G6NAFR-UH.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-VKC.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5AN8G6NCJR-XNC.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5ANAG6NAMR-UH.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-VKC.spd.hex
-./src/mainboard/google/kahlee/spd/hynix-H5ANAG6NCMR-XNC.spd.hex
-./src/mainboard/google/kahlee/spd/micron-MT40A1G16KNR-075-E.spd.hex
-./src/mainboard/google/kahlee/spd/micron-MT40A1G16RC-062E-B.spd.hex
-./src/mainboard/google/kahlee/spd/micron-MT40A512M16JY-083E-B.spd.hex
-./src/mainboard/google/kahlee/spd/micron-MT40A512M16LY-075-E.spd.hex
-./src/mainboard/google/kahlee/spd/micron-MT40A512M16TB-062E-J.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4A8G165WB-BCRC.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCTD.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4A8G165WC-BCWE.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCTD.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4AAG165WA-BCWE.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCRC.spd.hex
-./src/mainboard/google/kahlee/spd/samsung-K4AAG165WB-MCTD.spd.hex
-./src/mainboard/google/kahlee/variants/baseboard/mainboard.c
-./src/mainboard/google/kahlee/Kconfig
-./src/mainboard/google/link/early_init.c
-./src/mainboard/google/link/elpida_4Gb_1600_x16.spd.hex
-./src/mainboard/google/link/hda_verb.c
-./src/mainboard/google/link/micron_4Gb_1600_1.35v_x16.spd.hex
-./src/mainboard/google/link/samsung_4Gb_1600_1.35v_x16.spd.hex
-./src/mainboard/google/octopus/variants/bloog/variant.c
-./src/mainboard/google/octopus/variants/bobba/variant.c
-./src/mainboard/google/octopus/variants/casta/variant.c
-./src/mainboard/google/octopus/variants/garg/variant.c
-./src/mainboard/google/octopus/variants/meep/variant.c
-./src/mainboard/google/octopus/variants/phaser/mainboard.c
-./src/mainboard/google/peach_pit/mainboard.c
-./src/mainboard/google/poppy/spd/empty.spd.hex
-./src/mainboard/google/poppy/spd/empty_ddr4.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H5AN4G6NAFR-UHC.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H5AN4G6NBJR-UHC.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NAFR-UHC.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H5AN8G6NCJR-VKC.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NAMR-UHC.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H5ANAG6NCMR-VKC.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNN8GTALAR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBJTALAR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNBKTALBR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCLGALAR-NVD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNCPTALBR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/hynix_dimm_H9CCNNNFAGMLLR-NUD.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT40A1G16KNR-075E.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT40A256M16GE-083E.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT40A256M16LY-075F.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16LY-075E.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT40A512M16TB-062EJ.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L1G64D8QC-107.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-093.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L256M32D1PF-107.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L256M64D2PP-107.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-093.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex
-./src/mainboard/google/poppy/spd/micron_dimm_MT52L512M64D4PQ-107.spd.hex
-./src/mainboard/google/poppy/spd/nayna_dimm_NT6CL256T32CM-H1.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K3QF3F30BM-AGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K3QF4F40BM-AGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K3QFAFA0CM-AGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4A4G165WE-BCRC.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4A8G165WB-BCRC.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4A8G165WC-BCTD.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4AAG165WB-MCRC.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304EB-EGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304EC-EGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4E6E304ED-EGCG.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4E8E324EB-EGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EB-EGCG.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EC-EGCF.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304EC-EGCG.spd.hex
-./src/mainboard/google/poppy/spd/samsung_dimm_K4EBE304ED-EGCG.spd.hex
-./src/mainboard/google/poppy/variants/nami/mainboard.c
-./src/mainboard/google/poppy/romstage.c
-./src/mainboard/google/rambi/spd/HT_micron_HTTC4G63CFR-PBA_x16_4Gb.spd.hex
-./src/mainboard/google/rambi/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
-./src/mainboard/google/rambi/spd/Samsung_2Gib_K4B4G1646Q-HYK0.spd.hex
-./src/mainboard/google/rambi/spd/Samsung_2Gib_M471B5674QH0.spd.hex
-./src/mainboard/google/rambi/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex
-./src/mainboard/google/rambi/spd/empty.spd.hex
-./src/mainboard/google/rambi/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
-./src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
-./src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63CFR-PBA.spd.hex
-./src/mainboard/google/rambi/spd/hynix_2GiB_dimm_H5TC4G63MFR-PBA.spd.hex
-./src/mainboard/google/rambi/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
-./src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
-./src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16HA-125a.spd.hex
-./src/mainboard/google/rambi/spd/micron_2GiB_dimm_MT41K256M16TW-107.spd.hex
-./src/mainboard/google/rambi/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex
-./src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646E-BYK0.spd.hex
-./src/mainboard/google/rambi/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
-./src/mainboard/google/rambi/variants/ninja/lan.c
-./src/mainboard/google/rambi/variants/sumo/lan.c
-./src/mainboard/google/rambi/romstage.c
-./src/mainboard/google/reef/variants/coral/mainboard.c
-./src/mainboard/google/sarien/variants/arcada/devicetree.cb
-./src/mainboard/google/slippy/variants/falco/spd/Elpida_EDJ4216EFBG.spd.hex
-./src/mainboard/google/slippy/variants/falco/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/slippy/variants/falco/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/slippy/variants/falco/spd/Samsung_M471B5674QH0.spd.hex
-./src/mainboard/google/slippy/variants/falco/romstage.c
-./src/mainboard/google/slippy/variants/leon/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/slippy/variants/leon/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/slippy/variants/leon/spd/Samsung_K4B4G1646Q.spd.hex
-./src/mainboard/google/slippy/variants/leon/romstage.c
-./src/mainboard/google/slippy/variants/peppy/spd/Elpida_EDJ4216EFBG.spd.hex
-./src/mainboard/google/slippy/variants/peppy/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/slippy/variants/peppy/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/slippy/variants/peppy/romstage.c
-./src/mainboard/google/slippy/variants/wolf/spd/Hynix_HMT425S6AFR6A.spd.hex
-./src/mainboard/google/slippy/variants/wolf/spd/Micron_4KTF25664HZ.spd.hex
-./src/mainboard/google/slippy/variants/wolf/spd/Samsung_K4B4G1646B.spd.hex
-./src/mainboard/google/slippy/variants/wolf/romstage.c
-./src/mainboard/google/dragonegg/romstage_fsp_params.c
-./src/mainboard/google/dragonegg/spd/Hynix_H9HCNNN8KUMLHR_2GB.spd.hex
-./src/mainboard/google/dragonegg/spd/Hynix_H9HCNNNCPMMLHR_4GB.spd.hex
-./src/mainboard/google/dragonegg/spd/Micron_MT53E2G32D8QD_8GB.spd.hex
-./src/mainboard/google/dragonegg/spd/Micron_MT53E512M32D2NP_2GB.spd.hex
-./src/mainboard/hp/abm/mptable.c
-./src/mainboard/hp/pavilion_m6_1035dx/mptable.c
-./src/mainboard/hp/z220_sff_workstation/early_init.c
-./src/mainboard/hp/2760p/early_init.c
-./src/mainboard/hp/8470p/early_init.c
-./src/mainboard/hp/dl165_g6_fam10/romstage.c
-./src/mainboard/hp/revolve_810_g1/early_init.c
-./src/mainboard/hp/revolve_810_g1/spd/hynix_4g.spd.hex
-./src/mainboard/ibase/mb899/cmos.layout
-./src/mainboard/ibase/mb899/superio_hwm.c
-./src/mainboard/intel/apollolake_rvp/romstage.c
-./src/mainboard/intel/coffeelake_rvp/variants/cml_u/include/variant/hda_verb.h
-./src/mainboard/intel/coffeelake_rvp/variants/whl_u/include/variant/hda_verb.h
-./src/mainboard/intel/glkrvp/romstage.c
-./src/mainboard/intel/harcuvar/spd/micron_4GiB_dimm_MTA9ASF51272PZ-2G1A2.spd.hex
-./src/mainboard/intel/harcuvar/spd/spd.c
-./src/mainboard/intel/icelake_rvp/spd/empty.spd.hex
-./src/mainboard/intel/icelake_rvp/spd/samsung_K4F6E304HBMGCJ.spd.hex
-./src/mainboard/intel/icelake_rvp/variants/icl_u/include/variant/hda_verb.h
-./src/mainboard/intel/icelake_rvp/variants/icl_y/include/variant/hda_verb.h
-./src/mainboard/intel/kblrvp/spd/empty.spd.hex
-./src/mainboard/intel/kblrvp/spd/hynix_dimm_H9CCNNNBJTMLAR.spd.hex
-./src/mainboard/intel/kblrvp/spd/rvp3.spd.hex
-./src/mainboard/intel/kblrvp/variants/rvp11/include/variant/hda_verb.h
-./src/mainboard/intel/kblrvp/variants/rvp3/include/variant/hda_verb.h
-./src/mainboard/intel/kblrvp/variants/rvp7/include/variant/hda_verb.h
-./src/mainboard/intel/kblrvp/Kconfig
-./src/mainboard/intel/kunimitsu/spd/empty.spd.hex
-./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTALAR-NUD-1G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNN8JTBLAR-NUD-1G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTALAR-NUD-2G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/hynix_dimm_H9CCNNNBLTBLAR-NUD-2G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/mic_dimm_EDF8132A3MA-JD-F-1G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E6E304EE-EGCF-2G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCE.spd.hex
-./src/mainboard/intel/kunimitsu/spd/samsung_dimm_K4E8E304EE-EGCF-1G-1866.spd.hex
-./src/mainboard/intel/kunimitsu/spd/spd_util.c
-./src/mainboard/intel/leafhill/Kconfig
-./src/mainboard/intel/leafhill/romstage.c
-./src/mainboard/intel/minnow3/Kconfig
-./src/mainboard/intel/minnow3/romstage.c
-./src/mainboard/intel/strago/Kconfig
-./src/mainboard/intel/cannonlake_rvp/spd/empty.spd.hex
-./src/mainboard/intel/cannonlake_rvp/spd/samsung_ddr4_4GB.spd.hex
-./src/mainboard/intel/cannonlake_rvp/spd/samsung_lpddr4_8GB.spd.hex
-./src/mainboard/intel/mohonpeak/Kconfig
-./src/mainboard/jetway/nf81-t56n-lf/Kconfig
-./src/mainboard/jetway/pa78vm5/romstage.c
-./src/mainboard/kontron/986lcd-m/cmos.layout
-./src/mainboard/kontron/986lcd-m/mainboard.c
-./src/mainboard/lenovo/g505s/mptable.c
-./src/mainboard/lenovo/s230u/spd/elpida_2gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/elpida_4gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/elpida_8gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/hynix_2gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/hynix_4gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/samsung_2gb.spd.hex
-./src/mainboard/lenovo/s230u/spd/samsung_4gb.spd.hex
-./src/mainboard/lenovo/s230u/early_init.c
-./src/mainboard/lenovo/t430s/variants/t431s/spd/samsung_4gb.spd.hex
-./src/mainboard/lenovo/t430s/variants/t431s/romstage.c
-./src/mainboard/lenovo/x1_carbon_gen1/spd/elpida.hex
-./src/mainboard/lenovo/x1_carbon_gen1/spd/hynix.hex
-./src/mainboard/lenovo/x1_carbon_gen1/spd/samsung.hex
-./src/mainboard/lenovo/x1_carbon_gen1/early_init.c
-./src/mainboard/lenovo/x220/variants/x1/romstage.c
-./src/mainboard/lenovo/x220/early_init.c
-./src/mainboard/lippert/frontrunner-af/Kconfig
-./src/mainboard/lippert/frontrunner-af/mptable.c
-./src/mainboard/lippert/toucan-af/Kconfig
-./src/mainboard/lippert/toucan-af/mptable.c
-./src/mainboard/msi/ms7707/Kconfig
-./src/mainboard/msi/ms7707/early_init.c
-./src/mainboard/msi/ms7721/mptable.c
-./src/mainboard/msi/ms9652_fam10/romstage.c
-./src/mainboard/opencellular/elgon/gbcv2.dts
-./src/mainboard/packardbell/ms2290/mainboard.c
-./src/mainboard/pcengines/apu1/Kconfig
-./src/mainboard/pcengines/apu2/Kconfig
-./src/mainboard/portwell/m107/spd/KINGSTON_B5116ECMDXGGB.spd.hex
-./src/mainboard/portwell/m107/spd/MICRON_MT41K512M16HA-125A.spd.hex
-./src/mainboard/portwell/m107/spd/SAMSUNG_K4B8G1646D-MYKO.spd.hex
-./src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L1G32D4PG-107.spd.hex
-./src/mainboard/razer/blade_stealth_kbl/spd/micron_dimm_MT52L512M32D2PF-107.spd.hex
-./src/mainboard/samsung/lumpy/early_init.c
-./src/mainboard/sapphire/pureplatinumh61/early_init.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl1/lcd_panel.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl4/lcd_panel.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl5/lcd_panel.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c
-./src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c
-./src/mainboard/siemens/mc_apl1/mainboard.c
-./src/mainboard/siemens/mc_apl1/romstage.c
-./src/mainboard/siemens/mc_bdx1/mainboard.c
-./src/mainboard/siemens/mc_tcu3/lcd_panel.c
-./src/mainboard/siemens/mc_tcu3/mainboard.c
-./src/mainboard/siemens/mc_tcu3/romstage.c
-./src/mainboard/supermicro/h8dmr_fam10/romstage.c
-./src/mainboard/supermicro/h8qme_fam10/romstage.c
-./src/mainboard/supermicro/h8scm_fam10/romstage.c
-./src/mainboard/up/squared/romstage.c
-./src/mainboard/adi/rcc-dff/Kconfig
-./src/mainboard/advansus/a785e-i/mptable.c
-./src/mainboard/advansus/a785e-i/romstage.c
-./src/mainboard/avalue/eax-785e/mptable.c
-./src/mainboard/avalue/eax-785e/romstage.c
-./src/mainboard/iei/kino-780am2-fam10/romstage.c
-./src/mainboard/tyan/s2912_fam10/romstage.c
-./src/northbridge/amd/pi/00630F01/Kconfig
-./src/northbridge/amd/pi/00730F01/Kconfig
-./src/northbridge/amd/pi/00660F01/Kconfig
-./src/northbridge/amd/amdmct/mct/mctardk3.c
-./src/northbridge/amd/amdmct/mct/mctardk4.c
-./src/northbridge/amd/amdmct/mct/mcttmrl.c
-./src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
-./src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-./src/northbridge/intel/gm45/raminit_read_write_training.c
-./src/northbridge/intel/haswell/Kconfig
-./src/northbridge/intel/haswell/raminit.c
-./src/northbridge/intel/i945/raminit.c
-./src/northbridge/intel/pineview/raminit.c
-./src/northbridge/intel/sandybridge/Kconfig
-./src/northbridge/intel/sandybridge/gma.c
-./src/northbridge/intel/sandybridge/raminit.c
-./src/northbridge/intel/sandybridge/raminit_mrc.c
-./src/northbridge/intel/sandybridge/raminit_patterns.h
-./src/northbridge/intel/x4x/dq_dqs.c
-./src/northbridge/intel/x4x/raminit_ddr23.c
-./src/northbridge/intel/x4x/raminit_tables.c
-./src/northbridge/intel/fsp_rangeley/fsp/Kconfig
-./src/northbridge/intel/nehalem/raminit.c
-./src/northbridge/intel/nehalem/raminit_tables.c
-./src/security/intel/txt/Kconfig
-./src/security/tpm/tss/tcg-1.2/tss_commands.h
-./src/security/vboot/secdata_tpm.c
-./src/soc/amd/picasso/Kconfig
-./src/soc/amd/stoneyridge/Kconfig
-./src/soc/cavium/cn81xx/Kconfig
-./src/soc/cavium/common/rom_clib_s_nbl1fw.bin.hex
-./src/soc/cavium/common/rom_csib_s_nbl1fw.bin.hex
-./src/soc/intel/apollolake/Kconfig
-./src/soc/intel/apollolake/nhlt.c
-./src/soc/intel/baytrail/bootblock/bootblock.c
-./src/soc/intel/baytrail/romstage/raminit.c
-./src/soc/intel/baytrail/Kconfig
-./src/soc/intel/baytrail/acpi.c
-./src/soc/intel/braswell/acpi.c
-./src/soc/intel/braswell/gpio.c
-./src/soc/intel/broadwell/Kconfig
-./src/soc/intel/broadwell/acpi.c
-./src/soc/intel/broadwell/romstage/raminit.c
-./src/soc/intel/cannonlake/nhlt.c
-./src/soc/intel/common/block/cpu/car/cache_as_ram_fsp.S
-./src/soc/intel/common/mma.c
-./src/soc/intel/denverton_ns/acpi.c
-./src/soc/intel/denverton_ns/chip.c
-./src/soc/intel/quark/romstage/romstage.c
-./src/soc/intel/quark/Kconfig
-./src/soc/intel/skylake/nhlt/da7219.c
-./src/soc/intel/skylake/nhlt/dmic.c
-./src/soc/intel/skylake/nhlt/max98357.c
-./src/soc/intel/skylake/nhlt/max98373.c
-./src/soc/intel/skylake/nhlt/max98927.c
-./src/soc/intel/skylake/nhlt/nau88l25.c
-./src/soc/intel/skylake/nhlt/rt5514.c
-./src/soc/intel/skylake/nhlt/rt5663.c
-./src/soc/intel/skylake/nhlt/ssm4567.c
-./src/soc/intel/fsp_baytrail/Kconfig
-./src/soc/intel/fsp_baytrail/acpi.c
-./src/soc/intel/fsp_baytrail/bootblock/bootblock.c
-./src/soc/intel/fsp_broadwell_de/bootblock/bootblock.c
-./src/soc/intel/fsp_broadwell_de/fsp/Kconfig
-./src/soc/intel/fsp_broadwell_de/fsp/chipset_fsp_util.c
-./src/soc/mediatek/mt8183/spm.c
-./src/soc/mediatek/mt8183/sspm.c
-./src/soc/nvidia/tegra210/Kconfig
-./src/soc/nvidia/tegra210/mtc.c
-./src/soc/qualcomm/ipq40xx/Kconfig
-./src/soc/qualcomm/ipq40xx/lcc.c
-./src/soc/qualcomm/ipq806x/Kconfig
-./src/soc/qualcomm/ipq806x/blobs_init.c
-./src/soc/qualcomm/ipq806x/lcc.c
-./src/soc/samsung/exynos5250/clock.c
-./src/soc/samsung/exynos5420/clock.c
-./src/southbridge/amd/agesa/hudson/Kconfig
-./src/southbridge/amd/cimx/sb800/Kconfig
-./src/southbridge/amd/pi/hudson/Kconfig
-./src/southbridge/intel/bd82x6x/lpc.c
-./src/southbridge/intel/common/firmware/Kconfig
-./src/southbridge/intel/i82801ix/dmi_setup.c
-./src/southbridge/nvidia/ck804/early_setup_ss.h
-./src/southbridge/nvidia/mcp55/early_setup_ss.h
-./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/ON/F14OnInitEarlyTable.c
-./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
-./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
-./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
-./src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
-./src/vendorcode/amd/agesa/f14/Proc/CPU/cpuMicrocodePatch.c
-./src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
-./src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
-./src/vendorcode/amd/agesa/f14/Proc/Mem/Main/muc.c
-./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnInitEarlyTable.c
-./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
-./src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/cpuF15WheaInitDataTables.c
-./src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuMicrocodePatch.c
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxIntegratedInfoTableTN.c
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
-./src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
-./src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/muc.c
-./src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/TN/mptn3.c
-./src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/DDR3/mtlrdimm3.c
-./src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
-./src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbInitEarlyTable.c
-./src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/cpuF16WheaInitDataTables.c
-./src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuMicrocodePatch.c
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbGfxIntTableV3/GfxLibV3.c
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbF1TableKB.c
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h
-./src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/excel925.h
-./src/vendorcode/amd/agesa/f16kb/Proc/Mem/Main/muc.c
-./src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpkb3.c
-./src/vendorcode/amd/cimx/sb800/SATA.c
-./src/vendorcode/amd/pi/Kconfig
-./src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-8514.c
-./src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse-xfi.c
-./src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse.c
-./src/vendorcode/cavium/bdk/libdram/lib_octeon_shared.c
-./src/vendorcode/eltan/security/verified_boot/vboot_check.c
-./src/vendorcode/google/chromeos/build-snow.sh
-./src/vendorcode/google/chromeos/sar.c
-./src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/IndustryStandard/Tpm12.h
-./src/vendorcode/intel/edk2/UDK2017/MdePkg/Include/Protocol/HiiConfigAccess.h
-./src/vendorcode/intel/fsp/fsp2_0/cannonlake/FspmUpd.h
-./src/vendorcode/intel/fsp/fsp2_0/cometlake/FspmUpd.h
-./util/amdtools/example_input/lspci-cb-48G-667MHz-18.2-20090909e
-./util/amdtools/example_input/lspci-prop-48G-667MHz-18.2
-./util/autoport/readme.md
-./util/bincfg/bincfg.lex.c_shipped
-./util/bincfg/bincfg.tab.c_shipped
-./util/cbfstool/lz4/lib/lz4.c
-./util/cbfstool/fit.c
-./util/cbfstool/fmd_parser.c_shipped
-./util/cbfstool/fmd_scanner.c_shipped
-./util/cbfstool/linux_trampoline.c
-./util/ifdtool/ifdtool.c
-./util/intelmetool/intelmetool.c
-./util/kbc1126/kbc1126_ec_dump.c
-./util/kconfig/zconf.hash.c_shipped
-./util/kconfig/zconf.lex.c_shipped
-./util/kconfig/zconf.tab.c_shipped
-./util/mma/mma_automated_test.sh
-./util/mtkheader/gen-bl-img.py
-./util/nvidia/cbootimage/samples/sign.sh
-./util/nvidia/cbootimage/src/aes_ref.c
-./util/nvramtool/accessors/layout-bin.c
-./util/qualcomm/scripts/cmm/debug_cb_common.cmm
-./util/qualcomm/createxbl.py
-./util/riscv/make-spike-elf.sh
-./util/riscv/sifive-gpt.py
-./util/rockchip/make_idb.py
-./util/sconfig/lex.yy.c_shipped
-./util/sconfig/sconfig.tab.c_shipped
-./util/spdtool/spdtool.py
-./util/superiotool/fintek.c
-./util/superiotool/ite.c
-./util/superiotool/nuvoton.c
-./util/superiotool/smsc.c
-./util/superiotool/winbond.c
-./util/xcompile/xcompile
-./util/genprof/genprof.c
-./util/romcc/test.sh
-./util/romcc/tests/include/linux_console.h
-./util/romcc/tests/linux_console.h
-./util/romcc/tests/linux_test5.c
-./util/romcc/tests/raminit_test6.c
-./util/romcc/tests/raminit_test7.c
-./util/romcc/tests/simple_test14.c
-./util/romcc/tests/simple_test30.c
-./util/romcc/tests/simple_test38.c
-./util/romcc/tests/simple_test39.c
-./util/romcc/tests/simple_test54.c
-./util/romcc/tests/simple_test59.c
-./util/romcc/tests/simple_test72.c
-./util/romcc/tests/simple_test73.c
-./Makefile.inc
-./deblob-check

resources/coreboot/fam15h_udimm/patches/0001-Revert-Revert-nb-amd-mct_ddr3-Fix-RDIMM-training-fai.patch

@@ -1,31 +0,0 @@
-From 8f2988cba4fffef1bd4f65e123c76bf4b7a18672 Mon Sep 17 00:00:00 2001
-From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
-Date: Sun, 7 Feb 2021 15:29:40 +0100
-Subject: [PATCH 1/6] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training
- failure on Fam15h" (fixes a bug that prevent certain RAM modules from
- booting)
-
-This reverts commit 610d1c67b2298a9840681c2b4492b6d3fdf44a46.
-
-After 610d1c67b2298a9840681c2b4492b6d3fdf44a46 many RAM modules wouldn't work and you couldn't even see any output on the screen.
----
- src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
-index ddaaaab8d5..3b07786b91 100644
---- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
-+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
-@@ -71,6 +71,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
- 		misc2 |= ((cs_mux_67 & 0x1) << 27);
- 		misc2 &= ~(0x1 << 26);		/* CsMux45 = cs_mux_45 */
- 		misc2 |= ((cs_mux_45 & 0x1) << 26);
-+
-+		if (pDCTstat->Status & (1 << SB_Registered))
-+			misc2 |= 1 << SubMemclkRegDly;
- 	} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
- 		if (pDCTstat->Status & (1 << SB_Registered)) {
- 			misc2 |= 1 << SubMemclkRegDly;
--- 
-2.25.1
-

resources/coreboot/fam15h_udimm/patches/0003-Tweak-cmos-defaults-for-KCMA-D8-for-a-little-speed-b.patch

@@ -1,38 +0,0 @@
-From 7a00638cea41ad939a59fc0e5996959435fbdb7f Mon Sep 17 00:00:00 2001
-From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
-Date: Sun, 7 Feb 2021 16:40:05 +0100
-Subject: [PATCH 3/6] Tweak cmos defaults for KCMA-D8 (for a little speed
- boost)
-
-63xx CPUs have the option to use a reduced latency value inside the crossbar.
-Setting "experimental_memory_speed_boost=Enable" aparently only has an effect
-on 63xx CPUs and may, in certain cases, yield a slight memory bandwidth
-increase (according to Timothy Pearson), but maybe it also works for
-43xx CPUs.
-
-Setting "l3_cache_partitioning=Enable" will increase performance in certain
-situations. See:
-https://developer.arm.com/documentation/100453/0401/functional-description/l3-cache/l3-cache-partitioning?lang=en
----
- src/mainboard/asus/kcma-d8/cmos.default | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default
-index 306687157f..4e033d756f 100644
---- a/src/mainboard/asus/kcma-d8/cmos.default
-+++ b/src/mainboard/asus/kcma-d8/cmos.default
-@@ -21,9 +21,9 @@ sata_ahci_mode=Enable
- sata_alpm=Disable
- maximum_p_state_limit=0xf
- probe_filter=Auto
--l3_cache_partitioning=Disable
-+l3_cache_partitioning=Enable
- gart=Enable
- ehci_async_data_cache=Enable
--experimental_memory_speed_boost=Disable
-+experimental_memory_speed_boost=Enable
- power_on_after_fail=On
- boot_option=Fallback
--- 
-2.25.1
-

resources/coreboot/fam15h_udimm/patches/0004-Do-not-use-microcode-updates-on-AMD-platforms.patch

@@ -1,108 +0,0 @@
-From 2b1d40b970d9cbbb4f8fe30679e9b6909aa3d99a Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Thu, 6 May 2021 17:07:06 +0100
-Subject: [PATCH 4/6] Do not use microcode updates on AMD platforms
-
-Coreboot is hardcoding the use of microcode updates on some platforms.
-
-Just nuke it from orbit. This is the libre branch of osboot, so microcode must
-not be used.
----
- src/cpu/Makefile.inc                          | 52 +------------------
- src/cpu/amd/family_10h-family_15h/Kconfig     |  1 -
- .../amd/family_10h-family_15h/Makefile.inc    | 10 +---
- 3 files changed, 2 insertions(+), 61 deletions(-)
-
-diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
-index b80c30d72b..e7909d32ed 100644
---- a/src/cpu/Makefile.inc
-+++ b/src/cpu/Makefile.inc
-@@ -14,54 +14,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
- ## Rules for building the microcode blob in CBFS
- ################################################################################
- 
--ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
--cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
--cbfs-files-y  += cpu_microcode_blob.bin
--cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
--
--$(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER_FILES))
--	echo "   util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
--	util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
--endif
--
--ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y)
--cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
--endif
--# otherwise `cpu_microcode_bins` should be filled by platform makefiles
--
--# We just mash all microcode binaries together into one binary to rule them all.
--# This approach assumes that the microcode binaries are properly padded, and
--# their headers specify the correct size. This works fairly well on isolatied
--# updates, such as Intel and some AMD microcode, but won't work very well if the
--# updates are wrapped in a container, like AMD's microcode update container. If
--# there is only one microcode binary (i.e. one container), then we don't have
--# this issue, and this rule will continue to work.
--$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))
--	for bin in $(cpu_microcode_bins); do \
--		if [ ! -f "$$bin" ]; then \
--			echo "Microcode error: $$bin does not exist"; \
--			NO_MICROCODE_FILE=1; \
--		fi; \
--	done; \
--	if [ -n "$$NO_MICROCODE_FILE" ]; then \
--		if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \
--			echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
--		fi; \
--		false; \
--	fi
--	$(if $^,,false) # fail if no file is given at all
--	@printf "    MICROCODE  $(subst $(obj)/,,$(@))\n"
--	@echo $(cpu_microcode_bins)
--	cat $^ > $@
--
--cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
--cpu_microcode_blob.bin-type := microcode
--
--ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
--cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
--else
--cpu_microcode_blob.bin-align := 16
--endif
-+# No microcode permitted in this version of coreboot.
-diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
-index ad4f5f4ba6..21150ab1a7 100644
---- a/src/cpu/amd/family_10h-family_15h/Kconfig
-+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
-@@ -8,7 +8,6 @@ config CPU_AMD_MODEL_10XXX
- 	select TSC_SYNC_LFENCE
- 	select UDELAY_LAPIC
- 	select SUPPORT_CPU_UCODE_IN_CBFS
--	select CPU_MICROCODE_MULTIPLE_FILES
- 	select CAR_GLOBAL_MIGRATION
- 
- if CPU_AMD_MODEL_10XXX
-diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-index 7035323026..e0029f562d 100644
---- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
-+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
-@@ -14,12 +14,4 @@ ramstage-y += ram_calc.c
- ramstage-y += monotonic_timer.c
- ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
- 
--# Microcode for Family 10h, 11h, 12h, and 14h
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin
--microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
--microcode_amd.bin-type := microcode
--
--# Microcode for Family 15h
--cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
--microcode_amd_fam15h.bin-type := microcode
-+# Microcode deleted in this version of coreboot.
--- 
-2.25.1
-

resources/coreboot/fam15h_udimm/patches/0006-asus-kgpe-d16-enable-lc_cache_partitioning-and-exper.patch

@@ -1,32 +0,0 @@
-From f0aac7261e16adc8e61eca7a506ff2de5112be47 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Fri, 7 May 2021 19:43:32 +0100
-Subject: [PATCH 6/6] asus/kgpe-d16: enable lc_cache_partitioning and
- experimental_memory_speed_boost
-
-This really only benefits 63xx opterons which are less reliable in libreboot due
-to lack of CPU microcode updates, but we might aswell enable this anyway.
----
- src/mainboard/asus/kgpe-d16/cmos.default | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
-index 7c496a50d7..8a25620e1d 100644
---- a/src/mainboard/asus/kgpe-d16/cmos.default
-+++ b/src/mainboard/asus/kgpe-d16/cmos.default
-@@ -21,10 +21,10 @@ sata_ahci_mode=Enable
- sata_alpm=Disable
- maximum_p_state_limit=0xf
- probe_filter=Auto
--l3_cache_partitioning=Disable
-+l3_cache_partitioning=Enable
- ieee1394_controller=Enable
- gart=Enable
- ehci_async_data_cache=Enable
--experimental_memory_speed_boost=Disable
-+experimental_memory_speed_boost=Enable
- power_on_after_fail=On
- boot_option=Fallback
--- 
-2.25.1
-

resources/coreboot/g43t-am3/board.cfg

@@ -1,6 +1,8 @@
 cbtree="default"
 romtype="normal"
 arch="x86_64"
-payload_grub="y"
-payload_grub_withseabios="y"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
+microcode_required="n"
+blobs_required="n"

resources/coreboot/g43t-am3/config/libgfxinit_txtmode

@@ -11,14 +11,17 @@ CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -34,6 +37,12 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
 # CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
 # end of General setup
 
 #
@@ -51,30 +60,25 @@ CONFIG_VENDOR_ACER=y
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BAP is not set
 # CONFIG_VENDOR_BIOSTAR is not set
 # CONFIG_VENDOR_BOSTENTECH is not set
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
 # CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_ELMEX is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GIZMOSPHERE is not set
 # CONFIG_VENDOR_GOOGLE is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_JETWAY is not set
 # CONFIG_VENDOR_KONTRON is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_LIPPERT is not set
 # CONFIG_VENDOR_MSI is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
@@ -89,9 +93,9 @@ CONFIG_VENDOR_ACER=y
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
 # CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SCALEWAY is not set
 # CONFIG_VENDOR_SIEMENS is not set
 # CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
@@ -106,24 +110,24 @@ CONFIG_DIMM_SPD_SIZE=256
 CONFIG_FMDFILE=""
 # CONFIG_NO_POST is not set
 CONFIG_MAINBOARD_VENDOR="Acer"
+# CONFIG_BOARD_ACER_VN7_572G is not set
 CONFIG_BOARD_ACER_G43T_AM3=y
 CONFIG_CBFS_SIZE=0x200000
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_MAX_CPUS=4
-# CONFIG_VBOOT is not set
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
 CONFIG_DEVICETREE="devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Acer"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-CONFIG_UART_FOR_CONSOLE=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_POST_DEVICE=y
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 CONFIG_DCACHE_RAM_BASE=0xfeff8000
 CONFIG_DCACHE_RAM_SIZE=0x8000
@@ -136,9 +140,8 @@ CONFIG_HAVE_INTEL_FIRMWARE=y
 CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CONSOLE_SERIAL=y
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="G43T-AM3"
 # CONFIG_HAVE_IFD_BIN is not set
 CONFIG_PCIEXP_HOTPLUG_BUSES=32
@@ -147,10 +150,12 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
 CONFIG_PS2K_EISAID="PNP0303"
 CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
+# CONFIG_DEBUG_SMI is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 CONFIG_PCIEXP_CLK_PM=y
-CONFIG_DRIVERS_UART_8250IO=y
+# CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_HEAP_SIZE=0x4000
+CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -182,32 +187,29 @@ CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
 #
 # SoC
 #
-CONFIG_ARCH_ALL_STAGES_X86=y
 CONFIG_CHIPSET_DEVICETREE=""
 CONFIG_CBFS_MCACHE_SIZE=0x4000
 CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_RAMBASE=0xe00000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d"
+CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X"
 CONFIG_EHCI_BAR=0xfef00000
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_STACK_SIZE=0x1000
+CONFIG_STACK_SIZE=0x2000
 CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_BOOTBLOCK_IN_CBFS=y
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_AZALIA_MAX_CODECS=4
 CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_TTYS0_BASE=0x3f8
-CONFIG_TTYS0_LCS=3
-CONFIG_UART_PCI_ADDR=0x0
+CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_CBFS_CACHE_ALIGN=8
 
 #
 # CPU
@@ -217,7 +219,6 @@ CONFIG_CPU_INTEL_MODEL_1067X=y
 CONFIG_CPU_INTEL_MODEL_F3X=y
 CONFIG_CPU_INTEL_MODEL_F4X=y
 CONFIG_SOCKET_SPECIFIC_OPTIONS=y
-CONFIG_SSE2=y
 CONFIG_CPU_INTEL_SOCKET_LGA775=y
 CONFIG_CPU_INTEL_COMMON=y
 CONFIG_ENABLE_VMX=y
@@ -230,6 +231,7 @@ CONFIG_PARALLEL_MP=y
 CONFIG_XAPIC_ONLY=y
 # CONFIG_X2APIC_ONLY is not set
 # CONFIG_X2APIC_RUNTIME is not set
+# CONFIG_X2APIC_LATE_WORKAROUND is not set
 CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
@@ -237,28 +239,27 @@ CONFIG_SETUP_XIP_CACHE=y
 CONFIG_LOGICAL_CPUS=y
 CONFIG_HAVE_SMI_HANDLER=y
 CONFIG_SMM_TSEG=y
-CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
-CONFIG_SMM_STUB_STACK_SIZE=0x400
-CONFIG_CPU_INFO_V2=y
+CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
+CONFIG_AP_STACK_SIZE=0x800
 CONFIG_SMP=y
 CONFIG_MMX=y
 CONFIG_SSE=y
+CONFIG_SSE2=y
 CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-# CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS is not set
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
 
 #
 # Northbridge
 #
-CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y
 CONFIG_NORTHBRIDGE_INTEL_X4X=y
 
 #
 # Southbridge
 #
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_PCIEXP_HOTPLUG=y
 CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
@@ -276,10 +277,10 @@ CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
 CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
 # CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
 CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
 CONFIG_RCBA_LENGTH=0x4000
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
 
 #
 # Super I/O
@@ -309,17 +310,16 @@ CONFIG_HAVE_EXP_X86_64_SUPPORT=y
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_RAMTOP=0x1000000
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_NUM_IPI_STARTS=2
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_HPET_ADDRESS=0xfed00000
 CONFIG_POSTCAR_STAGE=y
 CONFIG_BOOTBLOCK_SIMPLE=y
 # CONFIG_BOOTBLOCK_NORMAL is not set
 CONFIG_COLLECT_TIMESTAMPS_TSC=y
 CONFIG_HAVE_CF9_RESET=y
+CONFIG_DEBUG_HW_BREAKPOINTS=y
+CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # end of Chipset
 
 #
@@ -331,6 +331,7 @@ CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
 CONFIG_MAINBOARD_USE_LIBGFXINIT=y
 # CONFIG_VGA_ROM_RUN is not set
 # CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
 
 #
 # Display
@@ -349,16 +350,26 @@ CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
 CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
+# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
-CONFIG_RESOURCE_ALLOCATOR_V4=y
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_NO_DDR5=y
+CONFIG_NO_LPDDR4=y
+CONFIG_NO_DDR4=y
+CONFIG_USE_DDR3=y
+CONFIG_USE_DDR2=y
 # end of Devices
 
 #
@@ -383,15 +394,18 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DRIVERS_UART=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 CONFIG_HAVE_USBDEBUG_OPTIONS=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
 CONFIG_DRIVERS_I2C_CK505=y
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
@@ -401,18 +415,24 @@ CONFIG_GFX_GMA_GENERATION="G45"
 CONFIG_GFX_GMA_PCH="No_PCH"
 CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
 CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
 # end of Generic Drivers
 
 #
 # Security
 #
 
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
 #
 # Verified Boot (vboot)
 #
@@ -451,27 +471,12 @@ CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_BOOTBLOCK_CONSOLE=y
 CONFIG_POSTCAR_CONSOLE=y
 CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_BAUD=115200
 # CONFIG_SPKMODEM is not set
 # CONFIG_CONSOLE_NE2K is not set
 CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
 # CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
@@ -482,6 +487,8 @@ CONFIG_CONSOLE_CBMEM=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
 # CONFIG_CMOS_POST is not set
 CONFIG_POST_DEVICE_NONE=y
 # CONFIG_POST_DEVICE_LPC is not set
@@ -508,28 +515,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # Payload
 #
 CONFIG_PAYLOAD_NONE=y
-# CONFIG_PAYLOAD_ELF is not set
-# CONFIG_PAYLOAD_BOOTBOOT is not set
-# CONFIG_PAYLOAD_FILO is not set
-# CONFIG_PAYLOAD_GRUB2 is not set
-# CONFIG_PAYLOAD_LINUXBOOT is not set
-# CONFIG_PAYLOAD_SEABIOS is not set
-# CONFIG_PAYLOAD_UBOOT is not set
-# CONFIG_PAYLOAD_YABITS is not set
-# CONFIG_PAYLOAD_LINUX is not set
-# CONFIG_PAYLOAD_TIANOCORE is not set
-CONFIG_PAYLOAD_OPTIONS=""
-# CONFIG_PXE is not set
-CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
-
-#
-# Secondary Payloads
-#
-# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
-# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
-# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
-# CONFIG_TINT_SECONDARY_PAYLOAD is not set
-# end of Secondary Payloads
 # end of Payload
 
 #
@@ -548,19 +533,16 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
 #
 # General Debug Settings
 #
-# CONFIG_GDB_STUB is not set
 # CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_SMI is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set
 # CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_HAVE_EM100_SUPPORT is not set
 # end of Debugging
 
 CONFIG_RAMSTAGE_ADA=y
@@ -568,6 +550,7 @@ CONFIG_RAMSTAGE_LIBHWBASE=y
 CONFIG_HWBASE_DYNAMIC_MMIO=y
 CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
 CONFIG_HWBASE_DIRECT_PCIDEV=y
+CONFIG_DECOMPRESS_OFAST=y
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

resources/coreboot/g43t-am3_16mb/board.cfg

@@ -1,7 +1,9 @@
 cbtree="default"
 romtype="normal"
 arch="x86_64"
-payload_grub="y"
-payload_grub_withseabios="y"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
-payload_memtest="y"
+payload_memtest="n"
+microcode_required="n"
+blobs_required="n"

resources/coreboot/g43t-am3_16mb/config/libgfxinit_txtmode

@@ -11,14 +11,17 @@ CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -34,6 +37,12 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
 # CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
 # end of General setup
 
 #
@@ -51,30 +60,25 @@ CONFIG_VENDOR_ACER=y
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BAP is not set
 # CONFIG_VENDOR_BIOSTAR is not set
 # CONFIG_VENDOR_BOSTENTECH is not set
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
 # CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_ELMEX is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GIZMOSPHERE is not set
 # CONFIG_VENDOR_GOOGLE is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_JETWAY is not set
 # CONFIG_VENDOR_KONTRON is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_LIPPERT is not set
 # CONFIG_VENDOR_MSI is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
@@ -89,9 +93,9 @@ CONFIG_VENDOR_ACER=y
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
 # CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SCALEWAY is not set
 # CONFIG_VENDOR_SIEMENS is not set
 # CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
@@ -106,24 +110,24 @@ CONFIG_DIMM_SPD_SIZE=256
 CONFIG_FMDFILE=""
 # CONFIG_NO_POST is not set
 CONFIG_MAINBOARD_VENDOR="Acer"
+# CONFIG_BOARD_ACER_VN7_572G is not set
 CONFIG_BOARD_ACER_G43T_AM3=y
 CONFIG_CBFS_SIZE=0x1000000
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_MAX_CPUS=4
-# CONFIG_VBOOT is not set
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
 CONFIG_DEVICETREE="devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Acer"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-CONFIG_UART_FOR_CONSOLE=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_POST_DEVICE=y
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 CONFIG_DCACHE_RAM_BASE=0xfeff8000
 CONFIG_DCACHE_RAM_SIZE=0x8000
@@ -136,9 +140,8 @@ CONFIG_HAVE_INTEL_FIRMWARE=y
 CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CONSOLE_SERIAL=y
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="G43T-AM3"
 # CONFIG_HAVE_IFD_BIN is not set
 CONFIG_PCIEXP_HOTPLUG_BUSES=32
@@ -147,10 +150,12 @@ CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
 CONFIG_PS2K_EISAID="PNP0303"
 CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
+# CONFIG_DEBUG_SMI is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 CONFIG_PCIEXP_CLK_PM=y
-CONFIG_DRIVERS_UART_8250IO=y
+# CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_HEAP_SIZE=0x4000
+CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_2048=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -182,32 +187,29 @@ CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
 #
 # SoC
 #
-CONFIG_ARCH_ALL_STAGES_X86=y
 CONFIG_CHIPSET_DEVICETREE=""
 CONFIG_CBFS_MCACHE_SIZE=0x4000
 CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_RAMBASE=0xe00000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d"
+CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X"
 CONFIG_EHCI_BAR=0xfef00000
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_STACK_SIZE=0x1000
+CONFIG_STACK_SIZE=0x2000
 CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_BOOTBLOCK_IN_CBFS=y
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_AZALIA_MAX_CODECS=4
 CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_TTYS0_BASE=0x3f8
-CONFIG_TTYS0_LCS=3
-CONFIG_UART_PCI_ADDR=0x0
+CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_CBFS_CACHE_ALIGN=8
 
 #
 # CPU
@@ -217,7 +219,6 @@ CONFIG_CPU_INTEL_MODEL_1067X=y
 CONFIG_CPU_INTEL_MODEL_F3X=y
 CONFIG_CPU_INTEL_MODEL_F4X=y
 CONFIG_SOCKET_SPECIFIC_OPTIONS=y
-CONFIG_SSE2=y
 CONFIG_CPU_INTEL_SOCKET_LGA775=y
 CONFIG_CPU_INTEL_COMMON=y
 CONFIG_ENABLE_VMX=y
@@ -230,6 +231,7 @@ CONFIG_PARALLEL_MP=y
 CONFIG_XAPIC_ONLY=y
 # CONFIG_X2APIC_ONLY is not set
 # CONFIG_X2APIC_RUNTIME is not set
+# CONFIG_X2APIC_LATE_WORKAROUND is not set
 CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
@@ -237,28 +239,27 @@ CONFIG_SETUP_XIP_CACHE=y
 CONFIG_LOGICAL_CPUS=y
 CONFIG_HAVE_SMI_HANDLER=y
 CONFIG_SMM_TSEG=y
-CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
-CONFIG_SMM_STUB_STACK_SIZE=0x400
-CONFIG_CPU_INFO_V2=y
+CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
+CONFIG_AP_STACK_SIZE=0x800
 CONFIG_SMP=y
 CONFIG_MMX=y
 CONFIG_SSE=y
+CONFIG_SSE2=y
 CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-# CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS is not set
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
 
 #
 # Northbridge
 #
-CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y
 CONFIG_NORTHBRIDGE_INTEL_X4X=y
 
 #
 # Southbridge
 #
-CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_PCIEXP_HOTPLUG=y
 CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
@@ -276,10 +277,10 @@ CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
 CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
 # CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
 CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
 CONFIG_RCBA_LENGTH=0x4000
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
 
 #
 # Super I/O
@@ -309,17 +310,16 @@ CONFIG_HAVE_EXP_X86_64_SUPPORT=y
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_RAMTOP=0x1000000
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_NUM_IPI_STARTS=2
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_HPET_ADDRESS=0xfed00000
 CONFIG_POSTCAR_STAGE=y
 CONFIG_BOOTBLOCK_SIMPLE=y
 # CONFIG_BOOTBLOCK_NORMAL is not set
 CONFIG_COLLECT_TIMESTAMPS_TSC=y
 CONFIG_HAVE_CF9_RESET=y
+CONFIG_DEBUG_HW_BREAKPOINTS=y
+CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # end of Chipset
 
 #
@@ -331,6 +331,7 @@ CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
 CONFIG_MAINBOARD_USE_LIBGFXINIT=y
 # CONFIG_VGA_ROM_RUN is not set
 # CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
 
 #
 # Display
@@ -349,16 +350,26 @@ CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
 CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
+# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
 # CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
 CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
-CONFIG_RESOURCE_ALLOCATOR_V4=y
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_NO_DDR5=y
+CONFIG_NO_LPDDR4=y
+CONFIG_NO_DDR4=y
+CONFIG_USE_DDR3=y
+CONFIG_USE_DDR2=y
 # end of Devices
 
 #
@@ -383,15 +394,18 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DRIVERS_UART=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 CONFIG_HAVE_USBDEBUG_OPTIONS=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
 CONFIG_DRIVERS_I2C_CK505=y
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
@@ -401,18 +415,24 @@ CONFIG_GFX_GMA_GENERATION="G45"
 CONFIG_GFX_GMA_PCH="No_PCH"
 CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
 CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
 # end of Generic Drivers
 
 #
 # Security
 #
 
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
 #
 # Verified Boot (vboot)
 #
@@ -451,27 +471,12 @@ CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_BOOTBLOCK_CONSOLE=y
 CONFIG_POSTCAR_CONSOLE=y
 CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_BAUD=115200
 # CONFIG_SPKMODEM is not set
 # CONFIG_CONSOLE_NE2K is not set
 CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
 # CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
@@ -482,6 +487,8 @@ CONFIG_CONSOLE_CBMEM=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
 # CONFIG_CMOS_POST is not set
 CONFIG_POST_DEVICE_NONE=y
 # CONFIG_POST_DEVICE_LPC is not set
@@ -508,28 +515,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # Payload
 #
 CONFIG_PAYLOAD_NONE=y
-# CONFIG_PAYLOAD_ELF is not set
-# CONFIG_PAYLOAD_BOOTBOOT is not set
-# CONFIG_PAYLOAD_FILO is not set
-# CONFIG_PAYLOAD_GRUB2 is not set
-# CONFIG_PAYLOAD_LINUXBOOT is not set
-# CONFIG_PAYLOAD_SEABIOS is not set
-# CONFIG_PAYLOAD_UBOOT is not set
-# CONFIG_PAYLOAD_YABITS is not set
-# CONFIG_PAYLOAD_LINUX is not set
-# CONFIG_PAYLOAD_TIANOCORE is not set
-CONFIG_PAYLOAD_OPTIONS=""
-# CONFIG_PXE is not set
-CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
-
-#
-# Secondary Payloads
-#
-# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
-# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
-# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
-# CONFIG_TINT_SECONDARY_PAYLOAD is not set
-# end of Secondary Payloads
 # end of Payload
 
 #
@@ -548,19 +533,16 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
 #
 # General Debug Settings
 #
-# CONFIG_GDB_STUB is not set
 # CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_SMI is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set
 # CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_HAVE_EM100_SUPPORT is not set
 # end of Debugging
 
 CONFIG_RAMSTAGE_ADA=y
@@ -568,6 +550,7 @@ CONFIG_RAMSTAGE_LIBHWBASE=y
 CONFIG_HWBASE_DYNAMIC_MMIO=y
 CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
 CONFIG_HWBASE_DIRECT_PCIDEV=y
+CONFIG_DECOMPRESS_OFAST=y
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

resources/coreboot/ga-g41m-es2l/board.cfg

@@ -1,6 +1,9 @@
 cbtree="default"
 romtype="normal"
 arch="x86_64"
-payload_grub="y"
-payload_grub_withseabios="y"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
+grub_scan_disk="ata"
+microcode_required="n"
+blobs_required="n"

resources/coreboot/ga-g41m-es2l/config/libgfxinit_txtmode

@@ -11,14 +11,17 @@ CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
+# CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
 CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_COMPRESS_RAMSTAGE_LZMA=y
+# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
 # CONFIG_TIMESTAMPS_ON_CONSOLE is not set
@@ -34,6 +37,12 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
 # CONFIG_FW_CONFIG is not set
+
+#
+# Software Bill Of Materials (SBOM)
+#
+# CONFIG_SBOM is not set
+# end of Software Bill Of Materials (SBOM)
 # end of General setup
 
 #
@@ -51,30 +60,25 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BAP is not set
 # CONFIG_VENDOR_BIOSTAR is not set
 # CONFIG_VENDOR_BOSTENTECH is not set
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
 # CONFIG_VENDOR_DELL is not set
-# CONFIG_VENDOR_ELMEX is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
 # CONFIG_VENDOR_GETAC is not set
 CONFIG_VENDOR_GIGABYTE=y
-# CONFIG_VENDOR_GIZMOSPHERE is not set
 # CONFIG_VENDOR_GOOGLE is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_JETWAY is not set
 # CONFIG_VENDOR_KONTRON is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_LIPPERT is not set
 # CONFIG_VENDOR_MSI is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
@@ -89,9 +93,9 @@ CONFIG_VENDOR_GIGABYTE=y
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
 # CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SCALEWAY is not set
 # CONFIG_VENDOR_SIEMENS is not set
 # CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
@@ -107,22 +111,21 @@ CONFIG_FMDFILE=""
 # CONFIG_NO_POST is not set
 CONFIG_MAINBOARD_VENDOR="GIGABYTE"
 CONFIG_CBFS_SIZE=0x00100000
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_MAX_CPUS=4
-# CONFIG_VBOOT is not set
+# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
+CONFIG_POST_DEVICE=y
+CONFIG_POST_IO=y
 CONFIG_DEVICETREE="devicetree.cb"
+# CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="GIGABYTE"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-CONFIG_UART_FOR_CONSOLE=0
 # CONFIG_CONSOLE_POST is not set
-CONFIG_POST_DEVICE=y
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
 CONFIG_DCACHE_RAM_BASE=0xfeff8000
 CONFIG_DCACHE_RAM_SIZE=0x8000
@@ -134,7 +137,7 @@ CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
 CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
 CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
+# CONFIG_DRIVERS_INTEL_WIFI is not set
 # CONFIG_BOARD_GIGABYTE_GA_945GCM_S2L is not set
 # CONFIG_BOARD_GIGABYTE_GA_945GCM_S2C is not set
 # CONFIG_BOARD_GIGABYTE_GA_B75M_D3H is not set
@@ -143,18 +146,23 @@ CONFIG_DRIVERS_INTEL_WIFI=y
 # CONFIG_BOARD_GIGABYTE_GA_D510UD is not set
 CONFIG_BOARD_GIGABYTE_GA_G41M_ES2L=y
 # CONFIG_BOARD_GIGABYTE_GA_H61M_S2PV is not set
+# CONFIG_BOARD_GIGABYTE_GA_H61M_DS2 is not set
 # CONFIG_BOARD_GIGABYTE_GA_H61M_DS2V is not set
 # CONFIG_BOARD_GIGABYTE_GA_H61MA_D3V is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CONSOLE_SERIAL=y
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="GA-G41M-ES2L"
+CONFIG_PCIEXP_HOTPLUG_BUSES=32
+CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
 CONFIG_PS2K_EISAID="PNP0303"
 CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
+# CONFIG_DEBUG_SMI is not set
 CONFIG_PCIEXP_L1_SUB_STATE=y
 CONFIG_PCIEXP_CLK_PM=y
-CONFIG_DRIVERS_UART_8250IO=y
+# CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_HEAP_SIZE=0x4000
+CONFIG_EC_GPE_SCI=0x50
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -186,32 +194,29 @@ CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
 #
 # SoC
 #
-CONFIG_ARCH_ALL_STAGES_X86=y
 CONFIG_CHIPSET_DEVICETREE=""
 CONFIG_CBFS_MCACHE_SIZE=0x4000
 CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_RAMBASE=0xe00000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d"
+CONFIG_ACPI_CPU_STRING="\\_SB.CP%02X"
 CONFIG_EHCI_BAR=0xfef00000
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_STACK_SIZE=0x1000
+CONFIG_STACK_SIZE=0x2000
 CONFIG_VBT_DATA_SIZE_KB=8
 CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
 CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_BOOTBLOCK_IN_CBFS=y
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_AZALIA_MAX_CODECS=3
 CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_TTYS0_BASE=0x3f8
-CONFIG_TTYS0_LCS=3
-CONFIG_UART_PCI_ADDR=0x0
+CONFIG_FIXED_SMBUS_IO_BASE=0x400
+CONFIG_HPET_MIN_TICKS=0x80
+CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
@@ -224,7 +229,6 @@ CONFIG_CPU_INTEL_MODEL_1067X=y
 CONFIG_CPU_INTEL_MODEL_F3X=y
 CONFIG_CPU_INTEL_MODEL_F4X=y
 CONFIG_SOCKET_SPECIFIC_OPTIONS=y
-CONFIG_SSE2=y
 CONFIG_CPU_INTEL_SOCKET_LGA775=y
 CONFIG_CPU_INTEL_COMMON=y
 CONFIG_ENABLE_VMX=y
@@ -237,6 +241,7 @@ CONFIG_PARALLEL_MP=y
 CONFIG_XAPIC_ONLY=y
 # CONFIG_X2APIC_ONLY is not set
 # CONFIG_X2APIC_RUNTIME is not set
+# CONFIG_X2APIC_LATE_WORKAROUND is not set
 CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
@@ -244,29 +249,28 @@ CONFIG_SETUP_XIP_CACHE=y
 CONFIG_LOGICAL_CPUS=y
 CONFIG_HAVE_SMI_HANDLER=y
 CONFIG_SMM_TSEG=y
-CONFIG_SMM_MODULE_HEAP_SIZE=0x4000
-CONFIG_SMM_STUB_STACK_SIZE=0x400
-CONFIG_CPU_INFO_V2=y
+CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
+CONFIG_AP_STACK_SIZE=0x800
 CONFIG_SMP=y
 CONFIG_MMX=y
 CONFIG_SSE=y
+CONFIG_SSE2=y
 CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-# CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS is not set
+CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
+CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
 # CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-CONFIG_CPU_MICROCODE_CBFS_NONE=y
+# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
 
 #
 # Northbridge
 #
-CONFIG_NORTHBRIDGE_SPECIFIC_OPTIONS=y
 CONFIG_NORTHBRIDGE_INTEL_X4X=y
 
 #
 # Southbridge
 #
-CONFIG_HPET_MIN_TICKS=0x80
-# CONFIG_PCIEXP_HOTPLUG is not set
+CONFIG_PCIEXP_HOTPLUG=y
 CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
@@ -284,10 +288,10 @@ CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
 CONFIG_INTEL_CHIPSET_LOCKDOWN=y
+CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
 CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
 CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
 CONFIG_RCBA_LENGTH=0x4000
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
 
 #
 # Super I/O
@@ -312,17 +316,16 @@ CONFIG_HAVE_EXP_X86_64_SUPPORT=y
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
 CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_RAMTOP=0x1000000
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_NUM_IPI_STARTS=2
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_HPET_ADDRESS=0xfed00000
 CONFIG_POSTCAR_STAGE=y
 CONFIG_BOOTBLOCK_SIMPLE=y
 # CONFIG_BOOTBLOCK_NORMAL is not set
 CONFIG_COLLECT_TIMESTAMPS_TSC=y
 CONFIG_HAVE_CF9_RESET=y
+CONFIG_DEBUG_HW_BREAKPOINTS=y
+CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # end of Chipset
 
 #
@@ -334,6 +337,7 @@ CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
 CONFIG_MAINBOARD_USE_LIBGFXINIT=y
 # CONFIG_VGA_ROM_RUN is not set
 # CONFIG_NO_GFX_INIT is not set
+CONFIG_NO_EARLY_GFX_INIT=y
 
 #
 # Display
@@ -352,13 +356,26 @@ CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
 CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
 CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
+# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
+# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
+CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
+# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
+CONFIG_PCIEXP_HOTPLUG_IO=0x2000
+CONFIG_FIRMWARE_CONNECTION_MANAGER=y
+# CONFIG_SOFTWARE_CONNECTION_MANAGER is not set
 # CONFIG_EARLY_PCI_BRIDGE is not set
 CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
 CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
 CONFIG_INTEL_GMA_HAVE_VBT=y
 CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
-CONFIG_RESOURCE_ALLOCATOR_V4=y
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
+CONFIG_NO_DDR5=y
+CONFIG_NO_LPDDR4=y
+CONFIG_NO_DDR4=y
+CONFIG_USE_DDR3=y
+CONFIG_USE_DDR2=y
 # end of Devices
 
 #
@@ -385,13 +402,16 @@ CONFIG_SPI_FLASH_MACRONIX=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_SPI_FLASH_SST=y
 CONFIG_SPI_FLASH_STMICRO=y
-CONFIG_DRIVERS_UART=y
 # CONFIG_DRIVERS_UART_OXPCIE is not set
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
+# CONFIG_DRIVERS_I2C_MAX98396 is not set
 CONFIG_INTEL_GMA_ACPI=y
 CONFIG_GFX_GMA=y
 CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
@@ -401,18 +421,24 @@ CONFIG_GFX_GMA_GENERATION="G45"
 CONFIG_GFX_GMA_PCH="No_PCH"
 CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
 CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
+# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
 # CONFIG_DRIVERS_PS2_KEYBOARD is not set
 CONFIG_DRIVERS_MC146818=y
 # CONFIG_USE_PC_CMOS_ALTCENTURY is not set
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
 # end of Generic Drivers
 
 #
 # Security
 #
 
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
 #
 # Verified Boot (vboot)
 #
@@ -452,27 +478,12 @@ CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
 CONFIG_BOOTBLOCK_CONSOLE=y
 CONFIG_POSTCAR_CONSOLE=y
 CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_BAUD=115200
 # CONFIG_SPKMODEM is not set
 # CONFIG_CONSOLE_NE2K is not set
 CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
 # CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_CONSOLE_I2C_SMBUS is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
@@ -483,6 +494,8 @@ CONFIG_CONSOLE_CBMEM=y
 # CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
 CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
 # CONFIG_CMOS_POST is not set
 CONFIG_POST_DEVICE_NONE=y
 # CONFIG_POST_DEVICE_LPC is not set
@@ -509,28 +522,6 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
 # Payload
 #
 CONFIG_PAYLOAD_NONE=y
-# CONFIG_PAYLOAD_ELF is not set
-# CONFIG_PAYLOAD_BOOTBOOT is not set
-# CONFIG_PAYLOAD_FILO is not set
-# CONFIG_PAYLOAD_GRUB2 is not set
-# CONFIG_PAYLOAD_LINUXBOOT is not set
-# CONFIG_PAYLOAD_SEABIOS is not set
-# CONFIG_PAYLOAD_UBOOT is not set
-# CONFIG_PAYLOAD_YABITS is not set
-# CONFIG_PAYLOAD_LINUX is not set
-# CONFIG_PAYLOAD_TIANOCORE is not set
-CONFIG_PAYLOAD_OPTIONS=""
-# CONFIG_PXE is not set
-CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
-
-#
-# Secondary Payloads
-#
-# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
-# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
-# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
-# CONFIG_TINT_SECONDARY_PAYLOAD is not set
-# end of Secondary Payloads
 # end of Payload
 
 #
@@ -549,19 +540,16 @@ CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
 #
 # General Debug Settings
 #
-# CONFIG_GDB_STUB is not set
 # CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
 CONFIG_HAVE_DEBUG_SMBUS=y
 # CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_SMI is not set
 # CONFIG_DEBUG_CONSOLE_INIT is not set
 # CONFIG_DEBUG_SPI_FLASH is not set
 # CONFIG_DEBUG_BOOT_STATE is not set
 # CONFIG_DEBUG_ADA_CODE is not set
-# CONFIG_HAVE_EM100_SUPPORT is not set
 # end of Debugging
 
 CONFIG_RAMSTAGE_ADA=y
@@ -569,6 +557,7 @@ CONFIG_RAMSTAGE_LIBHWBASE=y
 CONFIG_HWBASE_DYNAMIC_MMIO=y
 CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
 CONFIG_HWBASE_DIRECT_PCIDEV=y
+CONFIG_DECOMPRESS_OFAST=y
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

resources/coreboot/gru_bob/board.cfg

@@ -0,0 +1,6 @@
+cbtree="cros"
+romtype="normal"
+arch="AArch64"
+payload_uboot="y"
+blobs_required="n"
+microcode_required="n"

resources/coreboot/gru_bob/config/libgfxinit_corebootfb

@@ -0,0 +1,875 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_ALLOW_EXPERIMENTAL_CLANG is not set
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+CONFIG_OPTION_BACKEND_NONE=y
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_COMPRESS_PRERAM_STAGES=y
+CONFIG_COMPRESS_BOOTBLOCK=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+# CONFIG_COLLECT_TIMESTAMPS is not set
+# CONFIG_USE_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+# CONFIG_ASAN is not set
+CONFIG_NO_STAGE_CACHE=y
+# CONFIG_CBMEM_STAGE_CACHE is not set
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
+# end of General setup
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_51NB is not set
+# CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_BAP is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BOSTENTECH is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_CLEVO is not set
+# CONFIG_VENDOR_COMPULAB is not set
+# CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_ELMEX is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EXAMPLE is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+CONFIG_VENDOR_GOOGLE=y
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIBRETREND is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PINE64 is not set
+# CONFIG_VENDOR_PORTWELL is not set
+# CONFIG_VENDOR_PRODRIVE is not set
+# CONFIG_VENDOR_PROTECTLI is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RAZER is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SCALEWAY is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_SYSTEM76 is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_UP is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_PART_NUMBER="Bob"
+CONFIG_MAINBOARD_DIR="google/gru"
+CONFIG_DIMM_MAX=4
+CONFIG_DIMM_SPD_SIZE=256
+CONFIG_FMDFILE=""
+# CONFIG_NO_POST is not set
+CONFIG_MAINBOARD_VENDOR="Google"
+CONFIG_CBFS_SIZE=0x00800000
+CONFIG_CONSOLE_SERIAL=y
+CONFIG_MAX_CPUS=1
+CONFIG_POST_DEVICE=y
+CONFIG_UART_FOR_CONSOLE=0
+# CONFIG_VBOOT is not set
+# CONFIG_CHROMEOS is not set
+CONFIG_DEVICETREE="devicetree.cb"
+CONFIG_OVERRIDE_DEVICETREE=""
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=1
+CONFIG_CONSOLE_SERIAL_UART_ADDRESS=0xFF1A0000
+# CONFIG_CONSOLE_POST is not set
+CONFIG_MEMLAYOUT_LD_FILE="src/soc/rockchip/rk3399/memlayout.ld"
+CONFIG_SPI_FLASH_WINBOND=y
+
+#
+# Asurada
+#
+# CONFIG_BOARD_GOOGLE_ASURADA is not set
+# CONFIG_BOARD_GOOGLE_HAYATO is not set
+# CONFIG_BOARD_GOOGLE_SPHERION is not set
+
+#
+# Auron
+#
+# CONFIG_BOARD_GOOGLE_AURON_PAINE is not set
+# CONFIG_BOARD_GOOGLE_AURON_YUNA is not set
+# CONFIG_BOARD_GOOGLE_BUDDY is not set
+# CONFIG_BOARD_GOOGLE_GANDOF is not set
+# CONFIG_BOARD_GOOGLE_LULU is not set
+# CONFIG_BOARD_GOOGLE_SAMUS is not set
+
+#
+# Beltino
+#
+# CONFIG_BOARD_GOOGLE_MCCLOUD is not set
+# CONFIG_BOARD_GOOGLE_MONROE is not set
+# CONFIG_BOARD_GOOGLE_PANTHER is not set
+# CONFIG_BOARD_GOOGLE_TRICKY is not set
+# CONFIG_BOARD_GOOGLE_ZAKO is not set
+
+#
+# Brya
+#
+# CONFIG_BOARD_GOOGLE_AGAH is not set
+# CONFIG_BOARD_GOOGLE_ANAHERA is not set
+# CONFIG_BOARD_GOOGLE_ANAHERA4ES is not set
+# CONFIG_BOARD_GOOGLE_BRASK is not set
+# CONFIG_BOARD_GOOGLE_BRYA0 is not set
+# CONFIG_BOARD_GOOGLE_BRYA4ES is not set
+# CONFIG_BOARD_GOOGLE_FELWINTER is not set
+# CONFIG_BOARD_GOOGLE_GIMBLE is not set
+# CONFIG_BOARD_GOOGLE_GIMBLE4ES is not set
+# CONFIG_BOARD_GOOGLE_KANO is not set
+# CONFIG_BOARD_GOOGLE_NIVVIKS is not set
+# CONFIG_BOARD_GOOGLE_NEREID is not set
+# CONFIG_BOARD_GOOGLE_PRIMUS is not set
+# CONFIG_BOARD_GOOGLE_PRIMUS4ES is not set
+# CONFIG_BOARD_GOOGLE_REDRIX is not set
+# CONFIG_BOARD_GOOGLE_REDRIX4ES is not set
+# CONFIG_BOARD_GOOGLE_SKOLAS4ES is not set
+# CONFIG_BOARD_GOOGLE_TAEKO is not set
+# CONFIG_BOARD_GOOGLE_TAEKO4ES is not set
+# CONFIG_BOARD_GOOGLE_TANIKS is not set
+# CONFIG_BOARD_GOOGLE_VELL is not set
+# CONFIG_BOARD_GOOGLE_VOLMAR is not set
+# CONFIG_BOARD_GOOGLE_BANSHEE is not set
+# CONFIG_BOARD_GOOGLE_CROTA is not set
+# CONFIG_BOARD_GOOGLE_MOLI is not set
+# CONFIG_BOARD_GOOGLE_KINOX is not set
+# CONFIG_BOARD_GOOGLE_CRAASK is not set
+# CONFIG_BOARD_GOOGLE_OSIRIS is not set
+# CONFIG_BOARD_GOOGLE_MITHRAX is not set
+# CONFIG_BOARD_GOOGLE_KULDAX is not set
+
+#
+# Butterfly
+#
+# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set
+
+#
+# Cherry
+#
+# CONFIG_BOARD_GOOGLE_CHERRY is not set
+# CONFIG_BOARD_GOOGLE_DOJO is not set
+# CONFIG_BOARD_GOOGLE_TOMATO is not set
+
+#
+# Kingler
+#
+# CONFIG_BOARD_GOOGLE_KINGLER is not set
+# CONFIG_BOARD_GOOGLE_STEELIX is not set
+
+#
+# Krabby
+#
+# CONFIG_BOARD_GOOGLE_KRABBY is not set
+
+#
+# Cyan
+#
+# CONFIG_BOARD_GOOGLE_BANON is not set
+# CONFIG_BOARD_GOOGLE_CELES is not set
+# CONFIG_BOARD_GOOGLE_CYAN is not set
+# CONFIG_BOARD_GOOGLE_EDGAR is not set
+# CONFIG_BOARD_GOOGLE_KEFKA is not set
+# CONFIG_BOARD_GOOGLE_REKS is not set
+# CONFIG_BOARD_GOOGLE_RELM is not set
+# CONFIG_BOARD_GOOGLE_SETZER is not set
+# CONFIG_BOARD_GOOGLE_TERRA is not set
+# CONFIG_BOARD_GOOGLE_ULTIMA is not set
+# CONFIG_BOARD_GOOGLE_WIZPIG is not set
+
+#
+# Daisy
+#
+# CONFIG_BOARD_GOOGLE_DAISY is not set
+
+#
+# Dedede
+#
+# CONFIG_BOARD_GOOGLE_BOTEN is not set
+# CONFIG_BOARD_GOOGLE_DEDEDE is not set
+# CONFIG_BOARD_GOOGLE_DRAWCIA is not set
+# CONFIG_BOARD_GOOGLE_HABOKI is not set
+# CONFIG_BOARD_GOOGLE_MADOO is not set
+# CONFIG_BOARD_GOOGLE_WADDLEDOO is not set
+# CONFIG_BOARD_GOOGLE_WADDLEDEE is not set
+# CONFIG_BOARD_GOOGLE_LALALA is not set
+# CONFIG_BOARD_GOOGLE_MAGOLOR is not set
+# CONFIG_BOARD_GOOGLE_METAKNIGHT is not set
+# CONFIG_BOARD_GOOGLE_LANTIS is not set
+# CONFIG_BOARD_GOOGLE_GALTIC is not set
+# CONFIG_BOARD_GOOGLE_SASUKE is not set
+# CONFIG_BOARD_GOOGLE_STORO is not set
+# CONFIG_BOARD_GOOGLE_SASUKETTE is not set
+# CONFIG_BOARD_GOOGLE_KRACKO is not set
+# CONFIG_BOARD_GOOGLE_BLIPPER is not set
+# CONFIG_BOARD_GOOGLE_CRET is not set
+# CONFIG_BOARD_GOOGLE_PIRIKA is not set
+# CONFIG_BOARD_GOOGLE_CAPPY2 is not set
+# CONFIG_BOARD_GOOGLE_BUGZZY is not set
+# CONFIG_BOARD_GOOGLE_CORORI is not set
+# CONFIG_BOARD_GOOGLE_DRIBLEE is not set
+# CONFIG_BOARD_GOOGLE_GOOEY is not set
+# CONFIG_BOARD_GOOGLE_BEADRIX is not set
+
+#
+# Drallion
+#
+# CONFIG_BOARD_GOOGLE_DRALLION is not set
+
+#
+# Eve
+#
+# CONFIG_BOARD_GOOGLE_EVE is not set
+
+#
+# Fizz
+#
+# CONFIG_BOARD_GOOGLE_FIZZ is not set
+# CONFIG_BOARD_GOOGLE_KARMA is not set
+# CONFIG_BOARD_GOOGLE_ENDEAVOUR is not set
+
+#
+# Foster
+#
+# CONFIG_BOARD_GOOGLE_FOSTER is not set
+
+#
+# Gale
+#
+# CONFIG_BOARD_GOOGLE_GALE is not set
+
+#
+# Glados
+#
+# CONFIG_BOARD_GOOGLE_ASUKA is not set
+# CONFIG_BOARD_GOOGLE_CAROLINE is not set
+# CONFIG_BOARD_GOOGLE_CAVE is not set
+# CONFIG_BOARD_GOOGLE_CHELL is not set
+# CONFIG_BOARD_GOOGLE_GLADOS is not set
+# CONFIG_BOARD_GOOGLE_LARS is not set
+# CONFIG_BOARD_GOOGLE_SENTRY is not set
+
+#
+# Gru
+#
+# CONFIG_BOARD_GOOGLE_KEVIN is not set
+# CONFIG_BOARD_GOOGLE_GRU is not set
+CONFIG_BOARD_GOOGLE_BOB=y
+# CONFIG_BOARD_GOOGLE_SCARLET is not set
+# CONFIG_BOARD_GOOGLE_NEFARIO is not set
+# CONFIG_BOARD_GOOGLE_RAINIER is not set
+
+#
+# Guybrush
+#
+# CONFIG_BOARD_GOOGLE_GUYBRUSH is not set
+# CONFIG_BOARD_GOOGLE_NIPPERKIN is not set
+# CONFIG_BOARD_GOOGLE_DEWATT is not set
+
+#
+# Hatch
+#
+# CONFIG_BOARD_GOOGLE_AKEMI is not set
+# CONFIG_BOARD_GOOGLE_AMBASSADOR is not set
+# CONFIG_BOARD_GOOGLE_DOOLY is not set
+# CONFIG_BOARD_GOOGLE_DRATINI is not set
+# CONFIG_BOARD_GOOGLE_DUFFY_LEGACY is not set
+# CONFIG_BOARD_GOOGLE_DUFFY is not set
+# CONFIG_BOARD_GOOGLE_FAFFY is not set
+# CONFIG_BOARD_GOOGLE_GENESIS is not set
+# CONFIG_BOARD_GOOGLE_HATCH is not set
+# CONFIG_BOARD_GOOGLE_HELIOS is not set
+# CONFIG_BOARD_GOOGLE_HELIOS_DISKSWAP is not set
+# CONFIG_BOARD_GOOGLE_JINLON is not set
+# CONFIG_BOARD_GOOGLE_KAISA_LEGACY is not set
+# CONFIG_BOARD_GOOGLE_KAISA is not set
+# CONFIG_BOARD_GOOGLE_KINDRED is not set
+# CONFIG_BOARD_GOOGLE_KOHAKU is not set
+# CONFIG_BOARD_GOOGLE_MOONBUGGY is not set
+# CONFIG_BOARD_GOOGLE_MUSHU is not set
+# CONFIG_BOARD_GOOGLE_NIGHTFURY is not set
+# CONFIG_BOARD_GOOGLE_NOIBAT is not set
+# CONFIG_BOARD_GOOGLE_PALKIA is not set
+# CONFIG_BOARD_GOOGLE_PUFF is not set
+# CONFIG_BOARD_GOOGLE_SCOUT is not set
+# CONFIG_BOARD_GOOGLE_WYVERN is not set
+
+#
+# Herobrine
+#
+
+#
+# (Herobrine requires 'Allow QC blobs repository')
+#
+
+#
+# Jecht
+#
+# CONFIG_BOARD_GOOGLE_GUADO is not set
+# CONFIG_BOARD_GOOGLE_JECHT is not set
+# CONFIG_BOARD_GOOGLE_RIKKU is not set
+# CONFIG_BOARD_GOOGLE_TIDUS is not set
+
+#
+# Kahlee
+#
+# CONFIG_BOARD_GOOGLE_ALEENA is not set
+# CONFIG_BOARD_GOOGLE_CAREENA is not set
+# CONFIG_BOARD_GOOGLE_GRUNT is not set
+# CONFIG_BOARD_GOOGLE_LIARA is not set
+# CONFIG_BOARD_GOOGLE_NUWANI is not set
+# CONFIG_BOARD_GOOGLE_TREEYA is not set
+
+#
+# Kukui
+#
+# CONFIG_BOARD_GOOGLE_KUKUI is not set
+# CONFIG_BOARD_GOOGLE_KRANE is not set
+# CONFIG_BOARD_GOOGLE_KODAMA is not set
+# CONFIG_BOARD_GOOGLE_KAKADU is not set
+# CONFIG_BOARD_GOOGLE_FLAPJACK is not set
+# CONFIG_BOARD_GOOGLE_KATSU is not set
+
+#
+# Jacuzzi
+#
+# CONFIG_BOARD_GOOGLE_JACUZZI is not set
+# CONFIG_BOARD_GOOGLE_JUNIPER is not set
+# CONFIG_BOARD_GOOGLE_KAPPA is not set
+# CONFIG_BOARD_GOOGLE_DAMU is not set
+# CONFIG_BOARD_GOOGLE_CERISE is not set
+# CONFIG_BOARD_GOOGLE_STERN is not set
+# CONFIG_BOARD_GOOGLE_WILLOW is not set
+# CONFIG_BOARD_GOOGLE_ESCHE is not set
+# CONFIG_BOARD_GOOGLE_BURNET is not set
+# CONFIG_BOARD_GOOGLE_FENNEL is not set
+# CONFIG_BOARD_GOOGLE_COZMO is not set
+# CONFIG_BOARD_GOOGLE_MAKOMO is not set
+# CONFIG_BOARD_GOOGLE_MUNNA is not set
+# CONFIG_BOARD_GOOGLE_PICO is not set
+
+#
+# Link
+#
+# CONFIG_BOARD_GOOGLE_LINK is not set
+
+#
+# Mistral
+#
+# CONFIG_BOARD_GOOGLE_MISTRAL is not set
+
+#
+# Nyan
+#
+# CONFIG_BOARD_GOOGLE_NYAN is not set
+
+#
+# Nyan Big
+#
+# CONFIG_BOARD_GOOGLE_NYAN_BIG is not set
+
+#
+# Nyan Blaze
+#
+# CONFIG_BOARD_GOOGLE_NYAN_BLAZE is not set
+
+#
+# Oak
+#
+# CONFIG_BOARD_GOOGLE_OAK is not set
+# CONFIG_BOARD_GOOGLE_ELM is not set
+# CONFIG_BOARD_GOOGLE_HANA is not set
+
+#
+# Octopus
+#
+# CONFIG_BOARD_GOOGLE_AMPTON is not set
+# CONFIG_BOARD_GOOGLE_BLOOG is not set
+# CONFIG_BOARD_GOOGLE_BOBBA is not set
+# CONFIG_BOARD_GOOGLE_CASTA is not set
+# CONFIG_BOARD_GOOGLE_DOOD is not set
+# CONFIG_BOARD_GOOGLE_FLEEX is not set
+# CONFIG_BOARD_GOOGLE_FOOB is not set
+# CONFIG_BOARD_GOOGLE_GARG is not set
+# CONFIG_BOARD_GOOGLE_LICK is not set
+# CONFIG_BOARD_GOOGLE_MEEP is not set
+# CONFIG_BOARD_GOOGLE_OCTOPUS is not set
+# CONFIG_BOARD_GOOGLE_PHASER is not set
+# CONFIG_BOARD_GOOGLE_YORP is not set
+
+#
+# Parrot
+#
+# CONFIG_BOARD_GOOGLE_PARROT is not set
+
+#
+# Peach Pit
+#
+# CONFIG_BOARD_GOOGLE_PEACH_PIT is not set
+
+#
+# Poppy
+#
+# CONFIG_BOARD_GOOGLE_ATLAS is not set
+# CONFIG_BOARD_GOOGLE_POPPY is not set
+# CONFIG_BOARD_GOOGLE_NAMI is not set
+# CONFIG_BOARD_GOOGLE_NAUTILUS is not set
+# CONFIG_BOARD_GOOGLE_NOCTURNE is not set
+# CONFIG_BOARD_GOOGLE_RAMMUS is not set
+# CONFIG_BOARD_GOOGLE_SORAKA is not set
+
+#
+# Rambi
+#
+# CONFIG_BOARD_GOOGLE_BANJO is not set
+# CONFIG_BOARD_GOOGLE_CANDY is not set
+# CONFIG_BOARD_GOOGLE_CLAPPER is not set
+# CONFIG_BOARD_GOOGLE_ENGUARDE is not set
+# CONFIG_BOARD_GOOGLE_GLIMMER is not set
+# CONFIG_BOARD_GOOGLE_GNAWTY is not set
+# CONFIG_BOARD_GOOGLE_HELI is not set
+# CONFIG_BOARD_GOOGLE_KIP is not set
+# CONFIG_BOARD_GOOGLE_NINJA is not set
+# CONFIG_BOARD_GOOGLE_ORCO is not set
+# CONFIG_BOARD_GOOGLE_QUAWKS is not set
+# CONFIG_BOARD_GOOGLE_SQUAWKS is not set
+# CONFIG_BOARD_GOOGLE_RAMBI is not set
+# CONFIG_BOARD_GOOGLE_SUMO is not set
+# CONFIG_BOARD_GOOGLE_SWANKY is not set
+# CONFIG_BOARD_GOOGLE_WINKY is not set
+
+#
+# Reef
+#
+# CONFIG_BOARD_GOOGLE_REEF is not set
+# CONFIG_BOARD_GOOGLE_PYRO is not set
+# CONFIG_BOARD_GOOGLE_SAND is not set
+# CONFIG_BOARD_GOOGLE_SNAPPY is not set
+# CONFIG_BOARD_GOOGLE_CORAL is not set
+
+#
+# Sarien
+#
+# CONFIG_BOARD_GOOGLE_ARCADA is not set
+# CONFIG_BOARD_GOOGLE_SARIEN is not set
+
+#
+# Skyrim
+#
+# CONFIG_BOARD_GOOGLE_SKYRIM is not set
+
+#
+# Slippy
+#
+# CONFIG_BOARD_GOOGLE_FALCO is not set
+# CONFIG_BOARD_GOOGLE_LEON is not set
+# CONFIG_BOARD_GOOGLE_PEPPY is not set
+# CONFIG_BOARD_GOOGLE_WOLF is not set
+
+#
+# Smaug
+#
+# CONFIG_BOARD_GOOGLE_SMAUG is not set
+
+#
+# Storm
+#
+# CONFIG_BOARD_GOOGLE_STORM is not set
+
+#
+# Stout
+#
+# CONFIG_BOARD_GOOGLE_STOUT is not set
+
+#
+# Trogdor
+#
+
+#
+# (Trogdor requires 'Allow QC blobs repository')
+#
+
+#
+# Veyron
+#
+# CONFIG_BOARD_GOOGLE_VEYRON_JAQ is not set
+# CONFIG_BOARD_GOOGLE_VEYRON_JERRY is not set
+# CONFIG_BOARD_GOOGLE_VEYRON_MIGHTY is not set
+# CONFIG_BOARD_GOOGLE_VEYRON_MINNIE is not set
+# CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY is not set
+
+#
+# Veyron Mickey
+#
+# CONFIG_BOARD_GOOGLE_VEYRON_MICKEY is not set
+
+#
+# Veyron Rialto
+#
+# CONFIG_BOARD_GOOGLE_VEYRON_RIALTO is not set
+
+#
+# Volteer
+#
+# CONFIG_BOARD_GOOGLE_DELBIN is not set
+# CONFIG_BOARD_GOOGLE_ELDRID is not set
+# CONFIG_BOARD_GOOGLE_HALVOR is not set
+# CONFIG_BOARD_GOOGLE_LINDAR is not set
+# CONFIG_BOARD_GOOGLE_MALEFOR is not set
+# CONFIG_BOARD_GOOGLE_TERRADOR is not set
+# CONFIG_BOARD_GOOGLE_TODOR is not set
+# CONFIG_BOARD_GOOGLE_TRONDO is not set
+# CONFIG_BOARD_GOOGLE_VOLTEER is not set
+# CONFIG_BOARD_GOOGLE_VOLTEER2 is not set
+# CONFIG_BOARD_GOOGLE_VOLTEER2_TI50 is not set
+# CONFIG_BOARD_GOOGLE_VOXEL is not set
+# CONFIG_BOARD_GOOGLE_ELEMI is not set
+# CONFIG_BOARD_GOOGLE_VOEMA is not set
+# CONFIG_BOARD_GOOGLE_DROBIT is not set
+# CONFIG_BOARD_GOOGLE_COPANO is not set
+# CONFIG_BOARD_GOOGLE_COLLIS is not set
+# CONFIG_BOARD_GOOGLE_VOLET is not set
+# CONFIG_BOARD_GOOGLE_CHRONICLER is not set
+
+#
+# Zork
+#
+# CONFIG_BOARD_GOOGLE_DALBOZ is not set
+# CONFIG_BOARD_GOOGLE_VILBOZ is not set
+# CONFIG_BOARD_GOOGLE_EZKINIL is not set
+# CONFIG_BOARD_GOOGLE_MORPHIUS is not set
+# CONFIG_BOARD_GOOGLE_TREMBYLE is not set
+# CONFIG_BOARD_GOOGLE_BERKNIP is not set
+# CONFIG_BOARD_GOOGLE_WOOMAX is not set
+# CONFIG_BOARD_GOOGLE_DIRINBOZ is not set
+# CONFIG_BOARD_GOOGLE_SHUBOZ is not set
+# CONFIG_BOARD_GOOGLE_GUMBOZ is not set
+CONFIG_DRIVER_TPM_SPI_BUS=0x0
+CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x5
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_DRIVER_TPM_I2C_BUS=0x0
+CONFIG_DRIVER_TPM_I2C_ADDR=0x20
+CONFIG_PMIC_BUS=-1
+CONFIG_BOARD_GOOGLE_GRU_COMMON=y
+CONFIG_GRU_HAS_TPM2=y
+CONFIG_GRU_HAS_CENTERLOG_PWM=y
+CONFIG_GRU_HAS_WLAN_RESET=y
+CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME=""
+CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US=0
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
+CONFIG_HEAP_SIZE=0x100000
+CONFIG_DRIVER_TPM_SPI_CHIP=0
+CONFIG_EC_GPE_SCI=0x50
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=8192
+CONFIG_ROM_SIZE=0x00800000
+# end of Mainboard
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_CHIPSET_DEVICETREE=""
+CONFIG_CBFS_CACHE_ALIGN=8
+CONFIG_ARM64_BL31_EXTERNAL_FILE=""
+CONFIG_ARCH_ARMV8_EXTENSION=0
+CONFIG_STACK_SIZE=0x0
+CONFIG_VBT_DATA_SIZE_KB=8
+CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
+CONFIG_INTEL_GMA_BCLV_WIDTH=16
+CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
+CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_TTYS0_BASE=0x3f8
+CONFIG_TTYS0_LCS=3
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_GENERIC_UDELAY=y
+CONFIG_SOC_ROCKCHIP_RK3399=y
+CONFIG_RK3399_SPREAD_SPECTRUM_DDR=y
+
+#
+# CPU
+#
+
+#
+# Northbridge
+#
+
+#
+# Southbridge
+#
+CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
+CONFIG_RCBA_LENGTH=0x4000
+
+#
+# Super I/O
+#
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_SUPPORTS_DPTF_TEVT=y
+CONFIG_EC_GOOGLE_CHROMEEC=y
+CONFIG_EC_GOOGLE_CHROMEEC_SPI=y
+CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP=0x0
+CONFIG_EC_GOOGLE_CHROMEEC_RTC=y
+CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_NONE=y
+# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL is not set
+# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN is not set
+CONFIG_MAINBOARD_HAS_CHROMEOS=y
+
+#
+# ChromeOS
+#
+# end of ChromeOS
+
+CONFIG_ARCH_ARM64=y
+CONFIG_ARCH_BOOTBLOCK_ARM64=y
+CONFIG_ARCH_VERSTAGE_ARM64=y
+CONFIG_ARCH_ROMSTAGE_ARM64=y
+CONFIG_ARCH_RAMSTAGE_ARM64=y
+CONFIG_ARCH_BOOTBLOCK_ARMV8_64=y
+CONFIG_ARCH_VERSTAGE_ARMV8_64=y
+CONFIG_ARCH_ROMSTAGE_ARMV8_64=y
+CONFIG_ARCH_RAMSTAGE_ARMV8_64=y
+CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE=y
+# end of Chipset
+
+#
+# Devices
+#
+CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
+CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
+CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y
+CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
+
+#
+# Display
+#
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
+CONFIG_LINEAR_FRAMEBUFFER=y
+# CONFIG_BOOTSPLASH is not set
+# end of Display
+
+# CONFIG_SOFTWARE_I2C is not set
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+CONFIG_RESOURCE_ALLOCATOR_V4=y
+# end of Devices
+
+#
+# Generic Drivers
+#
+CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
+# CONFIG_ELOG is not set
+CONFIG_COMMON_CBFS_SPI_WRAPPER=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_TPM_INIT_RAMSTAGE=y
+CONFIG_DRIVERS_UART=y
+CONFIG_UART_OVERRIDE_REFCLK=y
+CONFIG_DRIVERS_UART_8250MEM=y
+CONFIG_DRIVERS_UART_8250MEM_32=y
+# CONFIG_VPD is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
+CONFIG_INTEL_GMA_OPREGION_2_0=y
+CONFIG_SPI_TPM=y
+# end of Generic Drivers
+
+#
+# Security
+#
+
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
+#
+# Verified Boot (vboot)
+#
+# end of Verified Boot (vboot)
+
+CONFIG_TPM_GOOGLE=y
+CONFIG_TPM_GOOGLE_CR50=y
+CONFIG_TPM_GOOGLE_IMMEDIATELY_COMMIT_FW_SECDATA=y
+
+#
+# Trusted Platform Module
+#
+# CONFIG_NO_TPM is not set
+CONFIG_TPM2=y
+CONFIG_TPM=y
+CONFIG_MAINBOARD_HAS_TPM2=y
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_TPM_MEASURED_BOOT is not set
+# end of Trusted Platform Module
+
+#
+# Memory initialization
+#
+# end of Memory initialization
+
+CONFIG_BOOTMEDIA_LOCK_NONE=y
+# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
+# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
+# end of Security
+
+CONFIG_ACPI_HAVE_PCAT_8259=y
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_RTC=y
+
+#
+# Console
+#
+CONFIG_BOOTBLOCK_CONSOLE=y
+
+#
+# memory mapped, 8250-compatible
+#
+# CONFIG_CONSOLE_SERIAL_921600 is not set
+# CONFIG_CONSOLE_SERIAL_460800 is not set
+# CONFIG_CONSOLE_SERIAL_230400 is not set
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+CONFIG_TTYS0_BAUD=115200
+CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
+CONFIG_POST_DEVICE_NONE=y
+CONFIG_HWBASE_DEBUG_CB=y
+# end of Console
+
+CONFIG_HAVE_MONOTONIC_TIMER=y
+
+#
+# System tables
+#
+# end of System tables
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_FIT is not set
+# CONFIG_PAYLOAD_BOOTBOOT is not set
+# CONFIG_PAYLOAD_LINUXBOOT is not set
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_PAYLOAD_OPTIONS=""
+CONFIG_PAYLOAD_FIT_SUPPORT=y
+CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
+
+#
+# Secondary Payloads
+#
+# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set
+# end of Secondary Payloads
+# end of Payload
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+
+#
+# BLOB Debug Settings
+#
+
+#
+# General Debug Settings
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+# end of Debugging
+
+CONFIG_FLATTENED_DEVICE_TREE=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_NO_XIP_EARLY_STAGES=y
+CONFIG_GENERIC_GPIO_LIB=y
+CONFIG_HAVE_BOOTBLOCK=y
+CONFIG_HAVE_ROMSTAGE=y
+CONFIG_HAVE_RAMSTAGE=y

resources/coreboot/gru_kevin/board.cfg

@@ -0,0 +1,6 @@
+cbtree="cros"
+romtype="normal"
+arch="AArch64"
+payload_uboot="y"
+blobs_required="n"
+microcode_required="n"

resources/coreboot/gru_kevin/config/libgfxinit_corebootfb

@@ -0,0 +1,874 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# coreboot configuration
+#
+
+#
+# General setup
+#
+CONFIG_COREBOOT_BUILD=y
+CONFIG_LOCALVERSION=""
+CONFIG_CBFS_PREFIX="fallback"
+CONFIG_COMPILER_GCC=y
+# CONFIG_ALLOW_EXPERIMENTAL_CLANG is not set
+# CONFIG_ANY_TOOLCHAIN is not set
+# CONFIG_CCACHE is not set
+# CONFIG_FMD_GENPARSER is not set
+# CONFIG_UTIL_GENPARSER is not set
+CONFIG_OPTION_BACKEND_NONE=y
+CONFIG_COMPRESS_RAMSTAGE=y
+CONFIG_COMPRESS_PRERAM_STAGES=y
+CONFIG_COMPRESS_BOOTBLOCK=y
+CONFIG_INCLUDE_CONFIG_FILE=y
+# CONFIG_COLLECT_TIMESTAMPS is not set
+# CONFIG_USE_BLOBS is not set
+# CONFIG_COVERAGE is not set
+# CONFIG_UBSAN is not set
+# CONFIG_ASAN is not set
+CONFIG_NO_STAGE_CACHE=y
+# CONFIG_CBMEM_STAGE_CACHE is not set
+# CONFIG_UPDATE_IMAGE is not set
+# CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
+# end of General setup
+
+#
+# Mainboard
+#
+
+#
+# Important: Run 'make distclean' before switching boards
+#
+# CONFIG_VENDOR_51NB is not set
+# CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
+# CONFIG_VENDOR_AMD is not set
+# CONFIG_VENDOR_AOPEN is not set
+# CONFIG_VENDOR_APPLE is not set
+# CONFIG_VENDOR_ASROCK is not set
+# CONFIG_VENDOR_ASUS is not set
+# CONFIG_VENDOR_BAP is not set
+# CONFIG_VENDOR_BIOSTAR is not set
+# CONFIG_VENDOR_BOSTENTECH is not set
+# CONFIG_VENDOR_CAVIUM is not set
+# CONFIG_VENDOR_CLEVO is not set
+# CONFIG_VENDOR_COMPULAB is not set
+# CONFIG_VENDOR_DELL is not set
+# CONFIG_VENDOR_ELMEX is not set
+# CONFIG_VENDOR_EMULATION is not set
+# CONFIG_VENDOR_EXAMPLE is not set
+# CONFIG_VENDOR_FACEBOOK is not set
+# CONFIG_VENDOR_FOXCONN is not set
+# CONFIG_VENDOR_GETAC is not set
+# CONFIG_VENDOR_GIGABYTE is not set
+# CONFIG_VENDOR_GIZMOSPHERE is not set
+CONFIG_VENDOR_GOOGLE=y
+# CONFIG_VENDOR_HP is not set
+# CONFIG_VENDOR_IBASE is not set
+# CONFIG_VENDOR_INTEL is not set
+# CONFIG_VENDOR_JETWAY is not set
+# CONFIG_VENDOR_KONTRON is not set
+# CONFIG_VENDOR_LENOVO is not set
+# CONFIG_VENDOR_LIBRETREND is not set
+# CONFIG_VENDOR_LIPPERT is not set
+# CONFIG_VENDOR_MSI is not set
+# CONFIG_VENDOR_OCP is not set
+# CONFIG_VENDOR_OPENCELLULAR is not set
+# CONFIG_VENDOR_PACKARDBELL is not set
+# CONFIG_VENDOR_PCENGINES is not set
+# CONFIG_VENDOR_PINE64 is not set
+# CONFIG_VENDOR_PORTWELL is not set
+# CONFIG_VENDOR_PRODRIVE is not set
+# CONFIG_VENDOR_PROTECTLI is not set
+# CONFIG_VENDOR_PURISM is not set
+# CONFIG_VENDOR_RAZER is not set
+# CONFIG_VENDOR_RODA is not set
+# CONFIG_VENDOR_SAMSUNG is not set
+# CONFIG_VENDOR_SAPPHIRE is not set
+# CONFIG_VENDOR_SCALEWAY is not set
+# CONFIG_VENDOR_SIEMENS is not set
+# CONFIG_VENDOR_SIFIVE is not set
+# CONFIG_VENDOR_STARLABS is not set
+# CONFIG_VENDOR_SUPERMICRO is not set
+# CONFIG_VENDOR_SYSTEM76 is not set
+# CONFIG_VENDOR_TI is not set
+# CONFIG_VENDOR_UP is not set
+CONFIG_BOARD_SPECIFIC_OPTIONS=y
+CONFIG_MAINBOARD_PART_NUMBER="Kevin"
+CONFIG_MAINBOARD_DIR="google/gru"
+CONFIG_DIMM_MAX=4
+CONFIG_DIMM_SPD_SIZE=256
+CONFIG_FMDFILE=""
+# CONFIG_NO_POST is not set
+CONFIG_MAINBOARD_VENDOR="Google"
+CONFIG_CBFS_SIZE=0x00800000
+CONFIG_CONSOLE_SERIAL=y
+CONFIG_MAX_CPUS=1
+CONFIG_POST_DEVICE=y
+CONFIG_UART_FOR_CONSOLE=0
+# CONFIG_VBOOT is not set
+# CONFIG_CHROMEOS is not set
+CONFIG_DEVICETREE="devicetree.cb"
+CONFIG_OVERRIDE_DEVICETREE=""
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=1
+CONFIG_CONSOLE_SERIAL_UART_ADDRESS=0xFF1A0000
+# CONFIG_CONSOLE_POST is not set
+CONFIG_MEMLAYOUT_LD_FILE="src/soc/rockchip/rk3399/memlayout.ld"
+CONFIG_SPI_FLASH_WINBOND=y
+
+#
+# Asurada
+#
+# CONFIG_BOARD_GOOGLE_ASURADA is not set
+# CONFIG_BOARD_GOOGLE_HAYATO is not set
+# CONFIG_BOARD_GOOGLE_SPHERION is not set
+
+#
+# Auron
+#
+# CONFIG_BOARD_GOOGLE_AURON_PAINE is not set
+# CONFIG_BOARD_GOOGLE_AURON_YUNA is not set
+# CONFIG_BOARD_GOOGLE_BUDDY is not set
+# CONFIG_BOARD_GOOGLE_GANDOF is not set
+# CONFIG_BOARD_GOOGLE_LULU is not set
+# CONFIG_BOARD_GOOGLE_SAMUS is not set
+
+#
+# Beltino
+#
+# CONFIG_BOARD_GOOGLE_MCCLOUD is not set
+# CONFIG_BOARD_GOOGLE_MONROE is not set
+# CONFIG_BOARD_GOOGLE_PANTHER is not set
+# CONFIG_BOARD_GOOGLE_TRICKY is not set
+# CONFIG_BOARD_GOOGLE_ZAKO is not set
+
+#
+# Brya
+#
+# CONFIG_BOARD_GOOGLE_AGAH is not set
+# CONFIG_BOARD_GOOGLE_ANAHERA is not set
+# CONFIG_BOARD_GOOGLE_ANAHERA4ES is not set
+# CONFIG_BOARD_GOOGLE_BRASK is not set
+# CONFIG_BOARD_GOOGLE_BRYA0 is not set
+# CONFIG_BOARD_GOOGLE_BRYA4ES is not set
+# CONFIG_BOARD_GOOGLE_FELWINTER is not set
+# CONFIG_BOARD_GOOGLE_GIMBLE is not set
+# CONFIG_BOARD_GOOGLE_GIMBLE4ES is not set
+# CONFIG_BOARD_GOOGLE_KANO is not set
+# CONFIG_BOARD_GOOGLE_NIVVIKS is not set
+# CONFIG_BOARD_GOOGLE_NEREID is not set
+# CONFIG_BOARD_GOOGLE_PRIMUS is not set
+# CONFIG_BOARD_GOOGLE_PRIMUS4ES is not set
+# CONFIG_BOARD_GOOGLE_REDRIX is not set
+# CONFIG_BOARD_GOOGLE_REDRIX4ES is not set
+# CONFIG_BOARD_GOOGLE_SKOLAS4ES is not set
+# CONFIG_BOARD_GOOGLE_TAEKO is not set
+# CONFIG_BOARD_GOOGLE_TAEKO4ES is not set
+# CONFIG_BOARD_GOOGLE_TANIKS is not set
+# CONFIG_BOARD_GOOGLE_VELL is not set
+# CONFIG_BOARD_GOOGLE_VOLMAR is not set
+# CONFIG_BOARD_GOOGLE_BANSHEE is not set
+# CONFIG_BOARD_GOOGLE_CROTA is not set
+# CONFIG_BOARD_GOOGLE_MOLI is not set
+# CONFIG_BOARD_GOOGLE_KINOX is not set
+# CONFIG_BOARD_GOOGLE_CRAASK is not set
+# CONFIG_BOARD_GOOGLE_OSIRIS is not set
+# CONFIG_BOARD_GOOGLE_MITHRAX is not set
+# CONFIG_BOARD_GOOGLE_KULDAX is not set
+
+#
+# Butterfly
+#
+# CONFIG_BOARD_GOOGLE_BUTTERFLY is not set
+
+#
+# Cherry
+#
+# CONFIG_BOARD_GOOGLE_CHERRY is not set
+# CONFIG_BOARD_GOOGLE_DOJO is not set
+# CONFIG_BOARD_GOOGLE_TOMATO is not set
+
+#
+# Kingler
+#
+# CONFIG_BOARD_GOOGLE_KINGLER is not set
+# CONFIG_BOARD_GOOGLE_STEELIX is not set
+
+#
+# Krabby
+#
+# CONFIG_BOARD_GOOGLE_KRABBY is not set
+
+#
+# Cyan
+#
+# CONFIG_BOARD_GOOGLE_BANON is not set
+# CONFIG_BOARD_GOOGLE_CELES is not set
+# CONFIG_BOARD_GOOGLE_CYAN is not set
+# CONFIG_BOARD_GOOGLE_EDGAR is not set
+# CONFIG_BOARD_GOOGLE_KEFKA is not set
+# CONFIG_BOARD_GOOGLE_REKS is not set
+# CONFIG_BOARD_GOOGLE_RELM is not set
+# CONFIG_BOARD_GOOGLE_SETZER is not set
+# CONFIG_BOARD_GOOGLE_TERRA is not set
+# CONFIG_BOARD_GOOGLE_ULTIMA is not set
+# CONFIG_BOARD_GOOGLE_WIZPIG is not set
+
+#
+# Daisy
+#
+# CONFIG_BOARD_GOOGLE_DAISY is not set
+
+#
+# Dedede
+#
+# CONFIG_BOARD_GOOGLE_BOTEN is not set
+# CONFIG_BOARD_GOOGLE_DEDEDE is not set
+# CONFIG_BOARD_GOOGLE_DRAWCIA is not set
+# CONFIG_BOARD_GOOGLE_HABOKI is not set
+# CONFIG_BOARD_GOOGLE_MADOO is not set
+# CONFIG_BOARD_GOOGLE_WADDLEDOO is not set
+# CONFIG_BOARD_GOOGLE_WADDLEDEE is not set
+# CONFIG_BOARD_GOOGLE_LALALA is not set
+# CONFIG_BOARD_GOOGLE_MAGOLOR is not set
+# CONFIG_BOARD_GOOGLE_METAKNIGHT is not set
+# CONFIG_BOARD_GOOGLE_LANTIS is not set
+# CONFIG_BOARD_GOOGLE_GALTIC is not set
+# CONFIG_BOARD_GOOGLE_SASUKE is not set
+# CONFIG_BOARD_GOOGLE_STORO is not set
+# CONFIG_BOARD_GOOGLE_SASUKETTE is not set
+# CONFIG_BOARD_GOOGLE_KRACKO is not set
+# CONFIG_BOARD_GOOGLE_BLIPPER is not set
+# CONFIG_BOARD_GOOGLE_CRET is not set
+# CONFIG_BOARD_GOOGLE_PIRIKA is not set
+# CONFIG_BOARD_GOOGLE_CAPPY2 is not set
+# CONFIG_BOARD_GOOGLE_BUGZZY is not set
+# CONFIG_BOARD_GOOGLE_CORORI is not set
+# CONFIG_BOARD_GOOGLE_DRIBLEE is not set
+# CONFIG_BOARD_GOOGLE_GOOEY is not set
+# CONFIG_BOARD_GOOGLE_BEADRIX is not set
+
+#
+# Drallion
+#
+# CONFIG_BOARD_GOOGLE_DRALLION is not set
+
+#
+# Eve
+#
+# CONFIG_BOARD_GOOGLE_EVE is not set
+
+#
+# Fizz
+#
+# CONFIG_BOARD_GOOGLE_FIZZ is not set
+# CONFIG_BOARD_GOOGLE_KARMA is not set
+# CONFIG_BOARD_GOOGLE_ENDEAVOUR is not set
+
+#
+# Foster
+#
+# CONFIG_BOARD_GOOGLE_FOSTER is not set
+
+#
+# Gale
+#
+# CONFIG_BOARD_GOOGLE_GALE is not set
+
+#
+# Glados
+#
+# CONFIG_BOARD_GOOGLE_ASUKA is not set
+# CONFIG_BOARD_GOOGLE_CAROLINE is not set
+# CONFIG_BOARD_GOOGLE_CAVE is not set
+# CONFIG_BOARD_GOOGLE_CHELL is not set
+# CONFIG_BOARD_GOOGLE_GLADOS is not set
+# CONFIG_BOARD_GOOGLE_LARS is not set
+# CONFIG_BOARD_GOOGLE_SENTRY is not set
+
+#
+# Gru
+#
+CONFIG_BOARD_GOOGLE_KEVIN=y
+# CONFIG_BOARD_GOOGLE_GRU is not set
+# CONFIG_BOARD_GOOGLE_BOB is not set
+# CONFIG_BOARD_GOOGLE_SCARLET is not set
+# CONFIG_BOARD_GOOGLE_NEFARIO is not set
+# CONFIG_BOARD_GOOGLE_RAINIER is not set
+
+#
+# Guybrush
+#
+# CONFIG_BOARD_GOOGLE_GUYBRUSH is not set
+# CONFIG_BOARD_GOOGLE_NIPPERKIN is not set
+# CONFIG_BOARD_GOOGLE_DEWATT is not set
+
+#
+# Hatch
+#
+# CONFIG_BOARD_GOOGLE_AKEMI is not set
+# CONFIG_BOARD_GOOGLE_AMBASSADOR is not set
+# CONFIG_BOARD_GOOGLE_DOOLY is not set
+# CONFIG_BOARD_GOOGLE_DRATINI is not set
+# CONFIG_BOARD_GOOGLE_DUFFY_LEGACY is not set
+# CONFIG_BOARD_GOOGLE_DUFFY is not set
+# CONFIG_BOARD_GOOGLE_FAFFY is not set
+# CONFIG_BOARD_GOOGLE_GENESIS is not set
+# CONFIG_BOARD_GOOGLE_HATCH is not set
+# CONFIG_BOARD_GOOGLE_HELIOS is not set
+# CONFIG_BOARD_GOOGLE_HELIOS_DISKSWAP is not set
+# CONFIG_BOARD_GOOGLE_JINLON is not set
+# CONFIG_BOARD_GOOGLE_KAISA_LEGACY is not set
+# CONFIG_BOARD_GOOGLE_KAISA is not set
+# CONFIG_BOARD_GOOGLE_KINDRED is not set
+# CONFIG_BOARD_GOOGLE_KOHAKU is not set
+# CONFIG_BOARD_GOOGLE_MOONBUGGY is not set
+# CONFIG_BOARD_GOOGLE_MUSHU is not set
+# CONFIG_BOARD_GOOGLE_NIGHTFURY is not set
+# CONFIG_BOARD_GOOGLE_NOIBAT is not set
+# CONFIG_BOARD_GOOGLE_PALKIA is not set
+# CONFIG_BOARD_GOOGLE_PUFF is not set
+# CONFIG_BOARD_GOOGLE_SCOUT is not set
+# CONFIG_BOARD_GOOGLE_WYVERN is not set
+
+#
+# Herobrine
+#
+
+#
+# (Herobrine requires 'Allow QC blobs repository')
+#
+
+#
+# Jecht
+#
+# CONFIG_BOARD_GOOGLE_GUADO is not set
+# CONFIG_BOARD_GOOGLE_JECHT is not set
+# CONFIG_BOARD_GOOGLE_RIKKU is not set
+# CONFIG_BOARD_GOOGLE_TIDUS is not set
+
+#
+# Kahlee
+#
+# CONFIG_BOARD_GOOGLE_ALEENA is not set
+# CONFIG_BOARD_GOOGLE_CAREENA is not set
+# CONFIG_BOARD_GOOGLE_GRUNT is not set
+# CONFIG_BOARD_GOOGLE_LIARA is not set
+# CONFIG_BOARD_GOOGLE_NUWANI is not set
+# CONFIG_BOARD_GOOGLE_TREEYA is not set
+
+#
+# Kukui
+#
+# CONFIG_BOARD_GOOGLE_KUKUI is not set
+# CONFIG_BOARD_GOOGLE_KRANE is not set
+# CONFIG_BOARD_GOOGLE_KODAMA is not set
+# CONFIG_BOARD_GOOGLE_KAKADU is not set
+# CONFIG_BOARD_GOOGLE_FLAPJACK is not set
+# CONFIG_BOARD_GOOGLE_KATSU is not set
+
+#
+# Jacuzzi
+#
+# CONFIG_BOARD_GOOGLE_JACUZZI is not set
+# CONFIG_BOARD_GOOGLE_JUNIPER is not set
+# CONFIG_BOARD_GOOGLE_KAPPA is not set
+# CONFIG_BOARD_GOOGLE_DAMU is not set
+# CONFIG_BOARD_GOOGLE_CERISE is not set
+# CONFIG_BOARD_GOOGLE_STERN is not set
+# CONFIG_BOARD_GOOGLE_WILLOW is not set
+# CONFIG_BOARD_GOOGLE_ESCHE is not set
+# CONFIG_BOARD_GOOGLE_BURNET is not set
+# CONFIG_BOARD_GOOGLE_FENNEL is not set
+# CONFIG_BOARD_GOOGLE_COZMO is not set
+# CONFIG_BOARD_GOOGLE_MAKOMO is not set
+# CONFIG_BOARD_GOOGLE_MUNNA is not set
+# CONFIG_BOARD_GOOGLE_PICO is not set
+
+#
+# Link
+#
+# CONFIG_BOARD_GOOGLE_LINK is not set
+
+#
+# Mistral
+#
+# CONFIG_BOARD_GOOGLE_MISTRAL is not set
+
+#
+# Nyan
+#
+# CONFIG_BOARD_GOOGLE_NYAN is not set
+
+#
+# Nyan Big
+#
+# CONFIG_BOARD_GOOGLE_NYAN_BIG is not set
+
+#
+# Nyan Blaze
+#
+# CONFIG_BOARD_GOOGLE_NYAN_BLAZE is not set
+
+#
+# Oak
+#
+# CONFIG_BOARD_GOOGLE_OAK is not set
+# CONFIG_BOARD_GOOGLE_ELM is not set
+# CONFIG_BOARD_GOOGLE_HANA is not set
+
+#
+# Octopus
+#
+# CONFIG_BOARD_GOOGLE_AMPTON is not set
+# CONFIG_BOARD_GOOGLE_BLOOG is not set
+# CONFIG_BOARD_GOOGLE_BOBBA is not set
+# CONFIG_BOARD_GOOGLE_CASTA is not set
+# CONFIG_BOARD_GOOGLE_DOOD is not set
+# CONFIG_BOARD_GOOGLE_FLEEX is not set
+# CONFIG_BOARD_GOOGLE_FOOB is not set
+# CONFIG_BOARD_GOOGLE_GARG is not set
+# CONFIG_BOARD_GOOGLE_LICK is not set
+# CONFIG_BOARD_GOOGLE_MEEP is not set
+# CONFIG_BOARD_GOOGLE_OCTOPUS is not set
+# CONFIG_BOARD_GOOGLE_PHASER is not set
+# CONFIG_BOARD_GOOGLE_YORP is not set
+
+#
+# Parrot
+#
+# CONFIG_BOARD_GOOGLE_PARROT is not set
+
+#
+# Peach Pit
+#
+# CONFIG_BOARD_GOOGLE_PEACH_PIT is not set
+
+#
+# Poppy
+#
+# CONFIG_BOARD_GOOGLE_ATLAS is not set
+# CONFIG_BOARD_GOOGLE_POPPY is not set
+# CONFIG_BOARD_GOOGLE_NAMI is not set
+# CONFIG_BOARD_GOOGLE_NAUTILUS is not set
+# CONFIG_BOARD_GOOGLE_NOCTURNE is not set
+# CONFIG_BOARD_GOOGLE_RAMMUS is not set
+# CONFIG_BOARD_GOOGLE_SORAKA is not set
+
+#
+# Rambi
+#
+# CONFIG_BOARD_GOOGLE_BANJO is not set
+# CONFIG_BOARD_GOOGLE_CANDY is not set
+# CONFIG_BOARD_GOOGLE_CLAPPER is not set
+# CONFIG_BOARD_GOOGLE_ENGUARDE is not set
+# CONFIG_BOARD_GOOGLE_GLIMMER is not set
+# CONFIG_BOARD_GOOGLE_GNAWTY is not set
+# CONFIG_BOARD_GOOGLE_HELI is not set
+# CONFIG_BOARD_GOOGLE_KIP is not set
+# CONFIG_BOARD_GOOGLE_NINJA is not set
+# CONFIG_BOARD_GOOGLE_ORCO is not set
+# CONFIG_BOARD_GOOGLE_QUAWKS is not set
+# CONFIG_BOARD_GOOGLE_SQUAWKS is not set
+# CONFIG_BOARD_GOOGLE_RAMBI is not set
+# CONFIG_BOARD_GOOGLE_SUMO is not set
+# CONFIG_BOARD_GOOGLE_SWANKY is not set
+# CONFIG_BOARD_GOOGLE_WINKY is not set
+
+#
+# Reef
+#
+# CONFIG_BOARD_GOOGLE_REEF is not set
+# CONFIG_BOARD_GOOGLE_PYRO is not set
+# CONFIG_BOARD_GOOGLE_SAND is not set
+# CONFIG_BOARD_GOOGLE_SNAPPY is not set
+# CONFIG_BOARD_GOOGLE_CORAL is not set
+
+#
+# Sarien
+#
+# CONFIG_BOARD_GOOGLE_ARCADA is not set
+# CONFIG_BOARD_GOOGLE_SARIEN is not set
+
+#
+# Skyrim
+#
+# CONFIG_BOARD_GOOGLE_SKYRIM is not set
+
+#
+# Slippy
+#
+# CONFIG_BOARD_GOOGLE_FALCO is not set
+# CONFIG_BOARD_GOOGLE_LEON is not set
+# CONFIG_BOARD_GOOGLE_PEPPY is not set
+# CONFIG_BOARD_GOOGLE_WOLF is not set
+
+#
+# Smaug
+#
+# CONFIG_BOARD_GOOGLE_SMAUG is not set
+
+#
+# Storm
+#
+# CONFIG_BOARD_GOOGLE_STORM is not set
+
+#
+# Stout
+#
+# CONFIG_BOARD_GOOGLE_STOUT is not set
+
+#
+# Trogdor
+#
+
+#
+# (Trogdor requires 'Allow QC blobs repository')
+#
+
+#
+# Veyron
+#
+# CONFIG_BOARD_GOOGLE_VEYRON_JAQ is not set
+# CONFIG_BOARD_GOOGLE_VEYRON_JERRY is not set
+# CONFIG_BOARD_GOOGLE_VEYRON_MIGHTY is not set
+# CONFIG_BOARD_GOOGLE_VEYRON_MINNIE is not set
+# CONFIG_BOARD_GOOGLE_VEYRON_SPEEDY is not set
+
+#
+# Veyron Mickey
+#
+# CONFIG_BOARD_GOOGLE_VEYRON_MICKEY is not set
+
+#
+# Veyron Rialto
+#
+# CONFIG_BOARD_GOOGLE_VEYRON_RIALTO is not set
+
+#
+# Volteer
+#
+# CONFIG_BOARD_GOOGLE_DELBIN is not set
+# CONFIG_BOARD_GOOGLE_ELDRID is not set
+# CONFIG_BOARD_GOOGLE_HALVOR is not set
+# CONFIG_BOARD_GOOGLE_LINDAR is not set
+# CONFIG_BOARD_GOOGLE_MALEFOR is not set
+# CONFIG_BOARD_GOOGLE_TERRADOR is not set
+# CONFIG_BOARD_GOOGLE_TODOR is not set
+# CONFIG_BOARD_GOOGLE_TRONDO is not set
+# CONFIG_BOARD_GOOGLE_VOLTEER is not set
+# CONFIG_BOARD_GOOGLE_VOLTEER2 is not set
+# CONFIG_BOARD_GOOGLE_VOLTEER2_TI50 is not set
+# CONFIG_BOARD_GOOGLE_VOXEL is not set
+# CONFIG_BOARD_GOOGLE_ELEMI is not set
+# CONFIG_BOARD_GOOGLE_VOEMA is not set
+# CONFIG_BOARD_GOOGLE_DROBIT is not set
+# CONFIG_BOARD_GOOGLE_COPANO is not set
+# CONFIG_BOARD_GOOGLE_COLLIS is not set
+# CONFIG_BOARD_GOOGLE_VOLET is not set
+# CONFIG_BOARD_GOOGLE_CHRONICLER is not set
+
+#
+# Zork
+#
+# CONFIG_BOARD_GOOGLE_DALBOZ is not set
+# CONFIG_BOARD_GOOGLE_VILBOZ is not set
+# CONFIG_BOARD_GOOGLE_EZKINIL is not set
+# CONFIG_BOARD_GOOGLE_MORPHIUS is not set
+# CONFIG_BOARD_GOOGLE_TREMBYLE is not set
+# CONFIG_BOARD_GOOGLE_BERKNIP is not set
+# CONFIG_BOARD_GOOGLE_WOOMAX is not set
+# CONFIG_BOARD_GOOGLE_DIRINBOZ is not set
+# CONFIG_BOARD_GOOGLE_SHUBOZ is not set
+# CONFIG_BOARD_GOOGLE_GUMBOZ is not set
+CONFIG_DRIVER_TPM_SPI_BUS=0x0
+CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS=0x5
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_DRIVER_TPM_I2C_BUS=0x0
+CONFIG_DRIVER_TPM_I2C_ADDR=0x20
+CONFIG_PMIC_BUS=-1
+CONFIG_BOARD_GOOGLE_GRU_COMMON=y
+# CONFIG_GRU_HAS_TPM2 is not set
+CONFIG_GRU_HAS_CENTERLOG_PWM=y
+CONFIG_GRU_HAS_WLAN_RESET=y
+CONFIG_EC_GOOGLE_CHROMEEC_BOARDNAME=""
+CONFIG_EC_GOOGLE_CHROMEEC_SPI_WAKEUP_DELAY_US=0
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
+CONFIG_HEAP_SIZE=0x100000
+CONFIG_EC_GPE_SCI=0x50
+CONFIG_BOARD_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
+CONFIG_COREBOOT_ROMSIZE_KB_8192=y
+# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
+# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
+CONFIG_COREBOOT_ROMSIZE_KB=8192
+CONFIG_ROM_SIZE=0x00800000
+# end of Mainboard
+
+#
+# Chipset
+#
+
+#
+# SoC
+#
+CONFIG_CHIPSET_DEVICETREE=""
+CONFIG_CBFS_CACHE_ALIGN=8
+CONFIG_ARM64_BL31_EXTERNAL_FILE=""
+CONFIG_ARCH_ARMV8_EXTENSION=0
+CONFIG_STACK_SIZE=0x0
+CONFIG_VBT_DATA_SIZE_KB=8
+CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
+CONFIG_INTEL_GMA_BCLV_WIDTH=16
+CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
+CONFIG_INTEL_GMA_BCLM_WIDTH=16
+CONFIG_TTYS0_BASE=0x3f8
+CONFIG_TTYS0_LCS=3
+CONFIG_UART_PCI_ADDR=0x0
+CONFIG_GENERIC_UDELAY=y
+CONFIG_SOC_ROCKCHIP_RK3399=y
+# CONFIG_RK3399_SPREAD_SPECTRUM_DDR is not set
+
+#
+# CPU
+#
+
+#
+# Northbridge
+#
+
+#
+# Southbridge
+#
+CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
+CONFIG_RCBA_LENGTH=0x4000
+
+#
+# Super I/O
+#
+
+#
+# Embedded Controllers
+#
+CONFIG_EC_SUPPORTS_DPTF_TEVT=y
+CONFIG_EC_GOOGLE_CHROMEEC=y
+CONFIG_EC_GOOGLE_CHROMEEC_SPI=y
+CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP=0x0
+CONFIG_EC_GOOGLE_CHROMEEC_RTC=y
+CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_NONE=y
+# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_EXTERNAL is not set
+# CONFIG_EC_GOOGLE_CHROMEEC_FIRMWARE_BUILTIN is not set
+CONFIG_MAINBOARD_HAS_CHROMEOS=y
+
+#
+# ChromeOS
+#
+# end of ChromeOS
+
+CONFIG_ARCH_ARM64=y
+CONFIG_ARCH_BOOTBLOCK_ARM64=y
+CONFIG_ARCH_VERSTAGE_ARM64=y
+CONFIG_ARCH_ROMSTAGE_ARM64=y
+CONFIG_ARCH_RAMSTAGE_ARM64=y
+CONFIG_ARCH_BOOTBLOCK_ARMV8_64=y
+CONFIG_ARCH_VERSTAGE_ARMV8_64=y
+CONFIG_ARCH_ROMSTAGE_ARMV8_64=y
+CONFIG_ARCH_RAMSTAGE_ARMV8_64=y
+CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE=y
+# end of Chipset
+
+#
+# Devices
+#
+CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
+CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
+CONFIG_MAINBOARD_FORCE_NATIVE_VGA_INIT=y
+CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
+
+#
+# Display
+#
+CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
+CONFIG_LINEAR_FRAMEBUFFER=y
+# CONFIG_BOOTSPLASH is not set
+# end of Display
+
+# CONFIG_SOFTWARE_I2C is not set
+CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
+CONFIG_RESOURCE_ALLOCATOR_V4=y
+# end of Devices
+
+#
+# Generic Drivers
+#
+CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
+# CONFIG_ELOG is not set
+CONFIG_COMMON_CBFS_SPI_WRAPPER=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
+# CONFIG_SPI_FLASH_NO_FAST_READ is not set
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_TPM_INIT_RAMSTAGE=y
+CONFIG_DRIVERS_UART=y
+CONFIG_UART_OVERRIDE_REFCLK=y
+CONFIG_DRIVERS_UART_8250MEM=y
+CONFIG_DRIVERS_UART_8250MEM_32=y
+# CONFIG_VPD is not set
+# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
+# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
+CONFIG_I2C_TPM=y
+CONFIG_DRIVER_TIS_DEFAULT=y
+# CONFIG_DRIVER_I2C_TPM_ACPI is not set
+# CONFIG_DRIVER_TPM_DISPLAY_TIS_BYTES is not set
+CONFIG_INTEL_GMA_OPREGION_2_0=y
+# end of Generic Drivers
+
+#
+# Security
+#
+
+#
+# CBFS verification
+#
+# CONFIG_CBFS_VERIFICATION is not set
+# end of CBFS verification
+
+#
+# Verified Boot (vboot)
+#
+# end of Verified Boot (vboot)
+
+#
+# Trusted Platform Module
+#
+# CONFIG_NO_TPM is not set
+CONFIG_TPM1=y
+CONFIG_TPM=y
+CONFIG_MAINBOARD_HAS_TPM1=y
+# CONFIG_TPM_DEACTIVATE is not set
+# CONFIG_DEBUG_TPM is not set
+# CONFIG_TPM_MEASURED_BOOT is not set
+# end of Trusted Platform Module
+
+#
+# Memory initialization
+#
+# end of Memory initialization
+
+CONFIG_BOOTMEDIA_LOCK_NONE=y
+# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
+# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
+# end of Security
+
+CONFIG_ACPI_HAVE_PCAT_8259=y
+CONFIG_BOOT_DEVICE_SPI_FLASH=y
+CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_RTC=y
+
+#
+# Console
+#
+CONFIG_BOOTBLOCK_CONSOLE=y
+
+#
+# memory mapped, 8250-compatible
+#
+# CONFIG_CONSOLE_SERIAL_921600 is not set
+# CONFIG_CONSOLE_SERIAL_460800 is not set
+# CONFIG_CONSOLE_SERIAL_230400 is not set
+CONFIG_CONSOLE_SERIAL_115200=y
+# CONFIG_CONSOLE_SERIAL_57600 is not set
+# CONFIG_CONSOLE_SERIAL_38400 is not set
+# CONFIG_CONSOLE_SERIAL_19200 is not set
+# CONFIG_CONSOLE_SERIAL_9600 is not set
+CONFIG_TTYS0_BAUD=115200
+CONFIG_CONSOLE_CBMEM=y
+# CONFIG_CONSOLE_SPI_FLASH is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
+# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
+CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
+CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
+CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
+CONFIG_POST_DEVICE_NONE=y
+CONFIG_HWBASE_DEBUG_CB=y
+# end of Console
+
+CONFIG_HAVE_MONOTONIC_TIMER=y
+
+#
+# System tables
+#
+# end of System tables
+
+#
+# Payload
+#
+CONFIG_PAYLOAD_NONE=y
+# CONFIG_PAYLOAD_ELF is not set
+# CONFIG_PAYLOAD_FIT is not set
+# CONFIG_PAYLOAD_BOOTBOOT is not set
+# CONFIG_PAYLOAD_LINUXBOOT is not set
+# CONFIG_PAYLOAD_TIANOCORE is not set
+CONFIG_PAYLOAD_OPTIONS=""
+CONFIG_PAYLOAD_FIT_SUPPORT=y
+CONFIG_COMPRESS_SECONDARY_PAYLOAD=y
+
+#
+# Secondary Payloads
+#
+# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set
+# end of Secondary Payloads
+# end of Payload
+
+#
+# Debugging
+#
+
+#
+# CPU Debug Settings
+#
+
+#
+# BLOB Debug Settings
+#
+
+#
+# General Debug Settings
+#
+# CONFIG_GDB_STUB is not set
+# CONFIG_FATAL_ASSERTS is not set
+# CONFIG_DEBUG_CBFS is not set
+# CONFIG_DEBUG_MALLOC is not set
+# CONFIG_DEBUG_CONSOLE_INIT is not set
+# CONFIG_DEBUG_SPI_FLASH is not set
+# CONFIG_DEBUG_BOOT_STATE is not set
+# CONFIG_DEBUG_ADA_CODE is not set
+# end of Debugging
+
+CONFIG_FLATTENED_DEVICE_TREE=y
+CONFIG_WARNINGS_ARE_ERRORS=y
+CONFIG_MAX_REBOOT_CNT=3
+CONFIG_NO_XIP_EARLY_STAGES=y
+CONFIG_GENERIC_GPIO_LIB=y
+CONFIG_HAVE_BOOTBLOCK=y
+CONFIG_HAVE_ROMSTAGE=y
+CONFIG_HAVE_RAMSTAGE=y

resources/coreboot/haswell/board.cfg

@@ -0,0 +1,4 @@
+cbtree="haswell"
+romtype="normal"
+cbrevision="1411ecf6f0b2c7395bcb96b856dcfdddb1b0c81b"
+arch="x86_64"

resources/coreboot/haswell/patches/0001-commonlib-clamp.h-Add-more-clamping-functions.patch

@@ -0,0 +1,54 @@
+From dd58f5e9108bc596c93071705d2b53233d13ade6 Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sat, 7 May 2022 20:36:10 +0200
+Subject: [PATCH 01/26] commonlib/clamp.h: Add more clamping functions
+
+Add more clamping functions that work with different types.
+
+Change-Id: I14cf335d5a54f769f8fd9184450957e876affd6b
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ src/commonlib/include/commonlib/clamp.h | 26 +++++++++++++++++--------
+ 1 file changed, 18 insertions(+), 8 deletions(-)
+
+diff --git a/src/commonlib/include/commonlib/clamp.h b/src/commonlib/include/commonlib/clamp.h
+index e01a107ed4..526185195c 100644
+--- a/src/commonlib/include/commonlib/clamp.h
++++ b/src/commonlib/include/commonlib/clamp.h
+@@ -8,15 +8,25 @@
+ /*
+  * Clamp a value, so that it is between a lower and an upper bound.
+  */
+-static inline u32 clamp_u32(const u32 min, const u32 val, const u32 max)
+-{
+-	if (val > max)
+-		return max;
++#define __MAKE_CLAMP_FUNC(type) \
++	static inline type clamp_##type(const type min, const type val, const type max) \
++	{				\
++		if (val > max)		\
++			return max;	\
++		if (val < min)		\
++			return min;	\
++		return val;		\
++	}				\
+ 
+-	if (val < min)
+-		return min;
++__MAKE_CLAMP_FUNC(s8)	/* clamp_s8  */
++__MAKE_CLAMP_FUNC(u8)	/* clamp_u8  */
++__MAKE_CLAMP_FUNC(s16)	/* clamp_s16 */
++__MAKE_CLAMP_FUNC(u16)	/* clamp_u16 */
++__MAKE_CLAMP_FUNC(s32)	/* clamp_s32 */
++__MAKE_CLAMP_FUNC(u32)	/* clamp_u32 */
++__MAKE_CLAMP_FUNC(s64)	/* clamp_s64 */
++__MAKE_CLAMP_FUNC(u64)	/* clamp_u64 */
+ 
+-	return val;
+-}
++#undef __MAKE_CLAMP_FUNC
+ 
+ #endif /* COMMONLIB_CLAMP_H */
+-- 
+2.39.2
+

resources/coreboot/haswell/patches/0002-nb-intel-haswell-Introduce-option-to-not-use-MRC.bin.patch

@@ -0,0 +1,143 @@
+From c07391821c32cafea950574b85468f5b3284b6df Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Fri, 6 May 2022 21:12:14 +0200
+Subject: [PATCH 02/26] nb/intel/haswell: Introduce option to not use MRC.bin
+
+Introduce the `USE_NATIVE_RAMINIT` Kconfig option, which should allow
+booting coreboot on Haswell mainboards without the need of the closed
+source MRC.bin. For now, this option does not work at all; the needed
+magic will be implemented in subsequent commits. Add a config file to
+make sure the newly-introduced option gets build-tested.
+
+Change-Id: I46c77586f9b5771624082e07c60c205e578edd8e
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ configs/config.asrock_b85m_pro4.native_raminit    |  5 +++++
+ src/northbridge/intel/haswell/Kconfig             | 13 +++++++++++++
+ src/northbridge/intel/haswell/Makefile.inc        |  7 ++++++-
+ .../intel/haswell/native_raminit/Makefile.inc     |  3 +++
+ .../intel/haswell/native_raminit/raminit_native.c | 15 +++++++++++++++
+ 5 files changed, 42 insertions(+), 1 deletion(-)
+ create mode 100644 configs/config.asrock_b85m_pro4.native_raminit
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/Makefile.inc
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/raminit_native.c
+
+diff --git a/configs/config.asrock_b85m_pro4.native_raminit b/configs/config.asrock_b85m_pro4.native_raminit
+new file mode 100644
+index 0000000000..2de538926f
+--- /dev/null
++++ b/configs/config.asrock_b85m_pro4.native_raminit
+@@ -0,0 +1,5 @@
++# Configuration used to build-test native raminit
++CONFIG_VENDOR_ASROCK=y
++CONFIG_BOARD_ASROCK_B85M_PRO4=y
++CONFIG_USE_NATIVE_RAMINIT=y
++CONFIG_DEBUG_RAM_SETUP=y
+diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
+index 50acb09a91..b659bf6d98 100644
+--- a/src/northbridge/intel/haswell/Kconfig
++++ b/src/northbridge/intel/haswell/Kconfig
+@@ -9,6 +9,14 @@ config NORTHBRIDGE_INTEL_HASWELL
+ 
+ if NORTHBRIDGE_INTEL_HASWELL
+ 
++config USE_NATIVE_RAMINIT
++	bool "[NOT WORKING] Use native raminit"
++	default n
++	select HAVE_DEBUG_RAM_SETUP
++	help
++	  Select if you want to use coreboot implementation of raminit rather than
++	  MRC.bin. Currently incomplete and does not boot.
++
+ config HASWELL_VBOOT_IN_BOOTBLOCK
+ 	depends on VBOOT
+ 	bool "Start verstage in bootblock"
+@@ -45,6 +53,7 @@ config DCACHE_RAM_BASE
+ 
+ config DCACHE_RAM_SIZE
+ 	hex
++	default 0x40000 if USE_NATIVE_RAMINIT
+ 	default 0x10000
+ 	help
+ 	  The size of the cache-as-ram region required during bootblock
+@@ -53,12 +62,14 @@ config DCACHE_RAM_SIZE
+ 
+ config DCACHE_RAM_MRC_VAR_SIZE
+ 	hex
++	default 0x0 if USE_NATIVE_RAMINIT
+ 	default 0x30000
+ 	help
+ 	  The amount of cache-as-ram region required by the reference code.
+ 
+ config DCACHE_BSP_STACK_SIZE
+ 	hex
++	default 0x20000 if USE_NATIVE_RAMINIT
+ 	default 0x2000
+ 	help
+ 	  The amount of anticipated stack usage in CAR by bootblock and
+@@ -66,6 +77,7 @@ config DCACHE_BSP_STACK_SIZE
+ 
+ config HAVE_MRC
+ 	bool "Add a System Agent binary"
++	depends on !USE_NATIVE_RAMINIT
+ 	help
+ 	  Select this option to add a System Agent binary to
+ 	  the resulting coreboot image.
+@@ -82,6 +94,7 @@ config MRC_FILE
+ 
+ config HASWELL_HIDE_PEG_FROM_MRC
+ 	bool "Hide PEG devices from MRC to work around hardcoded MRC behavior"
++	depends on !USE_NATIVE_RAMINIT
+ 	default y
+ 	help
+ 	  If set, hides all PEG devices from MRC. This allows the iGPU
+diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
+index 2d1532be05..329f1f7ffe 100644
+--- a/src/northbridge/intel/haswell/Makefile.inc
++++ b/src/northbridge/intel/haswell/Makefile.inc
+@@ -19,6 +19,11 @@ romstage-y += report_platform.c
+ 
+ postcar-y += memmap.c
+ 
+-subdirs-y += haswell_mrc
++ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
++subdirs-y  += native_raminit
++
++else
++subdirs-y  += haswell_mrc
++endif
+ 
+ endif
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.inc b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+new file mode 100644
+index 0000000000..8cfb4fb33e
+--- /dev/null
++++ b/src/northbridge/intel/haswell/native_raminit/Makefile.inc
+@@ -0,0 +1,3 @@
++## SPDX-License-Identifier: GPL-2.0-or-later
++
++romstage-y += raminit_native.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+new file mode 100644
+index 0000000000..1aafdf8659
+--- /dev/null
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <console/console.h>
++#include <northbridge/intel/haswell/raminit.h>
++
++void perform_raminit(const int s3resume)
++{
++	/*
++	 * See, this function's name is a lie. There are more things to
++	 * do that memory initialisation, but they are relatively easy.
++	 */
++
++	/** TODO: Implement the required magic **/
++	die("NATIVE RAMINIT: More Magic (tm) required.\n");
++}
+-- 
+2.39.2
+

resources/coreboot/haswell/patches/0003-haswell-lynxpoint-Add-native-DMI-init.patch

@@ -0,0 +1,615 @@
+From 6ec71c6df97eded010e96c4ea2bd37cc6a13849d Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Fri, 6 May 2022 21:56:48 +0200
+Subject: [PATCH 03/26] haswell/lynxpoint: Add native DMI init
+
+Implement native DMI init for Haswell and Lynx Point. This is only
+needed on non-ULT platforms, and only when MRC.bin is not used.
+
+TEST=Verify DMI initialises correctly on Asrock B85M Pro4.
+
+Change-Id: I5fb1a2adc4ffbf0ebbf0d2d3a444055c53765faa
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ src/northbridge/intel/haswell/Makefile.inc    |   1 +
+ src/northbridge/intel/haswell/early_dmi.c     |  96 ++++++++++++
+ src/northbridge/intel/haswell/early_pcie.c    | 121 ++++++++++++++
+ src/northbridge/intel/haswell/haswell.h       |   3 +
+ .../haswell/native_raminit/raminit_native.c   |  15 ++
+ src/northbridge/intel/haswell/vcu_mailbox.c   | 147 ++++++++++++++++++
+ src/northbridge/intel/haswell/vcu_mailbox.h   |  16 ++
+ src/southbridge/intel/lynxpoint/Makefile.inc  |   2 +
+ .../intel/lynxpoint/early_pch_native.c        |  52 +++++++
+ src/southbridge/intel/lynxpoint/pch.h         |  20 ++-
+ 10 files changed, 472 insertions(+), 1 deletion(-)
+ create mode 100644 src/northbridge/intel/haswell/early_dmi.c
+ create mode 100644 src/northbridge/intel/haswell/early_pcie.c
+ create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.c
+ create mode 100644 src/northbridge/intel/haswell/vcu_mailbox.h
+ create mode 100644 src/southbridge/intel/lynxpoint/early_pch_native.c
+
+diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc
+index 329f1f7ffe..df0b097296 100644
+--- a/src/northbridge/intel/haswell/Makefile.inc
++++ b/src/northbridge/intel/haswell/Makefile.inc
+@@ -20,6 +20,7 @@ romstage-y += report_platform.c
+ postcar-y += memmap.c
+ 
+ ifeq ($(CONFIG_USE_NATIVE_RAMINIT),y)
++romstage-y += early_dmi.c early_pcie.c vcu_mailbox.c
+ subdirs-y  += native_raminit
+ 
+ else
+diff --git a/src/northbridge/intel/haswell/early_dmi.c b/src/northbridge/intel/haswell/early_dmi.c
+new file mode 100644
+index 0000000000..9941242fd5
+--- /dev/null
++++ b/src/northbridge/intel/haswell/early_dmi.c
+@@ -0,0 +1,96 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <console/console.h>
++#include <northbridge/intel/haswell/haswell.h>
++#include <southbridge/intel/lynxpoint/pch.h>
++#include <types.h>
++
++static void dmi_print_link_status(int loglevel)
++{
++	const uint16_t dmilsts = dmibar_read16(DMILSTS);
++	printk(loglevel, "DMI: Running at Gen%u x%u\n", dmilsts & 0xf, dmilsts >> 4 & 0x1f);
++}
++
++#define RETRAIN	(1 << 5)
++
++#define LTRN	(1 << 11)
++
++static void dmi_setup_physical_layer(void)
++{
++	/* Program DMI AFE settings, which are needed for DMI to work */
++	peg_dmi_recipe(false, 0);
++
++	/* Additional DMI programming steps */
++	dmibar_setbits32(0x258, 1 << 29);
++	dmibar_clrsetbits32(0x208, 0x7ff, 0x6b5);
++	dmibar_clrsetbits32(0x22c, 0xffff, 0x2020);
++
++	/* Write SA reference code version */
++	dmibar_write32(0x71c, 0x0000000f);
++	dmibar_write32(0x720, 0x01060200);
++
++	/* We also have to bring up the PCH side of the DMI link */
++	pch_dmi_setup_physical_layer();
++
++	/* Write-once settings */
++	dmibar_clrsetbits32(DMILCAP, 0x3f00f, 2 << 0);
++
++	printk(BIOS_DEBUG, "Retraining DMI at Gen2 speeds...\n");
++	dmi_print_link_status(BIOS_DEBUG);
++
++	/* Retrain link */
++	dmibar_setbits16(DMILCTL, RETRAIN);
++	do {} while (dmibar_read16(DMILSTS) & LTRN);
++	dmi_print_link_status(BIOS_DEBUG);
++
++	/* Retrain link again for DMI Gen2 speeds */
++	dmibar_setbits16(DMILCTL, RETRAIN);
++	do {} while (dmibar_read16(DMILSTS) & LTRN);
++	dmi_print_link_status(BIOS_INFO);
++}
++
++#define VC_ACTIVE	(1U << 31)
++
++#define VCNEGPND	(1 << 1)
++
++#define DMI_VC_CFG(vcid, tcmap)	(VC_ACTIVE | ((vcid) << 24) | (tcmap))
++
++static void dmi_tc_vc_mapping(void)
++{
++	printk(BIOS_DEBUG, "Programming SA  DMI VC/TC mappings...\n");
++
++	if (CONFIG(INTEL_LYNXPOINT_LP))
++		dmibar_setbits8(0xa78, 1 << 1);
++
++	/* Each TC is mapped to one and only one VC */
++	const u32 vc0 = DMI_VC_CFG(0, (1 << 6) | (1 << 5) | (1 << 4) | (1 << 3) | (1 << 0));
++	const u32 vc1 = DMI_VC_CFG(1, (1 << 1));
++	const u32 vcp = DMI_VC_CFG(2, (1 << 2));
++	const u32 vcm = DMI_VC_CFG(7, (1 << 7));
++	dmibar_write32(DMIVC0RCTL, vc0);
++	dmibar_write32(DMIVC1RCTL, vc1);
++	dmibar_write32(DMIVCPRCTL, vcp);
++	dmibar_write32(DMIVCMRCTL, vcm);
++
++	/* Set Extended VC Count (EVCC) to 1 if VC1 is active */
++	dmibar_clrsetbits8(DMIPVCCAP1, 7, !!(vc1 & VC_ACTIVE));
++
++	/*
++	 * We also have to program the PCH side of the DMI link. Since both ends
++	 * must use the same Virtual Channel settings, we pass them as arguments.
++	 */
++	pch_dmi_tc_vc_mapping(vc0, vc1, vcp, vcm);
++
++	printk(BIOS_DEBUG, "Waiting for SA  DMI VC negotiation... ");
++	do {} while (dmibar_read16(DMIVC0RSTS) & VCNEGPND);
++	do {} while (dmibar_read16(DMIVC1RSTS) & VCNEGPND);
++	do {} while (dmibar_read16(DMIVCPRSTS) & VCNEGPND);
++	do {} while (dmibar_read16(DMIVCMRSTS) & VCNEGPND);
++	printk(BIOS_DEBUG, "done!\n");
++}
++
++void dmi_early_init(void)
++{
++	dmi_setup_physical_layer();
++	dmi_tc_vc_mapping();
++}
+diff --git a/src/northbridge/intel/haswell/early_pcie.c b/src/northbridge/intel/haswell/early_pcie.c
+new file mode 100644
+index 0000000000..d3940e3fac
+--- /dev/null
++++ b/src/northbridge/intel/haswell/early_pcie.c
+@@ -0,0 +1,121 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <console/console.h>
++#include <device/pci_def.h>
++#include <device/pci_mmio_cfg.h>
++#include <device/pci_ops.h>
++#include <northbridge/intel/haswell/haswell.h>
++#include <northbridge/intel/haswell/vcu_mailbox.h>
++#include <types.h>
++
++#define PEG_DEV(func)		PCI_DEV(0, 1, func)
++
++#define MAX_PEG_FUNC		3
++
++static void peg_dmi_unset_and_set_mask_pcicfg(
++	volatile union pci_bank *const bank,
++	const uint32_t offset,
++	const uint32_t unset_mask,
++	const uint32_t set_mask,
++	const uint32_t shift,
++	const bool valid)
++{
++	if (!valid)
++		return;
++
++	volatile uint32_t *const addr = &bank->reg32[offset / sizeof(uint32_t)];
++	clrsetbits32(addr, unset_mask << shift, set_mask << shift);
++}
++
++static void peg_dmi_unset_and_set_mask_common(
++	const bool is_peg,
++	const uint32_t offset,
++	const uint32_t unset,
++	const uint32_t set,
++	const uint32_t shift,
++	const bool valid)
++{
++	const uint32_t unset_mask = unset << shift;
++	const uint32_t   set_mask =   set << shift;
++	if (is_peg) {
++		for (uint8_t i = 0; i < MAX_PEG_FUNC; i++)
++			pci_update_config32(PEG_DEV(i), offset, ~unset_mask, set_mask);
++	} else {
++		dmibar_clrsetbits32(offset, unset_mask, set_mask);
++	}
++}
++
++static void peg_dmi_unset_and_set_mask_vcu_mmio(
++	const uint32_t addr,
++	const uint32_t unset_mask,
++	const uint32_t set_mask,
++	const uint32_t shift,
++	const bool valid)
++{
++	if (!valid)
++		return;
++
++	vcu_update_mmio(addr, ~(unset_mask << shift), set_mask << shift);
++}
++
++#define BUNDLE_STEP	0x20
++
++static void *const dmibar = (void *)(uintptr_t)CONFIG_FIXED_DMIBAR_MMIO_BASE;
++
++void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev)
++{
++	const bool always = true;
++	const bool is_dmi = !is_peg;
++
++	/* Treat DMIBAR and PEG devices the same way */
++	volatile union pci_bank *const bank = is_peg ? pci_map_bus(dev) : dmibar;
++
++	const size_t bundles = (is_peg ? 8 : 2) * BUNDLE_STEP;
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP) {
++		/* These are actually per-lane */
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa00 + i, 0x1f, 0x0c,  0, always);
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0xa10 + i, 0x1f, 0x0c,  0, always);
++	}
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x02,  0, is_peg);
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x1f, 0x03,  5, is_peg);
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x3f, 0x09,  5, always);
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x0f, 0x05, 21, is_peg);
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x08,  6, is_peg);
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x0f, 0x00, 10, always);
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x910 + i, 0x07, 0x00, 18, always);
++
++	peg_dmi_unset_and_set_mask_vcu_mmio(0x0c008001, 0x1f, 0x03, 25, is_peg);
++	peg_dmi_unset_and_set_mask_vcu_mmio(0x0c0c8001, 0x3f, 0x00, 23, is_dmi);
++
++	peg_dmi_unset_and_set_mask_pcicfg(bank, 0xc28, 0x1f, 0x13, 18, always);
++
++	peg_dmi_unset_and_set_mask_common(is_peg, 0xc38, 0x01, 0x00,  6, always);
++	peg_dmi_unset_and_set_mask_common(is_peg, 0x260, 0x03, 0x02,  0, always);
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x900 + i, 0x03, 0x00, 26, always);
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x904 + i, 0x03, 0x03, 10, always);
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x90c + i, 0x1f, 0x07, 25, is_peg);
++
++	for (size_t i = 0; i < bundles; i += BUNDLE_STEP)
++		peg_dmi_unset_and_set_mask_pcicfg(bank, 0x91c + i, 0x07, 0x05, 27, is_peg);
++}
+diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
+index 1b29f6baf0..30b4abd0a7 100644
+--- a/src/northbridge/intel/haswell/haswell.h
++++ b/src/northbridge/intel/haswell/haswell.h
+@@ -34,6 +34,9 @@ void haswell_early_initialization(void);
+ void haswell_late_initialization(void);
+ void haswell_unhide_peg(void);
+ 
++void dmi_early_init(void);
++void peg_dmi_recipe(const bool is_peg, const pci_devfn_t dev);
++
+ void report_platform_info(void);
+ 
+ struct acpi_rsdp;
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+index 1aafdf8659..0938e026e3 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+@@ -1,7 +1,19 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+ #include <console/console.h>
++#include <northbridge/intel/haswell/haswell.h>
+ #include <northbridge/intel/haswell/raminit.h>
++#include <types.h>
++
++static bool early_init_native(int s3resume)
++{
++	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
++
++	if (!CONFIG(INTEL_LYNXPOINT_LP))
++		dmi_early_init();
++
++	return false;
++}
+ 
+ void perform_raminit(const int s3resume)
+ {
+@@ -9,6 +21,9 @@ void perform_raminit(const int s3resume)
+ 	 * See, this function's name is a lie. There are more things to
+ 	 * do that memory initialisation, but they are relatively easy.
+ 	 */
++	const bool cpu_replaced = early_init_native(s3resume);
++
++	(void)cpu_replaced;
+ 
+ 	/** TODO: Implement the required magic **/
+ 	die("NATIVE RAMINIT: More Magic (tm) required.\n");
+diff --git a/src/northbridge/intel/haswell/vcu_mailbox.c b/src/northbridge/intel/haswell/vcu_mailbox.c
+new file mode 100644
+index 0000000000..aead144023
+--- /dev/null
++++ b/src/northbridge/intel/haswell/vcu_mailbox.c
+@@ -0,0 +1,147 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <assert.h>
++#include <console/console.h>
++#include <delay.h>
++#include <northbridge/intel/haswell/haswell.h>
++#include <northbridge/intel/haswell/vcu_mailbox.h>
++#include <stdint.h>
++
++/*
++ * This is a library for the VCU (Validation Control Unit) mailbox. This
++ * mailbox is primarily used to adjust some magic PCIe tuning parameters.
++ *
++ * There are two revisions of the VCU mailbox. Rev1 is specific to Haswell
++ * stepping A0, and all other steppings use Rev2. Haswell stepping A0 CPUs
++ * are early Engineering Samples with undocumented errata, and most likely
++ * need special microcode updates to boot. Thus, the code does not support
++ * VCU mailbox Rev1, because no one should need it anymore.
++ */
++
++#define VCU_MAILBOX_INTERFACE	0x6c00
++#define VCU_MAILBOX_DATA	0x6c04
++
++#define VCU_RUN_BUSY		(1 << 31)
++
++enum vcu_opcode {
++	VCU_OPCODE_READ_VCU_API_VER_ID	= 0x01,
++	VCU_OPCODE_OPEN_SEQ		= 0x02,
++	VCU_OPCODE_CLOSE_SEQ		= 0x03,
++	VCU_OPCODE_READ_DATA		= 0x07,
++	VCU_OPCODE_WRITE_DATA		= 0x08,
++	VCU_OPCODE_READ_CSR		= 0x13,
++	VCU_OPCODE_WRITE_CSR		= 0x14,
++	VCU_OPCODE_READ_MMIO		= 0x15,
++	VCU_OPCODE_WRITE_MMIO		= 0x16,
++};
++
++enum vcu_sequence {
++	SEQ_ID_READ_CSR		= 0x1,
++	SEQ_ID_WRITE_CSR	= 0x2,
++	SEQ_ID_READ_MMIO	= 0x3,
++	SEQ_ID_WRITE_MMIO	= 0x4,
++};
++
++#define VCU_RESPONSE_MASK		0xffff
++#define VCU_RESPONSE_SUCCESS		0x40
++#define VCU_RESPONSE_BUSY		0x80
++#define VCU_RESPONSE_THREAD_UNAVAILABLE	0x82
++#define VCU_RESPONSE_ILLEGAL		0x90
++
++/* FIXME: Use timer API */
++static void send_vcu_command(const enum vcu_opcode opcode, const uint32_t data)
++{
++	for (unsigned int i = 0; i < 10; i++) {
++		mchbar_write32(VCU_MAILBOX_DATA, data);
++		mchbar_write32(VCU_MAILBOX_INTERFACE, opcode | VCU_RUN_BUSY);
++		uint32_t vcu_interface;
++		for (unsigned int j = 0; j < 100; j++) {
++			vcu_interface = mchbar_read32(VCU_MAILBOX_INTERFACE);
++			if (!(vcu_interface & VCU_RUN_BUSY))
++				break;
++
++			udelay(10);
++		}
++		if (vcu_interface & VCU_RUN_BUSY)
++			continue;
++
++		if ((vcu_interface & VCU_RESPONSE_MASK) == VCU_RESPONSE_SUCCESS)
++			return;
++	}
++	printk(BIOS_ERR, "VCU: Failed to send command\n");
++}
++
++static enum vcu_opcode get_register_opcode(enum vcu_sequence seq)
++{
++	switch (seq) {
++	case SEQ_ID_READ_CSR:
++		return VCU_OPCODE_READ_CSR;
++	case SEQ_ID_WRITE_CSR:
++		return VCU_OPCODE_WRITE_CSR;
++	case SEQ_ID_READ_MMIO:
++		return VCU_OPCODE_READ_MMIO;
++	case SEQ_ID_WRITE_MMIO:
++		return VCU_OPCODE_WRITE_MMIO;
++	default:
++		return dead_code_t(enum vcu_opcode);
++	}
++}
++
++static enum vcu_opcode get_data_opcode(enum vcu_sequence seq)
++{
++	switch (seq) {
++	case SEQ_ID_READ_CSR:
++	case SEQ_ID_READ_MMIO:
++		return VCU_OPCODE_READ_DATA;
++	case SEQ_ID_WRITE_CSR:
++	case SEQ_ID_WRITE_MMIO:
++		return VCU_OPCODE_WRITE_DATA;
++	default:
++		return dead_code_t(enum vcu_opcode);
++	}
++}
++
++static uint32_t send_vcu_sequence(uint32_t addr, enum vcu_sequence seq, uint32_t wr_data)
++{
++	send_vcu_command(VCU_OPCODE_OPEN_SEQ, seq);
++
++	send_vcu_command(get_register_opcode(seq), addr);
++
++	send_vcu_command(get_data_opcode(seq), wr_data);
++
++	const uint32_t rd_data = mchbar_read32(VCU_MAILBOX_DATA);
++
++	send_vcu_command(VCU_OPCODE_CLOSE_SEQ, seq);
++
++	return rd_data;
++}
++
++uint32_t vcu_read_csr(uint32_t addr)
++{
++	return send_vcu_sequence(addr, SEQ_ID_READ_CSR, 0);
++}
++
++void vcu_write_csr(uint32_t addr, uint32_t data)
++{
++	send_vcu_sequence(addr, SEQ_ID_WRITE_CSR, data);
++}
++
++void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue)
++{
++	vcu_write_csr(addr, (vcu_read_csr(addr) & andvalue) | orvalue);
++}
++
++uint32_t vcu_read_mmio(uint32_t addr)
++{
++	return send_vcu_sequence(addr, SEQ_ID_READ_MMIO, 0);
++}
++
++void vcu_write_mmio(uint32_t addr, uint32_t data)
++{
++	send_vcu_sequence(addr, SEQ_ID_WRITE_MMIO, data);
++}
++
++void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue)
++{
++	vcu_write_mmio(addr, (vcu_read_mmio(addr) & andvalue) | orvalue);
++}
+diff --git a/src/northbridge/intel/haswell/vcu_mailbox.h b/src/northbridge/intel/haswell/vcu_mailbox.h
+new file mode 100644
+index 0000000000..ba0a62e486
+--- /dev/null
++++ b/src/northbridge/intel/haswell/vcu_mailbox.h
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#ifndef HASWELL_VCU_MAILBOX_H
++#define HASWELL_VCU_MAILBOX_H
++
++#include <stdint.h>
++
++uint32_t vcu_read_csr(uint32_t addr);
++void vcu_write_csr(uint32_t addr, uint32_t data);
++void vcu_update_csr(uint32_t addr, uint32_t andvalue, uint32_t orvalue);
++
++uint32_t vcu_read_mmio(uint32_t addr);
++void vcu_write_mmio(uint32_t addr, uint32_t data);
++void vcu_update_mmio(uint32_t addr, uint32_t andvalue, uint32_t orvalue);
++
++#endif /* HASWELL_VCU_MAILBOX_H */
+diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
+index 02022d348d..b8503ac8bc 100644
+--- a/src/southbridge/intel/lynxpoint/Makefile.inc
++++ b/src/southbridge/intel/lynxpoint/Makefile.inc
+@@ -37,6 +37,8 @@ bootblock-y += early_pch.c
+ romstage-y += early_usb.c early_me.c me_status.c early_pch.c
+ romstage-y += pmutil.c
+ 
++romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c
++
+ ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
+ romstage-y += lp_gpio.c
+ ramstage-y += lp_gpio.c
+diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c
+new file mode 100644
+index 0000000000..c28ddfcf5d
+--- /dev/null
++++ b/src/southbridge/intel/lynxpoint/early_pch_native.c
+@@ -0,0 +1,52 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <console/console.h>
++#include <device/pci_ops.h>
++#include <southbridge/intel/lynxpoint/pch.h>
++#include <types.h>
++
++void pch_dmi_setup_physical_layer(void)
++{
++	/* FIXME: We need to make sure the SA supports Gen2 as well */
++	if ((RCBA32(0x21a4) & 0x0f) == 0x02) {
++		/* Set Gen 2 Common Clock N_FTS */
++		RCBA32_AND_OR(0x2340, ~0x00ff0000, 0x3a << 16);
++
++		/* Set Target Link Speed to DMI Gen2 */
++		RCBA8_AND_OR(DLCTL2, ~0x07, 0x02);
++	}
++}
++
++#define VC_ACTIVE	(1U << 31)
++
++#define VCNEGPND	(1 << 1)
++
++void pch_dmi_tc_vc_mapping(const u32 vc0, const u32 vc1, const u32 vcp, const u32 vcm)
++{
++	printk(BIOS_DEBUG, "Programming PCH DMI VC/TC mappings...\n");
++
++	RCBA32_AND_OR(CIR0050, ~(0xf << 20), 2 << 20);
++	if (vcp & VC_ACTIVE)
++		RCBA32_OR(CIR0050, 1 << 19 | 1 << 17);
++
++	RCBA32(CIR0050);	/* Posted Write */
++
++	/* Use the same virtual channel mapping on both ends of the DMI link */
++	RCBA32(V0CTL) = vc0;
++	RCBA32(V1CTL) = vc1;
++	RCBA32(V1CTL);		/* Posted Write */
++	RCBA32(VPCTL) = vcp;
++	RCBA32(VPCTL);		/* Posted Write */
++	RCBA32(VMCTL) = vcm;
++
++	/* Lock the registers */
++	RCBA32_OR(CIR0050, 1U << 31);
++	RCBA32(CIR0050);	/* Posted Write */
++
++	printk(BIOS_DEBUG, "Waiting for PCH DMI VC negotiation... ");
++	do {} while (RCBA16(V0STS) & VCNEGPND);
++	do {} while (RCBA16(V1STS) & VCNEGPND);
++	do {} while (RCBA16(VPSTS) & VCNEGPND);
++	do {} while (RCBA16(VMSTS) & VCNEGPND);
++	printk(BIOS_DEBUG, "done!\n");
++}
+diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
+index 7d9fc6d6af..b5e0c2a830 100644
+--- a/src/southbridge/intel/lynxpoint/pch.h
++++ b/src/southbridge/intel/lynxpoint/pch.h
+@@ -113,6 +113,9 @@ enum pch_platform_type {
+ 	PCH_TYPE_ULT	 = 5,
+ };
+ 
++void pch_dmi_setup_physical_layer(void);
++void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
++
+ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
+ void usb_ehci_disable(pci_devfn_t dev);
+ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
+@@ -406,9 +409,10 @@ void mainboard_config_rcba(void);
+ 
+ /* Southbridge IO BARs */
+ 
++#define PMBASE			0x40
+ #define GPIOBASE		0x48
+ 
+-#define PMBASE		0x40
++#define CIR0050		0x0050	/* 32bit */
+ 
+ #define RPC		0x0400	/* 32bit */
+ #define RPFN		0x0404	/* 32bit */
+@@ -431,6 +435,20 @@ void mainboard_config_rcba(void);
+ #define IOTR2		0x1e90	/* 64bit */
+ #define IOTR3		0x1e98	/* 64bit */
+ 
++#define V0CTL		0x2014	/* 32bit */
++#define V0STS		0x201a	/* 16bit */
++
++#define V1CTL		0x2020	/* 32bit */
++#define V1STS		0x2026	/* 16bit */
++
++#define VPCTL		0x2030	/* 32bit */
++#define VPSTS		0x2038	/* 16bit */
++
++#define VMCTL		0x2040	/* 32bit */
++#define VMSTS		0x2048	/* 16bit */
++
++#define DLCTL2		0x21b0
++
+ #define TCTL		0x3000	/*  8bit */
+ 
+ #define NOINT		0
+-- 
+2.39.2
+

resources/coreboot/haswell/patches/0004-haswell-lynxpoint-Add-native-early-ME-init.patch

@@ -0,0 +1,148 @@
+From 98142e01fc8ebb3b762974e9e4de75e7f5c073b4 Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Fri, 6 May 2022 22:18:21 +0200
+Subject: [PATCH 04/26] haswell/lynxpoint: Add native early ME init
+
+Implement native early ME init for Lynx Point. This is only needed when
+MRC.bin is not used.
+
+Change-Id: If416e2078f139f26b4742c564b70e018725bf003
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../haswell/native_raminit/raminit_native.c   | 17 ++++++++++-
+ src/southbridge/intel/lynxpoint/early_me.c    | 30 ++++++++++++++++++-
+ src/southbridge/intel/lynxpoint/me.h          |  7 +++--
+ 3 files changed, 50 insertions(+), 4 deletions(-)
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+index 0938e026e3..6a002548c1 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+@@ -1,18 +1,24 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+ #include <console/console.h>
++#include <delay.h>
+ #include <northbridge/intel/haswell/haswell.h>
+ #include <northbridge/intel/haswell/raminit.h>
++#include <southbridge/intel/lynxpoint/me.h>
+ #include <types.h>
+ 
+ static bool early_init_native(int s3resume)
+ {
+ 	printk(BIOS_DEBUG, "Starting native platform initialisation\n");
+ 
++	intel_early_me_init();
++	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
++	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
++
+ 	if (!CONFIG(INTEL_LYNXPOINT_LP))
+ 		dmi_early_init();
+ 
+-	return false;
++	return cpu_replaced;
+ }
+ 
+ void perform_raminit(const int s3resume)
+@@ -25,6 +31,15 @@ void perform_raminit(const int s3resume)
+ 
+ 	(void)cpu_replaced;
+ 
++	/** TODO: Move after raminit */
++	if (intel_early_me_uma_size() > 0) {
++		/** TODO: Update status once raminit is implemented **/
++		uint8_t me_status = ME_INIT_STATUS_ERROR;
++		intel_early_me_init_done(me_status);
++	}
++
++	intel_early_me_status();
++
+ 	/** TODO: Implement the required magic **/
+ 	die("NATIVE RAMINIT: More Magic (tm) required.\n");
+ }
+diff --git a/src/southbridge/intel/lynxpoint/early_me.c b/src/southbridge/intel/lynxpoint/early_me.c
+index 947c570e16..07013c5539 100644
+--- a/src/southbridge/intel/lynxpoint/early_me.c
++++ b/src/southbridge/intel/lynxpoint/early_me.c
+@@ -1,11 +1,12 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+ 
+ #include <arch/io.h>
++#include <cf9_reset.h>
+ #include <device/pci_ops.h>
+ #include <console/console.h>
+ #include <delay.h>
+ #include <halt.h>
+-
++#include <timer.h>
+ #include "me.h"
+ #include "pch.h"
+ 
+@@ -60,6 +61,33 @@ int intel_early_me_init(void)
+ 	return 0;
+ }
+ 
++bool intel_early_me_cpu_replacement_check(void)
++{
++	printk(BIOS_DEBUG, "ME: Checking whether CPU was replaced... ");
++
++	struct stopwatch timer;
++	stopwatch_init_msecs_expire(&timer, 50);
++
++	union me_hfs2 hfs2;
++	do {
++		hfs2.raw = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS2);
++		if (stopwatch_expired(&timer)) {
++			/* Assume CPU was replaced just in case */
++			printk(BIOS_DEBUG, "timed out, assuming CPU was replaced\n");
++			return true;
++		}
++		udelay(ME_DELAY);
++	} while (!hfs2.cpu_replaced_valid);
++
++	if (hfs2.warm_reset_request) {
++		printk(BIOS_DEBUG, "warm reset needed for dynamic fusing\n");
++		system_reset();
++	}
++
++	printk(BIOS_DEBUG, "%sreplaced\n", hfs2.cpu_replaced_sts ? "" : "not ");
++	return hfs2.cpu_replaced_sts;
++}
++
+ int intel_early_me_uma_size(void)
+ {
+ 	union me_uma uma = { .raw = pci_read_config32(PCH_ME_DEV, PCI_ME_UMA) };
+diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h
+index fe8b0260c4..6990322651 100644
+--- a/src/southbridge/intel/lynxpoint/me.h
++++ b/src/southbridge/intel/lynxpoint/me.h
+@@ -177,14 +177,16 @@ union me_did {
+ union me_hfs2 {
+ 	struct __packed {
+ 		u32 bist_in_progress: 1;
+-		u32 reserved1: 2;
++		u32 icc_prog_sts: 2;
+ 		u32 invoke_mebx: 1;
+ 		u32 cpu_replaced_sts: 1;
+ 		u32 mbp_rdy: 1;
+ 		u32 mfs_failure: 1;
+ 		u32 warm_reset_request: 1;
+ 		u32 cpu_replaced_valid: 1;
+-		u32 reserved2: 4;
++		u32 reserved: 2;
++		u32 fw_upd_ipu: 1;
++		u32 reserved2: 1;
+ 		u32 mbp_cleared: 1;
+ 		u32 reserved3: 2;
+ 		u32 current_state: 8;
+@@ -338,6 +340,7 @@ void intel_me_status(union me_hfs hfs, union me_hfs2 hfs2);
+ 
+ void intel_early_me_status(void);
+ int intel_early_me_init(void);
++bool intel_early_me_cpu_replacement_check(void);
+ int intel_early_me_uma_size(void);
+ int intel_early_me_init_done(u8 status);
+ 
+-- 
+2.39.2
+

resources/coreboot/haswell/patches/0005-sb-intel-lynxpoint-Add-native-USB-init.patch

@@ -0,0 +1,783 @@
+From 9bfb8614dbf1d9800ef8251cb3d839bcdbe5577f Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Fri, 6 May 2022 23:17:39 +0200
+Subject: [PATCH 05/26] sb/intel/lynxpoint: Add native USB init
+
+Implement native USB initialisation for Lynx Point. This is only needed
+when MRC.bin is not used.
+
+TO DO: Figure out how to deal with the FIXME's and TODO's lying around.
+
+Change-Id: Ie0fbeeca7b1ca1557173772d733fd2fa27703373
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../haswell/native_raminit/raminit_native.c   |   3 +
+ src/southbridge/intel/lynxpoint/Makefile.inc  |   2 +-
+ src/southbridge/intel/lynxpoint/early_usb.c   |  11 -
+ .../intel/lynxpoint/early_usb_native.c        | 584 ++++++++++++++++++
+ src/southbridge/intel/lynxpoint/pch.h         |  49 ++
+ 5 files changed, 637 insertions(+), 12 deletions(-)
+ create mode 100644 src/southbridge/intel/lynxpoint/early_usb_native.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+index 6a002548c1..ef61d4ee09 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+@@ -5,6 +5,7 @@
+ #include <northbridge/intel/haswell/haswell.h>
+ #include <northbridge/intel/haswell/raminit.h>
+ #include <southbridge/intel/lynxpoint/me.h>
++#include <southbridge/intel/lynxpoint/pch.h>
+ #include <types.h>
+ 
+ static bool early_init_native(int s3resume)
+@@ -15,6 +16,8 @@ static bool early_init_native(int s3resume)
+ 	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
+ 	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
+ 
++	early_usb_init();
++
+ 	if (!CONFIG(INTEL_LYNXPOINT_LP))
+ 		dmi_early_init();
+ 
+diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
+index b8503ac8bc..0e1f2fe4eb 100644
+--- a/src/southbridge/intel/lynxpoint/Makefile.inc
++++ b/src/southbridge/intel/lynxpoint/Makefile.inc
+@@ -37,7 +37,7 @@ bootblock-y += early_pch.c
+ romstage-y += early_usb.c early_me.c me_status.c early_pch.c
+ romstage-y += pmutil.c
+ 
+-romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c
++romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c
+ 
+ ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
+ romstage-y += lp_gpio.c
+diff --git a/src/southbridge/intel/lynxpoint/early_usb.c b/src/southbridge/intel/lynxpoint/early_usb.c
+index a753681ce0..52e8ac17f8 100644
+--- a/src/southbridge/intel/lynxpoint/early_usb.c
++++ b/src/southbridge/intel/lynxpoint/early_usb.c
+@@ -4,17 +4,6 @@
+ #include <device/pci_def.h>
+ #include "pch.h"
+ 
+-/* HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index
+- * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
+- */
+-#if CONFIG_USBDEBUG_HCD_INDEX != 2
+-#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
+-#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
+-#else
+-#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
+-#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
+-#endif
+-
+ /*
+  * Setup USB controller MMIO BAR to prevent the
+  * reference code from resetting the controller.
+diff --git a/src/southbridge/intel/lynxpoint/early_usb_native.c b/src/southbridge/intel/lynxpoint/early_usb_native.c
+new file mode 100644
+index 0000000000..cb6f6ee8e6
+--- /dev/null
++++ b/src/southbridge/intel/lynxpoint/early_usb_native.c
+@@ -0,0 +1,584 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <console/console.h>
++#include <delay.h>
++#include <device/mmio.h>
++#include <device/pci_def.h>
++#include <device/pci_ops.h>
++#include <northbridge/intel/haswell/haswell.h>
++#include <northbridge/intel/haswell/raminit.h>
++#include <southbridge/intel/lynxpoint/iobp.h>
++#include <southbridge/intel/lynxpoint/pch.h>
++#include <timer.h>
++#include <types.h>
++
++static unsigned int is_usbr_enabled(void)
++{
++	return !!(pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) & BIT(5));
++}
++
++static char *const xhci_bar = (char *)PCH_XHCI_TEMP_BAR0;
++
++static void ehci_hcs_init(const pci_devfn_t dev, const uintptr_t ehci_bar)
++{
++	pci_write_config32(dev, PCI_BASE_ADDRESS_0, ehci_bar);
++
++	/** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/
++	pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
++
++	char *const mem_bar = (char *)ehci_bar;
++
++	/**
++	 * Shared EHCI/XHCI ports w/a.
++	 * This step is required when some of the ports are routed to EHCI
++	 * and other ports are routed XHCI at the same time.
++	 *
++	 * FIXME: Under which conditions should this be done?
++	 */
++	pci_and_config16(dev, 0x78, ~0x03);
++
++	/* Skip reset if usbdebug is enabled */
++	if (!CONFIG(USBDEBUG_IN_PRE_RAM))
++		setbits32(mem_bar + EHCI_USB_CMD, EHCI_USB_CMD_HCRESET);
++
++	/* 2: Configure number of controllers and ports */
++	pci_or_config16(dev, EHCI_ACCESS_CNTL, ACCESS_CNTL_ENABLE);
++	clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf << 12, 0);
++	clrsetbits32(mem_bar + EHCI_HCS_PARAMS, 0xf <<  0, 2 + is_usbr_enabled());
++	pci_and_config16(dev, EHCI_ACCESS_CNTL, ~ACCESS_CNTL_ENABLE);
++
++	pci_or_config16(dev, 0x78, BIT(2));
++	pci_or_config16(dev, 0x7c, BIT(14) | BIT(7));
++	pci_update_config32(dev, 0x8c, ~(0xf << 8), (4 << 8));
++	pci_update_config32(dev, 0x8c, ~BIT(26), BIT(17));
++}
++
++static inline unsigned int physical_port_count(void)
++{
++	return MAX_USB2_PORTS;
++}
++
++static unsigned int hs_port_count(void)
++{
++	/** TODO: Apparently, WPT-LP has 10 USB2 ports **/
++	if (CONFIG(INTEL_LYNXPOINT_LP))
++		return 8;
++
++	switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 1) & 3) {
++	case 3:
++		return 8;
++	case 2:
++		return 10;
++	case 1:
++		return 12;
++	case 0:
++	default:
++		return 14;
++	}
++}
++
++static unsigned int ss_port_count(void)
++{
++	if (CONFIG(INTEL_LYNXPOINT_LP))
++		return 4;
++
++	switch ((pci_read_config32(PCH_XHCI_DEV, XHCI_USB3FUS) >> 3) & 3) {
++	case 3:
++		return 0;
++	case 2:
++		return 2;
++	case 1:
++		return 4;
++	case 0:
++	default:
++		return 6;
++	}
++}
++
++static void common_ehci_hcs_init(void)
++{
++	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
++
++	ehci_hcs_init(PCH_EHCI1_DEV, PCH_EHCI1_TEMP_BAR0);
++	if (!is_lp)
++		ehci_hcs_init(PCH_EHCI2_DEV, PCH_EHCI2_TEMP_BAR0);
++
++	pch_iobp_update(0xe5007f04, 0, 0x00004481);
++
++	for (unsigned int port = 0; port < physical_port_count(); port++)
++		pch_iobp_update(0xe500400f + port * 0x100, ~(1 << 0), 0 << 0);
++
++	pch_iobp_update(0xe5007f14, ~(3 << 19), (3 << 19));
++
++	if (is_lp)
++		pch_iobp_update(0xe5007f02, ~(3 << 22), (0 << 22));
++}
++
++static void xhci_open_memory_space(void)
++{
++	/** FIXME: Determine whether Bus Master is required (or clean it up afterwards) **/
++	pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, (uintptr_t)xhci_bar);
++	pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
++}
++
++static void xhci_close_memory_space(void)
++{
++	pci_and_config16(PCH_XHCI_DEV, PCI_COMMAND, ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY));
++	pci_write_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0, 0);
++}
++
++static void common_xhci_hc_init(void)
++{
++	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
++
++	if (!is_lp) {
++		const unsigned int max_ports = 15 + ss_port_count();
++		clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_1, 0xf << 28, max_ports << 28);
++	}
++
++	clrsetbits32(xhci_bar + XHCI_HCS_PARAMS_3, 0xffff << 16 | 0xff, 0x200 << 16 | 0x0a);
++	clrsetbits32(xhci_bar + XHCI_HCC_PARAMS, BIT(5), BIT(10) | BIT(9));
++
++	if (!is_lp)
++		clrsetbits32(xhci_bar + 0x8008, BIT(19), 0);
++
++	if (is_lp)
++		clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16));
++	else
++		clrsetbits32(xhci_bar + 0x8058, BIT(8), BIT(16) | BIT(20));
++
++	clrsetbits32(xhci_bar + 0x8060, 0, BIT(25) | BIT(18));
++	clrsetbits32(xhci_bar + 0x8090, 0, BIT(14) | BIT(8));
++	clrsetbits32(xhci_bar + 0x8094, 0, BIT(23) | BIT(21) | BIT(14));
++	clrsetbits32(xhci_bar + 0x80e0, BIT(16), BIT(6));
++	clrsetbits32(xhci_bar + 0x80ec, (7 << 12) | (7 << 9), (0 << 12) | (6 << 9));
++	clrsetbits32(xhci_bar + 0x80f0, BIT(20), 0);
++
++	if (is_lp)
++		clrsetbits32(xhci_bar + 0x80fc, 0, BIT(25));
++
++	if (is_lp)
++		clrsetbits32(xhci_bar + 0x8110, BIT(8) | BIT(2), BIT(20) | BIT(11));
++	else
++		clrsetbits32(xhci_bar + 0x8110, BIT(2), BIT(20) | BIT(11));
++
++	if (is_lp)
++		write32(xhci_bar + 0x8140, 0xff00f03c);
++	else
++		write32(xhci_bar + 0x8140, 0xff03c132);
++
++	if (is_lp)
++		clrsetbits32(xhci_bar + 0x8154, BIT(21), BIT(13));
++	else
++		clrsetbits32(xhci_bar + 0x8154, BIT(21) | BIT(13), 0);
++
++	clrsetbits32(xhci_bar + 0x8154, BIT(3), 0);
++
++	if (is_lp) {
++		clrsetbits32(xhci_bar + 0x8164, 0, BIT(1) | BIT(0));
++		write32(xhci_bar + 0x8174, 0x01400c0a);
++		write32(xhci_bar + 0x817c, 0x033200a3);
++		write32(xhci_bar + 0x8180, 0x00cb0028);
++		write32(xhci_bar + 0x8184, 0x0064001e);
++	}
++
++	/*
++	 * Note: Register at offset 0x44 is 32-bit, but bit 31 is write-once.
++	 * We use these weird partial accesses here to avoid locking bit 31.
++	 */
++	pci_or_config16(PCH_XHCI_DEV, 0x44, BIT(15) | BIT(14) | BIT(10) | BIT(0));
++	pci_or_config8(PCH_XHCI_DEV, 0x44 + 2, 0x0f);
++
++	/* LPT-LP >= B0 */
++	if (is_lp)
++		clrsetbits32(xhci_bar + 0x8188, 0, BIT(26) | BIT(24));
++
++	/* LPT-H >= C0 */
++	if (!is_lp)
++		clrsetbits32(xhci_bar + 0x8188, 0, BIT(24));
++}
++
++static inline bool is_mem_sr(void)
++{
++	return pci_read_config16(PCH_LPC_DEV, GEN_PMCON_2) & GEN_PMCON_2_MEM_SR;
++}
++
++static bool should_restore_xhci_smart_auto(void)
++{
++	if (!is_mem_sr())
++		return false;
++
++	return pci_read_config32(PCH_LPC_DEV, PMIR) & PMIR_XHCI_SMART_AUTO;
++}
++
++enum usb_port_route {
++	ROUTE_TO_EHCI,
++	ROUTE_TO_XHCI,
++};
++
++/* Returns whether port reset was successful */
++static bool reset_usb2_ports(const unsigned int ehci_ports)
++{
++	for (unsigned int port = 0; port < ehci_ports; port++) {
++		/* Initiate port reset for all USB2 ports */
++		clrsetbits32(
++			xhci_bar + XHCI_USB2_PORTSC(port),
++			XHCI_USB2_PORTSC_PED,
++			XHCI_USB2_PORTSC_PR);
++	}
++	/* Poll for port reset bit to be cleared or time out at 100ms */
++	struct stopwatch timer;
++	stopwatch_init_msecs_expire(&timer, 100);
++	uint32_t reg32;
++	do {
++		reg32 = 0;
++		for (unsigned int port = 0; port < ehci_ports; port++)
++			reg32 |= read32(xhci_bar + XHCI_USB2_PORTSC(port));
++
++		reg32 &= XHCI_USB2_PORTSC_PR;
++		if (!reg32) {
++			const long elapsed_time = stopwatch_duration_usecs(&timer);
++			printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time);
++			return true;
++		}
++		/* Reference code has a 10 ms delay here, but a smaller delay works too */
++		udelay(100);
++	} while (!stopwatch_expired(&timer));
++	printk(BIOS_ERR, "%s: timed out\n", __func__);
++	return !reg32;
++}
++
++/* Returns whether warm reset was successful */
++static bool warm_reset_usb3_ports(const unsigned int xhci_ports)
++{
++	for (unsigned int port = 0; port < xhci_ports; port++) {
++		/* Initiate warm reset for all USB3 ports */
++		clrsetbits32(
++			xhci_bar + XHCI_USB3_PORTSC(port),
++			XHCI_USB3_PORTSC_PED,
++			XHCI_USB3_PORTSC_WPR);
++	}
++	/* Poll for port reset bit to be cleared or time out at 100ms */
++	struct stopwatch timer;
++	stopwatch_init_msecs_expire(&timer, 100);
++	uint32_t reg32;
++	do {
++		reg32 = 0;
++		for (unsigned int port = 0; port < xhci_ports; port++)
++			reg32 |= read32(xhci_bar + XHCI_USB3_PORTSC(port));
++
++		reg32 &= XHCI_USB3_PORTSC_PR;
++		if (!reg32) {
++			const long elapsed_time = stopwatch_duration_usecs(&timer);
++			printk(BIOS_DEBUG, "%s: took %lu usecs\n", __func__, elapsed_time);
++			return true;
++		}
++		/* Reference code has a 10 ms delay here, but a smaller delay works too */
++		udelay(100);
++	} while (!stopwatch_expired(&timer));
++	printk(BIOS_ERR, "%s: timed out\n", __func__);
++	return !reg32;
++}
++
++static void perform_xhci_ehci_switching_flow(const enum usb_port_route usb_route)
++{
++	const pci_devfn_t dev = PCH_XHCI_DEV;
++
++	const unsigned int ehci_ports = hs_port_count() + is_usbr_enabled();
++	const unsigned int xhci_ports = ss_port_count();
++
++	const uint32_t ehci_mask = BIT(ehci_ports) - 1;
++	const uint32_t xhci_mask = BIT(xhci_ports) - 1;
++
++	/** TODO: Handle USBr port? How, though? **/
++	pci_update_config32(dev, XHCI_USB2PRM, ~XHCI_USB2PR_HCSEL, ehci_mask);
++	pci_update_config32(dev, XHCI_USB3PRM, ~XHCI_USB3PR_SSEN,  xhci_mask);
++
++	/*
++	 * Workaround for USB2PR / USB3PR value not surviving warm reset.
++	 * Restore USB Port Routing registers if OS HC Switch driver has been executed.
++	 */
++	if (should_restore_xhci_smart_auto()) {
++		/** FIXME: Derive values from mainboard code instead? **/
++		pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_mask);
++		pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN,  xhci_mask);
++	}
++
++	/* Later stages shouldn't need the value of this bit */
++	pci_and_config32(PCH_LPC_DEV, PMIR, ~PMIR_XHCI_SMART_AUTO);
++
++	/**
++	 * FIXME: Things here depend on the chosen routing mode.
++	 *        For now, implement both functions.
++	 */
++
++	/* Route to EHCI if xHCI disabled or auto mode */
++	if (usb_route == ROUTE_TO_EHCI) {
++		if (!reset_usb2_ports(ehci_ports))
++			printk(BIOS_ERR, "USB2 port reset timed out\n");
++
++		pci_and_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL);
++
++		for (unsigned int port = 0; port < ehci_ports; port++) {
++			clrsetbits32(
++				xhci_bar + XHCI_USB2_PORTSC(port),
++				XHCI_USB2_PORTSC_PED,
++				XHCI_USB2_PORTSC_CHST);
++		}
++
++		if (!warm_reset_usb3_ports(xhci_ports))
++			printk(BIOS_ERR, "USB3 warm reset timed out\n");
++
++		/* FIXME: BWG says this should be inside the warm reset function */
++		pci_and_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN);
++
++		for (unsigned int port = 0; port < ehci_ports; port++) {
++			clrsetbits32(
++				xhci_bar + XHCI_USB3_PORTSC(port),
++				XHCI_USB3_PORTSC_PED,
++				XHCI_USB3_PORTSC_CHST);
++		}
++
++		setbits32(xhci_bar + XHCI_USBCMD, BIT(0));
++		clrbits32(xhci_bar + XHCI_USBCMD, BIT(0));
++	}
++
++	/* Route to xHCI if xHCI enabled */
++	if (usb_route == ROUTE_TO_XHCI) {
++		if (is_mem_sr()) {
++			if (!warm_reset_usb3_ports(xhci_ports))
++				printk(BIOS_ERR, "USB3 warm reset timed out\n");
++		}
++
++		const uint32_t xhci_port_mask = pci_read_config32(dev, XHCI_USB3PRM) & 0x3f;
++		pci_update_config32(dev, XHCI_USB3PR, ~XHCI_USB3PR_SSEN, xhci_port_mask);
++
++		const uint32_t ehci_port_mask = pci_read_config32(dev, XHCI_USB2PRM) & 0x7fff;
++		pci_update_config32(dev, XHCI_USB2PR, ~XHCI_USB2PR_HCSEL, ehci_port_mask);
++	}
++}
++
++/* Do not shift in this macro, as it can cause undefined behaviour for bad port/oc values */
++#define PORT_TO_OC_SHIFT(port, oc)	((oc) * 8 + (port))
++
++/* Avoid shifting into undefined behaviour */
++static inline bool shift_ok(const int shift)
++{
++	return shift >= 0 && shift < 32;
++}
++
++static void usb_overcurrent_mapping(void)
++{
++	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
++
++	uint32_t ehci_1_ocmap = 0;
++	uint32_t ehci_2_ocmap = 0;
++	uint32_t xhci_1_ocmap = 0;
++	uint32_t xhci_2_ocmap = 0;
++
++	/*
++	 * EHCI
++	 */
++	for (unsigned int idx = 0; idx < physical_port_count(); idx++) {
++		const struct usb2_port_config *const port = &mainboard_usb2_ports[idx];
++		printk(BIOS_DEBUG, "USB2 port %u => ", idx);
++		if (!port->enable) {
++			printk(BIOS_DEBUG, "disabled\n");
++			continue;
++		}
++		const unsigned short oc_pin = port->oc_pin;
++		if (oc_pin == USB_OC_PIN_SKIP) {
++			printk(BIOS_DEBUG, "not mapped to OC pin\n");
++			continue;
++		}
++		/* Ports 0 .. 7 => OC 0 .. 3 */
++		if (idx < 8 && oc_pin <= 3) {
++			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin);
++			if (shift_ok(shift)) {
++				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
++				ehci_1_ocmap |= 1 << shift;
++				continue;
++			}
++		}
++		/* Ports 8 .. 13 => OC 4 .. 7 (LPT-H only) */
++		if (!is_lp && idx >= 8 && oc_pin >= 4) {
++			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4);
++			if (shift_ok(shift)) {
++				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
++				ehci_2_ocmap |= 1 << shift;
++				continue;
++			}
++		}
++		printk(BIOS_ERR, "Invalid OC pin %u for USB2 port %u\n", oc_pin, idx);
++	}
++	printk(BIOS_DEBUG, "\n");
++	pci_write_config32(PCH_EHCI1_DEV, EHCI_OCMAP, ehci_1_ocmap);
++	if (!is_lp)
++		pci_write_config32(PCH_EHCI2_DEV, EHCI_OCMAP, ehci_2_ocmap);
++
++	/*
++	 * xHCI
++	 */
++	for (unsigned int idx = 0; idx < ss_port_count(); idx++) {
++		const struct usb3_port_config *const port = &mainboard_usb3_ports[idx];
++		printk(BIOS_DEBUG, "USB3 port %u => ", idx);
++		if (!port->enable) {
++			printk(BIOS_DEBUG, "disabled\n");
++			continue;
++		}
++		const unsigned short oc_pin = port->oc_pin;
++		if (oc_pin == USB_OC_PIN_SKIP) {
++			printk(BIOS_DEBUG, "not mapped to OC pin\n");
++			continue;
++		}
++		/* Ports 0 .. 5 => OC 0 .. 3 */
++		if (oc_pin <= 3) {
++			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin);
++			if (shift_ok(shift)) {
++				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
++				xhci_1_ocmap |= 1 << shift;
++				continue;
++			}
++		}
++		/* Ports 0 .. 5 => OC 4 .. 7 (LPT-H only) */
++		if (!is_lp && oc_pin >= 4) {
++			const int shift = PORT_TO_OC_SHIFT(idx, oc_pin - 4);
++			if (shift_ok(shift)) {
++				printk(BIOS_DEBUG, "mapped to OC pin %u\n", oc_pin);
++				xhci_2_ocmap |= 1 << shift;
++				continue;
++			}
++		}
++		printk(BIOS_ERR, "Invalid OC pin %u for USB3 port %u\n", oc_pin, idx);
++	}
++	printk(BIOS_DEBUG, "\n");
++	pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM1, ehci_1_ocmap);
++	pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM1, xhci_1_ocmap);
++	if (!is_lp) {
++		pci_write_config32(PCH_XHCI_DEV, XHCI_U2OCM2, ehci_2_ocmap);
++		pci_write_config32(PCH_XHCI_DEV, XHCI_U3OCM2, xhci_2_ocmap);
++	}
++}
++
++static uint8_t get_ehci_tune_param_1(const struct usb2_port_config *const port)
++{
++	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
++
++	const enum pch_platform_type plat_type = get_pch_platform_type();
++	const enum usb2_port_location location = port->location;
++	const uint16_t length = port->length;
++	if (!is_lp) {
++		if (plat_type == PCH_TYPE_DESKTOP) {
++			if (location == USB_PORT_BACK_PANEL)
++				return 4; /* Back Panel */
++			else
++				return 3; /* Front Panel */
++
++		} else if (plat_type == PCH_TYPE_MOBILE) {
++			if (location == USB_PORT_INTERNAL)
++				return 5; /* Internal Topology */
++			else if (location == USB_PORT_DOCK)
++				return 4; /* Dock */
++			else if (length < 0x70)
++				return 5; /* Back Panel, less than 7" */
++			else
++				return 6; /* Back Panel, 7" or more */
++		}
++	} else {
++		if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) {
++			if (length < 0x70)
++				return 5; /* Back Panel, less than 7" */
++			else
++				return 6; /* Back Panel, 7" or more */
++		} else if (location == USB_PORT_DOCK) {
++			return 4; /* Dock */
++		} else {
++			return 5; /* Internal Topology */
++		}
++	}
++	printk(BIOS_ERR, "%s: Unhandled case\n", __func__);
++	return 0;
++}
++
++static uint8_t get_ehci_tune_param_2(const struct usb2_port_config *const port)
++{
++	const bool is_lp = CONFIG(INTEL_LYNXPOINT_LP);
++
++	const enum pch_platform_type plat_type = get_pch_platform_type();
++	const enum usb2_port_location location = port->location;
++	const uint16_t length = port->length;
++	if (!is_lp) {
++		if (plat_type == PCH_TYPE_DESKTOP) {
++			if (location == USB_PORT_BACK_PANEL) {
++				if (length < 0x80)
++					return 2; /* Back Panel, less than 8" */
++				else if (length < 0x130)
++					return 3; /* Back Panel, 8"-13" */
++				else
++					return 4; /* Back Panel, 13" or more */
++			} else {
++				return 2; /* Front Panel */
++			}
++
++		} else if (plat_type == PCH_TYPE_MOBILE) {
++			if (location == USB_PORT_INTERNAL) {
++				return 2; /* Internal Topology */
++			} else if (location == USB_PORT_DOCK) {
++				if (length < 0x50)
++					return 1; /* Dock, less than 5" */
++				else
++					return 2; /* Dock, 5" or more */
++			} else {
++				if (length < 0x100)
++					return 2; /* Back Panel, less than 10" */
++				else
++					return 3; /* Back Panel, 10" or more */
++			}
++		}
++	} else {
++		if (location == USB_PORT_BACK_PANEL || location == USB_PORT_MINI_PCIE) {
++			if (length < 0x100)
++				return 2; /* Back Panel, less than 10" */
++			else
++				return 3; /* Back Panel, 10" or more */
++		} else if (location == USB_PORT_DOCK) {
++			if (length < 0x50)
++				return 1; /* Dock, less than 5" */
++			else
++				return 2; /* Dock, 5" or more */
++		} else {
++			return 2; /* Internal Topology */
++		}
++	}
++	printk(BIOS_ERR, "%s: Unhandled case\n", __func__);
++	return 0;
++}
++
++static void program_ehci_port_length(void)
++{
++	for (unsigned int port = 0; port < physical_port_count(); port++) {
++		if (!mainboard_usb2_ports[port].enable)
++			continue;
++		const uint32_t addr = 0xe5004000 + (port + 1) * 0x100;
++		const uint8_t param_1 = get_ehci_tune_param_1(&mainboard_usb2_ports[port]);
++		const uint8_t param_2 = get_ehci_tune_param_2(&mainboard_usb2_ports[port]);
++		pch_iobp_update(addr, ~0x7f00, param_2 << 11 | param_1 << 8);
++	}
++}
++
++void early_usb_init(void)
++{
++	/** TODO: Make this configurable? How do the modes affect usbdebug? **/
++	const enum usb_port_route usb_route = ROUTE_TO_XHCI;
++	///(pd->boot_mode == 2 && pd->usb_xhci_on_resume) ? ROUTE_TO_XHCI : ROUTE_TO_EHCI;
++
++	common_ehci_hcs_init();
++	xhci_open_memory_space();
++	common_xhci_hc_init();
++	perform_xhci_ehci_switching_flow(usb_route);
++	usb_overcurrent_mapping();
++	program_ehci_port_length();
++	/** FIXME: USB per port control is missing, is it needed? **/
++	xhci_close_memory_space();
++	/** TODO: Close EHCI memory space? **/
++}
+diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
+index b5e0c2a830..ad983d86cf 100644
+--- a/src/southbridge/intel/lynxpoint/pch.h
++++ b/src/southbridge/intel/lynxpoint/pch.h
+@@ -115,6 +115,7 @@ enum pch_platform_type {
+ 
+ void pch_dmi_setup_physical_layer(void);
+ void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
++void early_usb_init(void);
+ 
+ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
+ void usb_ehci_disable(pci_devfn_t dev);
+@@ -202,6 +203,8 @@ void mainboard_config_rcba(void);
+ #define GEN_PMCON_1		0xa0
+ #define  SMI_LOCK		(1 << 4)
+ #define GEN_PMCON_2		0xa2
++#define  GEN_PMCON_2_DISB	(1 << 7)
++#define  GEN_PMCON_2_MEM_SR	(1 << 5)
+ #define  SYSTEM_RESET_STS	(1 << 4)
+ #define  THERMTRIP_STS		(1 << 3)
+ #define  SYSPWR_FLR		(1 << 1)
+@@ -215,6 +218,7 @@ void mainboard_config_rcba(void);
+ #define PMIR			0xac
+ #define  PMIR_CF9LOCK		(1 << 31)
+ #define  PMIR_CF9GR		(1 << 20)
++#define  PMIR_XHCI_SMART_AUTO	(1 << 16) /* c.f. LPT BWG or WPT-LP BIOS spec */
+ 
+ /* GEN_PMCON_3 bits */
+ #define RTC_BATTERY_DEAD	(1 << 2)
+@@ -282,6 +286,20 @@ void mainboard_config_rcba(void);
+ #define SATA_DTLE_DATA_SHIFT	24
+ #define SATA_DTLE_EDGE_SHIFT	16
+ 
++/*
++ * HCD_INDEX == 2 selects 0:1a.0 (PCH_EHCI2), any other index
++ * selects 0:1d.0 (PCH_EHCI1) for usbdebug use.
++ */
++#if CONFIG_USBDEBUG_HCD_INDEX != 2
++#define PCH_EHCI1_TEMP_BAR0 CONFIG_EHCI_BAR
++#define PCH_EHCI2_TEMP_BAR0 (PCH_EHCI1_TEMP_BAR0 + 0x400)
++#else
++#define PCH_EHCI2_TEMP_BAR0 CONFIG_EHCI_BAR
++#define PCH_EHCI1_TEMP_BAR0 (PCH_EHCI2_TEMP_BAR0 + 0x400)
++#endif
++
++#define PCH_XHCI_TEMP_BAR0	0xe8100000
++
+ /* EHCI PCI Registers */
+ #define EHCI_PWR_CTL_STS	0x54
+ #define  PWR_CTL_SET_MASK	0x3
+@@ -289,10 +307,15 @@ void mainboard_config_rcba(void);
+ #define  PWR_CTL_SET_D3		0x3
+ #define  PWR_CTL_ENABLE_PME	(1 << 8)
+ #define  PWR_CTL_STATUS_PME	(1 << 15)
++#define EHCI_OCMAP		0x74
++#define EHCI_ACCESS_CNTL	0x80
++#define  ACCESS_CNTL_ENABLE	(1 << 0)
+ 
+ /* EHCI Memory Registers */
++#define EHCI_HCS_PARAMS		0x04
+ #define EHCI_USB_CMD		0x20
+ #define  EHCI_USB_CMD_RUN	(1 << 0)
++#define  EHCI_USB_CMD_HCRESET	(1 << 1)
+ #define  EHCI_USB_CMD_PSE	(1 << 4)
+ #define  EHCI_USB_CMD_ASE	(1 << 5)
+ #define EHCI_PORTSC(port)	(0x64 + (port) * 4)
+@@ -301,6 +324,10 @@ void mainboard_config_rcba(void);
+ 
+ /* XHCI PCI Registers */
+ #define XHCI_PWR_CTL_STS	0x74
++#define XHCI_U2OCM1		0xc0
++#define XHCI_U2OCM2		0xc4
++#define XHCI_U3OCM1		0xc8
++#define XHCI_U3OCM2		0xcc
+ #define XHCI_USB2PR		0xd0
+ #define XHCI_USB2PRM		0xd4
+ #define  XHCI_USB2PR_HCSEL	0x7fff
+@@ -313,6 +340,27 @@ void mainboard_config_rcba(void);
+ #define XHCI_USB3PDO		0xe8
+ 
+ /* XHCI Memory Registers */
++#define XHCI_HCS_PARAMS_1	0x04
++#define XHCI_HCS_PARAMS_2	0x08
++#define XHCI_HCS_PARAMS_3	0x0c
++#define XHCI_HCC_PARAMS		0x10
++#define XHCI_USBCMD		0x80
++#define XHCI_USB2_PORTSC(port)	(0x480 + ((port) * 0x10))
++#define  XHCI_USB2_PORTSC_WPR	(1 << 31)	/* Warm Port Reset */
++#define  XHCI_USB2_PORTSC_CEC	(1 << 23)	/* Port Config Error Change */
++#define  XHCI_USB2_PORTSC_PLC	(1 << 22)	/* Port Link State Change */
++#define  XHCI_USB2_PORTSC_PRC	(1 << 21)	/* Port Reset Change */
++#define  XHCI_USB2_PORTSC_OCC	(1 << 20)	/* Over-current Change */
++#define  XHCI_USB2_PORTSC_WRC	(1 << 19)	/* Warm Port Reset Change */
++#define  XHCI_USB2_PORTSC_PEC	(1 << 18)	/* Port Enabled Disabled Change */
++#define  XHCI_USB2_PORTSC_CSC	(1 << 17)	/* Connect Status Change */
++#define  XHCI_USB2_PORTSC_CHST	(0x7f << 17)
++#define  XHCI_USB2_PORTSC_LWS	(1 << 16)	/* Port Link State Write Strobe */
++#define  XHCI_USB2_PORTSC_PP	(1 <<  9)
++#define  XHCI_USB2_PORTSC_PR	(1 <<  4)	/* Port Reset */
++#define  XHCI_USB2_PORTSC_PED	(1 <<  1)	/* Port Enable/Disabled */
++#define  XHCI_USB2_PORTSC_CCS	(1 <<  0)	/* Current Connect Status */
++
+ #define XHCI_USB3_PORTSC(port)	((pch_is_lp() ? 0x510 : 0x570) + ((port) * 0x10))
+ #define  XHCI_USB3_PORTSC_CHST	(0x7f << 17)
+ #define  XHCI_USB3_PORTSC_WCE	(1 << 25)	/* Wake on Connect */
+@@ -320,6 +368,7 @@ void mainboard_config_rcba(void);
+ #define  XHCI_USB3_PORTSC_WOE	(1 << 27)	/* Wake on Overcurrent */
+ #define  XHCI_USB3_PORTSC_WRC	(1 << 19)	/* Warm Reset Complete */
+ #define  XHCI_USB3_PORTSC_LWS	(1 << 16)	/* Link Write Strobe */
++#define  XHCI_USB3_PORTSC_PR	(1 << 4)	/* Port Reset */
+ #define  XHCI_USB3_PORTSC_PED	(1 << 1)	/* Port Enabled/Disabled */
+ #define  XHCI_USB3_PORTSC_WPR	(1 << 31)	/* Warm Port Reset */
+ #define  XHCI_USB3_PORTSC_PLS	(0xf << 5)	/* Port Link State */
+-- 
+2.39.2
+

resources/coreboot/haswell/patches/0006-sb-intel-lynxpoint-Add-native-thermal-init.patch

@@ -0,0 +1,128 @@
+From 92be49d8422b4bc1c89bb49535f4dc6a01d47295 Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Fri, 6 May 2022 23:22:11 +0200
+Subject: [PATCH 06/26] sb/intel/lynxpoint: Add native thermal init
+
+Implement native thermal initialisation for Lynx Point. This is only
+needed when MRC.bin is not used.
+
+Change-Id: I4a67a3092d0c2e56bfdacb513a899ef838193cbd
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../haswell/native_raminit/raminit_native.c   |  1 +
+ src/southbridge/intel/lynxpoint/Makefile.inc  |  2 +-
+ src/southbridge/intel/lynxpoint/pch.h         |  1 +
+ src/southbridge/intel/lynxpoint/thermal.c     | 64 +++++++++++++++++++
+ 4 files changed, 67 insertions(+), 1 deletion(-)
+ create mode 100644 src/southbridge/intel/lynxpoint/thermal.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+index ef61d4ee09..dd1f1ec14e 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+@@ -16,6 +16,7 @@ static bool early_init_native(int s3resume)
+ 	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
+ 	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
+ 
++	early_thermal_init();
+ 	early_usb_init();
+ 
+ 	if (!CONFIG(INTEL_LYNXPOINT_LP))
+diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
+index 0e1f2fe4eb..a9a9b153d6 100644
+--- a/src/southbridge/intel/lynxpoint/Makefile.inc
++++ b/src/southbridge/intel/lynxpoint/Makefile.inc
+@@ -37,7 +37,7 @@ bootblock-y += early_pch.c
+ romstage-y += early_usb.c early_me.c me_status.c early_pch.c
+ romstage-y += pmutil.c
+ 
+-romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c
++romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c
+ 
+ ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
+ romstage-y += lp_gpio.c
+diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
+index ad983d86cf..38a9349220 100644
+--- a/src/southbridge/intel/lynxpoint/pch.h
++++ b/src/southbridge/intel/lynxpoint/pch.h
+@@ -116,6 +116,7 @@ enum pch_platform_type {
+ void pch_dmi_setup_physical_layer(void);
+ void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
+ void early_usb_init(void);
++void early_thermal_init(void);
+ 
+ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
+ void usb_ehci_disable(pci_devfn_t dev);
+diff --git a/src/southbridge/intel/lynxpoint/thermal.c b/src/southbridge/intel/lynxpoint/thermal.c
+new file mode 100644
+index 0000000000..e71969ea0c
+--- /dev/null
++++ b/src/southbridge/intel/lynxpoint/thermal.c
+@@ -0,0 +1,64 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <device/mmio.h>
++#include <device/pci_ops.h>
++#include <southbridge/intel/lynxpoint/pch.h>
++#include <types.h>
++
++#define TBARB_TEMP 0x40000000
++
++#define THERMAL_DEV PCI_DEV(0, 0x1f, 6)
++
++/* Early thermal init, it may need to be done prior to giving ME its memory */
++void early_thermal_init(void)
++{
++	/* Program address for temporary BAR */
++	pci_write_config32(THERMAL_DEV, 0x40, TBARB_TEMP);
++	pci_write_config32(THERMAL_DEV, 0x44, 0);
++
++	/* Activate temporary BAR */
++	pci_or_config32(THERMAL_DEV, 0x40, 1);
++
++	/*
++	 * BWG section 17.3.1 says:
++	 *
++	 * ### Initializing Lynx Point Thermal Sensors ###
++	 *
++	 * The System BIOS must perform the following steps to initialize the Lynx
++	 * Point thermal subsystem device, D31:F6. The System BIOS is required to
++	 * repeat this process on a resume from Sx. BIOS may enable any or all of
++	 * the registers below based on OEM's platform configuration. Intel does
++	 * not recommend a value on some of the registers, since each platform has
++	 * different temperature trip points and one may enable a trip to cause an
++	 * SMI while another platform would cause an interrupt instead.
++	 *
++	 * The recommended flow for enabling thermal sensor is by setting up various
++	 * temperature trip points first, followed by enabling the desired trip
++	 * alert method and then enable the actual sensors from TSEL registers.
++	 * If this flow is not followed, software will need to take special care
++	 * to handle false events during setting up those registers.
++	 */
++
++	/* Step 1: Program CTT */
++	write16p(TBARB_TEMP + 0x10, 0x0154);
++
++	/* Step 2: Clear trip status from TSS and TAS */
++	write8p(TBARB_TEMP + 0x06, 0xff);
++	write8p(TBARB_TEMP + 0x80, 0xff);
++
++	/* Step 3: Program TSGPEN and TSPIEN to zero */
++	write8p(TBARB_TEMP + 0x84, 0x00);
++	write8p(TBARB_TEMP + 0x82, 0x00);
++
++	/*
++	 * Step 4: If thermal reporting to an EC over SMBus is supported,
++	 *         then write 0x01 to TSREL, else leave at default.
++	 */
++	write8p(TBARB_TEMP + 0x0a, 0x01);
++
++	/* Disable temporary BAR */
++	pci_and_config32(THERMAL_DEV, 0x40, ~1);
++
++	/* Clear temporary BAR address */
++	pci_write_config32(THERMAL_DEV, 0x40, 0);
++}
+-- 
+2.39.2
+

resources/coreboot/haswell/patches/0007-sb-intel-lynxpoint-Add-native-PCH-init.patch

@@ -0,0 +1,785 @@
+From 7378cb4fefc87b9a096bb14820a44f26f3a628f5 Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Fri, 6 May 2022 23:43:46 +0200
+Subject: [PATCH 07/26] sb/intel/lynxpoint: Add native PCH init
+
+Implement native PCH initialisation for Lynx Point. This is only needed
+when MRC.bin is not used.
+
+Change-Id: I36867bdc8b20000e44ff9d0d7b2c0d63952bd561
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../haswell/native_raminit/raminit_native.c   |   3 +-
+ src/southbridge/intel/lynxpoint/Makefile.inc  |   1 +
+ .../intel/lynxpoint/early_pch_native.c        | 123 +++++++++
+ .../intel/lynxpoint/hsio/Makefile.inc         |   8 +
+ src/southbridge/intel/lynxpoint/hsio/common.c |  52 ++++
+ src/southbridge/intel/lynxpoint/hsio/hsio.h   |  46 ++++
+ .../intel/lynxpoint/hsio/lpt_h_cx.c           | 244 ++++++++++++++++++
+ .../intel/lynxpoint/hsio/lpt_lp_bx.c          | 180 +++++++++++++
+ src/southbridge/intel/lynxpoint/pch.h         |   6 +
+ 9 files changed, 661 insertions(+), 2 deletions(-)
+ create mode 100644 src/southbridge/intel/lynxpoint/hsio/Makefile.inc
+ create mode 100644 src/southbridge/intel/lynxpoint/hsio/common.c
+ create mode 100644 src/southbridge/intel/lynxpoint/hsio/hsio.h
+ create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
+ create mode 100644 src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+index dd1f1ec14e..b6efb6b40d 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
++++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+@@ -16,8 +16,7 @@ static bool early_init_native(int s3resume)
+ 	/** TODO: CPU replacement check must be skipped in warm boots and S3 resumes **/
+ 	const bool cpu_replaced = !s3resume && intel_early_me_cpu_replacement_check();
+ 
+-	early_thermal_init();
+-	early_usb_init();
++	early_pch_init_native(s3resume);
+ 
+ 	if (!CONFIG(INTEL_LYNXPOINT_LP))
+ 		dmi_early_init();
+diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc
+index a9a9b153d6..63243ecc86 100644
+--- a/src/southbridge/intel/lynxpoint/Makefile.inc
++++ b/src/southbridge/intel/lynxpoint/Makefile.inc
+@@ -38,6 +38,7 @@ romstage-y += early_usb.c early_me.c me_status.c early_pch.c
+ romstage-y += pmutil.c
+ 
+ romstage-$(CONFIG_USE_NATIVE_RAMINIT) += early_pch_native.c early_usb_native.c iobp.c thermal.c
++subdirs-$(CONFIG_USE_NATIVE_RAMINIT) += hsio
+ 
+ ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
+ romstage-y += lp_gpio.c
+diff --git a/src/southbridge/intel/lynxpoint/early_pch_native.c b/src/southbridge/intel/lynxpoint/early_pch_native.c
+index c28ddfcf5d..421821fa5d 100644
+--- a/src/southbridge/intel/lynxpoint/early_pch_native.c
++++ b/src/southbridge/intel/lynxpoint/early_pch_native.c
+@@ -1,10 +1,133 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+ #include <console/console.h>
++#include <device/pci_def.h>
+ #include <device/pci_ops.h>
++#include <southbridge/intel/lynxpoint/hsio/hsio.h>
+ #include <southbridge/intel/lynxpoint/pch.h>
+ #include <types.h>
+ 
++static void early_sata_init(const uint8_t pch_revision)
++{
++	const bool is_mobile = get_pch_platform_type() != PCH_TYPE_DESKTOP;
++
++	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
++	printk(BIOS_DEBUG, "HSIO lane owner: 0x%02x\n", lane_owner);
++
++	/* BWG Step 2 */
++	pci_update_config32(PCH_SATA_DEV, SATA_SCLKG, ~0x1ff, 0x183);
++
++	/* BWG Step 3: Set OOB Retry Mode */
++	pci_or_config16(PCH_SATA_DEV, SATA_PCS, 1 << 15);
++
++	/* BWG Step 4: Program the SATA mPHY tables */
++	if (pch_is_lp()) {
++		if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) {
++			program_hsio_sata_lpt_lp_bx(is_mobile);
++		} else {
++			printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision);
++		}
++	} else {
++		if (pch_revision >= LPT_H_STEP_C0) {
++			program_hsio_sata_lpt_h_cx(is_mobile);
++		} else {
++			printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision);
++		}
++	}
++
++	/** FIXME: Program SATA RxEq tables **/
++
++	/* BWG Step 5 */
++	/** FIXME: Only for desktop and mobile (skip this on workstation and server) **/
++	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(22));
++
++	/* BWG Step 6 */
++	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(19));
++
++	/* BWG Step 7 */
++	pci_update_config32(PCH_SATA_DEV, 0x98, ~(0x3f << 7), 0x04 << 7);
++
++	/* BWG Step 8 */
++	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(20));
++
++	/* BWG Step 9 */
++	pci_update_config32(PCH_SATA_DEV, 0x98, ~(3 << 5), 1 << 5);
++
++	/* BWG Step 10 */
++	pci_or_config32(PCH_SATA_DEV, 0x98, BIT(18));
++
++	/* Enable SATA ports */
++	uint8_t sata_pcs = 0;
++	if (CONFIG(INTEL_LYNXPOINT_LP)) {
++		for (uint8_t i = 0; i < 4; i++) {
++			if ((lane_owner & BIT(7 - i)) == 0) {
++				sata_pcs |= BIT(i);
++			}
++		}
++	} else {
++		sata_pcs |= 0x0f;
++		for (uint8_t i = 4; i < 6; i++) {
++			if ((lane_owner & BIT(i)) == 0) {
++				sata_pcs |= BIT(i);
++			}
++		}
++	}
++	printk(BIOS_DEBUG, "SATA port enables: 0x%02x\n", sata_pcs);
++	pci_or_config8(PCH_SATA_DEV, SATA_PCS, sata_pcs);
++}
++
++void early_pch_init_native(int s3resume)
++{
++	const uint8_t pch_revision = pci_read_config8(PCH_LPC_DEV, PCI_REVISION_ID);
++
++	RCBA16(DISPBDF) = 0x0010;
++	RCBA32_OR(FD2, PCH_ENABLE_DBDF);
++
++	/** FIXME: Check GEN_PMCON_3 and handle RTC failure? **/
++
++	RCBA32(PRSTS) = BIT(4);
++
++	early_sata_init(pch_revision);
++
++	pci_or_config8(PCH_LPC_DEV, 0xa6, 1 << 1);
++	pci_and_config8(PCH_LPC_DEV, 0xdc, ~(1 << 5 | 1 << 1));
++
++	/** TODO: Send GET HSIO VER and update ChipsetInit table? Is it needed? **/
++
++	/** FIXME: GbE handling? **/
++
++	pci_update_config32(PCH_LPC_DEV, 0xac, ~(1 << 20), 0);
++
++	for (uint8_t i = 0; i < 8; i++)
++		pci_update_config32(PCI_DEV(0, 0x1c, i), 0x338, ~(1 << 26), 0);
++
++	pci_update_config8(PCI_DEV(0, 0x1c, 0), 0xf4, ~(3 << 5), 1 << 7);
++
++	pci_update_config8(PCI_DEV(0, 26, 0), 0x88, ~(1 << 2), 0);
++	pci_update_config8(PCI_DEV(0, 29, 0), 0x88, ~(1 << 2), 0);
++
++	/** FIXME: Disable SATA2 device? **/
++
++	if (pch_is_lp()) {
++		if (pch_revision >= LPT_LP_STEP_B0 && pch_revision <= LPT_LP_STEP_B2) {
++			program_hsio_xhci_lpt_lp_bx();
++			program_hsio_igbe_lpt_lp_bx();
++		} else {
++			printk(BIOS_ERR, "Unsupported PCH-LP stepping 0x%02x\n", pch_revision);
++		}
++	} else {
++		if (pch_revision >= LPT_H_STEP_C0) {
++			program_hsio_xhci_lpt_h_cx();
++			program_hsio_igbe_lpt_h_cx();
++		} else {
++			printk(BIOS_ERR, "Unsupported PCH-H stepping 0x%02x\n", pch_revision);
++		}
++	}
++
++	early_thermal_init();
++	early_usb_init();
++}
++
+ void pch_dmi_setup_physical_layer(void)
+ {
+ 	/* FIXME: We need to make sure the SA supports Gen2 as well */
+diff --git a/src/southbridge/intel/lynxpoint/hsio/Makefile.inc b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc
+new file mode 100644
+index 0000000000..6b74997511
+--- /dev/null
++++ b/src/southbridge/intel/lynxpoint/hsio/Makefile.inc
+@@ -0,0 +1,8 @@
++## SPDX-License-Identifier: GPL-2.0-or-later
++
++romstage-y += common.c
++ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
++romstage-y += lpt_lp_bx.c
++else
++romstage-y += lpt_h_cx.c
++endif
+diff --git a/src/southbridge/intel/lynxpoint/hsio/common.c b/src/southbridge/intel/lynxpoint/hsio/common.c
+new file mode 100644
+index 0000000000..9935ca347a
+--- /dev/null
++++ b/src/southbridge/intel/lynxpoint/hsio/common.c
+@@ -0,0 +1,52 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <device/pci_ops.h>
++#include <southbridge/intel/lynxpoint/hsio/hsio.h>
++#include <types.h>
++
++/*
++ * FIXME: Ask Intel whether all lanes need to be programmed as specified
++ * in the PCH BWG. If not, make separate tables and only check this once.
++ */
++void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or)
++{
++	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
++
++	if ((addr & 0xfe00) == 0x2000 && (lane_owner & (1 << 4)))
++		return;
++
++	if ((addr & 0xfe00) == 0x2200 && (lane_owner & (1 << 5)))
++		return;
++
++	if (CONFIG(INTEL_LYNXPOINT_LP)) {
++		if ((addr & 0xfe00) == 0x2400 && (lane_owner & (1 << 6)))
++			return;
++
++		if ((addr & 0xfe00) == 0x2600 && (lane_owner & (1 << 7)))
++			return;
++	}
++	hsio_update(addr, and, or);
++}
++
++/*
++ * FIXME: Ask Intel whether all lanes need to be programmed as specified
++ * in the PCH BWG. If not, make separate tables and only check this once.
++ */
++void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or)
++{
++	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
++	if (CONFIG(INTEL_LYNXPOINT_LP)) {
++		if ((addr & 0xfe00) == 0x2400 && ((lane_owner >> 0) & 3) != 2)
++			return;
++
++		if ((addr & 0xfe00) == 0x2600 && ((lane_owner >> 2) & 3) != 2)
++			return;
++	} else {
++		if ((addr & 0xfe00) == 0x2c00 && ((lane_owner >> 2) & 3) != 2)
++			return;
++
++		if ((addr & 0xfe00) == 0x2e00 && ((lane_owner >> 0) & 3) != 2)
++			return;
++	}
++	hsio_update(addr, and, or);
++}
+diff --git a/src/southbridge/intel/lynxpoint/hsio/hsio.h b/src/southbridge/intel/lynxpoint/hsio/hsio.h
+new file mode 100644
+index 0000000000..689ef4a05b
+--- /dev/null
++++ b/src/southbridge/intel/lynxpoint/hsio/hsio.h
+@@ -0,0 +1,46 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H
++#define SOUTHBRIDGE_INTEL_LYNXPOINT_HSIO_H
++
++#include <southbridge/intel/lynxpoint/iobp.h>
++#include <types.h>
++
++struct hsio_table_row {
++	uint32_t addr;
++	uint32_t and;
++	uint32_t or;
++};
++
++static inline void hsio_update(const uint32_t addr, const uint32_t and, const uint32_t or)
++{
++	pch_iobp_update(addr, and, or);
++}
++
++static inline void hsio_update_row(const struct hsio_table_row row)
++{
++	hsio_update(row.addr, row.and, row.or);
++}
++
++void hsio_xhci_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or);
++void hsio_sata_shared_update(const uint32_t addr, const uint32_t and, const uint32_t or);
++
++static inline void hsio_sata_shared_update_row(const struct hsio_table_row row)
++{
++	hsio_sata_shared_update(row.addr, row.and, row.or);
++}
++
++static inline void hsio_xhci_shared_update_row(const struct hsio_table_row row)
++{
++	hsio_xhci_shared_update(row.addr, row.and, row.or);
++}
++
++void program_hsio_sata_lpt_h_cx(const bool is_mobile);
++void program_hsio_xhci_lpt_h_cx(void);
++void program_hsio_igbe_lpt_h_cx(void);
++
++void program_hsio_sata_lpt_lp_bx(const bool is_mobile);
++void program_hsio_xhci_lpt_lp_bx(void);
++void program_hsio_igbe_lpt_lp_bx(void);
++
++#endif
+diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
+new file mode 100644
+index 0000000000..b5dd402742
+--- /dev/null
++++ b/src/southbridge/intel/lynxpoint/hsio/lpt_h_cx.c
+@@ -0,0 +1,244 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <device/pci_ops.h>
++#include <southbridge/intel/lynxpoint/hsio/hsio.h>
++#include <types.h>
++
++const struct hsio_table_row hsio_sata_shared_lpt_h_cx[] = {
++	{ 0xea002008, ~0xfffc6108, 0xea6c6108 },
++	{ 0xea002208, ~0xfffc6108, 0xea6c6108 },
++	{ 0xea002038, ~0x3f00000f, 0x0700000d },
++	{ 0xea002238, ~0x3f00000f, 0x0700000d },
++	{ 0xea00202c, ~0x00020f00, 0x00020100 },
++	{ 0xea00222c, ~0x00020f00, 0x00020100 },
++	{ 0xea002040, ~0x1f000000, 0x01000000 },
++	{ 0xea002240, ~0x1f000000, 0x01000000 },
++	{ 0xea002010, ~0xffff0000, 0x0d510000 },
++	{ 0xea002210, ~0xffff0000, 0x0d510000 },
++	{ 0xea002018, ~0xffff0300, 0x38250100 },
++	{ 0xea002218, ~0xffff0300, 0x38250100 },
++	{ 0xea002000, ~0xcf030000, 0xcf030000 },
++	{ 0xea002200, ~0xcf030000, 0xcf030000 },
++	{ 0xea002028, ~0xff1f0000, 0x580e0000 },
++	{ 0xea002228, ~0xff1f0000, 0x580e0000 },
++	{ 0xea00201c, ~0x00007c00, 0x00002400 },
++	{ 0xea00221c, ~0x00007c00, 0x00002400 },
++	{ 0xea00208c, ~0x00ff0000, 0x00800000 },
++	{ 0xea00228c, ~0x00ff0000, 0x00800000 },
++	{ 0xea0020a4, ~0x0030ff00, 0x00308300 },
++	{ 0xea0022a4, ~0x0030ff00, 0x00308300 },
++	{ 0xea0020ac, ~0x00000030, 0x00000020 },
++	{ 0xea0022ac, ~0x00000030, 0x00000020 },
++	{ 0xea002140, ~0x00ffffff, 0x00140718 },
++	{ 0xea002340, ~0x00ffffff, 0x00140718 },
++	{ 0xea002144, ~0x00ffffff, 0x00140998 },
++	{ 0xea002344, ~0x00ffffff, 0x00140998 },
++	{ 0xea002148, ~0x00ffffff, 0x00140998 },
++	{ 0xea002348, ~0x00ffffff, 0x00140998 },
++	{ 0xea00217c, ~0x03000000, 0x03000000 },
++	{ 0xea00237c, ~0x03000000, 0x03000000 },
++	{ 0xea002178, ~0x00001f00, 0x00001800 },
++	{ 0xea002378, ~0x00001f00, 0x00001800 },
++	{ 0xea00210c, ~0x0038000f, 0x00000005 },
++	{ 0xea00230c, ~0x0038000f, 0x00000005 },
++};
++
++const struct hsio_table_row hsio_sata_lpt_h_cx[] = {
++	{ 0xea008008, ~0xff000000, 0x1c000000 },
++	{ 0xea002408, ~0xfffc6108, 0xea6c6108 },
++	{ 0xea002608, ~0xfffc6108, 0xea6c6108 },
++	{ 0xea000808, ~0xfffc6108, 0xea6c6108 },
++	{ 0xea000a08, ~0xfffc6108, 0xea6c6108 },
++	{ 0xea002438, ~0x3f00000f, 0x0700000d },
++	{ 0xea002638, ~0x3f00000f, 0x0700000d },
++	{ 0xea000838, ~0x3f00000f, 0x0700000d },
++	{ 0xea000a38, ~0x3f00000f, 0x0700000d },
++	{ 0xea002440, ~0x1f000000, 0x01000000 },
++	{ 0xea002640, ~0x1f000000, 0x01000000 },
++	{ 0xea000840, ~0x1f000000, 0x01000000 },
++	{ 0xea000a40, ~0x1f000000, 0x01000000 },
++	{ 0xea002410, ~0xffff0000, 0x0d510000 },
++	{ 0xea002610, ~0xffff0000, 0x0d510000 },
++	{ 0xea000810, ~0xffff0000, 0x0d510000 },
++	{ 0xea000a10, ~0xffff0000, 0x0d510000 },
++	{ 0xea00242c, ~0x00020800, 0x00020000 },
++	{ 0xea00262c, ~0x00020800, 0x00020000 },
++	{ 0xea00082c, ~0x00020800, 0x00020000 },
++	{ 0xea000a2c, ~0x00020800, 0x00020000 },
++	{ 0xea002418, ~0xffff0300, 0x38250100 },
++	{ 0xea002618, ~0xffff0300, 0x38250100 },
++	{ 0xea000818, ~0xffff0300, 0x38250100 },
++	{ 0xea000a18, ~0xffff0300, 0x38250100 },
++	{ 0xea002400, ~0xcf030000, 0xcf030000 },
++	{ 0xea002600, ~0xcf030000, 0xcf030000 },
++	{ 0xea000800, ~0xcf030000, 0xcf030000 },
++	{ 0xea000a00, ~0xcf030000, 0xcf030000 },
++	{ 0xea002428, ~0xff1f0000, 0x580e0000 },
++	{ 0xea002628, ~0xff1f0000, 0x580e0000 },
++	{ 0xea000828, ~0xff1f0000, 0x580e0000 },
++	{ 0xea000a28, ~0xff1f0000, 0x580e0000 },
++	{ 0xea00241c, ~0x00007c00, 0x00002400 },
++	{ 0xea00261c, ~0x00007c00, 0x00002400 },
++	{ 0xea00081c, ~0x00007c00, 0x00002400 },
++	{ 0xea000a1c, ~0x00007c00, 0x00002400 },
++	{ 0xea00248c, ~0x00ff0000, 0x00800000 },
++	{ 0xea00268c, ~0x00ff0000, 0x00800000 },
++	{ 0xea00088c, ~0x00ff0000, 0x00800000 },
++	{ 0xea000a8c, ~0x00ff0000, 0x00800000 },
++	{ 0xea0024a4, ~0x0030ff00, 0x00308300 },
++	{ 0xea0026a4, ~0x0030ff00, 0x00308300 },
++	{ 0xea0008a4, ~0x0030ff00, 0x00308300 },
++	{ 0xea000aa4, ~0x0030ff00, 0x00308300 },
++	{ 0xea0024ac, ~0x00000030, 0x00000020 },
++	{ 0xea0026ac, ~0x00000030, 0x00000020 },
++	{ 0xea0008ac, ~0x00000030, 0x00000020 },
++	{ 0xea000aac, ~0x00000030, 0x00000020 },
++	{ 0xea002540, ~0x00ffffff, 0x00140718 },
++	{ 0xea002740, ~0x00ffffff, 0x00140718 },
++	{ 0xea000940, ~0x00ffffff, 0x00140718 },
++	{ 0xea000b40, ~0x00ffffff, 0x00140718 },
++	{ 0xea002544, ~0x00ffffff, 0x00140998 },
++	{ 0xea002744, ~0x00ffffff, 0x00140998 },
++	{ 0xea000944, ~0x00ffffff, 0x00140998 },
++	{ 0xea000b44, ~0x00ffffff, 0x00140998 },
++	{ 0xea002548, ~0x00ffffff, 0x00140998 },
++	{ 0xea002748, ~0x00ffffff, 0x00140998 },
++	{ 0xea000948, ~0x00ffffff, 0x00140998 },
++	{ 0xea000b48, ~0x00ffffff, 0x00140998 },
++	{ 0xea00257c, ~0x03000000, 0x03000000 },
++	{ 0xea00277c, ~0x03000000, 0x03000000 },
++	{ 0xea00097c, ~0x03000000, 0x03000000 },
++	{ 0xea000b7c, ~0x03000000, 0x03000000 },
++	{ 0xea002578, ~0x00001f00, 0x00001800 },
++	{ 0xea002778, ~0x00001f00, 0x00001800 },
++	{ 0xea000978, ~0x00001f00, 0x00001800 },
++	{ 0xea000b78, ~0x00001f00, 0x00001800 },
++	{ 0xea00250c, ~0x0038000f, 0x00000005 },
++	{ 0xea00270c, ~0x0038000f, 0x00000005 },
++	{ 0xea00090c, ~0x0038000f, 0x00000005 },
++	{ 0xea000b0c, ~0x0038000f, 0x00000005 },
++};
++
++const struct hsio_table_row hsio_xhci_shared_lpt_h_cx[] = {
++	{ 0xe9002c2c, ~0x00000700, 0x00000100 },
++	{ 0xe9002e2c, ~0x00000700, 0x00000100 },
++	{ 0xe9002dcc, ~0x00001407, 0x00001407 },
++	{ 0xe9002fcc, ~0x00001407, 0x00001407 },
++	{ 0xe9002d68, ~0x01000f3c, 0x00000a28 },
++	{ 0xe9002f68, ~0x01000f3c, 0x00000a28 },
++	{ 0xe9002d6c, ~0x000000ff, 0x0000003f },
++	{ 0xe9002f6c, ~0x000000ff, 0x0000003f },
++	{ 0xe9002d4c, ~0x00ffff00, 0x00120500 },
++	{ 0xe9002f4c, ~0x00ffff00, 0x00120500 },
++	{ 0xe9002d14, ~0x38000700, 0x00000100 },
++	{ 0xe9002f14, ~0x38000700, 0x00000100 },
++	{ 0xe9002d64, ~0x0000f000, 0x00005000 },
++	{ 0xe9002f64, ~0x0000f000, 0x00005000 },
++	{ 0xe9002d70, ~0x00000018, 0x00000000 },
++	{ 0xe9002f70, ~0x00000018, 0x00000000 },
++	{ 0xe9002c38, ~0x3f00000f, 0x0700000b },
++	{ 0xe9002e38, ~0x3f00000f, 0x0700000b },
++	{ 0xe9002d40, ~0x00800000, 0x00000000 },
++	{ 0xe9002f40, ~0x00800000, 0x00000000 },
++};
++
++const struct hsio_table_row hsio_xhci_lpt_h_cx[] = {
++	{ 0xe90031cc, ~0x00001407, 0x00001407 },
++	{ 0xe90033cc, ~0x00001407, 0x00001407 },
++	{ 0xe90015cc, ~0x00001407, 0x00001407 },
++	{ 0xe90017cc, ~0x00001407, 0x00001407 },
++	{ 0xe9003168, ~0x01000f3c, 0x00000a28 },
++	{ 0xe9003368, ~0x01000f3c, 0x00000a28 },
++	{ 0xe9001568, ~0x01000f3c, 0x00000a28 },
++	{ 0xe9001768, ~0x01000f3c, 0x00000a28 },
++	{ 0xe900316c, ~0x000000ff, 0x0000003f },
++	{ 0xe900336c, ~0x000000ff, 0x0000003f },
++	{ 0xe900156c, ~0x000000ff, 0x0000003f },
++	{ 0xe900176c, ~0x000000ff, 0x0000003f },
++	{ 0xe900314c, ~0x00ffff00, 0x00120500 },
++	{ 0xe900334c, ~0x00ffff00, 0x00120500 },
++	{ 0xe900154c, ~0x00ffff00, 0x00120500 },
++	{ 0xe900174c, ~0x00ffff00, 0x00120500 },
++	{ 0xe9003114, ~0x38000700, 0x00000100 },
++	{ 0xe9003314, ~0x38000700, 0x00000100 },
++	{ 0xe9001514, ~0x38000700, 0x00000100 },
++	{ 0xe9001714, ~0x38000700, 0x00000100 },
++	{ 0xe9003164, ~0x0000f000, 0x00005000 },
++	{ 0xe9003364, ~0x0000f000, 0x00005000 },
++	{ 0xe9001564, ~0x0000f000, 0x00005000 },
++	{ 0xe9001764, ~0x0000f000, 0x00005000 },
++	{ 0xe9003170, ~0x00000018, 0x00000000 },
++	{ 0xe9003370, ~0x00000018, 0x00000000 },
++	{ 0xe9001570, ~0x00000018, 0x00000000 },
++	{ 0xe9001770, ~0x00000018, 0x00000000 },
++	{ 0xe9003038, ~0x3f00000f, 0x0700000b },
++	{ 0xe9003238, ~0x3f00000f, 0x0700000b },
++	{ 0xe9001438, ~0x3f00000f, 0x0700000b },
++	{ 0xe9001638, ~0x3f00000f, 0x0700000b },
++	{ 0xe9003140, ~0x00800000, 0x00000000 },
++	{ 0xe9003340, ~0x00800000, 0x00000000 },
++	{ 0xe9001540, ~0x00800000, 0x00000000 },
++	{ 0xe9001740, ~0x00800000, 0x00000000 },
++};
++
++void program_hsio_sata_lpt_h_cx(const bool is_mobile)
++{
++	const struct hsio_table_row *pch_hsio_table;
++	size_t len;
++
++	pch_hsio_table = hsio_sata_lpt_h_cx;
++	len = ARRAY_SIZE(hsio_sata_lpt_h_cx);
++	for (size_t i = 0; i < len; i++)
++		hsio_update_row(pch_hsio_table[i]);
++
++	pch_hsio_table = hsio_sata_shared_lpt_h_cx;
++	len = ARRAY_SIZE(hsio_sata_shared_lpt_h_cx);
++	for (size_t i = 0; i < len; i++)
++		hsio_sata_shared_update_row(pch_hsio_table[i]);
++
++	const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67;
++
++	hsio_update(0xea002490, ~0x0000ffff, hsio_sata_value);
++	hsio_update(0xea002690, ~0x0000ffff, hsio_sata_value);
++	hsio_update(0xea000890, ~0x0000ffff, hsio_sata_value);
++	hsio_update(0xea000a90, ~0x0000ffff, hsio_sata_value);
++
++	hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value);
++	hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value);
++}
++
++void program_hsio_xhci_lpt_h_cx(void)
++{
++	const struct hsio_table_row *pch_hsio_table;
++	size_t len;
++
++	pch_hsio_table = hsio_xhci_lpt_h_cx;
++	len = ARRAY_SIZE(hsio_xhci_lpt_h_cx);
++
++	for (size_t i = 0; i < len; i++)
++		hsio_update_row(pch_hsio_table[i]);
++
++	pch_hsio_table = hsio_xhci_shared_lpt_h_cx;
++	len = ARRAY_SIZE(hsio_xhci_shared_lpt_h_cx);
++
++	for (size_t i = 0; i < len; i++)
++		hsio_xhci_shared_update_row(pch_hsio_table[i]);
++}
++
++void program_hsio_igbe_lpt_h_cx(void)
++{
++	const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc);
++	if (!(strpfusecfg1 & (1 << 19)))
++		return;
++
++	const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7;
++	const uint8_t lane_owner = pci_read_config8(PCI_DEV(0, 0x1c, 0), 0x410);
++	if (gbe_port == 0 && ((lane_owner >> 0) & 3) != 1)
++		return;
++
++	if (gbe_port == 1 && ((lane_owner >> 2) & 3) != 1)
++		return;
++
++	const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x2e - 2 * gbe_port) << 8;
++	hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100);
++}
+diff --git a/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
+new file mode 100644
+index 0000000000..24679e791a
+--- /dev/null
++++ b/src/southbridge/intel/lynxpoint/hsio/lpt_lp_bx.c
+@@ -0,0 +1,180 @@
++/* SPDX-License-Identifier: GPL-2.0-or-later */
++
++#include <device/pci_ops.h>
++#include <southbridge/intel/lynxpoint/iobp.h>
++#include <southbridge/intel/lynxpoint/hsio/hsio.h>
++#include <types.h>
++
++const struct hsio_table_row hsio_sata_shared_lpt_lp_bx[] = {
++	{ 0xea008008, ~0xff000000, 0x1c000000 },
++	{ 0xea002008, ~0xfffc6108, 0xea6c6108 },
++	{ 0xea002208, ~0xfffc6108, 0xea6c6108 },
++	{ 0xea002408, ~0xfffc6108, 0xea6c6108 },
++	{ 0xea002608, ~0xfffc6108, 0xea6c6108 },
++	{ 0xea002038, ~0x0000000f, 0x0000000d },
++	{ 0xea002238, ~0x0000000f, 0x0000000d },
++	{ 0xea002438, ~0x0000000f, 0x0000000d },
++	{ 0xea002638, ~0x0000000f, 0x0000000d },
++	{ 0xea00202c, ~0x00020f00, 0x00020100 },
++	{ 0xea00222c, ~0x00020f00, 0x00020100 },
++	{ 0xea00242c, ~0x00020f00, 0x00020100 },
++	{ 0xea00262c, ~0x00020f00, 0x00020100 },
++	{ 0xea002040, ~0x1f000000, 0x01000000 },
++	{ 0xea002240, ~0x1f000000, 0x01000000 },
++	{ 0xea002440, ~0x1f000000, 0x01000000 },
++	{ 0xea002640, ~0x1f000000, 0x01000000 },
++	{ 0xea002010, ~0xffff0000, 0x55510000 },
++	{ 0xea002210, ~0xffff0000, 0x55510000 },
++	{ 0xea002410, ~0xffff0000, 0x55510000 },
++	{ 0xea002610, ~0xffff0000, 0x55510000 },
++	{ 0xea002140, ~0x00ffffff, 0x00140718 },
++	{ 0xea002340, ~0x00ffffff, 0x00140718 },
++	{ 0xea002540, ~0x00ffffff, 0x00140718 },
++	{ 0xea002740, ~0x00ffffff, 0x00140718 },
++	{ 0xea002144, ~0x00ffffff, 0x00140998 },
++	{ 0xea002344, ~0x00ffffff, 0x00140998 },
++	{ 0xea002544, ~0x00ffffff, 0x00140998 },
++	{ 0xea002744, ~0x00ffffff, 0x00140998 },
++	{ 0xea002148, ~0x00ffffff, 0x00140998 },
++	{ 0xea002348, ~0x00ffffff, 0x00140998 },
++	{ 0xea002548, ~0x00ffffff, 0x00140998 },
++	{ 0xea002748, ~0x00ffffff, 0x00140998 },
++	{ 0xea00217c, ~0x03000000, 0x03000000 },
++	{ 0xea00237c, ~0x03000000, 0x03000000 },
++	{ 0xea00257c, ~0x03000000, 0x03000000 },
++	{ 0xea00277c, ~0x03000000, 0x03000000 },
++	{ 0xea00208c, ~0x00ff0000, 0x00800000 },
++	{ 0xea00228c, ~0x00ff0000, 0x00800000 },
++	{ 0xea00248c, ~0x00ff0000, 0x00800000 },
++	{ 0xea00268c, ~0x00ff0000, 0x00800000 },
++	{ 0xea0020a4, ~0x0030ff00, 0x00308300 },
++	{ 0xea0022a4, ~0x0030ff00, 0x00308300 },
++	{ 0xea0024a4, ~0x0030ff00, 0x00308300 },
++	{ 0xea0026a4, ~0x0030ff00, 0x00308300 },
++	{ 0xea0020ac, ~0x00000030, 0x00000020 },
++	{ 0xea0022ac, ~0x00000030, 0x00000020 },
++	{ 0xea0024ac, ~0x00000030, 0x00000020 },
++	{ 0xea0026ac, ~0x00000030, 0x00000020 },
++	{ 0xea002018, ~0xffff0300, 0x38250100 },
++	{ 0xea002218, ~0xffff0300, 0x38250100 },
++	{ 0xea002418, ~0xffff0300, 0x38250100 },
++	{ 0xea002618, ~0xffff0300, 0x38250100 },
++	{ 0xea002000, ~0xcf030000, 0xcf030000 },
++	{ 0xea002200, ~0xcf030000, 0xcf030000 },
++	{ 0xea002400, ~0xcf030000, 0xcf030000 },
++	{ 0xea002600, ~0xcf030000, 0xcf030000 },
++	{ 0xea002028, ~0xff1f0000, 0x580e0000 },
++	{ 0xea002228, ~0xff1f0000, 0x580e0000 },
++	{ 0xea002428, ~0xff1f0000, 0x580e0000 },
++	{ 0xea002628, ~0xff1f0000, 0x580e0000 },
++	{ 0xea00201c, ~0x00007c00, 0x00002400 },
++	{ 0xea00221c, ~0x00007c00, 0x00002400 },
++	{ 0xea00241c, ~0x00007c00, 0x00002400 },
++	{ 0xea00261c, ~0x00007c00, 0x00002400 },
++	{ 0xea002178, ~0x00001f00, 0x00001800 },
++	{ 0xea002378, ~0x00001f00, 0x00001800 },
++	{ 0xea002578, ~0x00001f00, 0x00001800 },
++	{ 0xea002778, ~0x00001f00, 0x00001800 },
++	{ 0xea00210c, ~0x0038000f, 0x00000005 },
++	{ 0xea00230c, ~0x0038000f, 0x00000005 },
++	{ 0xea00250c, ~0x0038000f, 0x00000005 },
++	{ 0xea00270c, ~0x0038000f, 0x00000005 },
++};
++
++const struct hsio_table_row hsio_xhci_shared_lpt_lp_bx[] = {
++	{ 0xe90025cc, ~0x00001407, 0x00001407 },
++	{ 0xe90027cc, ~0x00001407, 0x00001407 },
++	{ 0xe9002568, ~0x01000f3c, 0x00000a28 },
++	{ 0xe9002768, ~0x01000f3c, 0x00000a28 },
++	{ 0xe900242c, ~0x00000700, 0x00000100 },
++	{ 0xe900262c, ~0x00000700, 0x00000100 },
++	{ 0xe900256c, ~0x000000ff, 0x0000003f },
++	{ 0xe900276c, ~0x000000ff, 0x0000003f },
++	{ 0xe900254c, ~0x00ffff00, 0x00120500 },
++	{ 0xe900274c, ~0x00ffff00, 0x00120500 },
++	{ 0xe9002564, ~0x0000f000, 0x00005000 },
++	{ 0xe9002764, ~0x0000f000, 0x00005000 },
++	{ 0xe9002570, ~0x00000018, 0x00000000 },
++	{ 0xe9002770, ~0x00000018, 0x00000000 },
++	{ 0xe9002514, ~0x38000700, 0x00000100 },
++	{ 0xe9002714, ~0x38000700, 0x00000100 },
++	{ 0xe9002438, ~0x0000000f, 0x0000000b },
++	{ 0xe9002638, ~0x0000000f, 0x0000000b },
++	{ 0xe9002414, ~0x0000fe00, 0x00006600 },
++	{ 0xe9002614, ~0x0000fe00, 0x00006600 },
++	{ 0xe9002540, ~0x00800000, 0x00000000 },
++	{ 0xe9002740, ~0x00800000, 0x00000000 },
++};
++
++const struct hsio_table_row hsio_xhci_lpt_lp_bx[] = {
++	{ 0xe90021cc, ~0x00001407, 0x00001407 },
++	{ 0xe90023cc, ~0x00001407, 0x00001407 },
++	{ 0xe9002168, ~0x01000f3c, 0x00000a28 },
++	{ 0xe9002368, ~0x01000f3c, 0x00000a28 },
++	{ 0xe900216c, ~0x000000ff, 0x0000003f },
++	{ 0xe900236c, ~0x000000ff, 0x0000003f },
++	{ 0xe900214c, ~0x00ffff00, 0x00120500 },
++	{ 0xe900234c, ~0x00ffff00, 0x00120500 },
++	{ 0xe9002164, ~0x0000f000, 0x00005000 },
++	{ 0xe9002364, ~0x0000f000, 0x00005000 },
++	{ 0xe9002170, ~0x00000018, 0x00000000 },
++	{ 0xe9002370, ~0x00000018, 0x00000000 },
++	{ 0xe9002114, ~0x38000700, 0x00000100 },
++	{ 0xe9002314, ~0x38000700, 0x00000100 },
++	{ 0xe9002038, ~0x0000000f, 0x0000000b },
++	{ 0xe9002238, ~0x0000000f, 0x0000000b },
++	{ 0xe9002014, ~0x0000fe00, 0x00006600 },
++	{ 0xe9002214, ~0x0000fe00, 0x00006600 },
++	{ 0xe9002140, ~0x00800000, 0x00000000 },
++	{ 0xe9002340, ~0x00800000, 0x00000000 },
++};
++
++void program_hsio_sata_lpt_lp_bx(const bool is_mobile)
++{
++	const struct hsio_table_row *pch_hsio_table;
++	size_t len;
++
++	pch_hsio_table = hsio_sata_shared_lpt_lp_bx;
++	len = ARRAY_SIZE(hsio_sata_shared_lpt_lp_bx);
++	for (size_t i = 0; i < len; i++)
++		hsio_sata_shared_update_row(pch_hsio_table[i]);
++
++	const uint32_t hsio_sata_value = is_mobile ? 0x00004c5a : 0x00003e67;
++
++	hsio_sata_shared_update(0xea002090, ~0x0000ffff, hsio_sata_value);
++	hsio_sata_shared_update(0xea002290, ~0x0000ffff, hsio_sata_value);
++	hsio_sata_shared_update(0xea002490, ~0x0000ffff, hsio_sata_value);
++	hsio_sata_shared_update(0xea002690, ~0x0000ffff, hsio_sata_value);
++}
++
++void program_hsio_xhci_lpt_lp_bx(void)
++{
++	const struct hsio_table_row *pch_hsio_table;
++	size_t len;
++
++	pch_hsio_table = hsio_xhci_lpt_lp_bx;
++	len = ARRAY_SIZE(hsio_xhci_lpt_lp_bx);
++
++	for (size_t i = 0; i < len; i++)
++		hsio_update_row(pch_hsio_table[i]);
++
++	pch_hsio_table = hsio_xhci_shared_lpt_lp_bx;
++	len = ARRAY_SIZE(hsio_xhci_shared_lpt_lp_bx);
++
++	for (size_t i = 0; i < len; i++)
++		hsio_xhci_shared_update_row(pch_hsio_table[i]);
++}
++
++void program_hsio_igbe_lpt_lp_bx(void)
++{
++	const uint32_t strpfusecfg1 = pci_read_config32(PCI_DEV(0, 0x1c, 0), 0xfc);
++	if (!(strpfusecfg1 & (1 << 19)))
++		return;
++
++	const uint8_t gbe_port = (strpfusecfg1 >> 16) & 0x7;
++	if (gbe_port > 5)
++		return;
++
++	const uint32_t gbe_hsio_base = 0xe900 << 16 | (0x08 + 2 * gbe_port) << 8;
++	hsio_update(gbe_hsio_base + 0x08, ~0xf0000100, 0xe0000100);
++}
+diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h
+index 38a9349220..74b4d50017 100644
+--- a/src/southbridge/intel/lynxpoint/pch.h
++++ b/src/southbridge/intel/lynxpoint/pch.h
+@@ -117,6 +117,7 @@ void pch_dmi_setup_physical_layer(void);
+ void pch_dmi_tc_vc_mapping(u32 vc0, u32 vc1, u32 vcp, u32 vcm);
+ void early_usb_init(void);
+ void early_thermal_init(void);
++void early_pch_init_native(int s3resume);
+ 
+ void usb_ehci_sleep_prepare(pci_devfn_t dev, u8 slp_typ);
+ void usb_ehci_disable(pci_devfn_t dev);
+@@ -271,6 +272,10 @@ void mainboard_config_rcba(void);
+ #define   IDE_DECODE_ENABLE	(1 << 15)
+ #define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
+ 
++#define SATA_MAP		0x90
++#define SATA_PCS		0x92
++#define SATA_SCLKG		0x94
++
+ #define SATA_SIRI		0xa0 /* SATA Indexed Register Index */
+ #define SATA_SIRD		0xa4 /* SATA Indexed Register Data */
+ #define SATA_SP			0xd0 /* Scratchpad */
+@@ -580,6 +585,7 @@ void mainboard_config_rcba(void);
+ #define D19IR		0x3168	/* 16bit */
+ #define ACPIIRQEN	0x31e0	/* 32bit */
+ #define OIC		0x31fe	/* 16bit */
++#define PRSTS		0x3310	/* 32bit */
+ #define PMSYNC_CONFIG	0x33c4	/* 32bit */
+ #define PMSYNC_CONFIG2	0x33cc	/* 32bit */
+ #define SOFT_RESET_CTRL 0x38f4
+-- 
+2.39.2
+