mirror of
https://codeberg.org/libreboot/lbmk.git
synced 2026-07-11 14:02:52 +02:00
Compare commits
2 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 Leah Rowe
|
80118a24b8 | ||
|
Leah Rowe
|
fcf27a5719 |
+2
-17
@@ -1,9 +1,8 @@
|
||||
*~
|
||||
*.o
|
||||
/cache/
|
||||
/lbmk.err.log
|
||||
/repo/
|
||||
/docs/
|
||||
/cbutils/
|
||||
/pciroms/
|
||||
/util/dell-flash-unlock/dell_flash_unlock
|
||||
/TODO
|
||||
@@ -24,23 +23,9 @@
|
||||
/push
|
||||
/version
|
||||
/versiondate
|
||||
/.version
|
||||
/.versiondate
|
||||
/vendorfiles/
|
||||
*me.bin
|
||||
*sch5545ec.bin
|
||||
/mrc/
|
||||
/util/nvmutil/nvm
|
||||
/src/
|
||||
/CHANGELOG
|
||||
/todo.txt
|
||||
/lock
|
||||
/hash/
|
||||
/dump/
|
||||
/qrun*.sh
|
||||
*.tar.*
|
||||
/m
|
||||
/f
|
||||
/r
|
||||
/e
|
||||
/xbmkpath/
|
||||
/xbmkwd/
|
||||
|
||||
@@ -1,57 +1,123 @@
|
||||
Libreboot
|
||||
=========
|
||||
|
||||
Documentation: [libreboot.org](https://libreboot.org)\
|
||||
Support: [\#libreboot](https://web.libera.chat/#libreboot) on
|
||||
[Libera](https://libera.chat/) IRC
|
||||
Find libreboot documentation at <https://libreboot.org/>
|
||||
|
||||
Libreboot provides
|
||||
[libre](https://libreboot.org/freedom-status.html)
|
||||
boot firmware on
|
||||
[supported motherboards](https://libreboot.org/docs/install/#which-systems-are-supported-by-libreboot). It replaces proprietary vendor BIOS/UEFI implementations, by
|
||||
* Using coreboot to initialize the hardware (e.g. memory controller, CPU, etc.) while
|
||||
minimizing unwanted functionality (e.g. backdoors such as the Intel Management Engine)
|
||||
* ... which runs a payload such as SeaBIOS, GRUB, or U-Boot
|
||||
* ... which loads your operating system's boot loader (BSD and Linux-based
|
||||
[systems](systems) are supported).
|
||||
The `libreboot` project provides
|
||||
[libre](https://libreboot.org/freedom-status.html) *boot
|
||||
firmware* that initializes the hardware (e.g. memory controller, CPU,
|
||||
peripherals) on specific Intel/AMD x86 and ARM targets, which
|
||||
then starts a bootloader for your operating system. Linux/BSD are
|
||||
well-supported. It replaces proprietary BIOS/UEFI firmware. Help is available
|
||||
via [\#libreboot IRC](https://web.libera.chat/#libreboot)
|
||||
on [Libera](https://libera.chat/) IRC.
|
||||
|
||||
Why use Libreboot, and what is coreboot?
|
||||
----------------------------------------
|
||||
Why use Libreboot?
|
||||
==================
|
||||
|
||||
A lot of users who use libre operating systems still use proprietary boot
|
||||
firmware, which often contain backdoors and bugs, hampering
|
||||
[user freedom](https://writefreesoftware.org) and
|
||||
[right to repair](https://www.eff.org/issues/right-to-repair).
|
||||
Why should you use *libreboot*?
|
||||
----------------------------
|
||||
|
||||
[coreboot](https://coreboot.org) provides libre boot firmware by initializing
|
||||
the hardware then running a payload. However, coreboot is notoriously difficult
|
||||
to configure and install for most non-technical users, requiring detailed
|
||||
technical knowledge of hardware.
|
||||
Libreboot gives you freedoms that you otherwise can't get with most other
|
||||
boot firmware. It's extremely powerful and configurable for many use cases.
|
||||
|
||||
Libreboot solves this by being **a coreboot distribution** (in the same way
|
||||
that Alpine Linux is a Linux distribution). It provides a fully automated build
|
||||
system that downloads and compiles pre-configured ROM images for supported
|
||||
motherboards, so end-users could easily fetch images to flash onto their
|
||||
devices.
|
||||
You have rights. The right to privacy, freedom of thought, freedom of speech
|
||||
and the right to read. In this context, Libreboot gives you these rights.
|
||||
Your freedom matters.
|
||||
[Right to repair](https://vid.puffyan.us/watch?v=Npd_xDuNi9k) matters.
|
||||
Many people use proprietary (non-libre)
|
||||
boot firmware, even if they use [a libre OS](https://www.openbsd.org/).
|
||||
Proprietary firmware often contains backdoors (more info on the FAQ), and it
|
||||
and can be buggy. The libreboot project was founded in December 2013,
|
||||
with the express purpose of making coreboot firmware accessible for
|
||||
non-technical users.
|
||||
|
||||
Libreboot also produces documentation aimed at non-technical users and
|
||||
excellent user support via IRC.
|
||||
The `libreboot` project uses [coreboot](https://www.coreboot.org/) for [hardware
|
||||
initialisation](https://doc.coreboot.org/getting_started/architecture.html).
|
||||
Coreboot is notoriously difficult to install for most non-technical users; it
|
||||
handles only basic initialization and jumps to a separate
|
||||
[payload](https://doc.coreboot.org/payloads.html) program (e.g.
|
||||
[GRUB](https://www.gnu.org/software/grub/),
|
||||
[Tianocore](https://www.tianocore.org/)), which must also be configured.
|
||||
*The libreboot software solves this problem*; it is a *coreboot distribution* with
|
||||
an automated build system (named *lbmk*) that builds complete *ROM images*, for
|
||||
more robust installation. Documentation is provided.
|
||||
|
||||
Contribute
|
||||
----------
|
||||
How does Libreboot differ from coreboot?
|
||||
========================================
|
||||
|
||||
In the same way that *Debian* is a GNU+Linux distribution, `libreboot` is
|
||||
a *coreboot distribution*. If you want to build a ROM image from scratch, you
|
||||
otherwise have to perform expert-level configuration of coreboot, GRUB and
|
||||
whatever other software you need, to prepare the ROM image. With *libreboot*,
|
||||
you can literally download from Git or a source archive, and run `make`, and it
|
||||
will build entire ROM images. An automated build system, named `lbmk`
|
||||
(Libreboot MaKe), builds these ROM images automatically, without any user input
|
||||
or intervention required. Configuration has already been performed in advance.
|
||||
|
||||
If you were to build regular coreboot, without using libreboot's automated
|
||||
build system, it would require a lot more intervention and decent technical
|
||||
knowledge to produce a working configuration.
|
||||
|
||||
Regular binary releases of `libreboot` provide these
|
||||
ROM images pre-compiled, and you can simply install them, with no special
|
||||
knowledge or skill except the ability to follow installation instructions
|
||||
and run commands BSD/Linux.
|
||||
|
||||
Project goals
|
||||
=============
|
||||
|
||||
- *Support as much hardware as possible!* Libreboot aims to eventually
|
||||
have *maintainers* for every board supported by coreboot, at every
|
||||
point in time.
|
||||
- *Make coreboot easy to use*. Coreboot is notoriously difficult
|
||||
to install, due to an overall lack of user-focused documentation
|
||||
and support. Most people will simply give up before attempting to
|
||||
install coreboot. Libreboot's automated build system and user-friendly
|
||||
installation instructions solves this problem.
|
||||
|
||||
Libreboot attempts to bridge this divide by providing a build system
|
||||
automating much of the coreboot image creation and customization.
|
||||
Secondly, the project produces documentation aimed at non-technical users.
|
||||
Thirdly, the project attempts to provide excellent user support via IRC.
|
||||
|
||||
Libreboot already comes with a payload (GRUB), flashrom and other
|
||||
needed parts. Everything is fully integrated, in a way where most of
|
||||
the complicated steps that are otherwise required, are instead done
|
||||
for the user in advance.
|
||||
|
||||
You can download ROM images for your libreboot system and install
|
||||
them without having to build anything from source. If, however, you are
|
||||
interested in building your own image, the build system makes it relatively
|
||||
easy to do so.
|
||||
|
||||
Not a coreboot fork!
|
||||
--------------------
|
||||
|
||||
Libreboot is not a fork of coreboot. Every so often, the project
|
||||
re-bases on the latest version of coreboot, with the number of custom
|
||||
patches in use minimized. Tested, *stable* (static) releases are then provided
|
||||
in Libreboot, based on specific coreboot revisions.
|
||||
|
||||
How to help
|
||||
===========
|
||||
|
||||
You can check bugs listed on
|
||||
the [bug tracker](https://codeberg.org/libreboot/lbmk/issues).
|
||||
|
||||
You may use Codeberg pull requests to send patches with bug fixes or other
|
||||
improvements. This repository hosts the code for the main build system.
|
||||
The website lives in [a separate repository](https://codeberg.org/libreboot/lbwww).
|
||||
If you spot a bug and have a fix, the website has instructions for how to send
|
||||
patches, and you can also report it. Also, this entire website is
|
||||
written in Markdown and hosted in a [separate
|
||||
repository](https://codeberg.org/libreboot/lbwww) where you can send patches.
|
||||
|
||||
Development is also done on the IRC channel.
|
||||
Any and all development discussion and user support are all done on the IRC
|
||||
channel. More information is on https://libreboot.org/contact.html.
|
||||
|
||||
License for this README
|
||||
-----------------------
|
||||
LICENSE FOR THIS README
|
||||
=======================
|
||||
|
||||
It's just a README file. It is released under
|
||||
[Creative Commons Zero, version 1.0](https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt).
|
||||
It's just a README file. This README file is released under the terms of the
|
||||
Creative Commons Zero license, version 1.0 of the license, which you can
|
||||
read here:
|
||||
|
||||
<https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt>
|
||||
|
||||
@@ -0,0 +1,165 @@
|
||||
#!/usr/bin/env sh
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
# SPDX-FileCopyrightText: 2014,2015,2020,2021,2023 Leah Rowe <leah@libreboot.org>
|
||||
# SPDX-FileCopyrightText: 2015 Patrick "P. J." McDermott <pj@pehjota.net>
|
||||
# SPDX-FileCopyrightText: 2015, 2016 Klemens Nanni <contact@autoboot.org>
|
||||
# SPDX-FileCopyrightText: 2022, Caleb La Grange <thonkpeasant@protonmail.com>
|
||||
|
||||
[ "x${DEBUG+set}" = 'xset' ] && set -v
|
||||
set -u -e
|
||||
|
||||
export LC_COLLATE=C
|
||||
export LC_ALL=C
|
||||
|
||||
. "include/err.sh"
|
||||
. "include/option.sh"
|
||||
|
||||
eval "$(setvars "" option aur_notice tmpdir)"
|
||||
|
||||
tmpdir_was_set="y"
|
||||
set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n"
|
||||
if [ "${tmpdir_was_set}" = "y" ]; then
|
||||
tmpdir="${TMPDIR##*/}"
|
||||
tmpdir="${TMPDIR%_*}"
|
||||
if [ "${tmpdir}" = "lbmk" ]; then
|
||||
tmpdir=""
|
||||
tmpdir_was_set="n"
|
||||
fi
|
||||
fi
|
||||
if [ "${tmpdir_was_set}" = "n" ]; then
|
||||
export TMPDIR="/tmp"
|
||||
tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)"
|
||||
export TMPDIR="${tmpdir}"
|
||||
else
|
||||
export TMPDIR="${TMPDIR}"
|
||||
fi
|
||||
tmpdir="${TMPDIR}"
|
||||
|
||||
linkpath="${0}"
|
||||
linkname="${linkpath##*/}"
|
||||
buildpath="./script/${linkname}"
|
||||
|
||||
main()
|
||||
{
|
||||
xx_ id -u 1>/dev/null 2>/dev/null
|
||||
[ $# -lt 1 ] && fail "Too few arguments. Try: ${0} help"
|
||||
if [ "${1}" = "dependencies" ]; then
|
||||
xx_ install_packages $@
|
||||
lbmk_exit 0
|
||||
fi
|
||||
|
||||
initialise_command $@ && shift 1
|
||||
|
||||
check_git
|
||||
check_project "fail"
|
||||
git_init
|
||||
|
||||
execute_command $@
|
||||
lbmk_exit 0
|
||||
}
|
||||
|
||||
initialise_command()
|
||||
{
|
||||
[ "$(id -u)" != "0" ] || fail "this command as root is not permitted"
|
||||
|
||||
check_project
|
||||
|
||||
case "${1}" in
|
||||
help)
|
||||
usage ${0}
|
||||
lbmk_exit 0 ;;
|
||||
list)
|
||||
items "${buildpath}"
|
||||
lbmk_exit 0 ;;
|
||||
version)
|
||||
mkversion
|
||||
lbmk_exit 0 ;;
|
||||
esac
|
||||
option="${1}"
|
||||
}
|
||||
|
||||
install_packages()
|
||||
{
|
||||
if [ $# -lt 2 ]; then
|
||||
printf "You must specify a distro, namely:\n" 1>&2
|
||||
printf "Look at files under config/dependencies/\n" 1>&2
|
||||
printf "Example: ./build dependencies debian\n" 1>&2
|
||||
fail "install_packages: target not specified"
|
||||
fi
|
||||
|
||||
[ -f "config/dependencies/${2}" ] || fail "Unsupported target"
|
||||
|
||||
. "config/dependencies/${2}"
|
||||
|
||||
xx_ ${pkg_add} ${pkglist}
|
||||
[ -z "${aur_notice}" ] && return 0
|
||||
printf "You must install AUR packages: %s\n" "${aur_notice}" 1>&2
|
||||
}
|
||||
|
||||
# release archives contain .gitignore, but not .git.
|
||||
# lbmk can be run from lbmk.git, or an archive.
|
||||
git_init()
|
||||
{
|
||||
[ -L ".git" ] && fail "Reference .git is a symlink"
|
||||
[ -e ".git" ] && return 0
|
||||
eval "$(setvars "$(date -Rd @${versiondate})" cdate _nogit)"
|
||||
|
||||
git init || fail "${PWD}: cannot initialise Git repository"
|
||||
git add -A . || fail "${PWD}: cannot add files to Git repository"
|
||||
git commit -m "${projectname} ${version}" --date "${cdate}" \
|
||||
--author="lbmk <lbmk@libreboot.org>" || \
|
||||
fail "${PWD}: can't commit ${projectname}/${version}, date ${cdate}"
|
||||
git tag -a "${version}" -m "${projectname} ${version}" || \
|
||||
fail "${PWD}: cannot git-tag ${projectname}/${version}"
|
||||
}
|
||||
|
||||
execute_command()
|
||||
{
|
||||
lbmkcmd="${buildpath}/${option}"
|
||||
[ -f "${lbmkcmd}" ] || fail "Invalid command. Run: ${linkpath} help"
|
||||
"${lbmkcmd}" $@ || fail "execute_command: ${lbmkcmd} ${@}"
|
||||
}
|
||||
|
||||
usage()
|
||||
{
|
||||
progname=${0}
|
||||
cat <<- EOF
|
||||
$(mkversion)
|
||||
|
||||
USAGE: ${progname} <OPTION>
|
||||
|
||||
possible values for 'OPTION':
|
||||
$(items "${buildpath}")
|
||||
|
||||
To know what ${projectname} version you're on, type:
|
||||
${progname} version
|
||||
|
||||
Refer to ${projectname} documentation for more info.
|
||||
EOF
|
||||
}
|
||||
|
||||
mkversion()
|
||||
{
|
||||
printf "revision: %s %s\n" "${projectname}" "${version}"
|
||||
printf "revision date: %s\n" "$(date -Rud @${versiondate})"
|
||||
}
|
||||
|
||||
lbmk_exit()
|
||||
{
|
||||
tmp_cleanup || err "lbmk_exit: can't rm tmpdir upon exit $1: ${tmpdir}"
|
||||
exit $1
|
||||
}
|
||||
|
||||
fail()
|
||||
{
|
||||
tmp_cleanup || printf "WARNING: can't rm tmpdir: %s\n" "${tmpdir}" 1>&2
|
||||
err "${1}"
|
||||
}
|
||||
|
||||
tmp_cleanup()
|
||||
{
|
||||
[ "${tmpdir_was_set}" = "n" ] || return 0
|
||||
rm -Rf "${tmpdir}" || return 1
|
||||
}
|
||||
|
||||
main $@
|
||||
+231
-250
@@ -6,23 +6,20 @@
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
CONFIG_OPTION_BACKEND_NONE=y
|
||||
# CONFIG_USE_OPTION_TABLE is not set
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
@@ -33,10 +30,11 @@ CONFIG_USE_BLOBS=y
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_CBMEM_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
@@ -54,43 +52,37 @@ CONFIG_TSEG_STAGE_CACHE=y
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
CONFIG_VENDOR_APPLE=y
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
CONFIG_VENDOR_ASUS=y
|
||||
# CONFIG_VENDOR_BAP is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_ELMEX is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GIZMOSPHERE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_JETWAY is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_LIPPERT is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
@@ -100,87 +92,110 @@ CONFIG_VENDOR_APPLE=y
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SCALEWAY is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="MacBook2,1"
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="A88XM-E"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="apple/i945_macs"
|
||||
CONFIG_VGA_BIOS_ID="8086,27a2"
|
||||
CONFIG_MAINBOARD_DIR="asus/a88xm-e"
|
||||
CONFIG_VGA_BIOS_ID="1002,9996"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Apple"
|
||||
CONFIG_CBFS_SIZE=0x01000000
|
||||
CONFIG_MAX_CPUS=2
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_MAINBOARD_VENDOR="ASUS"
|
||||
CONFIG_CBFS_SIZE=0x00800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=4
|
||||
CONFIG_ONBOARD_VGA_IS_PRIMARY=y
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_VARIANT_DIR="macbook2_1"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_EFS_SPI_READ_MODE=2
|
||||
CONFIG_EFS_SPI_SPEED=1
|
||||
CONFIG_EFS_SPI_MICRON_FLAG=0
|
||||
CONFIG_NORMAL_READ_SPI_SPEED=1
|
||||
CONFIG_ALT_SPI_SPEED=1
|
||||
CONFIG_TPM_SPI_SPEED=1
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_BOARD_APPLE_MACBOOK11 is not set
|
||||
CONFIG_BOARD_APPLE_MACBOOK21=y
|
||||
# CONFIG_BOARD_APPLE_IMAC52 is not set
|
||||
# CONFIG_BOARD_APPLE_MACBOOKAIR4_2 is not set
|
||||
CONFIG_BOARD_APPLE_I945_MACS_COMMON=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Apple Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_IRQ_SLOT_COUNT=11
|
||||
CONFIG_HW_MEM_HOLE_SIZEK=0x200000
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_HUDSON_LEGACY_FREE is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
CONFIG_VGA_BIOS=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="ASUS"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="MacBook2,1"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_BOARD_ASUS_A88XM_E=y
|
||||
# CONFIG_BOARD_ASUS_AM1I_A is not set
|
||||
# CONFIG_BOARD_ASUS_F2A85_M is not set
|
||||
# CONFIG_BOARD_ASUS_F2A85_M_PRO is not set
|
||||
# CONFIG_BOARD_ASUS_F2A85_M_LE is not set
|
||||
# CONFIG_BOARD_ASUS_H61M_CS is not set
|
||||
# CONFIG_BOARD_ASUS_P8H61_M_LX is not set
|
||||
# CONFIG_BOARD_ASUS_P8H61_M_LX3_R2_0 is not set
|
||||
# CONFIG_BOARD_ASUS_P8H61_M_PRO is not set
|
||||
# CONFIG_BOARD_ASUS_P8H61_M_PRO_CM6630 is not set
|
||||
# CONFIG_BOARD_ASUS_MAXIMUS_IV_GENE_Z is not set
|
||||
# CONFIG_BOARD_ASUS_P2B is not set
|
||||
# CONFIG_BOARD_ASUS_P2B_D is not set
|
||||
# CONFIG_BOARD_ASUS_P2B_DS is not set
|
||||
# CONFIG_BOARD_ASUS_P2B_F is not set
|
||||
# CONFIG_BOARD_ASUS_P2B_LS is not set
|
||||
# CONFIG_BOARD_ASUS_P3B_F is not set
|
||||
# CONFIG_BOARD_ASUS_P5GC_MX is not set
|
||||
# CONFIG_BOARD_ASUS_P5QC is not set
|
||||
# CONFIG_BOARD_ASUS_P5Q_PRO is not set
|
||||
# CONFIG_BOARD_ASUS_P5QL_PRO is not set
|
||||
# CONFIG_BOARD_ASUS_P5Q_SE is not set
|
||||
# CONFIG_BOARD_ASUS_P5Q is not set
|
||||
# CONFIG_BOARD_ASUS_P5QL_EM is not set
|
||||
# CONFIG_BOARD_ASUS_P5QPL_AM is not set
|
||||
# CONFIG_BOARD_ASUS_P5G41T_M_LX is not set
|
||||
# CONFIG_BOARD_ASUS_P8C_WS is not set
|
||||
# CONFIG_BOARD_ASUS_P8H77_V is not set
|
||||
# CONFIG_BOARD_ASUS_P8Z77_M_PRO is not set
|
||||
# CONFIG_BOARD_ASUS_P8Z77_V_LX2 is not set
|
||||
# CONFIG_BOARD_ASUS_P8Z77_V is not set
|
||||
# CONFIG_BOARD_ASUS_P8Z77_M is not set
|
||||
# CONFIG_HUDSON_XHCI_FWM is not set
|
||||
# CONFIG_HUDSON_XHCI_ENABLE is not set
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0x30000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x10000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xF8000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_VGA_BIOS_FILE="../../../pciroms/pci1002,9996.rom"
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="A88XM-E"
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_HEAP_SIZE=0xc0000
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
@@ -188,25 +203,16 @@ CONFIG_BOARD_ROMSIZE_KB_2048=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=16384
|
||||
CONFIG_ROM_SIZE=0x01000000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=8192
|
||||
CONFIG_ROM_SIZE=0x00800000
|
||||
# end of Mainboard
|
||||
|
||||
CONFIG_SYSTEM_TYPE_LAPTOP=y
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
@@ -214,172 +220,145 @@ CONFIG_SYSTEM_TYPE_LAPTOP=y
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_ARCH_ALL_STAGES_X86=y
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
# CONFIG_VGA_BIOS_SECOND is not set
|
||||
CONFIG_ACPI_CPU_STRING="\\_SB.CP%02d"
|
||||
CONFIG_BOTTOMIO_POSITION=0x80000000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_AHCI_ROM_ID="1022,7801"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_VBT_DATA_SIZE_KB=8
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
CONFIG_TTYS0_LCS=3
|
||||
CONFIG_UART_PCI_ADDR=0x0
|
||||
CONFIG_SOC_AMD_COMMON=y
|
||||
CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO=y
|
||||
CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO_BIOSRAM=y
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
# CONFIG_TOP_SWAP_REDUNDANCY is not set
|
||||
CONFIG_SOC_AMD_COMMON_BLOCK_PCI_MMCONF=y
|
||||
# CONFIG_SOC_AMD_COMMON_BLOCK_SPI_DEBUG is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6EX=y
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_M=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_CPU_AMD_AGESA=y
|
||||
CONFIG_UDELAY_LAPIC_FIXED_FSB=200
|
||||
# CONFIG_ENABLE_MRC_CACHE is not set
|
||||
CONFIG_CPU_AMD_AGESA_FAMILY15_TN=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_LEGACY_SMP_INIT=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_UDELAY_LAPIC=y
|
||||
CONFIG_LAPIC_MONOTONIC_TIMER=y
|
||||
CONFIG_UNKNOWN_TSC_RATE=y
|
||||
CONFIG_TSC_SYNC_LFENCE=y
|
||||
CONFIG_LOGICAL_CPUS=y
|
||||
CONFIG_SMM_ASEG=y
|
||||
CONFIG_X86_AMD_FIXED_MTRRS=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_I945=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM=y
|
||||
CONFIG_I945_LVDS=y
|
||||
CONFIG_NORTHBRIDGE_AMD_AGESA=y
|
||||
CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_SOUTHBRIDGE_AMD_AGESA_HUDSON=y
|
||||
CONFIG_SOUTHBRIDGE_SPECIFIC_OPTIONS=y
|
||||
CONFIG_HUDSON_SATA_MODE=2
|
||||
|
||||
#
|
||||
# AHCI
|
||||
#
|
||||
# CONFIG_HUDSON_AHCI_ROM is not set
|
||||
CONFIG_ACPI_ENABLE_THERMAL_ZONE=y
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_ITE_COMMON_PRE_RAM=y
|
||||
CONFIG_SUPERIO_ITE_ENV_CTRL=y
|
||||
CONFIG_SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG=y
|
||||
CONFIG_SUPERIO_ITE_ENV_CTRL_8BIT_PWM=y
|
||||
CONFIG_SUPERIO_ITE_ENV_CTRL_PWM_FREQ2=y
|
||||
CONFIG_SUPERIO_ITE_ENV_CTRL_5FANS=y
|
||||
CONFIG_SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG=y
|
||||
CONFIG_SUPERIO_ITE_ENV_CTRL_EXT_ANY_TMPIN=y
|
||||
CONFIG_SUPERIO_ITE_IT8728F=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_EC_ACPI=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
|
||||
#
|
||||
# AMD Platform Initialization
|
||||
#
|
||||
# CONFIG_CPU_AMD_AGESA_BINARY_PI is not set
|
||||
CONFIG_CPU_AMD_AGESA_OPENSOURCE=y
|
||||
CONFIG_IDS_OPTIONS_HOOKED_UP=y
|
||||
CONFIG_IDS_ENABLED=y
|
||||
|
||||
#
|
||||
# Warning: IDS options may not work. Enable at your own risk!
|
||||
#
|
||||
# CONFIG_IDS_CONTROL_ENABLED is not set
|
||||
# CONFIG_IDS_PERF_ANALYSIS is not set
|
||||
# CONFIG_IDS_TRACING_ENABLED is not set
|
||||
CONFIG_CPU_AMD_AGESA_OPENSOURCE_MEM_JEDEC=y
|
||||
# CONFIG_CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_1 is not set
|
||||
# CONFIG_CPU_AMD_AGESA_OPENSOURCE_MEM_XMP_2 is not set
|
||||
# CONFIG_CPU_AMD_AGESA_OPENSOURCE_MEM_CUSTOM is not set
|
||||
# CONFIG_AGESA_EXTRA_TIMESTAMPS is not set
|
||||
# end of AMD Platform Initialization
|
||||
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_NUM_IPI_STARTS=2
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_HAVE_CF9_RESET_PREPARE=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
CONFIG_VGA_ROM_RUN_DEFAULT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_NO_GFX_INIT=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
@@ -387,28 +366,22 @@ CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
# CONFIG_INTEL_GMA_ADD_VBT is not set
|
||||
# CONFIG_VGA_BIOS_DGPU is not set
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
CONFIG_RESOURCE_ALLOCATOR_V3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
@@ -417,34 +390,31 @@ CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
CONFIG_DRIVERS_AMD_PI=y
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
|
||||
CONFIG_INTEL_GMA_OPREGION_2_0=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
CONFIG_USE_PC_CMOS_ALTCENTURY=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
@@ -466,18 +436,8 @@ CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -485,18 +445,12 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
@@ -508,12 +462,27 @@ CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
@@ -538,15 +507,17 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_GFXUMA=y
|
||||
CONFIG_HAVE_MP_TABLE=y
|
||||
CONFIG_HAVE_PIRQ_TABLE=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_MP_TABLE=y
|
||||
CONFIG_GENERATE_PIRQ_TABLE=y
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
@@ -554,6 +525,32 @@ CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# CONFIG_PAYLOAD_ELF is not set
|
||||
# CONFIG_PAYLOAD_BOOTBOOT is not set
|
||||
# CONFIG_PAYLOAD_FILO is not set
|
||||
# CONFIG_PAYLOAD_GRUB2 is not set
|
||||
# CONFIG_PAYLOAD_SEAGRUB is not set
|
||||
# CONFIG_PAYLOAD_LINUXBOOT is not set
|
||||
# CONFIG_PAYLOAD_SEABIOS is not set
|
||||
# CONFIG_PAYLOAD_UBOOT is not set
|
||||
# CONFIG_PAYLOAD_YABITS is not set
|
||||
# CONFIG_PAYLOAD_EDK2 is not set
|
||||
# CONFIG_PAYLOAD_LINUX is not set
|
||||
CONFIG_PAYLOAD_OPTIONS=""
|
||||
# CONFIG_PXE is not set
|
||||
# CONFIG_COMPRESS_SECONDARY_PAYLOAD is not set
|
||||
|
||||
#
|
||||
# Secondary Payloads
|
||||
#
|
||||
# CONFIG_COREINFO_SECONDARY_PAYLOAD is not set
|
||||
# CONFIG_GRUB2_SECONDARY_PAYLOAD is not set
|
||||
# CONFIG_MEMTEST_SECONDARY_PAYLOAD is not set
|
||||
# CONFIG_NVRAMCUI_SECONDARY_PAYLOAD is not set
|
||||
# CONFIG_SEABIOS_SECONDARY_PAYLOAD is not set
|
||||
# CONFIG_TINT_SECONDARY_PAYLOAD is not set
|
||||
# CONFIG_COREDOOM_SECONDARY_PAYLOAD is not set
|
||||
# end of Secondary Payloads
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
@@ -565,10 +562,6 @@ CONFIG_PAYLOAD_NONE=y
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
@@ -576,33 +569,21 @@ CONFIG_PAYLOAD_NONE=y
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_PIRQ is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,8 @@
|
||||
tree="default"
|
||||
romtype="normal"
|
||||
arch="x86_64"
|
||||
payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_seabios_grubonly="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="ahci"
|
||||
@@ -1,665 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="intel/d510mo"
|
||||
CONFIG_VGA_BIOS_ID="8086,a001"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Intel"
|
||||
CONFIG_CBFS_SIZE=0x00100000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
|
||||
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
|
||||
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
|
||||
|
||||
#
|
||||
# Coffeelake RVP
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
|
||||
CONFIG_BOARD_INTEL_D510MO=y
|
||||
# CONFIG_BOARD_INTEL_D945GCLF is not set
|
||||
# CONFIG_BOARD_INTEL_DCP847SKE is not set
|
||||
# CONFIG_BOARD_INTEL_DG41WV is not set
|
||||
# CONFIG_BOARD_INTEL_DG43GT is not set
|
||||
# CONFIG_BOARD_INTEL_DQ67SW is not set
|
||||
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
|
||||
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
|
||||
# CONFIG_BOARD_INTEL_GLKRVP is not set
|
||||
# CONFIG_BOARD_INTEL_HARCUVAR is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
|
||||
# CONFIG_BOARD_INTEL_LEAFHILL is not set
|
||||
# CONFIG_BOARD_INTEL_MINNOW3 is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_PANTHERLAKE_CRB is not set
|
||||
|
||||
#
|
||||
# Ptlrvp
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_PTLRVP is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
|
||||
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
|
||||
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
|
||||
# CONFIG_BOARD_INTEL_STRAGO is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
|
||||
# CONFIG_BOARD_INTEL_WTM2 is not set
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=32
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=1024
|
||||
CONFIG_ROM_SIZE=0x00100000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x80000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
# CONFIG_TOP_SWAP_REDUNDANCY is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_106CX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_CPU_HAS_L2_ENABLE_MSR=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM=y
|
||||
CONFIG_SUPERIO_WINBOND_W83627THG=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,8 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_memtest="y"
|
||||
release="n"
|
||||
build_depend="seabios/default memtest86plus"
|
||||
@@ -1,665 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="intel/d510mo"
|
||||
CONFIG_VGA_BIOS_ID="8086,a001"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Intel"
|
||||
CONFIG_CBFS_SIZE=0x01000000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
|
||||
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
|
||||
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
|
||||
|
||||
#
|
||||
# Coffeelake RVP
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
|
||||
CONFIG_BOARD_INTEL_D510MO=y
|
||||
# CONFIG_BOARD_INTEL_D945GCLF is not set
|
||||
# CONFIG_BOARD_INTEL_DCP847SKE is not set
|
||||
# CONFIG_BOARD_INTEL_DG41WV is not set
|
||||
# CONFIG_BOARD_INTEL_DG43GT is not set
|
||||
# CONFIG_BOARD_INTEL_DQ67SW is not set
|
||||
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
|
||||
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
|
||||
# CONFIG_BOARD_INTEL_GLKRVP is not set
|
||||
# CONFIG_BOARD_INTEL_HARCUVAR is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
|
||||
# CONFIG_BOARD_INTEL_LEAFHILL is not set
|
||||
# CONFIG_BOARD_INTEL_MINNOW3 is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_PANTHERLAKE_CRB is not set
|
||||
|
||||
#
|
||||
# Ptlrvp
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_PTLRVP is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
|
||||
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
|
||||
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
|
||||
# CONFIG_BOARD_INTEL_STRAGO is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
|
||||
# CONFIG_BOARD_INTEL_WTM2 is not set
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=32
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=16384
|
||||
CONFIG_ROM_SIZE=0x01000000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x80000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
# CONFIG_TOP_SWAP_REDUNDANCY is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_106CX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_CPU_HAS_L2_ENABLE_MSR=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM=y
|
||||
CONFIG_SUPERIO_WINBOND_W83627THG=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,8 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
release="n"
|
||||
@@ -1,664 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="intel/d945gclf"
|
||||
CONFIG_VGA_BIOS_ID="8086,2772"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Intel"
|
||||
CONFIG_CBFS_SIZE=0x00080000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_IRQ_SLOT_COUNT=18
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
|
||||
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
|
||||
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
|
||||
|
||||
#
|
||||
# Coffeelake RVP
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_D510MO is not set
|
||||
CONFIG_BOARD_INTEL_D945GCLF=y
|
||||
# CONFIG_BOARD_INTEL_DCP847SKE is not set
|
||||
# CONFIG_BOARD_INTEL_DG41WV is not set
|
||||
# CONFIG_BOARD_INTEL_DG43GT is not set
|
||||
# CONFIG_BOARD_INTEL_DQ67SW is not set
|
||||
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
|
||||
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
|
||||
# CONFIG_BOARD_INTEL_GLKRVP is not set
|
||||
# CONFIG_BOARD_INTEL_HARCUVAR is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
|
||||
# CONFIG_BOARD_INTEL_LEAFHILL is not set
|
||||
# CONFIG_BOARD_INTEL_MINNOW3 is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_PANTHERLAKE_CRB is not set
|
||||
|
||||
#
|
||||
# Ptlrvp
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_PTLRVP is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
|
||||
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
|
||||
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
|
||||
# CONFIG_BOARD_INTEL_STRAGO is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
|
||||
# CONFIG_BOARD_INTEL_WTM2 is not set
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=512
|
||||
CONFIG_ROM_SIZE=0x00080000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
# CONFIG_TOP_SWAP_REDUNDANCY is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_106CX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_441=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_I945=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_LPC47M15X=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
CONFIG_HAVE_MP_TABLE=y
|
||||
CONFIG_HAVE_PIRQ_TABLE=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_MP_TABLE=y
|
||||
CONFIG_GENERATE_PIRQ_TABLE=y
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
# CONFIG_DEBUG_PIRQ is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,7 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
release="n"
|
||||
build_depend="seabios/default"
|
||||
@@ -1,664 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="intel/d945gclf"
|
||||
CONFIG_VGA_BIOS_ID="8086,2772"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Intel"
|
||||
CONFIG_CBFS_SIZE=0x00800000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_IRQ_SLOT_COUNT=18
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
|
||||
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
|
||||
# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
|
||||
|
||||
#
|
||||
# Coffeelake RVP
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_D510MO is not set
|
||||
CONFIG_BOARD_INTEL_D945GCLF=y
|
||||
# CONFIG_BOARD_INTEL_DCP847SKE is not set
|
||||
# CONFIG_BOARD_INTEL_DG41WV is not set
|
||||
# CONFIG_BOARD_INTEL_DG43GT is not set
|
||||
# CONFIG_BOARD_INTEL_DQ67SW is not set
|
||||
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
|
||||
# CONFIG_BOARD_INTEL_FROST_CREEK is not set
|
||||
# CONFIG_BOARD_INTEL_GLKRVP is not set
|
||||
# CONFIG_BOARD_INTEL_HARCUVAR is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
|
||||
# CONFIG_BOARD_INTEL_LEAFHILL is not set
|
||||
# CONFIG_BOARD_INTEL_MINNOW3 is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_PANTHERLAKE_CRB is not set
|
||||
|
||||
#
|
||||
# Ptlrvp
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_PTLRVP is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
|
||||
# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
|
||||
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
|
||||
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
|
||||
# CONFIG_BOARD_INTEL_STRAGO is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
|
||||
# CONFIG_BOARD_INTEL_WTM2 is not set
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=8192
|
||||
CONFIG_ROM_SIZE=0x00800000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
# CONFIG_TOP_SWAP_REDUNDANCY is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_106CX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_441=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_I945=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_LPC47M15X=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
CONFIG_HAVE_MP_TABLE=y
|
||||
CONFIG_HAVE_PIRQ_TABLE=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_MP_TABLE=y
|
||||
CONFIG_GENERATE_PIRQ_TABLE=y
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
# CONFIG_DEBUG_PIRQ is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,8 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
release="n"
|
||||
build_depend="seabios/default grub/default"
|
||||
@@ -1,18 +0,0 @@
|
||||
3rdparty/fsp/EagleStreamFspBinPkg
|
||||
3rdparty/fsp/MeteorLakeFspBinPkg
|
||||
3rdparty/fsp/IceLakeFspBinPkg
|
||||
3rdparty/fsp/AmberLakeFspBinPkg
|
||||
3rdparty/fsp/DenvertonNSFspBinPkg
|
||||
3rdparty/fsp/TigerLakeFspBinPkg
|
||||
3rdparty/fsp/CedarIslandFspBinPkg
|
||||
3rdparty/fsp/ElkhartLakeFspBinPkg
|
||||
3rdparty/fsp/CometLakeFspBinPkg
|
||||
3rdparty/fsp/WhitleyFspBinPkg
|
||||
3rdparty/fsp/ArrowLakeFspBinPkg
|
||||
3rdparty/fsp/IdavilleFspBinPkg
|
||||
3rdparty/fsp/BraswellFspBinPkg
|
||||
3rdparty/fsp/CoffeeLakeFspBinPkg
|
||||
3rdparty/fsp/RaptorLakeFspBinPkg
|
||||
3rdparty/fsp/ApolloLakeFspBinPkg
|
||||
3rdparty/fsp/SkylakeFspBinPkg
|
||||
3rdparty/vboot/tests
|
||||
@@ -1,68 +0,0 @@
|
||||
From b6cbef6dc28cfe5c376310391a7bc0869ea5ffdb Mon Sep 17 00:00:00 2001
|
||||
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
|
||||
Date: Wed, 27 Oct 2021 13:36:01 +0200
|
||||
Subject: [PATCH 01/51] add c3 and clockgen to apple/macbook21
|
||||
|
||||
---
|
||||
src/mainboard/apple/i945_macs/Kconfig | 1 +
|
||||
src/mainboard/apple/i945_macs/cstates.c | 13 +++++++++++++
|
||||
src/mainboard/apple/i945_macs/devicetree.cb | 6 ++++++
|
||||
3 files changed, 20 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/apple/i945_macs/Kconfig b/src/mainboard/apple/i945_macs/Kconfig
|
||||
index 42774e484a..cd5155e81a 100644
|
||||
--- a/src/mainboard/apple/i945_macs/Kconfig
|
||||
+++ b/src/mainboard/apple/i945_macs/Kconfig
|
||||
@@ -20,6 +20,7 @@ config BOARD_APPLE_MACBOOK11
|
||||
bool
|
||||
select BOARD_APPLE_I945_MACS_COMMON
|
||||
select I945_LVDS
|
||||
+ select DRIVERS_I2C_CK505
|
||||
|
||||
config BOARD_APPLE_MACBOOK21
|
||||
bool
|
||||
diff --git a/src/mainboard/apple/i945_macs/cstates.c b/src/mainboard/apple/i945_macs/cstates.c
|
||||
index 13d06f0839..88b8669c61 100644
|
||||
--- a/src/mainboard/apple/i945_macs/cstates.c
|
||||
+++ b/src/mainboard/apple/i945_macs/cstates.c
|
||||
@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = {
|
||||
.addrh = 0,
|
||||
}
|
||||
},
|
||||
+ {
|
||||
+ .ctype = 3,
|
||||
+ .latency = 17,
|
||||
+ .power = 250,
|
||||
+ .resource = {
|
||||
+ .space_id = ACPI_ADDRESS_SPACE_FIXED,
|
||||
+ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
|
||||
+ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
|
||||
+ .access_size = ACPI_ACCESS_SIZE_UNDEFINED,
|
||||
+ .addrl = 0x20,
|
||||
+ .addrh = 0,
|
||||
+ }
|
||||
+ },
|
||||
};
|
||||
|
||||
int get_cst_entries(const acpi_cstate_t **entries)
|
||||
diff --git a/src/mainboard/apple/i945_macs/devicetree.cb b/src/mainboard/apple/i945_macs/devicetree.cb
|
||||
index b17f8ae529..18731b067f 100644
|
||||
--- a/src/mainboard/apple/i945_macs/devicetree.cb
|
||||
+++ b/src/mainboard/apple/i945_macs/devicetree.cb
|
||||
@@ -89,7 +89,13 @@ chip northbridge/intel/i945
|
||||
end
|
||||
device pci 1f.3 on # SMBUS
|
||||
subsystemid 0x8086 0x7270
|
||||
+ chip drivers/i2c/ck505
|
||||
+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }"
|
||||
+ register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }"
|
||||
+ device i2c 69 on end
|
||||
+ end
|
||||
end
|
||||
+
|
||||
end
|
||||
end
|
||||
end
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-1097
File diff suppressed because it is too large
Load Diff
@@ -1,34 +0,0 @@
|
||||
From c1fd80b55e3ab8f651c2ad6e6eec6cdcb3922f9b Mon Sep 17 00:00:00 2001
|
||||
From: persmule <persmule@gmail.com>
|
||||
Date: Sun, 31 Oct 2021 23:33:26 +0000
|
||||
Subject: [PATCH 03/51] lenovo/t400: Enable all SATA ports
|
||||
|
||||
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
|
||||
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
|
||||
chassis, and another one on its dock.
|
||||
|
||||
They have to be unmasked via device tree to use.
|
||||
|
||||
This patch unmasked all SATA ports found within t400s with factory firmware.
|
||||
---
|
||||
src/mainboard/lenovo/t400/devicetree.cb | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
|
||||
index 9e056772e9..9361f330d2 100644
|
||||
--- a/src/mainboard/lenovo/t400/devicetree.cb
|
||||
+++ b/src/mainboard/lenovo/t400/devicetree.cb
|
||||
@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
|
||||
register "gpe0_en" = "0x01000000"
|
||||
register "gpi1_routing" = "2"
|
||||
|
||||
- # Set AHCI mode, enable ports 1 and 2.
|
||||
- register "sata_port_map" = "0x03"
|
||||
+ # Set AHCI mode, enable ports 1, 2, 5 and 6.
|
||||
+ register "sata_port_map" = "0x33"
|
||||
register "sata_clock_request" = "0"
|
||||
register "sata_traffic_monitor" = "0"
|
||||
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-37
@@ -1,37 +0,0 @@
|
||||
From bf1bb17d48b43ca468bca0b2d31315450f8cf8c6 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 3 Jan 2022 19:06:22 +0000
|
||||
Subject: [PATCH 04/51] lenovo/x230: set me_state=Disabled in cmos.default
|
||||
|
||||
I only recently found out about this. It's possible to use me_cleaner to
|
||||
do the same thing, but some people might just flash coreboot and not do
|
||||
anything with the ME region
|
||||
|
||||
With this change, the ME is set to disabled. It's my understanding that this
|
||||
will accomplish more or less the same thing as me_cleaner, without actually
|
||||
using that. Of course, I still recommend using me_cleaner
|
||||
|
||||
I saw this when I audited coreboot's git history, and saw this:
|
||||
|
||||
commit 833e9bad4762e0dca6c867d3a18dbaf6d5166be8
|
||||
Author: Evgeny Zinoviev <me@ch1p.io>
|
||||
Date: Thu Nov 21 21:47:31 2019 +0300
|
||||
|
||||
sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode
|
||||
---
|
||||
src/mainboard/lenovo/x230/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
|
||||
index 732e214b32..8454f0eac0 100644
|
||||
--- a/src/mainboard/lenovo/x230/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x230/cmos.default
|
||||
@@ -17,4 +17,4 @@ trackpoint=Enable
|
||||
backlight=Both
|
||||
usb_always_on=Disable
|
||||
f1_to_f12_as_primary=Enable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-124
@@ -1,124 +0,0 @@
|
||||
From c0b5b390507c1a46af3224bd61f5c971e99607a2 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Wed, 2 Mar 2022 21:50:01 +0000
|
||||
Subject: [PATCH 05/51] set me_state=Disabled on all cmos.default files!
|
||||
|
||||
yeah. why the hell isn't this the default
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/lenovo/l520/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t420/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t420s/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t430/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t430s/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t520/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t530/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/x220/cmos.default | 2 +-
|
||||
src/mainboard/protectli/vault_cml/cmos.default | 2 +-
|
||||
src/mainboard/system76/tgl-u/cmos.default | 2 +-
|
||||
10 files changed, 10 insertions(+), 10 deletions(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
|
||||
index be08e0a342..b8970efa46 100644
|
||||
--- a/src/mainboard/lenovo/l520/cmos.default
|
||||
+++ b/src/mainboard/lenovo/l520/cmos.default
|
||||
@@ -16,4 +16,4 @@ sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
backlight=Both
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
|
||||
index 6fd26c5fe3..27a62d07b3 100644
|
||||
--- a/src/mainboard/lenovo/t420/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t420/cmos.default
|
||||
@@ -16,4 +16,4 @@ sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
|
||||
index 6fd26c5fe3..27a62d07b3 100644
|
||||
--- a/src/mainboard/lenovo/t420s/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t420s/cmos.default
|
||||
@@ -16,4 +16,4 @@ sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
|
||||
index 4857f92f67..ab1be1a678 100644
|
||||
--- a/src/mainboard/lenovo/t430/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t430/cmos.default
|
||||
@@ -17,4 +17,4 @@ trackpoint=Enable
|
||||
backlight=Both
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
|
||||
index 286fb0ae8c..5a05c73721 100644
|
||||
--- a/src/mainboard/lenovo/t430s/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t430s/cmos.default
|
||||
@@ -18,4 +18,4 @@ backlight=Both
|
||||
enable_dual_graphics=Disable
|
||||
usb_always_on=Disable
|
||||
f1_to_f12_as_primary=Enable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
|
||||
index 4857f92f67..ab1be1a678 100644
|
||||
--- a/src/mainboard/lenovo/t520/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t520/cmos.default
|
||||
@@ -17,4 +17,4 @@ trackpoint=Enable
|
||||
backlight=Both
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
|
||||
index 4857f92f67..ab1be1a678 100644
|
||||
--- a/src/mainboard/lenovo/t530/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t530/cmos.default
|
||||
@@ -17,4 +17,4 @@ trackpoint=Enable
|
||||
backlight=Both
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
|
||||
index ef706c1303..b318ab9772 100644
|
||||
--- a/src/mainboard/lenovo/x220/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x220/cmos.default
|
||||
@@ -15,4 +15,4 @@ usb_always_on=Disable
|
||||
fn_ctrl_swap=Disable
|
||||
sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
|
||||
index d61046df6b..8c793fd1c3 100644
|
||||
--- a/src/mainboard/protectli/vault_cml/cmos.default
|
||||
+++ b/src/mainboard/protectli/vault_cml/cmos.default
|
||||
@@ -2,4 +2,4 @@
|
||||
|
||||
boot_option=Fallback
|
||||
debug_level=Debug
|
||||
-me_state=Enable
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
|
||||
index d61046df6b..8c793fd1c3 100644
|
||||
--- a/src/mainboard/system76/tgl-u/cmos.default
|
||||
+++ b/src/mainboard/system76/tgl-u/cmos.default
|
||||
@@ -2,4 +2,4 @@
|
||||
|
||||
boot_option=Fallback
|
||||
debug_level=Debug
|
||||
-me_state=Enable
|
||||
+me_state=Disabled
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-207
@@ -1,207 +0,0 @@
|
||||
From 75892a195d53054ceee67e23c487c4103f559332 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sun, 19 Feb 2023 18:21:43 +0000
|
||||
Subject: [PATCH 06/51] util/ifdtool: add --nuke flag (all 0xFF on region)
|
||||
|
||||
When this option is used, the region's contents are overwritten
|
||||
with all ones (0xFF).
|
||||
|
||||
Example:
|
||||
|
||||
./ifdtool --nuke gbe coreboot.rom
|
||||
./ifdtool --nuke bios coreboot.com
|
||||
./ifdtool --nuke me coreboot.com
|
||||
|
||||
Rebased since the last revision update in lbmk.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/ifdtool/ifdtool.c | 116 +++++++++++++++++++++++++++++------------
|
||||
1 file changed, 84 insertions(+), 32 deletions(-)
|
||||
|
||||
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
|
||||
index 0b75db54bd..7f0c10bd0b 100644
|
||||
--- a/util/ifdtool/ifdtool.c
|
||||
+++ b/util/ifdtool/ifdtool.c
|
||||
@@ -2252,6 +2252,7 @@ static void print_usage(const char *name)
|
||||
" tgl - Tiger Lake\n"
|
||||
" wbg - Wellsburg\n"
|
||||
" -S | --setpchstrap Write a PCH strap\n"
|
||||
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
|
||||
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
|
||||
" -T | --topswapsize Set the Top Swap Block Size PCH strap value\n"
|
||||
" Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n"
|
||||
@@ -2263,6 +2264,60 @@ static void print_usage(const char *name)
|
||||
"\n");
|
||||
}
|
||||
|
||||
+static int
|
||||
+get_region_type_string(const char *region_type_string)
|
||||
+{
|
||||
+ if (!strcasecmp("Descriptor", region_type_string))
|
||||
+ return 0;
|
||||
+ else if (!strcasecmp("BIOS", region_type_string))
|
||||
+ return 1;
|
||||
+ else if (!strcasecmp("ME", region_type_string))
|
||||
+ return 2;
|
||||
+ else if (!strcasecmp("GbE", region_type_string))
|
||||
+ return 3;
|
||||
+ else if (!strcasecmp("Platform Data", region_type_string))
|
||||
+ return 4;
|
||||
+ else if (!strcasecmp("Device Exp1", region_type_string))
|
||||
+ return 5;
|
||||
+ else if (!strcasecmp("Secondary BIOS", region_type_string))
|
||||
+ return 6;
|
||||
+ else if (!strcasecmp("Reserved", region_type_string))
|
||||
+ return 7;
|
||||
+ else if (!strcasecmp("EC", region_type_string))
|
||||
+ return 8;
|
||||
+ else if (!strcasecmp("Device Exp2", region_type_string))
|
||||
+ return 9;
|
||||
+ else if (!strcasecmp("IE", region_type_string))
|
||||
+ return 10;
|
||||
+ else if (!strcasecmp("10GbE_0", region_type_string))
|
||||
+ return 11;
|
||||
+ else if (!strcasecmp("10GbE_1", region_type_string))
|
||||
+ return 12;
|
||||
+ else if (!strcasecmp("PTT", region_type_string))
|
||||
+ return 15;
|
||||
+ return -1;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+nuke(const char *filename, char *image, int size, int region_type)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct region region;
|
||||
+ const struct frba *frba = find_frba(image, size);
|
||||
+ if (!frba)
|
||||
+ exit(EXIT_FAILURE);
|
||||
+
|
||||
+ region = get_region(frba, region_type);
|
||||
+ if (region.size > 0) {
|
||||
+ for (i = region.base; i <= region.limit; i++) {
|
||||
+ if ((i + 1) > (size))
|
||||
+ break;
|
||||
+ image[i] = 0xFF;
|
||||
+ }
|
||||
+ write_image(filename, image, size);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int opt, option_index = 0;
|
||||
@@ -2270,6 +2325,7 @@ int main(int argc, char *argv[])
|
||||
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
|
||||
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
|
||||
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
|
||||
+ int mode_nuke = 0;
|
||||
int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
|
||||
int mode_settopswapsize = 0;
|
||||
char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL;
|
||||
@@ -2306,6 +2362,7 @@ int main(int argc, char *argv[])
|
||||
{"setpchstrap", 1, NULL, 'S'},
|
||||
{"newvalue", 1, NULL, 'V'},
|
||||
{"topswapsize", 1, NULL, 'T'},
|
||||
+ {"nuke", 1, NULL, 'N'},
|
||||
{0, 0, 0, 0}
|
||||
};
|
||||
|
||||
@@ -2355,35 +2412,8 @@ int main(int argc, char *argv[])
|
||||
region_fname++;
|
||||
// Descriptor, BIOS, ME, GbE, Platform
|
||||
// valid type?
|
||||
- if (!strcasecmp("Descriptor", region_type_string))
|
||||
- region_type = 0;
|
||||
- else if (!strcasecmp("BIOS", region_type_string))
|
||||
- region_type = 1;
|
||||
- else if (!strcasecmp("ME", region_type_string))
|
||||
- region_type = 2;
|
||||
- else if (!strcasecmp("GbE", region_type_string))
|
||||
- region_type = 3;
|
||||
- else if (!strcasecmp("Platform Data", region_type_string))
|
||||
- region_type = 4;
|
||||
- else if (!strcasecmp("Device Exp1", region_type_string))
|
||||
- region_type = 5;
|
||||
- else if (!strcasecmp("Secondary BIOS", region_type_string))
|
||||
- region_type = 6;
|
||||
- else if (!strcasecmp("Reserved", region_type_string))
|
||||
- region_type = 7;
|
||||
- else if (!strcasecmp("EC", region_type_string))
|
||||
- region_type = 8;
|
||||
- else if (!strcasecmp("Device Exp2", region_type_string))
|
||||
- region_type = 9;
|
||||
- else if (!strcasecmp("IE", region_type_string))
|
||||
- region_type = 10;
|
||||
- else if (!strcasecmp("10GbE_0", region_type_string))
|
||||
- region_type = 11;
|
||||
- else if (!strcasecmp("10GbE_1", region_type_string))
|
||||
- region_type = 12;
|
||||
- else if (!strcasecmp("PTT", region_type_string))
|
||||
- region_type = 15;
|
||||
- if (region_type == -1) {
|
||||
+ if ((region_type =
|
||||
+ get_region_type_string(region_type_string)) == -1) {
|
||||
fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
region_type_string);
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
@@ -2564,7 +2594,23 @@ int main(int argc, char *argv[])
|
||||
mode_settopswapsize = 1;
|
||||
top_swap_size_arg = optarg;
|
||||
break;
|
||||
- case 'v':
|
||||
+ case 'N':
|
||||
+ region_type_string = strdup(optarg);
|
||||
+ if (!region_type_string) {
|
||||
+ fprintf(stderr, "No region specified\n");
|
||||
+ print_usage(argv[0]);
|
||||
+ exit(EXIT_FAILURE);
|
||||
+ }
|
||||
+ if ((region_type =
|
||||
+ get_region_type_string(region_type_string)) == -1) {
|
||||
+ fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
+ region_type_string);
|
||||
+ print_usage(argv[0]);
|
||||
+ exit(EXIT_FAILURE);
|
||||
+ }
|
||||
+ mode_nuke = 1;
|
||||
+ break;
|
||||
+ Case 'v':
|
||||
print_version();
|
||||
exit(EXIT_SUCCESS);
|
||||
break;
|
||||
@@ -2583,7 +2629,8 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 |
|
||||
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
|
||||
- (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
|
||||
+ (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
|
||||
+ mode_nuke) > 1) {
|
||||
fprintf(stderr, "You may not specify more than one mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2592,7 +2639,8 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 +
|
||||
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
|
||||
- mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
|
||||
+ mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
|
||||
+ mode_nuke) == 0) {
|
||||
fprintf(stderr, "You need to specify a mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2758,6 +2806,10 @@ int main(int argc, char *argv[])
|
||||
write_image(new_filename, image, size);
|
||||
}
|
||||
|
||||
+ if (mode_nuke) {
|
||||
+ nuke(new_filename, image, size, region_type);
|
||||
+ }
|
||||
+
|
||||
if (mode_altmedisable) {
|
||||
struct fpsba *fpsba = find_fpsba(image, size);
|
||||
struct fmsba *fmsba = find_fmsba(image, size);
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-28
@@ -1,28 +0,0 @@
|
||||
From e4682c184ded28dc9daf7ae6cae9d121f3803bef Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sat, 6 May 2023 15:53:41 -0600
|
||||
Subject: [PATCH 07/51] mb/dell/e6400: Enable 01.0 device in devicetree for
|
||||
dGPU models
|
||||
|
||||
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/gm45_latitude/devicetree.cb | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/gm45_latitude/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
|
||||
index 5919803be2..76dae87153 100644
|
||||
--- a/src/mainboard/dell/gm45_latitude/devicetree.cb
|
||||
+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
|
||||
@@ -18,7 +18,7 @@ chip northbridge/intel/gm45
|
||||
ops gm45_pci_domain_ops
|
||||
|
||||
device pci 00.0 on end # host bridge
|
||||
- device pci 01.0 off end
|
||||
+ device pci 01.0 on end
|
||||
device pci 02.0 on end # VGA
|
||||
device pci 02.1 on end # Display
|
||||
device pci 03.0 on end # ME
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-39
@@ -1,39 +0,0 @@
|
||||
From 83a4706b4948797ff57f314c9518f256aea08e79 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Fri, 12 May 2023 19:55:15 -0600
|
||||
Subject: [PATCH 08/51] Remove warning for coreboot images built without a
|
||||
payload
|
||||
|
||||
I added this in upstream to prevent people from accidentally flashing
|
||||
roms without a payload resulting in a no boot situation, but in
|
||||
libreboot lbmk handles the payload and thus this warning always comes
|
||||
up. This has caused confusion and concern so just patch it out.
|
||||
---
|
||||
payloads/Makefile.mk | 13 +------------
|
||||
1 file changed, 1 insertion(+), 12 deletions(-)
|
||||
|
||||
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
|
||||
index 5f988dac1b..516133880f 100644
|
||||
--- a/payloads/Makefile.mk
|
||||
+++ b/payloads/Makefile.mk
|
||||
@@ -50,16 +50,5 @@ distclean-payloads:
|
||||
print-repo-info-payloads:
|
||||
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
|
||||
|
||||
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
|
||||
-show_notices:: warn_no_payload
|
||||
-endif
|
||||
-
|
||||
-warn_no_payload:
|
||||
- printf "\n\t** WARNING **\n"
|
||||
- printf "coreboot has been built without a payload. Writing\n"
|
||||
- printf "a coreboot image without a payload to your board's\n"
|
||||
- printf "flash chip will result in a non-booting system. You\n"
|
||||
- printf "can use cbfstool to add a payload to the image.\n\n"
|
||||
-
|
||||
.PHONY: force-payload coreinfo nvramcui
|
||||
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
|
||||
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-28
@@ -1,28 +0,0 @@
|
||||
From 9dbbefa5297329f316adeb95c2a78267be146509 Mon Sep 17 00:00:00 2001
|
||||
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
|
||||
Date: Thu, 22 Jun 2023 16:44:27 +0300
|
||||
Subject: [PATCH 09/51] HACK: Disable coreboot related BL31 features
|
||||
|
||||
I don't know why, but removing this BL31 make argument lets gru-kevin
|
||||
power off properly when shut down from Linux. Needs investigation.
|
||||
---
|
||||
src/arch/arm64/Makefile.mk | 3 ---
|
||||
1 file changed, 3 deletions(-)
|
||||
|
||||
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
|
||||
index 7310ce1c1f..b0a6ed1f84 100644
|
||||
--- a/src/arch/arm64/Makefile.mk
|
||||
+++ b/src/arch/arm64/Makefile.mk
|
||||
@@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
|
||||
# Always enable crash reporting, even on a release build
|
||||
BL31_MAKEARGS += CRASH_REPORTING=1
|
||||
|
||||
-# Enable coreboot-specific features like CBMEM console support
|
||||
-BL31_MAKEARGS += COREBOOT=1
|
||||
-
|
||||
# Avoid build/release|build/debug distinction by overriding BUILD_PLAT directly
|
||||
BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
|
||||
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,30 +0,0 @@
|
||||
From 6b112300df5d4538cf19e3f914f0a44628733204 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 5 Nov 2023 11:41:41 +0000
|
||||
Subject: [PATCH 10/51] dell/e6430: use ME Soft Temporary Disable
|
||||
|
||||
i overlooked this. it's set on other boards.
|
||||
|
||||
we use me_cleaner anyway, and we set the hap bit, but
|
||||
this additional setting takes effect even if the ME
|
||||
region is unaltered. it's just another layer of
|
||||
disablement, to absolutely ensure Intel ME is not alive
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/dell/snb_ivb_latitude/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default
|
||||
index 2a5b30f2b7..279415dfd1 100644
|
||||
--- a/src/mainboard/dell/snb_ivb_latitude/cmos.default
|
||||
+++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default
|
||||
@@ -6,4 +6,4 @@ bluetooth=Enable
|
||||
wwan=Enable
|
||||
wlan=Enable
|
||||
sata_mode=AHCI
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,872 +0,0 @@
|
||||
From 42e64e41ec9ce997f6615b7a67655715a67651b4 Mon Sep 17 00:00:00 2001
|
||||
From: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
Date: Sat, 23 Dec 2023 19:02:10 +0200
|
||||
Subject: [PATCH 11/51] mb/hp: Add Compaq Elite 8300 CMT port
|
||||
|
||||
Based on autoport and Z220 SuperIO code.
|
||||
|
||||
With SeaBIOS and Nouveau on Debian, only nomodeset works with GTX 780
|
||||
(must use proprietary driver instead).
|
||||
|
||||
Tested by xilynx / spot_ on #libreboot:
|
||||
- i3-3220, native raminit 2x2GB, M378B5773DH0-CH9 + MT8JTF25664AZ-1G6M1
|
||||
- Celeron G1620, native raminit 1x4GB, MT8JTF51264AZ-1G6E1
|
||||
- Booting Debian with Linux 6.1.0-16-amd64 via SeaBIOS
|
||||
- All SATA ports
|
||||
- Audio: internal speaker, headphone and microphone plugs
|
||||
- Rebooting
|
||||
- S3 suspend and wake
|
||||
- libgfxinit: VGA, DisplayPort
|
||||
- Ethernet
|
||||
- Super I/O: fan speeds stay in control
|
||||
- GPU in PEG slot
|
||||
|
||||
Untested:
|
||||
- EHCI debugging
|
||||
- Other PCI/PCIe slots
|
||||
- PS/2
|
||||
- Serial, parallel ports
|
||||
|
||||
Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363
|
||||
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
---
|
||||
.../hp/compaq_elite_8300_cmt/Kconfig | 39 ++++
|
||||
.../hp/compaq_elite_8300_cmt/Kconfig.name | 2 +
|
||||
.../hp/compaq_elite_8300_cmt/Makefile.mk | 7 +
|
||||
.../hp/compaq_elite_8300_cmt/acpi/ec.asl | 1 +
|
||||
.../compaq_elite_8300_cmt/acpi/platform.asl | 10 +
|
||||
.../hp/compaq_elite_8300_cmt/acpi/superio.asl | 29 +++
|
||||
.../hp/compaq_elite_8300_cmt/acpi_tables.c | 12 ++
|
||||
.../hp/compaq_elite_8300_cmt/board_info.txt | 5 +
|
||||
.../hp/compaq_elite_8300_cmt/cmos.default | 7 +
|
||||
.../hp/compaq_elite_8300_cmt/cmos.layout | 74 +++++++
|
||||
.../hp/compaq_elite_8300_cmt/data.vbt | Bin 0 -> 3902 bytes
|
||||
.../hp/compaq_elite_8300_cmt/devicetree.cb | 177 ++++++++++++++++
|
||||
.../hp/compaq_elite_8300_cmt/dsdt.asl | 26 +++
|
||||
.../hp/compaq_elite_8300_cmt/early_init.c | 14 ++
|
||||
.../compaq_elite_8300_cmt/gma-mainboard.ads | 17 ++
|
||||
src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++
|
||||
.../hp/compaq_elite_8300_cmt/hda_verb.c | 33 +++
|
||||
.../hp/compaq_elite_8300_cmt/mainboard.c | 16 ++
|
||||
18 files changed, 660 insertions(+)
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.default
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/data.vbt
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/gpio.c
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c
|
||||
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..d2bfd35dc4
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
|
||||
@@ -0,0 +1,39 @@
|
||||
+if BOARD_HP_COMPAQ_ELITE_8300_CMT
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS
|
||||
+ def_bool y
|
||||
+ select BOARD_ROMSIZE_KB_16384
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select INTEL_INT15
|
||||
+ select MAINBOARD_HAS_TPM1
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select MAINBOARD_USES_IFD_GBE_REGION
|
||||
+ select MEMORY_MAPPED_TPM
|
||||
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
|
||||
+ select SERIRQ_CONTINUOUS_MODE
|
||||
+ select SOUTHBRIDGE_INTEL_C216
|
||||
+ select SUPERIO_NUVOTON_NPCD378
|
||||
+ select USE_NATIVE_RAMINIT
|
||||
+
|
||||
+config CBFS_SIZE
|
||||
+ default 0x570000
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "hp/compaq_elite_8300_cmt"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "HP Compaq Elite 8300 CMT"
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,0152"
|
||||
+
|
||||
+config DRAM_RESET_GATE_GPIO
|
||||
+ default 60
|
||||
+
|
||||
+config USBDEBUG_HCD_INDEX # FIXME: check this
|
||||
+ default 2
|
||||
+endif
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..bd399b1e76
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
|
||||
@@ -0,0 +1,2 @@
|
||||
+config BOARD_HP_COMPAQ_ELITE_8300_CMT
|
||||
+ bool "Compaq Elite 8300 CMT"
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
|
||||
new file mode 100644
|
||||
index 0000000000..fb492d3583
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
|
||||
@@ -0,0 +1,7 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+bootblock-y += early_init.c
|
||||
+bootblock-y += gpio.c
|
||||
+romstage-y += early_init.c
|
||||
+romstage-y += gpio.c
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..73fa78ef14
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
|
||||
@@ -0,0 +1 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
|
||||
new file mode 100644
|
||||
index 0000000000..aff432b6f4
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
|
||||
@@ -0,0 +1,10 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Method(_WAK, 1)
|
||||
+{
|
||||
+ Return(Package() {0, 0})
|
||||
+}
|
||||
+
|
||||
+Method(_PTS, 1)
|
||||
+{
|
||||
+}
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..54f8e3fe95
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
|
||||
@@ -0,0 +1,29 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */
|
||||
+
|
||||
+#include <superio/nuvoton/npcd378/acpi/superio.asl>
|
||||
+
|
||||
+Scope (\_GPE)
|
||||
+{
|
||||
+ Method (_L0D, 0, NotSerialized)
|
||||
+ {
|
||||
+ Notify (\_SB.PCI0.EHC1, 0x02)
|
||||
+ Notify (\_SB.PCI0.EHC2, 0x02)
|
||||
+ //FIXME: Add GBE device
|
||||
+ //Notify (\_SB.PCI0.GBE, 0x02)
|
||||
+ }
|
||||
+
|
||||
+ Method (_L09, 0, NotSerialized)
|
||||
+ {
|
||||
+ Notify (\_SB.PCI0.RP01, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP02, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP03, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP04, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP05, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP06, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP07, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP08, 0x02)
|
||||
+ Notify (\_SB.PCI0.PEGP, 0x02)
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c
|
||||
new file mode 100644
|
||||
index 0000000000..8f4f83b826
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi_gnvs.h>
|
||||
+#include <soc/nvs.h>
|
||||
+
|
||||
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
|
||||
+{
|
||||
+ /* Temperature at which OS will shutdown */
|
||||
+ gnvs->tcrt = 100;
|
||||
+ /* Temperature at which OS will throttle CPU */
|
||||
+ gnvs->tpsv = 90;
|
||||
+}
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..16c29e82d8
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt
|
||||
@@ -0,0 +1,5 @@
|
||||
+Category: desktop
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
+Release year: 2012
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..6d27a79c66
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default
|
||||
@@ -0,0 +1,7 @@
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Enable
|
||||
+nmi=Enable
|
||||
+sata_mode=AHCI
|
||||
+gfx_uma_size=32M
|
||||
+psu_fan_lvl=3
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..1fc83b1a55
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout
|
||||
@@ -0,0 +1,74 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+400 3 h 0 psu_fan_lvl
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 1 nmi
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+
|
||||
+421 1 e 9 sata_mode
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 3 e 11 gfx_uma_size
|
||||
+
|
||||
+448 128 r 0 vbnv
|
||||
+
|
||||
+# SandyBridge MRC Scrambler Seed values
|
||||
+896 32 r 0 mrc_scrambler_seed
|
||||
+928 32 r 0 mrc_scrambler_seed_s3
|
||||
+960 16 r 0 mrc_scrambler_seed_chk
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+9 0 AHCI
|
||||
+9 1 IDE
|
||||
+11 0 32M
|
||||
+11 1 64M
|
||||
+11 2 96M
|
||||
+11 3 128M
|
||||
+11 4 160M
|
||||
+11 5 192M
|
||||
+11 6 224M
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 415 984
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt b/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..ba627e152b65d779a80529d3811ec4d21c1b1e54
|
||||
GIT binary patch
|
||||
literal 3902
|
||||
zcmdT{U2GIp6h5;vvp;uc+U>N$b}h{<64)*MnJ%?9P1V_-)?HZIZFkwM#K;zQp(Lf0
|
||||
z<tLDc9kdaQ30aLnL^K;s2=dhMWTFo|nZ_7XjUmSPK!^{95W@p8ks#}tpO&8zIx!OQ
|
||||
zPQE$ko;~;Lz2}~D=XOmtlA-CLNM|A&X^#!0H)V!X1yJCH+Hrg@ZIQ%qdRr`<32%!e
|
||||
zhohV5IamQTwRf%o6o9FhLR}l4OH3XpP6S4SG(9$1II_L8yRfU+nK)!=G!;$I@QxkD
|
||||
ziDGH&K(Rp6*_Xmpr<F+L;O>b69XhyYd$H6<buRR#UELiUx+zsQbar)jhLo-lr6HwH
|
||||
z>Fo<WE0Nehba-<rkql=N!$Wj<l*SV2a5_D(Ig)&trbdV3iAW+d5R-_pl<3~6Bc<KD
|
||||
z#t+ayG>9yU(vE~()R;1j?k!Dq(D1|r9o2pI)6wGoV(Cz^&><0>;1cWR7zP*~YL5XE
|
||||
z{3`?=k6Yy2an&85Zl2-7jM~D`7^g}MH^6WOPE9askfBLVUBl5fj(Wi%F%Ax(<(|k=
|
||||
zUH4c9hXO|5?0UW22lb}G1;Fb@mzSZ8u5fTU59si@;V}EXTQ}(rl%Wn?F&a92X)&+>
|
||||
zPTj@>Ls7r4(ffK2={zn6t_hS-cTaC$zZ!`R#y2KYqnT`O>nqx^H{P7_!|gKQVi}A&
|
||||
z)G!L9*Z>@59dMlOh4owoes{Vd<dPwV$RfrOM_mMtBi==PggB45i1-TeHR314Rm63~
|
||||
z9|&+0AczJ;Ga`TpA^H)6h!kQgqJWr0I1j?@szU?Z5NsM_$vRVlmxGf*(9T-+vzFa+
|
||||
z!`K`kmJ}>$kl1)tt1cJZseb2!YSsO`J_8jQ^hAhROmRyl4au@8tDixs`{k^Dwd%=Z
|
||||
zH-yjQdy~%q^YKY<!Z~QsaFSLvP<_4(KebAii%moAUIzzXdbGph$OYv=h6VegT-HIX
|
||||
zhmBa>th;}v$r!Z-pnAN<1I)+#R``=|huU|*W1ew~tpBFsG0q;_jCFT6Ulxt*TNv8#
|
||||
z2{`>`$JM`Jd{F+EzpU7VIlvml?AFW1Xv$0tKyom(Ej2b-oERG0Q?%Jx8HYk6s9{*E
|
||||
z_)hegWIm-8PLF`1DpU2QrTKj4;VUElwQBD4f+hZ<s%)PPsp_Q#i!T5@)2taxv1ghG
|
||||
z<B&&<DI4jDn$!FOh>Zbggj@JDLYbjpK69X2PaAVr^Xn{6e+%<?63)ABGAHVvOwA0G
|
||||
zop-g`)B~42TA5y1<#p#*n`4^oSOPu_>i&oRk>LBlzUQG|c;s(9<VO#^<&i}~RuI}x
|
||||
z<RL<GguYJXG9hOOy+q_62>FFjhafiyq*<UbLCy*!FVMFH`LsYj73iEG|16MS1xiG@
|
||||
zNhE7UniS<%MKUhZlcHP^$pw+li}F>GTo<V<$!jFiA<>K^@07@tL{CZbd5K(<q}Cgp
|
||||
z=D5OWb(o)+1@4lFyO?u`hP=smQS!Cx@SCx8`ItCXGEp|?Se~I$OQ9>*L<3rb71Ew*
|
||||
zhn0l-*|a>v(n`=1+Du-&m2f&k|07qiv~u)9FuttfVcu_x;V>QXdsXjZ?db(%oNhK5
|
||||
zme#7yVBD-k)j4Zp4ohoWFJ0rv5wpCVNbYROUKoL9Ww31Rg%2ZHHV$2!ik&#T)={qH
|
||||
z{mrUEty8JFXPPS;w@^`Y*;z%PU#m>bK7$Oci}}Epjc<@x;b&~*!<k@Zeq?5~lKODv
|
||||
zA_EJ8u45$aFet6+Tz;mY_(sgz72qmZ5DkWZn3D#BWHRv7#wxD)p^~C26;X-mqrjL$
|
||||
z8S4>Op}BgEe0X$iI{Gx<zTS2<*M4^|Sg17^@EYY@zAl0)<Ta?zd%bn~D02?r)iu%P
|
||||
wm+F7xwtgQt<KA_UyAYqlTkT_cS089?Pr=)R7|a9^*a9j1U$>1p1;4R>1E3jwQUCw|
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..3d21739b72
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
|
||||
@@ -0,0 +1,177 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+chip northbridge/intel/sandybridge
|
||||
+ register "gfx.use_spread_spectrum_clock" = "0"
|
||||
+ register "gpu_dp_b_hotplug" = "0"
|
||||
+ register "gpu_dp_c_hotplug" = "0"
|
||||
+ register "gpu_dp_d_hotplug" = "0"
|
||||
+ # BTX mainboard: Reversed mapping
|
||||
+ register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}"
|
||||
+ device domain 0 on
|
||||
+ subsystemid 0x103c 0x3396 inherit
|
||||
+
|
||||
+ device ref host_bridge on end # Host bridge Host bridge
|
||||
+ device ref peg10 on end # PEG
|
||||
+ device ref igd on end # iGPU
|
||||
+
|
||||
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
+ register "docking_supported" = "0"
|
||||
+ register "gen1_dec" = "0x00fc0a01"
|
||||
+ register "gen2_dec" = "0x00fc0801"
|
||||
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
|
||||
+ register "pcie_port_coalesce" = "1"
|
||||
+ register "sata_interface_speed_support" = "0x3"
|
||||
+ register "sata_port_map" = "0x1f"
|
||||
+ register "spi_lvscc" = "0x2005"
|
||||
+ register "spi_uvscc" = "0x2005"
|
||||
+ register "superspeed_capable_ports" = "0x0000000f"
|
||||
+ register "xhci_overcurrent_mapping" = "0x00000c03"
|
||||
+ register "xhci_switchable_ports" = "0x0000000f"
|
||||
+ register "usb_port_config" = "{
|
||||
+ { 1, 0, 0 },
|
||||
+ { 1, 0, 0 },
|
||||
+ { 1, 0, 1 },
|
||||
+ { 1, 0, 1 },
|
||||
+ { 1, 0, 2 },
|
||||
+ { 1, 0, 2 },
|
||||
+ { 1, 0, 3 },
|
||||
+ { 1, 0, 3 },
|
||||
+ { 1, 0, 4 },
|
||||
+ { 1, 0, 4 },
|
||||
+ { 1, 0, 6 },
|
||||
+ { 1, 0, 5 },
|
||||
+ { 1, 0, 5 },
|
||||
+ { 1, 0, 6 }
|
||||
+ }"
|
||||
+
|
||||
+ device ref xhci on end # USB 3.0 Controller
|
||||
+ device ref mei1 off end # Management Engine Interface 1
|
||||
+ device ref mei2 off end
|
||||
+ device ref me_ide_r off end
|
||||
+ device ref me_kt off end
|
||||
+ device ref gbe on end # Intel Gigabit Ethernet
|
||||
+ device ref ehci1 on end # USB2 EHCI #1
|
||||
+ device ref ehci2 on end # USB2 EHCI #2
|
||||
+ device ref hda on end # High Definition Audio
|
||||
+ device ref sata1 on end # SATA Controller 1
|
||||
+ device ref sata2 off end # SATA Controller 2
|
||||
+ device ref smbus on end # SMBus
|
||||
+
|
||||
+ device ref pcie_rp1 on end
|
||||
+ device ref pcie_rp2 on end
|
||||
+ device ref pcie_rp3 on end
|
||||
+ device ref pcie_rp4 on end
|
||||
+ device ref pcie_rp5 on end
|
||||
+ device ref pcie_rp6 on end
|
||||
+ device ref pcie_rp7 on end
|
||||
+ device ref pcie_rp8 on end
|
||||
+
|
||||
+ device ref pci_bridge on end
|
||||
+ device ref lpc on # LPC bridge
|
||||
+ chip superio/common # copied from Z220
|
||||
+ device pnp 2e.ff on # passes SIO base addr to SSDT gen
|
||||
+ chip superio/nuvoton/npcd378
|
||||
+ device pnp 2e.0 off end # Floppy
|
||||
+ device pnp 2e.1 on # Parallel port
|
||||
+ # global
|
||||
+
|
||||
+ # serialice: Vendor writes:
|
||||
+ irq 0x14 = 0x9c
|
||||
+ irq 0x1c = 0xa8
|
||||
+ irq 0x1d = 0x08
|
||||
+ irq 0x22 = 0x3f
|
||||
+ irq 0x1a = 0xb0
|
||||
+ # dumped from superiotool:
|
||||
+ irq 0x1b = 0x1e
|
||||
+ irq 0x27 = 0x08
|
||||
+ irq 0x2a = 0x20
|
||||
+ irq 0x2d = 0x01
|
||||
+ # parallel port
|
||||
+ io 0x60 = 0x378
|
||||
+ irq 0x70 = 0x07
|
||||
+ drq 0x74 = 0x01
|
||||
+ end
|
||||
+ device pnp 2e.2 off # COM1
|
||||
+ io 0x60 = 0x2f8
|
||||
+ irq 0x70 = 3
|
||||
+ end
|
||||
+ device pnp 2e.3 on # COM2, IR
|
||||
+ io 0x60 = 0x3f8
|
||||
+ irq 0x70 = 4
|
||||
+ end
|
||||
+ device pnp 2e.4 on # LED control
|
||||
+ io 0x60 = 0x600
|
||||
+ # IOBASE[0h] = bit0 LED red / green
|
||||
+ # IOBASE[0h] = bit1-4 LED PWM duty cycle
|
||||
+ # IOBASE[1h] = bit6 SWCC
|
||||
+
|
||||
+ io 0x62 = 0x610
|
||||
+ # IOBASE [0h] = GPES
|
||||
+ # IOBASE [1h] = GPEE
|
||||
+ # IOBASE [4h:7h] = 32bit upcounter at 1Mhz
|
||||
+ # IOBASE [8h:bh] = GPS
|
||||
+ # IOBASE [ch:fh] = GPE
|
||||
+ end
|
||||
+ device pnp 2e.5 on # Mouse
|
||||
+ irq 0x70 = 0xc
|
||||
+ end
|
||||
+ device pnp 2e.6 on # Keyboard
|
||||
+ io 0x60 = 0x0060
|
||||
+ io 0x62 = 0x0064
|
||||
+ irq 0x70 = 0x01
|
||||
+ # serialice: Vendor writes:
|
||||
+ drq 0xf0 = 0x40
|
||||
+ end
|
||||
+ device pnp 2e.7 on # WDT ?
|
||||
+ io 0x60 = 0x620
|
||||
+ end
|
||||
+ device pnp 2e.8 on # HWM
|
||||
+ io 0x60 = 0x800
|
||||
+ # IOBASE[0h:feh] HWM page
|
||||
+ # IOBASE[ffh] bit0-bit3 page selector
|
||||
+
|
||||
+ drq 0xf0 = 0x20
|
||||
+ drq 0xf1 = 0x01
|
||||
+ drq 0xf2 = 0x40
|
||||
+ drq 0xf3 = 0x01
|
||||
+
|
||||
+ drq 0xf4 = 0x66
|
||||
+ drq 0xf5 = 0x67
|
||||
+ drq 0xf6 = 0x66
|
||||
+ drq 0xf7 = 0x01
|
||||
+ end
|
||||
+ device pnp 2e.f on # GPIO OD ?
|
||||
+ drq 0xf1 = 0x97
|
||||
+ drq 0xf2 = 0x01
|
||||
+ drq 0xf5 = 0x08
|
||||
+ drq 0xfe = 0x80
|
||||
+ end
|
||||
+ device pnp 2e.15 on # BUS ?
|
||||
+ io 0x60 = 0x0680
|
||||
+ io 0x62 = 0x0690
|
||||
+ end
|
||||
+ device pnp 2e.1c on # Suspend Control ?
|
||||
+ io 0x60 = 0x640
|
||||
+ # writing to IOBASE[5h]
|
||||
+ # 0x0: Power off
|
||||
+ # 0x9: Power off and bricked until CMOS battery removed
|
||||
+ end
|
||||
+ device pnp 2e.1e on # GPIO ?
|
||||
+ io 0x60 = 0x660
|
||||
+ drq 0xf4 = 0x01
|
||||
+ # skip the following, as it
|
||||
+ # looks like remapped registers
|
||||
+ #drq 0xf5 = 0x06
|
||||
+ #drq 0xf6 = 0x60
|
||||
+ #drq 0xfe = 0x03
|
||||
+ end
|
||||
+ end
|
||||
+ end
|
||||
+ end
|
||||
+ chip drivers/pc80/tpm
|
||||
+ device pnp 4e.0 on end # TPM module
|
||||
+ end
|
||||
+ end
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..e8e2b3a3e5
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl
|
||||
@@ -0,0 +1,26 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20141018 /* OEM revision */
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+ #include "acpi/platform.asl"
|
||||
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..8d10c6317c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
|
||||
@@ -0,0 +1,14 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <bootblock_common.h>
|
||||
+#include <superio/nuvoton/npcd378/npcd378.h>
|
||||
+#include <superio/nuvoton/common/nuvoton.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
|
||||
+
|
||||
+void bootblock_mainboard_early_init(void)
|
||||
+{
|
||||
+ if (CONFIG(CONSOLE_SERIAL))
|
||||
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
+}
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..686f7d44db
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads
|
||||
@@ -0,0 +1,17 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (DP2,
|
||||
+ HDMI2,
|
||||
+ Analog,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..2ae852ae51
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c
|
||||
@@ -0,0 +1,191 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_GPIO,
|
||||
+ .gpio1 = GPIO_MODE_GPIO,
|
||||
+ .gpio2 = GPIO_MODE_NATIVE,
|
||||
+ .gpio3 = GPIO_MODE_NATIVE,
|
||||
+ .gpio4 = GPIO_MODE_NATIVE,
|
||||
+ .gpio5 = GPIO_MODE_NATIVE,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_GPIO,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_NATIVE,
|
||||
+ .gpio15 = GPIO_MODE_GPIO,
|
||||
+ .gpio16 = GPIO_MODE_GPIO,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||
+ .gpio19 = GPIO_MODE_NATIVE,
|
||||
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_NATIVE,
|
||||
+ .gpio31 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio0 = GPIO_DIR_INPUT,
|
||||
+ .gpio1 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio11 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio15 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio16 = GPIO_DIR_INPUT,
|
||||
+ .gpio17 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio29 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio31 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio15 = GPIO_LEVEL_LOW,
|
||||
+ .gpio17 = GPIO_LEVEL_LOW,
|
||||
+ .gpio28 = GPIO_LEVEL_LOW,
|
||||
+ .gpio29 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio0 = GPIO_INVERT,
|
||||
+ .gpio1 = GPIO_INVERT,
|
||||
+ .gpio6 = GPIO_INVERT,
|
||||
+ .gpio11 = GPIO_INVERT,
|
||||
+ .gpio13 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_GPIO,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_GPIO,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_NATIVE,
|
||||
+ .gpio46 = GPIO_MODE_GPIO,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_NATIVE,
|
||||
+ .gpio52 = GPIO_MODE_NATIVE,
|
||||
+ .gpio53 = GPIO_MODE_NATIVE,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_NATIVE,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_NATIVE,
|
||||
+ .gpio61 = GPIO_MODE_GPIO,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio32 = GPIO_DIR_INPUT,
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_INPUT,
|
||||
+ .gpio35 = GPIO_DIR_INPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio43 = GPIO_DIR_INPUT,
|
||||
+ .gpio46 = GPIO_DIR_INPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_INPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio61 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_GPIO,
|
||||
+ .gpio69 = GPIO_MODE_GPIO,
|
||||
+ .gpio70 = GPIO_MODE_GPIO,
|
||||
+ .gpio71 = GPIO_MODE_GPIO,
|
||||
+ .gpio72 = GPIO_MODE_GPIO,
|
||||
+ .gpio73 = GPIO_MODE_NATIVE,
|
||||
+ .gpio74 = GPIO_MODE_NATIVE,
|
||||
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio68 = GPIO_DIR_INPUT,
|
||||
+ .gpio69 = GPIO_DIR_INPUT,
|
||||
+ .gpio70 = GPIO_DIR_INPUT,
|
||||
+ .gpio71 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio72 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+ .gpio71 = GPIO_LEVEL_LOW,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ .reset = &pch_gpio_set1_reset,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ .reset = &pch_gpio_set2_reset,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ .reset = &pch_gpio_set3_reset,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..a1eafcda68
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c
|
||||
@@ -0,0 +1,33 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x10ec0221, /* Codec Vendor / Device ID: Realtek */
|
||||
+ 0x103c3396, /* Subsystem ID */
|
||||
+ 11, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(0, 0x103c3396),
|
||||
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x14, 0x01014020),
|
||||
+ AZALIA_PIN_CFG(0, 0x17, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f),
|
||||
+ AZALIA_PIN_CFG(0, 0x1b, 0x01813c30),
|
||||
+ AZALIA_PIN_CFG(0, 0x1d, 0x415901f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
|
||||
+
|
||||
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
+ 0x80860101, /* Subsystem ID */
|
||||
+ 4, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
+ AZALIA_PIN_CFG(3, 0x05, 0x58560010),
|
||||
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
+ AZALIA_PIN_CFG(3, 0x07, 0x58560030),
|
||||
+
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c
|
||||
new file mode 100644
|
||||
index 0000000000..8dbd95ef96
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c
|
||||
@@ -0,0 +1,16 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/device.h>
|
||||
+#include <drivers/intel/gma/int15.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+static void mainboard_enable(struct device *dev)
|
||||
+{
|
||||
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
|
||||
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
+}
|
||||
+
|
||||
+struct chip_operations mainboard_ops = {
|
||||
+ .enable_dev = mainboard_enable,
|
||||
+};
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-305
@@ -1,305 +0,0 @@
|
||||
From 601661d628ff7b8ffee8c1ed13307caa23d489ce Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 2 Mar 2024 22:51:09 +0000
|
||||
Subject: [PATCH 12/51] nb/intel/haswell: make IOMMU a runtime option
|
||||
|
||||
When I tested graphics cards on a coreboot port for Dell
|
||||
OptiPlex 9020 SFF, I could not use a graphics card unless
|
||||
I set iommu=off on the Linux cmdline.
|
||||
|
||||
Coreboot's current behaviour is to check whether the CPU
|
||||
has vt-d support and, if it does, initialise the IOMMU.
|
||||
|
||||
This patch maintains the current behaviour by default, but
|
||||
allows the user to turn *off* the IOMMU, even if vt-d is
|
||||
supported by the host CPU.
|
||||
|
||||
If iommu=Disable is specified, the check will not be
|
||||
performed, and the IOMMU will be left disabled. This option
|
||||
has been added to all current Haswell boards, though it is
|
||||
recommended to leave the IOMMU turned on in most setups.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/asrock/b85m_pro4/cmos.default | 1 +
|
||||
src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++
|
||||
src/mainboard/asrock/h81m-hds/cmos.default | 1 +
|
||||
src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 1 +
|
||||
src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++
|
||||
src/mainboard/google/beltino/cmos.layout | 5 +++++
|
||||
src/mainboard/google/slippy/cmos.layout | 5 +++++
|
||||
src/mainboard/intel/baskingridge/cmos.layout | 4 ++++
|
||||
src/mainboard/lenovo/haswell/cmos.default | 1 +
|
||||
src/mainboard/lenovo/haswell/cmos.layout | 3 +++
|
||||
src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
|
||||
src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++
|
||||
src/northbridge/intel/haswell/early_init.c | 15 ++++++++++-----
|
||||
14 files changed, 53 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default
|
||||
index 01bf20ad16..dfc8b80fb0 100644
|
||||
--- a/src/mainboard/asrock/b85m_pro4/cmos.default
|
||||
+++ b/src/mainboard/asrock/b85m_pro4/cmos.default
|
||||
@@ -4,3 +4,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
nmi=Enable
|
||||
power_on_after_fail=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout
|
||||
index efdc333fc2..c9883ea71d 100644
|
||||
--- a/src/mainboard/asrock/b85m_pro4/cmos.layout
|
||||
+++ b/src/mainboard/asrock/b85m_pro4/cmos.layout
|
||||
@@ -11,6 +11,7 @@
|
||||
395 4 e 4 debug_level
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
+ 412 1 e 6 iommu
|
||||
984 16 h 0 check_sum
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
@@ -38,6 +39,8 @@
|
||||
5 0 Disable
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
+ 6 0 Disable
|
||||
+ 6 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default
|
||||
index 01bf20ad16..dfc8b80fb0 100644
|
||||
--- a/src/mainboard/asrock/h81m-hds/cmos.default
|
||||
+++ b/src/mainboard/asrock/h81m-hds/cmos.default
|
||||
@@ -4,3 +4,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
nmi=Enable
|
||||
power_on_after_fail=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout
|
||||
index c9ba76c78f..95ee3d36fb 100644
|
||||
--- a/src/mainboard/asrock/h81m-hds/cmos.layout
|
||||
+++ b/src/mainboard/asrock/h81m-hds/cmos.layout
|
||||
@@ -21,6 +21,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 6 iommu
|
||||
+
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
|
||||
@@ -52,6 +55,9 @@ enumerations
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
|
||||
+6 0 Disable
|
||||
+6 1 Enable
|
||||
+
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
index 6c4a2a1be7..8000eea8c0 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
@@ -4,3 +4,4 @@ debug_level=Debug
|
||||
nmi=Disable
|
||||
power_on_after_fail=Disable
|
||||
fan_full_speed=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
index d10ad95b23..4a1496a878 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
@@ -21,6 +21,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
+# turn iommu on or off
|
||||
+411 1 e 6 iommu
|
||||
+
|
||||
# coreboot config options: EC
|
||||
412 1 e 1 fan_full_speed
|
||||
|
||||
@@ -55,6 +58,9 @@ enumerations
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
|
||||
+6 0 Disable
|
||||
+6 1 Enable
|
||||
+
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout
|
||||
index 78d44c1415..c143979ae1 100644
|
||||
--- a/src/mainboard/google/beltino/cmos.layout
|
||||
+++ b/src/mainboard/google/beltino/cmos.layout
|
||||
@@ -19,6 +19,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 8 iommu
|
||||
+
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
@@ -47,6 +50,8 @@ enumerations
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
+8 0 Disable
|
||||
+8 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout
|
||||
index 78d44c1415..c143979ae1 100644
|
||||
--- a/src/mainboard/google/slippy/cmos.layout
|
||||
+++ b/src/mainboard/google/slippy/cmos.layout
|
||||
@@ -19,6 +19,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 8 iommu
|
||||
+
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
@@ -47,6 +50,8 @@ enumerations
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
+8 0 Disable
|
||||
+8 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout
|
||||
index 78d44c1415..f2c602f541 100644
|
||||
--- a/src/mainboard/intel/baskingridge/cmos.layout
|
||||
+++ b/src/mainboard/intel/baskingridge/cmos.layout
|
||||
@@ -19,6 +19,8 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
+412 1 e 8 iommu
|
||||
+
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
@@ -47,6 +49,8 @@ enumerations
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
+8 0 Disable
|
||||
+8 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default
|
||||
index 08db97c5a9..cc6b363cd9 100644
|
||||
--- a/src/mainboard/lenovo/haswell/cmos.default
|
||||
+++ b/src/mainboard/lenovo/haswell/cmos.default
|
||||
@@ -14,3 +14,4 @@ trackpoint=Enable
|
||||
backlight=Keyboard
|
||||
enable_dual_graphics=Disable
|
||||
usb_always_on=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout
|
||||
index 27915d3ab7..59df76b64c 100644
|
||||
--- a/src/mainboard/lenovo/haswell/cmos.layout
|
||||
+++ b/src/mainboard/lenovo/haswell/cmos.layout
|
||||
@@ -23,6 +23,7 @@ entries
|
||||
|
||||
# coreboot config options: EC
|
||||
411 1 e 8 first_battery
|
||||
+413 1 e 14 iommu
|
||||
415 1 e 1 wlan
|
||||
416 1 e 1 trackpoint
|
||||
417 1 e 1 fn_ctrl_swap
|
||||
@@ -72,6 +73,8 @@ enumerations
|
||||
13 0 Disable
|
||||
13 1 AC and battery
|
||||
13 2 AC only
|
||||
+14 0 Disable
|
||||
+14 1 Enable
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default
|
||||
index 7ce38fb5d7..6049e7938a 100644
|
||||
--- a/src/mainboard/supermicro/x10slm-f/cmos.default
|
||||
+++ b/src/mainboard/supermicro/x10slm-f/cmos.default
|
||||
@@ -5,3 +5,4 @@ debug_level=Debug
|
||||
nmi=Enable
|
||||
power_on_after_fail=Keep
|
||||
hide_ast2400=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout
|
||||
index 38ba87aa45..24d39e97ee 100644
|
||||
--- a/src/mainboard/supermicro/x10slm-f/cmos.layout
|
||||
+++ b/src/mainboard/supermicro/x10slm-f/cmos.layout
|
||||
@@ -21,6 +21,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 6 iommu
|
||||
+
|
||||
# coreboot config options: mainboard
|
||||
416 1 e 1 hide_ast2400
|
||||
|
||||
@@ -55,6 +58,9 @@ enumerations
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
|
||||
+6 0 Disable
|
||||
+6 1 Enable
|
||||
+
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
|
||||
index 6a5ce53a40..e0007f72ee 100644
|
||||
--- a/src/northbridge/intel/haswell/early_init.c
|
||||
+++ b/src/northbridge/intel/haswell/early_init.c
|
||||
@@ -6,6 +6,7 @@
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <types.h>
|
||||
+#include <option.h>
|
||||
|
||||
#include "haswell.h"
|
||||
|
||||
@@ -80,14 +81,18 @@ static void haswell_setup_misc(void)
|
||||
static void northbridge_setup_iommu(void)
|
||||
{
|
||||
const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
|
||||
+ u8 enable_iommu = get_uint_option("iommu", 1);
|
||||
+
|
||||
if (capid0_a & VTD_DISABLE)
|
||||
return;
|
||||
|
||||
- /* Setup BARs: zeroize top 32 bits; set enable bit */
|
||||
- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
|
||||
- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
|
||||
- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
|
||||
- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
|
||||
+ if (enable_iommu) {
|
||||
+ /* Setup BARs: zeroize top 32 bits; set enable bit */
|
||||
+ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
|
||||
+ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
|
||||
+ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
|
||||
+ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
|
||||
+ }
|
||||
|
||||
if (cpu_is_haswell()) {
|
||||
/*
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-29
@@ -1,29 +0,0 @@
|
||||
From 1586b045a75b9cf8cd68a44739beefa501e6cbd3 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 2 Mar 2024 23:00:09 +0000
|
||||
Subject: [PATCH 13/51] dell/optiplex_9020: Disable IOMMU by default
|
||||
|
||||
Needed to make graphics cards work. Turning it on is
|
||||
recommended if only using iGPU, otherwise leave it off
|
||||
by default. The IOMMU is extremely buggy when a graphics
|
||||
card is used. Leaving it off by default will ensure that
|
||||
the default ROM images in Libreboot will work on any setup.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
index 8000eea8c0..0700f971ee 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
@@ -4,4 +4,4 @@ debug_level=Debug
|
||||
nmi=Disable
|
||||
power_on_after_fail=Disable
|
||||
fan_full_speed=Disable
|
||||
-iommu=Enable
|
||||
+iommu=Disable
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-51
@@ -1,51 +0,0 @@
|
||||
From 64e0140fec07d7062b147419781e200509c63053 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 6 Apr 2024 01:22:47 +0100
|
||||
Subject: [PATCH 14/51] nb/haswell: Fully disable iGPU when dGPU is used
|
||||
|
||||
My earlier patch disabled decode *and* disabled the iGPU itself, but
|
||||
a subsequent revision disabled only VGA decode. Upon revisiting, I
|
||||
found that, actually, yes, you also need to disable the iGPU entirely.
|
||||
|
||||
Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU.
|
||||
With this patch, the iGPU is completely disabled when you install a
|
||||
graphics card, but the iGPU is available to use when no graphics card
|
||||
is present.
|
||||
|
||||
For more context, see:
|
||||
|
||||
Author: Leah Rowe <info@minifree.org>
|
||||
Date: Fri Feb 23 13:33:31 2024 +0000
|
||||
|
||||
nb/haswell: Disable iGPU when dGPU is used
|
||||
|
||||
And look at the Gerrit comments:
|
||||
|
||||
https://review.coreboot.org/c/coreboot/+/80717/
|
||||
|
||||
So, my original submission on change 80717 was actually correct.
|
||||
This patch fixes the issue. I tested on iGPU and dGPU, with both
|
||||
broadwell and haswell mrc.bin.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/northbridge/intel/haswell/gma.c | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
|
||||
index fc44a98a57..451147d082 100644
|
||||
--- a/src/northbridge/intel/haswell/gma.c
|
||||
+++ b/src/northbridge/intel/haswell/gma.c
|
||||
@@ -655,6 +655,9 @@ static void gma_func0_disable(struct device *dev)
|
||||
{
|
||||
/* Disable VGA decode */
|
||||
pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
|
||||
+
|
||||
+ /* Required or else the graphics card doesn't work */
|
||||
+ dev->enabled = 0;
|
||||
}
|
||||
|
||||
static struct device_operations gma_func0_ops = {
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-147
@@ -1,147 +0,0 @@
|
||||
From f19a3eb6eee94881ac1c6c6fe28c1f523a12dcda Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Fri, 3 May 2024 11:03:32 -0600
|
||||
Subject: [PATCH 15/51] ec/dell/mec5035: Add S3 suspend SMI handler
|
||||
|
||||
This is necessary for S3 resume to work on SNB and newer Dell Latitude
|
||||
laptops. If a command isn't sent, the EC cuts power to the DIMMs,
|
||||
preventing the system from resuming. These commands were found using an
|
||||
FPGA to log all LPC bus transactions between the host and the EC and
|
||||
then narrowing down which ones were actually necessary.
|
||||
|
||||
Interestingly, the command IDs appear to be identical to those in
|
||||
ec/google/wilco, the EC used on Dell Latitude Chromebooks, and that EC
|
||||
implements a similar S3 SMI handler as the one implemented in this
|
||||
commit. The Wilco EC Kconfig does suggest that its firmware is a
|
||||
modified version of Dell's usual Latitude EC firmware, so the
|
||||
similarities seem to be intentional.
|
||||
|
||||
These similarities also identified a command to enable or disable wake
|
||||
sources like the power button and lid switch, and this was added to the
|
||||
SMI handler to disable lid wake as the system does not yet resume
|
||||
properly from a like wake with coreboot.
|
||||
|
||||
Tested on the Latitude E6430 (Ivy Bridge) and the Precision M6800
|
||||
(Haswell, not yet pushed).
|
||||
|
||||
Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/ec/dell/mec5035/Makefile.mk | 1 +
|
||||
src/ec/dell/mec5035/mec5035.c | 13 +++++++++++++
|
||||
src/ec/dell/mec5035/mec5035.h | 22 ++++++++++++++++++++++
|
||||
src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++
|
||||
4 files changed, 53 insertions(+)
|
||||
create mode 100644 src/ec/dell/mec5035/smihandler.c
|
||||
|
||||
diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk
|
||||
index 4ebdd811f9..be557e4599 100644
|
||||
--- a/src/ec/dell/mec5035/Makefile.mk
|
||||
+++ b/src/ec/dell/mec5035/Makefile.mk
|
||||
@@ -5,5 +5,6 @@ ifeq ($(CONFIG_EC_DELL_MEC5035),y)
|
||||
bootblock-y += mec5035.c
|
||||
romstage-y += mec5035.c
|
||||
ramstage-y += mec5035.c
|
||||
+smm-y += mec5035.c smihandler.c
|
||||
|
||||
endif
|
||||
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
|
||||
index 17ac2c1dab..c5067c16f6 100644
|
||||
--- a/src/ec/dell/mec5035/mec5035.c
|
||||
+++ b/src/ec/dell/mec5035/mec5035.c
|
||||
@@ -100,6 +100,19 @@ static void mec5035_power_button_route(enum ec_power_button_route target)
|
||||
write_mailbox_regs(&buf, 2, 1);
|
||||
ec_command(CMD_POWER_BUTTON_TO_HOST);
|
||||
}
|
||||
+void mec5035_change_wake(u8 source, enum ec_wake_change change)
|
||||
+{
|
||||
+ u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
|
||||
+ write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS);
|
||||
+ ec_command(CMD_ACPI_WAKEUP_CHANGE);
|
||||
+}
|
||||
+
|
||||
+void mec5035_sleep_enable(void)
|
||||
+{
|
||||
+ u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
|
||||
+ write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
|
||||
+ ec_command(CMD_SLEEP_ENABLE);
|
||||
+}
|
||||
|
||||
void mec5035_early_init(void)
|
||||
{
|
||||
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
|
||||
index 5fdf56631b..5cd907bf71 100644
|
||||
--- a/src/ec/dell/mec5035/mec5035.h
|
||||
+++ b/src/ec/dell/mec5035/mec5035.h
|
||||
@@ -4,6 +4,7 @@
|
||||
#define _EC_DELL_MEC5035_H_
|
||||
|
||||
#include <stdint.h>
|
||||
+#include <types.h>
|
||||
|
||||
#define NUM_REGISTERS 32
|
||||
|
||||
@@ -11,6 +12,8 @@ enum mec5035_cmd {
|
||||
CMD_MOUSE_TP = 0x1a,
|
||||
CMD_RADIO_CTRL = 0x2b,
|
||||
CMD_POWER_BUTTON_TO_HOST = 0x3e,
|
||||
+ CMD_ACPI_WAKEUP_CHANGE = 0x4a,
|
||||
+ CMD_SLEEP_ENABLE = 0x64,
|
||||
CMD_CPU_OK = 0xc2,
|
||||
};
|
||||
|
||||
@@ -39,9 +42,28 @@ enum ec_power_button_route {
|
||||
HOST
|
||||
};
|
||||
|
||||
+#define ACPI_WAKEUP_NUM_ARGS 4
|
||||
+enum ec_wake_change {
|
||||
+ WAKE_OFF = 0,
|
||||
+ WAKE_ON
|
||||
+};
|
||||
+
|
||||
+/* Copied from ec/google/wilco/commands.h. Not sure if these all apply */
|
||||
+enum ec_acpi_wake_events {
|
||||
+ EC_ACPI_WAKE_PWRB = BIT(0), /* Wake up by power button */
|
||||
+ EC_ACPI_WAKE_LID = BIT(1), /* Wake up by lid switch */
|
||||
+ EC_ACPI_WAKE_RTC = BIT(5), /* Wake up by RTC */
|
||||
+};
|
||||
+
|
||||
+#define SLEEP_EN_NUM_ARGS 2
|
||||
+
|
||||
u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
|
||||
void mec5035_cpu_ok(void);
|
||||
void mec5035_early_init(void);
|
||||
void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
|
||||
+void mec5035_change_wake(u8 source, enum ec_wake_change change);
|
||||
+void mec5035_sleep_enable(void);
|
||||
+
|
||||
+void mec5035_smi_sleep(int slp_type);
|
||||
|
||||
#endif /* _EC_DELL_MEC5035_H_ */
|
||||
diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c
|
||||
new file mode 100644
|
||||
index 0000000000..958733bf97
|
||||
--- /dev/null
|
||||
+++ b/src/ec/dell/mec5035/smihandler.c
|
||||
@@ -0,0 +1,17 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+#include <console/console.h>
|
||||
+#include <ec/acpi/ec.h>
|
||||
+#include "mec5035.h"
|
||||
+
|
||||
+void mec5035_smi_sleep(int slp_type)
|
||||
+{
|
||||
+ switch (slp_type) {
|
||||
+ case ACPI_S3:
|
||||
+ /* System does not yet resume properly if woken by lid */
|
||||
+ mec5035_change_wake(EC_ACPI_WAKE_LID, WAKE_OFF);
|
||||
+ mec5035_sleep_enable();
|
||||
+ break;
|
||||
+ }
|
||||
+}
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,223 +0,0 @@
|
||||
From c99ef7e409f450dbc66d2de930160f29a0c0d68e Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Mon, 10 May 2021 22:40:59 +0200
|
||||
Subject: [PATCH 16/51] nb/intel/gm45: Make DDR2 raminit work
|
||||
|
||||
List of changes:
|
||||
- Update some timing and ODT values
|
||||
- Patch RCOMP calibration to better match what MRC binaries do
|
||||
- Replay a hardcoded list of RCOMP codes after RcvEn
|
||||
|
||||
This makes raminit work at DDR2-800 speeds and fixes S3 resume as well.
|
||||
Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs.
|
||||
|
||||
Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
src/northbridge/intel/gm45/gm45.h | 2 +-
|
||||
src/northbridge/intel/gm45/raminit.c | 90 +++++++++++++++++--
|
||||
.../intel/gm45/raminit_rcomp_calibration.c | 27 ++++--
|
||||
3 files changed, 106 insertions(+), 13 deletions(-)
|
||||
|
||||
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
|
||||
index 90ab570524..d537ef82af 100644
|
||||
--- a/src/northbridge/intel/gm45/gm45.h
|
||||
+++ b/src/northbridge/intel/gm45/gm45.h
|
||||
@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
|
||||
int raminit_read_vco_index(void);
|
||||
u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
|
||||
|
||||
-void raminit_rcomp_calibration(stepping_t stepping);
|
||||
+void raminit_rcomp_calibration(int ddr_type, stepping_t stepping);
|
||||
void raminit_reset_readwrite_pointers(void);
|
||||
void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
|
||||
void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume);
|
||||
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
|
||||
index def9e1e331..7b091cc567 100644
|
||||
--- a/src/northbridge/intel/gm45/raminit.c
|
||||
+++ b/src/northbridge/intel/gm45/raminit.c
|
||||
@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping,
|
||||
}
|
||||
|
||||
/* Perform RCOMP calibration for DDR3. */
|
||||
- raminit_rcomp_calibration(stepping);
|
||||
+ raminit_rcomp_calibration(spd_type, stepping);
|
||||
|
||||
/* Run initial RCOMP. */
|
||||
mchbar_setbits32(0x418, 1 << 17);
|
||||
@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
|
||||
reg = (reg & ~(0xf << 10)) | (2 << 10);
|
||||
else
|
||||
reg = (reg & ~(0xf << 10)) | (3 << 10);
|
||||
- reg = (reg & ~(0x7 << 5)) | (3 << 5);
|
||||
+ reg = (reg & ~(0x7 << 5)) | (2 << 5);
|
||||
} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
|
||||
reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
|
||||
reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
|
||||
@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff)
|
||||
reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32));
|
||||
reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32));
|
||||
if (timings->mem_clock == MEM_CLOCK_667MT) {
|
||||
- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32));
|
||||
- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32));
|
||||
+ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32));
|
||||
+ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32));
|
||||
} else {
|
||||
- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32));
|
||||
- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32));
|
||||
+ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32));
|
||||
+ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32));
|
||||
}
|
||||
mchbar_write32(CxODT_HIGH(ch), reg);
|
||||
|
||||
@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume)
|
||||
raminit_write_training(timings->mem_clock, dimms, s3resume);
|
||||
}
|
||||
|
||||
+ /*
|
||||
+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
|
||||
+ * after receiver enable calibration, otherwise raminit sometimes
|
||||
+ * completes with non-working memory.
|
||||
+ */
|
||||
+ mchbar_write32(0x0530, 0x06060005);
|
||||
+ mchbar_write32(0x0680, 0x06060606);
|
||||
+ mchbar_write32(0x0684, 0x08070606);
|
||||
+ mchbar_write32(0x0688, 0x0e0e0c0a);
|
||||
+ mchbar_write32(0x068c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0698, 0x06060606);
|
||||
+ mchbar_write32(0x069c, 0x08070606);
|
||||
+ mchbar_write32(0x06a0, 0x0c0c0b0a);
|
||||
+ mchbar_write32(0x06a4, 0x0c0c0c0c);
|
||||
+
|
||||
+ mchbar_write32(0x06c0, 0x02020202);
|
||||
+ mchbar_write32(0x06c4, 0x03020202);
|
||||
+ mchbar_write32(0x06c8, 0x04040403);
|
||||
+ mchbar_write32(0x06cc, 0x04040404);
|
||||
+ mchbar_write32(0x06d8, 0x02020202);
|
||||
+ mchbar_write32(0x06dc, 0x03020202);
|
||||
+ mchbar_write32(0x06e0, 0x04040403);
|
||||
+ mchbar_write32(0x06e4, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0700, 0x02020202);
|
||||
+ mchbar_write32(0x0704, 0x03020202);
|
||||
+ mchbar_write32(0x0708, 0x04040403);
|
||||
+ mchbar_write32(0x070c, 0x04040404);
|
||||
+ mchbar_write32(0x0718, 0x02020202);
|
||||
+ mchbar_write32(0x071c, 0x03020202);
|
||||
+ mchbar_write32(0x0720, 0x04040403);
|
||||
+ mchbar_write32(0x0724, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0740, 0x02020202);
|
||||
+ mchbar_write32(0x0744, 0x03020202);
|
||||
+ mchbar_write32(0x0748, 0x04040403);
|
||||
+ mchbar_write32(0x074c, 0x04040404);
|
||||
+ mchbar_write32(0x0758, 0x02020202);
|
||||
+ mchbar_write32(0x075c, 0x03020202);
|
||||
+ mchbar_write32(0x0760, 0x04040403);
|
||||
+ mchbar_write32(0x0764, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0780, 0x06060606);
|
||||
+ mchbar_write32(0x0784, 0x09070606);
|
||||
+ mchbar_write32(0x0788, 0x0e0e0c0b);
|
||||
+ mchbar_write32(0x078c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0798, 0x06060606);
|
||||
+ mchbar_write32(0x079c, 0x09070606);
|
||||
+ mchbar_write32(0x07a0, 0x0d0d0c0b);
|
||||
+ mchbar_write32(0x07a4, 0x0d0d0d0d);
|
||||
+
|
||||
+ mchbar_write32(0x07c0, 0x06060606);
|
||||
+ mchbar_write32(0x07c4, 0x09070606);
|
||||
+ mchbar_write32(0x07c8, 0x0e0e0c0b);
|
||||
+ mchbar_write32(0x07cc, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x07d8, 0x06060606);
|
||||
+ mchbar_write32(0x07dc, 0x09070606);
|
||||
+ mchbar_write32(0x07e0, 0x0d0d0c0b);
|
||||
+ mchbar_write32(0x07e4, 0x0d0d0d0d);
|
||||
+
|
||||
+ mchbar_write32(0x0840, 0x06060606);
|
||||
+ mchbar_write32(0x0844, 0x08070606);
|
||||
+ mchbar_write32(0x0848, 0x0e0e0c0a);
|
||||
+ mchbar_write32(0x084c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0858, 0x06060606);
|
||||
+ mchbar_write32(0x085c, 0x08070606);
|
||||
+ mchbar_write32(0x0860, 0x0c0c0b0a);
|
||||
+ mchbar_write32(0x0864, 0x0c0c0c0c);
|
||||
+
|
||||
+ mchbar_write32(0x0880, 0x02020202);
|
||||
+ mchbar_write32(0x0884, 0x03020202);
|
||||
+ mchbar_write32(0x0888, 0x04040403);
|
||||
+ mchbar_write32(0x088c, 0x04040404);
|
||||
+ mchbar_write32(0x0898, 0x02020202);
|
||||
+ mchbar_write32(0x089c, 0x03020202);
|
||||
+ mchbar_write32(0x08a0, 0x04040403);
|
||||
+ mchbar_write32(0x08a4, 0x04040404);
|
||||
+
|
||||
igd_compute_ggc(sysinfo);
|
||||
|
||||
/* Program final memory map (with real values). */
|
||||
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
index aef863f05a..b74765fd9c 100644
|
||||
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step,
|
||||
mchbar += 4;
|
||||
}
|
||||
}
|
||||
-void raminit_rcomp_calibration(const stepping_t stepping) {
|
||||
+void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
|
||||
const int a1step = stepping >= STEPPING_CONVERSION_A1;
|
||||
|
||||
int i;
|
||||
|
||||
+ char magic_comp[2] = {0};
|
||||
+
|
||||
enum {
|
||||
PULL_UP = 0,
|
||||
PULL_DOWN = 1,
|
||||
@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
|
||||
reg = mchbar_read32(0x518);
|
||||
lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
|
||||
lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
|
||||
+ if (i == 1) {
|
||||
+ magic_comp[0] = (reg >> 8) & 0x3f;
|
||||
+ magic_comp[1] = (reg >> 0) & 0x3f;
|
||||
+ }
|
||||
}
|
||||
/* Cleanup? */
|
||||
mchbar_setbits32(0x400, 1 << 3);
|
||||
@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
|
||||
for (channel = 0; channel < 2; ++channel) {
|
||||
for (group = 0; group < 6; ++group) {
|
||||
for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) {
|
||||
- lookup_and_write(
|
||||
- a1step,
|
||||
- lut_idx[channel][group][pu_pd] - 7,
|
||||
- ddr3_lookup_schedule[group][pu_pd],
|
||||
- mchbar);
|
||||
+ if (ddr_type == DDR3) {
|
||||
+ lookup_and_write(
|
||||
+ a1step,
|
||||
+ lut_idx[channel][group][pu_pd] - 7,
|
||||
+ ddr3_lookup_schedule[group][pu_pd],
|
||||
+ mchbar);
|
||||
+ }
|
||||
mchbar += 0x0018;
|
||||
}
|
||||
+ if (ddr_type == DDR2) {
|
||||
+ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24);
|
||||
+ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0);
|
||||
+ }
|
||||
mchbar += 0x0010;
|
||||
/* Channel B knows only the first two groups. */
|
||||
if ((1 == channel) && (1 == group))
|
||||
@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
|
||||
}
|
||||
mchbar += 0x0040;
|
||||
}
|
||||
+
|
||||
+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
|
||||
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
|
||||
}
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-240
@@ -1,240 +0,0 @@
|
||||
From fcfd8484d5b7a50c170a7f5cc8a973c890e48afc Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Tue, 6 Aug 2024 00:50:24 +0100
|
||||
Subject: [PATCH 17/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
|
||||
|
||||
We add this patch:
|
||||
|
||||
commit commit_id_here
|
||||
Author: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Mon May 10 22:40:59 2021 +0200
|
||||
|
||||
nb/intel/gm45: Make DDR2 raminit work
|
||||
|
||||
This patch was original applied, in lbmk, only on coreboot/dell,
|
||||
separately from coreboot/default, which was wasteful because it
|
||||
meant having an entire coreboot tree just for a single board. We
|
||||
did this, because the DDR2 RCOMP fix happened to break DDR3 init
|
||||
on other boards.
|
||||
|
||||
What *this* new patch does on top of Angel's patch, is make sure
|
||||
that their changes only apply to DDR2, while DDR3 behaviour remains
|
||||
unchanged. This means that the Dell Latitude E6400 can be supported
|
||||
in the main coreboot tree, within lbmk.
|
||||
|
||||
Essentially, this patch restores the old behaviour, prior to applying
|
||||
Angel's patch, only when DDR3 memory is used.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/northbridge/intel/gm45/raminit.c | 161 +++++++++---------
|
||||
.../intel/gm45/raminit_rcomp_calibration.c | 9 +-
|
||||
2 files changed, 88 insertions(+), 82 deletions(-)
|
||||
|
||||
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
|
||||
index 7b091cc567..478898564a 100644
|
||||
--- a/src/northbridge/intel/gm45/raminit.c
|
||||
+++ b/src/northbridge/intel/gm45/raminit.c
|
||||
@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
|
||||
reg = (reg & ~(0xf << 10)) | (2 << 10);
|
||||
else
|
||||
reg = (reg & ~(0xf << 10)) | (3 << 10);
|
||||
- reg = (reg & ~(0x7 << 5)) | (2 << 5);
|
||||
+ if (spd_type == DDR2)
|
||||
+ reg = (reg & ~(0x7 << 5)) | (2 << 5);
|
||||
+ else
|
||||
+ reg = (reg & ~(0x7 << 5)) | (3 << 5);
|
||||
} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
|
||||
reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
|
||||
reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
|
||||
@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume)
|
||||
raminit_write_training(timings->mem_clock, dimms, s3resume);
|
||||
}
|
||||
|
||||
- /*
|
||||
- * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
|
||||
- * after receiver enable calibration, otherwise raminit sometimes
|
||||
- * completes with non-working memory.
|
||||
- */
|
||||
- mchbar_write32(0x0530, 0x06060005);
|
||||
- mchbar_write32(0x0680, 0x06060606);
|
||||
- mchbar_write32(0x0684, 0x08070606);
|
||||
- mchbar_write32(0x0688, 0x0e0e0c0a);
|
||||
- mchbar_write32(0x068c, 0x0e0e0e0e);
|
||||
- mchbar_write32(0x0698, 0x06060606);
|
||||
- mchbar_write32(0x069c, 0x08070606);
|
||||
- mchbar_write32(0x06a0, 0x0c0c0b0a);
|
||||
- mchbar_write32(0x06a4, 0x0c0c0c0c);
|
||||
-
|
||||
- mchbar_write32(0x06c0, 0x02020202);
|
||||
- mchbar_write32(0x06c4, 0x03020202);
|
||||
- mchbar_write32(0x06c8, 0x04040403);
|
||||
- mchbar_write32(0x06cc, 0x04040404);
|
||||
- mchbar_write32(0x06d8, 0x02020202);
|
||||
- mchbar_write32(0x06dc, 0x03020202);
|
||||
- mchbar_write32(0x06e0, 0x04040403);
|
||||
- mchbar_write32(0x06e4, 0x04040404);
|
||||
-
|
||||
- mchbar_write32(0x0700, 0x02020202);
|
||||
- mchbar_write32(0x0704, 0x03020202);
|
||||
- mchbar_write32(0x0708, 0x04040403);
|
||||
- mchbar_write32(0x070c, 0x04040404);
|
||||
- mchbar_write32(0x0718, 0x02020202);
|
||||
- mchbar_write32(0x071c, 0x03020202);
|
||||
- mchbar_write32(0x0720, 0x04040403);
|
||||
- mchbar_write32(0x0724, 0x04040404);
|
||||
-
|
||||
- mchbar_write32(0x0740, 0x02020202);
|
||||
- mchbar_write32(0x0744, 0x03020202);
|
||||
- mchbar_write32(0x0748, 0x04040403);
|
||||
- mchbar_write32(0x074c, 0x04040404);
|
||||
- mchbar_write32(0x0758, 0x02020202);
|
||||
- mchbar_write32(0x075c, 0x03020202);
|
||||
- mchbar_write32(0x0760, 0x04040403);
|
||||
- mchbar_write32(0x0764, 0x04040404);
|
||||
-
|
||||
- mchbar_write32(0x0780, 0x06060606);
|
||||
- mchbar_write32(0x0784, 0x09070606);
|
||||
- mchbar_write32(0x0788, 0x0e0e0c0b);
|
||||
- mchbar_write32(0x078c, 0x0e0e0e0e);
|
||||
- mchbar_write32(0x0798, 0x06060606);
|
||||
- mchbar_write32(0x079c, 0x09070606);
|
||||
- mchbar_write32(0x07a0, 0x0d0d0c0b);
|
||||
- mchbar_write32(0x07a4, 0x0d0d0d0d);
|
||||
-
|
||||
- mchbar_write32(0x07c0, 0x06060606);
|
||||
- mchbar_write32(0x07c4, 0x09070606);
|
||||
- mchbar_write32(0x07c8, 0x0e0e0c0b);
|
||||
- mchbar_write32(0x07cc, 0x0e0e0e0e);
|
||||
- mchbar_write32(0x07d8, 0x06060606);
|
||||
- mchbar_write32(0x07dc, 0x09070606);
|
||||
- mchbar_write32(0x07e0, 0x0d0d0c0b);
|
||||
- mchbar_write32(0x07e4, 0x0d0d0d0d);
|
||||
-
|
||||
- mchbar_write32(0x0840, 0x06060606);
|
||||
- mchbar_write32(0x0844, 0x08070606);
|
||||
- mchbar_write32(0x0848, 0x0e0e0c0a);
|
||||
- mchbar_write32(0x084c, 0x0e0e0e0e);
|
||||
- mchbar_write32(0x0858, 0x06060606);
|
||||
- mchbar_write32(0x085c, 0x08070606);
|
||||
- mchbar_write32(0x0860, 0x0c0c0b0a);
|
||||
- mchbar_write32(0x0864, 0x0c0c0c0c);
|
||||
-
|
||||
- mchbar_write32(0x0880, 0x02020202);
|
||||
- mchbar_write32(0x0884, 0x03020202);
|
||||
- mchbar_write32(0x0888, 0x04040403);
|
||||
- mchbar_write32(0x088c, 0x04040404);
|
||||
- mchbar_write32(0x0898, 0x02020202);
|
||||
- mchbar_write32(0x089c, 0x03020202);
|
||||
- mchbar_write32(0x08a0, 0x04040403);
|
||||
- mchbar_write32(0x08a4, 0x04040404);
|
||||
+ if (sysinfo->spd_type == DDR2) {
|
||||
+ /*
|
||||
+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
|
||||
+ * after receiver enable calibration, otherwise raminit sometimes
|
||||
+ * completes with non-working memory.
|
||||
+ */
|
||||
+ mchbar_write32(0x0530, 0x06060005);
|
||||
+ mchbar_write32(0x0680, 0x06060606);
|
||||
+ mchbar_write32(0x0684, 0x08070606);
|
||||
+ mchbar_write32(0x0688, 0x0e0e0c0a);
|
||||
+ mchbar_write32(0x068c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0698, 0x06060606);
|
||||
+ mchbar_write32(0x069c, 0x08070606);
|
||||
+ mchbar_write32(0x06a0, 0x0c0c0b0a);
|
||||
+ mchbar_write32(0x06a4, 0x0c0c0c0c);
|
||||
+
|
||||
+ mchbar_write32(0x06c0, 0x02020202);
|
||||
+ mchbar_write32(0x06c4, 0x03020202);
|
||||
+ mchbar_write32(0x06c8, 0x04040403);
|
||||
+ mchbar_write32(0x06cc, 0x04040404);
|
||||
+ mchbar_write32(0x06d8, 0x02020202);
|
||||
+ mchbar_write32(0x06dc, 0x03020202);
|
||||
+ mchbar_write32(0x06e0, 0x04040403);
|
||||
+ mchbar_write32(0x06e4, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0700, 0x02020202);
|
||||
+ mchbar_write32(0x0704, 0x03020202);
|
||||
+ mchbar_write32(0x0708, 0x04040403);
|
||||
+ mchbar_write32(0x070c, 0x04040404);
|
||||
+ mchbar_write32(0x0718, 0x02020202);
|
||||
+ mchbar_write32(0x071c, 0x03020202);
|
||||
+ mchbar_write32(0x0720, 0x04040403);
|
||||
+ mchbar_write32(0x0724, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0740, 0x02020202);
|
||||
+ mchbar_write32(0x0744, 0x03020202);
|
||||
+ mchbar_write32(0x0748, 0x04040403);
|
||||
+ mchbar_write32(0x074c, 0x04040404);
|
||||
+ mchbar_write32(0x0758, 0x02020202);
|
||||
+ mchbar_write32(0x075c, 0x03020202);
|
||||
+ mchbar_write32(0x0760, 0x04040403);
|
||||
+ mchbar_write32(0x0764, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0780, 0x06060606);
|
||||
+ mchbar_write32(0x0784, 0x09070606);
|
||||
+ mchbar_write32(0x0788, 0x0e0e0c0b);
|
||||
+ mchbar_write32(0x078c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0798, 0x06060606);
|
||||
+ mchbar_write32(0x079c, 0x09070606);
|
||||
+ mchbar_write32(0x07a0, 0x0d0d0c0b);
|
||||
+ mchbar_write32(0x07a4, 0x0d0d0d0d);
|
||||
+
|
||||
+ mchbar_write32(0x07c0, 0x06060606);
|
||||
+ mchbar_write32(0x07c4, 0x09070606);
|
||||
+ mchbar_write32(0x07c8, 0x0e0e0c0b);
|
||||
+ mchbar_write32(0x07cc, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x07d8, 0x06060606);
|
||||
+ mchbar_write32(0x07dc, 0x09070606);
|
||||
+ mchbar_write32(0x07e0, 0x0d0d0c0b);
|
||||
+ mchbar_write32(0x07e4, 0x0d0d0d0d);
|
||||
+
|
||||
+ mchbar_write32(0x0840, 0x06060606);
|
||||
+ mchbar_write32(0x0844, 0x08070606);
|
||||
+ mchbar_write32(0x0848, 0x0e0e0c0a);
|
||||
+ mchbar_write32(0x084c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0858, 0x06060606);
|
||||
+ mchbar_write32(0x085c, 0x08070606);
|
||||
+ mchbar_write32(0x0860, 0x0c0c0b0a);
|
||||
+ mchbar_write32(0x0864, 0x0c0c0c0c);
|
||||
+
|
||||
+ mchbar_write32(0x0880, 0x02020202);
|
||||
+ mchbar_write32(0x0884, 0x03020202);
|
||||
+ mchbar_write32(0x0888, 0x04040403);
|
||||
+ mchbar_write32(0x088c, 0x04040404);
|
||||
+ mchbar_write32(0x0898, 0x02020202);
|
||||
+ mchbar_write32(0x089c, 0x03020202);
|
||||
+ mchbar_write32(0x08a0, 0x04040403);
|
||||
+ mchbar_write32(0x08a4, 0x04040404);
|
||||
+ }
|
||||
|
||||
igd_compute_ggc(sysinfo);
|
||||
|
||||
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
index b74765fd9c..5d4505e063 100644
|
||||
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
|
||||
reg = mchbar_read32(0x518);
|
||||
lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
|
||||
lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
|
||||
- if (i == 1) {
|
||||
+ if ((i == 1) && (ddr_type == DDR2)) {
|
||||
magic_comp[0] = (reg >> 8) & 0x3f;
|
||||
magic_comp[1] = (reg >> 0) & 0x3f;
|
||||
}
|
||||
@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
|
||||
}
|
||||
mchbar += 0x0040;
|
||||
}
|
||||
-
|
||||
- mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
|
||||
- mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
|
||||
+ if (ddr_type == DDR2) {
|
||||
+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
|
||||
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
|
||||
+ }
|
||||
}
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-51
@@ -1,51 +0,0 @@
|
||||
From 499885b662b703c472309f64c123d99e65ebe9d2 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Mon, 20 May 2024 10:24:16 -0600
|
||||
Subject: [PATCH 18/51] mb/dell/e6400: Use 100 MHz reference clock for display
|
||||
|
||||
The E6400 uses a 100 MHz reference clock for spread spectrum support on
|
||||
LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
|
||||
the more common 1280 x 800 display panels, the numerical error was not
|
||||
large enough to cause noticable issues, but the actual pixel clock
|
||||
frequency derived from a 100 MHz reference using PLL configs calculated
|
||||
assuming a 96 MHz reference was not close enough for 1440 x 900 panels,
|
||||
which require a much higher pixel clock. This resulted in a garbled
|
||||
display in the pre-OS graphics environment provided by libgfxinit.
|
||||
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/gm45_latitude/Kconfig | 2 ++
|
||||
src/northbridge/intel/gm45/Kconfig | 4 ++++
|
||||
2 files changed, 6 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
|
||||
index edc79b0d43..5020744990 100644
|
||||
--- a/src/mainboard/dell/gm45_latitude/Kconfig
|
||||
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
|
||||
@@ -22,6 +22,8 @@ config BOARD_DELL_E6400
|
||||
select BOARD_DELL_GM45_LATITUDE_COMMON
|
||||
|
||||
if BOARD_DELL_GM45_LATITUDE_COMMON
|
||||
+config INTEL_GMA_DPLL_REF_FREQ
|
||||
+ default 100000000
|
||||
|
||||
config MAINBOARD_DIR
|
||||
default "dell/gm45_latitude"
|
||||
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
|
||||
index a776217475..35e89b0c88 100644
|
||||
--- a/src/northbridge/intel/gm45/Kconfig
|
||||
+++ b/src/northbridge/intel/gm45/Kconfig
|
||||
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
|
||||
|
||||
if NORTHBRIDGE_INTEL_GM45
|
||||
|
||||
+config INTEL_GMA_DPLL_REF_FREQ
|
||||
+ int
|
||||
+ default 96000000
|
||||
+
|
||||
config VBOOT
|
||||
select VBOOT_STARTS_IN_BOOTBLOCK
|
||||
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,52 +0,0 @@
|
||||
From db3148d6762fb16ca79d9bfb3df51210e04a580e Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Mon, 12 Aug 2024 02:15:24 +0100
|
||||
Subject: [PATCH 19/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
|
||||
|
||||
set it to 96MHz. fixes the following build error when
|
||||
building for x4x boards e.g. gigabyte ga-g41m-es2l:
|
||||
|
||||
hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config"
|
||||
make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1
|
||||
|
||||
this error was introduced when merging coreboot/dell
|
||||
into coreboot/default in lbmk. nicholas chin's fix in lbmk
|
||||
was as follows:
|
||||
|
||||
commit 8629873a6043067affc137be275b7aa69cb1f10c
|
||||
Author: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Mon May 20 10:46:25 2024 -0600
|
||||
|
||||
Fix E6400 display issue with 1440 x 900 panel
|
||||
|
||||
this currently corresponds to the patch in lbmk,
|
||||
as of 12 august 2024:
|
||||
|
||||
0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
|
||||
|
||||
The assumption prior to Nicholas's fix was 96MHz, so set
|
||||
it accordingly on x4x northbridge.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/northbridge/intel/x4x/Kconfig | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
|
||||
index 6fa4551957..646af3510b 100644
|
||||
--- a/src/northbridge/intel/x4x/Kconfig
|
||||
+++ b/src/northbridge/intel/x4x/Kconfig
|
||||
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
|
||||
|
||||
if NORTHBRIDGE_INTEL_X4X
|
||||
|
||||
+config INTEL_GMA_DPLL_REF_FREQ
|
||||
+ int
|
||||
+ default 96000000
|
||||
+
|
||||
config CBFS_SIZE
|
||||
default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
|
||||
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,332 +0,0 @@
|
||||
From da070b56c01b5ffe35d8dfdac2e7681be5392fc2 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Thu, 26 Sep 2024 19:51:25 -0600
|
||||
Subject: [PATCH 20/51] mb/dell/gm45_latitudes: Add E4300 variant
|
||||
|
||||
Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/gm45_latitude/Kconfig | 5 +
|
||||
src/mainboard/dell/gm45_latitude/Kconfig.name | 3 +
|
||||
.../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes
|
||||
.../variants/e4300/gma-mainboard.ads | 17 +++
|
||||
.../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++
|
||||
.../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++
|
||||
.../variants/e4300/overridetree.cb | 10 ++
|
||||
7 files changed, 210 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
|
||||
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
|
||||
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
|
||||
|
||||
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
|
||||
index 5020744990..d27d5728a8 100644
|
||||
--- a/src/mainboard/dell/gm45_latitude/Kconfig
|
||||
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
|
||||
@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
|
||||
config BOARD_DELL_E6400
|
||||
select BOARD_DELL_GM45_LATITUDE_COMMON
|
||||
|
||||
+config BOARD_DELL_E4300
|
||||
+ select BOARD_DELL_GM45_LATITUDE_COMMON
|
||||
+
|
||||
if BOARD_DELL_GM45_LATITUDE_COMMON
|
||||
config INTEL_GMA_DPLL_REF_FREQ
|
||||
default 100000000
|
||||
@@ -30,12 +33,14 @@ config MAINBOARD_DIR
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "Latitude E6400" if BOARD_DELL_E6400
|
||||
+ default "Latitude E4300" if BOARD_DELL_E4300
|
||||
|
||||
config OVERRIDE_DEVICETREE
|
||||
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
|
||||
config VARIANT_DIR
|
||||
default "e6400" if BOARD_DELL_E6400
|
||||
+ default "e4300" if BOARD_DELL_E4300
|
||||
|
||||
config USBDEBUG_HCD_INDEX
|
||||
default 1
|
||||
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
|
||||
index aefe777109..4dc95f46be 100644
|
||||
--- a/src/mainboard/dell/gm45_latitude/Kconfig.name
|
||||
+++ b/src/mainboard/dell/gm45_latitude/Kconfig.name
|
||||
@@ -1,4 +1,7 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
+config BOARD_DELL_E4300
|
||||
+ bool "Latitude E4300"
|
||||
+
|
||||
config BOARD_DELL_E6400
|
||||
bool "Latitude E6400"
|
||||
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3
|
||||
GIT binary patch
|
||||
literal 3881
|
||||
zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+
|
||||
zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5a<biIGGii6#d8gP4#QmGpeGyBx))(i;53
|
||||
zx0(69nR)Nco0&Inc1d4HFVD7b?CrX@org342aOf$sh&<9U7NP<Sl8a$zN4diQ+5M?
|
||||
z9rN*fa`GZDAW257d6jcVwtw%wp<VsFPss9IbIT6VyT7@GKQuhTyNCDm-+uql-l6R9
|
||||
zaA9y{CEr#U=-)Ruz;_Pq?H?H$9GyPr&Fjey7akuO+O>Nhx3i7B*>RjEs#<v0-hG36
|
||||
zcy@TCu#&g$*~7O8nNhxFaCC5F|KPw%gBc7st!SzQND;)Ih9pfkBd$T$U~A~qu#ltO
|
||||
zMczfDhAs`eH4JHpsJLH4lZIP4`dyfi4M|pkg+SayZ(n(7kunGFvl<qe=w81$=+A#a
|
||||
zN=hgb2&njUcPLB!=P$(o-$={^mxQGIHvtVGBS4IU%YyNVhd3krw*m^es@B12UftTZ
|
||||
zHsf}zTi<zK_vS6VeYx!qdQTpH>PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC
|
||||
zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpD<v6uK&w=s5=N^P
|
||||
zn1nKYZrHyr#A-t5vRX$dPN$Pl=yivfA{67CP>h$)OQqAIh6jOwCxuw)qvS0N+Nk!?
|
||||
zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E
|
||||
z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u
|
||||
z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L<DD#SV;6@`cGC4?jgJ8YLq>~qi^
|
||||
z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I<Q#e&+8Yy!=BeKi&0@sfte<K0&
|
||||
zMgsgs0(vE~6cP&098SWEom4ZZF%<l!OeEuw4n?=)Y_tg#&wy^{e@5{s`F9qRm`5m;
|
||||
zi_|4iQq@4&R8mD)tJIvCw3$`@-B9JV=`1}s_;B_rjtcVXpQ!o`MAJ$M5w65C7t<Ku
|
||||
z%xfIo$p$+0N}Qe(C7MY#!0SQ1({^-qFj5ylEHjhwn>8}OhGtOw#1e$Fn9w<r1Zp}l
|
||||
zPz$#mOP$ow*1(UHvmCGVz;T^IRnSxa*6jz+_oSD)xmT|Cbl&YcJ5M&d?&+&NDI2Y0
|
||||
zO0ai&>sUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6
|
||||
z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e%
|
||||
zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D
|
||||
z!+P0Z#|`^S!}`Hs7Yw^5X*DKUOVaL7TBAv}d|dV9^O8rYn%=4o&5GjdSWeb`yeyf7
|
||||
zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG*
|
||||
zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg
|
||||
zI{c?gKNv~R$<jgIlQvzm9GD`y{Dh<T(H)!WlUUWvtFvzDqaVV>&eHj<So5w}UG%+7
|
||||
zt=J~1YHpT3TjRY{XlrmCz6QBZ$WqGr>8!uus22Br_GkCD$Q)pf!<P$30Ez;o=qDzr
|
||||
z7@f;LJ+ZPlo=?}4PvMm&OKLGLZ0h1&n7U8@9GP~;8!wz(OqQ<s6e;@8hfYU0ht*9>
|
||||
zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K<j&AXad#XeO8mgw(v
|
||||
z_Gj1VBJZIpZ<>`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692<oYlGx5_cte6LX
|
||||
JE5(FU=`RLB=-&VU
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..89b81b3d69
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
|
||||
@@ -0,0 +1,17 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (DP2, -- dock DP
|
||||
+ Analog, -- mainboard VGA
|
||||
+ LVDS,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..b50f8da0b5
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
|
||||
@@ -0,0 +1,138 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_NATIVE,
|
||||
+ .gpio1 = GPIO_MODE_GPIO,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_GPIO,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_GPIO,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_NATIVE,
|
||||
+ .gpio16 = GPIO_MODE_NATIVE,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_GPIO,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_GPIO,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_NATIVE,
|
||||
+ .gpio30 = GPIO_MODE_NATIVE,
|
||||
+ .gpio31 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio1 = GPIO_DIR_INPUT,
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio3 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio5 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio17 = GPIO_DIR_INPUT,
|
||||
+ .gpio18 = GPIO_DIR_INPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio20 = GPIO_DIR_INPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio1 = GPIO_INVERT,
|
||||
+ .gpio7 = GPIO_INVERT,
|
||||
+ .gpio8 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_NATIVE,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_NATIVE,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_NATIVE,
|
||||
+ .gpio46 = GPIO_MODE_NATIVE,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_NATIVE,
|
||||
+ .gpio52 = GPIO_MODE_GPIO,
|
||||
+ .gpio53 = GPIO_MODE_GPIO,
|
||||
+ .gpio54 = GPIO_MODE_NATIVE,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_GPIO,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_INPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_INPUT,
|
||||
+ .gpio52 = GPIO_DIR_INPUT,
|
||||
+ .gpio53 = GPIO_DIR_INPUT,
|
||||
+ .gpio56 = GPIO_DIR_INPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..a9948a93dd
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
|
||||
@@ -0,0 +1,37 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ /* coreboot specific header */
|
||||
+ 0x111d76b2, /* IDT 92HD71B7X */
|
||||
+ 0x1028024d, /* Subsystem ID */
|
||||
+ 13, /* Number of entries */
|
||||
+
|
||||
+ /* Pin Widget Verb Table */
|
||||
+
|
||||
+ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
|
||||
+ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
|
||||
+ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
|
||||
+ AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
|
||||
+ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
|
||||
+ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
|
||||
+ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
|
||||
+ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
|
||||
+ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
|
||||
+ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
|
||||
+ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[] = {
|
||||
+ 0x00170500, /* power up codec */
|
||||
+ 0x00d70500, /* power up speakers */
|
||||
+ 0x00d70102, /* select mixer (input 0x2) for speakers */
|
||||
+ 0x00d70740, /* enable speakers output */
|
||||
+ 0x02770720, /* enable beep input */
|
||||
+ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
|
||||
+ 0x00d37000, /* unmute speakers */
|
||||
+};
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..20dfa245fb
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
|
||||
@@ -0,0 +1,10 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+chip northbridge/intel/gm45
|
||||
+ device domain 0 on
|
||||
+ subsystemid 0x1028 0x024d inherit
|
||||
+ chip southbridge/intel/i82801ix
|
||||
+ device pci 1c.2 off end # PCIe Port #3
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-70
@@ -1,70 +0,0 @@
|
||||
From 78cf7a8186ad389f6402da9e55f94830f368fcea Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Fri, 3 May 2024 16:31:12 -0600
|
||||
Subject: [PATCH 21/51] mb/dell: Add S3 SMI handler for Dell Latitudes
|
||||
|
||||
Integrate the previously added mec5035_smi_sleep() function into
|
||||
mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
|
||||
The E6400 does not require the EC command to sucessfully suspend and
|
||||
resume from S3, though sending it does enable the breathing effect on
|
||||
the power LED while in S3. Without it, all LEDs turn off during S3.
|
||||
|
||||
Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/gm45_latitude/smihandler.c | 9 +++++++++
|
||||
src/mainboard/dell/haswell_latitude/smihandler.c | 9 +++++++++
|
||||
src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
|
||||
3 files changed, 27 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c
|
||||
create mode 100644 src/mainboard/dell/haswell_latitude/smihandler.c
|
||||
create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
|
||||
|
||||
diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
|
||||
new file mode 100644
|
||||
index 0000000000..00e55b51db
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/gm45_latitude/smihandler.c
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <cpu/x86/smm.h>
|
||||
+#include <ec/dell/mec5035/mec5035.h>
|
||||
+
|
||||
+void mainboard_smi_sleep(u8 slp_typ)
|
||||
+{
|
||||
+ mec5035_smi_sleep(slp_typ);
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/haswell_latitude/smihandler.c b/src/mainboard/dell/haswell_latitude/smihandler.c
|
||||
new file mode 100644
|
||||
index 0000000000..00e55b51db
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/haswell_latitude/smihandler.c
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <cpu/x86/smm.h>
|
||||
+#include <ec/dell/mec5035/mec5035.h>
|
||||
+
|
||||
+void mainboard_smi_sleep(u8 slp_typ)
|
||||
+{
|
||||
+ mec5035_smi_sleep(slp_typ);
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
|
||||
new file mode 100644
|
||||
index 0000000000..00e55b51db
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <cpu/x86/smm.h>
|
||||
+#include <ec/dell/mec5035/mec5035.h>
|
||||
+
|
||||
+void mainboard_smi_sleep(u8 slp_typ)
|
||||
+{
|
||||
+ mec5035_smi_sleep(slp_typ);
|
||||
+}
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,31 +0,0 @@
|
||||
From 7f131cd791eb2dcf68f0e1e9049cc5b4c301232b Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Tue, 31 Dec 2024 14:42:24 +0000
|
||||
Subject: [PATCH 22/51] Disable compression on refcode insertion
|
||||
|
||||
Compression is not reliably reproducible. In an lbmk release
|
||||
context, this means we cannot rely on vendorfile insertion.
|
||||
|
||||
Therefore, use uncompressed refcode.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
Makefile.mk | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/Makefile.mk b/Makefile.mk
|
||||
index dbad313911..8f541ad187 100644
|
||||
--- a/Makefile.mk
|
||||
+++ b/Makefile.mk
|
||||
@@ -1432,7 +1432,7 @@ endif
|
||||
cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
|
||||
$(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
|
||||
$(CONFIG_CBFS_PREFIX)/refcode-type := stage
|
||||
-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG)
|
||||
+$(CONFIG_CBFS_PREFIX)/refcode-compression := none
|
||||
|
||||
cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
|
||||
vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-187
@@ -1,187 +0,0 @@
|
||||
From 0ef9596d987ae2f9d5d63f7961b60e7d05529d1b Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 21 Apr 2025 02:58:47 +0100
|
||||
Subject: [PATCH 23/51] nb/intel/*: Disable stack overflow debug options
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/northbridge/intel/e7505/Kconfig | 9 +++++++++
|
||||
src/northbridge/intel/gm45/Kconfig | 9 +++++++++
|
||||
src/northbridge/intel/haswell/Kconfig | 9 +++++++++
|
||||
src/northbridge/intel/i440bx/Kconfig | 13 +++++++++++++
|
||||
src/northbridge/intel/i945/Kconfig | 9 +++++++++
|
||||
src/northbridge/intel/ironlake/Kconfig | 9 +++++++++
|
||||
src/northbridge/intel/pineview/Kconfig | 9 +++++++++
|
||||
src/northbridge/intel/sandybridge/Kconfig | 9 +++++++++
|
||||
src/northbridge/intel/x4x/Kconfig | 9 +++++++++
|
||||
9 files changed, 85 insertions(+)
|
||||
|
||||
diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
|
||||
index 039a7396f8..ddcb986f10 100644
|
||||
--- a/src/northbridge/intel/e7505/Kconfig
|
||||
+++ b/src/northbridge/intel/e7505/Kconfig
|
||||
@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505
|
||||
select NO_CBFS_MCACHE
|
||||
select SMM_TSEG
|
||||
select NEED_SMALL_2MB_PAGE_TABLES
|
||||
+
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
|
||||
index 35e89b0c88..c5456d0ddf 100644
|
||||
--- a/src/northbridge/intel/gm45/Kconfig
|
||||
+++ b/src/northbridge/intel/gm45/Kconfig
|
||||
@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE
|
||||
config FIXED_EPBAR_MMIO_BASE
|
||||
default 0xfed19000
|
||||
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
endif
|
||||
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
|
||||
index d67cc14660..fa22e35ccb 100644
|
||||
--- a/src/northbridge/intel/haswell/Kconfig
|
||||
+++ b/src/northbridge/intel/haswell/Kconfig
|
||||
@@ -9,6 +9,15 @@ config NORTHBRIDGE_INTEL_HASWELL
|
||||
|
||||
if NORTHBRIDGE_INTEL_HASWELL
|
||||
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
config USE_NATIVE_RAMINIT
|
||||
bool "[NOT COMPLETE] Use native raminit"
|
||||
default n
|
||||
diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
|
||||
index dbb2d7436b..5e9418b6a9 100644
|
||||
--- a/src/northbridge/intel/i440bx/Kconfig
|
||||
+++ b/src/northbridge/intel/i440bx/Kconfig
|
||||
@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM
|
||||
If your board has 4 DIMM slots, you must use select this option, in
|
||||
your Kconfig file of the board. On boards with 3 DIMM slots,
|
||||
do _not_ select this option.
|
||||
+
|
||||
+if NORTHBRIDGE_INTEL_I440BX
|
||||
+
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+endif
|
||||
diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
|
||||
index c4e17f90bf..b12f5be091 100644
|
||||
--- a/src/northbridge/intel/i945/Kconfig
|
||||
+++ b/src/northbridge/intel/i945/Kconfig
|
||||
@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE
|
||||
config FIXED_EPBAR_MMIO_BASE
|
||||
default 0xfed19000
|
||||
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
endif
|
||||
diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
|
||||
index 39566a6e5f..f46acf6937 100644
|
||||
--- a/src/northbridge/intel/ironlake/Kconfig
|
||||
+++ b/src/northbridge/intel/ironlake/Kconfig
|
||||
@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE
|
||||
config FIXED_EPBAR_MMIO_BASE
|
||||
default 0xfed19000
|
||||
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
endif
|
||||
diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
|
||||
index a05b866dad..50e3a7cdb9 100644
|
||||
--- a/src/northbridge/intel/pineview/Kconfig
|
||||
+++ b/src/northbridge/intel/pineview/Kconfig
|
||||
@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE
|
||||
config DOMAIN_RESOURCE_32BIT_LIMIT
|
||||
default 0xfec00000
|
||||
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
endif
|
||||
diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
|
||||
index 9972a43da0..fe4ac5106c 100644
|
||||
--- a/src/northbridge/intel/sandybridge/Kconfig
|
||||
+++ b/src/northbridge/intel/sandybridge/Kconfig
|
||||
@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX
|
||||
default 2 if IGD_DEFAULT_UMA_SIZE_96MB
|
||||
default 3 if IGD_DEFAULT_UMA_SIZE_128MB
|
||||
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
endif
|
||||
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
|
||||
index 646af3510b..069fa0244d 100644
|
||||
--- a/src/northbridge/intel/x4x/Kconfig
|
||||
+++ b/src/northbridge/intel/x4x/Kconfig
|
||||
@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE
|
||||
config FIXED_EPBAR_MMIO_BASE
|
||||
default 0xfed19000
|
||||
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
endif
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,708 +0,0 @@
|
||||
From 57f57075c69ce6e1caf9d0daf991b1f373d7f04b Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Mon, 30 Sep 2024 20:44:38 -0400
|
||||
Subject: [PATCH 24/51] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
|
||||
|
||||
Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/optiplex_780/Kconfig | 40 ++++
|
||||
src/mainboard/dell/optiplex_780/Kconfig.name | 4 +
|
||||
src/mainboard/dell/optiplex_780/Makefile.mk | 10 +
|
||||
src/mainboard/dell/optiplex_780/acpi/ec.asl | 5 +
|
||||
.../dell/optiplex_780/acpi/ich10_pci_irqs.asl | 32 ++++
|
||||
.../dell/optiplex_780/acpi/superio.asl | 18 ++
|
||||
.../dell/optiplex_780/board_info.txt | 6 +
|
||||
src/mainboard/dell/optiplex_780/cmos.default | 8 +
|
||||
src/mainboard/dell/optiplex_780/cmos.layout | 72 ++++++++
|
||||
src/mainboard/dell/optiplex_780/cstates.c | 8 +
|
||||
src/mainboard/dell/optiplex_780/devicetree.cb | 63 +++++++
|
||||
src/mainboard/dell/optiplex_780/dsdt.asl | 26 +++
|
||||
.../dell/optiplex_780/gma-mainboard.ads | 16 ++
|
||||
.../optiplex_780/variants/780_mt/data.vbt | Bin 0 -> 1917 bytes
|
||||
.../optiplex_780/variants/780_mt/early_init.c | 12 ++
|
||||
.../dell/optiplex_780/variants/780_mt/gpio.c | 174 ++++++++++++++++++
|
||||
.../optiplex_780/variants/780_mt/hda_verb.c | 26 +++
|
||||
.../variants/780_mt/overridetree.cb | 10 +
|
||||
18 files changed, 530 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/Kconfig
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/cmos.default
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/cstates.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..2d06c75c9a
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/Kconfig
|
||||
@@ -0,0 +1,40 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+config BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
+ def_bool n
|
||||
+ select BOARD_ROMSIZE_KB_8192
|
||||
+ select CPU_INTEL_SOCKET_LGA775
|
||||
+ select DRIVERS_I2C_CK505
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select MAINBOARD_USES_IFD_GBE_REGION
|
||||
+ select NORTHBRIDGE_INTEL_X4X
|
||||
+ select PCIEXP_ASPM
|
||||
+ select PCIEXP_CLK_PM
|
||||
+ select SOUTHBRIDGE_INTEL_I82801JX
|
||||
+
|
||||
+config BOARD_DELL_OPTIPLEX_780_MT
|
||||
+ select BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
+
|
||||
+if BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,2e22"
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "dell/optiplex_780"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
|
||||
+
|
||||
+config OVERRIDE_DEVICETREE
|
||||
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
+
|
||||
+config VARIANT_DIR
|
||||
+ default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
|
||||
+
|
||||
+endif # BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..db7f2e8fe3
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
|
||||
@@ -0,0 +1,4 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+config BOARD_DELL_OPTIPLEX_780_MT
|
||||
+ bool "OptiPlex 780 MT"
|
||||
diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk
|
||||
new file mode 100644
|
||||
index 0000000000..d462995d75
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/Makefile.mk
|
||||
@@ -0,0 +1,10 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+ramstage-y += cstates.c
|
||||
+romstage-y += variants/$(VARIANT_DIR)/gpio.c
|
||||
+
|
||||
+bootblock-y += variants/$(VARIANT_DIR)/early_init.c
|
||||
+romstage-y += variants/$(VARIANT_DIR)/early_init.c
|
||||
+
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
|
||||
diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..479296cb76
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl
|
||||
@@ -0,0 +1,5 @@
|
||||
+/* SPDX-License-Identifier: CC-PDDC */
|
||||
+
|
||||
+/* Please update the license if adding licensable material. */
|
||||
+
|
||||
+/* dummy */
|
||||
diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
|
||||
new file mode 100644
|
||||
index 0000000000..b7588dcc41
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
|
||||
@@ -0,0 +1,32 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+/* This is board specific information:
|
||||
+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
|
||||
+ */
|
||||
+
|
||||
+If (PICM) {
|
||||
+ Return (Package() {
|
||||
+ /* PCI slot */
|
||||
+ Package() { 0x0001ffff, 0, 0, 0x14},
|
||||
+ Package() { 0x0001ffff, 1, 0, 0x15},
|
||||
+ Package() { 0x0001ffff, 2, 0, 0x16},
|
||||
+ Package() { 0x0001ffff, 3, 0, 0x17},
|
||||
+
|
||||
+ Package() { 0x0002ffff, 0, 0, 0x15},
|
||||
+ Package() { 0x0002ffff, 1, 0, 0x16},
|
||||
+ Package() { 0x0002ffff, 2, 0, 0x17},
|
||||
+ Package() { 0x0002ffff, 3, 0, 0x14},
|
||||
+ })
|
||||
+} Else {
|
||||
+ Return (Package() {
|
||||
+ Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
|
||||
+ Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
|
||||
+ Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
|
||||
+ Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
|
||||
+
|
||||
+ Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
|
||||
+ Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
|
||||
+ Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
|
||||
+ Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
|
||||
+ })
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..9f3900b86c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl
|
||||
@@ -0,0 +1,18 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#undef SUPERIO_DEV
|
||||
+#undef SUPERIO_PNP_BASE
|
||||
+#undef IT8720F_SHOW_SP1
|
||||
+#undef IT8720F_SHOW_SP2
|
||||
+#undef IT8720F_SHOW_EC
|
||||
+#undef IT8720F_SHOW_KBCK
|
||||
+#undef IT8720F_SHOW_KBCM
|
||||
+#undef IT8720F_SHOW_GPIO
|
||||
+#undef IT8720F_SHOW_CIR
|
||||
+#define SUPERIO_DEV SIO0
|
||||
+#define SUPERIO_PNP_BASE 0x2e
|
||||
+#define IT8720F_SHOW_EC 1
|
||||
+#define IT8720F_SHOW_KBCK 1
|
||||
+#define IT8720F_SHOW_KBCM 1
|
||||
+#define IT8720F_SHOW_GPIO 1
|
||||
+#include <superio/ite/it8720f/acpi/superio.asl>
|
||||
diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..aaf657b583
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/board_info.txt
|
||||
@@ -0,0 +1,6 @@
|
||||
+Category: desktop
|
||||
+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1
|
||||
+ROM package: SOIC-8
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..23f0e55f3e
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/cmos.default
|
||||
@@ -0,0 +1,8 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Disable
|
||||
+nmi=Enable
|
||||
+sata_mode=AHCI
|
||||
+gfx_uma_size=64M
|
||||
diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..9f5012adb4
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/cmos.layout
|
||||
@@ -0,0 +1,72 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 10 sata_mode
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+411 1 e 1 nmi
|
||||
+
|
||||
+# coreboot config options: cpu
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 4 e 11 gfx_uma_size
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+10 0 AHCI
|
||||
+10 1 Compatible
|
||||
+11 1 4M
|
||||
+11 2 8M
|
||||
+11 3 16M
|
||||
+11 4 32M
|
||||
+11 5 48M
|
||||
+11 6 64M
|
||||
+11 7 128M
|
||||
+11 8 256M
|
||||
+11 9 96M
|
||||
+11 10 160M
|
||||
+11 11 224M
|
||||
+11 12 352M
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 983 984
|
||||
diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c
|
||||
new file mode 100644
|
||||
index 0000000000..4adf0edc63
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/cstates.c
|
||||
@@ -0,0 +1,8 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpigen.h>
|
||||
+
|
||||
+int get_cst_entries(const acpi_cstate_t **entries)
|
||||
+{
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..95e3bd517c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/devicetree.cb
|
||||
@@ -0,0 +1,63 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+chip northbridge/intel/x4x
|
||||
+ device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster
|
||||
+ device domain 0 on
|
||||
+ ops x4x_pci_domain_ops # PCI domain
|
||||
+ subsystemid 0x8086 0x0028 inherit
|
||||
+ device pci 0.0 on end # Host Bridge
|
||||
+ device pci 1.0 on end # PCIe x16 2.0 slot
|
||||
+ device pci 2.0 on end # Integrated graphics controller
|
||||
+ device pci 2.1 on end # Integrated graphics controller 2
|
||||
+ device pci 3.0 off end # ME
|
||||
+ device pci 3.1 off end # ME
|
||||
+ chip southbridge/intel/i82801jx # ICH10
|
||||
+ register "gpe0_en" = "0x40"
|
||||
+
|
||||
+ # Set AHCI mode.
|
||||
+ register "sata_port_map" = "0x3f"
|
||||
+ register "sata_clock_request" = "1"
|
||||
+
|
||||
+ # Enable PCIe ports 0,1 as slots.
|
||||
+ register "pcie_slot_implemented" = "0x3"
|
||||
+
|
||||
+ device pci 19.0 on end # GBE
|
||||
+ device pci 1a.0 on end # USB
|
||||
+ device pci 1a.1 on end # USB
|
||||
+ device pci 1a.2 on end # USB
|
||||
+ device pci 1a.7 on end # USB
|
||||
+ device pci 1b.0 on end # Audio
|
||||
+ device pci 1c.0 off end # PCIe 1
|
||||
+ device pci 1c.1 off end # PCIe 2
|
||||
+ device pci 1c.2 off end # PCIe 3
|
||||
+ device pci 1c.3 off end # PCIe 4
|
||||
+ device pci 1c.4 off end # PCIe 5
|
||||
+ device pci 1c.5 off end # PCIe 6
|
||||
+ device pci 1d.0 on end # USB
|
||||
+ device pci 1d.1 on end # USB
|
||||
+ device pci 1d.2 on end # USB
|
||||
+ device pci 1d.7 on end # USB
|
||||
+ device pci 1e.0 on end # PCI bridge
|
||||
+ device pci 1f.0 on end # LPC bridge
|
||||
+ device pci 1f.2 on end # SATA (IDE: port 0-3, AHCI/RAID: 0-5)
|
||||
+ device pci 1f.3 on # SMBus
|
||||
+ chip drivers/i2c/ck505 # IDT CV194
|
||||
+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff,
|
||||
+ 0xff, 0xff, 0xff, 0xff,
|
||||
+ 0xff, 0xff, 0xff, 0xff,
|
||||
+ 0xff, 0xff, 0xff, 0xff,
|
||||
+ 0xff, 0xff, 0xff }"
|
||||
+ register "regs" = "{ 0x15, 0x82, 0xff, 0xff,
|
||||
+ 0xff, 0x00, 0x00, 0x95,
|
||||
+ 0x00, 0x65, 0x7d, 0x56,
|
||||
+ 0x13, 0xc0, 0x00, 0x07,
|
||||
+ 0x01, 0x0a, 0x64 }"
|
||||
+ device i2c 69 on end
|
||||
+ end
|
||||
+ end
|
||||
+ device pci 1f.4 off end
|
||||
+ device pci 1f.5 off end # SATA 2 (for port 4-5 in IDE mode)
|
||||
+ device pci 1f.6 off end # Thermal Subsystem
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..9ad70469de
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/dsdt.asl
|
||||
@@ -0,0 +1,26 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20090811 // OEM revision
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+
|
||||
+ OSYS = 2002
|
||||
+ // global NVS and variables
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/x4x/acpi/x4x.asl>
|
||||
+ #include <southbridge/intel/i82801jx/acpi/ich10.asl>
|
||||
+ }
|
||||
+
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..bc81cf4a40
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
|
||||
@@ -0,0 +1,16 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (DP2,
|
||||
+ Analog,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf
|
||||
GIT binary patch
|
||||
literal 1917
|
||||
zcmd6nO>7%Q6vzLwGv0Mv$FUpJ*ik4iQd_wnX*X`M0y3~p?8a$~>ZXxZMU`4dc9RGb
|
||||
zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX
|
||||
zznS;`v-5V=o<pVaS;}Q53%NpOI!8{cz{K0eVfK65_|*A}SF)Me%$4!N`H5-z90%~a
|
||||
zvGog3fe5LjnM&o#3$<#k{6>{ZwwmnN>gY?}>{`7^JBpP$l`EBIwbi0*k&aU)n@v)E
|
||||
znI_A1T57efS5MG<y}m-_+CrVKE#0VADDft%nb#Y<<ao9;Mf?!XvM)_$Xla>NN5_ut
|
||||
zt=x`G)EjR#mlhURC^2!A3p33TcBg4-d8JyTiF&hfk}|a#&Dfe2%~V^}=4!QavNzBh
|
||||
z0Pae^5`gfb?<R!YN+PQ)U7<%H;73qF3iyQT71$?W2s|f{69_4sRY(x>7Q)c(LsP)8
|
||||
zQy)2gw<F#IP`I}U>gG1S^>aw&0D}Z+-SCcJJF;s)yXJeQ|4N{SU?$I`#$HZa<Jq(M
|
||||
zbA{r}Z0XY6<@U{Y-d!KWR>9dWBuxA$6X;VK;%W?Y>I;0P`|*vwAK$S(VB2JSq6g4n
|
||||
z>oEf8XCt;_Y-iYBWz#<re{?il1^f{S#nht`VW!62^5R*KQ6_?#8e&Qw=9%`og2x!s
|
||||
z&J)wlZ=a<yoJkutfwu4%aVXlu?i^8v?R77IyGvKcD|M`CFG$6FUmK8q<|o>3T9EmJ
|
||||
z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<<Gei4)FzWqGEt6P8D
|
||||
zA9m}s>;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH`
|
||||
zawsKv^FvHqm+<DDPT)%}_kZ8^eT88YGmG-#)X3=RRB|L^Uj_{yd%JeO<1HRZVz=Fz
|
||||
z+aqUCWdF3_={#Q&&k)eF1i=WV`AbSlzo*bP?x?ir5BVVO`R34f89jWL{Z}or^BwmG
|
||||
z-E;A_iWVUUWnWQl3L|~0xA@rHJRA-;7V)Y6B5=@E8R@?(?5{Eh23RefpSOGX_F{8A
|
||||
z1PtU+iNng^h#C7J<vufJ9>c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E
|
||||
xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO(<xf!`#Pk3F
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..e2fa05cd8f
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <northbridge/intel/x4x/x4x.h>
|
||||
+
|
||||
+void mb_get_spd_map(u8 spd_map[4])
|
||||
+{
|
||||
+ // BTX form factor
|
||||
+ spd_map[0] = 0x53;
|
||||
+ spd_map[1] = 0x52;
|
||||
+ spd_map[2] = 0x51;
|
||||
+ spd_map[3] = 0x50;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..9993f17c55
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
|
||||
@@ -0,0 +1,174 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_NATIVE,
|
||||
+ .gpio1 = GPIO_MODE_NATIVE,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_GPIO,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_GPIO,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_NATIVE,
|
||||
+ .gpio8 = GPIO_MODE_NATIVE,
|
||||
+ .gpio9 = GPIO_MODE_GPIO,
|
||||
+ .gpio10 = GPIO_MODE_GPIO,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_NATIVE,
|
||||
+ .gpio16 = GPIO_MODE_GPIO,
|
||||
+ .gpio17 = GPIO_MODE_NATIVE,
|
||||
+ .gpio18 = GPIO_MODE_GPIO,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_GPIO,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_GPIO,
|
||||
+ .gpio31 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio3 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio5 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio9 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio10 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio16 = GPIO_DIR_INPUT,
|
||||
+ .gpio18 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio20 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio29 = GPIO_DIR_INPUT,
|
||||
+ .gpio30 = GPIO_DIR_INPUT,
|
||||
+ .gpio31 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio9 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio18 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio20 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio28 = GPIO_LEVEL_LOW,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio13 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_GPIO,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_NATIVE,
|
||||
+ .gpio46 = GPIO_MODE_NATIVE,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_NATIVE,
|
||||
+ .gpio52 = GPIO_MODE_NATIVE,
|
||||
+ .gpio53 = GPIO_MODE_NATIVE,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_GPIO,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio32 = GPIO_DIR_INPUT,
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_INPUT,
|
||||
+ .gpio35 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio56 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio35 = GPIO_LEVEL_LOW,
|
||||
+ .gpio49 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio56 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio60 = GPIO_LEVEL_LOW,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_NATIVE,
|
||||
+ .gpio69 = GPIO_MODE_NATIVE,
|
||||
+ .gpio70 = GPIO_MODE_NATIVE,
|
||||
+ .gpio71 = GPIO_MODE_NATIVE,
|
||||
+ .gpio72 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio72 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..4158bcf899
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
|
||||
@@ -0,0 +1,26 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ /* coreboot specific header */
|
||||
+ 0x11d4194a, /* Analog Devices AD1984A */
|
||||
+ 0xbfd40000, /* Subsystem ID */
|
||||
+ 10, /* Number of entries */
|
||||
+
|
||||
+ /* Pin Widget Verb Table */
|
||||
+ AZALIA_PIN_CFG(0, 0x11, 0x032140f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x12, 0x21214010),
|
||||
+ AZALIA_PIN_CFG(0, 0x13, 0x901701f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x14, 0x03a190f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x15, 0xb7a70121),
|
||||
+ AZALIA_PIN_CFG(0, 0x16, 0x9933012e),
|
||||
+ AZALIA_PIN_CFG(0, 0x17, 0x97a601f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1b, 0x014510f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1c, 0x21a19020),
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..555b1c1f5c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
|
||||
@@ -0,0 +1,10 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+chip northbridge/intel/x4x
|
||||
+ device domain 0 on
|
||||
+ chip southbridge/intel/i82801jx
|
||||
+ device pci 1c.0 on end # PCIe 1
|
||||
+ device pci 1c.1 on end # PCIe 2
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,326 +0,0 @@
|
||||
From e1ed4a9739d2cfc691d71c165d984ef171a2ea76 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Wed, 30 Oct 2024 20:55:25 -0600
|
||||
Subject: [PATCH 25/51] mb/dell/optiplex_780: Add USFF variant
|
||||
|
||||
Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/optiplex_780/Kconfig | 5 +
|
||||
src/mainboard/dell/optiplex_780/Kconfig.name | 3 +
|
||||
.../optiplex_780/variants/780_usff/data.vbt | Bin 0 -> 1917 bytes
|
||||
.../variants/780_usff/early_init.c | 9 +
|
||||
.../optiplex_780/variants/780_usff/gpio.c | 166 ++++++++++++++++++
|
||||
.../optiplex_780/variants/780_usff/hda_verb.c | 26 +++
|
||||
.../variants/780_usff/overridetree.cb | 10 ++
|
||||
7 files changed, 219 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
|
||||
index 2d06c75c9a..fc649e35d5 100644
|
||||
--- a/src/mainboard/dell/optiplex_780/Kconfig
|
||||
+++ b/src/mainboard/dell/optiplex_780/Kconfig
|
||||
@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
config BOARD_DELL_OPTIPLEX_780_MT
|
||||
select BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
|
||||
+config BOARD_DELL_OPTIPLEX_780_USFF
|
||||
+ select BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
+
|
||||
if BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
|
||||
config VGA_BIOS_ID
|
||||
@@ -30,11 +33,13 @@ config MAINBOARD_DIR
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
|
||||
+ default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF
|
||||
|
||||
config OVERRIDE_DEVICETREE
|
||||
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
|
||||
config VARIANT_DIR
|
||||
default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
|
||||
+ default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF
|
||||
|
||||
endif # BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
|
||||
index db7f2e8fe3..bc84c82a79 100644
|
||||
--- a/src/mainboard/dell/optiplex_780/Kconfig.name
|
||||
+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
|
||||
@@ -2,3 +2,6 @@
|
||||
|
||||
config BOARD_DELL_OPTIPLEX_780_MT
|
||||
bool "OptiPlex 780 MT"
|
||||
+
|
||||
+config BOARD_DELL_OPTIPLEX_780_USFF
|
||||
+ bool "OptiPlex 780 USFF"
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7
|
||||
GIT binary patch
|
||||
literal 1917
|
||||
zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@i<uQKf!)+gO;|
|
||||
zveT#>P+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G
|
||||
z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX
|
||||
zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv
|
||||
zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB
|
||||
zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU<Iv53Rb6YTgMPOY8;~P1Yglh^6Fgt1^
|
||||
zCTz|SVPcSpZ44F@&oNPUMO@&BE3y(57YP_Y!4SZhE?GXYa7k+b0(X|s7u3GDRf^1#
|
||||
zOd2ZCCPO|I&sHEt;p8UshhHtYQ>7!7x2m<d`Gu2<r+Qc4|6pwd8&zFboH_W7XE7uU
|
||||
zWW-@Cim&mdY2!O{JANR)OTJG2z>LBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T
|
||||
z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`<pE+J?KFZ=&_JVP1YL=#z<-Q*24K4
|
||||
zn+$YxrHNJJc`k?_8N=Kres26_#E8GLn2{jfW5P%ge`kL(Btkt=>xo)V)Ow=U6P12c
|
||||
z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8
|
||||
zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE
|
||||
zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb
|
||||
zV99s{>`r76L#Hr6XW6r|<iq#4Jr?XsxKyeJKEj7;e4SZ^1B12u&iV_9M0*Kem@fmn
|
||||
z1C>>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq<Gj{q2D(
|
||||
z>&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a=
|
||||
T#w3FFBiyj<XAh$hb(enud`r7S
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..2a55fc3a6e
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <northbridge/intel/x4x/x4x.h>
|
||||
+
|
||||
+void mb_get_spd_map(u8 spd_map[4])
|
||||
+{
|
||||
+ spd_map[0] = 0x50;
|
||||
+ spd_map[2] = 0x52;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..389f4077d7
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
|
||||
@@ -0,0 +1,166 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_NATIVE,
|
||||
+ .gpio1 = GPIO_MODE_NATIVE,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_GPIO,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_GPIO,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_NATIVE,
|
||||
+ .gpio8 = GPIO_MODE_NATIVE,
|
||||
+ .gpio9 = GPIO_MODE_GPIO,
|
||||
+ .gpio10 = GPIO_MODE_GPIO,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_NATIVE,
|
||||
+ .gpio16 = GPIO_MODE_GPIO,
|
||||
+ .gpio17 = GPIO_MODE_NATIVE,
|
||||
+ .gpio18 = GPIO_MODE_GPIO,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_GPIO,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_GPIO,
|
||||
+ .gpio31 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio3 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio5 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio9 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio10 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio16 = GPIO_DIR_INPUT,
|
||||
+ .gpio18 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio20 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio29 = GPIO_DIR_INPUT,
|
||||
+ .gpio30 = GPIO_DIR_INPUT,
|
||||
+ .gpio31 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio9 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio18 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio20 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio28 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio13 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_GPIO,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_NATIVE,
|
||||
+ .gpio46 = GPIO_MODE_NATIVE,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_NATIVE,
|
||||
+ .gpio52 = GPIO_MODE_NATIVE,
|
||||
+ .gpio53 = GPIO_MODE_NATIVE,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_GPIO,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio32 = GPIO_DIR_INPUT,
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_INPUT,
|
||||
+ .gpio35 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio56 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio35 = GPIO_LEVEL_LOW,
|
||||
+ .gpio49 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio56 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio60 = GPIO_LEVEL_LOW,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio72 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio72 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..c94e06b156
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
|
||||
@@ -0,0 +1,26 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ /* coreboot specific header */
|
||||
+ 0x11d4194a, /* Analog Devices AD1984A */
|
||||
+ 0x10280420, /* Subsystem ID */
|
||||
+ 10, /* Number of entries */
|
||||
+
|
||||
+ /* Pin Widget Verb Table */
|
||||
+ AZALIA_PIN_CFG(0, 0x11, 0x02214040),
|
||||
+ AZALIA_PIN_CFG(0, 0x12, 0x01014010),
|
||||
+ AZALIA_PIN_CFG(0, 0x13, 0x991301f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x14, 0x02a19020),
|
||||
+ AZALIA_PIN_CFG(0, 0x15, 0x01813030),
|
||||
+ AZALIA_PIN_CFG(0, 0x16, 0x413301f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x17, 0x41a601f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1b, 0x414501f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1c, 0x413301f0),
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..555b1c1f5c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
|
||||
@@ -0,0 +1,10 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+chip northbridge/intel/x4x
|
||||
+ device domain 0 on
|
||||
+ chip southbridge/intel/i82801jx
|
||||
+ device pci 1c.0 on end # PCIe 1
|
||||
+ device pci 1c.1 on end # PCIe 2
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,33 +0,0 @@
|
||||
From 55a33798ec9aadd38222f736d4c1b77f9902f3f4 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 6 Jan 2025 01:53:53 +0000
|
||||
Subject: [PATCH 26/51] src/intel/x4x: Disable stack overflow debug
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/northbridge/intel/x4x/Kconfig | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
|
||||
index 069fa0244d..8c70344846 100644
|
||||
--- a/src/northbridge/intel/x4x/Kconfig
|
||||
+++ b/src/northbridge/intel/x4x/Kconfig
|
||||
@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER
|
||||
int
|
||||
default 256
|
||||
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
# This number must be equal or lower than what's reported in ACPI PCI _CRS
|
||||
config DOMAIN_RESOURCE_32BIT_LIMIT
|
||||
default 0xfec00000
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,42 +0,0 @@
|
||||
From 56a581aeadb4efafc62efaba742b06b25852ccf8 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Tue, 22 Apr 2025 10:21:59 +0100
|
||||
Subject: [PATCH 27/51] hp/8300cmt: remove xhci_overcurrent_mapping
|
||||
|
||||
No longer needed, as per the following commit:
|
||||
|
||||
commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1
|
||||
Author: Keith Hui <buurin@gmail.com>
|
||||
Date: Tue Dec 31 18:19:31 2024 -0500
|
||||
|
||||
sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping
|
||||
|
||||
Removing this from the devicetree also allows the
|
||||
board to compile, otherwise an error is thrown:
|
||||
|
||||
build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping'
|
||||
147 | .xhci_overcurrent_mapping = 0x00000c03,
|
||||
| ^~~~~~~~~~~~~~~~~~~~~~~~
|
||||
build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror]
|
||||
147 | .xhci_overcurrent_mapping = 0x00000c03,
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
|
||||
index 3d21739b72..3a0b6d5c59 100644
|
||||
--- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
|
||||
@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge
|
||||
register "spi_lvscc" = "0x2005"
|
||||
register "spi_uvscc" = "0x2005"
|
||||
register "superspeed_capable_ports" = "0x0000000f"
|
||||
- register "xhci_overcurrent_mapping" = "0x00000c03"
|
||||
register "xhci_switchable_ports" = "0x0000000f"
|
||||
register "usb_port_config" = "{
|
||||
{ 1, 0, 0 },
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,47 +0,0 @@
|
||||
From 4470d8fb6760173090c43e6a82a8865f5917dd9b Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Wed, 11 Dec 2024 01:06:01 +0000
|
||||
Subject: [PATCH 28/51] dell/3050micro: disable nvme hotplug
|
||||
|
||||
in my testing, when running my 3050micro for a few days,
|
||||
the nvme would sometimes randomly rename.
|
||||
|
||||
e.g. nvme0n1 renamed to nvme0n2
|
||||
|
||||
this might cause crashes in linux, if booting only from the
|
||||
nvme. in my case, i was booting from mdraid (sata+nvme) and
|
||||
every few days, the nvme would rename at least once, causing
|
||||
my RAID to become unsynced. since i'm using RAID1, this was
|
||||
OK and I could simply re-sync the array, but this is quite
|
||||
precarious indeed. if you're using raid0, that will potentially
|
||||
corrupt your RAID array indefinitely.
|
||||
|
||||
this same issue manifested on the T480/T480 thinkpads, and
|
||||
S3 resume would break because of that, when booting from nvme,
|
||||
because the nvme would be "unplugged" and appear to linux as a
|
||||
new device (the one that you booted from).
|
||||
|
||||
the fix there was to disable hotplugging on that pci-e slot
|
||||
for the nvme, so apply the same fix here for 3050 micro
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
.../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
|
||||
index c5f1749b2c..ff48a8121a 100644
|
||||
--- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
|
||||
+++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
|
||||
@@ -46,7 +46,7 @@ chip soc/intel/skylake
|
||||
register "PcieRpAdvancedErrorReporting[20]" = "1"
|
||||
register "PcieRpLtrEnable[20]" = "true"
|
||||
register "PcieRpClkSrcNumber[20]" = "3"
|
||||
- register "PcieRpHotPlug[20]" = "1"
|
||||
+ register "PcieRpHotPlug[20]" = "0"
|
||||
end
|
||||
|
||||
end
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-61
@@ -1,61 +0,0 @@
|
||||
From f6b82e0483d7f9e47f465bb4884b199cfd9fe04b Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 6 Jan 2025 01:36:23 +0000
|
||||
Subject: [PATCH 29/51] src/intel/skylake: Disable stack overflow debug options
|
||||
|
||||
The option was appearing in T480/3050micro configs of lbmk,
|
||||
after updating on the coreboot/next uprev for 20241206 rev8:
|
||||
|
||||
CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y
|
||||
|
||||
I did some digging. See coreboot commit:
|
||||
|
||||
commit 51cc2bacb6b07279b97e9934d079060475481fb6
|
||||
Author: Subrata Banik <subratabanik@google.com>
|
||||
Date: Fri Dec 13 13:07:28 2024 +0530
|
||||
|
||||
soc/intel/pantherlake: Disable stack overflow debug options
|
||||
|
||||
Well now:
|
||||
|
||||
I'm disabling this behaviour on Skylake, for the same
|
||||
behaviour, because I want as few behaviour changes in general,
|
||||
as possible, for the rev8 release.
|
||||
|
||||
According to Subrata's patch, which was for Pantherlake,
|
||||
without this change, stack corruption can occur on verstage
|
||||
and romstage early on. Please look at that coreboot patch,
|
||||
referenced above, for clarity.
|
||||
|
||||
I see no harm in disabling this option for Skylake, since
|
||||
the behaviour that it otherwise enables was not present
|
||||
before.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/soc/intel/skylake/Kconfig | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
|
||||
index c76239936a..f8ff8cfa7a 100644
|
||||
--- a/src/soc/intel/skylake/Kconfig
|
||||
+++ b/src/soc/intel/skylake/Kconfig
|
||||
@@ -136,6 +136,15 @@ config DCACHE_RAM_SIZE
|
||||
The size of the cache-as-ram region required during bootblock
|
||||
and/or romstage.
|
||||
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
config DCACHE_BSP_STACK_SIZE
|
||||
hex
|
||||
default 0x20400 if FSP_USES_CB_STACK
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,36 +0,0 @@
|
||||
From 025eae54ed31b728866db1279a7cd86d7280dc58 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Thu, 26 Dec 2024 19:45:20 +0000
|
||||
Subject: [PATCH 30/51] soc/intel/skylake: Don't compress FSP-S
|
||||
|
||||
Build systems like lbmk need to reproducibly insert
|
||||
certain vendor files on release images.
|
||||
|
||||
Compression isn't always reproducible, and making it
|
||||
so costs a lot more time than simply disabling compression.
|
||||
|
||||
With this change, the FSP-S module will now be inserted
|
||||
without compression, which means that there will now be
|
||||
about 40KB of extra space used in the flash.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/soc/intel/skylake/Kconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
|
||||
index f8ff8cfa7a..97354cdaa5 100644
|
||||
--- a/src/soc/intel/skylake/Kconfig
|
||||
+++ b/src/soc/intel/skylake/Kconfig
|
||||
@@ -15,7 +15,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
|
||||
select DRAM_SUPPORT_DDR4
|
||||
select DRIVERS_USB_ACPI
|
||||
select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
|
||||
- select FSP_COMPRESS_FSP_S_LZ4
|
||||
+# select FSP_COMPRESS_FSP_S_LZ4
|
||||
select FSP_M_XIP
|
||||
select GENERIC_GPIO_LIB
|
||||
select HAVE_FSP_GOP
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-78
@@ -1,78 +0,0 @@
|
||||
From ca198ab68579cee7297c3675b440c0fd78ed7511 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Wed, 18 Dec 2024 02:06:18 +0000
|
||||
Subject: [PATCH 31/51] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
|
||||
|
||||
This is used by lbmk to know where a tb.bin file goes,
|
||||
when extracting and padding TBT.bin from Lenovo ThunderBolt
|
||||
firmware updates on T480/T480s and other machines, grabbing
|
||||
Lenovo update files.
|
||||
|
||||
Not used in any builds, so it's not relevant for ./mk inject
|
||||
|
||||
However, the ThunderBolt firmware is now auto-downloaded on
|
||||
T480/T480s. This is not inserted, because it doesn't go in
|
||||
the main flash, but the resulting ROM image can be flashed
|
||||
on the TB controller's separate flash chip.
|
||||
|
||||
Locations are as follows:
|
||||
|
||||
vendorfiles/t480s/tb.bin
|
||||
vendorfiles/t480/tb.bin
|
||||
|
||||
This can be used for other affected ThinkPads when they're
|
||||
added to Libreboot, but note that Lenovo provides different
|
||||
TB firmware files for each machine.
|
||||
|
||||
Since I assume it's the same TB controller on all of those
|
||||
machines, I have to wonder: what difference is there between
|
||||
the various TBT.bin files provided by Lenovo, and how do they
|
||||
differ in terms of actual flashed configuration?
|
||||
|
||||
We simply flash the padded TBT.bin when updating the firmware,
|
||||
flashing externally. That's what this patch is for, so that
|
||||
lbmk can auto-download them.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++
|
||||
1 file changed, 26 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
|
||||
index 2ffbaab85f..512b326381 100644
|
||||
--- a/src/mainboard/lenovo/Kconfig
|
||||
+++ b/src/mainboard/lenovo/Kconfig
|
||||
@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY
|
||||
string
|
||||
default MAINBOARD_PART_NUMBER
|
||||
|
||||
+config LENOVO_TBFW_BIN
|
||||
+ string "Lenovo ThunderBolt firmware bin file"
|
||||
+ default ""
|
||||
+ help
|
||||
+ ThunderBolt firmware for certain ThinkPad models e.g. T480.
|
||||
+ Not used in the actual build. Libreboot's build system uses this
|
||||
+ along with config/vendor/*/pkg.cfg entries defining a URL to the
|
||||
+ Lenovo download link and hash. The resulting file when processed by
|
||||
+ lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device.
|
||||
+ Earlier versions of this firmware had debug commands enabled that
|
||||
+ sent logs to said flash IC, and it would quickly fill up, bricking
|
||||
+ the ThunderBolt controller. With these updates, flashed externally,
|
||||
+ you can fix the issue if present or otherwise prevent it. The benefit
|
||||
+ here is that you then don't need to use Windows or a boot disk. You
|
||||
+ can flash the TB firmware while flashing Libreboot firmware. Easy!
|
||||
+ Look for these variables in lbmk:
|
||||
+ TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and
|
||||
+ CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file.
|
||||
+ The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting
|
||||
+ the firmware, putting it at that desired location. In this way, lbmk
|
||||
+ can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb
|
||||
+ and it appears at vendorfiles/t480/tb.bin fully padded and everything!
|
||||
+
|
||||
+ Just leave this blank if you don't care about this option. It's not
|
||||
+ useful for every ThinkPad, only certain models.
|
||||
+
|
||||
endif # VENDOR_LENOVO
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-37
@@ -1,37 +0,0 @@
|
||||
From cb3b76b4805886d5afc5846d351a292639b91bc6 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 21 Apr 2025 05:14:45 +0100
|
||||
Subject: [PATCH 32/51] Conditional TBFW setting for kabylake thinkpads
|
||||
|
||||
Otherwise, other boards will define it, which
|
||||
might trigger the vendor download script, and
|
||||
lead to a non-zero exit.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/lenovo/Kconfig | 4 ++++
|
||||
1 file changed, 4 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
|
||||
index 512b326381..b2c7763198 100644
|
||||
--- a/src/mainboard/lenovo/Kconfig
|
||||
+++ b/src/mainboard/lenovo/Kconfig
|
||||
@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY
|
||||
string
|
||||
default MAINBOARD_PART_NUMBER
|
||||
|
||||
+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580
|
||||
+
|
||||
config LENOVO_TBFW_BIN
|
||||
string "Lenovo ThunderBolt firmware bin file"
|
||||
default ""
|
||||
@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN
|
||||
Just leave this blank if you don't care about this option. It's not
|
||||
useful for every ThinkPad, only certain models.
|
||||
|
||||
+endif # BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580
|
||||
+
|
||||
endif # VENDOR_LENOVO
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-30
@@ -1,30 +0,0 @@
|
||||
From bb04b8f8db08f06100f801ddeb076f165c3d503a Mon Sep 17 00:00:00 2001
|
||||
From: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
Date: Sat, 27 Sep 2025 23:30:46 +0300
|
||||
Subject: [PATCH 33/51] soc/intel/alderlake: Disable
|
||||
MRC_CACHE_USING_MRC_VERSION
|
||||
|
||||
There's some issue with building against the FSP headers in src/vendorcode.
|
||||
Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing
|
||||
from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force.
|
||||
|
||||
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
---
|
||||
src/soc/intel/alderlake/Kconfig | 1 -
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index 334ea26e5b..0f1404ea49 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE
|
||||
select INTEL_GMA_VERSION_2
|
||||
select INTEL_TXT_LIB
|
||||
select MP_SERVICES_PPI_V2
|
||||
- select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO
|
||||
select MRC_SETTINGS_PROTECT
|
||||
select PARALLEL_MP_AP_WORK
|
||||
select PLATFORM_USES_FSP2_2
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-76
@@ -1,76 +0,0 @@
|
||||
From de90c8706495b73e24e362dd7c80f211581a2ad6 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 28 Sep 2025 03:17:50 +0100
|
||||
Subject: [PATCH 34/51] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks)
|
||||
|
||||
if you pass -k (keep fptr modules), don't use -r, don't
|
||||
use -t, you can essentially just use me_cleaner to
|
||||
extract a ME image without changing it. this is useful
|
||||
when for example, you just want to set the HAP bit.
|
||||
|
||||
however, me_cleaner still performs a FPTR check.
|
||||
|
||||
on some newer ME versions, it's always invalid according
|
||||
to me_cleaner, because for example it doesn't handle
|
||||
ME16 very well yet.
|
||||
|
||||
this patch adds an option to override the FPTR check
|
||||
|
||||
either pass -p or --pass-fptr
|
||||
|
||||
NOTE: we probably won't use this on coreboot's me_cleaner,
|
||||
which is the corna version. we only need it on the newer
|
||||
me_cleaner versions for e.g. ME16, on certain setups.
|
||||
still, it's best to have the patch here too, just in case.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/me_cleaner/me_cleaner.py | 14 ++++++++++----
|
||||
1 file changed, 10 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py
|
||||
index fae5e56732..228bac899f 100755
|
||||
--- a/util/me_cleaner/me_cleaner.py
|
||||
+++ b/util/me_cleaner/me_cleaner.py
|
||||
@@ -246,8 +246,10 @@ def check_partition_signature(f, offset):
|
||||
return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest()) # FIXME
|
||||
|
||||
|
||||
-def print_check_partition_signature(f, offset):
|
||||
- if check_partition_signature(f, offset):
|
||||
+def print_check_partition_signature(f, offset, pass_fptr):
|
||||
+ if pass_fptr:
|
||||
+ print("Skipping FPTR checks because the user told us to")
|
||||
+ elif check_partition_signature(f, offset):
|
||||
print("VALID")
|
||||
else:
|
||||
print("INVALID!!")
|
||||
@@ -486,6 +488,8 @@ if __name__ == "__main__":
|
||||
"--extract-me)", action="store_true")
|
||||
parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR "
|
||||
"modules, even when possible", action="store_true")
|
||||
+ parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks"
|
||||
+ "regardless of other operations", action="store_true")
|
||||
bw_list.add_argument("-w", "--whitelist", metavar="whitelist",
|
||||
help="Comma separated list of additional partitions "
|
||||
"to keep in the final image. This can be used to "
|
||||
@@ -871,12 +875,14 @@ if __name__ == "__main__":
|
||||
print("Checking the FTPR RSA signature of the extracted ME "
|
||||
"image... ", end="")
|
||||
print_check_partition_signature(mef_copy,
|
||||
- ftpr_offset + ftpr_mn2_offset)
|
||||
+ ftpr_offset + ftpr_mn2_offset,
|
||||
+ args.pass_fptr)
|
||||
mef_copy.close()
|
||||
|
||||
if not me6_ignition:
|
||||
print("Checking the FTPR RSA signature... ", end="")
|
||||
- print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset)
|
||||
+ print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset,
|
||||
+ args.pass_fptr)
|
||||
|
||||
f.close()
|
||||
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,35 +0,0 @@
|
||||
From 9887eeeb89b29ca8483c9742733fd78ccd7e171b Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sat, 4 Oct 2025 21:57:43 +0100
|
||||
Subject: [PATCH 35/51] soc/intel/alderlake: Don't compress FSP-S
|
||||
|
||||
Build systems like lbmk need to reproducibly insert
|
||||
certain vendor files on release images.
|
||||
|
||||
Compression isn't always reproducible, and making it
|
||||
so costs a lot more time than simply disabling compression.
|
||||
|
||||
With this change, FSP-S uses slightly more space inside
|
||||
the flash, but it's not that much.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/soc/intel/alderlake/Kconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index 0f1404ea49..f78729a9c4 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE
|
||||
select DRAM_SUPPORT_DDR5
|
||||
select DRIVERS_USB_ACPI
|
||||
select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
|
||||
- select FSP_COMPRESS_FSP_S_LZ4
|
||||
+# select FSP_COMPRESS_FSP_S_LZ4
|
||||
select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
|
||||
select FSP_M_XIP
|
||||
select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-33
@@ -1,33 +0,0 @@
|
||||
From 1f62cd582614cb3739475dd4439e132b931c5619 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sat, 4 Oct 2025 22:20:11 +0100
|
||||
Subject: [PATCH 36/51] alderlake: don't require full fsp repo for fd path
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/soc/intel/alderlake/Kconfig | 9 ++++++++-
|
||||
1 file changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index f78729a9c4..c05d06289e 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -442,7 +442,14 @@ config FSP_HEADER_PATH
|
||||
|
||||
config FSP_FD_PATH
|
||||
string
|
||||
- depends on FSP_USE_REPO
|
||||
+# dependency removed for lbmk purposes, so that the path is present
|
||||
+# in the config regardless of whether it's used. this is for ./mk -d
|
||||
+# on alderlake boards, which is used by lbmk to manually split fsp,
|
||||
+# even though the result is identical to what coreboot produces, because
|
||||
+# this enables lbmk to strip the fsp in release archives, and re-insert
|
||||
+# for compliance reasons (due to technicalities in intel's licensing),
|
||||
+# and to enable lbmk's advanced checksum verification of vendor files
|
||||
+# depends on FSP_USE_REPO
|
||||
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE
|
||||
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S
|
||||
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-46
@@ -1,46 +0,0 @@
|
||||
From 0af11ee58ae38a385431253b1f5f0e9dbce98d3d Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 6 Oct 2025 04:47:06 +0100
|
||||
Subject: [PATCH 37/51] soc/alderlake: disable stack overflow debug option
|
||||
|
||||
same as on other boards. based on this commit:
|
||||
|
||||
commit 51cc2bacb6b07279b97e9934d079060475481fb6
|
||||
Author: Subrata Banik <subratabanik@google.com>
|
||||
Author: Subrata Banik <subratabanik@google.com>
|
||||
Date: Fri Dec 13 13:07:28 2024 +0530
|
||||
|
||||
soc/intel/pantherlake: Disable stack overflow debug options
|
||||
|
||||
yeah, i've been replicating this change per platform.
|
||||
|
||||
we do alderlake now in libreboot, so let's set that here too.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/soc/intel/alderlake/Kconfig | 9 +++++++++
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index c05d06289e..acb87275d4 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -343,6 +343,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ
|
||||
int
|
||||
default 19200000
|
||||
|
||||
+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
|
||||
+ bool
|
||||
+ default n
|
||||
+
|
||||
config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
|
||||
int
|
||||
default 133
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-92
@@ -1,92 +0,0 @@
|
||||
From f1369485a721aa4ed239f6a8c0b0ad1b82884c7b Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sun, 11 May 2025 15:41:22 -0600
|
||||
Subject: [PATCH 38/51] ec/dell/mec5035: Add command to disable EC-initiated
|
||||
thermal shutdown
|
||||
|
||||
If command 0xBF isn't sent, the EC shuts down the system without warning
|
||||
as soon as the CPU temperature reaches about 87 degrees, without letting
|
||||
the CPU thermal throttle to try and reduce the temperature. With vendor
|
||||
firmware, the CPU is able to reach around 100 degrees before thermal
|
||||
throttling.
|
||||
|
||||
This command was found by collecting EC commands by logging the LPC bus
|
||||
while running with vendor firmware and then replaying observed commands
|
||||
from coreboot. By systematically replaying subsets of commands in a
|
||||
binary search pattern and then stress testing the system, the command to
|
||||
disable the shutdown was isolated.
|
||||
|
||||
The exact meaning of the parameters for this command are unknown at this
|
||||
time, but do seem to differ between different generations of these
|
||||
laptops. Due to this, the commmand should be called by mainboard
|
||||
specific code which passes the specific parameter value used.
|
||||
|
||||
The Google Wilco EC code, which runs on Latitude Chromebooks and shares
|
||||
many commands with the standard Latitude ECs, suggests that command 0xBF
|
||||
tells the EC about the processors CPUID. However, the values observed in
|
||||
LPC bus logs do not seem to correspond with any CPUID values on the
|
||||
non-Chromebook systems I tested.
|
||||
|
||||
Observed command parameter values (sent on mailbox registers 2-4):
|
||||
- E6430 (Ivy Bridge): 0x07, 0x00, 0x00
|
||||
- M6800 (Haswell): 0x14, 0x00, 0x00
|
||||
|
||||
Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++
|
||||
src/ec/dell/mec5035/mec5035.h | 2 ++
|
||||
2 files changed, 21 insertions(+)
|
||||
|
||||
diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
|
||||
index c5067c16f6..b316fa4989 100644
|
||||
--- a/src/ec/dell/mec5035/mec5035.c
|
||||
+++ b/src/ec/dell/mec5035/mec5035.c
|
||||
@@ -114,6 +114,25 @@ void mec5035_sleep_enable(void)
|
||||
ec_command(CMD_SLEEP_ENABLE);
|
||||
}
|
||||
|
||||
+void mec5035_cmd_bf(u8 i)
|
||||
+{
|
||||
+ /*
|
||||
+ * If this command isn't sent, the EC shuts down the system as soon as
|
||||
+ * the CPU temperature reaches about 87 degrees. It is unknown exactly
|
||||
+ * what the parameters represent. The Google Wilco EC code, which runs
|
||||
+ * on Latitude Chromebooks and shares some commands with the standard
|
||||
+ * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but
|
||||
+ * the values observed in LPC bus logs don't seem to match any CPUID
|
||||
+ * values of the normal Latitudes this was tested with.
|
||||
+ * Observed i values:
|
||||
+ * - E6430 (Ivy Bridge): 0x7
|
||||
+ * - M6800 (Haswell): 0x14
|
||||
+ */
|
||||
+ u8 buf[3] = {i, 0, 0};
|
||||
+ write_mailbox_regs(buf, 2, 3);
|
||||
+ ec_command(CMD_BF);
|
||||
+}
|
||||
+
|
||||
void mec5035_early_init(void)
|
||||
{
|
||||
/* If this isn't sent the EC shuts down the system after about 15
|
||||
diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
|
||||
index 5cd907bf71..71d1a71075 100644
|
||||
--- a/src/ec/dell/mec5035/mec5035.h
|
||||
+++ b/src/ec/dell/mec5035/mec5035.h
|
||||
@@ -14,6 +14,7 @@ enum mec5035_cmd {
|
||||
CMD_POWER_BUTTON_TO_HOST = 0x3e,
|
||||
CMD_ACPI_WAKEUP_CHANGE = 0x4a,
|
||||
CMD_SLEEP_ENABLE = 0x64,
|
||||
+ CMD_BF = 0xbf,
|
||||
CMD_CPU_OK = 0xc2,
|
||||
};
|
||||
|
||||
@@ -65,5 +66,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change);
|
||||
void mec5035_sleep_enable(void);
|
||||
|
||||
void mec5035_smi_sleep(int slp_type);
|
||||
+void mec5035_cmd_bf(u8 i);
|
||||
|
||||
#endif /* _EC_DELL_MEC5035_H_ */
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-36
@@ -1,36 +0,0 @@
|
||||
From 3e63073e195446ea3adef0e21f5369e7ef27494a Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sun, 11 May 2025 16:28:23 -0600
|
||||
Subject: [PATCH 39/51] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown
|
||||
at 87 degrees
|
||||
|
||||
If command 0xBF isn't sent, the EC will shut down the system without
|
||||
warning once the CPU reaches approximately 87 degrees, without the
|
||||
system thermal throttling first. Call the newly added function from the
|
||||
MEC5035 code to send this command and disable this behavior.
|
||||
|
||||
Tested on the Latitude E6430.
|
||||
|
||||
Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++
|
||||
1 file changed, 5 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c
|
||||
index ff83db095b..ef385a0a70 100644
|
||||
--- a/src/mainboard/dell/snb_ivb_latitude/early_init.c
|
||||
+++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c
|
||||
@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void)
|
||||
| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
|
||||
| COMB_LPC_EN | COMA_LPC_EN);
|
||||
mec5035_early_init();
|
||||
+
|
||||
+ /* Observed from LPC logs with vendor firmware. Seems to disable
|
||||
+ * EC-initiated shutdown when the CPU reaches approximately 87 degrees.
|
||||
+ * The exact meaning of the parameter is currently unknown. */
|
||||
+ mec5035_cmd_bf(0x07);
|
||||
}
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,28 +0,0 @@
|
||||
From f05e8514654cddb5041fa65a90ab5260ec55d1e5 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sat, 20 Dec 2025 20:12:48 +0100
|
||||
Subject: [PATCH 40/51] fix ifdtool build
|
||||
|
||||
not my mistake. someone messed up.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/ifdtool/ifdtool.c | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
|
||||
index 7f0c10bd0b..2a5365efe7 100644
|
||||
--- a/util/ifdtool/ifdtool.c
|
||||
+++ b/util/ifdtool/ifdtool.c
|
||||
@@ -2610,7 +2610,7 @@ int main(int argc, char *argv[])
|
||||
}
|
||||
mode_nuke = 1;
|
||||
break;
|
||||
- Case 'v':
|
||||
+ case 'v':
|
||||
print_version();
|
||||
exit(EXIT_SUCCESS);
|
||||
break;
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-30
@@ -1,30 +0,0 @@
|
||||
From 76a1f9c12fedcd595b540168efdd9a8439be3bcd Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sat, 20 Dec 2025 22:36:18 +0100
|
||||
Subject: [PATCH 41/51] tests/Makefile.mk: use 3rdparty/cmocka by default
|
||||
|
||||
(tests)
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
tests/Makefile.mk | 4 +++-
|
||||
1 file changed, 3 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/tests/Makefile.mk b/tests/Makefile.mk
|
||||
index 9e3f86a138..a5a518cd35 100644
|
||||
--- a/tests/Makefile.mk
|
||||
+++ b/tests/Makefile.mk
|
||||
@@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage
|
||||
endif
|
||||
|
||||
# Use system cmoka in default, or build from 3rdparty source code if requested
|
||||
-USE_SYSTEM_CMOCKA ?= 1
|
||||
+# PATCH NOTE: lbmk sets it to 0 by default. You can still override it to 1
|
||||
+# if you wish; upstream sets this to 1 by default, but we do 0
|
||||
+USE_SYSTEM_CMOCKA ?= 0
|
||||
ifeq ($(USE_SYSTEM_CMOCKA),1)
|
||||
ifeq ($(shell $(HOSTPKG_CONFIG) --exists cmocka || echo 1),1)
|
||||
$(warning No system cmocka, build from 3rdparty instead...)
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-51
@@ -1,51 +0,0 @@
|
||||
From 942ef84be2203c6a784e5dd80a0e1caeb1d8c98c Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Tue, 23 Dec 2025 18:41:27 +0100
|
||||
Subject: [PATCH 42/51] mb/dell/optiplex_780: use legacy HDA verb table
|
||||
|
||||
See:
|
||||
|
||||
commit 31fc5b06a6be62b30739d33eeabe6c2727679bb1
|
||||
Author: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
|
||||
Date: Thu Aug 7 08:31:24 2025 +0900
|
||||
|
||||
device: Introduce reworked azalia verb table
|
||||
|
||||
and:
|
||||
|
||||
commit 50a59d4464917503847eeeb2df4320c35cf2f6cc
|
||||
Author: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
|
||||
Date: Mon Sep 15 16:25:21 2025 +0900
|
||||
|
||||
device: Add Kconfig to prepare for reworked verb table implementation
|
||||
|
||||
Without this change, lbmk gets the following error
|
||||
when building for Dell OptiPlex 780:
|
||||
|
||||
i386-elf-ld.bfd: build/ramstage/device/azalia_device.o: in function `azalia_codecs_init':
|
||||
/path/to/corebootclone/src/device/azalia_device.c:318:(.text.azalia_codecs_init+0xa): undefined reference to `mainboard_azalia_codecs'
|
||||
|
||||
This is a temporary fix. Upstream will require that the code
|
||||
be fully adapted at a future date. Therefore, one could consider
|
||||
the current functionality to be "deprecated".
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/dell/optiplex_780/Kconfig | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
|
||||
index fc649e35d5..172bb2fa87 100644
|
||||
--- a/src/mainboard/dell/optiplex_780/Kconfig
|
||||
+++ b/src/mainboard/dell/optiplex_780/Kconfig
|
||||
@@ -2,6 +2,7 @@
|
||||
|
||||
config BOARD_DELL_OPTIPLEX_780_COMMON
|
||||
def_bool n
|
||||
+ select AZALIA_USE_LEGACY_VERB_TABLE
|
||||
select BOARD_ROMSIZE_KB_8192
|
||||
select CPU_INTEL_SOCKET_LGA775
|
||||
select DRIVERS_I2C_CK505
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,30 +0,0 @@
|
||||
From eb141cc6c1372b754fc1cbe9f1dad9aade066e70 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Tue, 23 Dec 2025 18:46:45 +0100
|
||||
Subject: [PATCH 43/51] hp8300cmt: use legacy verb table
|
||||
|
||||
same as for the 780 optiplex patch
|
||||
|
||||
coreboot is making some changes to the way verbs are
|
||||
handled. for now, this change is being made to adapt.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/hp/compaq_elite_8300_cmt/Kconfig | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
|
||||
index d2bfd35dc4..30be7fb3fe 100644
|
||||
--- a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
|
||||
@@ -2,6 +2,7 @@ if BOARD_HP_COMPAQ_ELITE_8300_CMT
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
+ select AZALIA_USE_LEGACY_VERB_TABLE
|
||||
select BOARD_ROMSIZE_KB_16384
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,34 +0,0 @@
|
||||
From 58f8869dbd58fb9bbb205b5b3bc37cc4ae58dd5b Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Tue, 6 Jan 2026 21:42:21 +0000
|
||||
Subject: [PATCH 44/51] topton x2e n150: use old fsp
|
||||
|
||||
i added the old fsp back, so that we didn't have to
|
||||
mess around with vendor files in lbmk, because coreboot
|
||||
upstream updated the fsp repo, which modified this
|
||||
fsp file.
|
||||
|
||||
we know the old fsp worked. there's no point testing
|
||||
the new one yet, unless someone can tell me about
|
||||
real bugs that got fixed.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/soc/intel/alderlake/Kconfig | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index acb87275d4..6f1e8b9107 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -463,6 +463,7 @@ config FSP_FD_PATH
|
||||
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S
|
||||
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P
|
||||
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S
|
||||
+ default "3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if BOARD_TOPTON_X2E_N150
|
||||
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N
|
||||
default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P
|
||||
default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-31
@@ -1,31 +0,0 @@
|
||||
From c4a5a3f5d01e8947c168cf5cf22755cba3cdf2fa Mon Sep 17 00:00:00 2001
|
||||
From: Ron Nazarov <ron@noisytoot.org>
|
||||
Date: Sat, 14 Feb 2026 20:13:01 +0000
|
||||
Subject: [PATCH 45/51] mb/supermicro/x11-lga1151-series: Disable ME HECI in
|
||||
devicetree
|
||||
|
||||
Since we always use me_cleaner, this speeds up boot time by preventing
|
||||
coreboot from wasting a few seconds waiting for HECI.
|
||||
|
||||
Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350
|
||||
Signed-off-by: Ron Nazarov <ron@noisytoot.org>
|
||||
---
|
||||
src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
|
||||
index d25288420f..edbb485969 100644
|
||||
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
|
||||
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
|
||||
@@ -15,7 +15,7 @@ chip soc/intel/skylake
|
||||
device ref sa_thermal on end
|
||||
device ref south_xhci on end
|
||||
device ref thermal on end
|
||||
- device ref heci1 on end
|
||||
+ device ref heci1 off end
|
||||
device ref sata on
|
||||
register "SataSalpSupport" = "1"
|
||||
register "SataPortsEnable" = "{
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-68
@@ -1,68 +0,0 @@
|
||||
From 763c811b82b631ab85e64e150ec70df76b57fd91 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Fri, 20 Feb 2026 01:23:32 +0000
|
||||
Subject: [PATCH 46/51] util/ifdtool: option to allow region override
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/ifdtool/ifdtool.c | 13 +++++++++++--
|
||||
1 file changed, 11 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
|
||||
index 2a5365efe7..c5c3570e6a 100644
|
||||
--- a/util/ifdtool/ifdtool.c
|
||||
+++ b/util/ifdtool/ifdtool.c
|
||||
@@ -78,6 +78,8 @@ static unsigned int max_regions = 0;
|
||||
static int selected_chip = 0;
|
||||
static int platform = -1;
|
||||
|
||||
+static int ignore_region_override = 0;
|
||||
+
|
||||
static const struct region_name region_names[MAX_REGIONS] = {
|
||||
{ "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" },
|
||||
{ "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" },
|
||||
@@ -2094,7 +2096,9 @@ static void new_layout(const char *filename, char *image, int size,
|
||||
}
|
||||
|
||||
for (j = i + 1; j < max_regions; j++) {
|
||||
- if (regions_collide(&new_regions[i], &new_regions[j])) {
|
||||
+ if (ignore_region_override) {
|
||||
+ printf("Ignoring region overlap by user's will.\n");
|
||||
+ } else if (regions_collide(&new_regions[i], &new_regions[j])) {
|
||||
fprintf(stderr, "Regions would overlap:\n");
|
||||
|
||||
/* See which string is longer and make sure we pad the shorter one */
|
||||
@@ -2107,6 +2111,7 @@ static void new_layout(const char *filename, char *image, int size,
|
||||
new_regions[i].base, new_regions[i].limit);
|
||||
fprintf(stderr, " %*s : %x-%x\n", padding, region_name(j),
|
||||
new_regions[j].base, new_regions[j].limit);
|
||||
+
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
}
|
||||
@@ -2363,10 +2368,11 @@ int main(int argc, char *argv[])
|
||||
{"newvalue", 1, NULL, 'V'},
|
||||
{"topswapsize", 1, NULL, 'T'},
|
||||
{"nuke", 1, NULL, 'N'},
|
||||
+ {"ignore-region-overlap", 0, NULL, 'I'},
|
||||
{0, 0, 0, 0}
|
||||
};
|
||||
|
||||
- while ((opt = getopt_long(argc, argv, "S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?",
|
||||
+ while ((opt = getopt_long(argc, argv, "I:S:V:df:F:D:C:M:xi:n:O:s:p:T:elrugEcvth?",
|
||||
long_options, &option_index)) != EOF) {
|
||||
switch (opt) {
|
||||
case 'd':
|
||||
@@ -2610,6 +2616,9 @@ int main(int argc, char *argv[])
|
||||
}
|
||||
mode_nuke = 1;
|
||||
break;
|
||||
+ case 'I':
|
||||
+ ignore_region_override = 1;
|
||||
+ break;
|
||||
case 'v':
|
||||
print_version();
|
||||
exit(EXIT_SUCCESS);
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,44 +0,0 @@
|
||||
From 3e12bbbac3b15803de4053f8983dc908029832ac Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Fri, 20 Feb 2026 19:31:19 +0000
|
||||
Subject: [PATCH 47/51] me_cleaner: don't modify if -k is used
|
||||
|
||||
don't remove *anything*. in libreboot, we only
|
||||
ever use -k when we werely want to extract the
|
||||
ME, but otherwise not modify it. this is because
|
||||
we rely on bruteforce, detecting when me.bin is
|
||||
found based on mecleaner validation.
|
||||
|
||||
this way, we can much more reliable get the ME
|
||||
images.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/me_cleaner/me_cleaner.py | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py
|
||||
index 228bac899f..269aa4ad04 100755
|
||||
--- a/util/me_cleaner/me_cleaner.py
|
||||
+++ b/util/me_cleaner/me_cleaner.py
|
||||
@@ -677,7 +677,7 @@ if __name__ == "__main__":
|
||||
# ME 6 Ignition: wipe everything
|
||||
me6_ignition = False
|
||||
if not args.check and not args.soft_disable_only and \
|
||||
- variant == "ME" and version[0] == 6:
|
||||
+ variant == "ME" and version[0] == 6 and not args.keep_modules:
|
||||
mef.seek(ftpr_offset + 0x20)
|
||||
num_modules = unpack("<I", mef.read(4))[0]
|
||||
mef.seek(ftpr_offset + 0x290 + (num_modules + 1) * 0x60)
|
||||
@@ -689,7 +689,7 @@ if __name__ == "__main__":
|
||||
me6_ignition = True
|
||||
|
||||
if not args.check:
|
||||
- if not args.soft_disable_only and not me6_ignition:
|
||||
+ if not args.soft_disable_only and not me6_ignition and not args.keep_modules:
|
||||
print("Reading partitions list...")
|
||||
unremovable_part_fpt = b""
|
||||
extra_part_end = 0
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-600
@@ -1,600 +0,0 @@
|
||||
From 6f301fe881df4ed8759bf5b16d59d530798fee30 Mon Sep 17 00:00:00 2001
|
||||
From: Kat Inskip <kat@inskip.me>
|
||||
Date: Tue, 17 Feb 2026 16:18:15 -0800
|
||||
Subject: [PATCH 48/51] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant
|
||||
|
||||
This machine is somewhat dissimilar from the X280 in the PCIe allocations in the overridetree. It also lacks soldered RAM, having a single SODIMM slot.
|
||||
|
||||
This port was based upon the work done by Johann C Rode for the X280 and the VBT and hda verbs were obtained from that work, not obtained separately. GPIO ports and PCI-e allocations have been checked against schematics after editing.
|
||||
|
||||
Functionality has been validated on a ThinkPad X270 with machine type model 20HMS2WU03 with 16GB onboard RAM and i5-7300U CPU. The laptop has been tested running libreboot, booting Guix via GRUB payload. A check of the hardware shows no issues (video, wifi, wired ethernet, reboot, sleep, NVMe).
|
||||
|
||||
An untested variety allowing for a Skylake CPU (for 20K5 and 20K6) has been included.
|
||||
---
|
||||
src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 14 ++
|
||||
.../lenovo/sklkbl_thinkpad/Kconfig.name | 3 +
|
||||
.../sklkbl_thinkpad/variants/x270/data.vbt | Bin 0 -> 6144 bytes
|
||||
.../variants/x270/gma-mainboard.ads | 19 ++
|
||||
.../sklkbl_thinkpad/variants/x270/gpio.c | 200 ++++++++++++++++++
|
||||
.../sklkbl_thinkpad/variants/x270/hda_verb.c | 124 +++++++++++
|
||||
.../variants/x270/memory_init_params.c | 19 ++
|
||||
.../variants/x270/overridetree.cb | 89 ++++++++
|
||||
8 files changed, 468 insertions(+)
|
||||
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt
|
||||
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c
|
||||
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
|
||||
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c
|
||||
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb
|
||||
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
|
||||
index 9d4b5f4965..1aaef40a0c 100644
|
||||
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
|
||||
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
|
||||
@@ -59,6 +59,16 @@ config BOARD_LENOVO_X280
|
||||
select SOC_INTEL_KABYLAKE
|
||||
select HAVE_SPD_IN_CBFS
|
||||
|
||||
+config BOARD_LENOVO_X270_20K6
|
||||
+ bool
|
||||
+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
|
||||
+ select SOC_INTEL_SKYLAKE
|
||||
+
|
||||
+config BOARD_LENOVO_X270_20HM
|
||||
+ bool
|
||||
+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
|
||||
+ select SOC_INTEL_KABYLAKE
|
||||
+
|
||||
if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
|
||||
|
||||
config MAINBOARD_DIR
|
||||
@@ -70,6 +80,8 @@ config VARIANT_DIR
|
||||
default "t480s" if BOARD_LENOVO_T480S
|
||||
default "t580" if BOARD_LENOVO_T580
|
||||
default "x280" if BOARD_LENOVO_X280
|
||||
+ default "x270" if BOARD_LENOVO_X270_20HM
|
||||
+ default "x270" if BOARD_LENOVO_X270_20K6
|
||||
|
||||
config OVERRIDE_DEVICETREE
|
||||
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
@@ -80,6 +92,8 @@ config MAINBOARD_PART_NUMBER
|
||||
default "T480s" if BOARD_LENOVO_T480S
|
||||
default "T580" if BOARD_LENOVO_T580
|
||||
default "X280" if BOARD_LENOVO_X280
|
||||
+ default "X270" if BOARD_LENOVO_X270_20HM
|
||||
+ default "X270" if BOARD_LENOVO_X270_20K6
|
||||
|
||||
config CBFS_SIZE
|
||||
default 0x900000
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
|
||||
index 1d2888840f..43f9296bc5 100644
|
||||
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
|
||||
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
|
||||
@@ -14,3 +14,6 @@ config BOARD_LENOVO_T580
|
||||
|
||||
config BOARD_LENOVO_X280
|
||||
bool "ThinkPad X280"
|
||||
+
|
||||
+config BOARD_LENOVO_X270_20HM
|
||||
+ bool "ThinkPad X270"
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..bfb312850e0ab4ea834c535df35edb45834ed248
|
||||
GIT binary patch
|
||||
literal 6144
|
||||
zcmeHKUu;ul6hF83w!Qs&FT30g8FkDf5a<SMw;NO(Gu-~!ShtRLf0!jPp+KunJ2ti<
|
||||
z!(djDC1OmZCThSK>4S-84?3TW@j;A<!SI4Hfy4)cZ%Ryzkr$&_&%L+X*all8F+}XS
|
||||
zJ>Pe}bI<wR^PTT+Hw^^)v9IeuG|<(CMM{ANOgTp7QVK?5eFwvV{=mUtG#2W@Z{Q*L
|
||||
zuHvs704a`JC;2pgbL8lFI^*rFBiLwTS1^j*!-oem>Bew+?D_HG5sZf-7&vkyok@=#
|
||||
z8c(ONZ(wf#4P2Q8j}K;2xbOJT;q+(=8en9Nz8wwCI}kNrqtD;ir1>5vxw&Phzs2{M
|
||||
z%))J<Sa&=U4fIE1`!Lpv;YeSgudl5;7(IaT-dIN@80l{d%gpFYXn5r0=-@NYj-xkJ
|
||||
zhfSKMZ6`b*njvFocyy!z1DOo=8a89tn;uJ#zK~8e$jtD+2%^9NaCUG8frDF3Ac;bU
|
||||
zsCz}M7L~A|ZxXOdP~y6h)KNnvD(Kq;tPvHG6S|U6bOmfXIhz2mS%j}9X0wZ+T_bqj
|
||||
zXxnr^s)&$SfU8N+0TPu)Tf622u#*~`3WpR45fbY~tLKVVqTxv7L=J6+U|N}iqKKzV
|
||||
zE3;KBI5a<PSkaG2QQ)<etxVHdmtteC!a2zj7Ps%Ly}K390sQ$Qc~QN9R&g4<C)O^|
|
||||
zCHYIxE+Pzy3Y;Q7OYE{Us3cxbyoK0Dyqma<I7WPc_z3Y3@d@J7#IF*+Nqm9Wm84JD
|
||||
z=$S38FW#=XSD9S~mKBnGp-}j|Pyl<vHY;76)j4&$rPG}wMJemd7bPnq0P-!;{gk9i
|
||||
z=%jhbi>*^Nkaf-o`vHErAoDN*Y&A{MBB|1XA+35B93JbHvvt;HaeY7Ec#IkF@Xxj@
|
||||
zP6k(;H@P#F3nedGs=JfjzpYa!OobkwSsK#P$I2^BlEsV4e37vB4$G)q{*N<I(*ajq
|
||||
z*&JS9uZYPFRw8QundXtFXdc=`+8A^?Y!r~71H4cTVb}y!kc7B->k!R-c0tBVQz1gd
|
||||
z3e(o>A@DI1+dL($vl6C>0P5ZV{-g^pxYUnb>@yes;8K5cv0E<O$kd&T?O~W^>Iue9
|
||||
zGkl+^pEC9(!=IS?2V-_OZgs0qxY=Ge4!PAyH+#j6AGy^p-0ZR&e|4+8#AFGZCACdr
|
||||
zF$s@L>dO*)UBXW!^=pZJE8*{w>Xz9W8F$NSx6GcD@g-S3E3@;mT(8=*w(DGW^(yn4
|
||||
zAdX73_atnRS>NOos_hk9XyacxDE>*#THX@!3ERpD`3eMIq6WR$s^UQVC#{1Gq^xt7
|
||||
zU?8;e8r(gGm_M5z*|kA$YW)zZ-l2VHoqv+IZZ{Mr6cJz<1g##<^?;^pBXkQfsMbG8
|
||||
zj)o*n*gYj7Okj_PE?l=Ea5?ktR3gF$jT6^<Je&2zx%n8loWqPkcg&O!L&qLnJ3P~*
|
||||
z>lfz{96(n%>cxN^_?5@v=|=~qd!SZp&lSg_nlhO)&rS-Zlsuej$mNrsT3tiG@m({M
|
||||
zLe6DKG@7OK!rMxtIkS-v>J2YzEOK;RC4{_vs)Sy=U6;SoGqpjBpI>WunFu_%4N1}+
|
||||
zr66ea`laMlN~`X%R;)1}c-lG)1mlXaawb#jKo7uXt@_M-9(a%~1Ur_1aKi)nIIh(s
|
||||
zEo69Ey~xpeG&5<f3uBVseO=gEven0SZPydqZ;zqEL;w*S*2-EAp-zWn7Alj9vfA(}
|
||||
zX3{w6L5jA=55^B2O=tEU8cII^4Wm=b)7I1A=v1~qV!HDZ{Y9GY{GJ!)WJ`0;WudU2
|
||||
z?%VTZTSVK|z$@((W&{}Qr^71++qk#jN4{YO;LIHTH^k+$U4C26Ksf{D43sla&OkW>
|
||||
I4@?IB2821pg#Z8m
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..fcfbd75a92
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gma-mainboard.ads
|
||||
@@ -0,0 +1,19 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (eDP,
|
||||
+ DP1,
|
||||
+ DP2,
|
||||
+ HDMI1,
|
||||
+ HDMI2,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..ec5db9c53c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/gpio.c
|
||||
@@ -0,0 +1,200 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <soc/gpio.h>
|
||||
+#include "../../variant.h"
|
||||
+
|
||||
+static const struct pad_config gpio_table[] = {
|
||||
+ /* ------- GPIO Community 0 ------- */
|
||||
+
|
||||
+ /* ------- GPIO Group GPP_A ------- */
|
||||
+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */
|
||||
+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */
|
||||
+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */
|
||||
+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */
|
||||
+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */
|
||||
+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */
|
||||
+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */
|
||||
+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */
|
||||
+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */
|
||||
+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */
|
||||
+ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */
|
||||
+ PAD_NC(GPP_A11, NONE),
|
||||
+ PAD_NC(GPP_A12, NONE), /* BM_BUSY#/ISH_GP6 */
|
||||
+ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */
|
||||
+ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */
|
||||
+ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSACK*/
|
||||
+ PAD_NC(GPP_A16, NONE),
|
||||
+ PAD_NC(GPP_A17, NONE),
|
||||
+ PAD_NC(GPP_A18, NONE), /* ISH_GP0 */
|
||||
+ PAD_NC(GPP_A19, NONE), /* ISH_GP1 */
|
||||
+ PAD_NC(GPP_A20, NONE), /* ISH_GP2 */
|
||||
+ PAD_NC(GPP_A21, NONE), /* ISH_GP3 */
|
||||
+ PAD_NC(GPP_A22, NONE), /* ISH_GP4 */
|
||||
+ PAD_NC(GPP_A23, NONE), /* ISH_GP5 */
|
||||
+
|
||||
+ /* ------- GPIO Group GPP_B ------- */
|
||||
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */
|
||||
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */
|
||||
+ PAD_NC(GPP_B2, NONE),
|
||||
+ PAD_NC(GPP_B3, NONE),
|
||||
+ PAD_NC(GPP_B4, NONE),
|
||||
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (Card Reader / SD) */
|
||||
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE1 (WLAN) */
|
||||
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE2 (GBE) */
|
||||
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (NVMe) */
|
||||
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
|
||||
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WWAN) */
|
||||
+ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* -EXT_PWR_GATE */
|
||||
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */
|
||||
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */
|
||||
+ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */
|
||||
+ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */
|
||||
+ PAD_NC(GPP_B16, NONE), /* GSPIO0_CLK */
|
||||
+ PAD_NC(GPP_B17, NONE),
|
||||
+ PAD_NC(GPP_B18, NONE),
|
||||
+ PAD_NC(GPP_B19, NONE),
|
||||
+ PAD_NC(GPP_B20, NONE),
|
||||
+ PAD_NC(GPP_B21, NONE),
|
||||
+ PAD_NC(GPP_B22, NONE),
|
||||
+ PAD_NC(GPP_B23, NONE),
|
||||
+
|
||||
+ /* ------- GPIO Community 1 ------- */
|
||||
+
|
||||
+ /* ------- GPIO Group GPP_C ------- */
|
||||
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
|
||||
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
|
||||
+ PAD_NC(GPP_C2, NONE), /* -SMBALERT */
|
||||
+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */
|
||||
+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
|
||||
+ PAD_NC(GPP_C5, NONE),
|
||||
+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */
|
||||
+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */
|
||||
+ PAD_NC(GPP_C8, NONE),
|
||||
+ PAD_NC(GPP_C9, NONE),
|
||||
+ PAD_NC(GPP_C10, NONE),
|
||||
+ PAD_NC(GPP_C11, NONE),
|
||||
+ PAD_NC(GPP_C12, NONE),
|
||||
+ PAD_NC(GPP_C13, NONE),
|
||||
+ PAD_NC(GPP_C14, NONE),
|
||||
+ PAD_NC(GPP_C15, NONE),
|
||||
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */
|
||||
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */
|
||||
+ PAD_NC(GPP_C18, NONE),
|
||||
+ PAD_NC(GPP_C19, NONE),
|
||||
+ PAD_NC(GPP_C20, NONE),
|
||||
+ PAD_NC(GPP_C21, NONE), /* X280: TBT_FORCE_PWR X270: INT#_TYPEC_CPU */
|
||||
+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
|
||||
+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
|
||||
+
|
||||
+ /* ------- GPIO Group GPP_D ------- */
|
||||
+ PAD_NC(GPP_D0, NONE),
|
||||
+ PAD_NC(GPP_D1, NONE),
|
||||
+ PAD_NC(GPP_D2, NONE),
|
||||
+ PAD_NC(GPP_D3, NONE),
|
||||
+ PAD_NC(GPP_D4, NONE),
|
||||
+ PAD_NC(GPP_D5, NONE),
|
||||
+ PAD_NC(GPP_D6, NONE),
|
||||
+ PAD_NC(GPP_D7, NONE),
|
||||
+ PAD_NC(GPP_D8, NONE),
|
||||
+ PAD_NC(GPP_D9, UP_20K),
|
||||
+ PAD_NC(GPP_D10, NONE),
|
||||
+ PAD_NC(GPP_D11, UP_20K),
|
||||
+ PAD_NC(GPP_D12, UP_20K),
|
||||
+ PAD_NC(GPP_D13, NONE),
|
||||
+ PAD_NC(GPP_D14, NONE),
|
||||
+ PAD_NC(GPP_D15, NONE),
|
||||
+ PAD_NC(GPP_D16, NONE),
|
||||
+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */
|
||||
+ PAD_NC(GPP_D18, NONE),
|
||||
+ PAD_NC(GPP_D19, NONE),
|
||||
+ PAD_NC(GPP_D20, NONE),
|
||||
+ PAD_NC(GPP_D21, NONE),
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */
|
||||
+ PAD_NC(GPP_D23, NONE),
|
||||
+
|
||||
+ /* ------- GPIO Group GPP_E ------- */
|
||||
+ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */
|
||||
+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -SATA1_DTCT */
|
||||
+ PAD_NC(GPP_E2, NONE),
|
||||
+ PAD_NC(GPP_E3, NONE), /* X280: -TBT_PLUG_EVENT X270: ? */
|
||||
+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */
|
||||
+ PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA1_DEVSLP */
|
||||
+ PAD_NC(GPP_E6, NONE),
|
||||
+ PAD_CFG_GPO(GPP_E7, 1, DEEP), /* -WWAN_DISABLE */
|
||||
+ PAD_NC(GPP_E8, NONE),
|
||||
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */
|
||||
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */
|
||||
+ PAD_NC(GPP_E11, NONE),
|
||||
+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */
|
||||
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */
|
||||
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */
|
||||
+ PAD_NC(GPP_E15, NONE),
|
||||
+ PAD_NC(GPP_E16, NONE),
|
||||
+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
|
||||
+ PAD_NC(GPP_E18, NONE),
|
||||
+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
|
||||
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */
|
||||
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */
|
||||
+ PAD_NC(GPP_E22, NONE),
|
||||
+ PAD_NC(GPP_E23, NONE),
|
||||
+
|
||||
+ /* ------- GPIO Community 2 ------- */
|
||||
+
|
||||
+ /* -------- GPIO Group GPD -------- */
|
||||
+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */
|
||||
+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */
|
||||
+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */
|
||||
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */
|
||||
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */
|
||||
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */
|
||||
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */
|
||||
+ PAD_NC(GPD7, NONE),
|
||||
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */
|
||||
+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */
|
||||
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */
|
||||
+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
|
||||
+
|
||||
+ /* ------- GPIO Community 3 ------- */
|
||||
+
|
||||
+ /* ------- GPIO Group GPP_F ------- */
|
||||
+ PAD_NC(GPP_F0, NONE), /* NFC_ACTIVE */
|
||||
+ PAD_NC(GPP_F1, NONE),
|
||||
+ PAD_NC(GPP_F2, NONE),
|
||||
+ PAD_NC(GPP_F3, NONE),
|
||||
+ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */
|
||||
+ PAD_NC(GPP_F5, UP_20K),
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI), /* -INT_MIC_DTCT */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG0 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG1 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG2 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG3 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI), /* PLANARID0 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI), /* PLANARID1 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI), /* PLANARID2 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI), /* PLANARID3 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID0 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID1 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID2 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID3 */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID4 */
|
||||
+ PAD_NC(GPP_F21, UP_20K),
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI), /* -TAMPER_SW_DTCT */
|
||||
+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI), /* -SC_DTCT */
|
||||
+
|
||||
+ /* ------- GPIO Group GPP_G ------- */
|
||||
+ PAD_NC(GPP_G0, NONE), /* SD_CMD */
|
||||
+ PAD_NC(GPP_G1, NONE), /* SD_DATA0 */
|
||||
+ PAD_NC(GPP_G2, NONE), /* SD_DATA1 */
|
||||
+ PAD_NC(GPP_G3, NONE), /* SD_DATA2 */
|
||||
+ PAD_NC(GPP_G4, NONE), /* X280: TBT_RTD3_PWR_EN X270: SD_DATA3 */
|
||||
+ PAD_NC(GPP_G5, NONE), /* X280: TBT_FORCE_USB_PWR X270: SD_CD# */
|
||||
+ PAD_NC(GPP_G6, NONE), /* X280: -TBT_PERST X270: SD_CLK */
|
||||
+ PAD_NC(GPP_G7, NONE), /* X280: -TBT_PCIE_WAKE X270: SD_WP */
|
||||
+
|
||||
+};
|
||||
+
|
||||
+void variant_config_gpios(void)
|
||||
+{
|
||||
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
+}
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..089e605eaf
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
|
||||
@@ -0,0 +1,124 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257
|
||||
+ 0x17aa2256, // Subsystem ID
|
||||
+ 18,
|
||||
+ AZALIA_SUBVENDOR(0, 0x17aa2256),
|
||||
+
|
||||
+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
|
||||
+ AZALIA_INTEGRATED,
|
||||
+ AZALIA_INTERNAL,
|
||||
+ AZALIA_MIC_IN,
|
||||
+ AZALIA_OTHER_DIGITAL,
|
||||
+ AZALIA_COLOR_UNKNOWN,
|
||||
+ AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
+ 2, 0
|
||||
+ )),
|
||||
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
|
||||
+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
|
||||
+ AZALIA_INTEGRATED,
|
||||
+ AZALIA_INTERNAL,
|
||||
+ AZALIA_SPEAKER,
|
||||
+ AZALIA_OTHER_ANALOG,
|
||||
+ AZALIA_COLOR_UNKNOWN,
|
||||
+ AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
+ 1, 0
|
||||
+ )),
|
||||
+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
|
||||
+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
|
||||
+ AZALIA_JACK,
|
||||
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
|
||||
+ AZALIA_MIC_IN,
|
||||
+ AZALIA_STEREO_MONO_1_8,
|
||||
+ AZALIA_BLACK,
|
||||
+ AZALIA_JACK_PRESENCE_DETECT,
|
||||
+ 3, 0
|
||||
+ )),
|
||||
+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
|
||||
+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
|
||||
+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
|
||||
+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
|
||||
+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
|
||||
+ AZALIA_JACK,
|
||||
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
|
||||
+ AZALIA_HP_OUT,
|
||||
+ AZALIA_STEREO_MONO_1_8,
|
||||
+ AZALIA_BLACK,
|
||||
+ AZALIA_JACK_PRESENCE_DETECT,
|
||||
+ 1, 15
|
||||
+ )),
|
||||
+
|
||||
+ //==========Widget node 0x20 - 0 :Hidden register SW reset
|
||||
+ 0x0205001A,
|
||||
+ 0x0204C003,
|
||||
+ 0x0205001A,
|
||||
+ 0x0204C003,
|
||||
+ 0x05850000,
|
||||
+ 0x0584F880,
|
||||
+ 0x05850000,
|
||||
+ 0x0584F880,
|
||||
+ //==========Widget node 0x20 - 1 : ClassD 2W
|
||||
+ 0x02050038,
|
||||
+ 0x02048981,
|
||||
+ 0x0205001B,
|
||||
+ 0x02040A4B,
|
||||
+ //==========Widget node 0x20 - 2
|
||||
+ 0x0205003C,
|
||||
+ 0x02043154,
|
||||
+ 0x0205003C,
|
||||
+ 0x02043114,
|
||||
+ //==========Widget node 0x20 - 3 :
|
||||
+ 0x02050046,
|
||||
+ 0x02040004,
|
||||
+ 0x05750003,
|
||||
+ 0x057409A3,
|
||||
+ //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD
|
||||
+ 0x02050009,
|
||||
+ 0x02046003,
|
||||
+ 0x0205000A,
|
||||
+ 0x02047770,
|
||||
+ //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB)
|
||||
+ 0x02050037,
|
||||
+ 0x0204FE15,
|
||||
+ 0x02050030,
|
||||
+ 0x02049004,
|
||||
+
|
||||
+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
|
||||
+ 0x80860101, // Subsystem ID
|
||||
+ 4,
|
||||
+ AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
+
|
||||
+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
|
||||
+ AZALIA_JACK,
|
||||
+ AZALIA_DIGITAL_DISPLAY,
|
||||
+ AZALIA_DIGITAL_OTHER_OUT,
|
||||
+ AZALIA_OTHER_DIGITAL,
|
||||
+ AZALIA_COLOR_UNKNOWN,
|
||||
+ AZALIA_JACK_PRESENCE_DETECT,
|
||||
+ 1, 0
|
||||
+ )),
|
||||
+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
|
||||
+ AZALIA_JACK,
|
||||
+ AZALIA_DIGITAL_DISPLAY,
|
||||
+ AZALIA_DIGITAL_OTHER_OUT,
|
||||
+ AZALIA_OTHER_DIGITAL,
|
||||
+ AZALIA_COLOR_UNKNOWN,
|
||||
+ AZALIA_JACK_PRESENCE_DETECT,
|
||||
+ 1, 0
|
||||
+ )),
|
||||
+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
|
||||
+ AZALIA_JACK,
|
||||
+ AZALIA_DIGITAL_DISPLAY,
|
||||
+ AZALIA_DIGITAL_OTHER_OUT,
|
||||
+ AZALIA_OTHER_DIGITAL,
|
||||
+ AZALIA_COLOR_UNKNOWN,
|
||||
+ AZALIA_JACK_PRESENCE_DETECT,
|
||||
+ 1, 0
|
||||
+ )),
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[] = {};
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c
|
||||
new file mode 100644
|
||||
index 0000000000..a2317c026d
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/memory_init_params.c
|
||||
@@ -0,0 +1,19 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <soc/romstage.h>
|
||||
+#include <spd_bin.h>
|
||||
+
|
||||
+void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
+{
|
||||
+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
|
||||
+ mem_cfg->DqPinsInterleaved = false; /* DDR_DQ probably not in interleave mode */
|
||||
+ mem_cfg->CaVrefConfig = 1; /* VREF_CA to CH_A */
|
||||
+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
|
||||
+
|
||||
+ /* Get SPD for memory slots */
|
||||
+ struct spd_block blk = { .addr_map = { 0x50 } };
|
||||
+ get_spd_smbus(&blk);
|
||||
+ dump_spd_info(&blk);
|
||||
+
|
||||
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
|
||||
+}
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..3191cdfac5
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb
|
||||
@@ -0,0 +1,89 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+chip soc/intel/skylake
|
||||
+ device domain 0 on
|
||||
+ device ref south_xhci on
|
||||
+ register "usb2_ports" = "{
|
||||
+ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on)
|
||||
+ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A)
|
||||
+ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot)
|
||||
+ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB docking station)
|
||||
+ [4] = USB2_PORT_MID(OC_SKIP), // JIRCAM (IR camera)
|
||||
+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB)
|
||||
+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB)
|
||||
+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam)
|
||||
+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader)
|
||||
+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel)
|
||||
+ }"
|
||||
+ register "usb3_ports" = "{
|
||||
+ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on)
|
||||
+ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A)
|
||||
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader)
|
||||
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSB3 (USB docking station)
|
||||
+ }"
|
||||
+ end
|
||||
+
|
||||
+ # PCIe
|
||||
+ # PCIe Controller 1 - 1x2 + 2x1
|
||||
+ # PCIE 1 - RP1 - Media / SD - CLKOUT0 - CLKREQ0
|
||||
+ # PCIE 2 - USB3 Port
|
||||
+ # PCIE 3 - RP3 - WiGig - CLKOUT1 - CLKREQ1
|
||||
+ # PCIE 3 - RP3 - WLAN - CLKOUT2 - CLKREQ2
|
||||
+ # PCIE 4 - GbE - GbE - CLKOUT3 - CLKREQ3
|
||||
+ # PCIe Controller 2 - 1x4
|
||||
+ # PCIE 5 - RP5 - NVMe - CLKOUT4 - CLKREQ4
|
||||
+ # PCIe Controller 3 - 4x1
|
||||
+ # PCIE 7 - RP8 - WWAN - CLKOUT5 - CLKREQ5
|
||||
+ # PCIE 8 - Optane
|
||||
+
|
||||
+ # Media / SD - x2
|
||||
+ device ref pcie_rp1 on
|
||||
+ register "PcieRpClkReqSupport[0]" = "true"
|
||||
+ register "PcieRpClkReqNumber[0]" = "0"
|
||||
+ register "PcieRpClkSrcNumber[0]" = "0"
|
||||
+ register "PcieRpAdvancedErrorReporting[0]" = "true"
|
||||
+ register "PcieRpHotPlug[0]" = "true"
|
||||
+ end
|
||||
+
|
||||
+ # M.2 WLAN x1
|
||||
+ device ref pcie_rp3 on
|
||||
+ register "PcieRpClkReqSupport[2]" = "true"
|
||||
+ register "PcieRpClkReqNumber[2]" = "2"
|
||||
+ register "PcieRpClkSrcNumber[2]" = "2"
|
||||
+ register "PcieRpAdvancedErrorReporting[2]" = "true"
|
||||
+ register "PcieRpLtrEnable[2]" = "true"
|
||||
+ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
|
||||
+ end
|
||||
+
|
||||
+ # Ethernet (clobbers RP4)
|
||||
+ device ref gbe on
|
||||
+ register "LanClkReqSupported" = "true"
|
||||
+ register "LanClkReqNumber" = "3"
|
||||
+ register "PcieRpClkReqNumber[3]" = "3"
|
||||
+ register "PcieRpClkSrcNumber[3]" = "3"
|
||||
+ register "EnableLanLtr" = "true"
|
||||
+ register "EnableLanK1Off" = "true"
|
||||
+ end
|
||||
+
|
||||
+ # M.2 2280 SSD - x4 (RP9)
|
||||
+ device ref pcie_rp5 on
|
||||
+ register "PcieRpClkReqSupport[4]" = "true"
|
||||
+ register "PcieRpClkReqNumber[4]" = "4"
|
||||
+ register "PcieRpClkSrcNumber[4]" = "4"
|
||||
+ register "PcieRpAdvancedErrorReporting[4]" = "true"
|
||||
+ register "PcieRpLtrEnable[4]" = "true"
|
||||
+ register "PcieRpHotPlug[4]" = "false"
|
||||
+ smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
|
||||
+ end
|
||||
+
|
||||
+ # M.2 WWAN x1
|
||||
+ device ref pcie_rp8 on
|
||||
+ register "PcieRpClkReqSupport[7]" = "true"
|
||||
+ register "PcieRpClkReqNumber[7]" = "5"
|
||||
+ register "PcieRpClkSrcNumber[7]" = "5"
|
||||
+ register "PcieRpAdvancedErrorReporting[7]" = "true"
|
||||
+ register "PcieRpLtrEnable[7]" = "true"
|
||||
+ smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-129
@@ -1,129 +0,0 @@
|
||||
From 4557102ed2f7e1355cc3a331c6452884458b7a5e Mon Sep 17 00:00:00 2001
|
||||
From: Kat Inskip <kat@inskip.me>
|
||||
Date: Sat, 21 Feb 2026 19:48:17 +0000
|
||||
Subject: [PATCH 49/51] mb/lenovo/x270: Provide correct vbt and hda_verb
|
||||
|
||||
---
|
||||
.../sklkbl_thinkpad/variants/x270/data.vbt | Bin 6144 -> 4449 bytes
|
||||
.../sklkbl_thinkpad/variants/x270/hda_verb.c | 29 +++++++++---------
|
||||
2 files changed, 15 insertions(+), 14 deletions(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt
|
||||
index bfb312850e0ab4ea834c535df35edb45834ed248..c6561a9c57e4e600bc0adb5f6679f2f5d6b6c640 100644
|
||||
GIT binary patch
|
||||
delta 1043
|
||||
zcmcgq-Afcv6hC)nXFtw-?CgzfEwH0L<XY;iA6b&MqFA;<TNWfjpGpWJ1oe;wyAeeY
|
||||
zMcY(Q_7B)gu#XWD5&2>gQ9&f-Qz1ka^prZC-JMFP=YHJZ{oQls$2s?7a?V`MjktC+
|
||||
zmIBAkE35L3T{R08;KY{a0fvRBG?I>!>>E2ha<Xn;f(Fw0W827aDAP^J*2b1rqGVGu
|
||||
z4=35iOQ$2bxub1s{!x>F{QO$c=4v8Y8%=?LrDlLIKmZ^Gf5CQN1XgElP&$RejtyZ5
|
||||
z##fpUKrO{7px=4oVy};I82ZMAiwFT|EMc$(iBg6qn;Wt%1))HsoGWjGZ6rwfW9y;f
|
||||
z+P1?LzVFv3072#UoFOjAux+UOm(9&6an}i+$f~@7#c_7}8xbIi0I-AuW05M@qt?NB
|
||||
zRe{Uu7N`$QfgK@eiP+G~9Av)K5N4SlnO~Vdm|74a%B*D8G8>rf%r0h{d4PGCIT}nO
|
||||
z1kb>tr{s#a!pI3<V`T+90M`?coAC1!em=6m55PcQ^@V_29c<|Lyif?1z2|Z8yl`i+
|
||||
za*7>%9?|1Fclp|1QdQ0P@qX6gB^>l)&nqO<`-*_VTP>kxOWk0S0g$)_YB$m-%5#X9
|
||||
zknW*;i1-ZYGfEFJqEnMDyL3$JbV`>Ob-boiL6=W;oYCpKE<*;!3~D!IpMe7goi*fD
|
||||
z18*Djz>w1hzA<RYkWmvWP1<3~y(SKswDE!|T@&w`^u&~}Onh&WX2~@cR$H{wl7ki=
|
||||
zx6FE}<&+P??J{cInaCmcvC%H#g%KPIM5p**le^3FJ5b#@YrFf!lJ5Fw^|}hU(#yx|
|
||||
p1AZCEz%XnQci@u>jgD~h(eazMzGB3(Uim8EziUhBPY#yb{{-gtq*(v}
|
||||
|
||||
delta 808
|
||||
zcmX|<OGp)A6vxjzu6O3ljQ8{Nk(S9(BbCHE<JFt5XtK0?gjPgG5JI{rvIi7a80sQQ
|
||||
zg6uLC1c5Drz(r|y5!E6?2%}X52`vJ5*`f#+6=ig;dixJQ&i|b6%=hA3C>e2Y=7&(6
|
||||
z1vl8CW+z-x@(%LgW907_fIdYjust^(YddwW|77|83Odly8SQ9J9BnF&$EbTJc{NqB
|
||||
z8Y0(=dhuwr>(#T5HPpr%yse4n(Ztt0#S21;HymyT1(vJ9HuOD)Uv5yoA$IBhCY^G0
|
||||
z(d~;~pIj21x?ibNp&{7!_@YPn0@PYX)d4me@cII*iNKvl04<fOJ`e{MF*<zc1s|X%
|
||||
zJC(chVSo^qn;|R|QrNAw`D<+_*4m8JpR6z`q^3-IP5>c{p;T8;tmbA>dO!%ck**r)
|
||||
zYT&6wLA@%NymTDqLC|>RKbP37?tsmjG8Gpd7)9xHCH87_(8_ZjHv|kZ<BS<X$YwS&
|
||||
zWsJu(GA&FObC@~C3^0StD07{;9m+tMV3S<Zrc_h#0)js;n95j}oXtROc;(nI$pWaj
|
||||
z1=>ZECQLbP;tP`&Ou1y@vPq>VYZ132^`jg_97TGF@)_bR(jv;=h#`x%SaO?%yDb{9
|
||||
z<gkTf7CpA)D+}LR^xcx0jgCz*TejHPWz%_EUbQh{Q|VJ%zOnJWO}}huIhgBEqa*h^
|
||||
zc*vp4jvROJt`nTbYt~4(P9Mq2geJ`mW^jY-ijUksQ&-|wH$8%!dwj5hWYjvMM?@L)
|
||||
zOt#PQ3z%&Gr0KzQq%L?F$qyDI#p`ontd(z|4G<1OH}pZJatA(ZRZ|e`6IX&6k;fD!
|
||||
Re`fqpo`k>sC+JqU`~#!PkzxP<
|
||||
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
|
||||
index 089e605eaf..60289355f8 100644
|
||||
--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
|
||||
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
|
||||
@@ -3,10 +3,10 @@
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
- 0x10ec0257, // Vendor/Device ID: Realtek ALC257
|
||||
- 0x17aa2256, // Subsystem ID
|
||||
- 18,
|
||||
- AZALIA_SUBVENDOR(0, 0x17aa2256),
|
||||
+ 0x10ec0298, // Vendor/Device ID: Realtek ALC298
|
||||
+ 0x17aa5062, // Subsystem ID
|
||||
+ 19,
|
||||
+ AZALIA_SUBVENDOR(0, 0x17aa5062),
|
||||
|
||||
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
|
||||
AZALIA_INTEGRATED,
|
||||
@@ -15,7 +15,7 @@ const u32 cim_verb_data[] = {
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
- 2, 0
|
||||
+ 4, 0
|
||||
)),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
|
||||
AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
|
||||
@@ -27,28 +27,29 @@ const u32 cim_verb_data[] = {
|
||||
AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
1, 0
|
||||
)),
|
||||
- AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
|
||||
- AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
|
||||
+ AZALIA_PIN_CFG(0, 0x17, AZALIA_PIN_CFG_NC(0)),
|
||||
+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
|
||||
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
|
||||
AZALIA_MIC_IN,
|
||||
AZALIA_STEREO_MONO_1_8,
|
||||
AZALIA_BLACK,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
3, 0
|
||||
)),
|
||||
+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
|
||||
- AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
|
||||
- AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
|
||||
+ AZALIA_PIN_CFG(0, 0x1d, 0x40648605), // does not describe a jack or internal device
|
||||
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
|
||||
+ AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
- AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
|
||||
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_LEFT,
|
||||
AZALIA_HP_OUT,
|
||||
AZALIA_STEREO_MONO_1_8,
|
||||
AZALIA_BLACK,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
- 1, 15
|
||||
+ 2, 0
|
||||
)),
|
||||
|
||||
//==========Widget node 0x20 - 0 :Hidden register SW reset
|
||||
@@ -107,7 +108,7 @@ const u32 cim_verb_data[] = {
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
- 1, 0
|
||||
+ 2, 0
|
||||
)),
|
||||
AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
@@ -116,7 +117,7 @@ const u32 cim_verb_data[] = {
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
- 1, 0
|
||||
+ 3, 0
|
||||
)),
|
||||
};
|
||||
|
||||
--
|
||||
2.47.3
|
||||
|
||||
-1530
File diff suppressed because it is too large
Load Diff
-411
@@ -1,411 +0,0 @@
|
||||
From 31f8f8de88963b1329aeac1b5c09de53165e7ce8 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Thu, 23 Apr 2026 20:27:35 +0100
|
||||
Subject: [PATCH 51/51] disable -Werror in the coreboot build system
|
||||
|
||||
we don't want it in libreboot, a coreboot distro.
|
||||
|
||||
you have NO IDEA how many times users have complained
|
||||
in the past that libreboot doesn't build, and it was
|
||||
code that was actually fine in practice, but the compiler
|
||||
was just being overly pedantic. i often sit there and
|
||||
fix each one. no more.
|
||||
|
||||
just remove Werror. this shall be libreboot policy from now
|
||||
on. it makes sense for coreboot to enable this, because that
|
||||
is for developers. coreboot-distro is for coreboot users.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
Makefile.mk | 2 --
|
||||
payloads/libpayload/Makefile.mk | 2 +-
|
||||
payloads/libpayload/Makefile.payload | 2 +-
|
||||
payloads/libpayload/sample/Makefile | 2 +-
|
||||
payloads/libpayload/sample/arch_mock/Makefile | 2 +-
|
||||
payloads/libpayload/tests/Makefile.mk | 2 +-
|
||||
payloads/linuxcheck/Makefile | 2 +-
|
||||
src/lib/gnat/Makefile.mk | 1 -
|
||||
tests/Makefile.common | 2 +-
|
||||
util/amdfwtool/Makefile.mk | 3 ++-
|
||||
util/archive/Makefile | 3 ++-
|
||||
util/bincfg/Makefile | 3 ++-
|
||||
util/bucts/Makefile | 3 ++-
|
||||
util/cbfstool/Makefile.mk | 2 +-
|
||||
util/cbfstool/lz4/Makefile | 8 ++++----
|
||||
util/cbmem/Makefile | 3 ++-
|
||||
util/ectool/Makefile | 2 +-
|
||||
util/futility/Makefile.mk | 2 +-
|
||||
util/ifdtool/Makefile.mk | 2 +-
|
||||
util/intelvbttool/Makefile | 2 +-
|
||||
util/msrtool/configure | 2 +-
|
||||
util/pmh7tool/Makefile | 2 +-
|
||||
util/superiotool/Makefile | 6 +++---
|
||||
util/uio_usbdebug/Makefile | 2 +-
|
||||
util/xcompile/xcompile | 2 +-
|
||||
25 files changed, 33 insertions(+), 31 deletions(-)
|
||||
|
||||
diff --git a/Makefile.mk b/Makefile.mk
|
||||
index 8f541ad187..ff9ed89e00 100644
|
||||
--- a/Makefile.mk
|
||||
+++ b/Makefile.mk
|
||||
@@ -555,7 +555,6 @@ CFLAGS_common += -ffunction-sections
|
||||
CFLAGS_common += -fdata-sections
|
||||
CFLAGS_common += -fno-pie
|
||||
CFLAGS_common += -Wstring-compare
|
||||
-CFLAGS_common += -Werror
|
||||
ifeq ($(CONFIG_COMPILER_GCC),y)
|
||||
CFLAGS_common += -Wold-style-declaration
|
||||
CFLAGS_common += -Wcast-function-type
|
||||
@@ -581,7 +580,6 @@ endif
|
||||
ADAFLAGS_common += -gnatp
|
||||
ADAFLAGS_common += -Wuninitialized
|
||||
ADAFLAGS_common += -Wall
|
||||
-ADAFLAGS_common += -Werror
|
||||
ADAFLAGS_common += -pipe
|
||||
ADAFLAGS_common += -g
|
||||
ADAFLAGS_common += -nostdinc
|
||||
diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk
|
||||
index 0f5d1a0e11..45c2c5ad74 100644
|
||||
--- a/payloads/libpayload/Makefile.mk
|
||||
+++ b/payloads/libpayload/Makefile.mk
|
||||
@@ -80,7 +80,7 @@ CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer
|
||||
CFLAGS += -ffunction-sections -fdata-sections
|
||||
CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla
|
||||
CFLAGS += -Wwrite-strings -Wredundant-decls -Wimplicit-fallthrough
|
||||
-CFLAGS += -Wstrict-aliasing -Wshadow -Wno-address-of-packed-member -Werror
|
||||
+CFLAGS += -Wstrict-aliasing -Wshadow -Wno-address-of-packed-member
|
||||
|
||||
ifeq ($(CONFIG_LP_LTO),y)
|
||||
CFLAGS += -flto
|
||||
diff --git a/payloads/libpayload/Makefile.payload b/payloads/libpayload/Makefile.payload
|
||||
index 2eafd4bec3..c74704c58d 100644
|
||||
--- a/payloads/libpayload/Makefile.payload
|
||||
+++ b/payloads/libpayload/Makefile.payload
|
||||
@@ -84,7 +84,7 @@ endif
|
||||
|
||||
CFLAGS = $(CFLAGS_$(ARCH))
|
||||
CFLAGS += -Os -ffreestanding
|
||||
-CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror
|
||||
+CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla
|
||||
ifeq ($(CONFIG_LP_LTO),y)
|
||||
CFLAGS += -flto
|
||||
endif
|
||||
diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile
|
||||
index 1249e9a017..269511d7df 100644
|
||||
--- a/payloads/libpayload/sample/Makefile
|
||||
+++ b/payloads/libpayload/sample/Makefile
|
||||
@@ -44,7 +44,7 @@ AS := $(AS_$(ARCH-y))
|
||||
LIBPAYLOAD_DIR := ../install/libpayload
|
||||
XCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/bin/lpgcc
|
||||
XAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/bin/lpas
|
||||
-CFLAGS := -fno-builtin -Wall -Werror -Os
|
||||
+CFLAGS := -fno-builtin -Wall -Os
|
||||
TARGET := hello
|
||||
OBJS := $(TARGET).o
|
||||
|
||||
diff --git a/payloads/libpayload/sample/arch_mock/Makefile b/payloads/libpayload/sample/arch_mock/Makefile
|
||||
index a1e748111e..a146c2b3be 100644
|
||||
--- a/payloads/libpayload/sample/arch_mock/Makefile
|
||||
+++ b/payloads/libpayload/sample/arch_mock/Makefile
|
||||
@@ -12,7 +12,7 @@ CC := gcc
|
||||
AS := as
|
||||
OBJCOPY := objcopy
|
||||
LIBPAYLOAD_DIR := ../../install/libpayload
|
||||
-CFLAGS := -fno-builtin -Wall -Werror -Os \
|
||||
+CFLAGS := -fno-builtin -Wall -Os \
|
||||
-include $(LIBPAYLOAD_DIR)/include/kconfig.h \
|
||||
-include $(LIBPAYLOAD_DIR)/include/compiler.h \
|
||||
-I $(LIBPAYLOAD_DIR)/include \
|
||||
diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk
|
||||
index 6b6c78d835..b2e7433b65 100644
|
||||
--- a/payloads/libpayload/tests/Makefile.mk
|
||||
+++ b/payloads/libpayload/tests/Makefile.mk
|
||||
@@ -45,7 +45,7 @@ TEST_CFLAGS += -I$(cmockasrc)/include
|
||||
# Minimal subset of warnings and errors. Tests can be less strict than actual build.
|
||||
TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wvla
|
||||
TEST_CFLAGS += -Wwrite-strings -Wno-address-of-packed-member -Wimplicit-fallthrough
|
||||
-TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror
|
||||
+TEST_CFLAGS += -Wstrict-aliasing -Wshadow
|
||||
TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type
|
||||
|
||||
TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin
|
||||
diff --git a/payloads/linuxcheck/Makefile b/payloads/linuxcheck/Makefile
|
||||
index 838c90df0c..a9d016db36 100644
|
||||
--- a/payloads/linuxcheck/Makefile
|
||||
+++ b/payloads/linuxcheck/Makefile
|
||||
@@ -3,7 +3,7 @@ XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile
|
||||
# build libpayload and put .config file in $(CURDIR) instead of ../libpayload
|
||||
# to avoid pollute the libpayload source directory and possible conflicts
|
||||
LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config"
|
||||
-CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib
|
||||
+CFLAGS += -Wall -Wvla -Os -ffreestanding -nostdinc -nostdlib
|
||||
ifeq ($(CONFIG_ARCH_X86),y)
|
||||
TARGETARCH = i386
|
||||
endif
|
||||
diff --git a/src/lib/gnat/Makefile.mk b/src/lib/gnat/Makefile.mk
|
||||
index 150a715067..9d9591bc00 100644
|
||||
--- a/src/lib/gnat/Makefile.mk
|
||||
+++ b/src/lib/gnat/Makefile.mk
|
||||
@@ -12,7 +12,6 @@ ADAFLAGS_libgnat-$(1) := \
|
||||
-gnatpg \
|
||||
-I$$(src)/lib/gnat/ \
|
||||
$$(GCC_ADAFLAGS_$(1)) \
|
||||
- -Werror \
|
||||
-fno-pie \
|
||||
|
||||
libgnat-$(1)-y += a-unccon.ads
|
||||
diff --git a/tests/Makefile.common b/tests/Makefile.common
|
||||
index 085e4cffc4..831867cf5c 100644
|
||||
--- a/tests/Makefile.common
|
||||
+++ b/tests/Makefile.common
|
||||
@@ -46,7 +46,7 @@ TEST_INCLUDES += -I$(dir $(TEST_KCONFIG_AUTOHEADER))
|
||||
# -Wmissing-prototypes just make working with the test framework cumbersome.
|
||||
# Only put conservative warnings here that really detect code that's obviously
|
||||
# unintentional.
|
||||
-TEST_CFLAGS += -Wall -Werror -Wundef -Wstrict-prototypes -Wno-inline-asm
|
||||
+TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wno-inline-asm
|
||||
TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type
|
||||
TEST_CFLAGS += -Wno-array-compare -Wno-trigraphs
|
||||
TEST_CFLAGS += -Wno-unused-but-set-variables
|
||||
diff --git a/util/amdfwtool/Makefile.mk b/util/amdfwtool/Makefile.mk
|
||||
index 0b9cc1b644..271afce4a7 100644
|
||||
--- a/util/amdfwtool/Makefile.mk
|
||||
+++ b/util/amdfwtool/Makefile.mk
|
||||
@@ -6,7 +6,8 @@ amdfwtoolobj = amdfwtool.o data_parse.o signed_psp.o handle_file.o opts.o
|
||||
amdfwreadobj = amdfwread.o
|
||||
amdfwheader = amdfwtool.h
|
||||
|
||||
-WERROR ?= -Werror
|
||||
+# no werror for you
|
||||
+WERROR ?=
|
||||
AMDFWTOOLCFLAGS :=-O2 -Wall -Wextra -Wshadow $(WERROR)
|
||||
AMDFWTOOLCFLAGS += -I $(top)/src/commonlib/bsd/include
|
||||
AMDFWTOOLCFLAGS += -D_GNU_SOURCE # memmem() from string.h
|
||||
diff --git a/util/archive/Makefile b/util/archive/Makefile
|
||||
index 2de6a6294a..70820aeba2 100644
|
||||
--- a/util/archive/Makefile
|
||||
+++ b/util/archive/Makefile
|
||||
@@ -1,7 +1,8 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
PROGRAM = archive
|
||||
HOSTCC ?= gcc
|
||||
-WERROR=-Werror
|
||||
+# no werror for u
|
||||
+WERROR=
|
||||
CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR}
|
||||
|
||||
SRCS = $(PROGRAM).c
|
||||
diff --git a/util/bincfg/Makefile b/util/bincfg/Makefile
|
||||
index dbcbc7711c..debef6c597 100644
|
||||
--- a/util/bincfg/Makefile
|
||||
+++ b/util/bincfg/Makefile
|
||||
@@ -3,7 +3,8 @@ CC = gcc
|
||||
YACC = bison
|
||||
LEX = flex
|
||||
TARGET=bincfg
|
||||
-WERROR=-Werror
|
||||
+# no werror for u
|
||||
+WERROR=
|
||||
CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR}
|
||||
CFLAGS+=-Wno-unused-function
|
||||
LDFLAGS= -lfl
|
||||
diff --git a/util/bucts/Makefile b/util/bucts/Makefile
|
||||
index d32258d1ec..a81aa5e1ae 100644
|
||||
--- a/util/bucts/Makefile
|
||||
+++ b/util/bucts/Makefile
|
||||
@@ -3,7 +3,8 @@ CC:=gcc
|
||||
OBJ:=bucts.o
|
||||
TARGET=bucts
|
||||
VERSION:=$(shell git describe)
|
||||
-WERROR=-Werror
|
||||
+# no werror for u
|
||||
+WERROR=
|
||||
CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR}
|
||||
|
||||
ifeq ($(shell uname), FreeBSD)
|
||||
diff --git a/util/cbfstool/Makefile.mk b/util/cbfstool/Makefile.mk
|
||||
index d3f07f9777..e34f69c1f1 100644
|
||||
--- a/util/cbfstool/Makefile.mk
|
||||
+++ b/util/cbfstool/Makefile.mk
|
||||
@@ -140,7 +140,7 @@ cse_serger_obj += common.o
|
||||
cse_serger_obj += cse_helpers.o
|
||||
cse_serger_obj += $(foreach var, $(bpdt_formats_obj), $(var))
|
||||
|
||||
-TOOLCFLAGS ?= -Werror -Wall -Wextra -Wshadow
|
||||
+TOOLCFLAGS ?= -Wall -Wextra -Wshadow
|
||||
TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow
|
||||
TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings
|
||||
TOOLCFLAGS += -O2
|
||||
diff --git a/util/cbfstool/lz4/Makefile b/util/cbfstool/lz4/Makefile
|
||||
index d624e84703..be484c805f 100644
|
||||
--- a/util/cbfstool/lz4/Makefile
|
||||
+++ b/util/cbfstool/lz4/Makefile
|
||||
@@ -72,10 +72,10 @@ cmake:
|
||||
@cd cmake_unofficial; cmake CMakeLists.txt; $(MAKE)
|
||||
|
||||
gpptest: clean
|
||||
- $(MAKE) all CC=g++ CFLAGS="-O3 -I../lib -Wall -Wextra -Wundef -Wshadow -Wcast-align -Werror"
|
||||
+ $(MAKE) all CC=g++ CFLAGS="-O3 -I../lib -Wall -Wextra -Wundef -Wshadow -Wcast-align"
|
||||
|
||||
clangtest: clean
|
||||
- CFLAGS="-O3 -Werror -Wconversion -Wno-sign-conversion" $(MAKE) all CC=clang
|
||||
+ CFLAGS="-O3 -Wconversion -Wno-sign-conversion" $(MAKE) all CC=clang
|
||||
|
||||
sanitize: clean
|
||||
CFLAGS="-O3 -g -fsanitize=undefined" $(MAKE) test CC=clang FUZZER_TIME="-T1mn" NB_LOOPS=-i1
|
||||
@@ -84,8 +84,8 @@ staticAnalyze: clean
|
||||
CFLAGS=-g clang-tidy $(CLANG_TIDY_CHECKS) $(CLANG_TIDY_ARGS) $(SRCS)
|
||||
|
||||
armtest: clean
|
||||
- CFLAGS="-O3 -Werror" $(MAKE) -C $(LZ4DIR) all CC=arm-linux-gnueabi-gcc
|
||||
- CFLAGS="-O3 -Werror" $(MAKE) -C $(PRGDIR) bins CC=arm-linux-gnueabi-gcc
|
||||
+ CFLAGS="-O3" $(MAKE) -C $(LZ4DIR) all CC=arm-linux-gnueabi-gcc
|
||||
+ CFLAGS="-O3" $(MAKE) -C $(PRGDIR) bins CC=arm-linux-gnueabi-gcc
|
||||
|
||||
versionsTest: clean
|
||||
$(MAKE) -C versionsTest
|
||||
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
|
||||
index e265ea6693..3aaaeac794 100644
|
||||
--- a/util/cbmem/Makefile
|
||||
+++ b/util/cbmem/Makefile
|
||||
@@ -9,7 +9,8 @@ CC ?= $(CROSS_COMPILE)gcc
|
||||
INSTALL ?= /usr/bin/env install
|
||||
PREFIX ?= /usr/local
|
||||
CFLAGS ?= -O2
|
||||
-WERROR=-Werror
|
||||
+# no werror for you!
|
||||
+WERROR=
|
||||
CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wshadow $(WERROR)
|
||||
CPPFLAGS += -I . -I $(ROOT)/commonlib/include -I $(ROOT)/commonlib/bsd/include
|
||||
CPPFLAGS += -include $(ROOT)/commonlib/bsd/include/commonlib/bsd/compiler.h
|
||||
diff --git a/util/ectool/Makefile b/util/ectool/Makefile
|
||||
index a90773e5c6..5724ac6009 100644
|
||||
--- a/util/ectool/Makefile
|
||||
+++ b/util/ectool/Makefile
|
||||
@@ -1,7 +1,7 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
CC ?= gcc
|
||||
-WERROR=-Werror
|
||||
+WERROR=
|
||||
CFLAGS = -O2 -Wall -Wextra -Wshadow $(WERROR)
|
||||
PROGRAM = ectool
|
||||
INSTALL ?= /usr/bin/env install
|
||||
diff --git a/util/futility/Makefile.mk b/util/futility/Makefile.mk
|
||||
index a7bcee50d3..cb5363b93e 100644
|
||||
--- a/util/futility/Makefile.mk
|
||||
+++ b/util/futility/Makefile.mk
|
||||
@@ -10,7 +10,7 @@ $(VBOOT_FUTILITY): | check-openssl-presence
|
||||
unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \
|
||||
BUILD=$(VBOOT_HOST_BUILD) \
|
||||
CC="$(HOSTCC)" \
|
||||
- WERROR="-Werror -Wno-deprecated-declarations" \
|
||||
+ WERROR="-Wno-deprecated-declarations" \
|
||||
PKG_CONFIG="$(HOSTPKGCONFIG)" \
|
||||
V=$(V) \
|
||||
USE_FLASHROM=0 \
|
||||
diff --git a/util/ifdtool/Makefile.mk b/util/ifdtool/Makefile.mk
|
||||
index 2b97bf51c8..47953aedb1 100644
|
||||
--- a/util/ifdtool/Makefile.mk
|
||||
+++ b/util/ifdtool/Makefile.mk
|
||||
@@ -2,7 +2,7 @@
|
||||
|
||||
ifdtoolobj = ifdtool.o fmap.o kv_pair.o valstr.o
|
||||
|
||||
-IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror
|
||||
+IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes
|
||||
IFDTOOLCFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include
|
||||
IFDTOOLCFLAGS += -I$(top)/util/cbfstool/flashmap
|
||||
IFDTOOLCFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h
|
||||
diff --git a/util/intelvbttool/Makefile b/util/intelvbttool/Makefile
|
||||
index 5c770dec9e..8963263354 100644
|
||||
--- a/util/intelvbttool/Makefile
|
||||
+++ b/util/intelvbttool/Makefile
|
||||
@@ -6,7 +6,7 @@ CC ?= gcc
|
||||
INSTALL ?= /usr/bin/env install
|
||||
PREFIX ?= /usr/local
|
||||
CFLAGS ?= -O2 -g
|
||||
-CFLAGS += -Wall -Werror
|
||||
+CFLAGS += -Wall
|
||||
CFLAGS += -I../../src/commonlib/include -I ../../src/commonlib/bsd/include
|
||||
|
||||
all: $(PROGRAM)
|
||||
diff --git a/util/msrtool/configure b/util/msrtool/configure
|
||||
index 659cbcd66b..731e24f550 100755
|
||||
--- a/util/msrtool/configure
|
||||
+++ b/util/msrtool/configure
|
||||
@@ -133,7 +133,7 @@ CC=`findprog "compiler" "${CC}" clang gcc cc icc` || exit
|
||||
INSTALL=`findprog "install" "${INSTALL}" install ginstall` || exit
|
||||
|
||||
test -n "$DEBUG" && myCFLAGS="-O2 -g" || myCFLAGS="-Os"
|
||||
-CFLAGS="${CFLAGS} ${myCFLAGS} -Wall -Werror"
|
||||
+CFLAGS="${CFLAGS} ${myCFLAGS} -Wall"
|
||||
|
||||
cat > .config.c << EOF
|
||||
#include <pci/pci.h>
|
||||
diff --git a/util/pmh7tool/Makefile b/util/pmh7tool/Makefile
|
||||
index 0a2ebbe147..c04d7e9bf9 100644
|
||||
--- a/util/pmh7tool/Makefile
|
||||
+++ b/util/pmh7tool/Makefile
|
||||
@@ -1,7 +1,7 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
CC = gcc
|
||||
-CFLAGS = -O2 -Wall -Wextra -Werror
|
||||
+CFLAGS = -O2 -Wall -Wextra
|
||||
PROGRAM = pmh7tool
|
||||
INSTALL = /usr/bin/env install
|
||||
PREFIX = /usr/local
|
||||
diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile
|
||||
index 39839d9aa6..06aa7b6571 100644
|
||||
--- a/util/superiotool/Makefile
|
||||
+++ b/util/superiotool/Makefile
|
||||
@@ -12,7 +12,7 @@ PREFIX ?= /usr/local
|
||||
VERSION := -D'SUPERIOTOOL_VERSION="$(shell git describe 2>/dev/null)"'
|
||||
|
||||
CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \
|
||||
- -Werror-implicit-function-declaration -std=c11 -pedantic $(VERSION) \
|
||||
+ -std=c11 -pedantic $(VERSION) \
|
||||
-Wno-variadic-macros -I $(TOP)/src/commonlib/bsd/include
|
||||
LDFLAGS += -lz
|
||||
|
||||
@@ -24,8 +24,8 @@ ifeq ($(OS_ARCH), Darwin)
|
||||
LIBS = -framework IOKit -framework DirectHW -lpci -lz
|
||||
endif
|
||||
ifeq ($(OS_ARCH), FreeBSD)
|
||||
-CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \
|
||||
- -Werror-implicit-function-declaration -std=c11 $(VERSION) \
|
||||
+CFLAGS = -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \
|
||||
+ -std=c11 $(VERSION) \
|
||||
-I/usr/local/include
|
||||
LDFLAGS += -L/usr/local/lib
|
||||
LIBS = -lz
|
||||
diff --git a/util/uio_usbdebug/Makefile b/util/uio_usbdebug/Makefile
|
||||
index af1cc8e1ec..2ceb28cd53 100644
|
||||
--- a/util/uio_usbdebug/Makefile
|
||||
+++ b/util/uio_usbdebug/Makefile
|
||||
@@ -30,7 +30,7 @@ KCONFIG_H := ../../src/include/kconfig.h
|
||||
|
||||
CFLAGS += \
|
||||
-m32 -g \
|
||||
- -Wall -Wextra -Werror \
|
||||
+ -Wall -Wextra \
|
||||
-Wno-unused-parameter -Wno-error=sign-compare
|
||||
CPPFLAGS += \
|
||||
-Iinclude/ \
|
||||
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
|
||||
index f88da69306..ef43e28683 100755
|
||||
--- a/util/xcompile/xcompile
|
||||
+++ b/util/xcompile/xcompile
|
||||
@@ -124,7 +124,7 @@ testcc() {
|
||||
local tmp_o="$TMPFILE.o"
|
||||
rm -f "$tmp_c" "$tmp_o"
|
||||
echo "void _start(void) {}" >"$tmp_c"
|
||||
- "$cc" -nostdlib -Werror $cflags -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1
|
||||
+ "$cc" -nostdlib $cflags -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
testld() {
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
rev="62c8197dd25376cb7b18d272af167cb176d28bcf"
|
||||
romtype="normal"
|
||||
rev="54d0cc9a3cf31963ebf0ca85a87a7e464ef678a7" # 4.18_branch
|
||||
arch="x86_64"
|
||||
|
||||
@@ -1,849 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
CONFIG_OPTION_BACKEND_NONE=y
|
||||
# CONFIG_USE_OPTION_TABLE is not set
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3040 Micro"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_3040"
|
||||
CONFIG_VGA_BIOS_ID="8086,0406"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0xEEE000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3040 Micro"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_USE_PM_ACPI_TIMER=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_3040=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_DCACHE_RAM_BASE=0xfef00000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/3040micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3040micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
|
||||
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=16384
|
||||
CONFIG_ROM_SIZE=0x01000000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
|
||||
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
|
||||
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
|
||||
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x200000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x800
|
||||
CONFIG_ACPI_BERT_SIZE=0x0
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IFD_CHIPSET="sklkbl"
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_MAX_ROOT_PORTS=24
|
||||
CONFIG_PCR_BASE_ADDRESS=0xfd000000
|
||||
CONFIG_CPU_BCLK_MHZ=100
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
|
||||
CONFIG_CPU_XTAL_HZ=24000000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
|
||||
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
|
||||
# CONFIG_ENABLE_SATA_TEST_MODE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
|
||||
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
|
||||
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_FSP_PUBLISH_MBP_HOB=y
|
||||
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
|
||||
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
|
||||
CONFIG_SOC_INTEL_KABYLAKE=y
|
||||
CONFIG_SKYLAKE_SOC_PCH_H=y
|
||||
# CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU is not set
|
||||
# CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU is not set
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FSP_T_LOCATION=0xfffe0000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_SOC_INTEL_COMMON=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
|
||||
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
|
||||
# CONFIG_USE_COREBOOT_MP_INIT is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
|
||||
CONFIG_INTEL_CAR_NEM_ENHANCED=y
|
||||
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
|
||||
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
|
||||
CONFIG_HAVE_HYPERTHREADING=y
|
||||
# CONFIG_FSP_HYPERTHREADING is not set
|
||||
# CONFIG_INTEL_KEYLOCKER is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
|
||||
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
|
||||
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
|
||||
CONFIG_SOC_INTEL_CSE_RW_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
|
||||
CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
|
||||
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
|
||||
CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
|
||||
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
|
||||
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
|
||||
CONFIG_SA_ENABLE_DPR=y
|
||||
CONFIG_HAVE_CAPID_A_REGISTER=y
|
||||
CONFIG_HAVE_BDSM_BGSM_REGISTER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
|
||||
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
|
||||
|
||||
#
|
||||
# Intel SoC Common coreboot stages and non-IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BASECODE=y
|
||||
CONFIG_SOC_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
|
||||
CONFIG_PAVP=y
|
||||
# CONFIG_MMA is not set
|
||||
CONFIG_SOC_INTEL_COMMON_NHLT=y
|
||||
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_PARALLEL_MP_AP_WORK=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_UDK_BASE=y
|
||||
CONFIG_UDK_2017_BINDING=y
|
||||
CONFIG_UDK_2013_VERSION=2013
|
||||
CONFIG_UDK_2017_VERSION=2017
|
||||
CONFIG_UDK_202005_VERSION=202005
|
||||
CONFIG_UDK_202111_VERSION=202111
|
||||
CONFIG_UDK_202302_VERSION=202302
|
||||
CONFIG_UDK_202305_VERSION=202305
|
||||
CONFIG_UDK_VERSION=2017
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_FSP_GOP=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_RUN_FSP_GOP is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y
|
||||
# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set
|
||||
# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set
|
||||
# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR4=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
CONFIG_MRC_SETTINGS_PROTECT=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
# CONFIG_FSP_USE_REPO is not set
|
||||
# CONFIG_DISPLAY_HOBS is not set
|
||||
# CONFIG_DISPLAY_UPD_DATA is not set
|
||||
CONFIG_PLATFORM_USES_FSP2_0=y
|
||||
CONFIG_PLATFORM_USES_FSP2_X86_32=y
|
||||
CONFIG_HAVE_INTEL_FSP_REPO=y
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
CONFIG_FSP_S_CBFS="fsps.bin"
|
||||
CONFIG_FSP_M_CBFS="fspm.bin"
|
||||
# CONFIG_FSP_FULL_FD is not set
|
||||
CONFIG_FSP_T_RESERVED_SIZE=0x0
|
||||
CONFIG_FSP_M_XIP=y
|
||||
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
|
||||
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
|
||||
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
|
||||
CONFIG_FSP_VGA_MODE12_BPP=0x0
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
CONFIG_USE_PC_CMOS_ALTCENTURY=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_USB_ACPI=y
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_ACPI_LPIT=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_ACPI_S1_NOT_SUPPORTED=y
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
|
||||
# CONFIG_DISPLAY_FSP_HEADER is not set
|
||||
# CONFIG_VERIFY_HOBS is not set
|
||||
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
|
||||
CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
|
||||
# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
CONFIG_HAVE_DEBUG_GPIO=y
|
||||
# CONFIG_DEBUG_GPIO is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,842 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
CONFIG_OPTION_BACKEND_NONE=y
|
||||
# CONFIG_USE_OPTION_TABLE is not set
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3040 Micro"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_3040"
|
||||
CONFIG_VGA_BIOS_ID="8086,0406"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0xEEE000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3040 Micro"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_USE_PM_ACPI_TIMER=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_3040=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_DCACHE_RAM_BASE=0xfef00000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/3040micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3040micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
|
||||
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=16384
|
||||
CONFIG_ROM_SIZE=0x01000000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
|
||||
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
|
||||
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
|
||||
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x200000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x800
|
||||
CONFIG_ACPI_BERT_SIZE=0x0
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IFD_CHIPSET="sklkbl"
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_MAX_ROOT_PORTS=24
|
||||
CONFIG_PCR_BASE_ADDRESS=0xfd000000
|
||||
CONFIG_CPU_BCLK_MHZ=100
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
|
||||
CONFIG_CPU_XTAL_HZ=24000000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
|
||||
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
|
||||
# CONFIG_ENABLE_SATA_TEST_MODE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
|
||||
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
|
||||
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_FSP_PUBLISH_MBP_HOB=y
|
||||
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
|
||||
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
|
||||
CONFIG_SOC_INTEL_KABYLAKE=y
|
||||
CONFIG_SKYLAKE_SOC_PCH_H=y
|
||||
# CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU is not set
|
||||
# CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU is not set
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FSP_T_LOCATION=0xfffe0000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_SOC_INTEL_COMMON=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
|
||||
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
|
||||
# CONFIG_USE_COREBOOT_MP_INIT is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
|
||||
CONFIG_INTEL_CAR_NEM_ENHANCED=y
|
||||
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
|
||||
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
|
||||
CONFIG_HAVE_HYPERTHREADING=y
|
||||
# CONFIG_FSP_HYPERTHREADING is not set
|
||||
# CONFIG_INTEL_KEYLOCKER is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
|
||||
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
|
||||
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
|
||||
CONFIG_SOC_INTEL_CSE_RW_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
|
||||
CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
|
||||
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
|
||||
CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
|
||||
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
|
||||
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
|
||||
CONFIG_SA_ENABLE_DPR=y
|
||||
CONFIG_HAVE_CAPID_A_REGISTER=y
|
||||
CONFIG_HAVE_BDSM_BGSM_REGISTER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
|
||||
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
|
||||
|
||||
#
|
||||
# Intel SoC Common coreboot stages and non-IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BASECODE=y
|
||||
CONFIG_SOC_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
|
||||
CONFIG_PAVP=y
|
||||
# CONFIG_MMA is not set
|
||||
CONFIG_SOC_INTEL_COMMON_NHLT=y
|
||||
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_PARALLEL_MP_AP_WORK=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_UDK_BASE=y
|
||||
CONFIG_UDK_2017_BINDING=y
|
||||
CONFIG_UDK_2013_VERSION=2013
|
||||
CONFIG_UDK_2017_VERSION=2017
|
||||
CONFIG_UDK_202005_VERSION=202005
|
||||
CONFIG_UDK_202111_VERSION=202111
|
||||
CONFIG_UDK_202302_VERSION=202302
|
||||
CONFIG_UDK_202305_VERSION=202305
|
||||
CONFIG_UDK_VERSION=2017
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_FSP_GOP=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_RUN_FSP_GOP is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR4=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
CONFIG_MRC_SETTINGS_PROTECT=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
# CONFIG_FSP_USE_REPO is not set
|
||||
# CONFIG_DISPLAY_HOBS is not set
|
||||
# CONFIG_DISPLAY_UPD_DATA is not set
|
||||
CONFIG_PLATFORM_USES_FSP2_0=y
|
||||
CONFIG_PLATFORM_USES_FSP2_X86_32=y
|
||||
CONFIG_HAVE_INTEL_FSP_REPO=y
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
CONFIG_FSP_S_CBFS="fsps.bin"
|
||||
CONFIG_FSP_M_CBFS="fspm.bin"
|
||||
# CONFIG_FSP_FULL_FD is not set
|
||||
CONFIG_FSP_T_RESERVED_SIZE=0x0
|
||||
CONFIG_FSP_M_XIP=y
|
||||
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
|
||||
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
|
||||
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
|
||||
CONFIG_FSP_VGA_MODE12_BPP=0x0
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
CONFIG_USE_PC_CMOS_ALTCENTURY=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_USB_ACPI=y
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_ACPI_LPIT=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_ACPI_S1_NOT_SUPPORTED=y
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
|
||||
# CONFIG_DISPLAY_FSP_HEADER is not set
|
||||
# CONFIG_VERIFY_HOBS is not set
|
||||
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
|
||||
CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
|
||||
# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
CONFIG_HAVE_DEBUG_GPIO=y
|
||||
# CONFIG_DEBUG_GPIO is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,13 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci"
|
||||
grubtree="xhci_nvme"
|
||||
vcfg="3040micro"
|
||||
build_depend="seabios/default grub/xhci_nvme memtest86plus u-boot/amd64coreboot"
|
||||
IFD_platform="sklkbl"
|
||||
payload_uboot="amd64"
|
||||
@@ -1,851 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/sklkbl_desktops"
|
||||
CONFIG_VGA_BIOS_ID="8086,0406"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=512
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0xEEE000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=16
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="optiplex_3050"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
|
||||
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_USE_PM_ACPI_TIMER=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_3050=y
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_SKLKBL_DESKTOPS_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfef00000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
|
||||
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=16384
|
||||
CONFIG_ROM_SIZE=0x01000000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
|
||||
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
|
||||
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
|
||||
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x200000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x800
|
||||
CONFIG_ACPI_BERT_SIZE=0x0
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IFD_CHIPSET="sklkbl"
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_MAX_ROOT_PORTS=24
|
||||
CONFIG_PCR_BASE_ADDRESS=0xfd000000
|
||||
CONFIG_CPU_BCLK_MHZ=100
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
|
||||
CONFIG_CPU_XTAL_HZ=24000000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
|
||||
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
|
||||
# CONFIG_ENABLE_SATA_TEST_MODE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
|
||||
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
|
||||
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_FSP_PUBLISH_MBP_HOB=y
|
||||
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
|
||||
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
|
||||
CONFIG_SOC_INTEL_KABYLAKE=y
|
||||
CONFIG_SKYLAKE_SOC_PCH_H=y
|
||||
CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
|
||||
CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FSP_T_LOCATION=0xfffe0000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_SOC_INTEL_COMMON=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
|
||||
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
|
||||
# CONFIG_USE_COREBOOT_MP_INIT is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
|
||||
CONFIG_INTEL_CAR_NEM_ENHANCED=y
|
||||
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
|
||||
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
|
||||
CONFIG_HAVE_HYPERTHREADING=y
|
||||
# CONFIG_FSP_HYPERTHREADING is not set
|
||||
# CONFIG_INTEL_KEYLOCKER is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
|
||||
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
|
||||
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
|
||||
CONFIG_SOC_INTEL_CSE_RW_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
|
||||
CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
|
||||
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
|
||||
CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
|
||||
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
|
||||
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
|
||||
CONFIG_SA_ENABLE_DPR=y
|
||||
CONFIG_HAVE_CAPID_A_REGISTER=y
|
||||
CONFIG_HAVE_BDSM_BGSM_REGISTER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
|
||||
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
|
||||
|
||||
#
|
||||
# Intel SoC Common coreboot stages and non-IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BASECODE=y
|
||||
CONFIG_SOC_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
|
||||
CONFIG_PAVP=y
|
||||
# CONFIG_MMA is not set
|
||||
CONFIG_SOC_INTEL_COMMON_NHLT=y
|
||||
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_PARALLEL_MP_AP_WORK=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_UDK_BASE=y
|
||||
CONFIG_UDK_2017_BINDING=y
|
||||
CONFIG_UDK_2013_VERSION=2013
|
||||
CONFIG_UDK_2017_VERSION=2017
|
||||
CONFIG_UDK_202005_VERSION=202005
|
||||
CONFIG_UDK_202111_VERSION=202111
|
||||
CONFIG_UDK_202302_VERSION=202302
|
||||
CONFIG_UDK_202305_VERSION=202305
|
||||
CONFIG_UDK_VERSION=2017
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_FSP_GOP=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_RUN_FSP_GOP is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y
|
||||
# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set
|
||||
# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set
|
||||
# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR4=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
CONFIG_MRC_SETTINGS_PROTECT=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
# CONFIG_FSP_USE_REPO is not set
|
||||
# CONFIG_DISPLAY_HOBS is not set
|
||||
# CONFIG_DISPLAY_UPD_DATA is not set
|
||||
CONFIG_PLATFORM_USES_FSP2_0=y
|
||||
CONFIG_PLATFORM_USES_FSP2_X86_32=y
|
||||
CONFIG_HAVE_INTEL_FSP_REPO=y
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
CONFIG_FSP_S_CBFS="fsps.bin"
|
||||
CONFIG_FSP_M_CBFS="fspm.bin"
|
||||
# CONFIG_FSP_FULL_FD is not set
|
||||
CONFIG_FSP_T_RESERVED_SIZE=0x0
|
||||
CONFIG_FSP_M_XIP=y
|
||||
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
|
||||
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
|
||||
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
|
||||
CONFIG_FSP_VGA_MODE12_BPP=0x0
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
CONFIG_USE_PC_CMOS_ALTCENTURY=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_USB_ACPI=y
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_ACPI_LPIT=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_ACPI_S1_NOT_SUPPORTED=y
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
|
||||
# CONFIG_DISPLAY_FSP_HEADER is not set
|
||||
# CONFIG_VERIFY_HOBS is not set
|
||||
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
|
||||
CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
|
||||
# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
CONFIG_HAVE_DEBUG_GPIO=y
|
||||
# CONFIG_DEBUG_GPIO is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,844 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/sklkbl_desktops"
|
||||
CONFIG_VGA_BIOS_ID="8086,0406"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=512
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0xEEE000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=16
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="optiplex_3050"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
|
||||
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_USE_PM_ACPI_TIMER=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_3050=y
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_SKLKBL_DESKTOPS_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfef00000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
|
||||
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=16384
|
||||
CONFIG_ROM_SIZE=0x01000000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
|
||||
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
|
||||
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
|
||||
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x200000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x800
|
||||
CONFIG_ACPI_BERT_SIZE=0x0
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IFD_CHIPSET="sklkbl"
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_MAX_ROOT_PORTS=24
|
||||
CONFIG_PCR_BASE_ADDRESS=0xfd000000
|
||||
CONFIG_CPU_BCLK_MHZ=100
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
|
||||
CONFIG_CPU_XTAL_HZ=24000000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
|
||||
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
|
||||
# CONFIG_ENABLE_SATA_TEST_MODE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
|
||||
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
|
||||
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_FSP_PUBLISH_MBP_HOB=y
|
||||
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
|
||||
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
|
||||
CONFIG_SOC_INTEL_KABYLAKE=y
|
||||
CONFIG_SKYLAKE_SOC_PCH_H=y
|
||||
CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
|
||||
CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FSP_T_LOCATION=0xfffe0000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_SOC_INTEL_COMMON=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
|
||||
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
|
||||
# CONFIG_USE_COREBOOT_MP_INIT is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
|
||||
CONFIG_INTEL_CAR_NEM_ENHANCED=y
|
||||
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
|
||||
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
|
||||
CONFIG_HAVE_HYPERTHREADING=y
|
||||
# CONFIG_FSP_HYPERTHREADING is not set
|
||||
# CONFIG_INTEL_KEYLOCKER is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
|
||||
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
|
||||
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
|
||||
CONFIG_SOC_INTEL_CSE_RW_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
|
||||
CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
|
||||
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
|
||||
CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
|
||||
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
|
||||
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
|
||||
CONFIG_SA_ENABLE_DPR=y
|
||||
CONFIG_HAVE_CAPID_A_REGISTER=y
|
||||
CONFIG_HAVE_BDSM_BGSM_REGISTER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
|
||||
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
|
||||
|
||||
#
|
||||
# Intel SoC Common coreboot stages and non-IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BASECODE=y
|
||||
CONFIG_SOC_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
|
||||
CONFIG_PAVP=y
|
||||
# CONFIG_MMA is not set
|
||||
CONFIG_SOC_INTEL_COMMON_NHLT=y
|
||||
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_PARALLEL_MP_AP_WORK=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_UDK_BASE=y
|
||||
CONFIG_UDK_2017_BINDING=y
|
||||
CONFIG_UDK_2013_VERSION=2013
|
||||
CONFIG_UDK_2017_VERSION=2017
|
||||
CONFIG_UDK_202005_VERSION=202005
|
||||
CONFIG_UDK_202111_VERSION=202111
|
||||
CONFIG_UDK_202302_VERSION=202302
|
||||
CONFIG_UDK_202305_VERSION=202305
|
||||
CONFIG_UDK_VERSION=2017
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_FSP_GOP=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_RUN_FSP_GOP is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR4=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
CONFIG_MRC_SETTINGS_PROTECT=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
# CONFIG_FSP_USE_REPO is not set
|
||||
# CONFIG_DISPLAY_HOBS is not set
|
||||
# CONFIG_DISPLAY_UPD_DATA is not set
|
||||
CONFIG_PLATFORM_USES_FSP2_0=y
|
||||
CONFIG_PLATFORM_USES_FSP2_X86_32=y
|
||||
CONFIG_HAVE_INTEL_FSP_REPO=y
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
CONFIG_FSP_S_CBFS="fsps.bin"
|
||||
CONFIG_FSP_M_CBFS="fspm.bin"
|
||||
# CONFIG_FSP_FULL_FD is not set
|
||||
CONFIG_FSP_T_RESERVED_SIZE=0x0
|
||||
CONFIG_FSP_M_XIP=y
|
||||
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
|
||||
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
|
||||
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
|
||||
CONFIG_FSP_VGA_MODE12_BPP=0x0
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
CONFIG_USE_PC_CMOS_ALTCENTURY=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_USB_ACPI=y
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_ACPI_LPIT=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_ACPI_S1_NOT_SUPPORTED=y
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
|
||||
# CONFIG_DISPLAY_FSP_HEADER is not set
|
||||
# CONFIG_VERIFY_HOBS is not set
|
||||
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
|
||||
CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
|
||||
# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
CONFIG_HAVE_DEBUG_GPIO=y
|
||||
# CONFIG_DEBUG_GPIO is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,13 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci"
|
||||
grubtree="xhci_nvme"
|
||||
vcfg="3050micro"
|
||||
build_depend="seabios/default grub/xhci_nvme memtest86plus u-boot/amd64coreboot"
|
||||
IFD_platform="sklkbl"
|
||||
payload_uboot="amd64"
|
||||
@@ -1,833 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/sklkbl_desktops"
|
||||
CONFIG_VGA_BIOS_ID="8086,0406"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=512
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0xEEE000
|
||||
# CONFIG_CONSOLE_SERIAL is not set
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=16
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_VARIANT_DIR="optiplex_3050"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
|
||||
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_USE_PM_ACPI_TIMER=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_3050=y
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_SKLKBL_DESKTOPS_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfef00000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
|
||||
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=16384
|
||||
CONFIG_ROM_SIZE=0x01000000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
|
||||
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
|
||||
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
|
||||
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x200000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x800
|
||||
CONFIG_ACPI_BERT_SIZE=0x0
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IFD_CHIPSET="sklkbl"
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_MAX_ROOT_PORTS=24
|
||||
CONFIG_PCR_BASE_ADDRESS=0xfd000000
|
||||
CONFIG_CPU_BCLK_MHZ=100
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
|
||||
CONFIG_CPU_XTAL_HZ=24000000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
|
||||
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
|
||||
# CONFIG_ENABLE_SATA_TEST_MODE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
|
||||
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
|
||||
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_FSP_PUBLISH_MBP_HOB=y
|
||||
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
|
||||
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
|
||||
CONFIG_SOC_INTEL_KABYLAKE=y
|
||||
CONFIG_SKYLAKE_SOC_PCH_H=y
|
||||
CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
|
||||
CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FSP_T_LOCATION=0xfffe0000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_SOC_INTEL_COMMON=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
|
||||
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
|
||||
# CONFIG_USE_COREBOOT_MP_INIT is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
|
||||
CONFIG_INTEL_CAR_NEM_ENHANCED=y
|
||||
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
|
||||
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
|
||||
CONFIG_HAVE_HYPERTHREADING=y
|
||||
# CONFIG_FSP_HYPERTHREADING is not set
|
||||
# CONFIG_INTEL_KEYLOCKER is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
|
||||
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
|
||||
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
|
||||
CONFIG_SOC_INTEL_CSE_RW_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
|
||||
CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
|
||||
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
|
||||
CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
|
||||
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
|
||||
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
|
||||
CONFIG_SA_ENABLE_DPR=y
|
||||
CONFIG_HAVE_CAPID_A_REGISTER=y
|
||||
CONFIG_HAVE_BDSM_BGSM_REGISTER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
|
||||
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
|
||||
|
||||
#
|
||||
# Intel SoC Common coreboot stages and non-IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BASECODE=y
|
||||
CONFIG_SOC_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
|
||||
CONFIG_PAVP=y
|
||||
# CONFIG_MMA is not set
|
||||
CONFIG_SOC_INTEL_COMMON_NHLT=y
|
||||
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_PARALLEL_MP_AP_WORK=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_UDK_BASE=y
|
||||
CONFIG_UDK_2017_BINDING=y
|
||||
CONFIG_UDK_2013_VERSION=2013
|
||||
CONFIG_UDK_2017_VERSION=2017
|
||||
CONFIG_UDK_202005_VERSION=202005
|
||||
CONFIG_UDK_202111_VERSION=202111
|
||||
CONFIG_UDK_202302_VERSION=202302
|
||||
CONFIG_UDK_202305_VERSION=202305
|
||||
CONFIG_UDK_VERSION=2017
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_FSP_GOP=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_RUN_FSP_GOP is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y
|
||||
# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set
|
||||
# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set
|
||||
# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR4=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
CONFIG_MRC_SETTINGS_PROTECT=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
# CONFIG_FSP_USE_REPO is not set
|
||||
# CONFIG_DISPLAY_HOBS is not set
|
||||
# CONFIG_DISPLAY_UPD_DATA is not set
|
||||
CONFIG_PLATFORM_USES_FSP2_0=y
|
||||
CONFIG_PLATFORM_USES_FSP2_X86_32=y
|
||||
CONFIG_HAVE_INTEL_FSP_REPO=y
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
CONFIG_FSP_S_CBFS="fsps.bin"
|
||||
CONFIG_FSP_M_CBFS="fspm.bin"
|
||||
# CONFIG_FSP_FULL_FD is not set
|
||||
CONFIG_FSP_T_RESERVED_SIZE=0x0
|
||||
CONFIG_FSP_M_XIP=y
|
||||
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
|
||||
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
|
||||
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
|
||||
CONFIG_FSP_VGA_MODE12_BPP=0x0
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
CONFIG_USE_PC_CMOS_ALTCENTURY=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_USB_ACPI=y
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_NONE is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_WHOLE_RO=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_WHOLE_NO_ACCESS is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_ACPI_LPIT=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_ACPI_S1_NOT_SUPPORTED=y
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
|
||||
# CONFIG_DISPLAY_FSP_HEADER is not set
|
||||
# CONFIG_VERIFY_HOBS is not set
|
||||
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
|
||||
CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
|
||||
# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
CONFIG_HAVE_DEBUG_GPIO=y
|
||||
# CONFIG_DEBUG_GPIO is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,826 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/sklkbl_desktops"
|
||||
CONFIG_VGA_BIOS_ID="8086,0406"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=512
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0xEEE000
|
||||
# CONFIG_CONSOLE_SERIAL is not set
|
||||
CONFIG_MAX_CPUS=16
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_VARIANT_DIR="optiplex_3050"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(CONFIG_VARIANT_DIR)/data.vbt"
|
||||
# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_USE_PM_ACPI_TIMER=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_3050=y
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_SKLKBL_DESKTOPS_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfef00000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
|
||||
CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=16384
|
||||
CONFIG_ROM_SIZE=0x01000000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
|
||||
CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
|
||||
CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
|
||||
CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x200000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x800
|
||||
CONFIG_ACPI_BERT_SIZE=0x0
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IFD_CHIPSET="sklkbl"
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_MAX_ROOT_PORTS=24
|
||||
CONFIG_PCR_BASE_ADDRESS=0xfd000000
|
||||
CONFIG_CPU_BCLK_MHZ=100
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
|
||||
CONFIG_CPU_XTAL_HZ=24000000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
|
||||
CONFIG_SOC_INTEL_I2C_DEV_MAX=6
|
||||
# CONFIG_ENABLE_SATA_TEST_MODE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
|
||||
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
|
||||
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_FSP_PUBLISH_MBP_HOB=y
|
||||
CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
|
||||
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
|
||||
CONFIG_SOC_INTEL_KABYLAKE=y
|
||||
CONFIG_SKYLAKE_SOC_PCH_H=y
|
||||
CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
|
||||
CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FSP_T_LOCATION=0xfffe0000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_SOC_INTEL_COMMON=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
|
||||
CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
|
||||
# CONFIG_USE_COREBOOT_MP_INIT is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
|
||||
CONFIG_INTEL_CAR_NEM_ENHANCED=y
|
||||
# CONFIG_USE_INTEL_FSP_MP_INIT is not set
|
||||
CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
|
||||
CONFIG_HAVE_HYPERTHREADING=y
|
||||
# CONFIG_FSP_HYPERTHREADING is not set
|
||||
# CONFIG_INTEL_KEYLOCKER is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
|
||||
CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
|
||||
CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
|
||||
CONFIG_SOC_INTEL_CSE_RW_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_RW_VERSION=""
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
|
||||
CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
|
||||
CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
|
||||
CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
|
||||
CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
|
||||
CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
|
||||
# CONFIG_SOC_INTEL_DISABLE_IGD is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
|
||||
CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
|
||||
# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
|
||||
CONFIG_SA_ENABLE_DPR=y
|
||||
CONFIG_HAVE_CAPID_A_REGISTER=y
|
||||
CONFIG_HAVE_BDSM_BGSM_REGISTER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
|
||||
CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
|
||||
CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
|
||||
CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
|
||||
|
||||
#
|
||||
# Intel SoC Common coreboot stages and non-IP blocks
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_BASECODE=y
|
||||
CONFIG_SOC_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
|
||||
CONFIG_PAVP=y
|
||||
# CONFIG_MMA is not set
|
||||
CONFIG_SOC_INTEL_COMMON_NHLT=y
|
||||
# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_PARALLEL_MP_AP_WORK=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_UDK_BASE=y
|
||||
CONFIG_UDK_2017_BINDING=y
|
||||
CONFIG_UDK_2013_VERSION=2013
|
||||
CONFIG_UDK_2017_VERSION=2017
|
||||
CONFIG_UDK_202005_VERSION=202005
|
||||
CONFIG_UDK_202111_VERSION=202111
|
||||
CONFIG_UDK_202302_VERSION=202302
|
||||
CONFIG_UDK_202305_VERSION=202305
|
||||
CONFIG_UDK_VERSION=2017
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_FSP_GOP=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_RUN_FSP_GOP is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR4=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
CONFIG_MRC_SETTINGS_PROTECT=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
# CONFIG_FSP_USE_REPO is not set
|
||||
# CONFIG_DISPLAY_HOBS is not set
|
||||
# CONFIG_DISPLAY_UPD_DATA is not set
|
||||
CONFIG_PLATFORM_USES_FSP2_0=y
|
||||
CONFIG_PLATFORM_USES_FSP2_X86_32=y
|
||||
CONFIG_HAVE_INTEL_FSP_REPO=y
|
||||
CONFIG_ADD_FSP_BINARIES=y
|
||||
CONFIG_FSP_S_CBFS="fsps.bin"
|
||||
CONFIG_FSP_M_CBFS="fspm.bin"
|
||||
# CONFIG_FSP_FULL_FD is not set
|
||||
CONFIG_FSP_T_RESERVED_SIZE=0x0
|
||||
CONFIG_FSP_M_XIP=y
|
||||
CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
|
||||
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
|
||||
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
|
||||
CONFIG_FSP_VGA_MODE12_BPP=0x0
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
CONFIG_USE_PC_CMOS_ALTCENTURY=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_USB_ACPI=y
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_NONE is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_WHOLE_RO=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_WHOLE_NO_ACCESS is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_ACPI_LPIT=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_ACPI_S1_NOT_SUPPORTED=y
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
|
||||
# CONFIG_DISPLAY_FSP_HEADER is not set
|
||||
# CONFIG_VERIFY_HOBS is not set
|
||||
# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
|
||||
CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
|
||||
# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
CONFIG_HAVE_DEBUG_GPIO=y
|
||||
# CONFIG_DEBUG_GPIO is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,14 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci"
|
||||
grubtree="xhci_nvme"
|
||||
vcfg="3050micro"
|
||||
build_depend="seabios/default grub/xhci_nvme memtest86plus u-boot/amd64coreboot"
|
||||
IFD_platform="sklkbl"
|
||||
payload_uboot="amd64"
|
||||
payload_grubsea="y"
|
||||
@@ -1,717 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 9010"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/snb_ivb_workstations"
|
||||
CONFIG_VGA_BIOS_ID="8086,0106"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0xBE5000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="optiplex_9010_sff"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="variants/baseboard/devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_DRAM_RESET_GATE_GPIO=60
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Precision T1650"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_TPM_PIRQ=0x0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9010=y
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_SNB_IVB_WORKSTATIONS=y
|
||||
CONFIG_INCLUDE_SMSC_SCH5545_EC_FW=y
|
||||
CONFIG_SMSC_SCH5545_EC_FW_FILE="../../../vendorfiles/t1650/sch5545ec.bin"
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefe0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x20000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/t1650/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t1650/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/t1650/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xf0000000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_206AX=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
|
||||
# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
|
||||
CONFIG_RAMINIT_ENABLE_ECC=y
|
||||
CONFIG_IGD_DEFAULT_UMA_SIZE_32MB=y
|
||||
# CONFIG_IGD_DEFAULT_UMA_SIZE_64MB is not set
|
||||
# CONFIG_IGD_DEFAULT_UMA_SIZE_96MB is not set
|
||||
# CONFIG_IGD_DEFAULT_UMA_SIZE_128MB is not set
|
||||
CONFIG_IGD_DEFAULT_UMA_INDEX=0
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_C216=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH5545=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_TPM_INIT_RAMSTAGE=y
|
||||
# CONFIG_TPM_PPI is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Ironlake"
|
||||
CONFIG_GFX_GMA_PCH="Cougar_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_MEMORY_MAPPED_TPM=y
|
||||
CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_TPM1=y
|
||||
# CONFIG_TPM2 is not set
|
||||
CONFIG_TPM=y
|
||||
CONFIG_MAINBOARD_HAS_TPM1=y
|
||||
# CONFIG_TPM_DEACTIVATE is not set
|
||||
# CONFIG_DEBUG_TPM is not set
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_INTEL_TXT is not set
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,12 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci"
|
||||
grubtree="nvme"
|
||||
vcfg="t1650"
|
||||
build_depend="seabios/default grub/nvme memtest86plus u-boot/amd64coreboot"
|
||||
payload_uboot="amd64"
|
||||
@@ -1,687 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x7FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_mt"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=8192
|
||||
CONFIG_ROM_SIZE=0x00800000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,683 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x7FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_mt"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=8192
|
||||
CONFIG_ROM_SIZE=0x00800000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,11 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci ata"
|
||||
grubtree="nvme"
|
||||
build_depend="seabios/default grub/nvme memtest86plus u-boot/amd64coreboot"
|
||||
payload_uboot="amd64"
|
||||
@@ -1,687 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x5FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_mt"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8_truncate"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=6144
|
||||
CONFIG_ROM_SIZE=0x00600000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,683 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x5FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_mt"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8_truncate"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=6144
|
||||
CONFIG_ROM_SIZE=0x00600000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,11 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci ata"
|
||||
grubtree="nvme"
|
||||
build_depend="seabios/default grub/nvme memtest86plus u-boot/amd64coreboot"
|
||||
payload_uboot="amd64"
|
||||
@@ -1,687 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 USFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x7FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_usff"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=8192
|
||||
CONFIG_ROM_SIZE=0x00800000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,683 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 USFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x7FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_usff"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=8192
|
||||
CONFIG_ROM_SIZE=0x00800000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,11 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci ata"
|
||||
grubtree="nvme"
|
||||
build_depend="seabios/default grub/nvme memtest86plus u-boot/amd64coreboot"
|
||||
payload_uboot="amd64"
|
||||
@@ -1,687 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 USFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x5FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_usff"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8_truncate"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=6144
|
||||
CONFIG_ROM_SIZE=0x00600000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,683 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 USFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_780"
|
||||
CONFIG_VGA_BIOS_ID="8086,2e22"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x5FD000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_VARIANT_DIR="780_usff"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_INTEL_GMA_DPLL_REF_FREQ=96000000
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfeff8000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8_truncate"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=6144
|
||||
CONFIG_ROM_SIZE=0x00600000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F3X=y
|
||||
CONFIG_CPU_INTEL_MODEL_F4X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_LGA775=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
CONFIG_MRC_STASH_TO_CBMEM=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,11 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci ata"
|
||||
grubtree="nvme"
|
||||
build_depend="seabios/default grub/nvme memtest86plus u-boot/amd64coreboot"
|
||||
payload_uboot="amd64"
|
||||
@@ -1,705 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
CONFIG_UTIL_GENPARSER=y
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_TPM_PIRQ=0x0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xf0000000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_TPM_INIT_RAMSTAGE=y
|
||||
# CONFIG_TPM_PPI is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
CONFIG_HAS_DIGITAL_IO_POWER_DOMAIN=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_MEMORY_MAPPED_TPM=y
|
||||
CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_TPM1=y
|
||||
# CONFIG_TPM2 is not set
|
||||
CONFIG_TPM=y
|
||||
CONFIG_MAINBOARD_HAS_TPM1=y
|
||||
# CONFIG_TPM_DEACTIVATE is not set
|
||||
# CONFIG_DEBUG_TPM is not set
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_INTEL_TXT is not set
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,702 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
CONFIG_UTIL_GENPARSER=y
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_TPM_PIRQ=0x0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xf0000000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_TPM_INIT_RAMSTAGE=y
|
||||
# CONFIG_TPM_PPI is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
CONFIG_HAS_DIGITAL_IO_POWER_DOMAIN=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_MEMORY_MAPPED_TPM=y
|
||||
CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_TPM1=y
|
||||
# CONFIG_TPM2 is not set
|
||||
CONFIG_TPM=y
|
||||
CONFIG_MAINBOARD_HAS_TPM1=y
|
||||
# CONFIG_TPM_DEACTIVATE is not set
|
||||
# CONFIG_DEBUG_TPM is not set
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_INTEL_TXT is not set
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,12 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci"
|
||||
grubtree="xhci_nvme"
|
||||
vcfg="haswell"
|
||||
build_depend="seabios/default grub/xhci_nvme memtest86plus u-boot/amd64coreboot"
|
||||
payload_uboot="amd64"
|
||||
@@ -1,705 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_TPM_PIRQ=0x0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xf0000000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_TPM_INIT_RAMSTAGE=y
|
||||
# CONFIG_TPM_PPI is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
CONFIG_HAS_DIGITAL_IO_POWER_DOMAIN=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_MEMORY_MAPPED_TPM=y
|
||||
CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_TPM1=y
|
||||
# CONFIG_TPM2 is not set
|
||||
CONFIG_TPM=y
|
||||
CONFIG_MAINBOARD_HAS_TPM1=y
|
||||
# CONFIG_TPM_DEACTIVATE is not set
|
||||
# CONFIG_DEBUG_TPM is not set
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_INTEL_TXT is not set
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,702 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_TPM_PIRQ=0x0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xf0000000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_TPM_INIT_RAMSTAGE=y
|
||||
# CONFIG_TPM_PPI is not set
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
CONFIG_HAS_DIGITAL_IO_POWER_DOMAIN=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_MEMORY_MAPPED_TPM=y
|
||||
CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_TPM1=y
|
||||
# CONFIG_TPM2 is not set
|
||||
CONFIG_TPM=y
|
||||
CONFIG_MAINBOARD_HAS_TPM1=y
|
||||
# CONFIG_TPM_DEACTIVATE is not set
|
||||
# CONFIG_DEBUG_TPM is not set
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_INTEL_TXT is not set
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,12 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="nvme ahci"
|
||||
grubtree="xhci_nvme"
|
||||
vcfg="haswell"
|
||||
build_depend="seabios/default grub/xhci_nvme memtest86plus u-boot/amd64coreboot"
|
||||
payload_uboot="amd64"
|
||||
@@ -1,664 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="Latitude E4300"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/gm45_latitude"
|
||||
CONFIG_VGA_BIOS_ID="8086,2a42"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x3FD000
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_VARIANT_DIR="e4300"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_USBDEBUG_HCD_INDEX=1
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E4300"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_BOARD_DELL_E4300=y
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_GM45_LATITUDE_COMMON=y
|
||||
CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x10000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=4096
|
||||
CONFIG_ROM_SIZE=0x00400000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
CONFIG_SYSTEM_TYPE_LAPTOP=y
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x61254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_P=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_EC_DELL_MEC5035=y
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,660 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="Latitude E4300"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/gm45_latitude"
|
||||
CONFIG_VGA_BIOS_ID="8086,2a42"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x3FD000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_VARIANT_DIR="e4300"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_USBDEBUG_HCD_INDEX=1
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E4300"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_BOARD_DELL_E4300=y
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_GM45_LATITUDE_COMMON=y
|
||||
CONFIG_INTEL_GMA_DPLL_REF_FREQ=100000000
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x10000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/ich9m/4_ifd"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/ich9m/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=4096
|
||||
CONFIG_ROM_SIZE=0x00400000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
CONFIG_SYSTEM_TYPE_LAPTOP=y
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x61254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_6FX=y
|
||||
CONFIG_CPU_INTEL_MODEL_1067X=y
|
||||
CONFIG_CPU_INTEL_SOCKET_P=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_EC_DELL_MEC5035=y
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
# CONFIG_HAVE_ME_BIN is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
CONFIG_DRAM_SUPPORT_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="G45"
|
||||
CONFIG_GFX_GMA_PCH="No_PCH"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -1,9 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_grub="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="ahci"
|
||||
payload_uboot="amd64"
|
||||
@@ -1,684 +0,0 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_LTO is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOOSTAR is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ARM is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_CWWK is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_ERYING is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_FRAMEWORK is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HARDKERNEL is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LATTEPANDA is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MITAC_COMPUTING is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_NOVACUSTOM is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_TOPTON is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
# CONFIG_VENDOR_VIA is not set
|
||||
CONFIG_MAINBOARD_PART_NUMBER="Latitude E5420"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/snb_ivb_latitude"
|
||||
CONFIG_VGA_BIOS_ID="8086,0116"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x5ea000
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=1600
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=2560
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_VARIANT_DIR="e5420"
|
||||
CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_DRAM_RESET_GATE_GPIO=60
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
CONFIG_USBDEBUG_HCD_INDEX=2
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Latitude E5420"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
CONFIG_BOARD_DELL_LATITUDE_E5420=y
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
# CONFIG_BOARD_DELL_XPS_8300 is not set
|
||||
CONFIG_BOARD_DELL_SNB_IVB_LATITUDE_COMMON=y
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefe0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x20000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell_sandybridge/6_ifd_nogbe"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/dell_sandybridge/me.bin"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=8
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="LVDS"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=6144
|
||||
CONFIG_ROM_SIZE=0x00600000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
CONFIG_SYSTEM_TYPE_LAPTOP=y
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
# CONFIG_USE_X86_64_SUPPORT is not set
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=4
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xf0000000
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_206AX=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
|
||||
# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
|
||||
CONFIG_RAMINIT_ENABLE_ECC=y
|
||||
CONFIG_IGD_DEFAULT_UMA_SIZE_32MB=y
|
||||
# CONFIG_IGD_DEFAULT_UMA_SIZE_64MB is not set
|
||||
# CONFIG_IGD_DEFAULT_UMA_SIZE_96MB is not set
|
||||
# CONFIG_IGD_DEFAULT_UMA_SIZE_128MB is not set
|
||||
CONFIG_IGD_DEFAULT_UMA_INDEX=0
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_EC_ACPI=y
|
||||
CONFIG_EC_DELL_MEC5035=y
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x800
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_LVDS=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Ironlake"
|
||||
CONFIG_GFX_GMA_PCH="Cougar_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
CONFIG_DRIVERS_MTK_WIFI=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
|
||||
#
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user