mirror of
https://codeberg.org/libreboot/lbmk.git
synced 2026-09-20 05:30:25 +02:00
Compare commits
2 Commits
| Author | SHA1 | Date | |
|---|---|---|---|
 Leah Rowe
|
5931a5d99a | ||
|
Leah Rowe
|
a43d2e60e8 |
+2
-17
@@ -1,9 +1,8 @@
|
||||
*~
|
||||
*.o
|
||||
/cache/
|
||||
/lbmk.err.log
|
||||
/repo/
|
||||
/docs/
|
||||
/cbutils/
|
||||
/pciroms/
|
||||
/util/dell-flash-unlock/dell_flash_unlock
|
||||
/TODO
|
||||
@@ -24,23 +23,9 @@
|
||||
/push
|
||||
/version
|
||||
/versiondate
|
||||
/.version
|
||||
/.versiondate
|
||||
/vendorfiles/
|
||||
*me.bin
|
||||
*sch5545ec.bin
|
||||
/mrc/
|
||||
/util/nvmutil/nvm
|
||||
/src/
|
||||
/CHANGELOG
|
||||
/todo.txt
|
||||
/lock
|
||||
/hash/
|
||||
/dump/
|
||||
/qrun*.sh
|
||||
*.tar.*
|
||||
/m
|
||||
/f
|
||||
/r
|
||||
/e
|
||||
/xbmkpath/
|
||||
/xbmkwd/
|
||||
|
||||
@@ -1,9 +1,3 @@
|
||||
NOTE: This applies to lwmk.git, a fork of LibreBook MaKe (lbmk).
|
||||
The Libreboot build system was used as a base, to produce the
|
||||
new LibreWolf build system. This file was just "COPYING" in the
|
||||
original lbmk, as that build system was largely provided under
|
||||
the following, terrible license:
|
||||
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
@@ -1,322 +1,123 @@
|
||||
<div align="center">
|
||||
|
||||
|
||||
|
||||
**THIS WILL BE REMOVED AT A LATER DATE.**
|
||||
|
||||
It's a proof of concept showing early modifications of lbmk, turning it into
|
||||
lwmk - LibreWolf MaKe, for building librewolf releases. I'm doing this for
|
||||
fun, to replace LibreWolf's source.git and bsys6.git build systems. Most
|
||||
features not added yet, but lbmk's "mkhelper" feature can (and will) be used
|
||||
to implement custom logic e.g. interacting with the mach build system in
|
||||
firefox. This will be a unified package manager for building *many* firefox
|
||||
derivatives, starting with LibreWolf, with the aim that all of the mozilla
|
||||
forks later use it, and perhaps work more closely with each other. I will
|
||||
publish this on a separate website when it's ready. **You are looking at
|
||||
an old version of it. I'm much further ahead locally. I will release it
|
||||
when it's finished!"
|
||||
|
||||
# LibreWolf
|
||||
|
||||
This repository contains all the patches and theming that make up LibreWolf,
|
||||
as well as the LibreWolf preferences (in [settings/](./settings)) and the
|
||||
scripts and Makefile to build LibreWolf.
|
||||
|
||||
This is a re-design of the LibreWolf build system, called LibreWolf MaKe, or
|
||||
just lwmk for short. It is a fork of the LibreBoot MaKe (lbmk) build system,
|
||||
which Libreboot uses to build coreboot images. It was decided that this design
|
||||
is beneficial for LibreWolf, as it offers advanced features by comparison, such
|
||||
as:
|
||||
|
||||
* Automatic caching of sources when downloading (Git repositories are used)
|
||||
* Redundant repository links are possible, for reliability in the future
|
||||
* Ability to declare custom git submodules, regardless of whether a project
|
||||
uses them; actual git submodules are unused. The lwmk design allows
|
||||
systematic patching and revision resets on submodules.
|
||||
* Ability to download files as submodules as well, hash-checking everything.
|
||||
Both git repositories and files are checked relentlessly, even when using
|
||||
local cache, to ensure integrity and general reproducibility.
|
||||
* Multi-tree design: projects like firefox can be build single- or multi-tree.
|
||||
In lwmk nomenclature, this means that a given project can have multiple
|
||||
targets, or just build one target. Multi-tree is preferred, where feasible;
|
||||
in lwmk, you can specify multiple revisions of Firefox, and multiple targets
|
||||
off of each tree name on the given revision. An application for this might
|
||||
be providing LibreWolf along with variants like LibreWolf-Hellfire, or
|
||||
more opiniated forks of LibreWolf that mostly just change a few configs.
|
||||
* Completely generalised design. The `mk` script and `include/` directory do
|
||||
not generally contain project-specific build logic. Each project can use
|
||||
mkhelpers to specify custom steps e.g. pre-configure, post-build, and so on,
|
||||
much like on a BSD ports system. This design is reminiscent of a Linux distro,
|
||||
because indeed it was first implemented for Libreboot which is a coreboot
|
||||
distro; this design generalises the downloading, patching and building
|
||||
of any source tree. It is highly flexible and configurable.
|
||||
* Ease of use. Despite high configurability, the overarching philosophy is
|
||||
like that for OpenBSD: Knobs are for nobs. We want everything to be as simple
|
||||
as possible for the user, with sane defaults for everything. The design
|
||||
of the entire build system reflects this philosophy.
|
||||
|
||||
The lwmk build system can generate binaries on the spot, and it does so
|
||||
using out-of-tree building. It can also generate clean source tarballs of
|
||||
sources e.g. Firefox sources.
|
||||
|
||||
The multi-tree nature of LibreWolf MaKe mean that you can support any number
|
||||
of actual Firefox derivatives. This build system is designed for use with
|
||||
the LibreWolf project, but it is intended that this design be used on every
|
||||
other Firefox fork; perhaps the projects can even work with each other, or
|
||||
there can be another project that uses this design and generalises all of
|
||||
the Mozilla forks. This might be useful for Linux distros, which can then
|
||||
just do something like:
|
||||
|
||||
./mk -b firefox
|
||||
|
||||
This would build every variant of Firefox in lwmk. Every defined tree, at each
|
||||
defined revision, for each target defined referencing each tree. The best
|
||||
part: because it uses the same design from the Libreboot build system, there
|
||||
are *no make files* in the tree, until you run `./mk -f`.
|
||||
|
||||
One caveat: this is a very much Linux- and BSD-brained build system. It is
|
||||
NOT designed to run on others like Windows or Mac. That being said, it can
|
||||
generate source tarballs of Firefox and its variants such as LibreWolf. These
|
||||
tarballs are cross-platform, and that will always be the case.
|
||||
|
||||
</div>
|
||||
|
||||
## Infra
|
||||
|
||||
### Overview
|
||||
|
||||
```mermaid
|
||||
graph LR
|
||||
FFSRC(Firefox Source)
|
||||
|
||||
FFSRC--Tarball--->Source
|
||||
|
||||
subgraph LibreWolf/
|
||||
Website(Website<br><br>- Documentation<br>- FAQ)
|
||||
subgraph Browser/
|
||||
Source(Source<br><br>- Patches<br>- Theming<br>- Settings<br>- Weblate<br>- Build scripts)
|
||||
bsys6(bsys6<br><br>New Docker building<br>repository)
|
||||
AppImage
|
||||
ArchGentoo["Arch / Gentoo"]
|
||||
end
|
||||
end
|
||||
Website-->librewolf.net
|
||||
Source--"Source tarball"-->bsys6
|
||||
AppImage--".appimage"-->librewolf.net
|
||||
bsys6--"Windows setup.exe"--->librewolf.net
|
||||
bsys6--"Windows portable.zip"--->librewolf.net
|
||||
bsys6--"Windows .msix"--->MS("Microsoft Store")
|
||||
bsys6--"Windows .nupkg"--->Chocolatey
|
||||
bsys6--"Linux binary tarball"--->Flathub
|
||||
bsys6--"Linux binary tarball"--> AppImage
|
||||
bsys6--"Linux .deb"--->repo.librewolf.net
|
||||
bsys6--"Linux .rpm"--->repo.librewolf.net
|
||||
bsys6--"Linux binary tarball<br>for 'librewolf-bin'"--> ArchGentoo
|
||||
Source--"Source tarball<br>for 'librewolf'"-->ArchGentoo
|
||||
ArchGentoo-->AUR_Overlay["AUR / Overlay"]
|
||||
```
|
||||
|
||||
### Packages
|
||||
|
||||
These are the locations where people have their repositories and build artifacts.
|
||||
|
||||
Active:
|
||||
|
||||
- [Arch](https://archlinux.org/packages/extra/x86_64/librewolf/) - Arch Linux package
|
||||
- [BSYS6](https://librewolf.dev/librewolf/bsys6) - Linux Mint, Fedora,
|
||||
Ubuntu, MacOS, portable and setup for Windows
|
||||
- [Gentoo](https://codeberg.org/librewolf/gentoo) - Gentoo GNU/Linux package
|
||||
|
||||
Downstream:
|
||||
|
||||
- [Alpine Linux](https://pkgs.alpinelinux.org/packages?name=librewolf&arch=)
|
||||
|
||||
### Forks
|
||||
|
||||
Previous:
|
||||
|
||||
- [CachyOS Browser](https://github.com/cachyos/cachyos-browser-settings)
|
||||
- [FireDragon Browser](https://github.com/dr460nf1r3/firedragon-browser)
|
||||
|
||||
## Build
|
||||
|
||||
There are two ways to build LibreWolf.
|
||||
You can either use the source tarball
|
||||
or compile directly with this repository.
|
||||
|
||||
### Build: Tarball
|
||||
|
||||
1. Let's **[download the latest tarball](https://librewolf.dev/librewolf/source/releases)**.
|
||||
This tarball is the latest produced by the [CI](https://librewolf.dev/librewolf/source/actions?workflow=source-release.yaml).
|
||||
You can also check the `sha256sum` of the tarball there:
|
||||
|
||||
```bash
|
||||
tar xf <tarball>
|
||||
cd <folder>
|
||||
```
|
||||
|
||||
2. Then, you have to bootstrap your system to be able to build LibreWolf.
|
||||
You only have to do this one time.
|
||||
It is done by running the following command:
|
||||
|
||||
```bash
|
||||
./mach --no-interactive bootstrap --application-choice=browser
|
||||
```
|
||||
|
||||
3. Build LibreWolf and then package or run it with the following commands:
|
||||
|
||||
```bash
|
||||
./mach build && ./mach package
|
||||
# or
|
||||
./mach build && ./mach run
|
||||
```
|
||||
|
||||
> [!NOTE]
|
||||
>
|
||||
> To get all parameters of `./mach`, use:
|
||||
>
|
||||
> ```bash
|
||||
> ./mach configure -- --help | less
|
||||
> ```
|
||||
|
||||
### Build: Repository
|
||||
|
||||
1. Clone this repository with Git:
|
||||
|
||||
```bash
|
||||
git clone --recursive git@librewolf.dev:librewolf/source.git librewolf-source --depth=1 && cd librewolf-source
|
||||
```
|
||||
|
||||
2. Build LibreWolf source code,
|
||||
also you have to bootstrap your system to be able to build LibreWolf.
|
||||
You only have to do this one time.
|
||||
|
||||
```bash
|
||||
make dir && make bootstrap
|
||||
```
|
||||
|
||||
3. Package LibreWolf or run it with the following commands:
|
||||
|
||||
```bash
|
||||
make build && make package
|
||||
# or
|
||||
make build && make run
|
||||
```
|
||||
|
||||
## Translations
|
||||
|
||||
We use Weblate to localize all LibreWolf-specific strings.
|
||||
You can help us by translating LibreWolf into your language at
|
||||
<https://translate.codeberg.org/engage/librewolf>.
|
||||
Here is the current translation status:
|
||||
|
||||
<a href="https://translate.codeberg.org/engage/librewolf/">
|
||||
<img src="https://translate.codeberg.org/widget/librewolf/multi-auto.svg" alt="Translation status"/>
|
||||
</a>
|
||||
|
||||
## Development
|
||||
|
||||
### Development: Creating a patch
|
||||
|
||||
The easiest way to make patches is to go to the LibreWolf source folder:
|
||||
|
||||
```bash
|
||||
cd librewolf-$(cat version)
|
||||
git init
|
||||
git add <path_to_file_you_changed>
|
||||
git commit -am initial-commit
|
||||
git diff > ../mypatch.patch
|
||||
```
|
||||
|
||||
We have Gitter / Matrix rooms,
|
||||
and on the website we have links to the various issue trackers.
|
||||
|
||||
### Development: Existing patches
|
||||
|
||||
The easiest way to make patches is to go to the LibreWolf source folder:
|
||||
|
||||
```bash
|
||||
make fetch
|
||||
./scripts/git-patchtree.sh patches/sed-patches/disable-pocket.patch
|
||||
```
|
||||
|
||||
Now change the source tree the way you want,
|
||||
keeping in mind to `git add` new files.
|
||||
When done, you can create the new patch with:
|
||||
|
||||
```bash
|
||||
cd firefox-<version>
|
||||
git diff 4b825dc642cb6eb9a060e54bf8d69288fbee4904 HEAD > ../my-patch-name.patch
|
||||
```
|
||||
|
||||
This ID is the hash value of the first commit, which is called `initial`.
|
||||
Don't forget to commit changes before doing this diff,
|
||||
or the patch will be incomplete.
|
||||
|
||||
### Development: Creating a patch for problems in Mozilla's [Bugzilla](https://bugzilla.mozilla.org)
|
||||
|
||||
Well, first of all:
|
||||
|
||||
- [Create an account](https://bugzilla.mozilla.org/createaccount.cgi).
|
||||
- Handy link: [Bugs Filed Today](https://bugzilla.mozilla.org/buglist.cgi?cmdtype=dorem&remaction=run&namedcmd=Bugs%20Filed%20Today&sharer_id=1&list_id=15939480).
|
||||
- The essential: [Firefox Source Tree Documentation](https://firefox-source-docs.mozilla.org/).
|
||||
|
||||
Now that you have a patch in LibreWolf, that's not enough to upload to Mozilla.
|
||||
See, Mozilla only accepts patches against Nightly.
|
||||
So here is how to do that:
|
||||
|
||||
1. If you have not done so already,
|
||||
create the `mozilla-unified` folder and build Firefox with it:
|
||||
|
||||
```bash
|
||||
hg clone https://hg.mozilla.org/mozilla-unified && cd mozilla-unified
|
||||
hg update
|
||||
MOZBUILD_STATE_PATH=$HOME/.mozbuild ./mach --no-interactive bootstrap --application-choice=browser
|
||||
./mach build
|
||||
./mach run
|
||||
```
|
||||
|
||||
2. If you skipped the previous step, you could ensure that you're up to date with:
|
||||
|
||||
```bash
|
||||
cd mozilla-unified
|
||||
hg pull && hg update
|
||||
```
|
||||
|
||||
3. Now you can apply your patch to Nightly:
|
||||
|
||||
```bash
|
||||
patch -p1 -i ../mypatch.patch
|
||||
```
|
||||
|
||||
4. Now, let Mercurial create the patch:
|
||||
|
||||
```bash
|
||||
hg diff > ../my-nightly-patch.patch
|
||||
```
|
||||
|
||||
5. After this, it can be uploaded to Bugzilla.
|
||||
|
||||
#### Development: Contributing
|
||||
|
||||
Time to start hacking! You should join us on [Matrix](https://chat.mozilla.org),
|
||||
say hello in the [Introduction channel](https://chat.mozilla.org/#/room/#introduction:mozilla.org),
|
||||
and [find a bug to start working on](https://codetribute.mozilla.org).
|
||||
See the [Firefox Contributors' Quick Reference](https://firefox-source-docs.mozilla.org/contributing/contribution_quickref.html#firefox-contributors-quick-reference)
|
||||
to learn how to test your changes,
|
||||
send patches to Mozilla,
|
||||
update your source code locally, and more.
|
||||
|
||||
## MacOS and Windows
|
||||
|
||||
We understand, life isn't always fair 😺.
|
||||
The same steps as above apply you will just have to walk through
|
||||
the beginning part of the guides for:
|
||||
|
||||
- [MacOS](https://firefox-source-docs.mozilla.org/setup/macos_build.html):
|
||||
The cross-compiled Mac `.dmg` files are somewhat new.
|
||||
They should work, perhaps with the exception of the `make setup-wasi` step.
|
||||
- [Windows](https://firefox-source-docs.mozilla.org/setup/windows_build.html):
|
||||
Building on Windows is not very well tested.
|
||||
|
||||
Help with testing these targets is always welcome.
|
||||
Libreboot
|
||||
=========
|
||||
|
||||
Find libreboot documentation at <https://libreboot.org/>
|
||||
|
||||
The `libreboot` project provides
|
||||
[libre](https://libreboot.org/freedom-status.html) *boot
|
||||
firmware* that initializes the hardware (e.g. memory controller, CPU,
|
||||
peripherals) on specific Intel/AMD x86 and ARM targets, which
|
||||
then starts a bootloader for your operating system. Linux/BSD are
|
||||
well-supported. It replaces proprietary BIOS/UEFI firmware. Help is available
|
||||
via [\#libreboot IRC](https://web.libera.chat/#libreboot)
|
||||
on [Libera](https://libera.chat/) IRC.
|
||||
|
||||
Why use Libreboot?
|
||||
==================
|
||||
|
||||
Why should you use *libreboot*?
|
||||
----------------------------
|
||||
|
||||
Libreboot gives you freedoms that you otherwise can't get with most other
|
||||
boot firmware. It's extremely powerful and configurable for many use cases.
|
||||
|
||||
You have rights. The right to privacy, freedom of thought, freedom of speech
|
||||
and the right to read. In this context, Libreboot gives you these rights.
|
||||
Your freedom matters.
|
||||
[Right to repair](https://vid.puffyan.us/watch?v=Npd_xDuNi9k) matters.
|
||||
Many people use proprietary (non-libre)
|
||||
boot firmware, even if they use [a libre OS](https://www.openbsd.org/).
|
||||
Proprietary firmware often contains backdoors (more info on the FAQ), and it
|
||||
and can be buggy. The libreboot project was founded in December 2013,
|
||||
with the express purpose of making coreboot firmware accessible for
|
||||
non-technical users.
|
||||
|
||||
The `libreboot` project uses [coreboot](https://www.coreboot.org/) for [hardware
|
||||
initialisation](https://doc.coreboot.org/getting_started/architecture.html).
|
||||
Coreboot is notoriously difficult to install for most non-technical users; it
|
||||
handles only basic initialization and jumps to a separate
|
||||
[payload](https://doc.coreboot.org/payloads.html) program (e.g.
|
||||
[GRUB](https://www.gnu.org/software/grub/),
|
||||
[Tianocore](https://www.tianocore.org/)), which must also be configured.
|
||||
*The libreboot software solves this problem*; it is a *coreboot distribution* with
|
||||
an automated build system (named *lbmk*) that builds complete *ROM images*, for
|
||||
more robust installation. Documentation is provided.
|
||||
|
||||
How does Libreboot differ from coreboot?
|
||||
========================================
|
||||
|
||||
In the same way that *Debian* is a GNU+Linux distribution, `libreboot` is
|
||||
a *coreboot distribution*. If you want to build a ROM image from scratch, you
|
||||
otherwise have to perform expert-level configuration of coreboot, GRUB and
|
||||
whatever other software you need, to prepare the ROM image. With *libreboot*,
|
||||
you can literally download from Git or a source archive, and run `make`, and it
|
||||
will build entire ROM images. An automated build system, named `lbmk`
|
||||
(Libreboot MaKe), builds these ROM images automatically, without any user input
|
||||
or intervention required. Configuration has already been performed in advance.
|
||||
|
||||
If you were to build regular coreboot, without using libreboot's automated
|
||||
build system, it would require a lot more intervention and decent technical
|
||||
knowledge to produce a working configuration.
|
||||
|
||||
Regular binary releases of `libreboot` provide these
|
||||
ROM images pre-compiled, and you can simply install them, with no special
|
||||
knowledge or skill except the ability to follow installation instructions
|
||||
and run commands BSD/Linux.
|
||||
|
||||
Project goals
|
||||
=============
|
||||
|
||||
- *Support as much hardware as possible!* Libreboot aims to eventually
|
||||
have *maintainers* for every board supported by coreboot, at every
|
||||
point in time.
|
||||
- *Make coreboot easy to use*. Coreboot is notoriously difficult
|
||||
to install, due to an overall lack of user-focused documentation
|
||||
and support. Most people will simply give up before attempting to
|
||||
install coreboot. Libreboot's automated build system and user-friendly
|
||||
installation instructions solves this problem.
|
||||
|
||||
Libreboot attempts to bridge this divide by providing a build system
|
||||
automating much of the coreboot image creation and customization.
|
||||
Secondly, the project produces documentation aimed at non-technical users.
|
||||
Thirdly, the project attempts to provide excellent user support via IRC.
|
||||
|
||||
Libreboot already comes with a payload (GRUB), flashprog and other
|
||||
needed parts. Everything is fully integrated, in a way where most of
|
||||
the complicated steps that are otherwise required, are instead done
|
||||
for the user in advance.
|
||||
|
||||
You can download ROM images for your libreboot system and install
|
||||
them without having to build anything from source. If, however, you are
|
||||
interested in building your own image, the build system makes it relatively
|
||||
easy to do so.
|
||||
|
||||
Not a coreboot fork!
|
||||
--------------------
|
||||
|
||||
Libreboot is not a fork of coreboot. Every so often, the project
|
||||
re-bases on the latest version of coreboot, with the number of custom
|
||||
patches in use minimized. Tested, *stable* (static) releases are then provided
|
||||
in Libreboot, based on specific coreboot revisions.
|
||||
|
||||
How to help
|
||||
===========
|
||||
|
||||
You can check bugs listed on
|
||||
the [bug tracker](https://codeberg.org/libreboot/lbmk/issues).
|
||||
|
||||
If you spot a bug and have a fix, the website has instructions for how to send
|
||||
patches, and you can also report it. Also, this entire website is
|
||||
written in Markdown and hosted in a [separate
|
||||
repository](https://codeberg.org/libreboot/lbwww) where you can send patches.
|
||||
|
||||
Any and all development discussion and user support are all done on the IRC
|
||||
channel. More information is on <https://libreboot.org/contact.html>.
|
||||
|
||||
LICENSE FOR THIS README
|
||||
=======================
|
||||
|
||||
It's just a README file. This README file is released under the terms of the
|
||||
Creative Commons Zero license, version 1.0 of the license, which you can
|
||||
read here:
|
||||
|
||||
<https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt>
|
||||
|
||||
@@ -0,0 +1,151 @@
|
||||
#!/usr/bin/env sh
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
# SPDX-FileCopyrightText: 2014,2015,2020,2021,2023 Leah Rowe <leah@libreboot.org>
|
||||
# SPDX-FileCopyrightText: 2015 Patrick "P. J." McDermott <pj@pehjota.net>
|
||||
# SPDX-FileCopyrightText: 2015, 2016 Klemens Nanni <contact@autoboot.org>
|
||||
# SPDX-FileCopyrightText: 2022, Caleb La Grange <thonkpeasant@protonmail.com>
|
||||
|
||||
set -u -e
|
||||
|
||||
export LC_COLLATE=C
|
||||
export LC_ALL=C
|
||||
|
||||
. "include/err.sh"
|
||||
. "include/option.sh"
|
||||
|
||||
eval "$(setvars "" option aur_notice tmpdir)"
|
||||
err="fail"
|
||||
|
||||
tmpdir_was_set="y"
|
||||
set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n"
|
||||
if [ "${tmpdir_was_set}" = "y" ]; then
|
||||
[ "${TMPDIR%_*}" = "/tmp/lbmk" ] || tmpdir_was_set="n"
|
||||
fi
|
||||
if [ "${tmpdir_was_set}" = "n" ]; then
|
||||
export TMPDIR="/tmp"
|
||||
tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)"
|
||||
export TMPDIR="${tmpdir}"
|
||||
else
|
||||
export TMPDIR="${TMPDIR}"
|
||||
tmpdir="${TMPDIR}"
|
||||
fi
|
||||
|
||||
linkpath="${0}"
|
||||
linkname="${linkpath##*/}"
|
||||
buildpath="./script/${linkname}"
|
||||
|
||||
main()
|
||||
{
|
||||
x_ id -u 1>/dev/null 2>/dev/null
|
||||
[ $# -lt 1 ] && $err "Too few arguments. Try: ${0} help"
|
||||
|
||||
[ "$1" = "dependencies" ] && x_ install_packages $@ && lbmk_exit 0
|
||||
|
||||
for cmd in initcmd check_git check_project git_init excmd; do
|
||||
eval "${cmd} \$@"
|
||||
done
|
||||
lbmk_exit 0
|
||||
}
|
||||
|
||||
initcmd()
|
||||
{
|
||||
[ "$(id -u)" != "0" ] || $err "this command as root is not permitted"
|
||||
|
||||
check_project
|
||||
|
||||
case "${1}" in
|
||||
help) usage ${0} ;;
|
||||
list) items "${buildpath}" ;;
|
||||
version) mkversion ;;
|
||||
*)
|
||||
option="${1}"
|
||||
return 0 ;;
|
||||
esac
|
||||
lbmk_exit 0
|
||||
}
|
||||
|
||||
install_packages()
|
||||
{
|
||||
if [ $# -lt 2 ]; then
|
||||
printf "You must specify a distro, namely:\n" 1>&2
|
||||
printf "Look at files under config/dependencies/\n" 1>&2
|
||||
printf "Example: ./build dependencies debian\n" 1>&2
|
||||
$err "install_packages: target not specified"
|
||||
fi
|
||||
|
||||
[ -f "config/dependencies/${2}" ] || $err "Unsupported target"
|
||||
|
||||
. "config/dependencies/${2}"
|
||||
|
||||
x_ ${pkg_add} ${pkglist}
|
||||
[ -z "${aur_notice}" ] && return 0
|
||||
printf "You must install AUR packages: %s\n" "$aur_notice" 1>&2
|
||||
}
|
||||
|
||||
# release archives contain .gitignore, but not .git.
|
||||
# lbmk can be run from lbmk.git, or an archive.
|
||||
git_init()
|
||||
{
|
||||
[ -L ".git" ] && $err "Reference .git is a symlink"
|
||||
[ -e ".git" ] && return 0
|
||||
eval "$(setvars "$(date -Rd @${versiondate})" cdate _nogit)"
|
||||
|
||||
git init || $err "${PWD}: cannot initialise Git repository"
|
||||
git add -A . || $err "${PWD}: cannot add files to Git repository"
|
||||
git commit -m "${projectname} ${version}" --date "${cdate}" \
|
||||
--author="lbmk <lbmk@libreboot.org>" || \
|
||||
$err "$PWD: can't commit ${projectname}/${version}, date $cdate"
|
||||
git tag -a "${version}" -m "${projectname} ${version}" || \
|
||||
$err "${PWD}: cannot git-tag ${projectname}/${version}"
|
||||
}
|
||||
|
||||
excmd()
|
||||
{
|
||||
lbmkcmd="${buildpath}/${option}"
|
||||
[ -f "${lbmkcmd}" ] || $err "Invalid command. Run: ${linkpath} help"
|
||||
shift 1; "$lbmkcmd" $@ || $err "excmd: ${lbmkcmd} ${@}"
|
||||
}
|
||||
|
||||
usage()
|
||||
{
|
||||
progname=${0}
|
||||
cat <<- EOF
|
||||
$(mkversion)
|
||||
|
||||
USAGE: ${progname} <OPTION>
|
||||
|
||||
possible values for 'OPTION':
|
||||
$(items "${buildpath}")
|
||||
|
||||
To know what ${projectname} version you're on, type:
|
||||
${progname} version
|
||||
|
||||
Refer to ${projectname} documentation for more info.
|
||||
EOF
|
||||
}
|
||||
|
||||
mkversion()
|
||||
{
|
||||
printf "revision: %s %s\n" "$projectname" "$version"
|
||||
printf "revision date: %s\n" "$(date -Rud @${versiondate})"
|
||||
}
|
||||
|
||||
lbmk_exit()
|
||||
{
|
||||
tmp_cleanup || err_ "lbmk_exit: can't rm tmpdir upon exit $1: $tmpdir"
|
||||
exit $1
|
||||
}
|
||||
|
||||
fail()
|
||||
{
|
||||
tmp_cleanup || printf "WARNING: can't rm tmpdir: %s\n" "$tmpdir" 1>&2
|
||||
err_ "${1}"
|
||||
}
|
||||
|
||||
tmp_cleanup()
|
||||
{
|
||||
[ "${tmpdir_was_set}" = "n" ] || return 0
|
||||
rm -Rf "${tmpdir}" || return 1
|
||||
}
|
||||
|
||||
main $@
|
||||
@@ -0,0 +1 @@
|
||||
build/coreboot.rom
|
||||
+56
@@ -0,0 +1,56 @@
|
||||
From f22f408956bf02609a96b7d72fb3321da159bfc6 Mon Sep 17 00:00:00 2001
|
||||
From: Nico Huber <nico.huber@secunet.com>
|
||||
Date: Tue, 22 Jun 2021 13:49:44 +0000
|
||||
Subject: [PATCH 1/1] cbfstool: Make use of spurious null-termination
|
||||
|
||||
The null-termination of `filetypes` was added after the code was
|
||||
written, obviously resulting in NULL dereferences. As some more
|
||||
code has grown around the termination, it's hard to revert the
|
||||
regression, so let's update the code that still used the array
|
||||
length.
|
||||
|
||||
This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
|
||||
which actually did fix something, but only one path while it broke
|
||||
two others. We should be careful with fixes, they can always break
|
||||
something else. Especially when a dumb tool triggered the patching
|
||||
it seems likely that fewer people looked into related code.
|
||||
|
||||
Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
|
||||
Signed-off-by: Nico Huber <nico.huber@secunet.com>
|
||||
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
|
||||
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
||||
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
||||
---
|
||||
util/cbfstool/common.c | 8 ++++----
|
||||
1 file changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
|
||||
index e2ed38ffc4..539d0baccf 100644
|
||||
--- a/util/cbfstool/common.c
|
||||
+++ b/util/cbfstool/common.c
|
||||
@@ -168,10 +168,10 @@ void print_supported_architectures(void)
|
||||
|
||||
void print_supported_filetypes(void)
|
||||
{
|
||||
- int i, number = ARRAY_SIZE(filetypes);
|
||||
+ int i;
|
||||
|
||||
- for (i=0; i<number; i++) {
|
||||
- printf(" %s%c", filetypes[i].name, (i==(number-1))?'\n':',');
|
||||
+ for (i=0; filetypes[i].name; i++) {
|
||||
+ printf(" %s%c", filetypes[i].name, filetypes[i + 1].name ? ',' : '\n');
|
||||
if ((i%8) == 7)
|
||||
printf("\n");
|
||||
}
|
||||
@@ -180,7 +180,7 @@ void print_supported_filetypes(void)
|
||||
uint64_t intfiletype(const char *name)
|
||||
{
|
||||
size_t i;
|
||||
- for (i = 0; i < (sizeof(filetypes) / sizeof(struct typedesc_t)); i++)
|
||||
+ for (i = 0; filetypes[i].name; i++)
|
||||
if (strcmp(filetypes[i].name, name) == 0)
|
||||
return filetypes[i].type;
|
||||
return -1;
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,2 @@
|
||||
tree="coreboot413"
|
||||
rev="5c186c6777c9438ff4681929c9c25c98dee28bef"
|
||||
@@ -0,0 +1,606 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="intel/d510mo"
|
||||
CONFIG_VGA_BIOS_ID="8086,a001"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Intel"
|
||||
CONFIG_CBFS_SIZE=0x00100000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
|
||||
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
|
||||
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
|
||||
|
||||
#
|
||||
# Coffeelake RVP
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
|
||||
CONFIG_BOARD_INTEL_D510MO=y
|
||||
# CONFIG_BOARD_INTEL_D945GCLF is not set
|
||||
# CONFIG_BOARD_INTEL_DCP847SKE is not set
|
||||
# CONFIG_BOARD_INTEL_DG41WV is not set
|
||||
# CONFIG_BOARD_INTEL_DG43GT is not set
|
||||
# CONFIG_BOARD_INTEL_DQ67SW is not set
|
||||
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
|
||||
# CONFIG_BOARD_INTEL_GLKRVP is not set
|
||||
# CONFIG_BOARD_INTEL_HARCUVAR is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
|
||||
# CONFIG_BOARD_INTEL_LEAFHILL is not set
|
||||
# CONFIG_BOARD_INTEL_MINNOW3 is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
|
||||
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
|
||||
# CONFIG_BOARD_INTEL_STRAGO is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
|
||||
# CONFIG_BOARD_INTEL_WTM2 is not set
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=32
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=1024
|
||||
CONFIG_ROM_SIZE=0x00100000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x80000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_106CX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_CPU_HAS_L2_ENABLE_MSR=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM=y
|
||||
CONFIG_SUPERIO_WINBOND_W83627THG=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
|
||||
CONFIG_USE_DDR3=y
|
||||
CONFIG_USE_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,6 @@
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_grub="n"
|
||||
payload_grub_withseabios="n"
|
||||
payload_seabios="y"
|
||||
payload_memtest="y"
|
||||
@@ -0,0 +1,606 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="D510MO"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="intel/d510mo"
|
||||
CONFIG_VGA_BIOS_ID="8086,a001"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Intel"
|
||||
CONFIG_CBFS_SIZE=0x01000000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=256
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
|
||||
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
|
||||
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
|
||||
|
||||
#
|
||||
# Coffeelake RVP
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
|
||||
CONFIG_BOARD_INTEL_D510MO=y
|
||||
# CONFIG_BOARD_INTEL_D945GCLF is not set
|
||||
# CONFIG_BOARD_INTEL_DCP847SKE is not set
|
||||
# CONFIG_BOARD_INTEL_DG41WV is not set
|
||||
# CONFIG_BOARD_INTEL_DG43GT is not set
|
||||
# CONFIG_BOARD_INTEL_DQ67SW is not set
|
||||
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
|
||||
# CONFIG_BOARD_INTEL_GLKRVP is not set
|
||||
# CONFIG_BOARD_INTEL_HARCUVAR is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
|
||||
# CONFIG_BOARD_INTEL_LEAFHILL is not set
|
||||
# CONFIG_BOARD_INTEL_MINNOW3 is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
|
||||
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
|
||||
# CONFIG_BOARD_INTEL_STRAGO is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
|
||||
# CONFIG_BOARD_INTEL_WTM2 is not set
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
|
||||
CONFIG_PCIEXP_HOTPLUG_BUSES=32
|
||||
CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=16384
|
||||
CONFIG_ROM_SIZE=0x01000000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x80000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_106CX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_FCBGA559=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_CPU_HAS_L2_ENABLE_MSR=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_WINBOND_COMMON_PRE_RAM=y
|
||||
CONFIG_SUPERIO_WINBOND_W83627THG=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x10000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
|
||||
# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
|
||||
CONFIG_PCIEXP_HOTPLUG_IO=0x2000
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
|
||||
CONFIG_USE_DDR3=y
|
||||
CONFIG_USE_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
CONFIG_DRIVERS_I2C_CK505=y
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,5 @@
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_memtest="y"
|
||||
@@ -0,0 +1,605 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="intel/d945gclf"
|
||||
CONFIG_VGA_BIOS_ID="8086,2772"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Intel"
|
||||
CONFIG_CBFS_SIZE=0x00080000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_IRQ_SLOT_COUNT=18
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
|
||||
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
|
||||
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
|
||||
|
||||
#
|
||||
# Coffeelake RVP
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_D510MO is not set
|
||||
CONFIG_BOARD_INTEL_D945GCLF=y
|
||||
# CONFIG_BOARD_INTEL_DCP847SKE is not set
|
||||
# CONFIG_BOARD_INTEL_DG41WV is not set
|
||||
# CONFIG_BOARD_INTEL_DG43GT is not set
|
||||
# CONFIG_BOARD_INTEL_DQ67SW is not set
|
||||
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
|
||||
# CONFIG_BOARD_INTEL_GLKRVP is not set
|
||||
# CONFIG_BOARD_INTEL_HARCUVAR is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
|
||||
# CONFIG_BOARD_INTEL_LEAFHILL is not set
|
||||
# CONFIG_BOARD_INTEL_MINNOW3 is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
|
||||
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
|
||||
# CONFIG_BOARD_INTEL_STRAGO is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
|
||||
# CONFIG_BOARD_INTEL_WTM2 is not set
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=512
|
||||
CONFIG_ROM_SIZE=0x00080000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_106CX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_441=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_I945=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_LPC47M15X=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
CONFIG_HAVE_MP_TABLE=y
|
||||
CONFIG_HAVE_PIRQ_TABLE=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_MP_TABLE=y
|
||||
CONFIG_GENERATE_PIRQ_TABLE=y
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
# CONFIG_DEBUG_PIRQ is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,6 @@
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_grub="n"
|
||||
payload_grub_withseabios="n"
|
||||
payload_seabios="y"
|
||||
payload_memtest="n"
|
||||
@@ -0,0 +1,605 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
# CONFIG_NO_STAGE_CACHE is not set
|
||||
CONFIG_TSEG_STAGE_CACHE=y
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
# CONFIG_VENDOR_DELL is not set
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
CONFIG_VENDOR_INTEL=y
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="intel/d945gclf"
|
||||
CONFIG_VGA_BIOS_ID="8086,2772"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Intel"
|
||||
CONFIG_CBFS_SIZE=0x00800000
|
||||
CONFIG_MAX_CPUS=4
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_IRQ_SLOT_COUNT=18
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xfefc0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x8000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
# CONFIG_DRIVERS_INTEL_WIFI is not set
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
|
||||
# CONFIG_BOARD_INTEL_ADLRVP_RPL_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
|
||||
# CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
|
||||
# CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
|
||||
# CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
|
||||
|
||||
#
|
||||
# Coffeelake RVP
|
||||
#
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_WHISKEYLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_COFFEELAKE_RVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_COMETLAKE_RVPU is not set
|
||||
# CONFIG_BOARD_INTEL_D510MO is not set
|
||||
CONFIG_BOARD_INTEL_D945GCLF=y
|
||||
# CONFIG_BOARD_INTEL_DCP847SKE is not set
|
||||
# CONFIG_BOARD_INTEL_DG41WV is not set
|
||||
# CONFIG_BOARD_INTEL_DG43GT is not set
|
||||
# CONFIG_BOARD_INTEL_DQ67SW is not set
|
||||
# CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
|
||||
# CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
|
||||
# CONFIG_BOARD_INTEL_GLKRVP is not set
|
||||
# CONFIG_BOARD_INTEL_HARCUVAR is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
|
||||
# CONFIG_BOARD_INTEL_JASPERLAKE_RVP_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP3 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP7 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP8 is not set
|
||||
# CONFIG_BOARD_INTEL_KBLRVP11 is not set
|
||||
# CONFIG_BOARD_INTEL_KUNIMITSU is not set
|
||||
# CONFIG_BOARD_INTEL_LEAFHILL is not set
|
||||
# CONFIG_BOARD_INTEL_MINNOW3 is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
|
||||
# CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
|
||||
# CONFIG_BOARD_INTEL_SKLSDLBRK is not set
|
||||
# CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
|
||||
# CONFIG_BOARD_INTEL_STRAGO is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP3 is not set
|
||||
# CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
|
||||
# CONFIG_BOARD_INTEL_WTM2 is not set
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
# CONFIG_PCIEXP_ASPM is not set
|
||||
# CONFIG_PCIEXP_L1_SUB_STATE is not set
|
||||
# CONFIG_PCIEXP_CLK_PM is not set
|
||||
# CONFIG_DRIVERS_UART_8250IO is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=8192
|
||||
CONFIG_ROM_SIZE=0x00800000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
|
||||
CONFIG_EHCI_BAR=0xfef00000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_INTEL_HAS_TOP_SWAP=y
|
||||
# CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
|
||||
CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_MODEL_106CX=y
|
||||
CONFIG_CPU_INTEL_SOCKET_441=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_MICROCODE_UPDATE_PRE_RAM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_I945=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_HPET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_LPC47M15X=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
CONFIG_SIPI_VECTOR_IN_ROM=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_NATIVE_VGA_INIT=y
|
||||
CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR2=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_EDID=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_INTEL_GMA_SSC_ALTERNATE_REF=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_CBMEM_DUMP_TO_UART is not set
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=0
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_NULL=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
CONFIG_HAVE_MP_TABLE=y
|
||||
CONFIG_HAVE_PIRQ_TABLE=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_MP_TABLE=y
|
||||
CONFIG_GENERATE_PIRQ_TABLE=y
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
# CONFIG_DEBUG_PIRQ is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,6 @@
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_grub="n"
|
||||
payload_grub_withseabios="n"
|
||||
payload_seabios="y"
|
||||
payload_memtest="n"
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
From 1195c954a3b6822e5e843067251c0c80c9520eab Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@retroboot.org>
|
||||
Date: Fri, 19 Mar 2021 05:54:58 +0000
|
||||
Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of
|
||||
8MiB
|
||||
|
||||
---
|
||||
src/mainboard/apple/macbook21/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
|
||||
index cf1bc4566e..dc0df3b6d6 100644
|
||||
--- a/src/mainboard/apple/macbook21/cmos.default
|
||||
+++ b/src/mainboard/apple/macbook21/cmos.default
|
||||
@@ -5,4 +5,4 @@ boot_devices=''
|
||||
boot_default=0x40
|
||||
cmos_defaults_loaded=Yes
|
||||
lpt=Enable
|
||||
-gfx_uma_size=8M
|
||||
+gfx_uma_size=64M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
From 50a52cea2b43e6e407b456c082e908c7d29e090b Mon Sep 17 00:00:00 2001
|
||||
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
|
||||
Date: Wed, 27 Oct 2021 13:36:01 +0200
|
||||
Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
|
||||
|
||||
---
|
||||
src/mainboard/apple/macbook21/Kconfig | 1 +
|
||||
src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++
|
||||
src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++
|
||||
3 files changed, 20 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
|
||||
index 5f5ffde588..27377b737c 100644
|
||||
--- a/src/mainboard/apple/macbook21/Kconfig
|
||||
+++ b/src/mainboard/apple/macbook21/Kconfig
|
||||
@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_ACPI_RESUME
|
||||
select I945_LVDS
|
||||
+ select DRIVERS_I2C_CK505
|
||||
|
||||
config MAINBOARD_DIR
|
||||
default "apple/macbook21"
|
||||
diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c
|
||||
index 13d06f0839..88b8669c61 100644
|
||||
--- a/src/mainboard/apple/macbook21/cstates.c
|
||||
+++ b/src/mainboard/apple/macbook21/cstates.c
|
||||
@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = {
|
||||
.addrh = 0,
|
||||
}
|
||||
},
|
||||
+ {
|
||||
+ .ctype = 3,
|
||||
+ .latency = 17,
|
||||
+ .power = 250,
|
||||
+ .resource = {
|
||||
+ .space_id = ACPI_ADDRESS_SPACE_FIXED,
|
||||
+ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
|
||||
+ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
|
||||
+ .access_size = ACPI_ACCESS_SIZE_UNDEFINED,
|
||||
+ .addrl = 0x20,
|
||||
+ .addrh = 0,
|
||||
+ }
|
||||
+ },
|
||||
};
|
||||
|
||||
int get_cst_entries(const acpi_cstate_t **entries)
|
||||
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
|
||||
index fd86e939b9..263fbabcd1 100644
|
||||
--- a/src/mainboard/apple/macbook21/devicetree.cb
|
||||
+++ b/src/mainboard/apple/macbook21/devicetree.cb
|
||||
@@ -100,7 +100,13 @@ chip northbridge/intel/i945
|
||||
end
|
||||
device pci 1f.3 on # SMBUS
|
||||
subsystemid 0x8086 0x7270
|
||||
+ chip drivers/i2c/ck505
|
||||
+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }"
|
||||
+ register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }"
|
||||
+ device i2c 69 on end
|
||||
+ end
|
||||
end
|
||||
+
|
||||
end
|
||||
end
|
||||
end
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
From ca4cd66f411247395a323e5ea1abf09e83057827 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@osboot.org>
|
||||
Date: Sun, 3 Jan 2021 03:34:01 +0000
|
||||
Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default
|
||||
(previously it was 8MiB)
|
||||
|
||||
---
|
||||
src/mainboard/lenovo/x60/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
|
||||
index 5c3576d1f3..88170a1aab 100644
|
||||
--- a/src/mainboard/lenovo/x60/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x60/cmos.default
|
||||
@@ -15,4 +15,4 @@ trackpoint=Enable
|
||||
sticky_fn=Disable
|
||||
power_management_beeps=Enable
|
||||
low_battery_beep=Enable
|
||||
-gfx_uma_size=8M
|
||||
+gfx_uma_size=64M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
From eca0f4a3a4d6907e92b948547a362ca0ac3fc382 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@osboot.org>
|
||||
Date: Mon, 22 Feb 2021 22:16:59 +0000
|
||||
Subject: [PATCH 04/30] lenovo/t60: make 64MiB VRAM the default in cmos.default
|
||||
|
||||
---
|
||||
src/mainboard/lenovo/t60/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
|
||||
index af865f16da..7f03157df7 100644
|
||||
--- a/src/mainboard/lenovo/t60/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t60/cmos.default
|
||||
@@ -15,4 +15,4 @@ trackpoint=Enable
|
||||
sticky_fn=Disable
|
||||
power_management_beeps=Enable
|
||||
low_battery_beep=Enable
|
||||
-gfx_uma_size=8M
|
||||
+gfx_uma_size=64M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
From 2eae87815675aebd472b6042777fe51279be4550 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Fri, 14 May 2021 13:10:33 +0100
|
||||
Subject: [PATCH 05/30] lenovo/t400: set VRAM to 256MiB VRAM by default
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/lenovo/t400/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
|
||||
index a326e315b1..b907a3e2df 100644
|
||||
--- a/src/mainboard/lenovo/t400/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t400/cmos.default
|
||||
@@ -13,4 +13,4 @@ power_management_beeps=Enable
|
||||
low_battery_beep=Enable
|
||||
sata_mode=AHCI
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
-gfx_uma_size=32M
|
||||
+gfx_uma_size=256M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,23 @@
|
||||
From f6b4913a5eca619b745d5ccea9af022a54fb185b Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Fri, 14 May 2021 13:11:59 +0100
|
||||
Subject: [PATCH 06/30] lenovo/x200: set VRAM to 256MiB by default
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/lenovo/x200/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
|
||||
index bb4323836e..458b3f19c5 100644
|
||||
--- a/src/mainboard/lenovo/x200/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x200/cmos.default
|
||||
@@ -12,4 +12,4 @@ sticky_fn=Disable
|
||||
power_management_beeps=Enable
|
||||
low_battery_beep=Enable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=32M
|
||||
+gfx_uma_size=256M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
From a3a0969075163be413f968b03671aa5d8662672a Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Fri, 14 May 2021 13:18:26 +0100
|
||||
Subject: [PATCH 07/30] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
|
||||
index 8372032119..bedad54d2a 100644
|
||||
--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
|
||||
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
|
||||
@@ -2,4 +2,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
power_on_after_fail=Enable
|
||||
nmi=Enable
|
||||
-gfx_uma_size=64M
|
||||
+gfx_uma_size=256M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+23
@@ -0,0 +1,23 @@
|
||||
From 223ac17617b3a0c08925abbbe42d0d003e144a28 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Fri, 14 May 2021 13:21:39 +0100
|
||||
Subject: [PATCH 08/30] acer/g43t-am3: set VRAM to 256MiB by default
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/acer/g43t-am3/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
|
||||
index 706f5dd551..e8b45ea22c 100644
|
||||
--- a/src/mainboard/acer/g43t-am3/cmos.default
|
||||
+++ b/src/mainboard/acer/g43t-am3/cmos.default
|
||||
@@ -3,4 +3,4 @@ debug_level=Debug
|
||||
power_on_after_fail=Disable
|
||||
nmi=Enable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=64M
|
||||
+gfx_uma_size=256M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,34 @@
|
||||
From 80ebbfef42454ea0911e5fc3858103d905987ed8 Mon Sep 17 00:00:00 2001
|
||||
From: persmule <persmule@gmail.com>
|
||||
Date: Sun, 31 Oct 2021 23:33:26 +0000
|
||||
Subject: [PATCH 09/30] lenovo/t400: Enable all SATA ports
|
||||
|
||||
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
|
||||
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
|
||||
chassis, and another one on its dock.
|
||||
|
||||
They have to be unmasked via device tree to use.
|
||||
|
||||
This patch unmasked all SATA ports found within t400s with factory firmware.
|
||||
---
|
||||
src/mainboard/lenovo/t400/devicetree.cb | 4 ++--
|
||||
1 file changed, 2 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
|
||||
index 259c3e1b21..3d007533a4 100644
|
||||
--- a/src/mainboard/lenovo/t400/devicetree.cb
|
||||
+++ b/src/mainboard/lenovo/t400/devicetree.cb
|
||||
@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
|
||||
register "gpe0_en" = "0x01000000"
|
||||
register "gpi1_routing" = "2"
|
||||
|
||||
- # Set AHCI mode, enable ports 1 and 2.
|
||||
- register "sata_port_map" = "0x03"
|
||||
+ # Set AHCI mode, enable ports 1, 2, 5 and 6.
|
||||
+ register "sata_port_map" = "0x33"
|
||||
register "sata_clock_request" = "0"
|
||||
register "sata_traffic_monitor" = "0"
|
||||
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+22
@@ -0,0 +1,22 @@
|
||||
From 318a97c284f8d5030100476a32516ddc9e51603d Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 20 Dec 2021 01:29:31 +0000
|
||||
Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
|
||||
default
|
||||
|
||||
---
|
||||
src/mainboard/lenovo/x230/cmos.default | 1 +
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
|
||||
index 7314066c2b..2e315d4521 100644
|
||||
--- a/src/mainboard/lenovo/x230/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x230/cmos.default
|
||||
@@ -16,3 +16,4 @@ backlight=Both
|
||||
usb_always_on=Disable
|
||||
f1_to_f12_as_primary=Enable
|
||||
me_state=Normal
|
||||
+gfx_uma_size=224M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+38
@@ -0,0 +1,38 @@
|
||||
From 47afbe8b94edd1ff58c1daf0bda020e6afac35f4 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 3 Jan 2022 19:06:22 +0000
|
||||
Subject: [PATCH 11/30] lenovo/x230: set me_state=Disabled in cmos.default
|
||||
|
||||
I only recently found out about this. It's possible to use me_cleaner to
|
||||
do the same thing, but some people might just flash coreboot and not do
|
||||
anything with the ME region
|
||||
|
||||
With this change, the ME is set to disabled. It's my understanding that this
|
||||
will accomplish more or less the same thing as me_cleaner, without actually
|
||||
using that. Of course, I still recommend using me_cleaner
|
||||
|
||||
I saw this when I audited coreboot's git history, and saw this:
|
||||
|
||||
commit 833e9bad4762e0dca6c867d3a18dbaf6d5166be8
|
||||
Author: Evgeny Zinoviev <me@ch1p.io>
|
||||
Date: Thu Nov 21 21:47:31 2019 +0300
|
||||
|
||||
sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode
|
||||
---
|
||||
src/mainboard/lenovo/x230/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
|
||||
index 2e315d4521..3585cbd58b 100644
|
||||
--- a/src/mainboard/lenovo/x230/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x230/cmos.default
|
||||
@@ -15,5 +15,5 @@ trackpoint=Enable
|
||||
backlight=Both
|
||||
usb_always_on=Disable
|
||||
f1_to_f12_as_primary=Enable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
gfx_uma_size=224M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+122
@@ -0,0 +1,122 @@
|
||||
From 531ef34ece796f38cb8a13a54856e46e79842e29 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Wed, 2 Mar 2022 21:50:01 +0000
|
||||
Subject: [PATCH 12/30] set me_state=Disabled on all cmos.default files!
|
||||
|
||||
yeah. why the hell isn't this the default
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/lenovo/l520/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t420/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t420s/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t430/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t430s/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t520/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/t530/cmos.default | 2 +-
|
||||
src/mainboard/lenovo/x220/cmos.default | 2 +-
|
||||
src/mainboard/protectli/vault_cml/cmos.default | 2 +-
|
||||
src/mainboard/system76/tgl-u/cmos.default | 2 +-
|
||||
10 files changed, 10 insertions(+), 10 deletions(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
|
||||
index 681c40e78b..57cdcf9162 100644
|
||||
--- a/src/mainboard/lenovo/l520/cmos.default
|
||||
+++ b/src/mainboard/lenovo/l520/cmos.default
|
||||
@@ -14,4 +14,4 @@ sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
backlight=Both
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
|
||||
index 8244071b8a..c011867916 100644
|
||||
--- a/src/mainboard/lenovo/t420/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t420/cmos.default
|
||||
@@ -14,4 +14,4 @@ sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
|
||||
index 8244071b8a..c011867916 100644
|
||||
--- a/src/mainboard/lenovo/t420s/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t420s/cmos.default
|
||||
@@ -14,4 +14,4 @@ sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
|
||||
index 26795fe5cf..55e1e6c04e 100644
|
||||
--- a/src/mainboard/lenovo/t430/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t430/cmos.default
|
||||
@@ -15,4 +15,4 @@ trackpoint=Enable
|
||||
backlight=Both
|
||||
usb_always_on=Disable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
|
||||
index 52dbf70377..b16800ca9e 100644
|
||||
--- a/src/mainboard/lenovo/t430s/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t430s/cmos.default
|
||||
@@ -16,4 +16,4 @@ backlight=Both
|
||||
enable_dual_graphics=Disable
|
||||
usb_always_on=Disable
|
||||
f1_to_f12_as_primary=Enable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
|
||||
index cf79b391e2..b66f7034dc 100644
|
||||
--- a/src/mainboard/lenovo/t520/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t520/cmos.default
|
||||
@@ -15,4 +15,4 @@ trackpoint=Enable
|
||||
backlight=Both
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
|
||||
index cf79b391e2..b66f7034dc 100644
|
||||
--- a/src/mainboard/lenovo/t530/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t530/cmos.default
|
||||
@@ -15,4 +15,4 @@ trackpoint=Enable
|
||||
backlight=Both
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
|
||||
index 6d1d57a795..52f303dfdb 100644
|
||||
--- a/src/mainboard/lenovo/x220/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x220/cmos.default
|
||||
@@ -13,4 +13,4 @@ usb_always_on=Disable
|
||||
fn_ctrl_swap=Disable
|
||||
sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
|
||||
index 62715bc6ba..129b5fd121 100644
|
||||
--- a/src/mainboard/protectli/vault_cml/cmos.default
|
||||
+++ b/src/mainboard/protectli/vault_cml/cmos.default
|
||||
@@ -1,3 +1,3 @@
|
||||
boot_option=Fallback
|
||||
debug_level=Debug
|
||||
-me_state=Enable
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
|
||||
index 62715bc6ba..129b5fd121 100644
|
||||
--- a/src/mainboard/system76/tgl-u/cmos.default
|
||||
+++ b/src/mainboard/system76/tgl-u/cmos.default
|
||||
@@ -1,3 +1,3 @@
|
||||
boot_option=Fallback
|
||||
debug_level=Debug
|
||||
-me_state=Enable
|
||||
+me_state=Disabled
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,198 @@
|
||||
From 7b9003f98c7c685b2fe56781f3b0916018037b72 Mon Sep 17 00:00:00 2001
|
||||
From: Alexander Couzens <lynxis@fe80.eu>
|
||||
Date: Sat, 19 Mar 2022 13:42:33 +0000
|
||||
Subject: [PATCH 13/30] lenovo/x230: introduce FHD variant
|
||||
|
||||
There is a modification for the x230 which uses the 2nd DP from the dock
|
||||
as the integrated panel's connection, which allows using a custom eDP
|
||||
panel instead of the stock LVDS display.
|
||||
|
||||
There are several adapter boards present on the market and all of them
|
||||
uses the same method of enabling the custom eDP panel.
|
||||
|
||||
To make this work with coreboot, the internal LVDS connector should be
|
||||
disabled in libgfxinit. The VBT has been modified as well, which allows
|
||||
brightness controls to work out of the box.
|
||||
|
||||
The modifications done to the VBT are:
|
||||
- Remove the LVDS port entry.
|
||||
- Move the DP-3 (which is the 2nd DP on the dock) entry to the first
|
||||
position on the list.
|
||||
- Set the DP-3 as internally connected.
|
||||
|
||||
This has been reported to work with the following panels:
|
||||
- LP125WF2-SPB4 (1920*1080, 12.5")
|
||||
- LQ125T1JW02 (2560*1440, 12.5")
|
||||
- LQ133M1JW21 (1920*1080, 13.3")
|
||||
- LTN133HL10-201 (1920*1080, 13.3")
|
||||
- B133HAN04.6 (1920*1080, 13.3")
|
||||
- B133QAN02.0 (2560*1600, 13.3")
|
||||
|
||||
Other eDP panels not on this list should work as well.
|
||||
|
||||
Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0
|
||||
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
|
||||
Signed-off-by: Felix Singer <felixsinger@posteo.net>
|
||||
---
|
||||
src/mainboard/lenovo/x230/Kconfig | 15 ++++++++-----
|
||||
src/mainboard/lenovo/x230/Kconfig.name | 3 +++
|
||||
src/mainboard/lenovo/x230/Makefile.mk | 5 +++++
|
||||
.../lenovo/x230/variants/x230_edp/data.vbt | Bin 0 -> 4281 bytes
|
||||
.../x230/variants/x230_edp/gma-mainboard.ads | 21 ++++++++++++++++++
|
||||
5 files changed, 38 insertions(+), 6 deletions(-)
|
||||
create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
|
||||
create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
|
||||
|
||||
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
|
||||
index 279095629b..acfd0ed561 100644
|
||||
--- a/src/mainboard/lenovo/x230/Kconfig
|
||||
+++ b/src/mainboard/lenovo/x230/Kconfig
|
||||
@@ -1,4 +1,4 @@
|
||||
-if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S
|
||||
+if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select H8_HAS_BAT_THRESHOLDS_IMPL
|
||||
select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S
|
||||
select NO_UART_ON_SUPERIO
|
||||
- select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
|
||||
+ select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
|
||||
select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_OPTION_TABLE
|
||||
@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select INTEL_INT15
|
||||
select DRIVERS_RICOH_RCE822
|
||||
select MEMORY_MAPPED_TPM
|
||||
- select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
|
||||
+ select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
|
||||
select MAINBOARD_HAS_LIBGFXINIT
|
||||
select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
|
||||
select INTEL_GMA_HAVE_VBT
|
||||
@@ -47,17 +47,20 @@ config MAINBOARD_DIR
|
||||
default "lenovo/x230"
|
||||
|
||||
config VARIANT_DIR
|
||||
- default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
|
||||
+ default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
|
||||
default "x230s" if BOARD_LENOVO_X230S
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
- default "ThinkPad X230" if BOARD_LENOVO_X230
|
||||
+ default "ThinkPad X230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230_EDP
|
||||
default "ThinkPad X230t" if BOARD_LENOVO_X230T
|
||||
default "ThinkPad X230s" if BOARD_LENOVO_X230S
|
||||
|
||||
config OVERRIDE_DEVICETREE
|
||||
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
|
||||
+config INTEL_GMA_VBT_FILE
|
||||
+ default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
|
||||
+
|
||||
config USBDEBUG_HCD_INDEX
|
||||
int
|
||||
default 2
|
||||
@@ -79,4 +82,4 @@ config PS2M_EISAID
|
||||
config THINKPADEC_HKEY_EISAID
|
||||
default "LEN0068"
|
||||
|
||||
-endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S
|
||||
+endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
|
||||
diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name
|
||||
index 1a01436879..e7290a12dd 100644
|
||||
--- a/src/mainboard/lenovo/x230/Kconfig.name
|
||||
+++ b/src/mainboard/lenovo/x230/Kconfig.name
|
||||
@@ -6,3 +6,6 @@ config BOARD_LENOVO_X230T
|
||||
|
||||
config BOARD_LENOVO_X230S
|
||||
bool "ThinkPad X230s"
|
||||
+
|
||||
+config BOARD_LENOVO_X230_EDP
|
||||
+ bool "ThinkPad X230 eDP Mod (2K/FHD)"
|
||||
diff --git a/src/mainboard/lenovo/x230/Makefile.mk b/src/mainboard/lenovo/x230/Makefile.mk
|
||||
index 8e801f145d..6e6f9f90b9 100644
|
||||
--- a/src/mainboard/lenovo/x230/Makefile.mk
|
||||
+++ b/src/mainboard/lenovo/x230/Makefile.mk
|
||||
@@ -5,4 +5,9 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
|
||||
romstage-y += variants/$(VARIANT_DIR)/early_init.c
|
||||
romstage-y += variants/$(VARIANT_DIR)/gpio.c
|
||||
ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
|
||||
+
|
||||
+ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y)
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads
|
||||
+else
|
||||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
|
||||
+endif
|
||||
diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt b/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
|
||||
GIT binary patch
|
||||
literal 4281
|
||||
zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^
|
||||
zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
|
||||
zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
|
||||
zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
|
||||
zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
|
||||
zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
|
||||
z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
|
||||
zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
|
||||
z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
|
||||
z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
|
||||
zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT
|
||||
zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
|
||||
z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}(
|
||||
z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg
|
||||
zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW>
|
||||
zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn
|
||||
zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L
|
||||
zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy;
|
||||
z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY
|
||||
zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
|
||||
zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
|
||||
zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
|
||||
z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
|
||||
zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
|
||||
zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
|
||||
zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
|
||||
z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
|
||||
zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
|
||||
zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH
|
||||
z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
|
||||
zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
|
||||
p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..f7cf0bc264
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
|
||||
@@ -0,0 +1,21 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (DP1,
|
||||
+ DP2,
|
||||
+ DP3,
|
||||
+ HDMI1,
|
||||
+ HDMI2,
|
||||
+ HDMI3,
|
||||
+ Analog,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+25
@@ -0,0 +1,25 @@
|
||||
From 9959fe252cceca7005b63e3313f7f95114f1f93c Mon Sep 17 00:00:00 2001
|
||||
From: Alexei Sorokin <sor.alexei@meowr.ru>
|
||||
Date: Sun, 27 Nov 2022 18:36:26 +0300
|
||||
Subject: [PATCH 14/30] lenovo/x230: fix the data.vbt path for the EDP variant
|
||||
|
||||
---
|
||||
src/mainboard/lenovo/x230/Kconfig | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
|
||||
index acfd0ed561..34108c3c04 100644
|
||||
--- a/src/mainboard/lenovo/x230/Kconfig
|
||||
+++ b/src/mainboard/lenovo/x230/Kconfig
|
||||
@@ -59,7 +59,7 @@ config OVERRIDE_DEVICETREE
|
||||
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
|
||||
config INTEL_GMA_VBT_FILE
|
||||
- default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
|
||||
+ default "src/mainboard/\$(MAINBOARDDIR)/variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
|
||||
|
||||
config USBDEBUG_HCD_INDEX
|
||||
int
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+203
@@ -0,0 +1,203 @@
|
||||
From 158b79e6057e071d039619f617c112d31fb13f64 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 19 Feb 2023 18:21:43 +0000
|
||||
Subject: [PATCH 15/30] util/ifdtool: add --nuke flag (all 0xFF on region)
|
||||
|
||||
When this option is used, the region's contents are overwritten
|
||||
with all ones (0xFF).
|
||||
|
||||
Example:
|
||||
|
||||
./ifdtool --nuke gbe coreboot.rom
|
||||
./ifdtool --nuke bios coreboot.com
|
||||
./ifdtool --nuke me coreboot.com
|
||||
|
||||
Rebased since the last revision update in lbmk.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
|
||||
1 file changed, 81 insertions(+), 31 deletions(-)
|
||||
|
||||
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
|
||||
index 191b3216de..38132b4a28 100644
|
||||
--- a/util/ifdtool/ifdtool.c
|
||||
+++ b/util/ifdtool/ifdtool.c
|
||||
@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
|
||||
" tgl - Tiger Lake\n"
|
||||
" wbg - Wellsburg\n"
|
||||
" -S | --setpchstrap Write a PCH strap\n"
|
||||
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
|
||||
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
|
||||
" -v | --version: print the version\n"
|
||||
" -h | --help: print this help\n\n"
|
||||
@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
|
||||
"\n");
|
||||
}
|
||||
|
||||
+static int
|
||||
+get_region_type_string(const char *region_type_string)
|
||||
+{
|
||||
+ if (!strcasecmp("Descriptor", region_type_string))
|
||||
+ return 0;
|
||||
+ else if (!strcasecmp("BIOS", region_type_string))
|
||||
+ return 1;
|
||||
+ else if (!strcasecmp("ME", region_type_string))
|
||||
+ return 2;
|
||||
+ else if (!strcasecmp("GbE", region_type_string))
|
||||
+ return 3;
|
||||
+ else if (!strcasecmp("Platform Data", region_type_string))
|
||||
+ return 4;
|
||||
+ else if (!strcasecmp("Device Exp1", region_type_string))
|
||||
+ return 5;
|
||||
+ else if (!strcasecmp("Secondary BIOS", region_type_string))
|
||||
+ return 6;
|
||||
+ else if (!strcasecmp("Reserved", region_type_string))
|
||||
+ return 7;
|
||||
+ else if (!strcasecmp("EC", region_type_string))
|
||||
+ return 8;
|
||||
+ else if (!strcasecmp("Device Exp2", region_type_string))
|
||||
+ return 9;
|
||||
+ else if (!strcasecmp("IE", region_type_string))
|
||||
+ return 10;
|
||||
+ else if (!strcasecmp("10GbE_0", region_type_string))
|
||||
+ return 11;
|
||||
+ else if (!strcasecmp("10GbE_1", region_type_string))
|
||||
+ return 12;
|
||||
+ else if (!strcasecmp("PTT", region_type_string))
|
||||
+ return 15;
|
||||
+ return -1;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+nuke(const char *filename, char *image, int size, int region_type)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct region region;
|
||||
+ const struct frba *frba = find_frba(image, size);
|
||||
+ if (!frba)
|
||||
+ exit(EXIT_FAILURE);
|
||||
+
|
||||
+ region = get_region(frba, region_type);
|
||||
+ if (region.size > 0) {
|
||||
+ for (i = region.base; i <= region.limit; i++) {
|
||||
+ if ((i + 1) > (size))
|
||||
+ break;
|
||||
+ image[i] = 0xFF;
|
||||
+ }
|
||||
+ write_image(filename, image, size);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int opt, option_index = 0;
|
||||
@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
|
||||
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
|
||||
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
|
||||
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
|
||||
+ int mode_nuke = 0;
|
||||
int mode_gpr0_disable = 0;
|
||||
char *region_type_string = NULL, *region_fname = NULL;
|
||||
const char *layout_fname = NULL;
|
||||
@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
|
||||
{"validate", 0, NULL, 't'},
|
||||
{"setpchstrap", 1, NULL, 'S'},
|
||||
{"newvalue", 1, NULL, 'V'},
|
||||
+ {"nuke", 1, NULL, 'N'},
|
||||
{0, 0, 0, 0}
|
||||
};
|
||||
|
||||
@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
|
||||
region_fname++;
|
||||
// Descriptor, BIOS, ME, GbE, Platform
|
||||
// valid type?
|
||||
- if (!strcasecmp("Descriptor", region_type_string))
|
||||
- region_type = 0;
|
||||
- else if (!strcasecmp("BIOS", region_type_string))
|
||||
- region_type = 1;
|
||||
- else if (!strcasecmp("ME", region_type_string))
|
||||
- region_type = 2;
|
||||
- else if (!strcasecmp("GbE", region_type_string))
|
||||
- region_type = 3;
|
||||
- else if (!strcasecmp("Platform Data", region_type_string))
|
||||
- region_type = 4;
|
||||
- else if (!strcasecmp("Device Exp1", region_type_string))
|
||||
- region_type = 5;
|
||||
- else if (!strcasecmp("Secondary BIOS", region_type_string))
|
||||
- region_type = 6;
|
||||
- else if (!strcasecmp("Reserved", region_type_string))
|
||||
- region_type = 7;
|
||||
- else if (!strcasecmp("EC", region_type_string))
|
||||
- region_type = 8;
|
||||
- else if (!strcasecmp("Device Exp2", region_type_string))
|
||||
- region_type = 9;
|
||||
- else if (!strcasecmp("IE", region_type_string))
|
||||
- region_type = 10;
|
||||
- else if (!strcasecmp("10GbE_0", region_type_string))
|
||||
- region_type = 11;
|
||||
- else if (!strcasecmp("10GbE_1", region_type_string))
|
||||
- region_type = 12;
|
||||
- else if (!strcasecmp("PTT", region_type_string))
|
||||
- region_type = 15;
|
||||
- if (region_type == -1) {
|
||||
+ if ((region_type =
|
||||
+ get_region_type_string(region_type_string)) == -1) {
|
||||
fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
region_type_string);
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
|
||||
case 't':
|
||||
mode_validate = 1;
|
||||
break;
|
||||
+ case 'N':
|
||||
+ region_type_string = strdup(optarg);
|
||||
+ if (!region_type_string) {
|
||||
+ fprintf(stderr, "No region specified\n");
|
||||
+ print_usage(argv[0]);
|
||||
+ exit(EXIT_FAILURE);
|
||||
+ }
|
||||
+ if ((region_type =
|
||||
+ get_region_type_string(region_type_string)) == -1) {
|
||||
+ fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
+ region_type_string);
|
||||
+ print_usage(argv[0]);
|
||||
+ exit(EXIT_FAILURE);
|
||||
+ }
|
||||
+ mode_nuke = 1;
|
||||
+ break;
|
||||
case 'v':
|
||||
print_version();
|
||||
exit(EXIT_SUCCESS);
|
||||
@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
|
||||
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
|
||||
- mode_gpr0_disable) > 1) {
|
||||
+ mode_gpr0_disable + mode_nuke) > 1) {
|
||||
fprintf(stderr, "You may not specify more than one mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
|
||||
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
|
||||
- mode_validate + mode_gpr0_disable) == 0) {
|
||||
+ mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
|
||||
fprintf(stderr, "You need to specify a mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
|
||||
write_image(new_filename, image, size);
|
||||
}
|
||||
|
||||
+ if (mode_nuke) {
|
||||
+ nuke(new_filename, image, size, region_type);
|
||||
+ }
|
||||
+
|
||||
if (mode_altmedisable) {
|
||||
struct fpsba *fpsba = find_fpsba(image, size);
|
||||
struct fmsba *fmsba = find_fmsba(image, size);
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Wed, 1 Dec 2021 02:53:00 +0000
|
||||
Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert
|
||||
"cpu/intel/model_1067x: enable PECI"
|
||||
|
||||
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
|
||||
|
||||
Enabling PECI without microcode updates loaded causes the CPUID feature set
|
||||
to become corrupted. And one consequence is broken SpeedStep. At least, that's
|
||||
my understanding looking at Intel Errata. This revert is not a fix, because
|
||||
upstream is correct (upstream assumes microcode updates). We will simply
|
||||
maintain this revert patch in Libreboot, from now on.
|
||||
---
|
||||
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
|
||||
1 file changed, 9 deletions(-)
|
||||
|
||||
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
index 315e7c36fc..1423fd72bc 100644
|
||||
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
|
||||
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
|
||||
}
|
||||
|
||||
-#define IA32_PECI_CTL 0x5a0
|
||||
-
|
||||
static void configure_misc(const int eist, const int tm2, const int emttm)
|
||||
{
|
||||
msr_t msr;
|
||||
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
|
||||
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
|
||||
wrmsr(IA32_MISC_ENABLE, msr);
|
||||
}
|
||||
-
|
||||
- /* Enable PECI
|
||||
- WARNING: due to Erratum AW67 described in Intel document #318733
|
||||
- the microcode must be updated before this MSR is written to. */
|
||||
- msr = rdmsr(IA32_PECI_CTL);
|
||||
- msr.lo |= 1;
|
||||
- wrmsr(IA32_PECI_CTL, msr);
|
||||
}
|
||||
|
||||
#define PIC_SENS_CFG 0x1aa
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+173
@@ -0,0 +1,173 @@
|
||||
From 8a94f38398b8fa554fa4ae53ecb88a372df634fd Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 17 Apr 2023 15:49:57 +0100
|
||||
Subject: [PATCH 17/30] GM45-type CPUs: don't enable alternative SMRR
|
||||
|
||||
This reverts the changes in coreboot revision:
|
||||
df7aecd92643d207feaf7fd840f8835097346644
|
||||
|
||||
While this fix is *technically correct*, the one in
|
||||
coreboot, it breaks rebooting as tested on several
|
||||
GM45 ThinkPads e.g. X200, T400, when microcode
|
||||
updates are not applied.
|
||||
|
||||
Since November 2022, Libreboot includes microcode
|
||||
updates by default, but it tells users how to remove
|
||||
it from the ROM (with cbfstool) if they wish.
|
||||
|
||||
Well, with Libreboot 20221214, 20230319 and 20230413,
|
||||
mitigations present in Libreboot 20220710 (which did
|
||||
not have microcode updates) do not exist.
|
||||
|
||||
This patch, along with the other patch to remove PECI
|
||||
support (which breaks speedstep when microcode updates
|
||||
are not applied) have now been re-added to Libreboot.
|
||||
|
||||
It is still best to use microcode updates by default.
|
||||
These patches in coreboot are not critically urgent,
|
||||
and you can use the machines with or without them,
|
||||
regardless of ucode.
|
||||
|
||||
I'll probably re-write this and the other patch at
|
||||
some point, applying the change conditionally upon
|
||||
whether or not microcode is applied.
|
||||
|
||||
Pragmatism is a good thing. I recommend it.
|
||||
---
|
||||
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
|
||||
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
|
||||
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
|
||||
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
|
||||
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
|
||||
5 files changed, 16 insertions(+), 26 deletions(-)
|
||||
|
||||
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
index 1423fd72bc..d1f98ca43a 100644
|
||||
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
@@ -8,6 +8,7 @@
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/name.h>
|
||||
#include <cpu/intel/smm_reloc.h>
|
||||
+#include <cpu/intel/common/common.h>
|
||||
|
||||
#define MSR_BBL_CR_CTL3 0x11e
|
||||
|
||||
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
|
||||
fill_processor_name(processor_name);
|
||||
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
|
||||
|
||||
+ /* Set virtualization based on Kconfig option */
|
||||
+ set_vmx_and_lock();
|
||||
+
|
||||
/* Configure C States */
|
||||
configure_c_states(quad);
|
||||
|
||||
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
|
||||
index bc53214310..72f40f6762 100644
|
||||
--- a/src/cpu/intel/model_1067x/mp_init.c
|
||||
+++ b/src/cpu/intel/model_1067x/mp_init.c
|
||||
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
|
||||
smm_initialize();
|
||||
}
|
||||
|
||||
-#define SMRR_SUPPORTED (1 << 11)
|
||||
-
|
||||
static void per_cpu_smm_trigger(void)
|
||||
{
|
||||
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
|
||||
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
|
||||
- set_feature_ctrl_vmx();
|
||||
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
|
||||
- /* We don't care if the lock is already setting
|
||||
- as our smm relocation handler is able to handle
|
||||
- setups where SMRR is not enabled here. */
|
||||
- if (ia32_ft_ctrl.lo & (1 << 0)) {
|
||||
- /* IA32_FEATURE_CONTROL locked. If we set it again we
|
||||
- get an illegal instruction. */
|
||||
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
|
||||
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
|
||||
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
|
||||
- } else {
|
||||
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
|
||||
- printk(BIOS_INFO,
|
||||
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
|
||||
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
|
||||
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
|
||||
- }
|
||||
- } else {
|
||||
- set_vmx_and_lock();
|
||||
- }
|
||||
-
|
||||
/* Relocate the SMM handler. */
|
||||
smm_relocate();
|
||||
}
|
||||
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
|
||||
index 05f5f327cc..0450c2ad83 100644
|
||||
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
|
||||
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <cpu/intel/speedstep.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/name.h>
|
||||
+#include <cpu/intel/common/common.h>
|
||||
|
||||
#define HIGHEST_CLEVEL 3
|
||||
static void configure_c_states(void)
|
||||
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
|
||||
fill_processor_name(processor_name);
|
||||
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
|
||||
|
||||
+ /* Set virtualization based on Kconfig option */
|
||||
+ set_vmx_and_lock();
|
||||
+
|
||||
/* Configure C States */
|
||||
configure_c_states();
|
||||
|
||||
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
|
||||
index 5bd1c32815..f3bb08cde3 100644
|
||||
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
|
||||
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <cpu/intel/speedstep.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/name.h>
|
||||
+#include <cpu/intel/common/common.h>
|
||||
|
||||
#define HIGHEST_CLEVEL 3
|
||||
static void configure_c_states(void)
|
||||
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
|
||||
/* Setup Page Attribute Tables (PAT) */
|
||||
// TODO set up PAT
|
||||
|
||||
+ /* Set virtualization based on Kconfig option */
|
||||
+ set_vmx_and_lock();
|
||||
+
|
||||
/* Configure C States */
|
||||
configure_c_states();
|
||||
|
||||
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
|
||||
index 535fb8fae7..f7b05facd2 100644
|
||||
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
|
||||
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <cpu/intel/speedstep.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/name.h>
|
||||
+#include <cpu/intel/common/common.h>
|
||||
|
||||
#define HIGHEST_CLEVEL 3
|
||||
static void configure_c_states(void)
|
||||
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
|
||||
/* Setup Page Attribute Tables (PAT) */
|
||||
// TODO set up PAT
|
||||
|
||||
+ /* Set virtualization based on Kconfig option */
|
||||
+ set_vmx_and_lock();
|
||||
+
|
||||
/* Configure C States */
|
||||
configure_c_states();
|
||||
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+28
@@ -0,0 +1,28 @@
|
||||
From 2b899f40ce5d728faa7c1da23c3348435b7ac9cb Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sat, 6 May 2023 15:53:41 -0600
|
||||
Subject: [PATCH 18/30] mb/dell/e6400: Enable 01.0 device in devicetree for
|
||||
dGPU models
|
||||
|
||||
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/e6400/devicetree.cb | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
|
||||
index bb954cbd7b..e9f3915d17 100644
|
||||
--- a/src/mainboard/dell/e6400/devicetree.cb
|
||||
+++ b/src/mainboard/dell/e6400/devicetree.cb
|
||||
@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
|
||||
ops gm45_pci_domain_ops
|
||||
|
||||
device pci 00.0 on end # host bridge
|
||||
- device pci 01.0 off end
|
||||
+ device pci 01.0 on end
|
||||
device pci 02.0 on end # VGA
|
||||
device pci 02.1 on end # Display
|
||||
device pci 03.0 on end # ME
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
From 2ccd3e71730004c3ffbed178087cb778c170079e Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Fri, 12 May 2023 19:55:15 -0600
|
||||
Subject: [PATCH 19/30] Remove warning for coreboot images built without a
|
||||
payload
|
||||
|
||||
I added this in upstream to prevent people from accidentally flashing
|
||||
roms without a payload resulting in a no boot situation, but in
|
||||
libreboot lbmk handles the payload and thus this warning always comes
|
||||
up. This has caused confusion and concern so just patch it out.
|
||||
---
|
||||
payloads/Makefile.mk | 13 +------------
|
||||
1 file changed, 1 insertion(+), 12 deletions(-)
|
||||
|
||||
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
|
||||
index a2336aa876..4f1692a873 100644
|
||||
--- a/payloads/Makefile.mk
|
||||
+++ b/payloads/Makefile.mk
|
||||
@@ -49,16 +49,5 @@ distclean-payloads:
|
||||
print-repo-info-payloads:
|
||||
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
|
||||
|
||||
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
|
||||
-show_notices:: warn_no_payload
|
||||
-endif
|
||||
-
|
||||
-warn_no_payload:
|
||||
- printf "\n\t** WARNING **\n"
|
||||
- printf "coreboot has been built without a payload. Writing\n"
|
||||
- printf "a coreboot image without a payload to your board's\n"
|
||||
- printf "flash chip will result in a non-booting system. You\n"
|
||||
- printf "can use cbfstool to add a payload to the image.\n\n"
|
||||
-
|
||||
.PHONY: force-payload coreinfo nvramcui
|
||||
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
|
||||
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,826 @@
|
||||
From a49df0307455d6d8b7a9efb9f4639b72be1b64d4 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sat, 19 Aug 2023 16:19:10 -0600
|
||||
Subject: [PATCH 20/30] mb/dell: Add Latitude E6430 (Ivy Bridge)
|
||||
|
||||
Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. This
|
||||
is based on the autoport output with some manual tweaks. The flash is
|
||||
8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. It
|
||||
can also be internally flashed by sending a command to the EC, which
|
||||
causes the EC to pull the FDO pin low and the firmware to skip setting
|
||||
up any chipset based write protections [1]. The EC is the SMSC MEC5055,
|
||||
which seems to be compatible with the existing MEC5035 code.
|
||||
|
||||
Working:
|
||||
- Libgfxinit
|
||||
- USB EHCI debug (left side usb port is HCD index 2, middle port on the
|
||||
right side is HCD index 1)
|
||||
- Keyboard
|
||||
- Touchpad/trackpoint
|
||||
- ExpressCard
|
||||
- Audio
|
||||
- Ethernet
|
||||
- SD card reader
|
||||
- mPCIe WiFi
|
||||
- SeaBIOS 1.16.2
|
||||
- edk2 (MrChromebox' fork, uefipayload_202306)
|
||||
- Internal flashing using dell-flash-unlock
|
||||
|
||||
Not working:
|
||||
- S3 suspend: Possibly EC related
|
||||
- Physical wireless switch - this triggers an SMI handler in the vendor
|
||||
firmware which sends commands to the EC to enable/disable wireless
|
||||
devices
|
||||
- Battery reporting - needs ACPI code for the EC
|
||||
- Brightness hotkeys - probably EC related
|
||||
|
||||
Unknown/untested:
|
||||
- Dock
|
||||
- eSATA
|
||||
- TPM
|
||||
- dGPU on non-UMA model
|
||||
- Bluetooth module (not included on my system)
|
||||
|
||||
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
|
||||
|
||||
Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/e6430/Kconfig | 44 +++++
|
||||
src/mainboard/dell/e6430/Kconfig.name | 2 +
|
||||
src/mainboard/dell/e6430/Makefile.inc | 6 +
|
||||
src/mainboard/dell/e6430/acpi/ec.asl | 9 +
|
||||
src/mainboard/dell/e6430/acpi/platform.asl | 12 ++
|
||||
src/mainboard/dell/e6430/acpi/superio.asl | 3 +
|
||||
src/mainboard/dell/e6430/acpi_tables.c | 16 ++
|
||||
src/mainboard/dell/e6430/board_info.txt | 6 +
|
||||
src/mainboard/dell/e6430/cmos.default | 9 +
|
||||
src/mainboard/dell/e6430/cmos.layout | 88 ++++++++++
|
||||
src/mainboard/dell/e6430/data.vbt | Bin 0 -> 6144 bytes
|
||||
src/mainboard/dell/e6430/devicetree.cb | 70 ++++++++
|
||||
src/mainboard/dell/e6430/dsdt.asl | 30 ++++
|
||||
src/mainboard/dell/e6430/early_init.c | 32 ++++
|
||||
src/mainboard/dell/e6430/gma-mainboard.ads | 20 +++
|
||||
src/mainboard/dell/e6430/gpio.c | 192 +++++++++++++++++++++
|
||||
src/mainboard/dell/e6430/hda_verb.c | 33 ++++
|
||||
src/mainboard/dell/e6430/mainboard.c | 21 +++
|
||||
18 files changed, 593 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/e6430/Kconfig
|
||||
create mode 100644 src/mainboard/dell/e6430/Kconfig.name
|
||||
create mode 100644 src/mainboard/dell/e6430/Makefile.inc
|
||||
create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl
|
||||
create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/dell/e6430/acpi_tables.c
|
||||
create mode 100644 src/mainboard/dell/e6430/board_info.txt
|
||||
create mode 100644 src/mainboard/dell/e6430/cmos.default
|
||||
create mode 100644 src/mainboard/dell/e6430/cmos.layout
|
||||
create mode 100644 src/mainboard/dell/e6430/data.vbt
|
||||
create mode 100644 src/mainboard/dell/e6430/devicetree.cb
|
||||
create mode 100644 src/mainboard/dell/e6430/dsdt.asl
|
||||
create mode 100644 src/mainboard/dell/e6430/early_init.c
|
||||
create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/e6430/gpio.c
|
||||
create mode 100644 src/mainboard/dell/e6430/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/e6430/mainboard.c
|
||||
|
||||
diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..e4c799803e
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/Kconfig
|
||||
@@ -0,0 +1,44 @@
|
||||
+if BOARD_DELL_LATITUDE_E6430
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS
|
||||
+ def_bool y
|
||||
+ select BOARD_ROMSIZE_KB_12288
|
||||
+ select EC_ACPI
|
||||
+ select EC_DELL_MEC5035
|
||||
+ select GFX_GMA_PANEL_1_ON_LVDS
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select INTEL_INT15
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select MAINBOARD_USES_IFD_GBE_REGION
|
||||
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
|
||||
+ select SERIRQ_CONTINUOUS_MODE
|
||||
+ select SOUTHBRIDGE_INTEL_C216
|
||||
+ select SYSTEM_TYPE_LAPTOP
|
||||
+ select USE_NATIVE_RAMINIT
|
||||
+
|
||||
+config DRAM_RESET_GATE_GPIO
|
||||
+ default 60
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "dell/e6430"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "Latitude E6430"
|
||||
+
|
||||
+config PS2K_EISAID
|
||||
+ default "PNP0303"
|
||||
+
|
||||
+config PS2M_EISAID
|
||||
+ default "PNP0F13"
|
||||
+
|
||||
+config USBDEBUG_HCD_INDEX
|
||||
+ default 2
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,0166"
|
||||
+
|
||||
+endif
|
||||
diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..f866b03585
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/Kconfig.name
|
||||
@@ -0,0 +1,2 @@
|
||||
+config BOARD_DELL_LATITUDE_E6430
|
||||
+ bool "Latitude E6430"
|
||||
diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc
|
||||
new file mode 100644
|
||||
index 0000000000..ba64e93eb8
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/Makefile.inc
|
||||
@@ -0,0 +1,6 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only
|
||||
+bootblock-y += early_init.c
|
||||
+bootblock-y += gpio.c
|
||||
+romstage-y += early_init.c
|
||||
+romstage-y += gpio.c
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..0d429410a9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/acpi/ec.asl
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Device(EC)
|
||||
+{
|
||||
+ Name (_HID, EISAID("PNP0C09"))
|
||||
+ Name (_UID, 0)
|
||||
+ Name (_GPE, 16)
|
||||
+/* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl
|
||||
new file mode 100644
|
||||
index 0000000000..2d24bbd9b9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/acpi/platform.asl
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Method(_WAK, 1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+ Return(Package() {0, 0})
|
||||
+}
|
||||
+
|
||||
+Method(_PTS,1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..55b1db5b11
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/acpi/superio.asl
|
||||
@@ -0,0 +1,3 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c
|
||||
new file mode 100644
|
||||
index 0000000000..e2759659bf
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/acpi_tables.c
|
||||
@@ -0,0 +1,16 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi_gnvs.h>
|
||||
+#include <soc/nvs.h>
|
||||
+
|
||||
+/* FIXME: check this function. */
|
||||
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
|
||||
+{
|
||||
+ /* The lid is open by default. */
|
||||
+ gnvs->lids = 1;
|
||||
+
|
||||
+ /* Temperature at which OS will shutdown */
|
||||
+ gnvs->tcrt = 100;
|
||||
+ /* Temperature at which OS will throttle CPU */
|
||||
+ gnvs->tpsv = 90;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..4601a4aaba
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/board_info.txt
|
||||
@@ -0,0 +1,6 @@
|
||||
+Category: laptop
|
||||
+ROM package: SOIC-8
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
+Release year: 2012
|
||||
diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..2a5b30f2b7
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/cmos.default
|
||||
@@ -0,0 +1,9 @@
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Disable
|
||||
+nmi=Enable
|
||||
+bluetooth=Enable
|
||||
+wwan=Enable
|
||||
+wlan=Enable
|
||||
+sata_mode=AHCI
|
||||
+me_state=Normal
|
||||
diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..1aa7e77bce
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/cmos.layout
|
||||
@@ -0,0 +1,88 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+
|
||||
+#400 8 r 0 reserved for century byte
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 1 nmi
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+411 1 e 9 sata_mode
|
||||
+
|
||||
+# coreboot config options: EC
|
||||
+412 1 e 1 bluetooth
|
||||
+413 1 e 1 wwan
|
||||
+414 1 e 1 wlan
|
||||
+
|
||||
+# coreboot config options: ME
|
||||
+424 1 e 14 me_state
|
||||
+425 2 h 0 me_state_prev
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 3 e 11 gfx_uma_size
|
||||
+435 2 e 12 hybrid_graphics_mode
|
||||
+440 8 h 0 volume
|
||||
+
|
||||
+# VBOOT
|
||||
+448 128 r 0 vbnv
|
||||
+
|
||||
+# SandyBridge MRC Scrambler Seed values
|
||||
+896 32 r 0 mrc_scrambler_seed
|
||||
+928 32 r 0 mrc_scrambler_seed_s3
|
||||
+960 16 r 0 mrc_scrambler_seed_chk
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+9 0 AHCI
|
||||
+9 1 Compatible
|
||||
+11 0 32M
|
||||
+11 1 64M
|
||||
+11 2 96M
|
||||
+11 3 128M
|
||||
+11 4 160M
|
||||
+11 5 192M
|
||||
+11 6 224M
|
||||
+14 0 Normal
|
||||
+14 1 Disabled
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 447 984
|
||||
diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d
|
||||
GIT binary patch
|
||||
literal 6144
|
||||
zcmeHKU2Gdw7XHRFw#VZc+nI!tq)j-qG$b@>#vu)%WW~fb!7ZV6LkJc^+qlG~(WXgp
|
||||
zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;)
|
||||
zjkMh#DR=zcpL5Use9xJ4?#x^=mKdcQb|t!Zj3v6R-<{Yod<{*&!ppI%xUMXT9lLMX
|
||||
zn;IM)+?yEQoxF~o#5x>}{dfwPkR;RSiC=!jj_JAlRQpJWpd}$VY+XtFX9|?cO&y#m
|
||||
z<SE`uGt*OdcG7S%MVsQ5GkI`wn)VeYZ#ytIou8d0Yb)J)AUAzmo)Vpuq&7;?RQ_;&
|
||||
zie?W??w`vSW@&DQ`Yr3=;cjcIHNi^L`QOvN$?05SGCy0nZ	>IdrG<AJm@gpdQPz
|
||||
zx_Yd5oSZFFa;9)-D-BLf(TLc`ERE!6^M%9tiLHiaXuwHXRU|<2BX~C?>4zSq6a*B6
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
z{ct?ZJ!#R&H|_;QGyr;2JDTu4Urkt)#LW}e65l@e>g0GR_nHOE`gieuP-A>69j*W0
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
ztg|e-5!;@t?uT+rR=1)e9yp?8gwNW88`Zyt!8rx=+B{i(4~DY`_-WO>sGeD;nsGcs
|
||||
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|
||||
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|
||||
z`Qth}G~%sFr{ZEKZb_%aySrD?sV%fJw`vFfda&ho1a>X)H^I}D_0A<|*{8kwEBU8>
|
||||
qS<b6g={WLAp3+&R^8(yo-t$_!=7BX2ta)I~18W{w^T5By1OEis_@J`@
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..054b01c5ac
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/devicetree.cb
|
||||
@@ -0,0 +1,70 @@
|
||||
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
|
||||
+ register "gpu_cpu_backlight" = "0x00001312"
|
||||
+ register "gpu_dp_b_hotplug" = "4"
|
||||
+ register "gpu_dp_c_hotplug" = "4"
|
||||
+ register "gpu_dp_d_hotplug" = "4"
|
||||
+ register "gpu_panel_port_select" = "0"
|
||||
+ register "gpu_panel_power_backlight_off_delay" = "2300"
|
||||
+ register "gpu_panel_power_backlight_on_delay" = "2300"
|
||||
+ register "gpu_panel_power_cycle_delay" = "6"
|
||||
+ register "gpu_panel_power_down_delay" = "400"
|
||||
+ register "gpu_panel_power_up_delay" = "400"
|
||||
+ register "gpu_pch_backlight" = "0x13121312"
|
||||
+
|
||||
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
|
||||
+
|
||||
+ device domain 0x0 on
|
||||
+ subsystemid 0x1028 0x0534 inherit
|
||||
+
|
||||
+ device ref host_bridge on end
|
||||
+ device ref peg10 off end
|
||||
+ device ref igd on end
|
||||
+
|
||||
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
+ register "docking_supported" = "1"
|
||||
+ register "gen1_dec" = "0x007c0681"
|
||||
+ register "gen2_dec" = "0x005c0921"
|
||||
+ register "gen3_dec" = "0x003c07e1"
|
||||
+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
|
||||
+ register "gpi0_routing" = "2"
|
||||
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
|
||||
+ register "pcie_port_coalesce" = "1"
|
||||
+ register "sata_interface_speed_support" = "0x3"
|
||||
+ register "sata_port_map" = "0x33"
|
||||
+ register "spi_lvscc" = "0x2005"
|
||||
+ register "spi_uvscc" = "0x2005"
|
||||
+ register "superspeed_capable_ports" = "0x0000000f"
|
||||
+ register "xhci_overcurrent_mapping" = "0x00000c03"
|
||||
+ register "xhci_switchable_ports" = "0x0000000f"
|
||||
+
|
||||
+ device ref xhci on end
|
||||
+ device ref mei1 on end
|
||||
+ device ref mei2 off end
|
||||
+ device ref me_ide_r off end
|
||||
+ device ref me_kt on end
|
||||
+ device ref gbe on end
|
||||
+ device ref ehci2 on end
|
||||
+ device ref hda on end
|
||||
+ device ref pcie_rp1 on end # WWAN Slot
|
||||
+ device ref pcie_rp2 on end # SLAN Slot
|
||||
+ device ref pcie_rp3 on end # ExpressCard
|
||||
+ device ref pcie_rp4 on end # E-Module (optical bay)
|
||||
+ device ref pcie_rp5 on end # Extra Half Mini PCIe slot
|
||||
+ device ref pcie_rp6 on end # SD/MMC Card Reader
|
||||
+ device ref pcie_rp7 off end
|
||||
+ device ref pcie_rp8 off end
|
||||
+ device ref ehci1 on end
|
||||
+ device ref pci_bridge off end
|
||||
+ device ref lpc on
|
||||
+ chip ec/dell/mec5035
|
||||
+ device pnp ff.0 on end
|
||||
+ end
|
||||
+ end
|
||||
+ device ref sata1 on end
|
||||
+ device ref smbus on end
|
||||
+ device ref sata2 off end
|
||||
+ device ref thermal off end
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/e6430/dsdt.asl b/src/mainboard/dell/e6430/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..7d13c55b08
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/dsdt.asl
|
||||
@@ -0,0 +1,30 @@
|
||||
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20141018 /* OEM revision */
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+ #include "acpi/platform.asl"
|
||||
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..d882c3d78b
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/early_init.c
|
||||
@@ -0,0 +1,32 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <bootblock_common.h>
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <ec/dell/mec5035/mec5035.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 0, 2 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 1, 3 },
|
||||
+ { 1, 1, 3 },
|
||||
+ { 1, 1, 4 },
|
||||
+ { 1, 1, 4 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 2, 6 },
|
||||
+ { 1, 2, 6 },
|
||||
+};
|
||||
+
|
||||
+void bootblock_mainboard_early_init(void)
|
||||
+{
|
||||
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
|
||||
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
|
||||
+ | COMB_LPC_EN | COMA_LPC_EN);
|
||||
+ mec5035_early_init();
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..1310830c8e
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/gma-mainboard.ads
|
||||
@@ -0,0 +1,20 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (
|
||||
+ HDMI1, -- mainboard HDMI
|
||||
+ DP2, -- dock DP
|
||||
+ DP3, -- dock DP
|
||||
+ Analog, --mainboard VGA
|
||||
+ LVDS,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..777570765a
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/gpio.c
|
||||
@@ -0,0 +1,192 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_GPIO,
|
||||
+ .gpio1 = GPIO_MODE_GPIO,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_GPIO,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_NATIVE,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_GPIO,
|
||||
+ .gpio16 = GPIO_MODE_GPIO,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_NATIVE,
|
||||
+ .gpio31 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio0 = GPIO_DIR_INPUT,
|
||||
+ .gpio1 = GPIO_DIR_INPUT,
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio3 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio15 = GPIO_DIR_INPUT,
|
||||
+ .gpio16 = GPIO_DIR_INPUT,
|
||||
+ .gpio17 = GPIO_DIR_INPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio29 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio28 = GPIO_LEVEL_LOW,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
+ .gpio30 = GPIO_RESET_RSMRST,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio0 = GPIO_INVERT,
|
||||
+ .gpio8 = GPIO_INVERT,
|
||||
+ .gpio13 = GPIO_INVERT,
|
||||
+ .gpio14 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_NATIVE,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_GPIO,
|
||||
+ .gpio46 = GPIO_MODE_NATIVE,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_GPIO,
|
||||
+ .gpio52 = GPIO_MODE_GPIO,
|
||||
+ .gpio53 = GPIO_MODE_NATIVE,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_NATIVE,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio35 = GPIO_DIR_INPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio45 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_INPUT,
|
||||
+ .gpio51 = GPIO_DIR_INPUT,
|
||||
+ .gpio52 = GPIO_DIR_INPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio34 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio45 = GPIO_LEVEL_LOW,
|
||||
+ .gpio60 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_GPIO,
|
||||
+ .gpio69 = GPIO_MODE_GPIO,
|
||||
+ .gpio70 = GPIO_MODE_GPIO,
|
||||
+ .gpio71 = GPIO_MODE_GPIO,
|
||||
+ .gpio72 = GPIO_MODE_NATIVE,
|
||||
+ .gpio73 = GPIO_MODE_NATIVE,
|
||||
+ .gpio74 = GPIO_MODE_NATIVE,
|
||||
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio68 = GPIO_DIR_INPUT,
|
||||
+ .gpio69 = GPIO_DIR_INPUT,
|
||||
+ .gpio70 = GPIO_DIR_INPUT,
|
||||
+ .gpio71 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ .reset = &pch_gpio_set1_reset,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ .reset = &pch_gpio_set2_reset,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ .reset = &pch_gpio_set3_reset,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..56ada95c58
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/hda_verb.c
|
||||
@@ -0,0 +1,33 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
|
||||
+ 0x10280534, /* Subsystem ID */
|
||||
+ 11, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(0, 0x10280534),
|
||||
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
|
||||
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
|
||||
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
||||
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
||||
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
||||
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
|
||||
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
|
||||
+
|
||||
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
+ 0x80860101, /* Subsystem ID */
|
||||
+ 4, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
+
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c
|
||||
new file mode 100644
|
||||
index 0000000000..31e49802fc
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6430/mainboard.c
|
||||
@@ -0,0 +1,21 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/device.h>
|
||||
+#include <drivers/intel/gma/int15.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+#include <ec/acpi/ec.h>
|
||||
+#include <console/console.h>
|
||||
+#include <pc80/keyboard.h>
|
||||
+
|
||||
+static void mainboard_enable(struct device *dev)
|
||||
+{
|
||||
+
|
||||
+ /* FIXME: fix these values. */
|
||||
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
+}
|
||||
+
|
||||
+struct chip_operations mainboard_ops = {
|
||||
+ .enable_dev = mainboard_enable,
|
||||
+};
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+28
@@ -0,0 +1,28 @@
|
||||
From 70262a5f4bf801814d68f8778ea89b5cd8ef8f9a Mon Sep 17 00:00:00 2001
|
||||
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
|
||||
Date: Thu, 22 Jun 2023 16:44:27 +0300
|
||||
Subject: [PATCH 21/30] HACK: Disable coreboot related BL31 features
|
||||
|
||||
I don't know why, but removing this BL31 make argument lets gru-kevin
|
||||
power off properly when shut down from Linux. Needs investigation.
|
||||
---
|
||||
src/arch/arm64/Makefile.mk | 3 ---
|
||||
1 file changed, 3 deletions(-)
|
||||
|
||||
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
|
||||
index 538d254ace..18e451d63c 100644
|
||||
--- a/src/arch/arm64/Makefile.mk
|
||||
+++ b/src/arch/arm64/Makefile.mk
|
||||
@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
|
||||
# Always enable crash reporting, even on a release build
|
||||
BL31_MAKEARGS += CRASH_REPORTING=1
|
||||
|
||||
-# Enable coreboot-specific features like CBMEM console support
|
||||
-BL31_MAKEARGS += COREBOOT=1
|
||||
-
|
||||
# Avoid build/release|build/debug distinction by overriding BUILD_PLAT directly
|
||||
BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
|
||||
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
From 536a1dd349f590cbefccac7e7364cafcdaec9600 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 22 Oct 2023 15:02:25 +0100
|
||||
Subject: [PATCH 22/30] don't use github for the acpica download
|
||||
|
||||
i have the tarball from a previous download, and i placed
|
||||
it on libreboot rsync, which then got mirrored to princeton.
|
||||
|
||||
today, github's ssl cert was b0rking the hell out and i really
|
||||
really wanted to finish a build, and didn't want to wait for
|
||||
github to fix their httpd.
|
||||
|
||||
so i'm now hosting this specific acpica tarball on rsync.
|
||||
|
||||
this patch makes that URL be used, instead of the github one.
|
||||
|
||||
that's the 2nd time i've had to patch coreboot's acpica download!
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/crossgcc/buildgcc | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
|
||||
index 23a5caf2bb..36565a906c 100755
|
||||
--- a/util/crossgcc/buildgcc
|
||||
+++ b/util/crossgcc/buildgcc
|
||||
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
|
||||
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
|
||||
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
|
||||
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
|
||||
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
|
||||
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
|
||||
# CLANG toolchain archive locations
|
||||
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
|
||||
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+142
@@ -0,0 +1,142 @@
|
||||
From ad812d008d570c1655bff13a9026f39a9efdcbc9 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Tue, 31 Oct 2023 18:24:39 +0000
|
||||
Subject: [PATCH 23/30] crank up vram allocation on more intel boards
|
||||
|
||||
these were added to libreboot, and it's a policy of
|
||||
libreboot to max out the vram settings. this was
|
||||
overlooked, in prior revisions and releases.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/dell/e6400/cmos.default | 2 +-
|
||||
src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
|
||||
src/mainboard/hp/compaq_8200_elite_sff/cmos.default | 2 +-
|
||||
src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
|
||||
src/mainboard/hp/snb_ivb_laptops/cmos.default | 1 +
|
||||
src/mainboard/lenovo/t420/cmos.default | 1 +
|
||||
src/mainboard/lenovo/t420s/cmos.default | 1 +
|
||||
src/mainboard/lenovo/t430/cmos.default | 1 +
|
||||
src/mainboard/lenovo/t520/cmos.default | 1 +
|
||||
src/mainboard/lenovo/t530/cmos.default | 1 +
|
||||
src/mainboard/lenovo/x201/cmos.default | 1 +
|
||||
src/mainboard/lenovo/x220/cmos.default | 1 +
|
||||
12 files changed, 12 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
|
||||
index eeb6f47364..25dfa38cb5 100644
|
||||
--- a/src/mainboard/dell/e6400/cmos.default
|
||||
+++ b/src/mainboard/dell/e6400/cmos.default
|
||||
@@ -2,4 +2,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
power_on_after_fail=Disable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=32M
|
||||
+gfx_uma_size=256M
|
||||
diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
|
||||
index ccc7e64625..7c97b84baf 100644
|
||||
--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
|
||||
+++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
|
||||
@@ -3,5 +3,5 @@ debug_level=Debug
|
||||
power_on_after_fail=Disable
|
||||
nmi=Enable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=128M
|
||||
+gfx_uma_size=224M
|
||||
fan_full_speed=Disable
|
||||
diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
|
||||
index 6d27a79c66..4517ffc7c2 100644
|
||||
--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
|
||||
+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
|
||||
@@ -3,5 +3,5 @@ debug_level=Debug
|
||||
power_on_after_fail=Enable
|
||||
nmi=Enable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=32M
|
||||
+gfx_uma_size=224M
|
||||
psu_fan_lvl=3
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
|
||||
index 6f3cec735e..9fc4db2990 100644
|
||||
--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
|
||||
@@ -3,4 +3,4 @@ debug_level=Debug
|
||||
power_on_after_fail=Enable
|
||||
nmi=Enable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=32M
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
|
||||
index ad822d5043..89418a4cfc 100644
|
||||
--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
|
||||
+++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
|
||||
@@ -3,3 +3,4 @@ debug_level=Debug
|
||||
power_on_after_fail=Disable
|
||||
nmi=Enable
|
||||
sata_mode=AHCI
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
|
||||
index c011867916..83f590d39d 100644
|
||||
--- a/src/mainboard/lenovo/t420/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t420/cmos.default
|
||||
@@ -15,3 +15,4 @@ trackpoint=Enable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
|
||||
index c011867916..83f590d39d 100644
|
||||
--- a/src/mainboard/lenovo/t420s/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t420s/cmos.default
|
||||
@@ -15,3 +15,4 @@ trackpoint=Enable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
|
||||
index 55e1e6c04e..a72108f47e 100644
|
||||
--- a/src/mainboard/lenovo/t430/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t430/cmos.default
|
||||
@@ -16,3 +16,4 @@ backlight=Both
|
||||
usb_always_on=Disable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
|
||||
index b66f7034dc..a73ea6e9ee 100644
|
||||
--- a/src/mainboard/lenovo/t520/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t520/cmos.default
|
||||
@@ -16,3 +16,4 @@ backlight=Both
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
|
||||
index b66f7034dc..a73ea6e9ee 100644
|
||||
--- a/src/mainboard/lenovo/t530/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t530/cmos.default
|
||||
@@ -16,3 +16,4 @@ backlight=Both
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
|
||||
index 2cf484fd5a..46294d91ca 100644
|
||||
--- a/src/mainboard/lenovo/x201/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x201/cmos.default
|
||||
@@ -15,3 +15,4 @@ power_management_beeps=Enable
|
||||
low_battery_beep=Enable
|
||||
sata_mode=AHCI
|
||||
usb_always_on=Disable
|
||||
+gfx_uma_size=128M
|
||||
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
|
||||
index 52f303dfdb..92a2026542 100644
|
||||
--- a/src/mainboard/lenovo/x220/cmos.default
|
||||
+++ b/src/mainboard/lenovo/x220/cmos.default
|
||||
@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable
|
||||
sticky_fn=Disable
|
||||
trackpoint=Enable
|
||||
me_state=Disabled
|
||||
+gfx_uma_size=224M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,30 @@
|
||||
From a9ab864aee1be7a03926443ddc94e4c5012719ba Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 5 Nov 2023 11:41:41 +0000
|
||||
Subject: [PATCH 24/30] dell/e6430: use ME Soft Temporary Disable
|
||||
|
||||
i overlooked this. it's set on other boards.
|
||||
|
||||
we use me_cleaner anyway, and we set the hap bit, but
|
||||
this additional setting takes effect even if the ME
|
||||
region is unaltered. it's just another layer of
|
||||
disablement, to absolutely ensure Intel ME is not alive
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/dell/e6430/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
|
||||
index 2a5b30f2b7..279415dfd1 100644
|
||||
--- a/src/mainboard/dell/e6430/cmos.default
|
||||
+++ b/src/mainboard/dell/e6430/cmos.default
|
||||
@@ -6,4 +6,4 @@ bluetooth=Enable
|
||||
wwan=Enable
|
||||
wlan=Enable
|
||||
sata_mode=AHCI
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
From 936a8f113772c93d7501e7133159ab4e23436222 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 5 Nov 2023 22:57:08 +0000
|
||||
Subject: [PATCH 25/30] use mirrorservice.org for gcc downloads
|
||||
|
||||
the gnu.org 302 redirect often fails
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/crossgcc/buildgcc | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
|
||||
index 36565a906c..4d4ca06113 100755
|
||||
--- a/util/crossgcc/buildgcc
|
||||
+++ b/util/crossgcc/buildgcc
|
||||
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
|
||||
# to the jenkins build as well, or the builder won't download it.
|
||||
|
||||
# GCC toolchain archive locations
|
||||
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
|
||||
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
|
||||
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
|
||||
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
|
||||
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
|
||||
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
|
||||
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
|
||||
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
|
||||
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
|
||||
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
|
||||
IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
|
||||
# CLANG toolchain archive locations
|
||||
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,792 @@
|
||||
From 973783a989cdcb7b77029e369156c81eefe8cc67 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sat, 19 Aug 2023 16:19:10 -0600
|
||||
Subject: [PATCH 26/30] mb/dell: Add Latitude E6530 (Ivy Bridge)
|
||||
|
||||
Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested. This
|
||||
is based on the autoport output with some manual tweaks. The flash is
|
||||
8MiB + 4MiB. It can be internally flashed by sending a command to the
|
||||
EC, which causes the EC to pull the FDO pin low and the firmware to skip
|
||||
setting up any chipset based write protections. [1] The EC is the SMSC
|
||||
MEC5055, which seems to be compatible with the existing MEC5035 code.
|
||||
|
||||
[1] https://gitlab.com/nic3-14159/dell-flash-unlock
|
||||
|
||||
Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/e6530/Kconfig | 37 ++++
|
||||
src/mainboard/dell/e6530/Kconfig.name | 2 +
|
||||
src/mainboard/dell/e6530/Makefile.inc | 6 +
|
||||
src/mainboard/dell/e6530/acpi/ec.asl | 9 +
|
||||
src/mainboard/dell/e6530/acpi/platform.asl | 12 ++
|
||||
src/mainboard/dell/e6530/acpi/superio.asl | 3 +
|
||||
src/mainboard/dell/e6530/acpi_tables.c | 16 ++
|
||||
src/mainboard/dell/e6530/board_info.txt | 6 +
|
||||
src/mainboard/dell/e6530/cmos.default | 9 +
|
||||
src/mainboard/dell/e6530/cmos.layout | 88 ++++++++++
|
||||
src/mainboard/dell/e6530/data.vbt | Bin 0 -> 4280 bytes
|
||||
src/mainboard/dell/e6530/devicetree.cb | 68 ++++++++
|
||||
src/mainboard/dell/e6530/dsdt.asl | 30 ++++
|
||||
src/mainboard/dell/e6530/early_init.c | 38 ++++
|
||||
src/mainboard/dell/e6530/gma-mainboard.ads | 20 +++
|
||||
src/mainboard/dell/e6530/gpio.c | 192 +++++++++++++++++++++
|
||||
src/mainboard/dell/e6530/hda_verb.c | 33 ++++
|
||||
src/mainboard/dell/e6530/mainboard.c | 21 +++
|
||||
18 files changed, 590 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/e6530/Kconfig
|
||||
create mode 100644 src/mainboard/dell/e6530/Kconfig.name
|
||||
create mode 100644 src/mainboard/dell/e6530/Makefile.inc
|
||||
create mode 100644 src/mainboard/dell/e6530/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/dell/e6530/acpi/platform.asl
|
||||
create mode 100644 src/mainboard/dell/e6530/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/dell/e6530/acpi_tables.c
|
||||
create mode 100644 src/mainboard/dell/e6530/board_info.txt
|
||||
create mode 100644 src/mainboard/dell/e6530/cmos.default
|
||||
create mode 100644 src/mainboard/dell/e6530/cmos.layout
|
||||
create mode 100644 src/mainboard/dell/e6530/data.vbt
|
||||
create mode 100644 src/mainboard/dell/e6530/devicetree.cb
|
||||
create mode 100644 src/mainboard/dell/e6530/dsdt.asl
|
||||
create mode 100644 src/mainboard/dell/e6530/early_init.c
|
||||
create mode 100644 src/mainboard/dell/e6530/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/e6530/gpio.c
|
||||
create mode 100644 src/mainboard/dell/e6530/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/e6530/mainboard.c
|
||||
|
||||
diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..582adddbd4
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/Kconfig
|
||||
@@ -0,0 +1,37 @@
|
||||
+if BOARD_DELL_LATITUDE_E6530
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS
|
||||
+ def_bool y
|
||||
+ select BOARD_ROMSIZE_KB_12288
|
||||
+ select EC_ACPI
|
||||
+ select EC_DELL_MEC5035
|
||||
+ select GFX_GMA_PANEL_1_ON_LVDS
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select INTEL_INT15
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select MAINBOARD_USES_IFD_GBE_REGION
|
||||
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
|
||||
+ select SERIRQ_CONTINUOUS_MODE
|
||||
+ select SOUTHBRIDGE_INTEL_C216
|
||||
+ select SYSTEM_TYPE_LAPTOP
|
||||
+ select USE_NATIVE_RAMINIT
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "dell/e6530"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "Latitude E6530"
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,0166"
|
||||
+
|
||||
+config DRAM_RESET_GATE_GPIO
|
||||
+ default 60
|
||||
+
|
||||
+config USBDEBUG_HCD_INDEX
|
||||
+ default 2
|
||||
+endif
|
||||
diff --git a/src/mainboard/dell/e6530/Kconfig.name b/src/mainboard/dell/e6530/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..01ed76d107
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/Kconfig.name
|
||||
@@ -0,0 +1,2 @@
|
||||
+config BOARD_DELL_LATITUDE_E6530
|
||||
+ bool "Latitude E6530"
|
||||
diff --git a/src/mainboard/dell/e6530/Makefile.inc b/src/mainboard/dell/e6530/Makefile.inc
|
||||
new file mode 100644
|
||||
index 0000000000..ba64e93eb8
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/Makefile.inc
|
||||
@@ -0,0 +1,6 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only
|
||||
+bootblock-y += early_init.c
|
||||
+bootblock-y += gpio.c
|
||||
+romstage-y += early_init.c
|
||||
+romstage-y += gpio.c
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
diff --git a/src/mainboard/dell/e6530/acpi/ec.asl b/src/mainboard/dell/e6530/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..0d429410a9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/acpi/ec.asl
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Device(EC)
|
||||
+{
|
||||
+ Name (_HID, EISAID("PNP0C09"))
|
||||
+ Name (_UID, 0)
|
||||
+ Name (_GPE, 16)
|
||||
+/* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6530/acpi/platform.asl b/src/mainboard/dell/e6530/acpi/platform.asl
|
||||
new file mode 100644
|
||||
index 0000000000..2d24bbd9b9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/acpi/platform.asl
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Method(_WAK, 1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+ Return(Package() {0, 0})
|
||||
+}
|
||||
+
|
||||
+Method(_PTS,1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6530/acpi/superio.asl b/src/mainboard/dell/e6530/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..55b1db5b11
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/acpi/superio.asl
|
||||
@@ -0,0 +1,3 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
diff --git a/src/mainboard/dell/e6530/acpi_tables.c b/src/mainboard/dell/e6530/acpi_tables.c
|
||||
new file mode 100644
|
||||
index 0000000000..e2759659bf
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/acpi_tables.c
|
||||
@@ -0,0 +1,16 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi_gnvs.h>
|
||||
+#include <soc/nvs.h>
|
||||
+
|
||||
+/* FIXME: check this function. */
|
||||
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
|
||||
+{
|
||||
+ /* The lid is open by default. */
|
||||
+ gnvs->lids = 1;
|
||||
+
|
||||
+ /* Temperature at which OS will shutdown */
|
||||
+ gnvs->tcrt = 100;
|
||||
+ /* Temperature at which OS will throttle CPU */
|
||||
+ gnvs->tpsv = 90;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6530/board_info.txt b/src/mainboard/dell/e6530/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..4601a4aaba
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/board_info.txt
|
||||
@@ -0,0 +1,6 @@
|
||||
+Category: laptop
|
||||
+ROM package: SOIC-8
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
+Release year: 2012
|
||||
diff --git a/src/mainboard/dell/e6530/cmos.default b/src/mainboard/dell/e6530/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..279415dfd1
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/cmos.default
|
||||
@@ -0,0 +1,9 @@
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Disable
|
||||
+nmi=Enable
|
||||
+bluetooth=Enable
|
||||
+wwan=Enable
|
||||
+wlan=Enable
|
||||
+sata_mode=AHCI
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..e85ea4c661
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/cmos.layout
|
||||
@@ -0,0 +1,88 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+
|
||||
+#400 8 r 0 reserved for century byte
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 1 nmi
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+411 1 e 9 sata_mode
|
||||
+
|
||||
+# coreboot config options: EC
|
||||
+412 1 e 1 bluetooth
|
||||
+413 1 e 1 wwan
|
||||
+415 1 e 1 wlan
|
||||
+
|
||||
+# coreboot config options: ME
|
||||
+424 1 e 14 me_state
|
||||
+425 2 h 0 me_state_prev
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 3 e 11 gfx_uma_size
|
||||
+435 2 e 12 hybrid_graphics_mode
|
||||
+440 8 h 0 volume
|
||||
+
|
||||
+# VBOOT
|
||||
+448 128 r 0 vbnv
|
||||
+
|
||||
+# SandyBridge MRC Scrambler Seed values
|
||||
+896 32 r 0 mrc_scrambler_seed
|
||||
+928 32 r 0 mrc_scrambler_seed_s3
|
||||
+960 16 r 0 mrc_scrambler_seed_chk
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+9 0 AHCI
|
||||
+9 1 Compatible
|
||||
+11 0 32M
|
||||
+11 1 64M
|
||||
+11 2 96M
|
||||
+11 3 128M
|
||||
+11 4 160M
|
||||
+11 5 192M
|
||||
+11 6 224M
|
||||
+14 0 Normal
|
||||
+14 1 Disabled
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 447 984
|
||||
diff --git a/src/mainboard/dell/e6530/data.vbt b/src/mainboard/dell/e6530/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
|
||||
GIT binary patch
|
||||
literal 4280
|
||||
zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV
|
||||
zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU
|
||||
zIJ+cPr4+cc-@WIad+wQY&YW{+c1J!nPPgn&^^N3Hy*D37jg0=7CSl@*=mXr>x75gi
|
||||
zTMlK0$A=H4Mh~QKqCa92jz_;d3rtFqp(o-4gCnzxrJ2}Rw@^!haWp<ahv&+aDb5_3
|
||||
zE0-vq=pkms7Ves!pD#^PA#PF^_wjBTO=oC(ayR{asyKURiBdh3?x76Ll#Z5WXklvl
|
||||
z@M5XFK#OxUXqrdzedca+l4WK~_tG8Hv&HgsX`$Za3pnYy`CpW$@0?nsSh|}MrfK#j
|
||||
z%y^t^lPNt{p5INwGcz<MWEN<wv`{J^Eluv$Rb2&6%ZgV5Bp(6~Lz2Eoz~@C!!B)bs
|
||||
z1x-OrK~}*8L07Po(5+xZL6I<}phTEf5QRsVJYHa{f^AXPFaoSsnJ0feXUdB=CJ>Fv
|
||||
zr&_=Q6YubieL}zoiJ0a+c+(bGwFN5g1pz;^rGP1sM+lHB@UAPM2&F=RB&yv@$caXF
|
||||
ze~Io&3CQe=cMHr!e{yiokd?~p&F&k`jg99Ex7}WO=$8*Kx8wXv4eSa_CJqKVkyRr&
|
||||
zCdcqs*@M5!gD84e@fW{|5B#mDGTH;JFw`h^stQcTjf@V3pNe8&f$=NG?-+klRGea*
|
||||
zX1vOHi}4@EM~qJyfuM>e#%9J&Mjzt`j5OnB#;uGZ<1WTMj3vgSj3*esXZY{I`KqUa
|
||||
zfbB~~a>piTMAVDNyHR<{<v-=}gXhE(15|emxueb8Kv%5>0{F7}8pool{7_h6u?7yg
|
||||
zlyNm>-Eq_&WjW{0$9ZHq6x?~W8l2#1g0CyrtN#R-nbWG(?>iNG1zRiZgj;Lm_%rVe
|
||||
zwZ6i{g#sR5xudpbj~5H9TNIQ3gMikIG@l(Z4IR@^2|Vu|LZteLF5@$KH5`Pr&3_vn
|
||||
z^!Fn27&z6hSPR+*;D*&lm-)OE=ZgjK*(X&XdBq7RDUd7>|Lou?UMNg6lVCB;TPz{Z
|
||||
zN4-~p*Rr=uq8OYdlAy38{}dt5%2}aUax{}zWzDRgmsn2|!)=Bp)U35;Ld3H+Ye=*_
|
||||
z4S&0{5*TVI!OU-SWz$XUwrrnb%9?NHau^uhn>&;%&X#8O7mt)SIJr8D$u?NS=rUW6
|
||||
zCmnxV&FgUDAWX}gZ+1AH&-C4Q=3sl5RX9=OWPfCtcRZi4tkX44YYfRH*@?H7T=Kz=
|
||||
zG*i-wU2jbJMK%ChTMTXZFJEm~k;KCj*D60g=j!2ns8Q`g%jSRK^?=IwL^|I5-K2zH
|
||||
z8*A0-mL%Q`R#xatM^u^E=IrX+2&bc;3rv!NipS^G*6zlIRAV(JJDU($OBHuptd&1(
|
||||
zoNu>t*Q}|siS8#MYavR6j7&(~AEL#OaV(^+gy>YrSPiLfgy{2-p=xT2Mtd}4R8#XB
|
||||
z-LDysYw8J&{-GJKYwEiif07x7u5QsOr5oeA`ZJxDb>p|XdQzvCb>nSaeP1UfY_x~f
|
||||
z9bwuRHf|5Ahr{&iu<>+QeI`t=g^e>|^=z1;5o23K?TP5uo%2>aXQWCKr#dH;Qr0*j
|
||||
z3LecKKarw5`Xblzd$&H4oP%y&l3egyUc<=<Azs)*u}X^*n$F~s2O<-paSF?q*HB+n
|
||||
zqBfj5;J|x@hM`M(QD20jrkwi8`y3l;8qO;#l8A#CMI8Kg9E{ERsT>TGXaGC^5Cz)J
|
||||
z4?eb?Kub*nWYdmhV-4?j<o}k#pt-{wK;b3U(B^+`s7-`HYOZOxv<+RG^LulAxKL|9
|
||||
z3NH#9{Lg*7U1&gy<zHSG$;LMHby+V=ENlGFVLKjt%kkph7kP1M8|vebT=K5)*E>JW
|
||||
zjd{Tu*o*CE*QO)}{_J>haU5zn+1QJ^eBg|d5n5-%|DwS@1+<Mtvat=iZ3BF??pZXh
|
||||
zth4PnnWL*s%}k43fbe34>yaZ_2@Kj<UGt)`2G5>K>)nIBR-xB@+1PQ2*c$lV?Z13o
|
||||
zbX%CHpm`!1Z4$d28~9k{rfu-0w@xg6{q!u2{)Dm_))4RK$?#7P*t7V+g_9d<V!MD`
|
||||
zaj`t-?uy6zsjzp<-IdM6g(XhQX2iF<+p?Kmw6?a+f^VMex*PuetNfqf+4_FpD%8TW
|
||||
eZvUbDHC^NLu5~gtzg|!EqSkX2ep9pg!tpEeo1jDh
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..96eed178c5
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/devicetree.cb
|
||||
@@ -0,0 +1,68 @@
|
||||
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
|
||||
+ register "gpu_cpu_backlight" = "0x00000251"
|
||||
+ register "gpu_dp_b_hotplug" = "4"
|
||||
+ register "gpu_dp_c_hotplug" = "4"
|
||||
+ register "gpu_dp_d_hotplug" = "4"
|
||||
+ register "gpu_panel_port_select" = "0"
|
||||
+ register "gpu_panel_power_backlight_off_delay" = "2300"
|
||||
+ register "gpu_panel_power_backlight_on_delay" = "2300"
|
||||
+ register "gpu_panel_power_cycle_delay" = "6"
|
||||
+ register "gpu_panel_power_down_delay" = "400"
|
||||
+ register "gpu_panel_power_up_delay" = "400"
|
||||
+ register "gpu_pch_backlight" = "0x13121312"
|
||||
+
|
||||
+ device domain 0x0 on
|
||||
+ subsystemid 0x1028 0x0535 inherit
|
||||
+
|
||||
+ device ref host_bridge on end # Host bridge
|
||||
+ device ref peg10 off end # PEG
|
||||
+ device ref igd on end # iGPU
|
||||
+
|
||||
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
+ register "docking_supported" = "1"
|
||||
+ register "gen1_dec" = "0x007c0681"
|
||||
+ register "gen2_dec" = "0x005c0921"
|
||||
+ register "gen3_dec" = "0x003c07e1"
|
||||
+ register "gen4_dec" = "0x007c0901"
|
||||
+ register "gpi0_routing" = "2"
|
||||
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
|
||||
+ register "pcie_port_coalesce" = "1"
|
||||
+ register "sata_interface_speed_support" = "0x3"
|
||||
+ register "sata_port_map" = "0x33"
|
||||
+ register "spi_lvscc" = "0x2005"
|
||||
+ register "spi_uvscc" = "0x2005"
|
||||
+ register "superspeed_capable_ports" = "0x0000000f"
|
||||
+ register "xhci_overcurrent_mapping" = "0x00000c03"
|
||||
+ register "xhci_switchable_ports" = "0x0000000f"
|
||||
+
|
||||
+ device ref xhci on end # USB 3.0 Controller
|
||||
+ device ref mei1 off end # Management Engine Interface 1
|
||||
+ device ref mei2 off end # Management Engine Interface 2
|
||||
+ device ref me_ide_r off end # Management Engine IDE-R
|
||||
+ device ref me_kt on end # Management Engine KT
|
||||
+ device ref gbe on end # Intel Gigabit Ethernet
|
||||
+ device ref ehci2 on end # USB2 EHCI #2
|
||||
+ device ref hda on end # High Definition Audio
|
||||
+ device ref pcie_rp1 on end # PCIe Port #1
|
||||
+ device ref pcie_rp2 on end # PCIe Port #2
|
||||
+ device ref pcie_rp3 on end # PCIe Port #3
|
||||
+ device ref pcie_rp4 on end # PCIe Port #4
|
||||
+ device ref pcie_rp5 off end # PCIe Port #5
|
||||
+ device ref pcie_rp6 on end # PCIe Port #6
|
||||
+ device ref pcie_rp7 off end # PCIe Port #7
|
||||
+ device ref pcie_rp8 off end # PCIe Port #8
|
||||
+ device ref ehci1 on end # USB2 EHCI #1
|
||||
+ device ref pci_bridge off end # PCI bridge
|
||||
+ device ref lpc on # LPC bridge
|
||||
+ chip ec/dell/mec5035
|
||||
+ device pnp ff.0 on end
|
||||
+ end
|
||||
+ end
|
||||
+ device ref sata1 on end # SATA Controller 1
|
||||
+ device ref smbus on end # SMBus
|
||||
+ device ref sata2 off end # SATA Controller 2
|
||||
+ device ref thermal off end # Thermal
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/e6530/dsdt.asl b/src/mainboard/dell/e6530/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..7d13c55b08
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/dsdt.asl
|
||||
@@ -0,0 +1,30 @@
|
||||
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20141018 /* OEM revision */
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+ #include "acpi/platform.asl"
|
||||
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..d57f48e7f1
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/early_init.c
|
||||
@@ -0,0 +1,38 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <bootblock_common.h>
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <ec/dell/mec5035/mec5035.h>
|
||||
+#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 0, 3 },
|
||||
+ { 1, 1, 3 },
|
||||
+ { 1, 1, 4 },
|
||||
+ { 1, 1, 4 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 2, 6 },
|
||||
+ { 1, 2, 6 },
|
||||
+};
|
||||
+
|
||||
+void bootblock_mainboard_early_init(void)
|
||||
+{
|
||||
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
|
||||
+ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
|
||||
+ mec5035_early_init();
|
||||
+}
|
||||
+
|
||||
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
+{
|
||||
+ read_spd(&spd[0], 0x50, id_only);
|
||||
+ read_spd(&spd[2], 0x52, id_only);
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6530/gma-mainboard.ads b/src/mainboard/dell/e6530/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..1310830c8e
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/gma-mainboard.ads
|
||||
@@ -0,0 +1,20 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (
|
||||
+ HDMI1, -- mainboard HDMI
|
||||
+ DP2, -- dock DP
|
||||
+ DP3, -- dock DP
|
||||
+ Analog, --mainboard VGA
|
||||
+ LVDS,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/e6530/gpio.c b/src/mainboard/dell/e6530/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..777570765a
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/gpio.c
|
||||
@@ -0,0 +1,192 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_GPIO,
|
||||
+ .gpio1 = GPIO_MODE_GPIO,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_GPIO,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_NATIVE,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_GPIO,
|
||||
+ .gpio16 = GPIO_MODE_GPIO,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_NATIVE,
|
||||
+ .gpio31 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio0 = GPIO_DIR_INPUT,
|
||||
+ .gpio1 = GPIO_DIR_INPUT,
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio3 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio15 = GPIO_DIR_INPUT,
|
||||
+ .gpio16 = GPIO_DIR_INPUT,
|
||||
+ .gpio17 = GPIO_DIR_INPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio29 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio28 = GPIO_LEVEL_LOW,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
+ .gpio30 = GPIO_RESET_RSMRST,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio0 = GPIO_INVERT,
|
||||
+ .gpio8 = GPIO_INVERT,
|
||||
+ .gpio13 = GPIO_INVERT,
|
||||
+ .gpio14 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_NATIVE,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_GPIO,
|
||||
+ .gpio46 = GPIO_MODE_NATIVE,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_GPIO,
|
||||
+ .gpio52 = GPIO_MODE_GPIO,
|
||||
+ .gpio53 = GPIO_MODE_NATIVE,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_NATIVE,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio35 = GPIO_DIR_INPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio45 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_INPUT,
|
||||
+ .gpio51 = GPIO_DIR_INPUT,
|
||||
+ .gpio52 = GPIO_DIR_INPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio34 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio45 = GPIO_LEVEL_LOW,
|
||||
+ .gpio60 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_GPIO,
|
||||
+ .gpio69 = GPIO_MODE_GPIO,
|
||||
+ .gpio70 = GPIO_MODE_GPIO,
|
||||
+ .gpio71 = GPIO_MODE_GPIO,
|
||||
+ .gpio72 = GPIO_MODE_NATIVE,
|
||||
+ .gpio73 = GPIO_MODE_NATIVE,
|
||||
+ .gpio74 = GPIO_MODE_NATIVE,
|
||||
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio68 = GPIO_DIR_INPUT,
|
||||
+ .gpio69 = GPIO_DIR_INPUT,
|
||||
+ .gpio70 = GPIO_DIR_INPUT,
|
||||
+ .gpio71 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ .reset = &pch_gpio_set1_reset,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ .reset = &pch_gpio_set2_reset,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ .reset = &pch_gpio_set3_reset,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/e6530/hda_verb.c b/src/mainboard/dell/e6530/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..9de7e34311
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/hda_verb.c
|
||||
@@ -0,0 +1,33 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
|
||||
+ 0x10280535, /* Subsystem ID */
|
||||
+ 11, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(0, 0x10280535),
|
||||
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
|
||||
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
|
||||
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
||||
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
||||
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
||||
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
|
||||
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
|
||||
+
|
||||
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
+ 0x80860101, /* Subsystem ID */
|
||||
+ 4, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
+
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/e6530/mainboard.c b/src/mainboard/dell/e6530/mainboard.c
|
||||
new file mode 100644
|
||||
index 0000000000..31e49802fc
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6530/mainboard.c
|
||||
@@ -0,0 +1,21 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/device.h>
|
||||
+#include <drivers/intel/gma/int15.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+#include <ec/acpi/ec.h>
|
||||
+#include <console/console.h>
|
||||
+#include <pc80/keyboard.h>
|
||||
+
|
||||
+static void mainboard_enable(struct device *dev)
|
||||
+{
|
||||
+
|
||||
+ /* FIXME: fix these values. */
|
||||
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
+}
|
||||
+
|
||||
+struct chip_operations mainboard_ops = {
|
||||
+ .enable_dev = mainboard_enable,
|
||||
+};
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,145 @@
|
||||
From 88652afd52b0a8e0fc8bb1656e59d8ae4796d847 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Thu, 25 Jan 2024 14:30:03 +0000
|
||||
Subject: [PATCH 27/30] rebase dell/e6530 to newer coreboot code
|
||||
|
||||
i diffed nicholas's current e6430 patch, versus the old one,
|
||||
prior to this revision update in lbmk, also cross referencing
|
||||
the original e6430 and e6530 patches, diffing them, and the
|
||||
result in this patch. most notably, spd data is now defined in
|
||||
the devicetree, instead of early_init.c as per:
|
||||
|
||||
commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da
|
||||
Author: Keith Hui <buurin@gmail.com>
|
||||
Date: Sat Jul 22 12:49:05 2023 -0400
|
||||
mb/*: Update SPD mapping for sandybridge boards
|
||||
|
||||
This should work fine. Will test after this builds.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/mainboard/dell/e6530/Kconfig | 15 +++++++++++----
|
||||
src/mainboard/dell/e6530/cmos.layout | 2 +-
|
||||
src/mainboard/dell/e6530/devicetree.cb | 8 +++++---
|
||||
src/mainboard/dell/e6530/early_init.c | 12 +++---------
|
||||
4 files changed, 20 insertions(+), 17 deletions(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
|
||||
index 582adddbd4..a104566890 100644
|
||||
--- a/src/mainboard/dell/e6530/Kconfig
|
||||
+++ b/src/mainboard/dell/e6530/Kconfig
|
||||
@@ -20,18 +20,25 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select SYSTEM_TYPE_LAPTOP
|
||||
select USE_NATIVE_RAMINIT
|
||||
|
||||
+config DRAM_RESET_GATE_GPIO
|
||||
+ default 60
|
||||
+
|
||||
config MAINBOARD_DIR
|
||||
default "dell/e6530"
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
default "Latitude E6530"
|
||||
|
||||
-config VGA_BIOS_ID
|
||||
- default "8086,0166"
|
||||
+config PS2K_EISAID
|
||||
+ default "PNP0303"
|
||||
|
||||
-config DRAM_RESET_GATE_GPIO
|
||||
- default 60
|
||||
+config PS2M_EISAID
|
||||
+ default "PNP0F13"
|
||||
|
||||
config USBDEBUG_HCD_INDEX
|
||||
default 2
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,0166"
|
||||
+
|
||||
endif
|
||||
diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
|
||||
index e85ea4c661..1aa7e77bce 100644
|
||||
--- a/src/mainboard/dell/e6530/cmos.layout
|
||||
+++ b/src/mainboard/dell/e6530/cmos.layout
|
||||
@@ -25,7 +25,7 @@ entries
|
||||
# coreboot config options: EC
|
||||
412 1 e 1 bluetooth
|
||||
413 1 e 1 wwan
|
||||
-415 1 e 1 wlan
|
||||
+414 1 e 1 wlan
|
||||
|
||||
# coreboot config options: ME
|
||||
424 1 e 14 me_state
|
||||
diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
|
||||
index 96eed178c5..37135bcf0f 100644
|
||||
--- a/src/mainboard/dell/e6530/devicetree.cb
|
||||
+++ b/src/mainboard/dell/e6530/devicetree.cb
|
||||
@@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
register "gpu_panel_power_up_delay" = "400"
|
||||
register "gpu_pch_backlight" = "0x13121312"
|
||||
|
||||
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
|
||||
+
|
||||
device domain 0x0 on
|
||||
subsystemid 0x1028 0x0535 inherit
|
||||
|
||||
@@ -24,7 +26,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
register "gen1_dec" = "0x007c0681"
|
||||
register "gen2_dec" = "0x005c0921"
|
||||
register "gen3_dec" = "0x003c07e1"
|
||||
- register "gen4_dec" = "0x007c0901"
|
||||
+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
|
||||
register "gpi0_routing" = "2"
|
||||
register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
|
||||
register "pcie_port_coalesce" = "1"
|
||||
@@ -37,7 +39,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
register "xhci_switchable_ports" = "0x0000000f"
|
||||
|
||||
device ref xhci on end # USB 3.0 Controller
|
||||
- device ref mei1 off end # Management Engine Interface 1
|
||||
+ device ref mei1 on end # Management Engine Interface 1
|
||||
device ref mei2 off end # Management Engine Interface 2
|
||||
device ref me_ide_r off end # Management Engine IDE-R
|
||||
device ref me_kt on end # Management Engine KT
|
||||
@@ -48,7 +50,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
device ref pcie_rp2 on end # PCIe Port #2
|
||||
device ref pcie_rp3 on end # PCIe Port #3
|
||||
device ref pcie_rp4 on end # PCIe Port #4
|
||||
- device ref pcie_rp5 off end # PCIe Port #5
|
||||
+ device ref pcie_rp5 on end # PCIe Port #5
|
||||
device ref pcie_rp6 on end # PCIe Port #6
|
||||
device ref pcie_rp7 off end # PCIe Port #7
|
||||
device ref pcie_rp8 off end # PCIe Port #8
|
||||
diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
|
||||
index d57f48e7f1..2b40f6963f 100644
|
||||
--- a/src/mainboard/dell/e6530/early_init.c
|
||||
+++ b/src/mainboard/dell/e6530/early_init.c
|
||||
@@ -4,7 +4,6 @@
|
||||
#include <bootblock_common.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <ec/dell/mec5035/mec5035.h>
|
||||
-#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
|
||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
@@ -26,13 +25,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
|
||||
void bootblock_mainboard_early_init(void)
|
||||
{
|
||||
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
|
||||
- pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
|
||||
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
|
||||
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
|
||||
+ | COMB_LPC_EN | COMA_LPC_EN);
|
||||
mec5035_early_init();
|
||||
}
|
||||
-
|
||||
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
|
||||
-{
|
||||
- read_spd(&spd[0], 0x50, id_only);
|
||||
- read_spd(&spd[2], 0x52, id_only);
|
||||
-}
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+54
@@ -0,0 +1,54 @@
|
||||
From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Thu, 25 Jan 2024 14:37:30 +0000
|
||||
Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree
|
||||
|
||||
we neuter anyway. disabling it in devicetree will prevent linux
|
||||
from ever trying to use it or load a driver for it, and thus
|
||||
might prevent benign error messages from appearing in dmesg.
|
||||
|
||||
this change was suggested by nicholas when asked on irc.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/mainboard/dell/e6430/devicetree.cb | 4 ++--
|
||||
src/mainboard/dell/e6530/devicetree.cb | 4 ++--
|
||||
2 files changed, 4 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
|
||||
index 054b01c5ac..2b8574c984 100644
|
||||
--- a/src/mainboard/dell/e6430/devicetree.cb
|
||||
+++ b/src/mainboard/dell/e6430/devicetree.cb
|
||||
@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
register "xhci_switchable_ports" = "0x0000000f"
|
||||
|
||||
device ref xhci on end
|
||||
- device ref mei1 on end
|
||||
+ device ref mei1 off end
|
||||
device ref mei2 off end
|
||||
device ref me_ide_r off end
|
||||
- device ref me_kt on end
|
||||
+ device ref me_kt off end
|
||||
device ref gbe on end
|
||||
device ref ehci2 on end
|
||||
device ref hda on end
|
||||
diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
|
||||
index 37135bcf0f..010200bb6d 100644
|
||||
--- a/src/mainboard/dell/e6530/devicetree.cb
|
||||
+++ b/src/mainboard/dell/e6530/devicetree.cb
|
||||
@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
register "xhci_switchable_ports" = "0x0000000f"
|
||||
|
||||
device ref xhci on end # USB 3.0 Controller
|
||||
- device ref mei1 on end # Management Engine Interface 1
|
||||
+ device ref mei1 off end # Management Engine Interface 1
|
||||
device ref mei2 off end # Management Engine Interface 2
|
||||
device ref me_ide_r off end # Management Engine IDE-R
|
||||
- device ref me_kt on end # Management Engine KT
|
||||
+ device ref me_kt off end # Management Engine KT
|
||||
device ref gbe on end # Intel Gigabit Ethernet
|
||||
device ref ehci2 on end # USB2 EHCI #2
|
||||
device ref hda on end # High Definition Audio
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+164
@@ -0,0 +1,164 @@
|
||||
From f07ed32c36978327709a113967ec40e5ba8d828e Mon Sep 17 00:00:00 2001
|
||||
From: risapav <risapav@gmail.com>
|
||||
Date: Sun, 17 Dec 2023 16:54:07 +0100
|
||||
Subject: [PATCH 29/30] x220_edp modification introduced, similar to x230_edp
|
||||
|
||||
---
|
||||
src/mainboard/lenovo/x220/Kconfig | 13 ++++++-----
|
||||
src/mainboard/lenovo/x220/Kconfig.name | 3 +++
|
||||
src/mainboard/lenovo/x220/Makefile.mk | 6 +++++
|
||||
.../lenovo/x220/variants/x220_edp/data.vbt | Bin 0 -> 4281 bytes
|
||||
.../x220/variants/x220_edp/gma-mainboard.ads | 21 ++++++++++++++++++
|
||||
5 files changed, 38 insertions(+), 5 deletions(-)
|
||||
create mode 100644 src/mainboard/lenovo/x220/variants/x220_edp/data.vbt
|
||||
create mode 100644 src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
|
||||
|
||||
diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
|
||||
index eeb55b4393..bc73a47df9 100644
|
||||
--- a/src/mainboard/lenovo/x220/Kconfig
|
||||
+++ b/src/mainboard/lenovo/x220/Kconfig
|
||||
@@ -1,4 +1,4 @@
|
||||
-if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
|
||||
+if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 || BOARD_LENOVO_X220_EDP
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS
|
||||
def_bool y
|
||||
@@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select DRIVERS_RICOH_RCE822
|
||||
select EC_LENOVO_H8
|
||||
select EC_LENOVO_PMH7
|
||||
- select GFX_GMA_PANEL_1_ON_LVDS
|
||||
+ select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
|
||||
select H8_HAS_BAT_THRESHOLDS_IMPL
|
||||
select HAVE_ACPI_RESUME
|
||||
select HAVE_ACPI_TABLES
|
||||
@@ -41,19 +41,22 @@ config MAINBOARD_DIR
|
||||
default "lenovo/x220"
|
||||
|
||||
config VARIANT_DIR
|
||||
- default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
|
||||
+ default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X220_EDP
|
||||
default "x1" if BOARD_LENOVO_X1
|
||||
|
||||
config FMDFILE
|
||||
default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
- default "ThinkPad X220" if BOARD_LENOVO_X220
|
||||
+ default "ThinkPad X220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220_EDP
|
||||
default "ThinkPad X220i" if BOARD_LENOVO_X220I
|
||||
default "ThinkPad X1" if BOARD_LENOVO_X1
|
||||
|
||||
config OVERRIDE_DEVICETREE
|
||||
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
+
|
||||
+config INTEL_GMA_VBT_FILE
|
||||
+ default "src/mainboard/\$(MAINBOARDDIR)/variants/x220_edp/data.vbt" if BOARD_LENOVO_X220_EDP
|
||||
|
||||
config USBDEBUG_HCD_INDEX
|
||||
int
|
||||
@@ -75,4 +78,4 @@ config PS2K_EISAID
|
||||
config PS2M_EISAID
|
||||
default "LEN0020"
|
||||
|
||||
-endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
|
||||
+endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 || BOARD_LENOVO_X220_EDP
|
||||
diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name
|
||||
index 988ac4fb55..cd501954e0 100644
|
||||
--- a/src/mainboard/lenovo/x220/Kconfig.name
|
||||
+++ b/src/mainboard/lenovo/x220/Kconfig.name
|
||||
@@ -6,3 +6,6 @@ config BOARD_LENOVO_X220I
|
||||
|
||||
config BOARD_LENOVO_X1
|
||||
bool "ThinkPad X1"
|
||||
+
|
||||
+config BOARD_LENOVO_X220_EDP
|
||||
+ bool "ThinkPad X220 eDP Mod (2K/FHD)"
|
||||
diff --git a/src/mainboard/lenovo/x220/Makefile.mk b/src/mainboard/lenovo/x220/Makefile.mk
|
||||
index b104bb52a9..052bf17a22 100644
|
||||
--- a/src/mainboard/lenovo/x220/Makefile.mk
|
||||
+++ b/src/mainboard/lenovo/x220/Makefile.mk
|
||||
@@ -4,6 +4,12 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
|
||||
romstage-y += variants/$(VARIANT_DIR)/gpio.c
|
||||
romstage-y += variants/$(VARIANT_DIR)/romstage.c
|
||||
|
||||
+
|
||||
+ifeq ($(CONFIG_BOARD_LENOVO_X220_EDP),y)
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x220_edp/gma-mainboard.ads
|
||||
+else
|
||||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
+endif
|
||||
+
|
||||
bootblock-y += early_init.c
|
||||
romstage-y += early_init.c
|
||||
diff --git a/src/mainboard/lenovo/x220/variants/x220_edp/data.vbt b/src/mainboard/lenovo/x220/variants/x220_edp/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
|
||||
GIT binary patch
|
||||
literal 4281
|
||||
zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^
|
||||
zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
|
||||
zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
|
||||
zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
|
||||
zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
|
||||
zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
|
||||
z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
|
||||
zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
|
||||
z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
|
||||
z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
|
||||
zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT
|
||||
zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
|
||||
z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}(
|
||||
z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg
|
||||
zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW>
|
||||
zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn
|
||||
zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L
|
||||
zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy;
|
||||
z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY
|
||||
zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
|
||||
zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
|
||||
zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
|
||||
z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
|
||||
zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
|
||||
zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
|
||||
zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
|
||||
z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
|
||||
zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
|
||||
zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH
|
||||
z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
|
||||
zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
|
||||
p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads b/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..f7cf0bc264
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
|
||||
@@ -0,0 +1,21 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (DP1,
|
||||
+ DP2,
|
||||
+ DP3,
|
||||
+ HDMI1,
|
||||
+ HDMI2,
|
||||
+ HDMI3,
|
||||
+ Analog,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,873 @@
|
||||
From 4e0b62e6f0977cf922b1947955538ddca63bb954 Mon Sep 17 00:00:00 2001
|
||||
From: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
Date: Sat, 23 Dec 2023 19:02:10 +0200
|
||||
Subject: [PATCH 30/30] mb/hp: Add Compaq Elite 8300 CMT port
|
||||
|
||||
Based on autoport and Z220 SuperIO code.
|
||||
|
||||
With SeaBIOS and Nouveau on Debian, only nomodeset works with GTX 780
|
||||
(must use proprietary driver instead).
|
||||
|
||||
Tested by xilynx / spot_ on #libreboot:
|
||||
- i3-3220, native raminit 2x2GB, M378B5773DH0-CH9 + MT8JTF25664AZ-1G6M1
|
||||
- Celeron G1620, native raminit 1x4GB, MT8JTF51264AZ-1G6E1
|
||||
- Booting Debian with Linux 6.1.0-16-amd64 via SeaBIOS
|
||||
- All SATA ports
|
||||
- Audio: internal speaker, headphone and microphone plugs
|
||||
- Rebooting
|
||||
- S3 suspend and wake
|
||||
- libgfxinit: VGA, DisplayPort
|
||||
- Ethernet
|
||||
- Super I/O: fan speeds stay in control
|
||||
- GPU in PEG slot
|
||||
|
||||
Untested:
|
||||
- EHCI debugging
|
||||
- Other PCI/PCIe slots
|
||||
- PS/2
|
||||
- Serial, parallel ports
|
||||
|
||||
Change-Id: Ie6ec60d2f4ee50d5e3fa2847c19fa4cf0ab73363
|
||||
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
---
|
||||
.../hp/compaq_elite_8300_cmt/Kconfig | 39 ++++
|
||||
.../hp/compaq_elite_8300_cmt/Kconfig.name | 2 +
|
||||
.../hp/compaq_elite_8300_cmt/Makefile.inc | 7 +
|
||||
.../hp/compaq_elite_8300_cmt/acpi/ec.asl | 1 +
|
||||
.../compaq_elite_8300_cmt/acpi/platform.asl | 10 +
|
||||
.../hp/compaq_elite_8300_cmt/acpi/superio.asl | 29 +++
|
||||
.../hp/compaq_elite_8300_cmt/acpi_tables.c | 12 ++
|
||||
.../hp/compaq_elite_8300_cmt/board_info.txt | 5 +
|
||||
.../hp/compaq_elite_8300_cmt/cmos.default | 7 +
|
||||
.../hp/compaq_elite_8300_cmt/cmos.layout | 74 +++++++
|
||||
.../hp/compaq_elite_8300_cmt/data.vbt | Bin 0 -> 3902 bytes
|
||||
.../hp/compaq_elite_8300_cmt/devicetree.cb | 161 +++++++++++++++
|
||||
.../hp/compaq_elite_8300_cmt/dsdt.asl | 26 +++
|
||||
.../hp/compaq_elite_8300_cmt/early_init.c | 31 +++
|
||||
.../compaq_elite_8300_cmt/gma-mainboard.ads | 17 ++
|
||||
src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++
|
||||
.../hp/compaq_elite_8300_cmt/hda_verb.c | 33 +++
|
||||
.../hp/compaq_elite_8300_cmt/mainboard.c | 16 ++
|
||||
18 files changed, 661 insertions(+)
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.default
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/data.vbt
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/gpio.c
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c
|
||||
create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c
|
||||
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..d2bfd35dc4
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
|
||||
@@ -0,0 +1,39 @@
|
||||
+if BOARD_HP_COMPAQ_ELITE_8300_CMT
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS
|
||||
+ def_bool y
|
||||
+ select BOARD_ROMSIZE_KB_16384
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select INTEL_INT15
|
||||
+ select MAINBOARD_HAS_TPM1
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select MAINBOARD_USES_IFD_GBE_REGION
|
||||
+ select MEMORY_MAPPED_TPM
|
||||
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
|
||||
+ select SERIRQ_CONTINUOUS_MODE
|
||||
+ select SOUTHBRIDGE_INTEL_C216
|
||||
+ select SUPERIO_NUVOTON_NPCD378
|
||||
+ select USE_NATIVE_RAMINIT
|
||||
+
|
||||
+config CBFS_SIZE
|
||||
+ default 0x570000
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "hp/compaq_elite_8300_cmt"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "HP Compaq Elite 8300 CMT"
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,0152"
|
||||
+
|
||||
+config DRAM_RESET_GATE_GPIO
|
||||
+ default 60
|
||||
+
|
||||
+config USBDEBUG_HCD_INDEX # FIXME: check this
|
||||
+ default 2
|
||||
+endif
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..bd399b1e76
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
|
||||
@@ -0,0 +1,2 @@
|
||||
+config BOARD_HP_COMPAQ_ELITE_8300_CMT
|
||||
+ bool "Compaq Elite 8300 CMT"
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
|
||||
new file mode 100644
|
||||
index 0000000000..fb492d3583
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
|
||||
@@ -0,0 +1,7 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+bootblock-y += early_init.c
|
||||
+bootblock-y += gpio.c
|
||||
+romstage-y += early_init.c
|
||||
+romstage-y += gpio.c
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..73fa78ef14
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
|
||||
@@ -0,0 +1 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
|
||||
new file mode 100644
|
||||
index 0000000000..aff432b6f4
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
|
||||
@@ -0,0 +1,10 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Method(_WAK, 1)
|
||||
+{
|
||||
+ Return(Package() {0, 0})
|
||||
+}
|
||||
+
|
||||
+Method(_PTS, 1)
|
||||
+{
|
||||
+}
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..54f8e3fe95
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
|
||||
@@ -0,0 +1,29 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+/* Copied over from compaq_8200_elite_sff/acpi/superio.asl */
|
||||
+
|
||||
+#include <superio/nuvoton/npcd378/acpi/superio.asl>
|
||||
+
|
||||
+Scope (\_GPE)
|
||||
+{
|
||||
+ Method (_L0D, 0, NotSerialized)
|
||||
+ {
|
||||
+ Notify (\_SB.PCI0.EHC1, 0x02)
|
||||
+ Notify (\_SB.PCI0.EHC2, 0x02)
|
||||
+ //FIXME: Add GBE device
|
||||
+ //Notify (\_SB.PCI0.GBE, 0x02)
|
||||
+ }
|
||||
+
|
||||
+ Method (_L09, 0, NotSerialized)
|
||||
+ {
|
||||
+ Notify (\_SB.PCI0.RP01, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP02, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP03, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP04, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP05, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP06, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP07, 0x02)
|
||||
+ Notify (\_SB.PCI0.RP08, 0x02)
|
||||
+ Notify (\_SB.PCI0.PEGP, 0x02)
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c
|
||||
new file mode 100644
|
||||
index 0000000000..8f4f83b826
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/acpi_tables.c
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi_gnvs.h>
|
||||
+#include <soc/nvs.h>
|
||||
+
|
||||
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
|
||||
+{
|
||||
+ /* Temperature at which OS will shutdown */
|
||||
+ gnvs->tcrt = 100;
|
||||
+ /* Temperature at which OS will throttle CPU */
|
||||
+ gnvs->tpsv = 90;
|
||||
+}
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..16c29e82d8
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/board_info.txt
|
||||
@@ -0,0 +1,5 @@
|
||||
+Category: desktop
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
+Release year: 2012
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..6d27a79c66
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.default
|
||||
@@ -0,0 +1,7 @@
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Enable
|
||||
+nmi=Enable
|
||||
+sata_mode=AHCI
|
||||
+gfx_uma_size=32M
|
||||
+psu_fan_lvl=3
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..1fc83b1a55
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/cmos.layout
|
||||
@@ -0,0 +1,74 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+400 3 h 0 psu_fan_lvl
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 1 nmi
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+
|
||||
+421 1 e 9 sata_mode
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 3 e 11 gfx_uma_size
|
||||
+
|
||||
+448 128 r 0 vbnv
|
||||
+
|
||||
+# SandyBridge MRC Scrambler Seed values
|
||||
+896 32 r 0 mrc_scrambler_seed
|
||||
+928 32 r 0 mrc_scrambler_seed_s3
|
||||
+960 16 r 0 mrc_scrambler_seed_chk
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+9 0 AHCI
|
||||
+9 1 IDE
|
||||
+11 0 32M
|
||||
+11 1 64M
|
||||
+11 2 96M
|
||||
+11 3 128M
|
||||
+11 4 160M
|
||||
+11 5 192M
|
||||
+11 6 224M
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 415 984
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt b/src/mainboard/hp/compaq_elite_8300_cmt/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..ba627e152b65d779a80529d3811ec4d21c1b1e54
|
||||
GIT binary patch
|
||||
literal 3902
|
||||
zcmdT{U2GIp6h5;vvp;uc+U>N$b}h{<64)*MnJ%?9P1V_-)?HZIZFkwM#K;zQp(Lf0
|
||||
z<tLDc9kdaQ30aLnL^K;s2=dhMWTFo|nZ_7XjUmSPK!^{95W@p8ks#}tpO&8zIx!OQ
|
||||
zPQE$ko;~;Lz2}~D=XOmtlA-CLNM|A&X^#!0H)V!X1yJCH+Hrg@ZIQ%qdRr`<32%!e
|
||||
zhohV5IamQTwRf%o6o9FhLR}l4OH3XpP6S4SG(9$1II_L8yRfU+nK)!=G!;$I@QxkD
|
||||
ziDGH&K(Rp6*_Xmpr<F+L;O>b69XhyYd$H6<buRR#UELiUx+zsQbar)jhLo-lr6HwH
|
||||
z>Fo<WE0Nehba-<rkql=N!$Wj<l*SV2a5_D(Ig)&trbdV3iAW+d5R-_pl<3~6Bc<KD
|
||||
z#t+ayG>9yU(vE~()R;1j?k!Dq(D1|r9o2pI)6wGoV(Cz^&><0>;1cWR7zP*~YL5XE
|
||||
z{3`?=k6Yy2an&85Zl2-7jM~D`7^g}MH^6WOPE9askfBLVUBl5fj(Wi%F%Ax(<(|k=
|
||||
zUH4c9hXO|5?0UW22lb}G1;Fb@mzSZ8u5fTU59si@;V}EXTQ}(rl%Wn?F&a92X)&+>
|
||||
zPTj@>Ls7r4(ffK2={zn6t_hS-cTaC$zZ!`R#y2KYqnT`O>nqx^H{P7_!|gKQVi}A&
|
||||
z)G!L9*Z>@59dMlOh4owoes{Vd<dPwV$RfrOM_mMtBi==PggB45i1-TeHR314Rm63~
|
||||
z9|&+0AczJ;Ga`TpA^H)6h!kQgqJWr0I1j?@szU?Z5NsM_$vRVlmxGf*(9T-+vzFa+
|
||||
z!`K`kmJ}>$kl1)tt1cJZseb2!YSsO`J_8jQ^hAhROmRyl4au@8tDixs`{k^Dwd%=Z
|
||||
zH-yjQdy~%q^YKY<!Z~QsaFSLvP<_4(KebAii%moAUIzzXdbGph$OYv=h6VegT-HIX
|
||||
zhmBa>th;}v$r!Z-pnAN<1I)+#R``=|huU|*W1ew~tpBFsG0q;_jCFT6Ulxt*TNv8#
|
||||
z2{`>`$JM`Jd{F+EzpU7VIlvml?AFW1Xv$0tKyom(Ej2b-oERG0Q?%Jx8HYk6s9{*E
|
||||
z_)hegWIm-8PLF`1DpU2QrTKj4;VUElwQBD4f+hZ<s%)PPsp_Q#i!T5@)2taxv1ghG
|
||||
z<B&&<DI4jDn$!FOh>Zbggj@JDLYbjpK69X2PaAVr^Xn{6e+%<?63)ABGAHVvOwA0G
|
||||
zop-g`)B~42TA5y1<#p#*n`4^oSOPu_>i&oRk>LBlzUQG|c;s(9<VO#^<&i}~RuI}x
|
||||
z<RL<GguYJXG9hOOy+q_62>FFjhafiyq*<UbLCy*!FVMFH`LsYj73iEG|16MS1xiG@
|
||||
zNhE7UniS<%MKUhZlcHP^$pw+li}F>GTo<V<$!jFiA<>K^@07@tL{CZbd5K(<q}Cgp
|
||||
z=D5OWb(o)+1@4lFyO?u`hP=smQS!Cx@SCx8`ItCXGEp|?Se~I$OQ9>*L<3rb71Ew*
|
||||
zhn0l-*|a>v(n`=1+Du-&m2f&k|07qiv~u)9FuttfVcu_x;V>QXdsXjZ?db(%oNhK5
|
||||
zme#7yVBD-k)j4Zp4ohoWFJ0rv5wpCVNbYROUKoL9Ww31Rg%2ZHHV$2!ik&#T)={qH
|
||||
z{mrUEty8JFXPPS;w@^`Y*;z%PU#m>bK7$Oci}}Epjc<@x;b&~*!<k@Zeq?5~lKODv
|
||||
zA_EJ8u45$aFet6+Tz;mY_(sgz72qmZ5DkWZn3D#BWHRv7#wxD)p^~C26;X-mqrjL$
|
||||
z8S4>Op}BgEe0X$iI{Gx<zTS2<*M4^|Sg17^@EYY@zAl0)<Ta?zd%bn~D02?r)iu%P
|
||||
wm+F7xwtgQt<KA_UyAYqlTkT_cS089?Pr=)R7|a9^*a9j1U$>1p1;4R>1E3jwQUCw|
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..f4efabd792
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
|
||||
@@ -0,0 +1,161 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+chip northbridge/intel/sandybridge
|
||||
+ register "gfx.use_spread_spectrum_clock" = "0"
|
||||
+ register "gpu_dp_b_hotplug" = "0"
|
||||
+ register "gpu_dp_c_hotplug" = "0"
|
||||
+ register "gpu_dp_d_hotplug" = "0"
|
||||
+ # BTX mainboard: Reversed mapping
|
||||
+ register "spd_addresses" = "{0x53, 0x52, 0x51, 0x50}"
|
||||
+ device domain 0 on
|
||||
+ subsystemid 0x103c 0x3396 inherit
|
||||
+
|
||||
+ device ref host_bridge on end # Host bridge Host bridge
|
||||
+ device ref peg10 on end # PEG
|
||||
+ device ref igd on end # iGPU
|
||||
+
|
||||
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
+ register "docking_supported" = "0"
|
||||
+ register "gen1_dec" = "0x00fc0a01"
|
||||
+ register "gen2_dec" = "0x00fc0801"
|
||||
+ register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
|
||||
+ register "pcie_port_coalesce" = "1"
|
||||
+ register "sata_interface_speed_support" = "0x3"
|
||||
+ register "sata_port_map" = "0x1f"
|
||||
+ register "spi_lvscc" = "0x2005"
|
||||
+ register "spi_uvscc" = "0x2005"
|
||||
+ register "superspeed_capable_ports" = "0x0000000f"
|
||||
+ register "xhci_overcurrent_mapping" = "0x00000c03"
|
||||
+ register "xhci_switchable_ports" = "0x0000000f"
|
||||
+
|
||||
+ device ref xhci on end # USB 3.0 Controller
|
||||
+ device ref mei1 off end # Management Engine Interface 1
|
||||
+ device ref mei2 off end
|
||||
+ device ref me_ide_r off end
|
||||
+ device ref me_kt off end
|
||||
+ device ref gbe on end # Intel Gigabit Ethernet
|
||||
+ device ref ehci1 on end # USB2 EHCI #1
|
||||
+ device ref ehci2 on end # USB2 EHCI #2
|
||||
+ device ref hda on end # High Definition Audio
|
||||
+ device ref sata1 on end # SATA Controller 1
|
||||
+ device ref sata2 off end # SATA Controller 2
|
||||
+ device ref smbus on end # SMBus
|
||||
+
|
||||
+ device ref pcie_rp1 on end
|
||||
+ device ref pcie_rp2 on end
|
||||
+ device ref pcie_rp3 on end
|
||||
+ device ref pcie_rp4 on end
|
||||
+ device ref pcie_rp5 on end
|
||||
+ device ref pcie_rp5 on end
|
||||
+ device ref pcie_rp7 on end
|
||||
+ device ref pcie_rp8 on end
|
||||
+
|
||||
+ device ref pci_bridge on end
|
||||
+ device ref lpc on # LPC bridge
|
||||
+ chip superio/common # copied from Z220
|
||||
+ device pnp 2e.ff on # passes SIO base addr to SSDT gen
|
||||
+ chip superio/nuvoton/npcd378
|
||||
+ device pnp 2e.0 off end # Floppy
|
||||
+ device pnp 2e.1 on # Parallel port
|
||||
+ # global
|
||||
+
|
||||
+ # serialice: Vendor writes:
|
||||
+ irq 0x14 = 0x9c
|
||||
+ irq 0x1c = 0xa8
|
||||
+ irq 0x1d = 0x08
|
||||
+ irq 0x22 = 0x3f
|
||||
+ irq 0x1a = 0xb0
|
||||
+ # dumped from superiotool:
|
||||
+ irq 0x1b = 0x1e
|
||||
+ irq 0x27 = 0x08
|
||||
+ irq 0x2a = 0x20
|
||||
+ irq 0x2d = 0x01
|
||||
+ # parallel port
|
||||
+ io 0x60 = 0x378
|
||||
+ irq 0x70 = 0x07
|
||||
+ drq 0x74 = 0x01
|
||||
+ end
|
||||
+ device pnp 2e.2 off # COM1
|
||||
+ io 0x60 = 0x2f8
|
||||
+ irq 0x70 = 3
|
||||
+ end
|
||||
+ device pnp 2e.3 on # COM2, IR
|
||||
+ io 0x60 = 0x3f8
|
||||
+ irq 0x70 = 4
|
||||
+ end
|
||||
+ device pnp 2e.4 on # LED control
|
||||
+ io 0x60 = 0x600
|
||||
+ # IOBASE[0h] = bit0 LED red / green
|
||||
+ # IOBASE[0h] = bit1-4 LED PWM duty cycle
|
||||
+ # IOBASE[1h] = bit6 SWCC
|
||||
+
|
||||
+ io 0x62 = 0x610
|
||||
+ # IOBASE [0h] = GPES
|
||||
+ # IOBASE [1h] = GPEE
|
||||
+ # IOBASE [4h:7h] = 32bit upcounter at 1Mhz
|
||||
+ # IOBASE [8h:bh] = GPS
|
||||
+ # IOBASE [ch:fh] = GPE
|
||||
+ end
|
||||
+ device pnp 2e.5 on # Mouse
|
||||
+ irq 0x70 = 0xc
|
||||
+ end
|
||||
+ device pnp 2e.6 on # Keyboard
|
||||
+ io 0x60 = 0x0060
|
||||
+ io 0x62 = 0x0064
|
||||
+ irq 0x70 = 0x01
|
||||
+ # serialice: Vendor writes:
|
||||
+ drq 0xf0 = 0x40
|
||||
+ end
|
||||
+ device pnp 2e.7 on # WDT ?
|
||||
+ io 0x60 = 0x620
|
||||
+ end
|
||||
+ device pnp 2e.8 on # HWM
|
||||
+ io 0x60 = 0x800
|
||||
+ # IOBASE[0h:feh] HWM page
|
||||
+ # IOBASE[ffh] bit0-bit3 page selector
|
||||
+
|
||||
+ drq 0xf0 = 0x20
|
||||
+ drq 0xf1 = 0x01
|
||||
+ drq 0xf2 = 0x40
|
||||
+ drq 0xf3 = 0x01
|
||||
+
|
||||
+ drq 0xf4 = 0x66
|
||||
+ drq 0xf5 = 0x67
|
||||
+ drq 0xf6 = 0x66
|
||||
+ drq 0xf7 = 0x01
|
||||
+ end
|
||||
+ device pnp 2e.f on # GPIO OD ?
|
||||
+ drq 0xf1 = 0x97
|
||||
+ drq 0xf2 = 0x01
|
||||
+ drq 0xf5 = 0x08
|
||||
+ drq 0xfe = 0x80
|
||||
+ end
|
||||
+ device pnp 2e.15 on # BUS ?
|
||||
+ io 0x60 = 0x0680
|
||||
+ io 0x62 = 0x0690
|
||||
+ end
|
||||
+ device pnp 2e.1c on # Suspend Control ?
|
||||
+ io 0x60 = 0x640
|
||||
+ # writing to IOBASE[5h]
|
||||
+ # 0x0: Power off
|
||||
+ # 0x9: Power off and bricked until CMOS battery removed
|
||||
+ end
|
||||
+ device pnp 2e.1e on # GPIO ?
|
||||
+ io 0x60 = 0x660
|
||||
+ drq 0xf4 = 0x01
|
||||
+ # skip the following, as it
|
||||
+ # looks like remapped registers
|
||||
+ #drq 0xf5 = 0x06
|
||||
+ #drq 0xf6 = 0x60
|
||||
+ #drq 0xfe = 0x03
|
||||
+ end
|
||||
+ end
|
||||
+ end
|
||||
+ end
|
||||
+ chip drivers/pc80/tpm
|
||||
+ device pnp 4e.0 on end # TPM module
|
||||
+ end
|
||||
+ end
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..e8e2b3a3e5
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/dsdt.asl
|
||||
@@ -0,0 +1,26 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20141018 /* OEM revision */
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+ #include "acpi/platform.asl"
|
||||
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..99b7891c70
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
|
||||
@@ -0,0 +1,31 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <bootblock_common.h>
|
||||
+#include <superio/nuvoton/npcd378/npcd378.h>
|
||||
+#include <superio/nuvoton/common/nuvoton.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
|
||||
+
|
||||
+const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
+ { 1, 0, 0 },
|
||||
+ { 1, 0, 0 },
|
||||
+ { 1, 0, 1 },
|
||||
+ { 1, 0, 1 },
|
||||
+ { 1, 0, 2 },
|
||||
+ { 1, 0, 2 },
|
||||
+ { 1, 0, 3 },
|
||||
+ { 1, 0, 3 },
|
||||
+ { 1, 0, 4 },
|
||||
+ { 1, 0, 4 },
|
||||
+ { 1, 0, 6 },
|
||||
+ { 1, 0, 5 },
|
||||
+ { 1, 0, 5 },
|
||||
+ { 1, 0, 6 },
|
||||
+};
|
||||
+
|
||||
+void bootblock_mainboard_early_init(void)
|
||||
+{
|
||||
+ if (CONFIG(CONSOLE_SERIAL))
|
||||
+ nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
+}
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..686f7d44db
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/gma-mainboard.ads
|
||||
@@ -0,0 +1,17 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (DP2,
|
||||
+ HDMI2,
|
||||
+ Analog,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..2ae852ae51
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/gpio.c
|
||||
@@ -0,0 +1,191 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_GPIO,
|
||||
+ .gpio1 = GPIO_MODE_GPIO,
|
||||
+ .gpio2 = GPIO_MODE_NATIVE,
|
||||
+ .gpio3 = GPIO_MODE_NATIVE,
|
||||
+ .gpio4 = GPIO_MODE_NATIVE,
|
||||
+ .gpio5 = GPIO_MODE_NATIVE,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_GPIO,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_NATIVE,
|
||||
+ .gpio15 = GPIO_MODE_GPIO,
|
||||
+ .gpio16 = GPIO_MODE_GPIO,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||
+ .gpio19 = GPIO_MODE_NATIVE,
|
||||
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_NATIVE,
|
||||
+ .gpio31 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio0 = GPIO_DIR_INPUT,
|
||||
+ .gpio1 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio11 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio15 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio16 = GPIO_DIR_INPUT,
|
||||
+ .gpio17 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio29 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio31 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio15 = GPIO_LEVEL_LOW,
|
||||
+ .gpio17 = GPIO_LEVEL_LOW,
|
||||
+ .gpio28 = GPIO_LEVEL_LOW,
|
||||
+ .gpio29 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio0 = GPIO_INVERT,
|
||||
+ .gpio1 = GPIO_INVERT,
|
||||
+ .gpio6 = GPIO_INVERT,
|
||||
+ .gpio11 = GPIO_INVERT,
|
||||
+ .gpio13 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_GPIO,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_GPIO,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_NATIVE,
|
||||
+ .gpio46 = GPIO_MODE_GPIO,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_NATIVE,
|
||||
+ .gpio52 = GPIO_MODE_NATIVE,
|
||||
+ .gpio53 = GPIO_MODE_NATIVE,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_NATIVE,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_NATIVE,
|
||||
+ .gpio61 = GPIO_MODE_GPIO,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio32 = GPIO_DIR_INPUT,
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_INPUT,
|
||||
+ .gpio35 = GPIO_DIR_INPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio43 = GPIO_DIR_INPUT,
|
||||
+ .gpio46 = GPIO_DIR_INPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_INPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio61 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_GPIO,
|
||||
+ .gpio69 = GPIO_MODE_GPIO,
|
||||
+ .gpio70 = GPIO_MODE_GPIO,
|
||||
+ .gpio71 = GPIO_MODE_GPIO,
|
||||
+ .gpio72 = GPIO_MODE_GPIO,
|
||||
+ .gpio73 = GPIO_MODE_NATIVE,
|
||||
+ .gpio74 = GPIO_MODE_NATIVE,
|
||||
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio68 = GPIO_DIR_INPUT,
|
||||
+ .gpio69 = GPIO_DIR_INPUT,
|
||||
+ .gpio70 = GPIO_DIR_INPUT,
|
||||
+ .gpio71 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio72 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+ .gpio71 = GPIO_LEVEL_LOW,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ .reset = &pch_gpio_set1_reset,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ .reset = &pch_gpio_set2_reset,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ .reset = &pch_gpio_set3_reset,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..a1eafcda68
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/hda_verb.c
|
||||
@@ -0,0 +1,33 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x10ec0221, /* Codec Vendor / Device ID: Realtek */
|
||||
+ 0x103c3396, /* Subsystem ID */
|
||||
+ 11, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(0, 0x103c3396),
|
||||
+ AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x14, 0x01014020),
|
||||
+ AZALIA_PIN_CFG(0, 0x17, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x18, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1a, 0x02a11c3f),
|
||||
+ AZALIA_PIN_CFG(0, 0x1b, 0x01813c30),
|
||||
+ AZALIA_PIN_CFG(0, 0x1d, 0x415901f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x21, 0x0221102f),
|
||||
+
|
||||
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
+ 0x80860101, /* Subsystem ID */
|
||||
+ 4, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
+ AZALIA_PIN_CFG(3, 0x05, 0x58560010),
|
||||
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
+ AZALIA_PIN_CFG(3, 0x07, 0x58560030),
|
||||
+
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c
|
||||
new file mode 100644
|
||||
index 0000000000..8dbd95ef96
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/hp/compaq_elite_8300_cmt/mainboard.c
|
||||
@@ -0,0 +1,16 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/device.h>
|
||||
+#include <drivers/intel/gma/int15.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+static void mainboard_enable(struct device *dev)
|
||||
+{
|
||||
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
|
||||
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
+}
|
||||
+
|
||||
+struct chip_operations mainboard_ops = {
|
||||
+ .enable_dev = mainboard_enable,
|
||||
+};
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+923
@@ -0,0 +1,923 @@
|
||||
From 38a713eb071dd9c1b7d5092ce686537e5d9266f5 Mon Sep 17 00:00:00 2001
|
||||
From: Mate Kukri <kukri.mate@gmail.com>
|
||||
Date: Mon, 4 Dec 2023 21:34:18 +0000
|
||||
Subject: [PATCH 1/1] mb/dell: Add OptiPlex 7020/9020 port
|
||||
MIME-Version: 1.0
|
||||
Content-Type: text/plain; charset=UTF-8
|
||||
Content-Transfer-Encoding: 8bit
|
||||
|
||||
The OptiPlex 7020 and 9020 use physically identical motherboards.
|
||||
|
||||
Each model comes in the following form factors:
|
||||
- 7020: SFF, MT
|
||||
- 9020: USFF (not currently supported), SFF, MT
|
||||
|
||||
(7020 SFF) Boots Linux and Windows 10:
|
||||
- Tested with an i3-4160 and i5-4460
|
||||
- DRAM init works using the MRC (4G, 4G+4G)
|
||||
- iGPU init works using libgfxinit (VGA, 2x DP)
|
||||
- PCIe 16x: tested, ok
|
||||
- PCIe 4x: tested, ok
|
||||
- All USB2 and USB3 ports work
|
||||
- SMSC SCH5555 Super I/O: serial works, PS/2 untested
|
||||
- Audio: back and front output works, internal speaker works,
|
||||
mic inputs untested
|
||||
- Ethernet: tested, works
|
||||
|
||||
(9020 MT)
|
||||
- Tested by Michael Büchler (thanks for the overridetree)
|
||||
|
||||
Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a
|
||||
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/optiplex_9020/Kconfig | 34 +++
|
||||
src/mainboard/dell/optiplex_9020/Kconfig.name | 11 +
|
||||
src/mainboard/dell/optiplex_9020/Makefile.inc | 5 +
|
||||
src/mainboard/dell/optiplex_9020/acpi/ec.asl | 3 +
|
||||
.../dell/optiplex_9020/acpi/platform.asl | 11 +
|
||||
.../dell/optiplex_9020/acpi/superio.asl | 3 +
|
||||
.../dell/optiplex_9020/board_info.txt | 8 +
|
||||
src/mainboard/dell/optiplex_9020/bootblock.c | 116 ++++++++++
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 4 +
|
||||
src/mainboard/dell/optiplex_9020/cmos.layout | 58 +++++
|
||||
src/mainboard/dell/optiplex_9020/data.vbt | Bin 0 -> 4409 bytes
|
||||
.../dell/optiplex_9020/devicetree.cb | 80 +++++++
|
||||
src/mainboard/dell/optiplex_9020/dsdt.asl | 25 ++
|
||||
.../dell/optiplex_9020/gma-mainboard.ads | 18 ++
|
||||
src/mainboard/dell/optiplex_9020/gpio.c | 217 ++++++++++++++++++
|
||||
src/mainboard/dell/optiplex_9020/hda_verb.c | 27 +++
|
||||
src/mainboard/dell/optiplex_9020/mainboard.c | 15 ++
|
||||
.../dell/optiplex_9020/overridetree_mt.cb | 10 +
|
||||
src/mainboard/dell/optiplex_9020/romstage.c | 53 +++++
|
||||
19 files changed, 698 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig.name
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/Makefile.inc
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/acpi/platform.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/board_info.txt
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/bootblock.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/cmos.default
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/data.vbt
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/devicetree.cb
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/dsdt.asl
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/gpio.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/mainboard.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/overridetree_mt.cb
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/romstage.c
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..774a72f161
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/Kconfig
|
||||
@@ -0,0 +1,34 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+if BOARD_DELL_OPTIPLEX_9020_SFF || BOARD_DELL_OPTIPLEX_9020_MT
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS
|
||||
+ def_bool y
|
||||
+ select BOARD_ROMSIZE_KB_12288
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select INTEL_INT15
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select MAINBOARD_USES_IFD_GBE_REGION
|
||||
+ select NORTHBRIDGE_INTEL_HASWELL
|
||||
+ select SERIRQ_CONTINUOUS_MODE
|
||||
+ select SOUTHBRIDGE_INTEL_LYNXPOINT
|
||||
+ select SUPERIO_SMSC_SCH555x
|
||||
+
|
||||
+config CBFS_SIZE
|
||||
+ default 0x600000
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "dell/optiplex_9020"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "OptiPlex 7020/9020 SFF" if BOARD_DELL_OPTIPLEX_9020_SFF
|
||||
+ default "OptiPlex 7020/9020 MT" if BOARD_DELL_OPTIPLEX_9020_MT
|
||||
+
|
||||
+config OVERRIDE_DEVICETREE
|
||||
+ default "overridetree_mt.cb" if BOARD_DELL_OPTIPLEX_9020_MT
|
||||
+
|
||||
+endif
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/Kconfig.name b/src/mainboard/dell/optiplex_9020/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..c25c330a44
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/Kconfig.name
|
||||
@@ -0,0 +1,11 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+config BOARD_DELL_OPTIPLEX_9020_SFF
|
||||
+ bool "OptiPlex 7020/9020 SFF"
|
||||
+ help
|
||||
+ The 7020 SFF and 9020 SFF mainboards are physically identical.
|
||||
+
|
||||
+config BOARD_DELL_OPTIPLEX_9020_MT
|
||||
+ bool "OptiPlex 7020/9020 MT"
|
||||
+ help
|
||||
+ The 7020 MT and 9020 MT mainboards are physically identical.
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc
|
||||
new file mode 100644
|
||||
index 0000000000..6ca2f2afaa
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/Makefile.inc
|
||||
@@ -0,0 +1,5 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+romstage-y += gpio.c
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
+bootblock-y += bootblock.c
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/acpi/ec.asl b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..16990d45f4
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
|
||||
@@ -0,0 +1,3 @@
|
||||
+/* SPDX-License-Identifier: CC-PDDC */
|
||||
+
|
||||
+/* Please update the license if adding licensable material. */
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/acpi/platform.asl b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
|
||||
new file mode 100644
|
||||
index 0000000000..cda7682e3e
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
|
||||
@@ -0,0 +1,11 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Method(_WAK, 1)
|
||||
+{
|
||||
+ Return(Package() { 0, 0 })
|
||||
+}
|
||||
+
|
||||
+Method(_PTS, 1)
|
||||
+{
|
||||
+
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/acpi/superio.asl b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..16990d45f4
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
|
||||
@@ -0,0 +1,3 @@
|
||||
+/* SPDX-License-Identifier: CC-PDDC */
|
||||
+
|
||||
+/* Please update the license if adding licensable material. */
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/board_info.txt b/src/mainboard/dell/optiplex_9020/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..e30cf9c41f
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/board_info.txt
|
||||
@@ -0,0 +1,8 @@
|
||||
+Vendor name: Dell Inc.
|
||||
+Board name: OptiPlex 7020/9020
|
||||
+Release year: 2014
|
||||
+Category: desktop
|
||||
+ROM package: SOIC-8
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
|
||||
new file mode 100644
|
||||
index 0000000000..2837cf9cf1
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/bootblock.c
|
||||
@@ -0,0 +1,116 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <arch/io.h>
|
||||
+#include <device/pnp_ops.h>
|
||||
+#include <superio/smsc/sch555x/sch555x.h>
|
||||
+#include <southbridge/intel/lynxpoint/pch.h>
|
||||
+
|
||||
+static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
|
||||
+{
|
||||
+ // Clear EC-to-Host mailbox
|
||||
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
|
||||
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
|
||||
+
|
||||
+ // Send address and value to the EC
|
||||
+ sch555x_emi_write16(0, (addr1 * 2) | 0x101);
|
||||
+ sch555x_emi_write32(4, val | (addr2 << 16));
|
||||
+
|
||||
+ // Wait for acknowledgement message from EC
|
||||
+ outb(1, SCH555x_EMI_IOBASE);
|
||||
+ size_t timeout = 0;
|
||||
+ do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
|
||||
+}
|
||||
+
|
||||
+struct ec_init_entry {
|
||||
+ uint16_t addr;
|
||||
+ uint8_t val;
|
||||
+};
|
||||
+
|
||||
+static void ec_init(void)
|
||||
+{
|
||||
+ /*
|
||||
+ * Tables from CORE_PEI
|
||||
+ */
|
||||
+
|
||||
+ static const struct ec_init_entry init_table1[] = {
|
||||
+ {0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10},
|
||||
+ {0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10},
|
||||
+ {0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12},
|
||||
+ {0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12},
|
||||
+ {0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10},
|
||||
+ {0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11},
|
||||
+ };
|
||||
+
|
||||
+ for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i)
|
||||
+ ec_write(2, init_table1[i].addr, init_table1[i].val);
|
||||
+
|
||||
+ static const struct ec_init_entry init_table2[] = {
|
||||
+ {0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f},
|
||||
+ {0x0083, 0xbb}, {0x0085, 0xd9}, {0x0086, 0x2c}, {0x008a, 0x34},
|
||||
+ {0x008b, 0x60}, {0x0090, 0x5e}, {0x0091, 0x5e}, {0x0092, 0x86},
|
||||
+ {0x0096, 0xa4}, {0x0097, 0xa4}, {0x0098, 0xa4}, {0x009b, 0xa4},
|
||||
+ {0x00a0, 0x0a}, {0x00a1, 0x0a}, {0x00ae, 0x7c}, {0x00af, 0x7c},
|
||||
+ {0x00b0, 0x9e}, {0x00b3, 0x7c}, {0x00b6, 0x08}, {0x00b7, 0x08},
|
||||
+ {0x00ea, 0x64}, {0x00ef, 0xff}, {0x00f8, 0x15}, {0x00f9, 0x00},
|
||||
+ {0x00f0, 0x30}, {0x00fd, 0x01}, {0x01a1, 0x00}, {0x01a2, 0x00},
|
||||
+ {0x01b1, 0x08}, {0x01be, 0x90}, {0x0280, 0x24}, {0x0281, 0x13},
|
||||
+ {0x0282, 0x03}, {0x0283, 0x0a}, {0x0284, 0x80}, {0x0285, 0x03},
|
||||
+ {0x0288, 0x80}, {0x0289, 0x0c}, {0x028a, 0x03}, {0x028b, 0x0a},
|
||||
+ {0x028c, 0x80}, {0x028d, 0x03}, {0x0040, 0x01},
|
||||
+ };
|
||||
+
|
||||
+ for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i)
|
||||
+ ec_write(1, init_table2[i].addr, init_table2[i].val);
|
||||
+
|
||||
+ /*
|
||||
+ * Table from PeiHwmInit
|
||||
+ */
|
||||
+
|
||||
+ static const struct ec_init_entry hwm_init_table[] = {
|
||||
+ {0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f},
|
||||
+ {0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33},
|
||||
+ {0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff},
|
||||
+ {0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00},
|
||||
+ {0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00},
|
||||
+ {0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80},
|
||||
+ {0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02},
|
||||
+ {0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04},
|
||||
+ {0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50},
|
||||
+ {0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50},
|
||||
+ {0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c},
|
||||
+ {0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd},
|
||||
+ {0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e},
|
||||
+ {0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00},
|
||||
+ {0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff},
|
||||
+ {0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00},
|
||||
+ {0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c},
|
||||
+ {0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02},
|
||||
+ {0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03},
|
||||
+ };
|
||||
+
|
||||
+ for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i)
|
||||
+ ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val);
|
||||
+}
|
||||
+
|
||||
+#define SCH555x_IOBASE 0x2e
|
||||
+#define GLOBAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL)
|
||||
+#define SERIAL_DEV PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1)
|
||||
+
|
||||
+void mainboard_config_superio(void)
|
||||
+{
|
||||
+ // Super I/O early init will map Runtime and EMI registers
|
||||
+ sch555x_early_init(GLOBAL_DEV);
|
||||
+
|
||||
+ // Changes LED color among a few other things (extracted from Dell's FW)
|
||||
+ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS);
|
||||
+ outb(0x00, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN);
|
||||
+ outb(0x18, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN1);
|
||||
+ outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
|
||||
+ outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
|
||||
+
|
||||
+ // Magic EC init
|
||||
+ ec_init();
|
||||
+
|
||||
+ // Magic EC init is needed for UART1 initialization to work
|
||||
+ sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..b159660aa8
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
@@ -0,0 +1,4 @@
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+nmi=Disable
|
||||
+power_on_after_fail=Disable
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..c9ba76c78f
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
@@ -0,0 +1,58 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 3 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 4 debug_level
|
||||
+
|
||||
+#400 8 r 0 reserved for century byte
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 1 nmi
|
||||
+409 2 e 5 power_on_after_fail
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+
|
||||
+3 0 Fallback
|
||||
+3 1 Normal
|
||||
+
|
||||
+4 0 Emergency
|
||||
+4 1 Alert
|
||||
+4 2 Critical
|
||||
+4 3 Error
|
||||
+4 4 Warning
|
||||
+4 5 Notice
|
||||
+4 6 Info
|
||||
+4 7 Debug
|
||||
+4 8 Spew
|
||||
+
|
||||
+5 0 Disable
|
||||
+5 1 Enable
|
||||
+5 2 Keep
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 415 984
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/data.vbt b/src/mainboard/dell/optiplex_9020/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..1779f3b8d1018ba0aae480103b145bd7b6dd6187
|
||||
GIT binary patch
|
||||
literal 4409
|
||||
zcmdT{T}&KR6h8B_yR)-1!!lr9XiE<T5h_au1f&hdSy<_UtKG6lH%+yR*`>u$pi5g@
|
||||
zP3)>@YHE~+rqQIfO&U!#QHhDMkD3^5qG|e|_!FbV_|P=QG{y&G)b-q%VY>waTYnNg
|
||||
zlQZY%p84*%_nv!argpGv03)IJ_Pe7|bSMP|Y$`oQ_r=uJyEVQm92yAi>WXgdz6a04
|
||||
zD)5&6aRng7aW^T=MoU}o*#7ireSZT+;@h#UsjZ1Q4>q^r@OTD8dxst!AG;&CDL8Oo
|
||||
z^uXRm#BdDb@opR+9u95~SuwW<QzMfTqeF)qF*csrKZ)H~hheKJ9Bag}aojteN>8Tu
|
||||
zlb(JA9~v1O%8aBZS%1O)#VHqfy2mFDXGV7K*^l+z4cKBBMzF<bZbmC*>>kfdG+}6T
|
||||
z6#H4sB=%D$nS<$6lPaq+z<VHx902D6&lA9LzqdfOh#}ETa^{d^Qa3IULMDVoxLYjf
|
||||
zv_SO(uW~#!R!i{VA*TVEBzVEHO|WbbVKxbVzx(ZS+aUqD7$Jw01c2!TeBcCl0o=?F
|
||||
z28TS8$Zmu%>jW^<CJybs=4~hTnz>lR#jfi;e=$Iyv50HHXlZTl*xYG$g?l1>(OCb$
|
||||
zU}DG4>=REuHB||}y?K34mZfn9c;qU`2=#DU;Ndl)1MU?sz-wNFPrQEkmiQ;)T^<R}
|
||||
zdUSY)_#@&kiGTFS@Cz|7$)FHd5Z4d~iSHopC5{t6K)joHAMs<vPZPgD{1Wk5;x~xj
|
||||
zC4QgyW8%+<za@4bfZuX_7Ccs_S<aEAwgkTj&o@B!q~ky7_`O%{^_3mzbL0|(U(%J!
|
||||
zc|7n(?qUFPIq6Q8fk_B7y<FHqia0WANkND?_5ev%QVGY-<-AEUTj=`t?()a1=55O5
|
||||
z{_mRaBdE^OAe?=LY&@K6Vl9(-%92(Xz`HWb2jrieR~917`}6Ye2PkFGM<<PdozIAn
|
||||
z^~{K!pyf`h0{p_snin|Dy#pS02chH`c=HRG@BbfDysjI9Dy8GmAziVGdEP8P1@20r
|
||||
zBqq#pp3aSG?5Z($i{C%72adbj0IKXTPv?C2Liz8vth$FvMX=5WiS0s*j42Hu+7sIq
|
||||
z8yZWG-Z!*2U8Hey1X2}XhM>*}9BsG30>%b-aT^$>F;QlFs?KdZG`Fp?&P=>G?}^-H
|
||||
z8V}91nC5%)o<Kdc9}(=yRN9ZYz<R5Y#!XvQOq$z%Cn**6PyxTvRRPl+f_+_}SCoA<
|
||||
za@Vv<hO&AVF3|ye$@4RJwCumBv5E4paIqMm<F?cxfHmzf>&;H%+*-esTyM8m72{dk
|
||||
zN_}yhSK?iwVn0WBiCk!kp>joHDlbZb@-S0HiL0(nDpFM`l;n%Xd2HQIg5o*w(&Ie1
|
||||
zXo(bBhcHASlm}+e6jDvD2&s06<%&>b5^ABIR?)PhL=q;MUUIqs5lZ+1pe5A$068bG
|
||||
zYk1wEhT|Z7B_sHB-6yZ{VV6%I@W~JQaLT8j@X2R<_@Ph#!Y6;{LrKvq6}eWyK1JWD
|
||||
z$ioUgr|72?`J93m6@5;TuPEqO_4TUUsA9jWr&M`N#p9~}sw&T@IIHTHRrx0s1Dd`;
|
||||
zlUp_1q3NTVd{D!an*OFHpV#mkO~0ziziR4+t74X)<Fci+?Wnk=j6%hk;1x^$%=t;W
|
||||
zN^Yg4Uc8pHADlgcLV{lz;Y<lab7BqFXUpvws%k&N(?Ss`Sx<+!GQ!KP+0;bGI<u<0
|
||||
z4SuHz074M#Hw&c+7DDH;qgZ?(u>Ea)e<*`45Lgb&Bj~FK_ryRq5ZmCESNs5##`izi
|
||||
zWl>%<LQf28jJj3r(DnvHaKF`A!KQ&LD-NM<^&lbC85n4V#QQeF4>b${%1!r_HHzg|
|
||||
zb7P%(J~^e(e?Sd9{<%GhPj7S-3+AEyh&WB(;<TE@je=%!#d%nM6pIdgs~&vU<?vS!
|
||||
ztaC^yZYGz`LA7!K7Z$M=S1RF53~x3RqnkZtSM@aQ$D;QIzd0M&*AX-mLFdJ1%|nTW
|
||||
zKu4H+<*IHlA(@4;q~A}wijjptb-`A1OTqCOFSJ6vTQS-lW>Em~L_u66jOlR9ZUEZ|
|
||||
zMhC-jAj9!85eeUR&5CZpNVwUt>909-|5kF?Ve@Y58TNJV5CLGmjb)HGdJ22pR+!su
|
||||
z`@ntQ1&|Z3+xNb&p(?Li{yzJDS)dq4FZ3_c3(;&nw}2XNf@gau=U)2uzaL_df=2EH
|
||||
PTo#&U0FLJAf1&;f?(g8r
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..c0b17a15ff
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
|
||||
@@ -0,0 +1,80 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+chip northbridge/intel/haswell
|
||||
+ # This mainboard has VGA
|
||||
+ register "gpu_ddi_e_connected" = "1"
|
||||
+
|
||||
+ chip cpu/intel/haswell
|
||||
+ device cpu_cluster 0 on ops haswell_cpu_bus_ops end
|
||||
+ end
|
||||
+
|
||||
+ device domain 0 on
|
||||
+ ops haswell_pci_domain_ops
|
||||
+
|
||||
+ subsystemid 0x1028 0x05a5 inherit
|
||||
+
|
||||
+ device pci 00.0 on end # Host bridge
|
||||
+ device pci 01.0 on end # PCIe graphics
|
||||
+ device pci 02.0 on end # VGA controller
|
||||
+ device pci 03.0 on end # Mini-HD audio
|
||||
+
|
||||
+ chip southbridge/intel/lynxpoint
|
||||
+ register "gen1_dec" = "0x007c0a01"
|
||||
+ register "gen2_dec" = "0x007c0901"
|
||||
+ register "gen3_dec" = "0x003c07e1"
|
||||
+ register "gen4_dec" = "0x001c0901"
|
||||
+ register "sata_port_map" = "0x33"
|
||||
+
|
||||
+ device pci 14.0 on end # xHCI controller
|
||||
+ device pci 16.0 on end # Management Engine interface 1
|
||||
+ device pci 16.1 off end # Management Engine interface 2
|
||||
+ device pci 16.2 off end # Management Engine IDE-R
|
||||
+ device pci 16.3 on end # Management Engine KT
|
||||
+ device pci 19.0 on # Intel Gigabit Ethernet
|
||||
+ subsystemid 0x1028 0x05a4
|
||||
+ end
|
||||
+ device pci 1a.0 on end # EHCI controller #2
|
||||
+ device pci 1b.0 on end # HD audio controller
|
||||
+ device pci 1c.0 off end
|
||||
+ device pci 1c.1 off end
|
||||
+ device pci 1c.2 off end
|
||||
+ device pci 1c.3 off end
|
||||
+ device pci 1c.4 on end # PCIe 4x slot
|
||||
+ device pci 1c.5 off end
|
||||
+ device pci 1c.6 off end
|
||||
+ device pci 1c.7 off end
|
||||
+ device pci 1d.0 on end # EHCI controller #1
|
||||
+ device pci 1f.0 on # LPC bridge
|
||||
+ chip superio/smsc/sch555x
|
||||
+ device pnp 2e.0 on # EMI
|
||||
+ io 0x60 = 0xa00
|
||||
+ end
|
||||
+ device pnp 2e.1 on # 8042
|
||||
+ io 0x60 = 0x60
|
||||
+ irq 0x0f = 0
|
||||
+ irq 0x70 = 1
|
||||
+ irq 0x72 = 12
|
||||
+ end
|
||||
+ device pnp 2e.7 on # UART1
|
||||
+ io 0x60 = 0x3f8
|
||||
+ irq 0x0f = 2
|
||||
+ irq 0x70 = 4
|
||||
+ end
|
||||
+ device pnp 2e.8 off end # UART2
|
||||
+ device pnp 2e.c on # LPC interface
|
||||
+ io 0x60 = 0x2e
|
||||
+ end
|
||||
+ device pnp 2e.a on # Runtime registers
|
||||
+ io 0x60 = 0xa40
|
||||
+ end
|
||||
+ device pnp 2e.b off end # Floppy Controller
|
||||
+ device pnp 2e.11 off end # Parallel Port
|
||||
+ end
|
||||
+ end
|
||||
+ device pci 1f.2 on end # SATA controller 1
|
||||
+ device pci 1f.3 on end # SMBus
|
||||
+ device pci 1f.5 off end # SATA controller 2
|
||||
+ device pci 1f.6 off end # Thermal
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/dsdt.asl b/src/mainboard/dell/optiplex_9020/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..7ec1e9775a
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/dsdt.asl
|
||||
@@ -0,0 +1,25 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20181031 /* OEM Revision */
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+ #include "acpi/platform.asl"
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+ #include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/haswell/acpi/hostbridge.asl>
|
||||
+ #include <southbridge/intel/lynxpoint/acpi/pch.asl>
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..173f2f1d0d
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
|
||||
@@ -0,0 +1,18 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (DP1,
|
||||
+ DP2,
|
||||
+ DP3,
|
||||
+ Analog,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/gpio.c b/src/mainboard/dell/optiplex_9020/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..48b7707e2c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/gpio.c
|
||||
@@ -0,0 +1,217 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_GPIO,
|
||||
+ .gpio1 = GPIO_MODE_GPIO,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_GPIO,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_GPIO,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_GPIO,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_NATIVE,
|
||||
+ .gpio15 = GPIO_MODE_GPIO,
|
||||
+ .gpio16 = GPIO_MODE_NATIVE,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||
+ .gpio19 = GPIO_MODE_NATIVE,
|
||||
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_GPIO,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_GPIO,
|
||||
+ .gpio26 = GPIO_MODE_GPIO,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_NATIVE,
|
||||
+ .gpio30 = GPIO_MODE_NATIVE,
|
||||
+ .gpio31 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio0 = GPIO_DIR_INPUT,
|
||||
+ .gpio1 = GPIO_DIR_INPUT,
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio3 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio5 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio11 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio15 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio17 = GPIO_DIR_INPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio23 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio25 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio26 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio31 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio13 = GPIO_LEVEL_LOW,
|
||||
+ .gpio15 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio22 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio23 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio25 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio26 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio28 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+ .gpio18 = GPIO_BLINK,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio8 = GPIO_INVERT,
|
||||
+ .gpio9 = GPIO_INVERT,
|
||||
+ .gpio11 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
+ .gpio26 = GPIO_RESET_RSMRST,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_GPIO,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_NATIVE,
|
||||
+ .gpio37 = GPIO_MODE_NATIVE,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_GPIO,
|
||||
+ .gpio45 = GPIO_MODE_GPIO,
|
||||
+ .gpio46 = GPIO_MODE_GPIO,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_GPIO,
|
||||
+ .gpio51 = GPIO_MODE_GPIO,
|
||||
+ .gpio52 = GPIO_MODE_GPIO,
|
||||
+ .gpio53 = GPIO_MODE_GPIO,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_GPIO,
|
||||
+ .gpio56 = GPIO_MODE_NATIVE,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio32 = GPIO_DIR_INPUT,
|
||||
+ .gpio33 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio34 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio35 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio44 = GPIO_DIR_INPUT,
|
||||
+ .gpio45 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio46 = GPIO_DIR_INPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_INPUT,
|
||||
+ .gpio50 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio51 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio52 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio53 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio54 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio55 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio57 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio33 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio34 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio45 = GPIO_LEVEL_LOW,
|
||||
+ .gpio50 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio51 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio52 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio53 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio54 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio55 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio57 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio60 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_GPIO,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_GPIO,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_GPIO,
|
||||
+ .gpio69 = GPIO_MODE_GPIO,
|
||||
+ .gpio70 = GPIO_MODE_NATIVE,
|
||||
+ .gpio71 = GPIO_MODE_NATIVE,
|
||||
+ .gpio72 = GPIO_MODE_GPIO,
|
||||
+ .gpio73 = GPIO_MODE_GPIO,
|
||||
+ .gpio74 = GPIO_MODE_GPIO,
|
||||
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio64 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio66 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio68 = GPIO_DIR_INPUT,
|
||||
+ .gpio69 = GPIO_DIR_INPUT,
|
||||
+ .gpio72 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio73 = GPIO_DIR_INPUT,
|
||||
+ .gpio74 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+ .gpio64 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio66 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio72 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio74 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ .reset = &pch_gpio_set1_reset,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ .reset = &pch_gpio_set2_reset,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ .reset = &pch_gpio_set3_reset,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/hda_verb.c b/src/mainboard/dell/optiplex_9020/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..df43ade3e6
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/hda_verb.c
|
||||
@@ -0,0 +1,27 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <stdint.h>
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x10ec0280, /* Realtek ALC3220 */
|
||||
+ 0x102805a5, /* Subsystem ID */
|
||||
+ 13, /* Number of entries */
|
||||
+ AZALIA_SUBVENDOR(0, 0x102805a5),
|
||||
+ AZALIA_PIN_CFG(0, 0x12, 0x4008c000),
|
||||
+ AZALIA_PIN_CFG(0, 0x13, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x14, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x15, 0x0221401f),
|
||||
+ AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x18, 0x01a13040),
|
||||
+ AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1a, 0x02a19030),
|
||||
+ AZALIA_PIN_CFG(0, 0x1b, 0x01014020),
|
||||
+ AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
|
||||
+ AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
|
||||
new file mode 100644
|
||||
index 0000000000..c834fea5d3
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
|
||||
@@ -0,0 +1,15 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/device.h>
|
||||
+#include <drivers/intel/gma/int15.h>
|
||||
+
|
||||
+static void mainboard_enable(struct device *dev)
|
||||
+{
|
||||
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
|
||||
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
+}
|
||||
+
|
||||
+struct chip_operations mainboard_ops = {
|
||||
+ .enable_dev = mainboard_enable,
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
|
||||
new file mode 100644
|
||||
index 0000000000..90205c2d68
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
|
||||
@@ -0,0 +1,10 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+chip northbridge/intel/haswell
|
||||
+ device domain 0 on
|
||||
+ chip southbridge/intel/lynxpoint
|
||||
+ device pci 1c.1 on end # PCI (via XIO2001 bridge)
|
||||
+ device pci 1c.2 on end # PCIe 1x slot
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c
|
||||
new file mode 100644
|
||||
index 0000000000..2b9cdaa5fd
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/romstage.c
|
||||
@@ -0,0 +1,53 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+#include <northbridge/intel/haswell/raminit.h>
|
||||
+#include <southbridge/intel/lynxpoint/pch.h>
|
||||
+
|
||||
+void mainboard_config_rcba(void)
|
||||
+{
|
||||
+ RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQC, PIRQD, PIRQA);
|
||||
+ RCBA16(D29IR) = DIR_ROUTE(PIRQC, PIRQA, PIRQD, PIRQH);
|
||||
+ RCBA16(D28IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
|
||||
+ RCBA16(D27IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQG);
|
||||
+ RCBA16(D26IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQF, PIRQA);
|
||||
+ RCBA16(D25IR) = DIR_ROUTE(PIRQH, PIRQG, PIRQF, PIRQE);
|
||||
+ RCBA16(D22IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQA);
|
||||
+ RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
|
||||
+}
|
||||
+
|
||||
+void mb_get_spd_map(struct spd_info *spdi)
|
||||
+{
|
||||
+ spdi->addresses[0] = 0x50;
|
||||
+ spdi->addresses[1] = 0x51;
|
||||
+ spdi->addresses[2] = 0x52;
|
||||
+ spdi->addresses[3] = 0x53;
|
||||
+}
|
||||
+
|
||||
+const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
|
||||
+ /* Length, Enable, OCn#, Location */
|
||||
+ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
|
||||
+ {0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
|
||||
+ {0x0040, 1, 1, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 2, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 3, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 3, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 0, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 0, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 4, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 4, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 5, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 5, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 6, USB_PORT_BACK_PANEL},
|
||||
+ {0x0040, 1, 7, USB_PORT_BACK_PANEL},
|
||||
+};
|
||||
+
|
||||
+const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
|
||||
+ /* Enable, OCn# */
|
||||
+ {1, 6},
|
||||
+ {1, 7},
|
||||
+ {0, USB_OC_PIN_SKIP},
|
||||
+ {0, USB_OC_PIN_SKIP},
|
||||
+ {1, 1},
|
||||
+ {1, 2},
|
||||
+};
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,774 @@
|
||||
From 41002e64c92e90903fa591c4a8a1cc0108833743 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sun, 26 Nov 2023 17:08:52 -0700
|
||||
Subject: [PATCH] mb/dell: Add Latitude E6420 (Sandy Bridge)
|
||||
|
||||
Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/e6420/Kconfig | 38 ++++
|
||||
src/mainboard/dell/e6420/Kconfig.name | 2 +
|
||||
src/mainboard/dell/e6420/Makefile.inc | 6 +
|
||||
src/mainboard/dell/e6420/acpi/ec.asl | 9 +
|
||||
src/mainboard/dell/e6420/acpi/platform.asl | 12 ++
|
||||
src/mainboard/dell/e6420/acpi/superio.asl | 3 +
|
||||
src/mainboard/dell/e6420/acpi_tables.c | 16 ++
|
||||
src/mainboard/dell/e6420/board_info.txt | 6 +
|
||||
src/mainboard/dell/e6420/cmos.default | 9 +
|
||||
src/mainboard/dell/e6420/cmos.layout | 88 ++++++++++
|
||||
src/mainboard/dell/e6420/data.vbt | Bin 0 -> 6144 bytes
|
||||
src/mainboard/dell/e6420/devicetree.cb | 66 +++++++
|
||||
src/mainboard/dell/e6420/dsdt.asl | 30 ++++
|
||||
src/mainboard/dell/e6420/early_init.c | 32 ++++
|
||||
src/mainboard/dell/e6420/gma-mainboard.ads | 20 +++
|
||||
src/mainboard/dell/e6420/gpio.c | 191 +++++++++++++++++++++
|
||||
src/mainboard/dell/e6420/hda_verb.c | 33 ++++
|
||||
src/mainboard/dell/e6420/mainboard.c | 21 +++
|
||||
18 files changed, 582 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/e6420/Kconfig
|
||||
create mode 100644 src/mainboard/dell/e6420/Kconfig.name
|
||||
create mode 100644 src/mainboard/dell/e6420/Makefile.inc
|
||||
create mode 100644 src/mainboard/dell/e6420/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/dell/e6420/acpi/platform.asl
|
||||
create mode 100644 src/mainboard/dell/e6420/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/dell/e6420/acpi_tables.c
|
||||
create mode 100644 src/mainboard/dell/e6420/board_info.txt
|
||||
create mode 100644 src/mainboard/dell/e6420/cmos.default
|
||||
create mode 100644 src/mainboard/dell/e6420/cmos.layout
|
||||
create mode 100644 src/mainboard/dell/e6420/data.vbt
|
||||
create mode 100644 src/mainboard/dell/e6420/devicetree.cb
|
||||
create mode 100644 src/mainboard/dell/e6420/dsdt.asl
|
||||
create mode 100644 src/mainboard/dell/e6420/early_init.c
|
||||
create mode 100644 src/mainboard/dell/e6420/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/e6420/gpio.c
|
||||
create mode 100644 src/mainboard/dell/e6420/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/e6420/mainboard.c
|
||||
|
||||
diff --git a/src/mainboard/dell/e6420/Kconfig b/src/mainboard/dell/e6420/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..cff62bf70c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/Kconfig
|
||||
@@ -0,0 +1,38 @@
|
||||
+if BOARD_DELL_LATITUDE_E6420
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS
|
||||
+ def_bool y
|
||||
+ select BOARD_ROMSIZE_KB_10240
|
||||
+ select EC_ACPI
|
||||
+ select EC_DELL_MEC5035
|
||||
+ select GFX_GMA_PANEL_1_ON_LVDS
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select INTEL_INT15
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select MAINBOARD_USES_IFD_GBE_REGION
|
||||
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
|
||||
+ select SERIRQ_CONTINUOUS_MODE
|
||||
+ select SOUTHBRIDGE_INTEL_BD82X6X
|
||||
+ select SYSTEM_TYPE_LAPTOP
|
||||
+ select USE_NATIVE_RAMINIT
|
||||
+
|
||||
+config DRAM_RESET_GATE_GPIO
|
||||
+ default 60
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "dell/e6420"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "Latitude E6420"
|
||||
+
|
||||
+config USBDEBUG_HCD_INDEX
|
||||
+ default 2
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,0126"
|
||||
+
|
||||
+endif # BOARD_DELL_LATITUDE_E6420
|
||||
diff --git a/src/mainboard/dell/e6420/Kconfig.name b/src/mainboard/dell/e6420/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..1722891e7b
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/Kconfig.name
|
||||
@@ -0,0 +1,2 @@
|
||||
+config BOARD_DELL_LATITUDE_E6420
|
||||
+ bool "Latitude E6420"
|
||||
diff --git a/src/mainboard/dell/e6420/Makefile.inc b/src/mainboard/dell/e6420/Makefile.inc
|
||||
new file mode 100644
|
||||
index 0000000000..ba64e93eb8
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/Makefile.inc
|
||||
@@ -0,0 +1,6 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only
|
||||
+bootblock-y += early_init.c
|
||||
+bootblock-y += gpio.c
|
||||
+romstage-y += early_init.c
|
||||
+romstage-y += gpio.c
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
diff --git a/src/mainboard/dell/e6420/acpi/ec.asl b/src/mainboard/dell/e6420/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..0d429410a9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/acpi/ec.asl
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Device(EC)
|
||||
+{
|
||||
+ Name (_HID, EISAID("PNP0C09"))
|
||||
+ Name (_UID, 0)
|
||||
+ Name (_GPE, 16)
|
||||
+/* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6420/acpi/platform.asl b/src/mainboard/dell/e6420/acpi/platform.asl
|
||||
new file mode 100644
|
||||
index 0000000000..2d24bbd9b9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/acpi/platform.asl
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Method(_WAK, 1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+ Return(Package() {0, 0})
|
||||
+}
|
||||
+
|
||||
+Method(_PTS,1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6420/acpi/superio.asl b/src/mainboard/dell/e6420/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..55b1db5b11
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/acpi/superio.asl
|
||||
@@ -0,0 +1,3 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
diff --git a/src/mainboard/dell/e6420/acpi_tables.c b/src/mainboard/dell/e6420/acpi_tables.c
|
||||
new file mode 100644
|
||||
index 0000000000..e2759659bf
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/acpi_tables.c
|
||||
@@ -0,0 +1,16 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi_gnvs.h>
|
||||
+#include <soc/nvs.h>
|
||||
+
|
||||
+/* FIXME: check this function. */
|
||||
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
|
||||
+{
|
||||
+ /* The lid is open by default. */
|
||||
+ gnvs->lids = 1;
|
||||
+
|
||||
+ /* Temperature at which OS will shutdown */
|
||||
+ gnvs->tcrt = 100;
|
||||
+ /* Temperature at which OS will throttle CPU */
|
||||
+ gnvs->tpsv = 90;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6420/board_info.txt b/src/mainboard/dell/e6420/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..34d5ad9e0b
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/board_info.txt
|
||||
@@ -0,0 +1,6 @@
|
||||
+Category: laptop
|
||||
+ROM package: SOIC-8
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
+Release year: 2011
|
||||
diff --git a/src/mainboard/dell/e6420/cmos.default b/src/mainboard/dell/e6420/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..279415dfd1
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/cmos.default
|
||||
@@ -0,0 +1,9 @@
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Disable
|
||||
+nmi=Enable
|
||||
+bluetooth=Enable
|
||||
+wwan=Enable
|
||||
+wlan=Enable
|
||||
+sata_mode=AHCI
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/dell/e6420/cmos.layout b/src/mainboard/dell/e6420/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..1aa7e77bce
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/cmos.layout
|
||||
@@ -0,0 +1,88 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+
|
||||
+#400 8 r 0 reserved for century byte
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 1 nmi
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+411 1 e 9 sata_mode
|
||||
+
|
||||
+# coreboot config options: EC
|
||||
+412 1 e 1 bluetooth
|
||||
+413 1 e 1 wwan
|
||||
+414 1 e 1 wlan
|
||||
+
|
||||
+# coreboot config options: ME
|
||||
+424 1 e 14 me_state
|
||||
+425 2 h 0 me_state_prev
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 3 e 11 gfx_uma_size
|
||||
+435 2 e 12 hybrid_graphics_mode
|
||||
+440 8 h 0 volume
|
||||
+
|
||||
+# VBOOT
|
||||
+448 128 r 0 vbnv
|
||||
+
|
||||
+# SandyBridge MRC Scrambler Seed values
|
||||
+896 32 r 0 mrc_scrambler_seed
|
||||
+928 32 r 0 mrc_scrambler_seed_s3
|
||||
+960 16 r 0 mrc_scrambler_seed_chk
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+9 0 AHCI
|
||||
+9 1 Compatible
|
||||
+11 0 32M
|
||||
+11 1 64M
|
||||
+11 2 96M
|
||||
+11 3 128M
|
||||
+11 4 160M
|
||||
+11 5 192M
|
||||
+11 6 224M
|
||||
+14 0 Normal
|
||||
+14 1 Disabled
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 447 984
|
||||
diff --git a/src/mainboard/dell/e6420/data.vbt b/src/mainboard/dell/e6420/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd
|
||||
GIT binary patch
|
||||
literal 6144
|
||||
zcmeHKeQZ-z6hE);wSBvNZ|mO1=*HLC2BQN8uVX6{N9eY)75ORymb$R8!YYuAZEgeE
|
||||
zKk|S@Fen*n41W-viAF;r%)~^EkpLz-B{2q##)LmGAtoY;7*Qhv_1yPbw$TC$2}G0K
|
||||
z=6Ao&x#ym9?z!i_&TOh(kLzky2cN8MTpny#R<;VU4Rkn?rBIz(YL~BBw<%b&zGhSH
|
||||
z$~AQ>@D0d=Xx6RE0BwSxspWdrW9y<FZGD@&x3_JL;p$p!;!BVdcKLkht0=-%(Jj&T
|
||||
z_GkyztZ%>#t7^)^(T-R<7W?O6ZTI%A+j=`<Jw3Q%dk6N!da<_?7oyiU3)^<~_TiSk
|
||||
zE$y+=RK3PGQ`gzmXYPRBx>C|f*UP9{h|4>ANrAe~?ymV*)83AaT#FuTjP=C2cg5P~
|
||||
zt4w78r$t#300cWY_k)mevmAmFI3&oBfytoAAPQiYK$XEIgHwV@5-gJ-Q-*p8yfTDj
|
||||
zaDz=1Y!X1B3`OpQ&Ik}bM|0xHn0gYNZw0rT=7AXS2in-q8K^?)0|el+Z6geW7i7MM
|
||||
zv~!|>HqL-|Fk}EYOa@)R<X)VQ7c}d8R1b@RTn5rq(90|QRg0?wwZZz(6Dz}w>zg9Y
|
||||
z8;!mD_V*XSjT33~$`o`s>zEGBq8AQ`HaH?y!Fh2QiX1v@aCo4LaENf&DZ_cE2A2qb
|
||||
z5@cC}X)=S^1RvpXLWs~v*hqMau$!=t@B-mg!XV)|;eEm>!Z6`H;R4|&!d1d`f|S7^
|
||||
zli+B98*!TfPE&6~NVM5j3v{N3OTjpnm_L@BPh(}esd(J!gj?~iJP?n|OZZOiTqlql
|
||||
zg<NWR@g&-*W-E%A7|*1Z_`sVO$K&iAP+VIj9{<1hT%SXsK}IBk8!daftR`6-)EUiS
|
||||
zvv*HR(#-ZwhA~7wcmxbe4%E?Y7P0y{1q|nqR1L29UR8v@#No^g5MH)7!>{%-$T|cR
|
||||
zZx5|xm>Fl>;@$m};P{0WC>O~<Nl1`*PLgPN_hP2a^h+L$ls&SYrkDYr+&l*%%S?^Q
|
||||
ziPSdtHE<LNEnr7cs=ihL-C>-p>*$9CpHRLgN|POkqD^UP4nw|4nf0bc8MOBk<;%js
|
||||
zfpCAWNzqSPlz@X%j9CGrwZDKUl@K{g6pzqiIIARDQ)#@^RW&0pmNG;XZ?!SlHB?L#
|
||||
zKRAMgq(R;aQd%@Gy38-LS@ix)fR**(P3B9wI=Uk^&cWmmwB<vf21<0#LBA!;qtAh(
|
||||
zYe5g_T{+gw^mi8QzPPraBoH~8oCz%r=$nVi1A)`Y8IKqIdqm6MihqxtpFaTggaPxu
|
||||
zQP07nf#&kPkPp}Cmk$F1g7q7QK;kz~80i&oDN}~wYbPUI6AtG5H+$T!@f5FzUhp21
|
||||
z^XiPT3rb%B@sA9g!n88R7BOsLS|?+D3}0v3dyIX|@JFWo&e%<c#V)PV#g@7-=F*;V
|
||||
zvAr&Q+ogTvVxPM3XP5Smi`f;Nt7uCU)}Y`HMcbpW=M_AuXlE35PQl+4O{7m66&I@7
|
||||
zGL@}Sai^*sP}va`KTx$VRQ8REf2*1+lTFH0=UkNx+eN|1rVyipl)Du=h=@%w+iQZG
|
||||
zT6@-PdW^oyFb44AG`HMZWEnP{&OQ+jC`N4emoS)x;EPN}uaSFOf-Mn8JRRO<WJc
|
||||
zn6%=L94~PR)%Ua_HTZcfTXD<p{%8p|<N<;Efw$Zb4$}{m8@7c((~<7^thaau&@Wx#
|
||||
zVGNL)lmH@{o=h*{muXGc!;nXrVgpp3;1V1stMj=4AtxyzX+?SoB~zN}!*r?9Qvs1P
|
||||
zmV_(CTmt0sY&6=F=_M>E34GYvuh1uQF+BUdWyQC5SaEM1QvKlHBMs13C}n{0SwRxW
|
||||
ziekMa&kvRFruRcKCevGy5)TxUBDlur@E{TtQ^NQ>nO+Cgl)&Ga(PxqVW?e3TLH-UY
|
||||
zdL3T{z^xdd`$(STFUb8R*cKa}r>n{Wk+MXRH~o-hN}#9OF*>T#>rfhiRs(Wc-R^9@
|
||||
z%F=<}dn(E}ADc03zJ>JvZe;_8f+WFLL4%qNYs`_aa`a$Pl5H;iO^Wt*cP3W(d=(g}
|
||||
zZ%nKT1$|r-tAv8($u2-BI2Uiz#%OT&!Q3b~Ru2P2j;Gem!@wfPsTR%J>W{8z)oq^J
|
||||
k^Qm&?O@bFkw4CTocwoW<6CRlGz=Q`TJTT#bN9KWl0rH4|j{pDw
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/e6420/devicetree.cb b/src/mainboard/dell/e6420/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..f9259f7175
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/devicetree.cb
|
||||
@@ -0,0 +1,66 @@
|
||||
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
|
||||
+ register "gpu_cpu_backlight" = "0x0000054f"
|
||||
+ register "gpu_dp_b_hotplug" = "4"
|
||||
+ register "gpu_dp_c_hotplug" = "4"
|
||||
+ register "gpu_dp_d_hotplug" = "4"
|
||||
+ register "gpu_panel_port_select" = "0"
|
||||
+ register "gpu_panel_power_backlight_off_delay" = "2300"
|
||||
+ register "gpu_panel_power_backlight_on_delay" = "2300"
|
||||
+ register "gpu_panel_power_cycle_delay" = "6"
|
||||
+ register "gpu_panel_power_down_delay" = "400"
|
||||
+ register "gpu_panel_power_up_delay" = "400"
|
||||
+ register "gpu_pch_backlight" = "0x13121312"
|
||||
+
|
||||
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
|
||||
+
|
||||
+ device domain 0x0 on
|
||||
+ subsystemid 0x1028 0x0493 inherit
|
||||
+
|
||||
+ device ref host_bridge on end # Host bridge
|
||||
+ device ref peg10 on end # PEG
|
||||
+ device ref igd on end # iGPU
|
||||
+
|
||||
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
+ register "docking_supported" = "1"
|
||||
+ register "gen1_dec" = "0x007c0681"
|
||||
+ register "gen2_dec" = "0x007c0901"
|
||||
+ register "gen3_dec" = "0x003c07e1"
|
||||
+ register "gen4_dec" = "0x001c0901"
|
||||
+ register "gpi0_routing" = "2"
|
||||
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
|
||||
+ register "pcie_port_coalesce" = "1"
|
||||
+ register "sata_interface_speed_support" = "0x3"
|
||||
+ register "sata_port_map" = "0x3b"
|
||||
+ register "spi_lvscc" = "0x2005"
|
||||
+ register "spi_uvscc" = "0x2005"
|
||||
+
|
||||
+ device ref mei1 off end
|
||||
+ device ref mei2 off end
|
||||
+ device ref me_ide_r off end
|
||||
+ device ref me_kt off end
|
||||
+ device ref gbe on end
|
||||
+ device ref ehci2 on end
|
||||
+ device ref hda on end
|
||||
+ device ref pcie_rp1 on end
|
||||
+ device ref pcie_rp2 on end
|
||||
+ device ref pcie_rp3 on end
|
||||
+ device ref pcie_rp4 on end
|
||||
+ device ref pcie_rp5 off end
|
||||
+ device ref pcie_rp6 on end
|
||||
+ device ref pcie_rp7 off end
|
||||
+ device ref pcie_rp8 off end
|
||||
+ device ref ehci1 on end
|
||||
+ device ref pci_bridge off end
|
||||
+ device ref lpc on
|
||||
+ chip ec/dell/mec5035
|
||||
+ device pnp ff.0 on end
|
||||
+ end
|
||||
+ end
|
||||
+ device ref sata1 on end
|
||||
+ device ref smbus on end
|
||||
+ device ref sata2 off end
|
||||
+ device ref thermal off end
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/e6420/dsdt.asl b/src/mainboard/dell/e6420/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..7d13c55b08
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/dsdt.asl
|
||||
@@ -0,0 +1,30 @@
|
||||
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20141018 /* OEM revision */
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+ #include "acpi/platform.asl"
|
||||
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6420/early_init.c b/src/mainboard/dell/e6420/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..0682441ed6
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/early_init.c
|
||||
@@ -0,0 +1,32 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <bootblock_common.h>
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <ec/dell/mec5035/mec5035.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 0, 2 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 1, 3 },
|
||||
+ { 1, 1, 3 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 7 },
|
||||
+ { 1, 1, 6 },
|
||||
+ { 1, 0, 6 },
|
||||
+ { 1, 0, 7 },
|
||||
+};
|
||||
+
|
||||
+void bootblock_mainboard_early_init(void)
|
||||
+{
|
||||
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
|
||||
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
|
||||
+ | COMB_LPC_EN | COMA_LPC_EN);
|
||||
+ mec5035_early_init();
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6420/gma-mainboard.ads b/src/mainboard/dell/e6420/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..2a16f44360
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/gma-mainboard.ads
|
||||
@@ -0,0 +1,20 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (
|
||||
+ HDMI1, -- mainboard HDMI
|
||||
+ DP2, -- dock DP
|
||||
+ DP3, -- dock DP
|
||||
+ Analog, -- mainboard VGA
|
||||
+ LVDS,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/e6420/gpio.c b/src/mainboard/dell/e6420/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..943c743f48
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/gpio.c
|
||||
@@ -0,0 +1,191 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_GPIO,
|
||||
+ .gpio1 = GPIO_MODE_NATIVE,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_NATIVE,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_NATIVE,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_GPIO,
|
||||
+ .gpio16 = GPIO_MODE_GPIO,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_GPIO,
|
||||
+ .gpio31 = GPIO_MODE_GPIO,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio0 = GPIO_DIR_INPUT,
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio15 = GPIO_DIR_INPUT,
|
||||
+ .gpio16 = GPIO_DIR_INPUT,
|
||||
+ .gpio17 = GPIO_DIR_INPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_INPUT,
|
||||
+ .gpio29 = GPIO_DIR_INPUT,
|
||||
+ .gpio30 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio31 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio30 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio0 = GPIO_INVERT,
|
||||
+ .gpio8 = GPIO_INVERT,
|
||||
+ .gpio14 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_NATIVE,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_GPIO,
|
||||
+ .gpio46 = GPIO_MODE_NATIVE,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_GPIO,
|
||||
+ .gpio52 = GPIO_MODE_GPIO,
|
||||
+ .gpio53 = GPIO_MODE_NATIVE,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_NATIVE,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio35 = GPIO_DIR_INPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio45 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio51 = GPIO_DIR_INPUT,
|
||||
+ .gpio52 = GPIO_DIR_INPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio34 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio45 = GPIO_LEVEL_LOW,
|
||||
+ .gpio49 = GPIO_LEVEL_LOW,
|
||||
+ .gpio60 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_GPIO,
|
||||
+ .gpio69 = GPIO_MODE_GPIO,
|
||||
+ .gpio70 = GPIO_MODE_GPIO,
|
||||
+ .gpio71 = GPIO_MODE_GPIO,
|
||||
+ .gpio72 = GPIO_MODE_NATIVE,
|
||||
+ .gpio73 = GPIO_MODE_NATIVE,
|
||||
+ .gpio74 = GPIO_MODE_NATIVE,
|
||||
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio68 = GPIO_DIR_INPUT,
|
||||
+ .gpio69 = GPIO_DIR_INPUT,
|
||||
+ .gpio70 = GPIO_DIR_INPUT,
|
||||
+ .gpio71 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ .reset = &pch_gpio_set1_reset,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ .reset = &pch_gpio_set2_reset,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ .reset = &pch_gpio_set3_reset,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/e6420/hda_verb.c b/src/mainboard/dell/e6420/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..b3803b7c65
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/hda_verb.c
|
||||
@@ -0,0 +1,33 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
|
||||
+ 0x10280493, /* Subsystem ID */
|
||||
+ 11, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(0, 0x10280493),
|
||||
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
|
||||
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
|
||||
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
||||
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
||||
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
||||
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
|
||||
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
|
||||
+
|
||||
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
|
||||
+ 0x80860101, /* Subsystem ID */
|
||||
+ 4, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
+
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/e6420/mainboard.c b/src/mainboard/dell/e6420/mainboard.c
|
||||
new file mode 100644
|
||||
index 0000000000..31e49802fc
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6420/mainboard.c
|
||||
@@ -0,0 +1,21 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/device.h>
|
||||
+#include <drivers/intel/gma/int15.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+#include <ec/acpi/ec.h>
|
||||
+#include <console/console.h>
|
||||
+#include <pc80/keyboard.h>
|
||||
+
|
||||
+static void mainboard_enable(struct device *dev)
|
||||
+{
|
||||
+
|
||||
+ /* FIXME: fix these values. */
|
||||
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
+}
|
||||
+
|
||||
+struct chip_operations mainboard_ops = {
|
||||
+ .enable_dev = mainboard_enable,
|
||||
+};
|
||||
--
|
||||
2.43.0
|
||||
|
||||
@@ -0,0 +1,773 @@
|
||||
From 5e8bff81220d4d0f663feed443e4594b76e442bf Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Wed, 31 Jan 2024 22:07:25 -0700
|
||||
Subject: [PATCH] mb/dell: Add Latitude E6520 (Sandy Bridge)
|
||||
|
||||
Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/e6520/Kconfig | 38 +++++
|
||||
src/mainboard/dell/e6520/Kconfig.name | 2 +
|
||||
src/mainboard/dell/e6520/Makefile.inc | 6 +
|
||||
src/mainboard/dell/e6520/acpi/ec.asl | 9 +
|
||||
src/mainboard/dell/e6520/acpi/platform.asl | 12 ++
|
||||
src/mainboard/dell/e6520/acpi/superio.asl | 3 +
|
||||
src/mainboard/dell/e6520/acpi_tables.c | 16 ++
|
||||
src/mainboard/dell/e6520/board_info.txt | 6 +
|
||||
src/mainboard/dell/e6520/cmos.default | 9 +
|
||||
src/mainboard/dell/e6520/cmos.layout | 88 ++++++++++
|
||||
src/mainboard/dell/e6520/data.vbt | Bin 0 -> 6144 bytes
|
||||
src/mainboard/dell/e6520/devicetree.cb | 66 +++++++
|
||||
src/mainboard/dell/e6520/dsdt.asl | 30 ++++
|
||||
src/mainboard/dell/e6520/early_init.c | 32 ++++
|
||||
src/mainboard/dell/e6520/gma-mainboard.ads | 20 +++
|
||||
src/mainboard/dell/e6520/gpio.c | 190 +++++++++++++++++++++
|
||||
src/mainboard/dell/e6520/hda_verb.c | 33 ++++
|
||||
src/mainboard/dell/e6520/mainboard.c | 21 +++
|
||||
18 files changed, 581 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/e6520/Kconfig
|
||||
create mode 100644 src/mainboard/dell/e6520/Kconfig.name
|
||||
create mode 100644 src/mainboard/dell/e6520/Makefile.inc
|
||||
create mode 100644 src/mainboard/dell/e6520/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/dell/e6520/acpi/platform.asl
|
||||
create mode 100644 src/mainboard/dell/e6520/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/dell/e6520/acpi_tables.c
|
||||
create mode 100644 src/mainboard/dell/e6520/board_info.txt
|
||||
create mode 100644 src/mainboard/dell/e6520/cmos.default
|
||||
create mode 100644 src/mainboard/dell/e6520/cmos.layout
|
||||
create mode 100644 src/mainboard/dell/e6520/data.vbt
|
||||
create mode 100644 src/mainboard/dell/e6520/devicetree.cb
|
||||
create mode 100644 src/mainboard/dell/e6520/dsdt.asl
|
||||
create mode 100644 src/mainboard/dell/e6520/early_init.c
|
||||
create mode 100644 src/mainboard/dell/e6520/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/e6520/gpio.c
|
||||
create mode 100644 src/mainboard/dell/e6520/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/e6520/mainboard.c
|
||||
|
||||
diff --git a/src/mainboard/dell/e6520/Kconfig b/src/mainboard/dell/e6520/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..db9f25b4ac
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/Kconfig
|
||||
@@ -0,0 +1,38 @@
|
||||
+if BOARD_DELL_LATITUDE_E6520
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS
|
||||
+ def_bool y
|
||||
+ select BOARD_ROMSIZE_KB_10240
|
||||
+ select EC_ACPI
|
||||
+ select EC_DELL_MEC5035
|
||||
+ select GFX_GMA_PANEL_1_ON_LVDS
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select INTEL_INT15
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select MAINBOARD_USES_IFD_GBE_REGION
|
||||
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
|
||||
+ select SERIRQ_CONTINUOUS_MODE
|
||||
+ select SOUTHBRIDGE_INTEL_BD82X6X
|
||||
+ select SYSTEM_TYPE_LAPTOP
|
||||
+ select USE_NATIVE_RAMINIT
|
||||
+
|
||||
+config DRAM_RESET_GATE_GPIO
|
||||
+ default 60
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "dell/e6520"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "Latitude E6520"
|
||||
+
|
||||
+config USBDEBUG_HCD_INDEX
|
||||
+ default 2
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,0116"
|
||||
+
|
||||
+endif # BOARD_DELL_LATITUDE_E6520
|
||||
diff --git a/src/mainboard/dell/e6520/Kconfig.name b/src/mainboard/dell/e6520/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..25968e80e5
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/Kconfig.name
|
||||
@@ -0,0 +1,2 @@
|
||||
+config BOARD_DELL_LATITUDE_E6520
|
||||
+ bool "Latitude E6520"
|
||||
diff --git a/src/mainboard/dell/e6520/Makefile.inc b/src/mainboard/dell/e6520/Makefile.inc
|
||||
new file mode 100644
|
||||
index 0000000000..ba64e93eb8
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/Makefile.inc
|
||||
@@ -0,0 +1,6 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only
|
||||
+bootblock-y += early_init.c
|
||||
+bootblock-y += gpio.c
|
||||
+romstage-y += early_init.c
|
||||
+romstage-y += gpio.c
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
diff --git a/src/mainboard/dell/e6520/acpi/ec.asl b/src/mainboard/dell/e6520/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..0d429410a9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/acpi/ec.asl
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Device(EC)
|
||||
+{
|
||||
+ Name (_HID, EISAID("PNP0C09"))
|
||||
+ Name (_UID, 0)
|
||||
+ Name (_GPE, 16)
|
||||
+/* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6520/acpi/platform.asl b/src/mainboard/dell/e6520/acpi/platform.asl
|
||||
new file mode 100644
|
||||
index 0000000000..2d24bbd9b9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/acpi/platform.asl
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Method(_WAK, 1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+ Return(Package() {0, 0})
|
||||
+}
|
||||
+
|
||||
+Method(_PTS,1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6520/acpi/superio.asl b/src/mainboard/dell/e6520/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..55b1db5b11
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/acpi/superio.asl
|
||||
@@ -0,0 +1,3 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
diff --git a/src/mainboard/dell/e6520/acpi_tables.c b/src/mainboard/dell/e6520/acpi_tables.c
|
||||
new file mode 100644
|
||||
index 0000000000..e2759659bf
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/acpi_tables.c
|
||||
@@ -0,0 +1,16 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi_gnvs.h>
|
||||
+#include <soc/nvs.h>
|
||||
+
|
||||
+/* FIXME: check this function. */
|
||||
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
|
||||
+{
|
||||
+ /* The lid is open by default. */
|
||||
+ gnvs->lids = 1;
|
||||
+
|
||||
+ /* Temperature at which OS will shutdown */
|
||||
+ gnvs->tcrt = 100;
|
||||
+ /* Temperature at which OS will throttle CPU */
|
||||
+ gnvs->tpsv = 90;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6520/board_info.txt b/src/mainboard/dell/e6520/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..34d5ad9e0b
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/board_info.txt
|
||||
@@ -0,0 +1,6 @@
|
||||
+Category: laptop
|
||||
+ROM package: SOIC-8
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
+Release year: 2011
|
||||
diff --git a/src/mainboard/dell/e6520/cmos.default b/src/mainboard/dell/e6520/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..279415dfd1
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/cmos.default
|
||||
@@ -0,0 +1,9 @@
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Disable
|
||||
+nmi=Enable
|
||||
+bluetooth=Enable
|
||||
+wwan=Enable
|
||||
+wlan=Enable
|
||||
+sata_mode=AHCI
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/dell/e6520/cmos.layout b/src/mainboard/dell/e6520/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..1aa7e77bce
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/cmos.layout
|
||||
@@ -0,0 +1,88 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+
|
||||
+#400 8 r 0 reserved for century byte
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 1 nmi
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+411 1 e 9 sata_mode
|
||||
+
|
||||
+# coreboot config options: EC
|
||||
+412 1 e 1 bluetooth
|
||||
+413 1 e 1 wwan
|
||||
+414 1 e 1 wlan
|
||||
+
|
||||
+# coreboot config options: ME
|
||||
+424 1 e 14 me_state
|
||||
+425 2 h 0 me_state_prev
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 3 e 11 gfx_uma_size
|
||||
+435 2 e 12 hybrid_graphics_mode
|
||||
+440 8 h 0 volume
|
||||
+
|
||||
+# VBOOT
|
||||
+448 128 r 0 vbnv
|
||||
+
|
||||
+# SandyBridge MRC Scrambler Seed values
|
||||
+896 32 r 0 mrc_scrambler_seed
|
||||
+928 32 r 0 mrc_scrambler_seed_s3
|
||||
+960 16 r 0 mrc_scrambler_seed_chk
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+9 0 AHCI
|
||||
+9 1 Compatible
|
||||
+11 0 32M
|
||||
+11 1 64M
|
||||
+11 2 96M
|
||||
+11 3 128M
|
||||
+11 4 160M
|
||||
+11 5 192M
|
||||
+11 6 224M
|
||||
+14 0 Normal
|
||||
+14 1 Disabled
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 447 984
|
||||
diff --git a/src/mainboard/dell/e6520/data.vbt b/src/mainboard/dell/e6520/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
|
||||
GIT binary patch
|
||||
literal 6144
|
||||
zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN)
|
||||
z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y
|
||||
z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+
|
||||
z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7
|
||||
zcXx+--0R}IwzW3-+`f2k?^Av5V7MpRO-q(9rn_R1@Xlz2Ztdy`$Gf6^w6~|bKi!!7
|
||||
z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ
|
||||
z)4V8f0Gt`D`+>9Fr~tnJ76EJ`5D_F1cn-`0$RgN9unI6kfYkzIiO?W`ON4+34lv1_
|
||||
zNdPDkq1cf$p8^EW;TS*O$CdzNo#1fbIG_Oi0T(ti0jwyt0le_p_HlvX^CFvr)>$b>
|
||||
zO-z8^CSU`w=mIK7Q)@9fR;XUzrFu{T=rRyygIZBpU9+Or>+?4R9%~G?Y-|g)Z`Sti
|
||||
z+do(U*Wb-xR~DzjS<75#=Us4sH^C9U2FCbND7L7u$>M|<;t=AnRfI9C0v8c~AVg7t
|
||||
zIU<3D2oK^>L;%r(*o=4*u?Mja@dDyi#4zFn;(f#^#3*76aUSs#;tJv#La-6YLRdQB
|
||||
zdcvfERkvH?k~GJlfM<HR476j(@nfm+47<!Ult@^ua5M3h6A}q=C0ognX9aX4mxq)U
|
||||
zXOhm=DbLene?C%_16Q)2NRV@Yacz`D;{V>Ve-1?&ZXy}n)YwnVAgNlz#zX;=IX)-F
|
||||
z)9LL3lbEdY5Co)LsK?vP)7s}G(5xduE!Y!#Wgh<IN3(3ey=-oWU(9aEJ_HzV53Jbq
|
||||
zj5B5RjzLUt>_T&xi$uUA#0e}X3D~`J(bHz;DgTa@GrpW6=>eZwJeNYYo*GjF=``;(
|
||||
zuoQ3|V5YoKd$j=KK{`uSX*DeU1oJg=+RT6)rLe6%2>Ci^!5ao=*gS}wFN=nUf`fTF
|
||||
zM?Gb5ycWjM7I?MJ!2;w|LFg=UoLq-ytr2iemG)AsW}bI4X9PK}T5UKsQi7anu=tD6
|
||||
zf|={kXkNeQBD>6bQ3taC8XJOJ^e40_ydyfr&a41L^1)jNrK<B_wV}+ZE`p;QK=rDz
|
||||
zTw`SJ+e`Oc*icaF4INF51Xg*~ts@m)@9ETt(*@N7yy0)Ddce%i9{^k2kbd8=Wns~P
|
||||
zWBD$~himxDharxF@f!ti^0$~9Zxt{tg`@Dbl_0Ki2Xp_MEw-<z6qgep;XYmR%Dl-F
|
||||
z%3cBfcN;Avikpz-gmw_6mymu!Unk0YgnUfsk3{*6kQ;=S*p(_fS!JhDyYh^k?6uRk
|
||||
z?8--W@~NHvY*+ra6SG9iC1s^V)<|@Rqzp*pd5NBslrs`JC(&Oeg~v}CnJ$x+)iP<8
|
||||
z=`LA0Ad@39{XkZ}kjXbP{YzHtS!70*yy%LcnJ#cz4u%*Wq!^d*AVMZdr&l=#Qgik~
|
||||
ze2l)cX+!kF9EaFhY;0^Uo_#VNC?7K2Tf=ZR1y5);b!mCGG?<cc#M0rtHKYeKi%BE?
|
||||
z@Y6|P8fx#li}c`Uv24UGyZaM0To;Ep<_AWZA1t~bFgI)uf}&Eq=L_Cs89=>wnT0Vx
|
||||
z-jp>o1ffJNommZ4?=TIPlePIw0hgQ706f*tBC`#pg>9&zRHe>J2%RxBTrOc6Adh9E
|
||||
ziJr`?VQH!N!_GkoKaoq|+3$^Ae0#sUxXlmM1Huq~g<=Ls?ILv+nQcH%PQedGOlH=Q
|
||||
z77rMcJlH4Mkc#U2(IDv>rsm1aHpsdL_RdT^i_ACcQUMIJcSus}*(?CIiy^#^=t=g1
|
||||
z+*^Zbh30&^#_bKclSy9pL$<B~pK8m*sLpIdnHM@W$nA7Ea@Z`x27K?aNK<@lCW(2L
|
||||
zb@kB3H8kKy4W3Hu)NN|kd!DL^o#iR9a{QYV-Wl&r&hmIFX{ezkIV<4zFiVUQ@K>ao
|
||||
z00DnFy~Uek!JRwhVX!of0)$Sa*X^S~LMQH0<E(UUx}L=|;Kgw(r(4q=nD)T52c|tR
|
||||
O?SW|zOncy=dEg(6JAK&z
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/e6520/devicetree.cb b/src/mainboard/dell/e6520/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..cfba8ef4e7
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/devicetree.cb
|
||||
@@ -0,0 +1,66 @@
|
||||
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
|
||||
+ register "gpu_cpu_backlight" = "0x00001312"
|
||||
+ register "gpu_dp_b_hotplug" = "4"
|
||||
+ register "gpu_dp_c_hotplug" = "4"
|
||||
+ register "gpu_dp_d_hotplug" = "4"
|
||||
+ register "gpu_panel_port_select" = "0"
|
||||
+ register "gpu_panel_power_backlight_off_delay" = "2300"
|
||||
+ register "gpu_panel_power_backlight_on_delay" = "2300"
|
||||
+ register "gpu_panel_power_cycle_delay" = "6"
|
||||
+ register "gpu_panel_power_down_delay" = "400"
|
||||
+ register "gpu_panel_power_up_delay" = "400"
|
||||
+ register "gpu_pch_backlight" = "0x13121312"
|
||||
+
|
||||
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
|
||||
+
|
||||
+ device domain 0x0 on
|
||||
+ subsystemid 0x1028 0x0494 inherit
|
||||
+
|
||||
+ device ref host_bridge on end # Host bridge
|
||||
+ device ref peg10 on end # PEG
|
||||
+ device ref igd on end # iGPU
|
||||
+
|
||||
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
+ register "docking_supported" = "1"
|
||||
+ register "gen1_dec" = "0x007c0681"
|
||||
+ register "gen2_dec" = "0x007c0901"
|
||||
+ register "gen3_dec" = "0x003c07e1"
|
||||
+ register "gen4_dec" = "0x001c0901"
|
||||
+ register "gpi0_routing" = "2"
|
||||
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
|
||||
+ register "pcie_port_coalesce" = "1"
|
||||
+ register "sata_interface_speed_support" = "0x3"
|
||||
+ register "sata_port_map" = "0x3b"
|
||||
+ register "spi_lvscc" = "0x2005"
|
||||
+ register "spi_uvscc" = "0x2005"
|
||||
+
|
||||
+ device ref mei1 off end
|
||||
+ device ref mei2 off end
|
||||
+ device ref me_ide_r off end
|
||||
+ device ref me_kt off end
|
||||
+ device ref gbe on end
|
||||
+ device ref ehci2 on end
|
||||
+ device ref hda on end
|
||||
+ device ref pcie_rp1 on end
|
||||
+ device ref pcie_rp2 on end
|
||||
+ device ref pcie_rp3 on end
|
||||
+ device ref pcie_rp4 on end
|
||||
+ device ref pcie_rp5 off end
|
||||
+ device ref pcie_rp6 on end
|
||||
+ device ref pcie_rp7 off end
|
||||
+ device ref pcie_rp8 off end
|
||||
+ device ref ehci1 on end
|
||||
+ device ref pci_bridge off end
|
||||
+ device ref lpc on
|
||||
+ chip ec/dell/mec5035
|
||||
+ device pnp ff.0 on end
|
||||
+ end
|
||||
+ end
|
||||
+ device ref sata1 on end
|
||||
+ device ref smbus on end
|
||||
+ device ref sata2 off end
|
||||
+ device ref thermal off end
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/e6520/dsdt.asl b/src/mainboard/dell/e6520/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..7d13c55b08
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/dsdt.asl
|
||||
@@ -0,0 +1,30 @@
|
||||
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20141018 /* OEM revision */
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+ #include "acpi/platform.asl"
|
||||
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6520/early_init.c b/src/mainboard/dell/e6520/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..2a37091df6
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/early_init.c
|
||||
@@ -0,0 +1,32 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <bootblock_common.h>
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <ec/dell/mec5035/mec5035.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 0, 2 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 0, 3 },
|
||||
+ { 1, 0, 3 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 7 },
|
||||
+ { 1, 1, 6 },
|
||||
+ { 1, 0, 6 },
|
||||
+ { 1, 0, 7 },
|
||||
+};
|
||||
+
|
||||
+void bootblock_mainboard_early_init(void)
|
||||
+{
|
||||
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
|
||||
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
|
||||
+ | COMB_LPC_EN | COMA_LPC_EN);
|
||||
+ mec5035_early_init();
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e6520/gma-mainboard.ads b/src/mainboard/dell/e6520/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..2a16f44360
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/gma-mainboard.ads
|
||||
@@ -0,0 +1,20 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (
|
||||
+ HDMI1, -- mainboard HDMI
|
||||
+ DP2, -- dock DP
|
||||
+ DP3, -- dock DP
|
||||
+ Analog, -- mainboard VGA
|
||||
+ LVDS,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/e6520/gpio.c b/src/mainboard/dell/e6520/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..61f01816c4
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/gpio.c
|
||||
@@ -0,0 +1,190 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_GPIO,
|
||||
+ .gpio1 = GPIO_MODE_NATIVE,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_NATIVE,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_NATIVE,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_NATIVE,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_GPIO,
|
||||
+ .gpio16 = GPIO_MODE_GPIO,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_GPIO,
|
||||
+ .gpio31 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio0 = GPIO_DIR_INPUT,
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio15 = GPIO_DIR_INPUT,
|
||||
+ .gpio16 = GPIO_DIR_INPUT,
|
||||
+ .gpio17 = GPIO_DIR_INPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_INPUT,
|
||||
+ .gpio29 = GPIO_DIR_INPUT,
|
||||
+ .gpio30 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio30 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio0 = GPIO_INVERT,
|
||||
+ .gpio8 = GPIO_INVERT,
|
||||
+ .gpio14 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_NATIVE,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_GPIO,
|
||||
+ .gpio46 = GPIO_MODE_NATIVE,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_GPIO,
|
||||
+ .gpio52 = GPIO_MODE_GPIO,
|
||||
+ .gpio53 = GPIO_MODE_NATIVE,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_NATIVE,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio35 = GPIO_DIR_INPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio45 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio51 = GPIO_DIR_INPUT,
|
||||
+ .gpio52 = GPIO_DIR_INPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio34 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio45 = GPIO_LEVEL_LOW,
|
||||
+ .gpio49 = GPIO_LEVEL_LOW,
|
||||
+ .gpio60 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_GPIO,
|
||||
+ .gpio69 = GPIO_MODE_GPIO,
|
||||
+ .gpio70 = GPIO_MODE_GPIO,
|
||||
+ .gpio71 = GPIO_MODE_GPIO,
|
||||
+ .gpio72 = GPIO_MODE_NATIVE,
|
||||
+ .gpio73 = GPIO_MODE_NATIVE,
|
||||
+ .gpio74 = GPIO_MODE_NATIVE,
|
||||
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio68 = GPIO_DIR_INPUT,
|
||||
+ .gpio69 = GPIO_DIR_INPUT,
|
||||
+ .gpio70 = GPIO_DIR_INPUT,
|
||||
+ .gpio71 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ .reset = &pch_gpio_set1_reset,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ .reset = &pch_gpio_set2_reset,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ .reset = &pch_gpio_set3_reset,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/e6520/hda_verb.c b/src/mainboard/dell/e6520/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..d33eb3b4c5
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/hda_verb.c
|
||||
@@ -0,0 +1,33 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
|
||||
+ 0x10280494, /* Subsystem ID */
|
||||
+ 11, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(0, 0x10280494),
|
||||
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
|
||||
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
|
||||
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
||||
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
||||
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
||||
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
|
||||
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
|
||||
+
|
||||
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
|
||||
+ 0x80860101, /* Subsystem ID */
|
||||
+ 4, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
+
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/e6520/mainboard.c b/src/mainboard/dell/e6520/mainboard.c
|
||||
new file mode 100644
|
||||
index 0000000000..31e49802fc
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e6520/mainboard.c
|
||||
@@ -0,0 +1,21 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/device.h>
|
||||
+#include <drivers/intel/gma/int15.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+#include <ec/acpi/ec.h>
|
||||
+#include <console/console.h>
|
||||
+#include <pc80/keyboard.h>
|
||||
+
|
||||
+static void mainboard_enable(struct device *dev)
|
||||
+{
|
||||
+
|
||||
+ /* FIXME: fix these values. */
|
||||
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
+}
|
||||
+
|
||||
+struct chip_operations mainboard_ops = {
|
||||
+ .enable_dev = mainboard_enable,
|
||||
+};
|
||||
--
|
||||
2.43.0
|
||||
|
||||
@@ -0,0 +1,780 @@
|
||||
From 86911e57c556389eed386bc23d5e87dd520afec9 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Wed, 31 Jan 2024 22:57:07 -0700
|
||||
Subject: [PATCH] mb/dell: Add Latitude E5530 (Ivy Bridge)
|
||||
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/e5530/Kconfig | 37 ++++
|
||||
src/mainboard/dell/e5530/Kconfig.name | 2 +
|
||||
src/mainboard/dell/e5530/Makefile.inc | 6 +
|
||||
src/mainboard/dell/e5530/acpi/ec.asl | 9 +
|
||||
src/mainboard/dell/e5530/acpi/platform.asl | 12 ++
|
||||
src/mainboard/dell/e5530/acpi/superio.asl | 3 +
|
||||
src/mainboard/dell/e5530/acpi_tables.c | 16 ++
|
||||
src/mainboard/dell/e5530/board_info.txt | 6 +
|
||||
src/mainboard/dell/e5530/cmos.default | 9 +
|
||||
src/mainboard/dell/e5530/cmos.layout | 88 ++++++++++
|
||||
src/mainboard/dell/e5530/data.vbt | Bin 0 -> 6144 bytes
|
||||
src/mainboard/dell/e5530/devicetree.cb | 70 ++++++++
|
||||
src/mainboard/dell/e5530/dsdt.asl | 30 ++++
|
||||
src/mainboard/dell/e5530/early_init.c | 32 ++++
|
||||
src/mainboard/dell/e5530/gma-mainboard.ads | 20 +++
|
||||
src/mainboard/dell/e5530/gpio.c | 194 +++++++++++++++++++++
|
||||
src/mainboard/dell/e5530/hda_verb.c | 33 ++++
|
||||
src/mainboard/dell/e5530/mainboard.c | 21 +++
|
||||
18 files changed, 588 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/e5530/Kconfig
|
||||
create mode 100644 src/mainboard/dell/e5530/Kconfig.name
|
||||
create mode 100644 src/mainboard/dell/e5530/Makefile.inc
|
||||
create mode 100644 src/mainboard/dell/e5530/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/dell/e5530/acpi/platform.asl
|
||||
create mode 100644 src/mainboard/dell/e5530/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/dell/e5530/acpi_tables.c
|
||||
create mode 100644 src/mainboard/dell/e5530/board_info.txt
|
||||
create mode 100644 src/mainboard/dell/e5530/cmos.default
|
||||
create mode 100644 src/mainboard/dell/e5530/cmos.layout
|
||||
create mode 100644 src/mainboard/dell/e5530/data.vbt
|
||||
create mode 100644 src/mainboard/dell/e5530/devicetree.cb
|
||||
create mode 100644 src/mainboard/dell/e5530/dsdt.asl
|
||||
create mode 100644 src/mainboard/dell/e5530/early_init.c
|
||||
create mode 100644 src/mainboard/dell/e5530/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/e5530/gpio.c
|
||||
create mode 100644 src/mainboard/dell/e5530/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/e5530/mainboard.c
|
||||
|
||||
diff --git a/src/mainboard/dell/e5530/Kconfig b/src/mainboard/dell/e5530/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..3faae4ee50
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/Kconfig
|
||||
@@ -0,0 +1,37 @@
|
||||
+if BOARD_DELL_LATITUDE_E5530
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS
|
||||
+ def_bool y
|
||||
+ select BOARD_ROMSIZE_KB_12288
|
||||
+ select EC_ACPI
|
||||
+ select EC_DELL_MEC5035
|
||||
+ select GFX_GMA_PANEL_1_ON_LVDS
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select INTEL_INT15
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
|
||||
+ select SERIRQ_CONTINUOUS_MODE
|
||||
+ select SOUTHBRIDGE_INTEL_C216
|
||||
+ select SYSTEM_TYPE_LAPTOP
|
||||
+ select USE_NATIVE_RAMINIT
|
||||
+
|
||||
+config DRAM_RESET_GATE_GPIO
|
||||
+ default 60
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "dell/e5530"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "Latitude E5530"
|
||||
+
|
||||
+config USBDEBUG_HCD_INDEX
|
||||
+ default 2
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,0166"
|
||||
+
|
||||
+endif # BOARD_DELL_LATITUDE_E5530
|
||||
diff --git a/src/mainboard/dell/e5530/Kconfig.name b/src/mainboard/dell/e5530/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..775963204a
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/Kconfig.name
|
||||
@@ -0,0 +1,2 @@
|
||||
+config BOARD_DELL_LATITUDE_E5530
|
||||
+ bool "Latitude E5530"
|
||||
diff --git a/src/mainboard/dell/e5530/Makefile.inc b/src/mainboard/dell/e5530/Makefile.inc
|
||||
new file mode 100644
|
||||
index 0000000000..ba64e93eb8
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/Makefile.inc
|
||||
@@ -0,0 +1,6 @@
|
||||
+# SPDX-License-Identifier: GPL-2.0-only
|
||||
+bootblock-y += early_init.c
|
||||
+bootblock-y += gpio.c
|
||||
+romstage-y += early_init.c
|
||||
+romstage-y += gpio.c
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
diff --git a/src/mainboard/dell/e5530/acpi/ec.asl b/src/mainboard/dell/e5530/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..0d429410a9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/acpi/ec.asl
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Device(EC)
|
||||
+{
|
||||
+ Name (_HID, EISAID("PNP0C09"))
|
||||
+ Name (_UID, 0)
|
||||
+ Name (_GPE, 16)
|
||||
+/* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5530/acpi/platform.asl b/src/mainboard/dell/e5530/acpi/platform.asl
|
||||
new file mode 100644
|
||||
index 0000000000..2d24bbd9b9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/acpi/platform.asl
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Method(_WAK, 1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+ Return(Package() {0, 0})
|
||||
+}
|
||||
+
|
||||
+Method(_PTS,1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5530/acpi/superio.asl b/src/mainboard/dell/e5530/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..55b1db5b11
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/acpi/superio.asl
|
||||
@@ -0,0 +1,3 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
diff --git a/src/mainboard/dell/e5530/acpi_tables.c b/src/mainboard/dell/e5530/acpi_tables.c
|
||||
new file mode 100644
|
||||
index 0000000000..e2759659bf
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/acpi_tables.c
|
||||
@@ -0,0 +1,16 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi_gnvs.h>
|
||||
+#include <soc/nvs.h>
|
||||
+
|
||||
+/* FIXME: check this function. */
|
||||
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
|
||||
+{
|
||||
+ /* The lid is open by default. */
|
||||
+ gnvs->lids = 1;
|
||||
+
|
||||
+ /* Temperature at which OS will shutdown */
|
||||
+ gnvs->tcrt = 100;
|
||||
+ /* Temperature at which OS will throttle CPU */
|
||||
+ gnvs->tpsv = 90;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5530/board_info.txt b/src/mainboard/dell/e5530/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..4601a4aaba
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/board_info.txt
|
||||
@@ -0,0 +1,6 @@
|
||||
+Category: laptop
|
||||
+ROM package: SOIC-8
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
+Release year: 2012
|
||||
diff --git a/src/mainboard/dell/e5530/cmos.default b/src/mainboard/dell/e5530/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..279415dfd1
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/cmos.default
|
||||
@@ -0,0 +1,9 @@
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Disable
|
||||
+nmi=Enable
|
||||
+bluetooth=Enable
|
||||
+wwan=Enable
|
||||
+wlan=Enable
|
||||
+sata_mode=AHCI
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/dell/e5530/cmos.layout b/src/mainboard/dell/e5530/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..1aa7e77bce
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/cmos.layout
|
||||
@@ -0,0 +1,88 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+
|
||||
+#400 8 r 0 reserved for century byte
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 1 nmi
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+411 1 e 9 sata_mode
|
||||
+
|
||||
+# coreboot config options: EC
|
||||
+412 1 e 1 bluetooth
|
||||
+413 1 e 1 wwan
|
||||
+414 1 e 1 wlan
|
||||
+
|
||||
+# coreboot config options: ME
|
||||
+424 1 e 14 me_state
|
||||
+425 2 h 0 me_state_prev
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 3 e 11 gfx_uma_size
|
||||
+435 2 e 12 hybrid_graphics_mode
|
||||
+440 8 h 0 volume
|
||||
+
|
||||
+# VBOOT
|
||||
+448 128 r 0 vbnv
|
||||
+
|
||||
+# SandyBridge MRC Scrambler Seed values
|
||||
+896 32 r 0 mrc_scrambler_seed
|
||||
+928 32 r 0 mrc_scrambler_seed_s3
|
||||
+960 16 r 0 mrc_scrambler_seed_chk
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+9 0 AHCI
|
||||
+9 1 Compatible
|
||||
+11 0 32M
|
||||
+11 1 64M
|
||||
+11 2 96M
|
||||
+11 3 128M
|
||||
+11 4 160M
|
||||
+11 5 192M
|
||||
+11 6 224M
|
||||
+14 0 Normal
|
||||
+14 1 Disabled
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 447 984
|
||||
diff --git a/src/mainboard/dell/e5530/data.vbt b/src/mainboard/dell/e5530/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3
|
||||
GIT binary patch
|
||||
literal 6144
|
||||
zcmeHKU2Gdg5dO}0w$JA~+qs02q)iz56C9e5vuQ#oL0l3O+%|395Q2peO{y4(2uX0t
|
||||
zuMja1N)bPb1cE+5)fYsCK!89MFQAGChyWpk5PuR<K|G+sLmxmOR4}u5=Rg`mj70g7
|
||||
zvgdDic6N4dW^QKhynd)>kS^cR)3#-(r*-?zo-O^C(kLvv8XM<+Y3tdt^YY!P?!oTe
|
||||
zJ^ed-x6w0Lh5fN#jsv5TWE#mtd*_yky}9xDK(kOwLt+C7_AQAd#iwr=o0`gvQZ`{x
|
||||
z6ZeT`x^^;8+a~jSa^o~PF@8J6N5;o#dhCwebaM;!_oisw1#O9K={qQM<@Oeu$lXeN
|
||||
z#wJGcW4Y<2)-A{Bot(NoKX%>qdnw-AOi9bKT9Z~HL5|7PJDHz4kGlEx143q+26EH6
|
||||
z{4KfB^9;?<fTOaiNPy%=@LovL&q<^d1Qdi+Xex9SvIM^ZLq%9cP{A1rE>#dw(WfA;
|
||||
zBCR3@pCS1a;A|CZW1h7H*l#mW{%y{bf)9ofiz!EHzyiac@{RpMzz>O-<~{hx5tw%b
|
||||
z3ZJWD4_g-`iF`tUJb}+Vfe;XI1T2Y4_Y!iVk<<T4ce(^PWKh<?N^a`t+}vgNr25iZ
|
||||
z`!fTBL)ojYF5G?3y|eW=`9>MLB9et&!A7LDDE7&5ye#|hn%s#IWgagDEPNHHMUhb-
|
||||
ztc9t?uz{bD#kh#kpsE;AO-wWHV?4olPStRPag^~k<737bjBgm<GlC%vRgBe)4U9I%
|
||||
zg^XUtcE**A5ylOSn;A2V2N;hso?--U#>t|ufS}_`LGs2bcSKCVBh4s0>G7ZR_@NWx
|
||||
zkph}GhP}~YR?roT!61GqzQ?gBsuv3jY}UXbmr|alv^VxUqbz5<`5=!hhpaa*7DK~4
|
||||
zP4ad6dhH!>nYpc4{J&G-w{UiWo$zXnTz{tAq0|?c_`QJ7pKmCwIpe7Uix$P?9}v*1
|
||||
z(aVR6OkMkQ6oM}*UC@j78!~>7=OZCVYXeu|u0SiI4}w$uw6&0P09LF%Hp}O&IA3gl
|
||||
z4@ap0NfAe+q(ZVm{Bwe*Do~kbCc$Q!x7b3Sk9tLgVmsR<Q4H=9Nl;mmf2xpY<*d*-
|
||||
z`yI_BR#`La=Oxxt#qgS`3pER^nh^CZ%*qlq2N9@uSAtz-C7AhduB_U|{>#oOrY`tq
|
||||
z%|?L!zRd2-$V6^@$H<Mj3MXf#F<J+^8%<X2{tnmQTI*aK*ageBrm9^|<Ked3j_s;%
|
||||
zva<(Dob)BOwdcj8Z67UhYUAjbk==Of9W#D7k!DJobLx$$fXD_wuZyD&Kk-$EIY~S`
|
||||
zan1ANbFUW8hZ0pUw5)y??*}!;chdgq|0X5;s;m`@YdY{zs4z#z8e;13T6b4tC7gy$
|
||||
zTwszEQhk0!U$`3=Qi)ZbY^*|bAyvF>@ml^iaX;uzoVB3JA(|h9tcNKXHdA43N0|18
|
||||
z&3$2QE=)(l=6qQDAWT1oO-<KoblR+&{kk@!)1A8ch^`&b>2=+FU)Mg<35IDJ+8Tp;
|
||||
z40F)Xt}$rVFdsLxLk7KRn4cKhmj<a3vp%A&kI>eLd38j)HbM_Y%!3i_aD?8An8za8
|
||||
z@d(AD=Gv&%5;e{}p%i?_q(T*^IwzEx*Eu1wKHV9=lVUvjqv!B@cWER!2fe%`IqO?q
|
||||
z!=Wf4kzGUaLX8`m#*P^uL?%M#6qc9Qu(YT|ZMb#7UzCc_(DkQYEG<G&Q*QkX`CS`I
|
||||
z8cwQnl8A#CMH~W79L&{2*Jof_MD5t{bPTAszWUa20yPzD=*wW8)wHSu?avDhffu^!
|
||||
zL>Q#%k_O0@^DN5S@MXi$D;acJ>#cTV-(U@Offv4ACp4hO4$Ll!WO)s3P4=t9vpWBC
|
||||
zSckhlcD?xUuX=Gx96Dx{IsQ23r&;o1*+^Cp2RA3nd$A-RIHP2Q7uitC>c67FIR*5}
|
||||
zB3a%B!?6K=TJ$W+SJv@*9Lms{mTvWmU4Zanj_Z*lSqOGISzYp?yawOqLhVhRt#-E6
|
||||
zd)YW~h&meh-5prIE}Cr&7f?MMi&cqTt_^%Fa?>k(=`9jVoIf@}{g+WX#TpWuc+!2v
|
||||
zPG^>A|NZ2GlGsKdGqN{7>Fr7+Hc_^3z}uBhC4?nzOQ*!QyVugGjkK_~$bvtfY`h79
|
||||
z9rOI3;Mt}9)_G{zXTAPw`8T@6=Ut0r9R5;0#Zy|#8F;v4^UAmqft3iXL|`QXD-l?U
|
||||
Jz~2*rUjdP?m;3+#
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/e5530/devicetree.cb b/src/mainboard/dell/e5530/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..2af748cf27
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/devicetree.cb
|
||||
@@ -0,0 +1,70 @@
|
||||
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
|
||||
+ register "gpu_cpu_backlight" = "0x00000000"
|
||||
+ register "gpu_dp_b_hotplug" = "4"
|
||||
+ register "gpu_dp_c_hotplug" = "4"
|
||||
+ register "gpu_dp_d_hotplug" = "4"
|
||||
+ register "gpu_panel_port_select" = "0"
|
||||
+ register "gpu_panel_power_backlight_off_delay" = "2300"
|
||||
+ register "gpu_panel_power_backlight_on_delay" = "2300"
|
||||
+ register "gpu_panel_power_cycle_delay" = "6"
|
||||
+ register "gpu_panel_power_down_delay" = "400"
|
||||
+ register "gpu_panel_power_up_delay" = "400"
|
||||
+ register "gpu_pch_backlight" = "0x03d003d0"
|
||||
+
|
||||
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
|
||||
+
|
||||
+ device domain 0x0 on
|
||||
+ subsystemid 0x1028 0x053d inherit
|
||||
+
|
||||
+ device ref host_bridge on end
|
||||
+ device ref peg10 off end
|
||||
+ device ref igd on end
|
||||
+
|
||||
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
+ register "docking_supported" = "1"
|
||||
+ register "gen1_dec" = "0x007c0681"
|
||||
+ register "gen2_dec" = "0x005c0921"
|
||||
+ register "gen3_dec" = "0x003c07e1"
|
||||
+ register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
|
||||
+ register "gpi0_routing" = "2"
|
||||
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
|
||||
+ register "pcie_port_coalesce" = "1"
|
||||
+ register "sata_interface_speed_support" = "0x3"
|
||||
+ register "sata_port_map" = "0x33"
|
||||
+ register "spi_lvscc" = "0x2005"
|
||||
+ register "spi_uvscc" = "0x2005"
|
||||
+ register "superspeed_capable_ports" = "0x0000000f"
|
||||
+ register "xhci_overcurrent_mapping" = "0x00000c03"
|
||||
+ register "xhci_switchable_ports" = "0x0000000f"
|
||||
+
|
||||
+ device ref xhci on end
|
||||
+ device ref mei1 off end
|
||||
+ device ref mei2 off end
|
||||
+ device ref me_ide_r off end
|
||||
+ device ref me_kt off end
|
||||
+ device ref gbe off end
|
||||
+ device ref ehci2 on end
|
||||
+ device ref hda on end
|
||||
+ device ref pcie_rp1 on end # WWAN Slot
|
||||
+ device ref pcie_rp2 on end # SLAN Slot
|
||||
+ device ref pcie_rp3 on end # ExpressCard
|
||||
+ device ref pcie_rp4 off end
|
||||
+ device ref pcie_rp5 on end # Extra Half Mini PCIe slot
|
||||
+ device ref pcie_rp6 on end # SD/MMC Card Reader
|
||||
+ device ref pcie_rp7 on end # BCM5761 Ethernet
|
||||
+ device ref pcie_rp8 off end
|
||||
+ device ref ehci1 on end
|
||||
+ device ref pci_bridge off end
|
||||
+ device ref lpc on
|
||||
+ chip ec/dell/mec5035
|
||||
+ device pnp ff.0 on end
|
||||
+ end
|
||||
+ end
|
||||
+ device ref sata1 on end
|
||||
+ device ref smbus on end
|
||||
+ device ref sata2 off end
|
||||
+ device ref thermal off end
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/e5530/dsdt.asl b/src/mainboard/dell/e5530/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..7d13c55b08
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/dsdt.asl
|
||||
@@ -0,0 +1,30 @@
|
||||
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20141018 /* OEM revision */
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+ #include "acpi/platform.asl"
|
||||
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5530/early_init.c b/src/mainboard/dell/e5530/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..00fd5f6795
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/early_init.c
|
||||
@@ -0,0 +1,32 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <bootblock_common.h>
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <ec/dell/mec5035/mec5035.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 1, 3 },
|
||||
+ { 1, 0, 3 },
|
||||
+ { 1, 2, 4 },
|
||||
+ { 1, 1, 4 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 0, 6 },
|
||||
+ { 1, 1, 6 },
|
||||
+};
|
||||
+
|
||||
+void bootblock_mainboard_early_init(void)
|
||||
+{
|
||||
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
|
||||
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
|
||||
+ | COMB_LPC_EN | COMA_LPC_EN);
|
||||
+ mec5035_early_init();
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5530/gma-mainboard.ads b/src/mainboard/dell/e5530/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..1310830c8e
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/gma-mainboard.ads
|
||||
@@ -0,0 +1,20 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (
|
||||
+ HDMI1, -- mainboard HDMI
|
||||
+ DP2, -- dock DP
|
||||
+ DP3, -- dock DP
|
||||
+ Analog, --mainboard VGA
|
||||
+ LVDS,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/e5530/gpio.c b/src/mainboard/dell/e5530/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..0599f13921
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/gpio.c
|
||||
@@ -0,0 +1,194 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_GPIO,
|
||||
+ .gpio1 = GPIO_MODE_GPIO,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_GPIO,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_NATIVE,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_GPIO,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_GPIO,
|
||||
+ .gpio16 = GPIO_MODE_GPIO,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_NATIVE,
|
||||
+ .gpio31 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio0 = GPIO_DIR_INPUT,
|
||||
+ .gpio1 = GPIO_DIR_INPUT,
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio3 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio12 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio15 = GPIO_DIR_INPUT,
|
||||
+ .gpio16 = GPIO_DIR_INPUT,
|
||||
+ .gpio17 = GPIO_DIR_INPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio29 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio12 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio28 = GPIO_LEVEL_LOW,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
+ .gpio30 = GPIO_RESET_RSMRST,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio0 = GPIO_INVERT,
|
||||
+ .gpio8 = GPIO_INVERT,
|
||||
+ .gpio13 = GPIO_INVERT,
|
||||
+ .gpio14 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_NATIVE,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_GPIO,
|
||||
+ .gpio46 = GPIO_MODE_NATIVE,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_GPIO,
|
||||
+ .gpio50 = GPIO_MODE_NATIVE,
|
||||
+ .gpio51 = GPIO_MODE_GPIO,
|
||||
+ .gpio52 = GPIO_MODE_GPIO,
|
||||
+ .gpio53 = GPIO_MODE_GPIO,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_NATIVE,
|
||||
+ .gpio56 = GPIO_MODE_NATIVE,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_INPUT,
|
||||
+ .gpio35 = GPIO_DIR_INPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_INPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio45 = GPIO_DIR_INPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio49 = GPIO_DIR_INPUT,
|
||||
+ .gpio51 = GPIO_DIR_INPUT,
|
||||
+ .gpio52 = GPIO_DIR_INPUT,
|
||||
+ .gpio53 = GPIO_DIR_INPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio60 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_GPIO,
|
||||
+ .gpio69 = GPIO_MODE_GPIO,
|
||||
+ .gpio70 = GPIO_MODE_GPIO,
|
||||
+ .gpio71 = GPIO_MODE_GPIO,
|
||||
+ .gpio72 = GPIO_MODE_NATIVE,
|
||||
+ .gpio73 = GPIO_MODE_NATIVE,
|
||||
+ .gpio74 = GPIO_MODE_GPIO,
|
||||
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio68 = GPIO_DIR_INPUT,
|
||||
+ .gpio69 = GPIO_DIR_INPUT,
|
||||
+ .gpio70 = GPIO_DIR_INPUT,
|
||||
+ .gpio71 = GPIO_DIR_INPUT,
|
||||
+ .gpio74 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ .reset = &pch_gpio_set1_reset,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ .reset = &pch_gpio_set2_reset,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ .reset = &pch_gpio_set3_reset,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/e5530/hda_verb.c b/src/mainboard/dell/e5530/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..4c7c36ee05
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/hda_verb.c
|
||||
@@ -0,0 +1,33 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x111d76df, /* Codec Vendor / Device ID: IDT */
|
||||
+ 0x1028053d, /* Subsystem ID */
|
||||
+ 11, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(0, 0x1028053d),
|
||||
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
|
||||
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
|
||||
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
||||
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
||||
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
||||
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0),
|
||||
+
|
||||
+ 0x80862806, /* Codec Vendor / Device ID: Intel */
|
||||
+ 0x80860101, /* Subsystem ID */
|
||||
+ 4, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
+
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/e5530/mainboard.c b/src/mainboard/dell/e5530/mainboard.c
|
||||
new file mode 100644
|
||||
index 0000000000..31e49802fc
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5530/mainboard.c
|
||||
@@ -0,0 +1,21 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/device.h>
|
||||
+#include <drivers/intel/gma/int15.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+#include <ec/acpi/ec.h>
|
||||
+#include <console/console.h>
|
||||
+#include <pc80/keyboard.h>
|
||||
+
|
||||
+static void mainboard_enable(struct device *dev)
|
||||
+{
|
||||
+
|
||||
+ /* FIXME: fix these values. */
|
||||
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
+}
|
||||
+
|
||||
+struct chip_operations mainboard_ops = {
|
||||
+ .enable_dev = mainboard_enable,
|
||||
+};
|
||||
--
|
||||
2.43.0
|
||||
|
||||
+1556
File diff suppressed because it is too large
Load Diff
+41
@@ -0,0 +1,41 @@
|
||||
From b2cf0657a2058118baf6f4ec96e356de3c9e493e Mon Sep 17 00:00:00 2001
|
||||
From: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
Date: Sun, 11 Feb 2024 19:02:20 +0200
|
||||
Subject: [PATCH] hp8560w: Add MXM System Infomation Structure
|
||||
|
||||
Change-Id: I45b421f2d7baf8ca8dedbd3b1ab1e38392b6219b
|
||||
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
---
|
||||
src/mainboard/hp/snb_ivb_laptops/Makefile.mk | 6 ++++++
|
||||
.../hp/snb_ivb_laptops/variants/8560w/mxm-30-sis | Bin 0 -> 129 bytes
|
||||
2 files changed, 6 insertions(+)
|
||||
create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
|
||||
|
||||
diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
|
||||
index c007bb68cd..7950abbc4e 100644
|
||||
--- a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
|
||||
+++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
|
||||
@@ -9,3 +9,9 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb
|
||||
|
||||
# FIXME: Other variants with same size onboard RAM may exist.
|
||||
SPD_SOURCES = hynix_4g
|
||||
+
|
||||
+ifeq ($(CONFIG_BOARD_HP_8560W),y)
|
||||
+cbfs-files-y += mxm-30-sis
|
||||
+mxm-30-sis-file := variants/$(VARIANT_DIR)/mxm-30-sis
|
||||
+mxm-30-sis-type := raw
|
||||
+endif
|
||||
diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..7e4e245a50d8d5d36ddb22e3b1aed3fa87a2f57d
|
||||
GIT binary patch
|
||||
literal 129
|
||||
zcmeZ`@Qr6?sAMn@-0}aX9Rou`%?mKiz;Fq|&xF!hw;=rNM_^h3Dy{$(SAdE$zF=lx
|
||||
o@?l{RW{6;7W}LwIl$Vj2apDSgHUS2PJFE;0Kxqas5d=FN0HAs+0RR91
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
--
|
||||
2.43.1
|
||||
|
||||
@@ -0,0 +1,775 @@
|
||||
From 7c7ce2087e1ff5f0eedb65793254163d01be3056 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Wed, 7 Feb 2024 10:23:38 -0700
|
||||
Subject: [PATCH] mb/dell: Add Latitude E5520 (Sandybridge)
|
||||
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/e5520/Kconfig | 37 ++++
|
||||
src/mainboard/dell/e5520/Kconfig.name | 2 +
|
||||
src/mainboard/dell/e5520/Makefile.inc | 5 +
|
||||
src/mainboard/dell/e5520/acpi/ec.asl | 9 +
|
||||
src/mainboard/dell/e5520/acpi/platform.asl | 12 ++
|
||||
src/mainboard/dell/e5520/acpi/superio.asl | 3 +
|
||||
src/mainboard/dell/e5520/acpi_tables.c | 16 ++
|
||||
src/mainboard/dell/e5520/board_info.txt | 6 +
|
||||
src/mainboard/dell/e5520/cmos.default | 9 +
|
||||
src/mainboard/dell/e5520/cmos.layout | 88 ++++++++++
|
||||
src/mainboard/dell/e5520/data.vbt | Bin 0 -> 6144 bytes
|
||||
src/mainboard/dell/e5520/devicetree.cb | 66 +++++++
|
||||
src/mainboard/dell/e5520/dsdt.asl | 30 ++++
|
||||
src/mainboard/dell/e5520/early_init.c | 32 ++++
|
||||
src/mainboard/dell/e5520/gma-mainboard.ads | 20 +++
|
||||
src/mainboard/dell/e5520/gpio.c | 195 +++++++++++++++++++++
|
||||
src/mainboard/dell/e5520/hda_verb.c | 33 ++++
|
||||
src/mainboard/dell/e5520/mainboard.c | 21 +++
|
||||
18 files changed, 584 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/e5520/Kconfig
|
||||
create mode 100644 src/mainboard/dell/e5520/Kconfig.name
|
||||
create mode 100644 src/mainboard/dell/e5520/Makefile.inc
|
||||
create mode 100644 src/mainboard/dell/e5520/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/dell/e5520/acpi/platform.asl
|
||||
create mode 100644 src/mainboard/dell/e5520/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/dell/e5520/acpi_tables.c
|
||||
create mode 100644 src/mainboard/dell/e5520/board_info.txt
|
||||
create mode 100644 src/mainboard/dell/e5520/cmos.default
|
||||
create mode 100644 src/mainboard/dell/e5520/cmos.layout
|
||||
create mode 100644 src/mainboard/dell/e5520/data.vbt
|
||||
create mode 100644 src/mainboard/dell/e5520/devicetree.cb
|
||||
create mode 100644 src/mainboard/dell/e5520/dsdt.asl
|
||||
create mode 100644 src/mainboard/dell/e5520/early_init.c
|
||||
create mode 100644 src/mainboard/dell/e5520/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/e5520/gpio.c
|
||||
create mode 100644 src/mainboard/dell/e5520/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/e5520/mainboard.c
|
||||
|
||||
diff --git a/src/mainboard/dell/e5520/Kconfig b/src/mainboard/dell/e5520/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..213c54cf5c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/Kconfig
|
||||
@@ -0,0 +1,37 @@
|
||||
+if BOARD_DELL_LATITUDE_E5520
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS
|
||||
+ def_bool y
|
||||
+ select BOARD_ROMSIZE_KB_6144
|
||||
+ select EC_ACPI
|
||||
+ select EC_DELL_MEC5035
|
||||
+ select GFX_GMA_PANEL_1_ON_LVDS
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select INTEL_INT15
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
|
||||
+ select SERIRQ_CONTINUOUS_MODE
|
||||
+ select SOUTHBRIDGE_INTEL_BD82X6X
|
||||
+ select SYSTEM_TYPE_LAPTOP
|
||||
+ select USE_NATIVE_RAMINIT
|
||||
+
|
||||
+config DRAM_RESET_GATE_GPIO
|
||||
+ default 60
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "dell/e5520"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "Latitude E5520"
|
||||
+
|
||||
+config USBDEBUG_HCD_INDEX
|
||||
+ default 2
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,0126"
|
||||
+
|
||||
+endif # BOARD_DELL_LATITUDE_E5520
|
||||
diff --git a/src/mainboard/dell/e5520/Kconfig.name b/src/mainboard/dell/e5520/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..c88913e8b3
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/Kconfig.name
|
||||
@@ -0,0 +1,2 @@
|
||||
+config BOARD_DELL_LATITUDE_E5520
|
||||
+ bool "Latitude E5520"
|
||||
diff --git a/src/mainboard/dell/e5520/Makefile.inc b/src/mainboard/dell/e5520/Makefile.inc
|
||||
new file mode 100644
|
||||
index 0000000000..18391d8b18
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/Makefile.inc
|
||||
@@ -0,0 +1,5 @@
|
||||
+bootblock-y += early_init.c
|
||||
+bootblock-y += gpio.c
|
||||
+romstage-y += early_init.c
|
||||
+romstage-y += gpio.c
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
diff --git a/src/mainboard/dell/e5520/acpi/ec.asl b/src/mainboard/dell/e5520/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..0d429410a9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/acpi/ec.asl
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Device(EC)
|
||||
+{
|
||||
+ Name (_HID, EISAID("PNP0C09"))
|
||||
+ Name (_UID, 0)
|
||||
+ Name (_GPE, 16)
|
||||
+/* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5520/acpi/platform.asl b/src/mainboard/dell/e5520/acpi/platform.asl
|
||||
new file mode 100644
|
||||
index 0000000000..2d24bbd9b9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/acpi/platform.asl
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Method(_WAK, 1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+ Return(Package() {0, 0})
|
||||
+}
|
||||
+
|
||||
+Method(_PTS,1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5520/acpi/superio.asl b/src/mainboard/dell/e5520/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..55b1db5b11
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/acpi/superio.asl
|
||||
@@ -0,0 +1,3 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
diff --git a/src/mainboard/dell/e5520/acpi_tables.c b/src/mainboard/dell/e5520/acpi_tables.c
|
||||
new file mode 100644
|
||||
index 0000000000..e2759659bf
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/acpi_tables.c
|
||||
@@ -0,0 +1,16 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi_gnvs.h>
|
||||
+#include <soc/nvs.h>
|
||||
+
|
||||
+/* FIXME: check this function. */
|
||||
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
|
||||
+{
|
||||
+ /* The lid is open by default. */
|
||||
+ gnvs->lids = 1;
|
||||
+
|
||||
+ /* Temperature at which OS will shutdown */
|
||||
+ gnvs->tcrt = 100;
|
||||
+ /* Temperature at which OS will throttle CPU */
|
||||
+ gnvs->tpsv = 90;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5520/board_info.txt b/src/mainboard/dell/e5520/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..34d5ad9e0b
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/board_info.txt
|
||||
@@ -0,0 +1,6 @@
|
||||
+Category: laptop
|
||||
+ROM package: SOIC-8
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
+Release year: 2011
|
||||
diff --git a/src/mainboard/dell/e5520/cmos.default b/src/mainboard/dell/e5520/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..279415dfd1
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/cmos.default
|
||||
@@ -0,0 +1,9 @@
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Disable
|
||||
+nmi=Enable
|
||||
+bluetooth=Enable
|
||||
+wwan=Enable
|
||||
+wlan=Enable
|
||||
+sata_mode=AHCI
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/dell/e5520/cmos.layout b/src/mainboard/dell/e5520/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..1aa7e77bce
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/cmos.layout
|
||||
@@ -0,0 +1,88 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+
|
||||
+#400 8 r 0 reserved for century byte
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 1 nmi
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+411 1 e 9 sata_mode
|
||||
+
|
||||
+# coreboot config options: EC
|
||||
+412 1 e 1 bluetooth
|
||||
+413 1 e 1 wwan
|
||||
+414 1 e 1 wlan
|
||||
+
|
||||
+# coreboot config options: ME
|
||||
+424 1 e 14 me_state
|
||||
+425 2 h 0 me_state_prev
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 3 e 11 gfx_uma_size
|
||||
+435 2 e 12 hybrid_graphics_mode
|
||||
+440 8 h 0 volume
|
||||
+
|
||||
+# VBOOT
|
||||
+448 128 r 0 vbnv
|
||||
+
|
||||
+# SandyBridge MRC Scrambler Seed values
|
||||
+896 32 r 0 mrc_scrambler_seed
|
||||
+928 32 r 0 mrc_scrambler_seed_s3
|
||||
+960 16 r 0 mrc_scrambler_seed_chk
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+9 0 AHCI
|
||||
+9 1 Compatible
|
||||
+11 0 32M
|
||||
+11 1 64M
|
||||
+11 2 96M
|
||||
+11 3 128M
|
||||
+11 4 160M
|
||||
+11 5 192M
|
||||
+11 6 224M
|
||||
+14 0 Normal
|
||||
+14 1 Disabled
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 447 984
|
||||
diff --git a/src/mainboard/dell/e5520/data.vbt b/src/mainboard/dell/e5520/data.vbt
|
||||
new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729
|
||||
GIT binary patch
|
||||
literal 6144
|
||||
zcmeHKZ){Ul6hE);wSBvNZ|mL$bmQOM2BTvXUI!}^N9ejTij1vnu+)Wx6<c9(Y_%K6
|
||||
zzOV-@f<ehpWB5RHBpMBgG7}RuMuM2=l*E{6G$wq&gqTQ3#E2RZsOP@dvW*rP7>Fjj
|
||||
z&F`Lj?>YC}bI(2Z+}C+6zKyiGrosQXuW7A+&1%<rN+Y1ck(}dLrx)Ma#^x>lnvFGE
|
||||
zeD#gB>*#Tq4&j^|7Xcz1r^pp*)g#T}u1Me3ct>Pgls5Qi3!6e2W0%`a-Ic|3efWuR
|
||||
zXJ@#}wJyGMTXTcY<%@TBKh@(3hP$Gjv}E}rx-%9D_eLXhYe!c&-VyDg-Cdo1>Biji
|
||||
zNNsnlFW#|jdoOj?mZ43m>cVO%UE9@*E7x|%V~c4`XD4l9GCi~@+7pfMibfX8L?!^I
|
||||
zc~Rg1I5SxH1DAEZ0{jA41jrJBh#-l;b6^%g7QrThRe)&%tQH_!ggOD7A_PRRgGuI0
|
||||
z0zi=n#rCB66d-sO$M~^6wgeb$2fH1|0R`v}xUiWCU`4SF;Dyh&j|mK&6WJWJ&Pq9I
|
||||
zVgmFQfh+)vE}(KWwHA|Oh3fSkss|;2E(2i}s1?gRRV%8!K7U={vHD=s#+Fd)W^M1j
|
||||
z{R4$??VSvEWpgT=vCM&1-U$bI6CB~IV3Z$$Vv7o!EDnev4j~R(MHsazZ~^fLLKGF4
|
||||
zEfQFOa3dZ?1Q1P#&4?!vyAk^k&m&$z3?WV+-b0*1j37o4=MX<3E+eiYge(Ht2umAW
|
||||
zOPDmU>UL{flI9u|@JtVvfp#o8ek?VfVV9YP5(%pnZX~{PKq4WoWGmV8t$=Ri@{zLQ
|
||||
zNYYt4<$0Ry&qIoG;7s-t333)Nu8opN{NG!)&!I@eO(cVx8vBVEBvotJ7%yNl$7iQ_
|
||||
zI=xk30+V$ff`F6<wRoF(TK%j9nsr#H23umU%)_7jNOl%*FPU567qbg;4gtp711nj2
|
||||
z#+kHw`v4|5cA+`UMIvAl;slnH1nl0v=xH<al>1}ljxDE1dcda^&!do|r^eJkI?aC-
|
||||
zEQMSfm?<w*Unzumkj_w5>VYL6W4=aCiy4rk%xq~5LV?bi|GL2$G7li<%c7yd;6T34
|
||||
zQBN5huZ3~6`ChGkpb$Bg5ITb#2iK-qs|1`=sl6Dhn(Lj&8Agt?S{sTDmmtRj7Jm_1
|
||||
zFnt{w&FdFkWS3bl>OeL?eO+*i{)9G!cSI-InGt|U0eEYmRCOHm7|I;#LO8ksRIeJ#
|
||||
zGe+jTwPg4C4TYuN(9zULV3k+hI$YuPo=%N8oZ#u_4S!3Xelt6N0BmuC`hCNeg+&97
|
||||
z6*!>)uHvr%2004GZv?!_-y&|TRmil=9D%Q`1aXBsnD^gov3*UZI34&1_vn(B=T4kZ
|
||||
z_A>ClXVIBNaS^hd&^DrU6VgZMYeadMkdFxcktn|ra-Gl;n^I{bt86rCQ=YMry*B!$
|
||||
zP5ID9KDE)GZOY#^VwPyRq^y+48j0?ZlzxdkC()CV@`*&wO7vGr;qjA3rb}gIwM-gi
|
||||
zx>HsT$mEDj-<OpyWb%zn|B@A3Hkp<!FT5;hrt_SZiy?*wDaIu{h>%Ir=@rh7)SR;b
|
||||
zAEWQGv_X1)wq0y5Ha0c~&psIsln<Hiu3;#Lf;%*eI<@?p8cfMJV(IYi8q$NA#iS8`
|
||||
z_~|4t4b^wtMSAeFST^F8-Tm<zu8D&j^8=&I4;I}Im>aeSK~X8*^Z9SE44_`P#KIUL
|
||||
zf6^N2f>5HCPWM3N+f0MyWOV^kz~!-wVc4MRXOY>4Jsxd1RyBKEMzNf{RKhesKFdbq
|
||||
zJ(*d<l2Y#n?E?~iBA39P?~Pr2d#}5=#Sfl-VGzGUF$4U2KcqCIVlwkC(&7PQk_X!a
|
||||
z8}3Jgq-&U*Co|h1>l)ZQGyW_x->i#;FvQ*=Nv&nG0N5@D@jjv_Q}K}6MP?1A6`JGe
|
||||
zDwj9pN+x;T4>`I9e5x(uqdK#OGB31ikk@Xv=dxLb4fx(;ktX@rOb~M~?dYQQYiPia
|
||||
z8r;jUQ?sd2@3||-cb2Eb%JFYfxHsONoaJ^eqoKN{<g9?-%`7oWz+aJS0tEc!^d@hD
|
||||
z1-I{%hr!Y?0uVZpUbl__37xn@jkD6Z>3SATgBQlEoN7&ZV9Eni9+>jLln16fFy(=V
|
||||
H=7E0zE^L4Z
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/e5520/devicetree.cb b/src/mainboard/dell/e5520/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..bef96ac14c
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/devicetree.cb
|
||||
@@ -0,0 +1,66 @@
|
||||
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
|
||||
+ register "gpu_cpu_backlight" = "0x00000218"
|
||||
+ register "gpu_dp_b_hotplug" = "4"
|
||||
+ register "gpu_dp_c_hotplug" = "4"
|
||||
+ register "gpu_dp_d_hotplug" = "4"
|
||||
+ register "gpu_panel_port_select" = "0"
|
||||
+ register "gpu_panel_power_backlight_off_delay" = "2300"
|
||||
+ register "gpu_panel_power_backlight_on_delay" = "2300"
|
||||
+ register "gpu_panel_power_cycle_delay" = "6"
|
||||
+ register "gpu_panel_power_down_delay" = "400"
|
||||
+ register "gpu_panel_power_up_delay" = "400"
|
||||
+ register "gpu_pch_backlight" = "0x13121312"
|
||||
+
|
||||
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
|
||||
+
|
||||
+ device domain 0x0 on
|
||||
+ subsystemid 0x1028 0x049a inherit
|
||||
+
|
||||
+ device ref host_bridge on end # Host bridge
|
||||
+ device ref peg10 on end # PEG
|
||||
+ device ref igd on end # iGPU
|
||||
+
|
||||
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
+ register "docking_supported" = "1"
|
||||
+ register "gen1_dec" = "0x007c0681"
|
||||
+ register "gen2_dec" = "0x007c0901"
|
||||
+ register "gen3_dec" = "0x003c07e1"
|
||||
+ register "gen4_dec" = "0x001c0901"
|
||||
+ register "gpi0_routing" = "2"
|
||||
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
|
||||
+ register "pcie_port_coalesce" = "1"
|
||||
+ register "sata_interface_speed_support" = "0x3"
|
||||
+ register "sata_port_map" = "0x3b"
|
||||
+ register "spi_lvscc" = "0x2005"
|
||||
+ register "spi_uvscc" = "0x2005"
|
||||
+
|
||||
+ device ref mei1 off end
|
||||
+ device ref mei2 off end
|
||||
+ device ref me_ide_r off end
|
||||
+ device ref me_kt off end
|
||||
+ device ref gbe off end
|
||||
+ device ref ehci2 on end
|
||||
+ device ref hda on end
|
||||
+ device ref pcie_rp1 on end
|
||||
+ device ref pcie_rp2 on end
|
||||
+ device ref pcie_rp3 on end
|
||||
+ device ref pcie_rp4 off end
|
||||
+ device ref pcie_rp5 on end
|
||||
+ device ref pcie_rp6 on end
|
||||
+ device ref pcie_rp7 on end
|
||||
+ device ref pcie_rp8 off end
|
||||
+ device ref ehci1 on end
|
||||
+ device ref pci_bridge off end
|
||||
+ device ref lpc on
|
||||
+ chip ec/dell/mec5035
|
||||
+ device pnp ff.0 on end
|
||||
+ end
|
||||
+ end
|
||||
+ device ref sata1 on end
|
||||
+ device ref smbus on end
|
||||
+ device ref sata2 off end
|
||||
+ device ref thermal off end
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/e5520/dsdt.asl b/src/mainboard/dell/e5520/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..7d13c55b08
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/dsdt.asl
|
||||
@@ -0,0 +1,30 @@
|
||||
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20141018 /* OEM revision */
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+ #include "acpi/platform.asl"
|
||||
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5520/early_init.c b/src/mainboard/dell/e5520/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..7297921546
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/early_init.c
|
||||
@@ -0,0 +1,32 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <bootblock_common.h>
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <ec/dell/mec5035/mec5035.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 1, 3 },
|
||||
+ { 1, 1, 3 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 7 },
|
||||
+ { 1, 1, 6 },
|
||||
+ { 1, 1, 6 },
|
||||
+ { 1, 1, 7 },
|
||||
+};
|
||||
+
|
||||
+void bootblock_mainboard_early_init(void)
|
||||
+{
|
||||
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
|
||||
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
|
||||
+ | COMB_LPC_EN | COMA_LPC_EN);
|
||||
+ mec5035_early_init();
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5520/gma-mainboard.ads b/src/mainboard/dell/e5520/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..2a16f44360
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/gma-mainboard.ads
|
||||
@@ -0,0 +1,20 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (
|
||||
+ HDMI1, -- mainboard HDMI
|
||||
+ DP2, -- dock DP
|
||||
+ DP3, -- dock DP
|
||||
+ Analog, -- mainboard VGA
|
||||
+ LVDS,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/e5520/gpio.c b/src/mainboard/dell/e5520/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..f76b93d9f0
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/gpio.c
|
||||
@@ -0,0 +1,195 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_GPIO,
|
||||
+ .gpio1 = GPIO_MODE_NATIVE,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_GPIO,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_NATIVE,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_GPIO,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_GPIO,
|
||||
+ .gpio16 = GPIO_MODE_NATIVE,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_GPIO,
|
||||
+ .gpio31 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio0 = GPIO_DIR_INPUT,
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio3 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio12 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio15 = GPIO_DIR_INPUT,
|
||||
+ .gpio17 = GPIO_DIR_INPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_INPUT,
|
||||
+ .gpio29 = GPIO_DIR_INPUT,
|
||||
+ .gpio30 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio12 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio30 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio0 = GPIO_INVERT,
|
||||
+ .gpio8 = GPIO_INVERT,
|
||||
+ .gpio14 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_NATIVE,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_NATIVE,
|
||||
+ .gpio46 = GPIO_MODE_GPIO,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_NATIVE,
|
||||
+ .gpio50 = GPIO_MODE_GPIO,
|
||||
+ .gpio51 = GPIO_MODE_GPIO,
|
||||
+ .gpio52 = GPIO_MODE_GPIO,
|
||||
+ .gpio53 = GPIO_MODE_GPIO,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_GPIO,
|
||||
+ .gpio56 = GPIO_MODE_GPIO,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio35 = GPIO_DIR_INPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio46 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio50 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio51 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio52 = GPIO_DIR_INPUT,
|
||||
+ .gpio53 = GPIO_DIR_INPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio55 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio56 = GPIO_DIR_INPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio34 = GPIO_LEVEL_LOW,
|
||||
+ .gpio37 = GPIO_LEVEL_LOW,
|
||||
+ .gpio46 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio50 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio51 = GPIO_LEVEL_LOW,
|
||||
+ .gpio55 = GPIO_LEVEL_LOW,
|
||||
+ .gpio60 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_NATIVE,
|
||||
+ .gpio69 = GPIO_MODE_NATIVE,
|
||||
+ .gpio70 = GPIO_MODE_NATIVE,
|
||||
+ .gpio71 = GPIO_MODE_NATIVE,
|
||||
+ .gpio72 = GPIO_MODE_NATIVE,
|
||||
+ .gpio73 = GPIO_MODE_NATIVE,
|
||||
+ .gpio74 = GPIO_MODE_GPIO,
|
||||
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio74 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ .reset = &pch_gpio_set1_reset,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ .reset = &pch_gpio_set2_reset,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ .reset = &pch_gpio_set3_reset,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/e5520/hda_verb.c b/src/mainboard/dell/e5520/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..e2efee3646
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/hda_verb.c
|
||||
@@ -0,0 +1,33 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
|
||||
+ 0x1028049a, /* Subsystem ID */
|
||||
+ 11, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(0, 0x1028049a),
|
||||
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
|
||||
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
|
||||
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
||||
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
||||
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
||||
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
|
||||
+
|
||||
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
|
||||
+ 0x80860101, /* Subsystem ID */
|
||||
+ 4, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
+
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/e5520/mainboard.c b/src/mainboard/dell/e5520/mainboard.c
|
||||
new file mode 100644
|
||||
index 0000000000..31e49802fc
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5520/mainboard.c
|
||||
@@ -0,0 +1,21 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/device.h>
|
||||
+#include <drivers/intel/gma/int15.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+#include <ec/acpi/ec.h>
|
||||
+#include <console/console.h>
|
||||
+#include <pc80/keyboard.h>
|
||||
+
|
||||
+static void mainboard_enable(struct device *dev)
|
||||
+{
|
||||
+
|
||||
+ /* FIXME: fix these values. */
|
||||
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
+}
|
||||
+
|
||||
+struct chip_operations mainboard_ops = {
|
||||
+ .enable_dev = mainboard_enable,
|
||||
+};
|
||||
--
|
||||
2.43.0
|
||||
|
||||
+292
@@ -0,0 +1,292 @@
|
||||
From 7c755b4502ea007f2216ea76f2ed734452def883 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 2 Mar 2024 22:51:09 +0000
|
||||
Subject: [PATCH 1/2] nb/intel/haswell: make IOMMU a runtime option
|
||||
|
||||
When I tested graphics cards on a coreboot port for Dell
|
||||
OptiPlex 9020 SFF, I could not use a graphics card unless
|
||||
I set iommu=off on the Linux cmdline.
|
||||
|
||||
Coreboot's current behaviour is to check whether the CPU
|
||||
has vt-d support and, if it does, initialise the IOMMU.
|
||||
|
||||
This patch maintains the current behaviour by default, but
|
||||
allows the user to turn *off* the IOMMU, even if vt-d is
|
||||
supported by the host CPU.
|
||||
|
||||
If iommu=Disable is specified, the check will not be
|
||||
performed, and the IOMMU will be left disabled. This option
|
||||
has been added to all current Haswell boards, though it is
|
||||
recommended to leave the IOMMU turned on in most setups.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/mainboard/asrock/b85m_pro4/cmos.default | 1 +
|
||||
src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++
|
||||
src/mainboard/asrock/h81m-hds/cmos.default | 1 +
|
||||
src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 1 +
|
||||
src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++
|
||||
src/mainboard/google/beltino/cmos.layout | 5 +++++
|
||||
src/mainboard/google/slippy/cmos.layout | 5 +++++
|
||||
src/mainboard/intel/baskingridge/cmos.layout | 4 ++++
|
||||
src/mainboard/lenovo/haswell/cmos.default | 1 +
|
||||
src/mainboard/lenovo/haswell/cmos.layout | 3 +++
|
||||
src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
|
||||
src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++
|
||||
src/northbridge/intel/haswell/early_init.c | 5 +++++
|
||||
14 files changed, 48 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default
|
||||
index c51001c03c..1c5c17f841 100644
|
||||
--- a/src/mainboard/asrock/b85m_pro4/cmos.default
|
||||
+++ b/src/mainboard/asrock/b85m_pro4/cmos.default
|
||||
@@ -2,3 +2,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
nmi=Enable
|
||||
power_on_after_fail=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout
|
||||
index efdc333fc2..c9883ea71d 100644
|
||||
--- a/src/mainboard/asrock/b85m_pro4/cmos.layout
|
||||
+++ b/src/mainboard/asrock/b85m_pro4/cmos.layout
|
||||
@@ -11,6 +11,7 @@
|
||||
395 4 e 4 debug_level
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
+ 412 1 e 6 iommu
|
||||
984 16 h 0 check_sum
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
@@ -38,6 +39,8 @@
|
||||
5 0 Disable
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
+ 6 0 Disable
|
||||
+ 6 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default
|
||||
index c51001c03c..1c5c17f841 100644
|
||||
--- a/src/mainboard/asrock/h81m-hds/cmos.default
|
||||
+++ b/src/mainboard/asrock/h81m-hds/cmos.default
|
||||
@@ -2,3 +2,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
nmi=Enable
|
||||
power_on_after_fail=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout
|
||||
index c9ba76c78f..95ee3d36fb 100644
|
||||
--- a/src/mainboard/asrock/h81m-hds/cmos.layout
|
||||
+++ b/src/mainboard/asrock/h81m-hds/cmos.layout
|
||||
@@ -21,6 +21,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 6 iommu
|
||||
+
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
|
||||
@@ -52,6 +55,9 @@ enumerations
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
|
||||
+6 0 Disable
|
||||
+6 1 Enable
|
||||
+
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
index b159660aa8..8253570f19 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
@@ -2,3 +2,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
nmi=Disable
|
||||
power_on_after_fail=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
index c9ba76c78f..72ff9c4bee 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
@@ -21,6 +21,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
+# turn iommu on or off
|
||||
+412 1 e 6 iommu
|
||||
+
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
|
||||
@@ -52,6 +55,9 @@ enumerations
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
|
||||
+6 0 Disable
|
||||
+6 1 Enable
|
||||
+
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout
|
||||
index 78d44c1415..c143979ae1 100644
|
||||
--- a/src/mainboard/google/beltino/cmos.layout
|
||||
+++ b/src/mainboard/google/beltino/cmos.layout
|
||||
@@ -19,6 +19,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 8 iommu
|
||||
+
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
@@ -47,6 +50,8 @@ enumerations
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
+8 0 Disable
|
||||
+8 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout
|
||||
index 78d44c1415..c143979ae1 100644
|
||||
--- a/src/mainboard/google/slippy/cmos.layout
|
||||
+++ b/src/mainboard/google/slippy/cmos.layout
|
||||
@@ -19,6 +19,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 8 iommu
|
||||
+
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
@@ -47,6 +50,8 @@ enumerations
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
+8 0 Disable
|
||||
+8 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout
|
||||
index 78d44c1415..f2c602f541 100644
|
||||
--- a/src/mainboard/intel/baskingridge/cmos.layout
|
||||
+++ b/src/mainboard/intel/baskingridge/cmos.layout
|
||||
@@ -19,6 +19,8 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 7 power_on_after_fail
|
||||
|
||||
+412 1 e 8 iommu
|
||||
+
|
||||
# coreboot config options: bootloader
|
||||
#Used by ChromeOS:
|
||||
416 128 r 0 vbnv
|
||||
@@ -47,6 +49,8 @@ enumerations
|
||||
7 0 Disable
|
||||
7 1 Enable
|
||||
7 2 Keep
|
||||
+8 0 Disable
|
||||
+8 1 Enable
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default
|
||||
index bb8626d48b..051658d757 100644
|
||||
--- a/src/mainboard/lenovo/haswell/cmos.default
|
||||
+++ b/src/mainboard/lenovo/haswell/cmos.default
|
||||
@@ -12,3 +12,4 @@ trackpoint=Enable
|
||||
backlight=Keyboard
|
||||
enable_dual_graphics=Disable
|
||||
usb_always_on=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout
|
||||
index 27915d3ab7..59df76b64c 100644
|
||||
--- a/src/mainboard/lenovo/haswell/cmos.layout
|
||||
+++ b/src/mainboard/lenovo/haswell/cmos.layout
|
||||
@@ -23,6 +23,7 @@ entries
|
||||
|
||||
# coreboot config options: EC
|
||||
411 1 e 8 first_battery
|
||||
+413 1 e 14 iommu
|
||||
415 1 e 1 wlan
|
||||
416 1 e 1 trackpoint
|
||||
417 1 e 1 fn_ctrl_swap
|
||||
@@ -72,6 +73,8 @@ enumerations
|
||||
13 0 Disable
|
||||
13 1 AC and battery
|
||||
13 2 AC only
|
||||
+14 0 Disable
|
||||
+14 1 Enable
|
||||
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default
|
||||
index f4047147f7..eea2c36b88 100644
|
||||
--- a/src/mainboard/supermicro/x10slm-f/cmos.default
|
||||
+++ b/src/mainboard/supermicro/x10slm-f/cmos.default
|
||||
@@ -3,3 +3,4 @@ debug_level=Debug
|
||||
nmi=Enable
|
||||
power_on_after_fail=Keep
|
||||
hide_ast2400=Disable
|
||||
+iommu=Enable
|
||||
diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout
|
||||
index 38ba87aa45..24d39e97ee 100644
|
||||
--- a/src/mainboard/supermicro/x10slm-f/cmos.layout
|
||||
+++ b/src/mainboard/supermicro/x10slm-f/cmos.layout
|
||||
@@ -21,6 +21,9 @@ entries
|
||||
408 1 e 1 nmi
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
+# enable or disable iommu
|
||||
+412 1 e 6 iommu
|
||||
+
|
||||
# coreboot config options: mainboard
|
||||
416 1 e 1 hide_ast2400
|
||||
|
||||
@@ -55,6 +58,9 @@ enumerations
|
||||
5 1 Enable
|
||||
5 2 Keep
|
||||
|
||||
+6 0 Disable
|
||||
+6 1 Enable
|
||||
+
|
||||
# -----------------------------------------------------------------
|
||||
checksums
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
|
||||
index e47deb5da6..1a7e0b1076 100644
|
||||
--- a/src/northbridge/intel/haswell/early_init.c
|
||||
+++ b/src/northbridge/intel/haswell/early_init.c
|
||||
@@ -5,6 +5,7 @@
|
||||
#include <device/mmio.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ops.h>
|
||||
+#include <option.h>
|
||||
|
||||
#include "haswell.h"
|
||||
|
||||
@@ -157,6 +158,10 @@ static void haswell_setup_misc(void)
|
||||
static void haswell_setup_iommu(void)
|
||||
{
|
||||
const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
|
||||
+ u8 enable_iommu = get_uint_option("iommu", 1);
|
||||
+
|
||||
+ if (!enable_iommu)
|
||||
+ return;
|
||||
|
||||
if (capid0_a & VTD_DISABLE)
|
||||
return;
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+29
@@ -0,0 +1,29 @@
|
||||
From 61041d49b94236400e836b8ea518d3a064b95c4e Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 2 Mar 2024 23:00:09 +0000
|
||||
Subject: [PATCH 2/2] dell/optiplex_9020: Disable IOMMU by default
|
||||
|
||||
Needed to make graphics cards work. Turning it on is
|
||||
recommended if only using iGPU, otherwise leave it off
|
||||
by default. The IOMMU is extremely buggy when a graphics
|
||||
card is used. Leaving it off by default will ensure that
|
||||
the default ROM images in Libreboot will work on any setup.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
index 8253570f19..7bccc80e51 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
@@ -2,4 +2,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
nmi=Disable
|
||||
power_on_after_fail=Disable
|
||||
-iommu=Enable
|
||||
+iommu=Disable
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,774 @@
|
||||
From 7dd58c8b301404a8bafee25a1e97a8a5d614b3d6 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Mon, 4 Mar 2024 18:05:43 -0700
|
||||
Subject: [PATCH] mb/dell: Add Latitude E5420 (Sandy Bridge)
|
||||
|
||||
---
|
||||
src/mainboard/dell/e5420/Kconfig | 37 ++++
|
||||
src/mainboard/dell/e5420/Kconfig.name | 2 +
|
||||
src/mainboard/dell/e5420/Makefile.mk | 5 +
|
||||
src/mainboard/dell/e5420/acpi/ec.asl | 9 +
|
||||
src/mainboard/dell/e5420/acpi/platform.asl | 12 ++
|
||||
src/mainboard/dell/e5420/acpi/superio.asl | 3 +
|
||||
src/mainboard/dell/e5420/acpi_tables.c | 16 ++
|
||||
src/mainboard/dell/e5420/board_info.txt | 6 +
|
||||
src/mainboard/dell/e5420/cmos.default | 9 +
|
||||
src/mainboard/dell/e5420/cmos.layout | 88 ++++++++++
|
||||
src/mainboard/dell/e5420/data.vbt | Bin 0 -> 6144 bytes
|
||||
src/mainboard/dell/e5420/devicetree.cb | 66 +++++++
|
||||
src/mainboard/dell/e5420/dsdt.asl | 30 ++++
|
||||
src/mainboard/dell/e5420/early_init.c | 32 ++++
|
||||
src/mainboard/dell/e5420/gma-mainboard.ads | 20 +++
|
||||
src/mainboard/dell/e5420/gpio.c | 195 +++++++++++++++++++++
|
||||
src/mainboard/dell/e5420/hda_verb.c | 33 ++++
|
||||
src/mainboard/dell/e5420/mainboard.c | 21 +++
|
||||
18 files changed, 584 insertions(+)
|
||||
create mode 100644 src/mainboard/dell/e5420/Kconfig
|
||||
create mode 100644 src/mainboard/dell/e5420/Kconfig.name
|
||||
create mode 100644 src/mainboard/dell/e5420/Makefile.mk
|
||||
create mode 100644 src/mainboard/dell/e5420/acpi/ec.asl
|
||||
create mode 100644 src/mainboard/dell/e5420/acpi/platform.asl
|
||||
create mode 100644 src/mainboard/dell/e5420/acpi/superio.asl
|
||||
create mode 100644 src/mainboard/dell/e5420/acpi_tables.c
|
||||
create mode 100644 src/mainboard/dell/e5420/board_info.txt
|
||||
create mode 100644 src/mainboard/dell/e5420/cmos.default
|
||||
create mode 100644 src/mainboard/dell/e5420/cmos.layout
|
||||
create mode 100755 src/mainboard/dell/e5420/data.vbt
|
||||
create mode 100644 src/mainboard/dell/e5420/devicetree.cb
|
||||
create mode 100644 src/mainboard/dell/e5420/dsdt.asl
|
||||
create mode 100644 src/mainboard/dell/e5420/early_init.c
|
||||
create mode 100644 src/mainboard/dell/e5420/gma-mainboard.ads
|
||||
create mode 100644 src/mainboard/dell/e5420/gpio.c
|
||||
create mode 100644 src/mainboard/dell/e5420/hda_verb.c
|
||||
create mode 100644 src/mainboard/dell/e5420/mainboard.c
|
||||
|
||||
diff --git a/src/mainboard/dell/e5420/Kconfig b/src/mainboard/dell/e5420/Kconfig
|
||||
new file mode 100644
|
||||
index 0000000000..f4385045ae
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/Kconfig
|
||||
@@ -0,0 +1,37 @@
|
||||
+if BOARD_DELL_LATITUDE_E5420
|
||||
+
|
||||
+config BOARD_SPECIFIC_OPTIONS
|
||||
+ def_bool y
|
||||
+ select BOARD_ROMSIZE_KB_6144
|
||||
+ select EC_ACPI
|
||||
+ select EC_DELL_MEC5035
|
||||
+ select GFX_GMA_PANEL_1_ON_LVDS
|
||||
+ select HAVE_ACPI_RESUME
|
||||
+ select HAVE_ACPI_TABLES
|
||||
+ select HAVE_CMOS_DEFAULT
|
||||
+ select HAVE_OPTION_TABLE
|
||||
+ select INTEL_GMA_HAVE_VBT
|
||||
+ select INTEL_INT15
|
||||
+ select MAINBOARD_HAS_LIBGFXINIT
|
||||
+ select NORTHBRIDGE_INTEL_SANDYBRIDGE
|
||||
+ select SERIRQ_CONTINUOUS_MODE
|
||||
+ select SOUTHBRIDGE_INTEL_BD82X6X
|
||||
+ select SYSTEM_TYPE_LAPTOP
|
||||
+ select USE_NATIVE_RAMINIT
|
||||
+
|
||||
+config DRAM_RESET_GATE_GPIO
|
||||
+ default 60
|
||||
+
|
||||
+config MAINBOARD_DIR
|
||||
+ default "dell/e5420"
|
||||
+
|
||||
+config MAINBOARD_PART_NUMBER
|
||||
+ default "Latitude E5420"
|
||||
+
|
||||
+config USBDEBUG_HCD_INDEX
|
||||
+ default 2
|
||||
+
|
||||
+config VGA_BIOS_ID
|
||||
+ default "8086,0116"
|
||||
+
|
||||
+endif # BOARD_DELL_LATITUDE_E5420
|
||||
diff --git a/src/mainboard/dell/e5420/Kconfig.name b/src/mainboard/dell/e5420/Kconfig.name
|
||||
new file mode 100644
|
||||
index 0000000000..eb495fb705
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/Kconfig.name
|
||||
@@ -0,0 +1,2 @@
|
||||
+config BOARD_DELL_LATITUDE_E5420
|
||||
+ bool "Latitude E5420"
|
||||
diff --git a/src/mainboard/dell/e5420/Makefile.mk b/src/mainboard/dell/e5420/Makefile.mk
|
||||
new file mode 100644
|
||||
index 0000000000..18391d8b18
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/Makefile.mk
|
||||
@@ -0,0 +1,5 @@
|
||||
+bootblock-y += early_init.c
|
||||
+bootblock-y += gpio.c
|
||||
+romstage-y += early_init.c
|
||||
+romstage-y += gpio.c
|
||||
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
diff --git a/src/mainboard/dell/e5420/acpi/ec.asl b/src/mainboard/dell/e5420/acpi/ec.asl
|
||||
new file mode 100644
|
||||
index 0000000000..0d429410a9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/acpi/ec.asl
|
||||
@@ -0,0 +1,9 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Device(EC)
|
||||
+{
|
||||
+ Name (_HID, EISAID("PNP0C09"))
|
||||
+ Name (_UID, 0)
|
||||
+ Name (_GPE, 16)
|
||||
+/* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5420/acpi/platform.asl b/src/mainboard/dell/e5420/acpi/platform.asl
|
||||
new file mode 100644
|
||||
index 0000000000..2d24bbd9b9
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/acpi/platform.asl
|
||||
@@ -0,0 +1,12 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+Method(_WAK, 1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+ Return(Package() {0, 0})
|
||||
+}
|
||||
+
|
||||
+Method(_PTS,1)
|
||||
+{
|
||||
+ /* FIXME: EC support */
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5420/acpi/superio.asl b/src/mainboard/dell/e5420/acpi/superio.asl
|
||||
new file mode 100644
|
||||
index 0000000000..55b1db5b11
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/acpi/superio.asl
|
||||
@@ -0,0 +1,3 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <drivers/pc80/pc/ps2_controller.asl>
|
||||
diff --git a/src/mainboard/dell/e5420/acpi_tables.c b/src/mainboard/dell/e5420/acpi_tables.c
|
||||
new file mode 100644
|
||||
index 0000000000..e2759659bf
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/acpi_tables.c
|
||||
@@ -0,0 +1,16 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <acpi/acpi_gnvs.h>
|
||||
+#include <soc/nvs.h>
|
||||
+
|
||||
+/* FIXME: check this function. */
|
||||
+void mainboard_fill_gnvs(struct global_nvs *gnvs)
|
||||
+{
|
||||
+ /* The lid is open by default. */
|
||||
+ gnvs->lids = 1;
|
||||
+
|
||||
+ /* Temperature at which OS will shutdown */
|
||||
+ gnvs->tcrt = 100;
|
||||
+ /* Temperature at which OS will throttle CPU */
|
||||
+ gnvs->tpsv = 90;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5420/board_info.txt b/src/mainboard/dell/e5420/board_info.txt
|
||||
new file mode 100644
|
||||
index 0000000000..34d5ad9e0b
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/board_info.txt
|
||||
@@ -0,0 +1,6 @@
|
||||
+Category: laptop
|
||||
+ROM package: SOIC-8
|
||||
+ROM protocol: SPI
|
||||
+ROM socketed: n
|
||||
+Flashrom support: y
|
||||
+Release year: 2011
|
||||
diff --git a/src/mainboard/dell/e5420/cmos.default b/src/mainboard/dell/e5420/cmos.default
|
||||
new file mode 100644
|
||||
index 0000000000..279415dfd1
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/cmos.default
|
||||
@@ -0,0 +1,9 @@
|
||||
+boot_option=Fallback
|
||||
+debug_level=Debug
|
||||
+power_on_after_fail=Disable
|
||||
+nmi=Enable
|
||||
+bluetooth=Enable
|
||||
+wwan=Enable
|
||||
+wlan=Enable
|
||||
+sata_mode=AHCI
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/dell/e5420/cmos.layout b/src/mainboard/dell/e5420/cmos.layout
|
||||
new file mode 100644
|
||||
index 0000000000..1aa7e77bce
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/cmos.layout
|
||||
@@ -0,0 +1,88 @@
|
||||
+## SPDX-License-Identifier: GPL-2.0-only
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+entries
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+0 120 r 0 reserved_memory
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# RTC_BOOT_BYTE (coreboot hardcoded)
|
||||
+384 1 e 4 boot_option
|
||||
+388 4 h 0 reboot_counter
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+# coreboot config options: console
|
||||
+395 4 e 6 debug_level
|
||||
+
|
||||
+#400 8 r 0 reserved for century byte
|
||||
+
|
||||
+# coreboot config options: southbridge
|
||||
+408 1 e 1 nmi
|
||||
+409 2 e 7 power_on_after_fail
|
||||
+411 1 e 9 sata_mode
|
||||
+
|
||||
+# coreboot config options: EC
|
||||
+412 1 e 1 bluetooth
|
||||
+413 1 e 1 wwan
|
||||
+414 1 e 1 wlan
|
||||
+
|
||||
+# coreboot config options: ME
|
||||
+424 1 e 14 me_state
|
||||
+425 2 h 0 me_state_prev
|
||||
+
|
||||
+# coreboot config options: northbridge
|
||||
+432 3 e 11 gfx_uma_size
|
||||
+435 2 e 12 hybrid_graphics_mode
|
||||
+440 8 h 0 volume
|
||||
+
|
||||
+# VBOOT
|
||||
+448 128 r 0 vbnv
|
||||
+
|
||||
+# SandyBridge MRC Scrambler Seed values
|
||||
+896 32 r 0 mrc_scrambler_seed
|
||||
+928 32 r 0 mrc_scrambler_seed_s3
|
||||
+960 16 r 0 mrc_scrambler_seed_chk
|
||||
+
|
||||
+# coreboot config options: check sums
|
||||
+984 16 h 0 check_sum
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+
|
||||
+enumerations
|
||||
+
|
||||
+#ID value text
|
||||
+1 0 Disable
|
||||
+1 1 Enable
|
||||
+2 0 Enable
|
||||
+2 1 Disable
|
||||
+4 0 Fallback
|
||||
+4 1 Normal
|
||||
+6 0 Emergency
|
||||
+6 1 Alert
|
||||
+6 2 Critical
|
||||
+6 3 Error
|
||||
+6 4 Warning
|
||||
+6 5 Notice
|
||||
+6 6 Info
|
||||
+6 7 Debug
|
||||
+6 8 Spew
|
||||
+7 0 Disable
|
||||
+7 1 Enable
|
||||
+7 2 Keep
|
||||
+9 0 AHCI
|
||||
+9 1 Compatible
|
||||
+11 0 32M
|
||||
+11 1 64M
|
||||
+11 2 96M
|
||||
+11 3 128M
|
||||
+11 4 160M
|
||||
+11 5 192M
|
||||
+11 6 224M
|
||||
+14 0 Normal
|
||||
+14 1 Disabled
|
||||
+
|
||||
+# -----------------------------------------------------------------
|
||||
+checksums
|
||||
+
|
||||
+checksum 392 447 984
|
||||
diff --git a/src/mainboard/dell/e5420/data.vbt b/src/mainboard/dell/e5420/data.vbt
|
||||
new file mode 100755
|
||||
index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57
|
||||
GIT binary patch
|
||||
literal 6144
|
||||
zcmeHKeQZ-z6hE);wSBvNZ!2$ObQ^;MgV6zl*Rhp}BXnCCMZU^_r7jRwT!kfLo8?3H
|
||||
zk9)u(7?cb(hChhTM57@QFfmbMB!G!dNsO6BW5OSp5EGF^jHnTTdhUBI+h`e+1ft1q
|
||||
z^SfW?+;h)4_uO+|XEfEV$91)<gOArWE)OnSTD}Ug6?8a~vz+SmQn!4~y3N7b^|hPp
|
||||
zR<5aEfv-b8M00Lk251!oO|8(YA6XaeXzkt-Z)@Ee!_{@z#Fro^?DqN4SGjRIu8KYp
|
||||
zZEufuU@5MM@7jv%h;75FS}ezKv?JDzCH}d%tE)A-GuDb*+B%}~w%88r>}c;!*XQ5O
|
||||
z)OU7u$J@4U+lk)#GSW%c%c)v`%R6?`w)LIyu6bD7-j0o&X9qUMcEsYlW3BU4rZRvt
|
||||
zqAUpjf*qXuLCCsU0YM2I5@gB1WKd)f1+Yt?%HWd0DZxYumP(K<LxTif8A39+!KMl}
|
||||
z31FHG)7?qk5g>e?=ER{f^&}W<0k@mxff(?6+Stw+s6y%k1mM$cLk#^FWWI*9bE1GY
|
||||
z&VY9?WC1u#23^3^UYw5?H0x2S2gN`x18Fko6_x(#MKyuCU_<D!mEp$qO_An}#@>DV
|
||||
zdkf*li41yW3p$*0Oo3+63kO6S91*KwP#l2i4jnc)JkUirL^$k}VbH0;CBh#BS=OLf
|
||||
zW-yE3BRon75gG{_2~QIC5cUzCC%i)FCmbidM>tIwAPf>N5Pl?FC0r*+Sq!oXj!keQ
|
||||
zVKcyK>TL+gc7oLco$28+FpeeXkEP}_Sea=mk#IWUR^m$!BogvszLPu83FJm0k6K<l
|
||||
z$#$~YiXtY*GpHp#@FvHJ1UnBD*H%d+{_j24XE4nmBa*?5mOWiold28s3}>*}<HaeO
|
||||
z+1|-8g2)FCfkDZIdb-Ub);z0#;XEbPfGe?A72!{DAUg|$m+Z~(i@h9j4gtm611ni(
|
||||
z#u>ACcP}M4exU`*MKVwl5+t6JBpTkmm}xWflKUe~7}`!#%z#gAo{NxUrpDAndYktu
|
||||
zI0}VLU`J7^xmF1AFiz5S^uzp*DPI$%$qq!(ikh0kP+(GKzF|@N?Y%_#Vp@M+xHr$F
|
||||
z=%+18z`-fT%z)9-TS$~Dh@2yeN7!UIt0h`fWxUu`JvA_ra*8P48l%7KR0&c1;0R75
|
||||
z4f0oz(xQ3MWqz5>qW5M4tZWExHs8<H(e1G@4km@5wEzOOP^x<l`YmA|eKs6j3wl8B
|
||||
z%C%;uygh%<#kGZ{fymL+OlV0!-*T!V5IB>X@p!@CBU=7e{5^Jl{s7by`po-AJqM2l
|
||||
znk(=^0bHkF0rUw7)^7j;$=_UIs8`6P6b-;vPDZ#U9L)W1_PAYRDP9k~;5$stt5ZiV
|
||||
zD0>;i-?OlYY2}P9WVnfGos4xee2r=EGWHR}ADH$VV>cO=xU?!4TjIi)OMBYI_PX#b
|
||||
zm-eBHed5BOT-x6*W>;{IqAga~G6lCQT93k>Q}CpsomJR*1%FjEkv?fuT%c-8RklXO
|
||||
zU8;6KWk*zeU)4TW+1D!mrE0EhHZfbBeN{4S7X@Pig%};A99QTdA~wZruL*8y?K!jP
|
||||
zG5R*k=);S}Zn<T;W!Mxt`(!+z7_r@3LVpf|FESauM&4}+wqzXfba-zG>A}on(uzNF
|
||||
zyu>BcjA})C@bg%<;+Eh2;Sz4heFFCbZ@C{FrXMIbYzu>?Bi-|vZ}JSFU%JA>7$7et
|
||||
z0Yo%CnOVZm#ZA}4kWZOn15};h5*#OM3b+6vHzgruMP>=5MNJK1y42{YgveP-!j%#(
|
||||
z0rGe@8t%!=66Ti%K4|Gx=o7gFp83wQ;+s3H7+r^SKlpp3KKcr!3@|n;NCH_=qL=3T
|
||||
zq3WH?en`b+W-HR-fnrhw*9aZ%M}lHX7@H?E>!6wv_&YQFEHdA$%Z1R--yub>=c@p?
|
||||
z6@7Fc$&>sAxwiz{BE$1kb$K9Co=ozlA973y^i(^BM|EZ$$^y`0KyHiMJ%O*XbfEX1
|
||||
ziZaH>W(1pWL0bo|T!x__N$^$DpmxI=bL6WUK3JGyn?rw-qC4ZA$yGjIB}N(=ldD2O
|
||||
zAJ@bxp<qR-3lIv<!P~SE8r*#_Ckl?$0|1fZ>2>n}u*mUIYFd>}O_wuwBD^r9<#=!0
|
||||
X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
|
||||
diff --git a/src/mainboard/dell/e5420/devicetree.cb b/src/mainboard/dell/e5420/devicetree.cb
|
||||
new file mode 100644
|
||||
index 0000000000..f26413557d
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/devicetree.cb
|
||||
@@ -0,0 +1,66 @@
|
||||
+chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
|
||||
+ register "gfx" = "GMA_STATIC_DISPLAYS(1)"
|
||||
+ register "gpu_cpu_backlight" = "0x00000c31"
|
||||
+ register "gpu_dp_b_hotplug" = "4"
|
||||
+ register "gpu_dp_c_hotplug" = "4"
|
||||
+ register "gpu_dp_d_hotplug" = "4"
|
||||
+ register "gpu_panel_port_select" = "0"
|
||||
+ register "gpu_panel_power_backlight_off_delay" = "2300"
|
||||
+ register "gpu_panel_power_backlight_on_delay" = "2300"
|
||||
+ register "gpu_panel_power_cycle_delay" = "6"
|
||||
+ register "gpu_panel_power_down_delay" = "400"
|
||||
+ register "gpu_panel_power_up_delay" = "400"
|
||||
+ register "gpu_pch_backlight" = "0x13121312"
|
||||
+
|
||||
+ register "spd_addresses" = "{0x50, 0, 0x52, 0}"
|
||||
+
|
||||
+ device domain 0x0 on
|
||||
+ subsystemid 0x1028 0x049b inherit
|
||||
+
|
||||
+ device ref host_bridge on end # Host bridge
|
||||
+ device ref peg10 on end # PEG
|
||||
+ device ref igd on end # iGPU
|
||||
+
|
||||
+ chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
|
||||
+ register "docking_supported" = "1"
|
||||
+ register "gen1_dec" = "0x007c0681"
|
||||
+ register "gen2_dec" = "0x007c0901"
|
||||
+ register "gen3_dec" = "0x003c07e1"
|
||||
+ register "gen4_dec" = "0x001c0901"
|
||||
+ register "gpi0_routing" = "2"
|
||||
+ register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
|
||||
+ register "pcie_port_coalesce" = "1"
|
||||
+ register "sata_interface_speed_support" = "0x3"
|
||||
+ register "sata_port_map" = "0x3b"
|
||||
+ register "spi_lvscc" = "0x2005"
|
||||
+ register "spi_uvscc" = "0x2005"
|
||||
+
|
||||
+ device ref mei1 off end
|
||||
+ device ref mei2 off end
|
||||
+ device ref me_ide_r off end
|
||||
+ device ref me_kt off end
|
||||
+ device ref gbe off end
|
||||
+ device ref ehci2 on end
|
||||
+ device ref hda on end
|
||||
+ device ref pcie_rp1 on end
|
||||
+ device ref pcie_rp2 on end
|
||||
+ device ref pcie_rp3 on end
|
||||
+ device ref pcie_rp4 off end
|
||||
+ device ref pcie_rp5 on end
|
||||
+ device ref pcie_rp6 on end
|
||||
+ device ref pcie_rp7 on end
|
||||
+ device ref pcie_rp8 off end
|
||||
+ device ref ehci1 on end
|
||||
+ device ref pci_bridge off end
|
||||
+ device ref lpc on
|
||||
+ chip ec/dell/mec5035
|
||||
+ device pnp ff.0 on end
|
||||
+ end
|
||||
+ end
|
||||
+ device ref sata1 on end
|
||||
+ device ref smbus on end
|
||||
+ device ref sata2 off end
|
||||
+ device ref thermal off end
|
||||
+ end
|
||||
+ end
|
||||
+end
|
||||
diff --git a/src/mainboard/dell/e5420/dsdt.asl b/src/mainboard/dell/e5420/dsdt.asl
|
||||
new file mode 100644
|
||||
index 0000000000..7d13c55b08
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/dsdt.asl
|
||||
@@ -0,0 +1,30 @@
|
||||
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
|
||||
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <acpi/acpi.h>
|
||||
+
|
||||
+DefinitionBlock(
|
||||
+ "dsdt.aml",
|
||||
+ "DSDT",
|
||||
+ ACPI_DSDT_REV_2,
|
||||
+ OEM_ID,
|
||||
+ ACPI_TABLE_CREATOR,
|
||||
+ 0x20141018 /* OEM revision */
|
||||
+)
|
||||
+{
|
||||
+ #include <acpi/dsdt_top.asl>
|
||||
+ #include "acpi/platform.asl"
|
||||
+ #include <cpu/intel/common/acpi/cpu.asl>
|
||||
+ #include <southbridge/intel/common/acpi/platform.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
|
||||
+
|
||||
+ Device (\_SB.PCI0)
|
||||
+ {
|
||||
+ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
|
||||
+ #include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5420/early_init.c b/src/mainboard/dell/e5420/early_init.c
|
||||
new file mode 100644
|
||||
index 0000000000..7297921546
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/early_init.c
|
||||
@@ -0,0 +1,32 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+
|
||||
+#include <bootblock_common.h>
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <ec/dell/mec5035/mec5035.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+
|
||||
+const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 0 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 1 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 1, 2 },
|
||||
+ { 1, 1, 3 },
|
||||
+ { 1, 1, 3 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 5 },
|
||||
+ { 1, 1, 7 },
|
||||
+ { 1, 1, 6 },
|
||||
+ { 1, 1, 6 },
|
||||
+ { 1, 1, 7 },
|
||||
+};
|
||||
+
|
||||
+void bootblock_mainboard_early_init(void)
|
||||
+{
|
||||
+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
|
||||
+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
|
||||
+ | COMB_LPC_EN | COMA_LPC_EN);
|
||||
+ mec5035_early_init();
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/e5420/gma-mainboard.ads b/src/mainboard/dell/e5420/gma-mainboard.ads
|
||||
new file mode 100644
|
||||
index 0000000000..2a16f44360
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/gma-mainboard.ads
|
||||
@@ -0,0 +1,20 @@
|
||||
+-- SPDX-License-Identifier: GPL-2.0-or-later
|
||||
+
|
||||
+with HW.GFX.GMA;
|
||||
+with HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+use HW.GFX.GMA;
|
||||
+use HW.GFX.GMA.Display_Probing;
|
||||
+
|
||||
+private package GMA.Mainboard is
|
||||
+
|
||||
+ ports : constant Port_List :=
|
||||
+ (
|
||||
+ HDMI1, -- mainboard HDMI
|
||||
+ DP2, -- dock DP
|
||||
+ DP3, -- dock DP
|
||||
+ Analog, -- mainboard VGA
|
||||
+ LVDS,
|
||||
+ others => Disabled);
|
||||
+
|
||||
+end GMA.Mainboard;
|
||||
diff --git a/src/mainboard/dell/e5420/gpio.c b/src/mainboard/dell/e5420/gpio.c
|
||||
new file mode 100644
|
||||
index 0000000000..f76b93d9f0
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/gpio.c
|
||||
@@ -0,0 +1,195 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <southbridge/intel/common/gpio.h>
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
+ .gpio0 = GPIO_MODE_GPIO,
|
||||
+ .gpio1 = GPIO_MODE_NATIVE,
|
||||
+ .gpio2 = GPIO_MODE_GPIO,
|
||||
+ .gpio3 = GPIO_MODE_GPIO,
|
||||
+ .gpio4 = GPIO_MODE_GPIO,
|
||||
+ .gpio5 = GPIO_MODE_NATIVE,
|
||||
+ .gpio6 = GPIO_MODE_GPIO,
|
||||
+ .gpio7 = GPIO_MODE_GPIO,
|
||||
+ .gpio8 = GPIO_MODE_GPIO,
|
||||
+ .gpio9 = GPIO_MODE_NATIVE,
|
||||
+ .gpio10 = GPIO_MODE_NATIVE,
|
||||
+ .gpio11 = GPIO_MODE_NATIVE,
|
||||
+ .gpio12 = GPIO_MODE_GPIO,
|
||||
+ .gpio13 = GPIO_MODE_GPIO,
|
||||
+ .gpio14 = GPIO_MODE_GPIO,
|
||||
+ .gpio15 = GPIO_MODE_GPIO,
|
||||
+ .gpio16 = GPIO_MODE_NATIVE,
|
||||
+ .gpio17 = GPIO_MODE_GPIO,
|
||||
+ .gpio18 = GPIO_MODE_NATIVE,
|
||||
+ .gpio19 = GPIO_MODE_GPIO,
|
||||
+ .gpio20 = GPIO_MODE_NATIVE,
|
||||
+ .gpio21 = GPIO_MODE_GPIO,
|
||||
+ .gpio22 = GPIO_MODE_GPIO,
|
||||
+ .gpio23 = GPIO_MODE_NATIVE,
|
||||
+ .gpio24 = GPIO_MODE_GPIO,
|
||||
+ .gpio25 = GPIO_MODE_NATIVE,
|
||||
+ .gpio26 = GPIO_MODE_NATIVE,
|
||||
+ .gpio27 = GPIO_MODE_GPIO,
|
||||
+ .gpio28 = GPIO_MODE_GPIO,
|
||||
+ .gpio29 = GPIO_MODE_GPIO,
|
||||
+ .gpio30 = GPIO_MODE_GPIO,
|
||||
+ .gpio31 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
+ .gpio0 = GPIO_DIR_INPUT,
|
||||
+ .gpio2 = GPIO_DIR_INPUT,
|
||||
+ .gpio3 = GPIO_DIR_INPUT,
|
||||
+ .gpio4 = GPIO_DIR_INPUT,
|
||||
+ .gpio6 = GPIO_DIR_INPUT,
|
||||
+ .gpio7 = GPIO_DIR_INPUT,
|
||||
+ .gpio8 = GPIO_DIR_INPUT,
|
||||
+ .gpio12 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio13 = GPIO_DIR_INPUT,
|
||||
+ .gpio14 = GPIO_DIR_INPUT,
|
||||
+ .gpio15 = GPIO_DIR_INPUT,
|
||||
+ .gpio17 = GPIO_DIR_INPUT,
|
||||
+ .gpio19 = GPIO_DIR_INPUT,
|
||||
+ .gpio21 = GPIO_DIR_INPUT,
|
||||
+ .gpio22 = GPIO_DIR_INPUT,
|
||||
+ .gpio24 = GPIO_DIR_INPUT,
|
||||
+ .gpio27 = GPIO_DIR_INPUT,
|
||||
+ .gpio28 = GPIO_DIR_INPUT,
|
||||
+ .gpio29 = GPIO_DIR_INPUT,
|
||||
+ .gpio30 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
+ .gpio12 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio30 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
+ .gpio0 = GPIO_INVERT,
|
||||
+ .gpio8 = GPIO_INVERT,
|
||||
+ .gpio14 = GPIO_INVERT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
+ .gpio32 = GPIO_MODE_NATIVE,
|
||||
+ .gpio33 = GPIO_MODE_GPIO,
|
||||
+ .gpio34 = GPIO_MODE_GPIO,
|
||||
+ .gpio35 = GPIO_MODE_GPIO,
|
||||
+ .gpio36 = GPIO_MODE_GPIO,
|
||||
+ .gpio37 = GPIO_MODE_GPIO,
|
||||
+ .gpio38 = GPIO_MODE_GPIO,
|
||||
+ .gpio39 = GPIO_MODE_GPIO,
|
||||
+ .gpio40 = GPIO_MODE_NATIVE,
|
||||
+ .gpio41 = GPIO_MODE_NATIVE,
|
||||
+ .gpio42 = GPIO_MODE_NATIVE,
|
||||
+ .gpio43 = GPIO_MODE_NATIVE,
|
||||
+ .gpio44 = GPIO_MODE_NATIVE,
|
||||
+ .gpio45 = GPIO_MODE_NATIVE,
|
||||
+ .gpio46 = GPIO_MODE_GPIO,
|
||||
+ .gpio47 = GPIO_MODE_NATIVE,
|
||||
+ .gpio48 = GPIO_MODE_GPIO,
|
||||
+ .gpio49 = GPIO_MODE_NATIVE,
|
||||
+ .gpio50 = GPIO_MODE_GPIO,
|
||||
+ .gpio51 = GPIO_MODE_GPIO,
|
||||
+ .gpio52 = GPIO_MODE_GPIO,
|
||||
+ .gpio53 = GPIO_MODE_GPIO,
|
||||
+ .gpio54 = GPIO_MODE_GPIO,
|
||||
+ .gpio55 = GPIO_MODE_GPIO,
|
||||
+ .gpio56 = GPIO_MODE_GPIO,
|
||||
+ .gpio57 = GPIO_MODE_GPIO,
|
||||
+ .gpio58 = GPIO_MODE_NATIVE,
|
||||
+ .gpio59 = GPIO_MODE_NATIVE,
|
||||
+ .gpio60 = GPIO_MODE_GPIO,
|
||||
+ .gpio61 = GPIO_MODE_NATIVE,
|
||||
+ .gpio62 = GPIO_MODE_NATIVE,
|
||||
+ .gpio63 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
+ .gpio33 = GPIO_DIR_INPUT,
|
||||
+ .gpio34 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio35 = GPIO_DIR_INPUT,
|
||||
+ .gpio36 = GPIO_DIR_INPUT,
|
||||
+ .gpio37 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio38 = GPIO_DIR_INPUT,
|
||||
+ .gpio39 = GPIO_DIR_INPUT,
|
||||
+ .gpio46 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio48 = GPIO_DIR_INPUT,
|
||||
+ .gpio50 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio51 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio52 = GPIO_DIR_INPUT,
|
||||
+ .gpio53 = GPIO_DIR_INPUT,
|
||||
+ .gpio54 = GPIO_DIR_INPUT,
|
||||
+ .gpio55 = GPIO_DIR_OUTPUT,
|
||||
+ .gpio56 = GPIO_DIR_INPUT,
|
||||
+ .gpio57 = GPIO_DIR_INPUT,
|
||||
+ .gpio60 = GPIO_DIR_OUTPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
+ .gpio34 = GPIO_LEVEL_LOW,
|
||||
+ .gpio37 = GPIO_LEVEL_LOW,
|
||||
+ .gpio46 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio50 = GPIO_LEVEL_HIGH,
|
||||
+ .gpio51 = GPIO_LEVEL_LOW,
|
||||
+ .gpio55 = GPIO_LEVEL_LOW,
|
||||
+ .gpio60 = GPIO_LEVEL_HIGH,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
+ .gpio64 = GPIO_MODE_NATIVE,
|
||||
+ .gpio65 = GPIO_MODE_NATIVE,
|
||||
+ .gpio66 = GPIO_MODE_NATIVE,
|
||||
+ .gpio67 = GPIO_MODE_NATIVE,
|
||||
+ .gpio68 = GPIO_MODE_NATIVE,
|
||||
+ .gpio69 = GPIO_MODE_NATIVE,
|
||||
+ .gpio70 = GPIO_MODE_NATIVE,
|
||||
+ .gpio71 = GPIO_MODE_NATIVE,
|
||||
+ .gpio72 = GPIO_MODE_NATIVE,
|
||||
+ .gpio73 = GPIO_MODE_NATIVE,
|
||||
+ .gpio74 = GPIO_MODE_GPIO,
|
||||
+ .gpio75 = GPIO_MODE_NATIVE,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
+ .gpio74 = GPIO_DIR_INPUT,
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
+};
|
||||
+
|
||||
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
||||
+};
|
||||
+
|
||||
+const struct pch_gpio_map mainboard_gpio_map = {
|
||||
+ .set1 = {
|
||||
+ .mode = &pch_gpio_set1_mode,
|
||||
+ .direction = &pch_gpio_set1_direction,
|
||||
+ .level = &pch_gpio_set1_level,
|
||||
+ .blink = &pch_gpio_set1_blink,
|
||||
+ .invert = &pch_gpio_set1_invert,
|
||||
+ .reset = &pch_gpio_set1_reset,
|
||||
+ },
|
||||
+ .set2 = {
|
||||
+ .mode = &pch_gpio_set2_mode,
|
||||
+ .direction = &pch_gpio_set2_direction,
|
||||
+ .level = &pch_gpio_set2_level,
|
||||
+ .reset = &pch_gpio_set2_reset,
|
||||
+ },
|
||||
+ .set3 = {
|
||||
+ .mode = &pch_gpio_set3_mode,
|
||||
+ .direction = &pch_gpio_set3_direction,
|
||||
+ .level = &pch_gpio_set3_level,
|
||||
+ .reset = &pch_gpio_set3_reset,
|
||||
+ },
|
||||
+};
|
||||
diff --git a/src/mainboard/dell/e5420/hda_verb.c b/src/mainboard/dell/e5420/hda_verb.c
|
||||
new file mode 100644
|
||||
index 0000000000..70e7c2e79a
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/hda_verb.c
|
||||
@@ -0,0 +1,33 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/azalia_device.h>
|
||||
+
|
||||
+const u32 cim_verb_data[] = {
|
||||
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
|
||||
+ 0x1028049b, /* Subsystem ID */
|
||||
+ 11, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(0, 0x1028049b),
|
||||
+ AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
|
||||
+ AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
|
||||
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
||||
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
||||
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
||||
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
||||
+ AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
||||
+ AZALIA_PIN_CFG(0, 0x20, 0xd5a30130),
|
||||
+
|
||||
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
|
||||
+ 0x80860101, /* Subsystem ID */
|
||||
+ 4, /* Number of 4 dword sets */
|
||||
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
||||
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
||||
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
||||
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
||||
+
|
||||
+};
|
||||
+
|
||||
+const u32 pc_beep_verbs[0] = {};
|
||||
+
|
||||
+AZALIA_ARRAY_SIZES;
|
||||
diff --git a/src/mainboard/dell/e5420/mainboard.c b/src/mainboard/dell/e5420/mainboard.c
|
||||
new file mode 100644
|
||||
index 0000000000..31e49802fc
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/e5420/mainboard.c
|
||||
@@ -0,0 +1,21 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <device/device.h>
|
||||
+#include <drivers/intel/gma/int15.h>
|
||||
+#include <southbridge/intel/bd82x6x/pch.h>
|
||||
+#include <ec/acpi/ec.h>
|
||||
+#include <console/console.h>
|
||||
+#include <pc80/keyboard.h>
|
||||
+
|
||||
+static void mainboard_enable(struct device *dev)
|
||||
+{
|
||||
+
|
||||
+ /* FIXME: fix these values. */
|
||||
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
+ GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
+}
|
||||
+
|
||||
+struct chip_operations mainboard_ops = {
|
||||
+ .enable_dev = mainboard_enable,
|
||||
+};
|
||||
--
|
||||
2.44.0
|
||||
|
||||
@@ -0,0 +1,66 @@
|
||||
From 4889f08306f1530211dcc6f6a4e999c6cc72f3ac Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 30 Mar 2024 05:57:54 +0000
|
||||
Subject: [PATCH 1/1] fix sata ports on dell 9020 sff and mt
|
||||
|
||||
mate kukri has a patch under review on coreboot that sets
|
||||
sata port map to 0x7 on sff and 0xf on mt.
|
||||
|
||||
see: intel 8 series pch datasheet, section 13.1.35
|
||||
|
||||
basically, the 6 least significant bits enable the sata
|
||||
slots; 1 for enable and 0 for disable. there can be up
|
||||
to 6 ports. least significant bit is port 0, then next
|
||||
is port 1, and so on.
|
||||
|
||||
coreboot currently enables ports 0, 1, 4 and 5, making this
|
||||
value 0x33 (converted to binary: 00110011). sff has ports
|
||||
0, 1 and 2 wired, so mate changed that to 0x7 (00000111).
|
||||
|
||||
on mt, the blue ports are ports 0 and 1, but the two white
|
||||
ports don't work, but coreboot enables 4 and 5; it is
|
||||
likely that the blue ports are in fact 0 and 1, and the
|
||||
white ports are 2 and 3, but we've not tested this!
|
||||
|
||||
it could be that the blue ports are ports 4 and 5, and
|
||||
the white ports are 2 and 3! we have not yet determined
|
||||
this, but mate set it to 0xf, meaning ports 0 1 2 and 3
|
||||
are enabled, in his patch under review. the chance that
|
||||
it's 2, 3, 4 and 5 on the board is unlikely, but it is
|
||||
theoretically possible and has not been confirmed.
|
||||
|
||||
therefore, for now, i will set the value to 0x3f, which
|
||||
in binary is 00111111, thus enabling all 6 slots. the two
|
||||
that aren't physically wired don't really matter. enabling
|
||||
ports (from the pch) that electrically aren't there and
|
||||
then powering on is electrically equivalent to those ports
|
||||
being actually being wired, but with no devices plugged
|
||||
into them. therefore, 0x3f is an effective shotgun fix.
|
||||
|
||||
i'll remove this patch and use mate's fix when the latter
|
||||
has been tested on MT; it has already been tested on SFF.
|
||||
|
||||
this patch fixes the 3rd sata slot on 9020 sff, and the 3rd
|
||||
and 4th sata slots on 9020 MT
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/mainboard/dell/optiplex_9020/devicetree.cb | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
|
||||
index c0b17a15ff..7bfa6736a6 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
|
||||
+++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
|
||||
@@ -23,7 +23,7 @@ chip northbridge/intel/haswell
|
||||
register "gen2_dec" = "0x007c0901"
|
||||
register "gen3_dec" = "0x003c07e1"
|
||||
register "gen4_dec" = "0x001c0901"
|
||||
- register "sata_port_map" = "0x33"
|
||||
+ register "sata_port_map" = "0x3f"
|
||||
|
||||
device pci 14.0 on end # xHCI controller
|
||||
device pci 16.0 on end # Management Engine interface 1
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,54 @@
|
||||
From c6ce9c635e6576c86c546177c3d770dec2f3c9ae Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Fri, 23 Feb 2024 13:33:31 +0000
|
||||
Subject: [PATCH 1/1] nb/haswell: Disable iGPU when dGPU is used
|
||||
|
||||
This is usually is handled by Haswell mrc.bin, disabling VGA
|
||||
decode on the iGPU when a dGPU is installed. However, Broadwell
|
||||
mrc.bin does not, so the iGPU and dGPU are both enabled.
|
||||
|
||||
This patch disables legacy VGA cycles for iGPU, under such
|
||||
conditions. It has been tested on Broadwell mrc.bin when
|
||||
using a graphics card on Dell OptiPlex 9020 SFF (currently
|
||||
under review at this time of writing, submitted by Mate
|
||||
Kukri).
|
||||
|
||||
This patch has also been tested when Haswell mrc.bin is used,
|
||||
and there are seemingly no breaking changes caused by it.
|
||||
|
||||
Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717
|
||||
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
||||
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
||||
---
|
||||
src/northbridge/intel/haswell/gma.c | 7 +++++++
|
||||
1 file changed, 7 insertions(+)
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
|
||||
index 6e6948b70f..48a0ba54c7 100644
|
||||
--- a/src/northbridge/intel/haswell/gma.c
|
||||
+++ b/src/northbridge/intel/haswell/gma.c
|
||||
@@ -461,12 +461,19 @@ static void gma_generate_ssdt(const struct device *dev)
|
||||
drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
|
||||
}
|
||||
|
||||
+static void gma_func0_disable(struct device *dev)
|
||||
+{
|
||||
+ /* Disable VGA decode */
|
||||
+ pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
|
||||
+}
|
||||
+
|
||||
static struct device_operations gma_func0_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = gma_func0_init,
|
||||
.acpi_fill_ssdt = gma_generate_ssdt,
|
||||
+ .vga_disable = gma_func0_disable,
|
||||
.ops_pci = &pci_dev_ops_pci,
|
||||
};
|
||||
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+51
@@ -0,0 +1,51 @@
|
||||
From 0801b3ba8a0ce0109e30d27f405c912d5d705e9c Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 6 Apr 2024 01:22:47 +0100
|
||||
Subject: [PATCH 1/1] nb/haswell: Fully disable iGPU when dGPU is used
|
||||
|
||||
My earlier patch disabled decode *and* disabled the iGPU itself, but
|
||||
a subsequent revision disabled only VGA decode. Upon revisiting, I
|
||||
found that, actually, yes, you also need to disable the iGPU entirely.
|
||||
|
||||
Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU.
|
||||
With this patch, the iGPU is completely disabled when you install a
|
||||
graphics card, but the iGPU is available to use when no graphics card
|
||||
is present.
|
||||
|
||||
For more context, see:
|
||||
|
||||
Author: Leah Rowe <info@minifree.org>
|
||||
Date: Fri Feb 23 13:33:31 2024 +0000
|
||||
|
||||
nb/haswell: Disable iGPU when dGPU is used
|
||||
|
||||
And look at the Gerrit comments:
|
||||
|
||||
https://review.coreboot.org/c/coreboot/+/80717/
|
||||
|
||||
So, my original submission on change 80717 was actually correct.
|
||||
This patch fixes the issue. I tested on iGPU and dGPU, with both
|
||||
broadwell and haswell mrc.bin.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/northbridge/intel/haswell/gma.c | 3 +++
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
|
||||
index 48a0ba54c7..f0b848852d 100644
|
||||
--- a/src/northbridge/intel/haswell/gma.c
|
||||
+++ b/src/northbridge/intel/haswell/gma.c
|
||||
@@ -465,6 +465,9 @@ static void gma_func0_disable(struct device *dev)
|
||||
{
|
||||
/* Disable VGA decode */
|
||||
pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
|
||||
+
|
||||
+ /* Required or else the graphics card doesn't work */
|
||||
+ dev->enabled = 0;
|
||||
}
|
||||
|
||||
static struct device_operations gma_func0_ops = {
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+594
@@ -0,0 +1,594 @@
|
||||
From f6340f3fe21e948ba94d0429467882c2fb90b77e Mon Sep 17 00:00:00 2001
|
||||
From: Mate Kukri <kukri.mate@gmail.com>
|
||||
Date: Sat, 6 Apr 2024 23:25:15 +0100
|
||||
Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization
|
||||
|
||||
There are 4 different chassis types specified by vendor firmware, each
|
||||
with a slightly different HWM configuration.
|
||||
|
||||
The chassis type to use is determined at runtime by reading a set of
|
||||
4 PCH GPIOs: 70, 38, 17, and 0.
|
||||
|
||||
Additionally vendor firmware also provides an option to run the fans at
|
||||
full speed. This is substituted with a coreboot nvram option in this
|
||||
implementation.
|
||||
|
||||
This was tested to make fan control work on my OptiPlex 7020 SFF.
|
||||
|
||||
NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
|
||||
however the OptiPlex 9020's SCH5555 does not use externally
|
||||
programmed EC firmware.
|
||||
|
||||
Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
|
||||
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/optiplex_9020/Makefile.inc | 3 +-
|
||||
src/mainboard/dell/optiplex_9020/bootblock.c | 25 +-
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 1 +
|
||||
src/mainboard/dell/optiplex_9020/cmos.layout | 5 +-
|
||||
src/mainboard/dell/optiplex_9020/mainboard.c | 382 ++++++++++++++++++
|
||||
src/mainboard/dell/optiplex_9020/sch5555_ec.c | 54 +++
|
||||
src/mainboard/dell/optiplex_9020/sch5555_ec.h | 7 +
|
||||
7 files changed, 455 insertions(+), 22 deletions(-)
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c
|
||||
create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h
|
||||
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc
|
||||
index 6ca2f2afaa..08e2e53577 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/Makefile.inc
|
||||
+++ b/src/mainboard/dell/optiplex_9020/Makefile.inc
|
||||
@@ -2,4 +2,5 @@
|
||||
|
||||
romstage-y += gpio.c
|
||||
ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
|
||||
-bootblock-y += bootblock.c
|
||||
+ramstage-y += sch5555_ec.c
|
||||
+bootblock-y += bootblock.c sch5555_ec.c
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
|
||||
index 2837cf9cf1..e5e759273e 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/bootblock.c
|
||||
+++ b/src/mainboard/dell/optiplex_9020/bootblock.c
|
||||
@@ -4,29 +4,14 @@
|
||||
#include <device/pnp_ops.h>
|
||||
#include <superio/smsc/sch555x/sch555x.h>
|
||||
#include <southbridge/intel/lynxpoint/pch.h>
|
||||
-
|
||||
-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
|
||||
-{
|
||||
- // Clear EC-to-Host mailbox
|
||||
- uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
|
||||
- outb(tmp, SCH555x_EMI_IOBASE + 1);
|
||||
-
|
||||
- // Send address and value to the EC
|
||||
- sch555x_emi_write16(0, (addr1 * 2) | 0x101);
|
||||
- sch555x_emi_write32(4, val | (addr2 << 16));
|
||||
-
|
||||
- // Wait for acknowledgement message from EC
|
||||
- outb(1, SCH555x_EMI_IOBASE);
|
||||
- size_t timeout = 0;
|
||||
- do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
|
||||
-}
|
||||
+#include "sch5555_ec.h"
|
||||
|
||||
struct ec_init_entry {
|
||||
uint16_t addr;
|
||||
uint8_t val;
|
||||
};
|
||||
|
||||
-static void ec_init(void)
|
||||
+static void bootblock_ec_init(void)
|
||||
{
|
||||
/*
|
||||
* Tables from CORE_PEI
|
||||
@@ -108,9 +93,9 @@ void mainboard_config_superio(void)
|
||||
outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
|
||||
outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
|
||||
|
||||
- // Magic EC init
|
||||
- ec_init();
|
||||
+ // Perform bootblock EC initialization
|
||||
+ bootblock_ec_init();
|
||||
|
||||
- // Magic EC init is needed for UART1 initialization to work
|
||||
+ // Bootblock EC initialization is required for UART1 to work
|
||||
sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
}
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
index 7bccc80e51..1909abcb9f 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.default
|
||||
@@ -3,3 +3,4 @@ debug_level=Debug
|
||||
nmi=Disable
|
||||
power_on_after_fail=Disable
|
||||
iommu=Disable
|
||||
+fan_full_speed=Disable
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
index 72ff9c4bee..4a1496a878 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
|
||||
@@ -22,7 +22,10 @@ entries
|
||||
409 2 e 5 power_on_after_fail
|
||||
|
||||
# turn iommu on or off
|
||||
-412 1 e 6 iommu
|
||||
+411 1 e 6 iommu
|
||||
+
|
||||
+# coreboot config options: EC
|
||||
+412 1 e 1 fan_full_speed
|
||||
|
||||
# coreboot config options: check sums
|
||||
984 16 h 0 check_sum
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
|
||||
index c834fea5d3..10b8aaca0e 100644
|
||||
--- a/src/mainboard/dell/optiplex_9020/mainboard.c
|
||||
+++ b/src/mainboard/dell/optiplex_9020/mainboard.c
|
||||
@@ -1,7 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
+#include <bootstate.h>
|
||||
+#include <cpu/x86/msr.h>
|
||||
#include <device/device.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
+#include <option.h>
|
||||
+#include <southbridge/intel/lynxpoint/lp_gpio.h>
|
||||
+#include "sch5555_ec.h"
|
||||
|
||||
static void mainboard_enable(struct device *dev)
|
||||
{
|
||||
@@ -13,3 +18,380 @@ static void mainboard_enable(struct device *dev)
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
+
|
||||
+#define HWM_TAB_ADD_TEMP_TARGET 1
|
||||
+#define HWM_TAB_PKG_POWER_ANY 0xffff
|
||||
+
|
||||
+struct hwm_tab_entry {
|
||||
+ uint16_t addr;
|
||||
+ uint8_t val;
|
||||
+ uint8_t flags;
|
||||
+ uint16_t pkg_power;
|
||||
+};
|
||||
+
|
||||
+struct hwm_tab_entry HWM_TAB3[] = {
|
||||
+ { 0x005, 0x33, 0, 0xffff },
|
||||
+ { 0x018, 0x2f, 0, 0xffff },
|
||||
+ { 0x019, 0x2f, 0, 0xffff },
|
||||
+ { 0x01a, 0x2f, 0, 0xffff },
|
||||
+ { 0x080, 0x00, 0, 0xffff },
|
||||
+ { 0x081, 0x00, 0, 0xffff },
|
||||
+ { 0x083, 0xbb, 0, 0xffff },
|
||||
+ { 0x085, 0x8a, 0, 0x0010 },
|
||||
+ { 0x086, 0x4c, 0, 0x0010 },
|
||||
+ { 0x08a, 0x66, 0, 0x0010 },
|
||||
+ { 0x08b, 0x5b, 0, 0x0010 },
|
||||
+ { 0x090, 0x65, 0, 0xffff },
|
||||
+ { 0x091, 0x70, 0, 0xffff },
|
||||
+ { 0x092, 0x86, 0, 0xffff },
|
||||
+ { 0x096, 0xa4, 0, 0xffff },
|
||||
+ { 0x097, 0xa4, 0, 0xffff },
|
||||
+ { 0x098, 0xa4, 0, 0xffff },
|
||||
+ { 0x09b, 0xa4, 0, 0xffff },
|
||||
+ { 0x0a0, 0x0e, 0, 0xffff },
|
||||
+ { 0x0a1, 0x0e, 0, 0xffff },
|
||||
+ { 0x0ae, 0x7c, 0, 0xffff },
|
||||
+ { 0x0af, 0x86, 0, 0xffff },
|
||||
+ { 0x0b0, 0x9a, 0, 0xffff },
|
||||
+ { 0x0b3, 0x9a, 0, 0xffff },
|
||||
+ { 0x0b6, 0x08, 0, 0xffff },
|
||||
+ { 0x0b7, 0x08, 0, 0xffff },
|
||||
+ { 0x0ea, 0x64, 0, 0x0020 },
|
||||
+ { 0x0ea, 0x5c, 0, 0x0010 },
|
||||
+ { 0x0ef, 0xff, 0, 0xffff },
|
||||
+ { 0x0f8, 0x15, 0, 0xffff },
|
||||
+ { 0x0f9, 0x00, 0, 0xffff },
|
||||
+ { 0x0f0, 0x30, 0, 0xffff },
|
||||
+ { 0x0fd, 0x01, 0, 0xffff },
|
||||
+ { 0x1a1, 0x00, 0, 0xffff },
|
||||
+ { 0x1a2, 0x00, 0, 0xffff },
|
||||
+ { 0x1b1, 0x08, 0, 0xffff },
|
||||
+ { 0x1be, 0x99, 0, 0xffff },
|
||||
+ { 0x280, 0xa0, 0, 0x0010 },
|
||||
+ { 0x281, 0x0f, 0, 0x0010 },
|
||||
+ { 0x282, 0x03, 0, 0xffff },
|
||||
+ { 0x283, 0x0a, 0, 0xffff },
|
||||
+ { 0x284, 0x80, 0, 0xffff },
|
||||
+ { 0x285, 0x03, 0, 0xffff },
|
||||
+ { 0x288, 0x68, 0, 0x0010 },
|
||||
+ { 0x289, 0x10, 0, 0x0010 },
|
||||
+ { 0x28a, 0x03, 0, 0xffff },
|
||||
+ { 0x28b, 0x0a, 0, 0xffff },
|
||||
+ { 0x28c, 0x80, 0, 0xffff },
|
||||
+ { 0x28d, 0x03, 0, 0xffff },
|
||||
+};
|
||||
+
|
||||
+struct hwm_tab_entry HWM_TAB4[] = {
|
||||
+ { 0x005, 0x33, 0, 0xffff },
|
||||
+ { 0x018, 0x2f, 0, 0xffff },
|
||||
+ { 0x019, 0x2f, 0, 0xffff },
|
||||
+ { 0x01a, 0x2f, 0, 0xffff },
|
||||
+ { 0x080, 0x00, 0, 0xffff },
|
||||
+ { 0x081, 0x00, 0, 0xffff },
|
||||
+ { 0x083, 0xbb, 0, 0xffff },
|
||||
+ { 0x085, 0x99, 0, 0x0020 },
|
||||
+ { 0x085, 0xad, 0, 0x0010 },
|
||||
+ { 0x086, 0x1c, 0, 0xffff },
|
||||
+ { 0x08a, 0x39, 0, 0x0020 },
|
||||
+ { 0x08a, 0x41, 0, 0x0010 },
|
||||
+ { 0x08b, 0x76, 0, 0x0020 },
|
||||
+ { 0x08b, 0x8b, 0, 0x0010 },
|
||||
+ { 0x090, 0x5e, 0, 0xffff },
|
||||
+ { 0x091, 0x5e, 0, 0xffff },
|
||||
+ { 0x092, 0x86, 0, 0xffff },
|
||||
+ { 0x096, 0xa4, 0, 0xffff },
|
||||
+ { 0x097, 0xa4, 0, 0xffff },
|
||||
+ { 0x098, 0xa4, 0, 0xffff },
|
||||
+ { 0x09b, 0xa4, 0, 0xffff },
|
||||
+ { 0x0a0, 0x0a, 0, 0xffff },
|
||||
+ { 0x0a1, 0x0a, 0, 0xffff },
|
||||
+ { 0x0ae, 0x7c, 0, 0xffff },
|
||||
+ { 0x0af, 0x7c, 0, 0xffff },
|
||||
+ { 0x0b0, 0x9a, 0, 0xffff },
|
||||
+ { 0x0b3, 0x7c, 0, 0xffff },
|
||||
+ { 0x0b6, 0x08, 0, 0xffff },
|
||||
+ { 0x0b7, 0x08, 0, 0xffff },
|
||||
+ { 0x0ea, 0x64, 0, 0x0020 },
|
||||
+ { 0x0ea, 0x5c, 0, 0x0010 },
|
||||
+ { 0x0ef, 0xff, 0, 0xffff },
|
||||
+ { 0x0f8, 0x15, 0, 0xffff },
|
||||
+ { 0x0f9, 0x00, 0, 0xffff },
|
||||
+ { 0x0f0, 0x30, 0, 0xffff },
|
||||
+ { 0x0fd, 0x01, 0, 0xffff },
|
||||
+ { 0x1a1, 0x00, 0, 0xffff },
|
||||
+ { 0x1a2, 0x00, 0, 0xffff },
|
||||
+ { 0x1b1, 0x08, 0, 0xffff },
|
||||
+ { 0x1be, 0x90, 0, 0xffff },
|
||||
+ { 0x280, 0x94, 0, 0x0020 },
|
||||
+ { 0x281, 0x11, 0, 0x0020 },
|
||||
+ { 0x280, 0x94, 0, 0x0010 },
|
||||
+ { 0x281, 0x11, 0, 0x0010 },
|
||||
+ { 0x282, 0x03, 0, 0xffff },
|
||||
+ { 0x283, 0x0a, 0, 0xffff },
|
||||
+ { 0x284, 0x80, 0, 0xffff },
|
||||
+ { 0x285, 0x03, 0, 0xffff },
|
||||
+ { 0x288, 0x28, 0, 0x0020 },
|
||||
+ { 0x289, 0x0a, 0, 0x0020 },
|
||||
+ { 0x288, 0x28, 0, 0x0010 },
|
||||
+ { 0x289, 0x0a, 0, 0x0010 },
|
||||
+ { 0x28a, 0x03, 0, 0xffff },
|
||||
+ { 0x28b, 0x0a, 0, 0xffff },
|
||||
+ { 0x28c, 0x80, 0, 0xffff },
|
||||
+ { 0x28d, 0x03, 0, 0xffff },
|
||||
+};
|
||||
+
|
||||
+struct hwm_tab_entry HWM_TAB5[] = {
|
||||
+ { 0x005, 0x33, 0, 0xffff },
|
||||
+ { 0x018, 0x2f, 0, 0xffff },
|
||||
+ { 0x019, 0x2f, 0, 0xffff },
|
||||
+ { 0x01a, 0x2f, 0, 0xffff },
|
||||
+ { 0x080, 0x00, 0, 0xffff },
|
||||
+ { 0x081, 0x00, 0, 0xffff },
|
||||
+ { 0x083, 0xbb, 0, 0xffff },
|
||||
+ { 0x085, 0x66, 0, 0x0020 },
|
||||
+ { 0x085, 0x5d, 0, 0x0010 },
|
||||
+ { 0x086, 0x1c, 0, 0xffff },
|
||||
+ { 0x08a, 0x39, 0, 0x0020 },
|
||||
+ { 0x08a, 0x41, 0, 0x0010 },
|
||||
+ { 0x08b, 0x76, 0, 0x0020 },
|
||||
+ { 0x08b, 0x80, 0, 0x0010 },
|
||||
+ { 0x090, 0x5d, 0, 0x0020 },
|
||||
+ { 0x090, 0x5e, 0, 0x0010 },
|
||||
+ { 0x091, 0x5e, 0, 0xffff },
|
||||
+ { 0x092, 0x86, 0, 0xffff },
|
||||
+ { 0x096, 0xa4, 0, 0xffff },
|
||||
+ { 0x097, 0xa4, 0, 0xffff },
|
||||
+ { 0x098, 0xa3, 0, 0x0020 },
|
||||
+ { 0x098, 0xa4, 0, 0x0010 },
|
||||
+ { 0x09b, 0xa4, 0, 0xffff },
|
||||
+ { 0x0a0, 0x08, 0, 0xffff },
|
||||
+ { 0x0a1, 0x0a, 0, 0xffff },
|
||||
+ { 0x0ae, 0x7c, 0, 0xffff },
|
||||
+ { 0x0af, 0x7c, 0, 0xffff },
|
||||
+ { 0x0b0, 0x9a, 0, 0xffff },
|
||||
+ { 0x0b3, 0x7c, 0, 0xffff },
|
||||
+ { 0x0b6, 0x08, 0, 0xffff },
|
||||
+ { 0x0b7, 0x08, 0, 0xffff },
|
||||
+ { 0x0ea, 0x64, 0, 0x0020 },
|
||||
+ { 0x0ea, 0x5c, 0, 0x0010 },
|
||||
+ { 0x0ef, 0xff, 0, 0xffff },
|
||||
+ { 0x0f8, 0x15, 0, 0xffff },
|
||||
+ { 0x0f9, 0x00, 0, 0xffff },
|
||||
+ { 0x0f0, 0x30, 0, 0xffff },
|
||||
+ { 0x0fd, 0x01, 0, 0xffff },
|
||||
+ { 0x1a1, 0x00, 0, 0xffff },
|
||||
+ { 0x1a2, 0x00, 0, 0xffff },
|
||||
+ { 0x1b1, 0x08, 0, 0xffff },
|
||||
+ { 0x1be, 0x98, 0, 0x0020 },
|
||||
+ { 0x1be, 0x90, 0, 0x0010 },
|
||||
+ { 0x280, 0x94, 0, 0x0020 },
|
||||
+ { 0x281, 0x11, 0, 0x0020 },
|
||||
+ { 0x280, 0x94, 0, 0x0010 },
|
||||
+ { 0x281, 0x11, 0, 0x0010 },
|
||||
+ { 0x282, 0x03, 0, 0xffff },
|
||||
+ { 0x283, 0x0a, 0, 0xffff },
|
||||
+ { 0x284, 0x80, 0, 0xffff },
|
||||
+ { 0x285, 0x03, 0, 0xffff },
|
||||
+ { 0x288, 0x28, 0, 0x0020 },
|
||||
+ { 0x289, 0x0a, 0, 0x0020 },
|
||||
+ { 0x288, 0x28, 0, 0x0010 },
|
||||
+ { 0x289, 0x0a, 0, 0x0010 },
|
||||
+ { 0x28a, 0x03, 0, 0xffff },
|
||||
+ { 0x28b, 0x0a, 0, 0xffff },
|
||||
+ { 0x28c, 0x80, 0, 0xffff },
|
||||
+ { 0x28d, 0x03, 0, 0xffff },
|
||||
+};
|
||||
+
|
||||
+struct hwm_tab_entry HWM_TAB6[] = {
|
||||
+ { 0x005, 0x33, 0, 0xffff },
|
||||
+ { 0x018, 0x2f, 0, 0xffff },
|
||||
+ { 0x019, 0x2f, 0, 0xffff },
|
||||
+ { 0x01a, 0x2f, 0, 0xffff },
|
||||
+ { 0x080, 0x00, 0, 0xffff },
|
||||
+ { 0x081, 0x00, 0, 0xffff },
|
||||
+ { 0x083, 0xbb, 0, 0xffff },
|
||||
+ { 0x085, 0x98, 0, 0xffff },
|
||||
+ { 0x086, 0x3c, 0, 0xffff },
|
||||
+ { 0x08a, 0x39, 0, 0x0020 },
|
||||
+ { 0x08a, 0x3d, 0, 0x0010 },
|
||||
+ { 0x08b, 0x44, 0, 0x0020 },
|
||||
+ { 0x08b, 0x51, 0, 0x0010 },
|
||||
+ { 0x090, 0x61, 0, 0xffff },
|
||||
+ { 0x091, 0x6d, 0, 0xffff },
|
||||
+ { 0x092, 0x86, 0, 0xffff },
|
||||
+ { 0x096, 0xa4, 0, 0xffff },
|
||||
+ { 0x097, 0xa4, 0, 0xffff },
|
||||
+ { 0x098, 0x9f, 0, 0x0020 },
|
||||
+ { 0x098, 0xa4, 0, 0x0010 },
|
||||
+ { 0x09b, 0xa4, 0, 0xffff },
|
||||
+ { 0x0a0, 0x0e, 0, 0xffff },
|
||||
+ { 0x0a1, 0x0e, 0, 0xffff },
|
||||
+ { 0x0ae, 0x7c, 0, 0xffff },
|
||||
+ { 0x0af, 0x7c, 0, 0xffff },
|
||||
+ { 0x0b0, 0x9b, 0, 0x0020 },
|
||||
+ { 0x0b0, 0x98, 0, 0x0010 },
|
||||
+ { 0x0b3, 0x9a, 0, 0xffff },
|
||||
+ { 0x0b6, 0x08, 0, 0xffff },
|
||||
+ { 0x0b7, 0x08, 0, 0xffff },
|
||||
+ { 0x0ea, 0x64, 0, 0x0020 },
|
||||
+ { 0x0ea, 0x5c, 0, 0x0010 },
|
||||
+ { 0x0ef, 0xff, 0, 0xffff },
|
||||
+ { 0x0f8, 0x15, 0, 0xffff },
|
||||
+ { 0x0f9, 0x00, 0, 0xffff },
|
||||
+ { 0x0f0, 0x30, 0, 0xffff },
|
||||
+ { 0x0fd, 0x01, 0, 0xffff },
|
||||
+ { 0x1a1, 0x00, 0, 0xffff },
|
||||
+ { 0x1a2, 0x00, 0, 0xffff },
|
||||
+ { 0x1b1, 0x08, 0, 0xffff },
|
||||
+ { 0x1be, 0x9a, 0, 0x0020 },
|
||||
+ { 0x1be, 0x96, 0, 0x0010 },
|
||||
+ { 0x280, 0x94, 0, 0x0020 },
|
||||
+ { 0x281, 0x11, 0, 0x0020 },
|
||||
+ { 0x280, 0x94, 0, 0x0010 },
|
||||
+ { 0x281, 0x11, 0, 0x0010 },
|
||||
+ { 0x282, 0x03, 0, 0xffff },
|
||||
+ { 0x283, 0x0a, 0, 0xffff },
|
||||
+ { 0x284, 0x80, 0, 0xffff },
|
||||
+ { 0x285, 0x03, 0, 0xffff },
|
||||
+ { 0x288, 0x94, 0, 0x0020 },
|
||||
+ { 0x289, 0x11, 0, 0x0020 },
|
||||
+ { 0x288, 0x94, 0, 0x0010 },
|
||||
+ { 0x289, 0x11, 0, 0x0010 },
|
||||
+ { 0x28a, 0x03, 0, 0xffff },
|
||||
+ { 0x28b, 0x0a, 0, 0xffff },
|
||||
+ { 0x28c, 0x80, 0, 0xffff },
|
||||
+ { 0x28d, 0x03, 0, 0xffff },
|
||||
+};
|
||||
+
|
||||
+static uint8_t get_chassis_type(void)
|
||||
+{
|
||||
+ uint8_t gpio_chassis_type;
|
||||
+
|
||||
+ // Read chassis type from GPIO
|
||||
+ gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
|
||||
+ get_gpio(17) << 1 | get_gpio(0);
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
|
||||
+
|
||||
+ // Turn it into internal chassis index
|
||||
+ switch (gpio_chassis_type) {
|
||||
+ case 0x08:
|
||||
+ case 0x0a:
|
||||
+ return 4;
|
||||
+ case 0x0b:
|
||||
+ return 3;
|
||||
+ case 0x0c:
|
||||
+ return 5;
|
||||
+ case 0x0d: // SFF
|
||||
+ case 0x0e:
|
||||
+ case 0x0f:
|
||||
+ return 6;
|
||||
+ default:
|
||||
+ die("Unknown GPIO chassis type\n");
|
||||
+ }
|
||||
+
|
||||
+}
|
||||
+
|
||||
+static uint8_t get_temp_target(void)
|
||||
+{
|
||||
+ uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff;
|
||||
+ if (!val)
|
||||
+ val = 20;
|
||||
+ return 0x95 - val;
|
||||
+}
|
||||
+
|
||||
+static uint16_t get_pkg_power(void)
|
||||
+{
|
||||
+ uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf;
|
||||
+ if (rapl_power_unit)
|
||||
+ rapl_power_unit = 2 << (rapl_power_unit - 1);
|
||||
+ uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff;
|
||||
+ if (pkg_power_info / rapl_power_unit > 0x41)
|
||||
+ return 32;
|
||||
+ else
|
||||
+ return 16;
|
||||
+}
|
||||
+
|
||||
+static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size)
|
||||
+{
|
||||
+ uint8_t temp_target = get_temp_target();
|
||||
+ uint16_t pkg_power = get_pkg_power();
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target);
|
||||
+ printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power);
|
||||
+
|
||||
+ for (size_t i = 0; i < size; ++i) {
|
||||
+ // Skip entry if it doesn't apply for this package power
|
||||
+ if (arr[i].pkg_power != pkg_power &&
|
||||
+ arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY)
|
||||
+ continue;
|
||||
+
|
||||
+ uint8_t val = arr[i].val;
|
||||
+
|
||||
+ // Add temp target to value if requested (current tables never do)
|
||||
+ if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET)
|
||||
+ val += temp_target;
|
||||
+
|
||||
+ // Perform write
|
||||
+ ec_write(1, arr[i].addr, val);
|
||||
+
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void sch5555_ec_hwm_init(void *arg)
|
||||
+{
|
||||
+ uint8_t chassis_type, saved_2fc;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n");
|
||||
+
|
||||
+ saved_2fc = ec_read(1, 0x2fc);
|
||||
+ ec_write(1, 0x2fc, 0xa0);
|
||||
+ ec_write(1, 0x2fd, 0x32);
|
||||
+
|
||||
+ // Apply HWM table based on chassis type
|
||||
+ chassis_type = get_chassis_type();
|
||||
+ printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type);
|
||||
+ switch (chassis_type) {
|
||||
+ case 3:
|
||||
+ apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3));
|
||||
+ break;
|
||||
+ case 4:
|
||||
+ apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4));
|
||||
+ break;
|
||||
+ case 5:
|
||||
+ apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5));
|
||||
+ break;
|
||||
+ case 6:
|
||||
+ apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6));
|
||||
+ break;
|
||||
+ default:
|
||||
+ die("Unknown chassis type\n");
|
||||
+ }
|
||||
+
|
||||
+ if (CONFIG_MAX_CPUS > 2) {
|
||||
+ ec_write(1, 0x9e, 0x30);
|
||||
+ ec_write(1, 0xeb, ec_read(1, 0xea));
|
||||
+ }
|
||||
+
|
||||
+ ec_write(1, 0x2fc, saved_2fc);
|
||||
+
|
||||
+ // Apply full speed fan config if requested
|
||||
+ if (get_uint_option("fan_full_speed", 0)) {
|
||||
+ printk(BIOS_DEBUG, "Setting full fan speed\n");
|
||||
+ ec_write(1, 0x80, 0x60 | ec_read(1, 0x80));
|
||||
+ ec_write(1, 0x81, 0x60 | ec_read(1, 0x81));
|
||||
+ }
|
||||
+
|
||||
+ ec_read(1, 0xb8);
|
||||
+
|
||||
+ if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) {
|
||||
+ ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb);
|
||||
+ ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb);
|
||||
+ ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb);
|
||||
+ ec_write(1, 0x8a, 0x99);
|
||||
+ ec_write(1, 0x8b, 0x47);
|
||||
+ ec_write(1, 0x8c, 0x91);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL);
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
|
||||
new file mode 100644
|
||||
index 0000000000..92244da9ab
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
|
||||
@@ -0,0 +1,54 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#include <arch/io.h>
|
||||
+#include <device/pnp_ops.h>
|
||||
+#include <superio/smsc/sch555x/sch555x.h>
|
||||
+#include "sch5555_ec.h"
|
||||
+
|
||||
+uint8_t ec_read(uint8_t addr1, uint16_t addr2)
|
||||
+{
|
||||
+ // clear ec-to-host mailbox
|
||||
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
|
||||
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
|
||||
+
|
||||
+ // send address
|
||||
+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
|
||||
+ outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4);
|
||||
+
|
||||
+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
|
||||
+ outl(addr2 << 16, SCH555x_EMI_IOBASE + 4);
|
||||
+
|
||||
+ // send message to ec
|
||||
+ outb(1, SCH555x_EMI_IOBASE);
|
||||
+
|
||||
+ // wait for ack
|
||||
+ for (size_t timeout = 0; timeout < 0xfff; ++timeout)
|
||||
+ if (inb(SCH555x_EMI_IOBASE + 1) & 1)
|
||||
+ break;
|
||||
+
|
||||
+ // read result
|
||||
+ outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2);
|
||||
+ return inb(SCH555x_EMI_IOBASE + 4);
|
||||
+}
|
||||
+
|
||||
+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
|
||||
+{
|
||||
+ // clear ec-to-host mailbox
|
||||
+ uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
|
||||
+ outb(tmp, SCH555x_EMI_IOBASE + 1);
|
||||
+
|
||||
+ // send address and value
|
||||
+ outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
|
||||
+ outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4);
|
||||
+
|
||||
+ outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
|
||||
+ outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4);
|
||||
+
|
||||
+ // send message to ec
|
||||
+ outb(1, SCH555x_EMI_IOBASE);
|
||||
+
|
||||
+ // wait for ack
|
||||
+ for (size_t timeout = 0; timeout < 0xfff; ++timeout)
|
||||
+ if (inb(SCH555x_EMI_IOBASE + 1) & 1)
|
||||
+ break;
|
||||
+}
|
||||
diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
|
||||
new file mode 100644
|
||||
index 0000000000..6e703ff865
|
||||
--- /dev/null
|
||||
+++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
|
||||
@@ -0,0 +1,7 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
+
|
||||
+#pragma once
|
||||
+
|
||||
+uint8_t ec_read(uint8_t addr1, uint16_t addr2);
|
||||
+
|
||||
+void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val);
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,348 @@
|
||||
From f3c5218c6d7e211c9e8425e5e71cda76a7de1fad Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sat, 7 May 2022 14:36:10 +0200
|
||||
Subject: [PATCH 01/15] haswell NRI: Initialise MPLL
|
||||
|
||||
Add code to initialise the MPLL (Memory PLL). The procedure is similar
|
||||
to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
|
||||
|
||||
Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../intel/haswell/native_raminit/Makefile.mk | 2 +
|
||||
.../intel/haswell/native_raminit/init_mpll.c | 210 ++++++++++++++++++
|
||||
.../haswell/native_raminit/io_comp_control.c | 22 ++
|
||||
.../haswell/native_raminit/raminit_main.c | 3 +-
|
||||
.../haswell/native_raminit/raminit_native.h | 11 +
|
||||
.../intel/haswell/registers/mchbar.h | 3 +
|
||||
6 files changed, 250 insertions(+), 1 deletion(-)
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/init_mpll.c
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/io_comp_control.c
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
index ebf7abc6ec..c125d84f0b 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
@@ -1,5 +1,7 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
+romstage-y += init_mpll.c
|
||||
+romstage-y += io_comp_control.c
|
||||
romstage-y += raminit_main.c
|
||||
romstage-y += raminit_native.c
|
||||
romstage-y += spd_bitmunching.c
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
|
||||
new file mode 100644
|
||||
index 0000000000..2faa183724
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
|
||||
@@ -0,0 +1,210 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <commonlib/clamp.h>
|
||||
+#include <console/console.h>
|
||||
+#include <delay.h>
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+#include <types.h>
|
||||
+
|
||||
+#include "raminit_native.h"
|
||||
+
|
||||
+static uint32_t get_mem_multiplier(const struct sysinfo *ctrl)
|
||||
+{
|
||||
+ const uint32_t mult = NS2MHZ_DIV256 / (ctrl->tCK * ctrl->base_freq);
|
||||
+
|
||||
+ if (ctrl->base_freq == 100)
|
||||
+ return clamp_u32(7, mult, 12);
|
||||
+
|
||||
+ if (ctrl->base_freq == 133)
|
||||
+ return clamp_u32(3, mult, 10);
|
||||
+
|
||||
+ die("Unsupported base frequency\n");
|
||||
+}
|
||||
+
|
||||
+static void normalize_tck(struct sysinfo *ctrl, const bool pll_ref100)
|
||||
+{
|
||||
+ /** TODO: Haswell supports up to DDR3-2600 **/
|
||||
+ if (ctrl->tCK <= TCK_1200MHZ) {
|
||||
+ ctrl->tCK = TCK_1200MHZ;
|
||||
+ ctrl->base_freq = 133;
|
||||
+ ctrl->mem_clock_mhz = 1200;
|
||||
+
|
||||
+ } else if (ctrl->tCK <= TCK_1100MHZ) {
|
||||
+ ctrl->tCK = TCK_1100MHZ;
|
||||
+ ctrl->base_freq = 100;
|
||||
+ ctrl->mem_clock_mhz = 1100;
|
||||
+
|
||||
+ } else if (ctrl->tCK <= TCK_1066MHZ) {
|
||||
+ ctrl->tCK = TCK_1066MHZ;
|
||||
+ ctrl->base_freq = 133;
|
||||
+ ctrl->mem_clock_mhz = 1066;
|
||||
+
|
||||
+ } else if (ctrl->tCK <= TCK_1000MHZ) {
|
||||
+ ctrl->tCK = TCK_1000MHZ;
|
||||
+ ctrl->base_freq = 100;
|
||||
+ ctrl->mem_clock_mhz = 1000;
|
||||
+
|
||||
+ } else if (ctrl->tCK <= TCK_933MHZ) {
|
||||
+ ctrl->tCK = TCK_933MHZ;
|
||||
+ ctrl->base_freq = 133;
|
||||
+ ctrl->mem_clock_mhz = 933;
|
||||
+
|
||||
+ } else if (ctrl->tCK <= TCK_900MHZ) {
|
||||
+ ctrl->tCK = TCK_900MHZ;
|
||||
+ ctrl->base_freq = 100;
|
||||
+ ctrl->mem_clock_mhz = 900;
|
||||
+
|
||||
+ } else if (ctrl->tCK <= TCK_800MHZ) {
|
||||
+ ctrl->tCK = TCK_800MHZ;
|
||||
+ ctrl->base_freq = 133;
|
||||
+ ctrl->mem_clock_mhz = 800;
|
||||
+
|
||||
+ } else if (ctrl->tCK <= TCK_700MHZ) {
|
||||
+ ctrl->tCK = TCK_700MHZ;
|
||||
+ ctrl->base_freq = 100;
|
||||
+ ctrl->mem_clock_mhz = 700;
|
||||
+
|
||||
+ } else if (ctrl->tCK <= TCK_666MHZ) {
|
||||
+ ctrl->tCK = TCK_666MHZ;
|
||||
+ ctrl->base_freq = 133;
|
||||
+ ctrl->mem_clock_mhz = 666;
|
||||
+
|
||||
+ } else if (ctrl->tCK <= TCK_533MHZ) {
|
||||
+ ctrl->tCK = TCK_533MHZ;
|
||||
+ ctrl->base_freq = 133;
|
||||
+ ctrl->mem_clock_mhz = 533;
|
||||
+
|
||||
+ } else if (ctrl->tCK <= TCK_400MHZ) {
|
||||
+ ctrl->tCK = TCK_400MHZ;
|
||||
+ ctrl->base_freq = 133;
|
||||
+ ctrl->mem_clock_mhz = 400;
|
||||
+
|
||||
+ } else {
|
||||
+ ctrl->tCK = 0;
|
||||
+ ctrl->base_freq = 1;
|
||||
+ ctrl->mem_clock_mhz = 0;
|
||||
+ return;
|
||||
+ }
|
||||
+ if (!pll_ref100 && ctrl->base_freq == 100) {
|
||||
+ /* Skip unsupported frequency */
|
||||
+ ctrl->tCK++;
|
||||
+ normalize_tck(ctrl, pll_ref100);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+#define MIN_CAS 4
|
||||
+#define MAX_CAS 24
|
||||
+
|
||||
+static uint8_t find_compatible_cas(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ printk(RAM_DEBUG, "With tCK %u, try CAS: ", ctrl->tCK);
|
||||
+ const uint8_t cas_lower = MAX(MIN_CAS, DIV_ROUND_UP(ctrl->tAA, ctrl->tCK));
|
||||
+ const uint8_t cas_upper = MIN(MAX_CAS, 19); /* JEDEC MR0 limit */
|
||||
+
|
||||
+ if (!(ctrl->cas_supported >> (cas_lower - MIN_CAS))) {
|
||||
+ printk(RAM_DEBUG, "DIMMs do not support CAS >= %u\n", cas_lower);
|
||||
+ ctrl->tCK++;
|
||||
+ return 0;
|
||||
+ }
|
||||
+ for (uint8_t cas = cas_lower; cas <= cas_upper; cas++) {
|
||||
+ printk(RAM_DEBUG, "%u ", cas);
|
||||
+ if (ctrl->cas_supported & BIT(cas - MIN_CAS)) {
|
||||
+ printk(RAM_DEBUG, "OK\n");
|
||||
+ return cas;
|
||||
+ }
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static enum raminit_status find_cas_tck(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ /** TODO: Honor all possible PLL_REF100_CFG values **/
|
||||
+ uint8_t pll_ref100 = (pci_read_config32(HOST_BRIDGE, CAPID0_B) >> 21) & 0x7;
|
||||
+ printk(RAM_DEBUG, "PLL_REF100_CFG value: 0x%x\n", pll_ref100);
|
||||
+ printk(RAM_DEBUG, "100MHz reference clock support: %s\n", pll_ref100 ? "yes" : "no");
|
||||
+
|
||||
+ uint8_t selected_cas;
|
||||
+ while (true) {
|
||||
+ /* Round tCK up so that it is a multiple of either 133 or 100 MHz */
|
||||
+ normalize_tck(ctrl, pll_ref100);
|
||||
+ if (!ctrl->tCK) {
|
||||
+ printk(BIOS_ERR, "Couldn't find compatible clock / CAS settings\n");
|
||||
+ return RAMINIT_STATUS_MPLL_INIT_FAILURE;
|
||||
+ }
|
||||
+ selected_cas = find_compatible_cas(ctrl);
|
||||
+ if (selected_cas)
|
||||
+ break;
|
||||
+
|
||||
+ ctrl->tCK++;
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "Found compatible clock / CAS settings\n");
|
||||
+ printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK);
|
||||
+ printk(BIOS_DEBUG, "Selected CAS latency : %uT\n", selected_cas);
|
||||
+ ctrl->multiplier = get_mem_multiplier(ctrl);
|
||||
+ return RAMINIT_STATUS_SUCCESS;
|
||||
+}
|
||||
+
|
||||
+enum raminit_status initialise_mpll(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ if (ctrl->tCK > TCK_400MHZ) {
|
||||
+ printk(BIOS_ERR, "tCK is too slow. Increasing to 400 MHz as last resort\n");
|
||||
+ ctrl->tCK = TCK_400MHZ;
|
||||
+ }
|
||||
+ while (true) {
|
||||
+ if (!ctrl->qclkps) {
|
||||
+ const enum raminit_status status = find_cas_tck(ctrl);
|
||||
+ if (status)
|
||||
+ return status;
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * Unlike previous generations, Haswell's MPLL won't shut down if the
|
||||
+ * requested frequency isn't supported. But we cannot reinitialize it.
|
||||
+ * Another different thing: MPLL registers are 4-bit instead of 8-bit.
|
||||
+ */
|
||||
+
|
||||
+ /** FIXME: Obtain current clock frequency if we want to skip this **/
|
||||
+ //if (mchbar_read32(MC_BIOS_DATA) != 0)
|
||||
+ // break;
|
||||
+
|
||||
+ uint32_t mc_bios_req = ctrl->multiplier;
|
||||
+ if (ctrl->base_freq == 100) {
|
||||
+ /* Use 100 MHz reference clock */
|
||||
+ mc_bios_req |= BIT(4);
|
||||
+ }
|
||||
+ mc_bios_req |= BIT(31);
|
||||
+ printk(RAM_DEBUG, "MC_BIOS_REQ = 0x%08x\n", mc_bios_req);
|
||||
+ printk(BIOS_DEBUG, "MPLL busy... ");
|
||||
+ mchbar_write32(MC_BIOS_REQ, mc_bios_req);
|
||||
+
|
||||
+ for (unsigned int i = 0; i <= 5000; i++) {
|
||||
+ if (!(mchbar_read32(MC_BIOS_REQ) & BIT(31))) {
|
||||
+ printk(BIOS_DEBUG, "done in %u us\n", i);
|
||||
+ break;
|
||||
+ }
|
||||
+ udelay(1);
|
||||
+ }
|
||||
+ if (mchbar_read32(MC_BIOS_REQ) & BIT(31))
|
||||
+ printk(BIOS_DEBUG, "did not lock\n");
|
||||
+
|
||||
+ /* Verify locked frequency */
|
||||
+ const uint32_t mc_bios_data = mchbar_read32(MC_BIOS_DATA);
|
||||
+ printk(RAM_DEBUG, "MC_BIOS_DATA = 0x%08x\n", mc_bios_data);
|
||||
+ if ((mc_bios_data & 0xf) >= ctrl->multiplier)
|
||||
+ break;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Retrying at a lower frequency\n\n");
|
||||
+ ctrl->tCK++;
|
||||
+ }
|
||||
+ if (!ctrl->mem_clock_mhz) {
|
||||
+ printk(BIOS_ERR, "Could not program MPLL frequency\n");
|
||||
+ return RAMINIT_STATUS_MPLL_INIT_FAILURE;
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "MPLL frequency is set to: %u MHz ", ctrl->mem_clock_mhz);
|
||||
+ ctrl->mem_clock_fs = 1000000000 / ctrl->mem_clock_mhz;
|
||||
+ printk(BIOS_DEBUG, "(period: %u femtoseconds)\n", ctrl->mem_clock_fs);
|
||||
+ ctrl->qclkps = ctrl->mem_clock_fs / 2000;
|
||||
+ printk(BIOS_DEBUG, "Quadrature clock period: %u picoseconds\n", ctrl->qclkps);
|
||||
+ return wait_for_first_rcomp();
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
|
||||
new file mode 100644
|
||||
index 0000000000..7e96c08938
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
|
||||
@@ -0,0 +1,22 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <commonlib/clamp.h>
|
||||
+#include <console/console.h>
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+#include <timer.h>
|
||||
+#include <types.h>
|
||||
+
|
||||
+#include "raminit_native.h"
|
||||
+
|
||||
+enum raminit_status wait_for_first_rcomp(void)
|
||||
+{
|
||||
+ struct stopwatch timer;
|
||||
+ stopwatch_init_msecs_expire(&timer, 2000);
|
||||
+ do {
|
||||
+ if (mchbar_read32(RCOMP_TIMER) & BIT(16))
|
||||
+ return RAMINIT_STATUS_SUCCESS;
|
||||
+
|
||||
+ } while (!stopwatch_expired(&timer));
|
||||
+ printk(BIOS_ERR, "Timed out waiting for RCOMP to complete\n");
|
||||
+ return RAMINIT_STATUS_POLL_TIMEOUT;
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
index b06330c4eb..09545422c0 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
@@ -20,7 +20,8 @@ struct task_entry {
|
||||
};
|
||||
|
||||
static const struct task_entry cold_boot[] = {
|
||||
- { collect_spd_info, true, "PROCSPD", },
|
||||
+ { collect_spd_info, true, "PROCSPD", },
|
||||
+ { initialise_mpll, true, "INITMPLL", },
|
||||
};
|
||||
|
||||
/* Return a generic stepping value to make stepping checks simpler */
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index 1a0793947e..a54581abc7 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -23,6 +23,8 @@ enum raminit_status {
|
||||
RAMINIT_STATUS_SUCCESS = 0,
|
||||
RAMINIT_STATUS_NO_MEMORY_INSTALLED,
|
||||
RAMINIT_STATUS_UNSUPPORTED_MEMORY,
|
||||
+ RAMINIT_STATUS_MPLL_INIT_FAILURE,
|
||||
+ RAMINIT_STATUS_POLL_TIMEOUT,
|
||||
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
|
||||
};
|
||||
|
||||
@@ -82,10 +84,19 @@ struct sysinfo {
|
||||
uint8_t rankmap[NUM_CHANNELS];
|
||||
uint8_t rank_mirrored[NUM_CHANNELS];
|
||||
uint32_t channel_size_mb[NUM_CHANNELS];
|
||||
+
|
||||
+ uint8_t base_freq; /* Memory base frequency, either 100 or 133 MHz */
|
||||
+ uint32_t multiplier;
|
||||
+ uint32_t mem_clock_mhz;
|
||||
+ uint32_t mem_clock_fs; /* Memory clock period in femtoseconds */
|
||||
+ uint32_t qclkps; /* Quadrature clock period in picoseconds */
|
||||
};
|
||||
|
||||
void raminit_main(enum raminit_boot_mode bootmode);
|
||||
|
||||
enum raminit_status collect_spd_info(struct sysinfo *ctrl);
|
||||
+enum raminit_status initialise_mpll(struct sysinfo *ctrl);
|
||||
+
|
||||
+enum raminit_status wait_for_first_rcomp(void);
|
||||
|
||||
#endif
|
||||
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
index 5610e7089a..45f8174995 100644
|
||||
--- a/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
@@ -13,6 +13,8 @@
|
||||
#define MC_INIT_STATE_G 0x5030
|
||||
#define MRC_REVISION 0x5034 /* MRC Revision */
|
||||
|
||||
+#define RCOMP_TIMER 0x5084
|
||||
+
|
||||
#define MC_LOCK 0x50fc /* Memory Controller Lock register */
|
||||
|
||||
#define GFXVTBAR 0x5400 /* Base address for IGD */
|
||||
@@ -61,6 +63,7 @@
|
||||
|
||||
#define BIOS_RESET_CPL 0x5da8 /* 8-bit */
|
||||
|
||||
+#define MC_BIOS_REQ 0x5e00 /* Memory frequency request register */
|
||||
#define MC_BIOS_DATA 0x5e04 /* Miscellaneous information for BIOS */
|
||||
#define SAPMCTL 0x5f00
|
||||
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,249 @@
|
||||
From e344871e519441d1f7bc6891ca1eda911e3e4bf5 Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sat, 7 May 2022 16:29:55 +0200
|
||||
Subject: [PATCH 02/15] haswell NRI: Post-process selected timings
|
||||
|
||||
Once the MPLL has been initialised, convert the timings from the SPD to
|
||||
be in DCLKs, which is what the hardware expects. In addition, calculate
|
||||
the values for tREFI and tXP.
|
||||
|
||||
Change-Id: Id02caf858f75b9e08016762b3aefda282b274386
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../intel/haswell/native_raminit/Makefile.mk | 1 +
|
||||
.../haswell/native_raminit/lookup_timings.c | 62 +++++++++++
|
||||
.../haswell/native_raminit/raminit_main.c | 1 +
|
||||
.../haswell/native_raminit/raminit_native.h | 8 ++
|
||||
.../haswell/native_raminit/spd_bitmunching.c | 100 ++++++++++++++++++
|
||||
5 files changed, 172 insertions(+)
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/lookup_timings.c
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
index c125d84f0b..2769e0bbb4 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
@@ -1,5 +1,6 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
+romstage-y += lookup_timings.c
|
||||
romstage-y += init_mpll.c
|
||||
romstage-y += io_comp_control.c
|
||||
romstage-y += raminit_main.c
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
|
||||
new file mode 100644
|
||||
index 0000000000..038686c844
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
|
||||
@@ -0,0 +1,62 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <commonlib/clamp.h>
|
||||
+#include <types.h>
|
||||
+
|
||||
+#include "raminit_native.h"
|
||||
+
|
||||
+struct timing_lookup {
|
||||
+ uint32_t clock;
|
||||
+ uint32_t value;
|
||||
+};
|
||||
+
|
||||
+static uint32_t lookup_timing(
|
||||
+ const uint32_t mem_clock_mhz,
|
||||
+ const struct timing_lookup *const lookup,
|
||||
+ const size_t length)
|
||||
+{
|
||||
+ /* Fall back to the last index */
|
||||
+ size_t i;
|
||||
+ for (i = 0; i < length - 1; i++) {
|
||||
+ /* Account for imprecise frequency values */
|
||||
+ if ((mem_clock_mhz - 5) <= lookup[i].clock)
|
||||
+ break;
|
||||
+ }
|
||||
+ return lookup[i].value;
|
||||
+}
|
||||
+
|
||||
+static const uint32_t fmax = UINT32_MAX;
|
||||
+
|
||||
+uint8_t get_tCWL(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ const struct timing_lookup lut[] = {
|
||||
+ { 400, 5 },
|
||||
+ { 533, 6 },
|
||||
+ { 666, 7 },
|
||||
+ { 800, 8 },
|
||||
+ { 933, 9 },
|
||||
+ { 1066, 10 },
|
||||
+ { 1200, 11 },
|
||||
+ { fmax, 12 },
|
||||
+ };
|
||||
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
|
||||
+}
|
||||
+
|
||||
+/* tREFI = 7800 ns * DDR MHz */
|
||||
+uint32_t get_tREFI(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ return (mem_clock_mhz * 7800) / 1000;
|
||||
+}
|
||||
+
|
||||
+uint32_t get_tXP(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ const struct timing_lookup lut[] = {
|
||||
+ { 400, 3 },
|
||||
+ { 666, 4 },
|
||||
+ { 800, 5 },
|
||||
+ { 933, 6 },
|
||||
+ { 1066, 7 },
|
||||
+ { fmax, 8 },
|
||||
+ };
|
||||
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
index 09545422c0..5f2be980d4 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
@@ -22,6 +22,7 @@ struct task_entry {
|
||||
static const struct task_entry cold_boot[] = {
|
||||
{ collect_spd_info, true, "PROCSPD", },
|
||||
{ initialise_mpll, true, "INITMPLL", },
|
||||
+ { convert_timings, true, "CONVTIM", },
|
||||
};
|
||||
|
||||
/* Return a generic stepping value to make stepping checks simpler */
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index a54581abc7..01e5ed1bd6 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -78,6 +78,9 @@ struct sysinfo {
|
||||
uint32_t tCWL;
|
||||
uint32_t tCMD;
|
||||
|
||||
+ uint32_t tREFI;
|
||||
+ uint32_t tXP;
|
||||
+
|
||||
uint8_t lanes; /* 8 or 9 */
|
||||
uint8_t chanmap;
|
||||
uint8_t dpc[NUM_CHANNELS]; /* DIMMs per channel */
|
||||
@@ -96,7 +99,12 @@ void raminit_main(enum raminit_boot_mode bootmode);
|
||||
|
||||
enum raminit_status collect_spd_info(struct sysinfo *ctrl);
|
||||
enum raminit_status initialise_mpll(struct sysinfo *ctrl);
|
||||
+enum raminit_status convert_timings(struct sysinfo *ctrl);
|
||||
|
||||
enum raminit_status wait_for_first_rcomp(void);
|
||||
|
||||
+uint8_t get_tCWL(uint32_t mem_clock_mhz);
|
||||
+uint32_t get_tREFI(uint32_t mem_clock_mhz);
|
||||
+uint32_t get_tXP(uint32_t mem_clock_mhz);
|
||||
+
|
||||
#endif
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
|
||||
index 2dab8504c4..9ba695fb64 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
|
||||
@@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl)
|
||||
get_spd_data(ctrl);
|
||||
return find_common_spd_parameters(ctrl);
|
||||
}
|
||||
+
|
||||
+#define MIN_CWL 5
|
||||
+#define MAX_CWL 12
|
||||
+
|
||||
+/* Except for tCK, hardware expects all timing values in DCLKs, not nanoseconds */
|
||||
+enum raminit_status convert_timings(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ /*
|
||||
+ * Obtain all required timing values, in DCLKs.
|
||||
+ */
|
||||
+
|
||||
+ /* Convert primary timings from nanoseconds to DCLKs */
|
||||
+ ctrl->tAA = DIV_ROUND_UP(ctrl->tAA, ctrl->tCK);
|
||||
+ ctrl->tWR = DIV_ROUND_UP(ctrl->tWR, ctrl->tCK);
|
||||
+ ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
|
||||
+ ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
|
||||
+ ctrl->tRP = DIV_ROUND_UP(ctrl->tRP, ctrl->tCK);
|
||||
+ ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
|
||||
+ ctrl->tRC = DIV_ROUND_UP(ctrl->tRC, ctrl->tCK);
|
||||
+ ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
|
||||
+ ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
|
||||
+ ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
|
||||
+ ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
|
||||
+ ctrl->tCWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
|
||||
+ ctrl->tCMD = DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK);
|
||||
+
|
||||
+ /* Constrain primary timings to hardware limits */
|
||||
+ /** TODO: complain when clamping? **/
|
||||
+ ctrl->tAA = clamp_u32(4, ctrl->tAA, 24);
|
||||
+ ctrl->tWR = clamp_u32(5, ctrl->tWR, 16);
|
||||
+ ctrl->tRCD = clamp_u32(4, ctrl->tRCD, 20);
|
||||
+ ctrl->tRRD = clamp_u32(4, ctrl->tRRD, 65535);
|
||||
+ ctrl->tRP = clamp_u32(4, ctrl->tRP, 15);
|
||||
+ ctrl->tRAS = clamp_u32(10, ctrl->tRAS, 40);
|
||||
+ ctrl->tRC = clamp_u32(1, ctrl->tRC, 4095);
|
||||
+ ctrl->tRFC = clamp_u32(1, ctrl->tRFC, 511);
|
||||
+ ctrl->tWTR = clamp_u32(4, ctrl->tWTR, 10);
|
||||
+ ctrl->tRTP = clamp_u32(4, ctrl->tRTP, 15);
|
||||
+ ctrl->tFAW = clamp_u32(10, ctrl->tFAW, 54);
|
||||
+
|
||||
+ /** TODO: Honor tREFI from XMP **/
|
||||
+ ctrl->tREFI = get_tREFI(ctrl->mem_clock_mhz);
|
||||
+ ctrl->tXP = get_tXP(ctrl->mem_clock_mhz);
|
||||
+
|
||||
+ /*
|
||||
+ * Check some values, and adjust them if necessary.
|
||||
+ */
|
||||
+
|
||||
+ /* If tWR cannot be written into DDR3 MR0, adjust it */
|
||||
+ switch (ctrl->tWR) {
|
||||
+ case 9:
|
||||
+ case 11:
|
||||
+ case 13:
|
||||
+ case 15:
|
||||
+ ctrl->tWR++;
|
||||
+ }
|
||||
+
|
||||
+ /* If tCWL is not supported or unspecified, look up a reasonable default */
|
||||
+ if (ctrl->tCWL < MIN_CWL || ctrl->tCWL > MAX_CWL)
|
||||
+ ctrl->tCWL = get_tCWL(ctrl->mem_clock_mhz);
|
||||
+
|
||||
+ /* This is needed to support ODT properly on 2DPC */
|
||||
+ if (ctrl->tAA - ctrl->tCWL > 4)
|
||||
+ ctrl->tCWL = ctrl->tAA - 4;
|
||||
+
|
||||
+ /* If tCMD is invalid, use a guesstimate default */
|
||||
+ if (!ctrl->tCMD) {
|
||||
+ ctrl->tCMD = MAX(ctrl->dpc[0], ctrl->dpc[1]);
|
||||
+ printk(RAM_DEBUG, "tCMD was zero, picking a guesstimate value\n");
|
||||
+ }
|
||||
+ ctrl->tCMD = clamp_u32(1, ctrl->tCMD, 3);
|
||||
+
|
||||
+ /*
|
||||
+ * Print final timings.
|
||||
+ */
|
||||
+
|
||||
+ /* tCK is special */
|
||||
+ printk(BIOS_DEBUG, "Selected tCK : %u ns\n", ctrl->tCK / 256);
|
||||
+
|
||||
+ /* Primary timings */
|
||||
+ printk(BIOS_DEBUG, "Selected tAA : %uT\n", ctrl->tAA);
|
||||
+ printk(BIOS_DEBUG, "Selected tWR : %uT\n", ctrl->tWR);
|
||||
+ printk(BIOS_DEBUG, "Selected tRCD : %uT\n", ctrl->tRCD);
|
||||
+ printk(BIOS_DEBUG, "Selected tRRD : %uT\n", ctrl->tRRD);
|
||||
+ printk(BIOS_DEBUG, "Selected tRP : %uT\n", ctrl->tRP);
|
||||
+ printk(BIOS_DEBUG, "Selected tRAS : %uT\n", ctrl->tRAS);
|
||||
+ printk(BIOS_DEBUG, "Selected tRC : %uT\n", ctrl->tRC);
|
||||
+ printk(BIOS_DEBUG, "Selected tRFC : %uT\n", ctrl->tRFC);
|
||||
+ printk(BIOS_DEBUG, "Selected tWTR : %uT\n", ctrl->tWTR);
|
||||
+ printk(BIOS_DEBUG, "Selected tRTP : %uT\n", ctrl->tRTP);
|
||||
+ printk(BIOS_DEBUG, "Selected tFAW : %uT\n", ctrl->tFAW);
|
||||
+ printk(BIOS_DEBUG, "Selected tCWL : %uT\n", ctrl->tCWL);
|
||||
+ printk(BIOS_DEBUG, "Selected tCMD : %uT\n", ctrl->tCMD);
|
||||
+
|
||||
+ /* Derived timings */
|
||||
+ printk(BIOS_DEBUG, "Selected tREFI : %uT\n", ctrl->tREFI);
|
||||
+ printk(BIOS_DEBUG, "Selected tXP : %uT\n", ctrl->tXP);
|
||||
+
|
||||
+ return RAMINIT_STATUS_SUCCESS;
|
||||
+}
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+1593
File diff suppressed because it is too large
Load Diff
+541
@@ -0,0 +1,541 @@
|
||||
From 136a9f660bda9cb515cbbe1e859bc68e7aa04d92 Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sat, 7 May 2022 20:59:58 +0200
|
||||
Subject: [PATCH 04/15] haswell NRI: Add timings/refresh programming
|
||||
|
||||
Program the registers with timing and refresh parameters.
|
||||
|
||||
Change-Id: Id2ea339d2c9ea8b56c71d6e88ec76949653ff5c2
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../haswell/native_raminit/lookup_timings.c | 102 ++++++++
|
||||
.../haswell/native_raminit/raminit_native.h | 14 ++
|
||||
.../haswell/native_raminit/reg_structs.h | 93 +++++++
|
||||
.../haswell/native_raminit/timings_refresh.c | 233 +++++++++++++++++-
|
||||
.../intel/haswell/registers/mchbar.h | 12 +
|
||||
5 files changed, 452 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
|
||||
index 038686c844..afe2c615d2 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
|
||||
@@ -60,3 +60,105 @@ uint32_t get_tXP(const uint32_t mem_clock_mhz)
|
||||
};
|
||||
return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
|
||||
}
|
||||
+
|
||||
+static uint32_t get_lpddr_tCKE(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ const struct timing_lookup lut[] = {
|
||||
+ { 533, 4 },
|
||||
+ { 666, 5 },
|
||||
+ { fmax, 6 },
|
||||
+ };
|
||||
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
|
||||
+}
|
||||
+
|
||||
+static uint32_t get_ddr_tCKE(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ const struct timing_lookup lut[] = {
|
||||
+ { 533, 3 },
|
||||
+ { 800, 4 },
|
||||
+ { 933, 5 },
|
||||
+ { 1200, 6 },
|
||||
+ { fmax, 7 },
|
||||
+ };
|
||||
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
|
||||
+}
|
||||
+
|
||||
+uint32_t get_tCKE(const uint32_t mem_clock_mhz, const bool lpddr)
|
||||
+{
|
||||
+ return lpddr ? get_lpddr_tCKE(mem_clock_mhz) : get_ddr_tCKE(mem_clock_mhz);
|
||||
+}
|
||||
+
|
||||
+uint32_t get_tXPDLL(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ const struct timing_lookup lut[] = {
|
||||
+ { 400, 10 },
|
||||
+ { 533, 13 },
|
||||
+ { 666, 16 },
|
||||
+ { 800, 20 },
|
||||
+ { 933, 23 },
|
||||
+ { 1066, 26 },
|
||||
+ { 1200, 29 },
|
||||
+ { fmax, 32 },
|
||||
+ };
|
||||
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
|
||||
+}
|
||||
+
|
||||
+uint32_t get_tAONPD(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ const struct timing_lookup lut[] = {
|
||||
+ { 400, 4 },
|
||||
+ { 533, 5 },
|
||||
+ { 666, 6 },
|
||||
+ { 800, 7 }, /* SNB had 8 */
|
||||
+ { 933, 8 },
|
||||
+ { 1066, 10 },
|
||||
+ { 1200, 11 },
|
||||
+ { fmax, 12 },
|
||||
+ };
|
||||
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
|
||||
+}
|
||||
+
|
||||
+uint32_t get_tMOD(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ const struct timing_lookup lut[] = {
|
||||
+ { 800, 12 },
|
||||
+ { 933, 14 },
|
||||
+ { 1066, 16 },
|
||||
+ { 1200, 18 },
|
||||
+ { fmax, 20 },
|
||||
+ };
|
||||
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
|
||||
+}
|
||||
+
|
||||
+uint32_t get_tXS_offset(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ return DIV_ROUND_UP(mem_clock_mhz, 100);
|
||||
+}
|
||||
+
|
||||
+static uint32_t get_lpddr_tZQOPER(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ return (mem_clock_mhz * 360) / 1000;
|
||||
+}
|
||||
+
|
||||
+static uint32_t get_ddr_tZQOPER(const uint32_t mem_clock_mhz)
|
||||
+{
|
||||
+ const struct timing_lookup lut[] = {
|
||||
+ { 800, 256 },
|
||||
+ { 933, 299 },
|
||||
+ { 1066, 342 },
|
||||
+ { 1200, 384 },
|
||||
+ { fmax, 427 },
|
||||
+ };
|
||||
+ return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
|
||||
+}
|
||||
+
|
||||
+/* tZQOPER defines the period required for ZQCL after SR exit */
|
||||
+uint32_t get_tZQOPER(const uint32_t mem_clock_mhz, const bool lpddr)
|
||||
+{
|
||||
+ return lpddr ? get_lpddr_tZQOPER(mem_clock_mhz) : get_ddr_tZQOPER(mem_clock_mhz);
|
||||
+}
|
||||
+
|
||||
+uint32_t get_tZQCS(const uint32_t mem_clock_mhz, const bool lpddr)
|
||||
+{
|
||||
+ return DIV_ROUND_UP(get_tZQOPER(mem_clock_mhz, lpddr), 4);
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index aa86b9aa39..cd1f2eb2a5 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -155,6 +155,12 @@ struct sysinfo {
|
||||
uint8_t cke_cmd_pi_code[NUM_CHANNELS][NUM_GROUPS];
|
||||
uint8_t cmd_north_pi_code[NUM_CHANNELS][NUM_GROUPS];
|
||||
uint8_t cmd_south_pi_code[NUM_CHANNELS][NUM_GROUPS];
|
||||
+
|
||||
+ union tc_bank_reg tc_bank[NUM_CHANNELS];
|
||||
+ union tc_bank_rank_a_reg tc_bankrank_a[NUM_CHANNELS];
|
||||
+ union tc_bank_rank_b_reg tc_bankrank_b[NUM_CHANNELS];
|
||||
+ union tc_bank_rank_c_reg tc_bankrank_c[NUM_CHANNELS];
|
||||
+ union tc_bank_rank_d_reg tc_bankrank_d[NUM_CHANNELS];
|
||||
};
|
||||
|
||||
static inline bool is_hsw_ult(void)
|
||||
@@ -200,6 +206,14 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
|
||||
void configure_timings(struct sysinfo *ctrl);
|
||||
void configure_refresh(struct sysinfo *ctrl);
|
||||
|
||||
+uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
|
||||
+uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
|
||||
+uint32_t get_tAONPD(uint32_t mem_clock_mhz);
|
||||
+uint32_t get_tMOD(uint32_t mem_clock_mhz);
|
||||
+uint32_t get_tXS_offset(uint32_t mem_clock_mhz);
|
||||
+uint32_t get_tZQOPER(uint32_t mem_clock_mhz, bool lpddr);
|
||||
+uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr);
|
||||
+
|
||||
enum raminit_status wait_for_first_rcomp(void);
|
||||
|
||||
uint8_t get_rx_bias(const struct sysinfo *ctrl);
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
index d11cda4b3d..70487e1640 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
@@ -335,6 +335,99 @@ union mcscheds_cbit_reg {
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
+union tc_bank_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t tRCD : 5; // Bits 4:0
|
||||
+ uint32_t tRP : 5; // Bits 9:5
|
||||
+ uint32_t tRAS : 6; // Bits 15:10
|
||||
+ uint32_t tRDPRE : 4; // Bits 19:16
|
||||
+ uint32_t tWRPRE : 6; // Bits 25:20
|
||||
+ uint32_t tRRD : 4; // Bits 29:26
|
||||
+ uint32_t tRPab_ext : 2; // Bits 31:30
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
+union tc_bank_rank_a_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t tCKE : 4; // Bits 3:0
|
||||
+ uint32_t tFAW : 8; // Bits 11:4
|
||||
+ uint32_t tRDRD_sr : 3; // Bits 14:12
|
||||
+ uint32_t tRDRD_dr : 4; // Bits 18:15
|
||||
+ uint32_t tRDRD_dd : 4; // Bits 22:19
|
||||
+ uint32_t tRDPDEN : 5; // Bits 27:23
|
||||
+ uint32_t : 1; // Bits 28:28
|
||||
+ uint32_t cmd_3st_dis : 1; // Bits 29:29
|
||||
+ uint32_t cmd_stretch : 2; // Bits 31:30
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
+union tc_bank_rank_b_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t tWRRD_sr : 6; // Bits 5:0
|
||||
+ uint32_t tWRRD_dr : 4; // Bits 9:6
|
||||
+ uint32_t tWRRD_dd : 4; // Bits 13:10
|
||||
+ uint32_t tWRWR_sr : 3; // Bits 16:14
|
||||
+ uint32_t tWRWR_dr : 4; // Bits 20:17
|
||||
+ uint32_t tWRWR_dd : 4; // Bits 24:21
|
||||
+ uint32_t tWRPDEN : 6; // Bits 30:25
|
||||
+ uint32_t dec_wrd : 1; // Bits 31:31
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
+union tc_bank_rank_c_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t tXPDLL : 6; // Bits 5:0
|
||||
+ uint32_t tXP : 4; // Bits 9:6
|
||||
+ uint32_t tAONPD : 4; // Bits 13:10
|
||||
+ uint32_t tRDWR_sr : 5; // Bits 18:14
|
||||
+ uint32_t tRDWR_dr : 5; // Bits 23:19
|
||||
+ uint32_t tRDWR_dd : 5; // Bits 28:24
|
||||
+ uint32_t : 3; // Bits 31:29
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
+/* NOTE: Non-ULT only implements the lower 21 bits (odt_write_delay is 2 bits) */
|
||||
+union tc_bank_rank_d_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t tAA : 5; // Bits 4:0
|
||||
+ uint32_t tCWL : 5; // Bits 9:5
|
||||
+ uint32_t tCPDED : 2; // Bits 11:10
|
||||
+ uint32_t tPRPDEN : 2; // Bits 13:12
|
||||
+ uint32_t odt_read_delay : 3; // Bits 16:14
|
||||
+ uint32_t odt_read_duration : 2; // Bits 18:17
|
||||
+ uint32_t odt_write_duration : 3; // Bits 21:19
|
||||
+ uint32_t odt_write_delay : 3; // Bits 24:22
|
||||
+ uint32_t odt_always_rank_0 : 1; // Bits 25:25
|
||||
+ uint32_t cmd_delay : 2; // Bits 27:26
|
||||
+ uint32_t : 4; // Bits 31:28
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
+union tc_rftp_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t tREFI : 16; // Bits 15:0
|
||||
+ uint32_t tRFC : 9; // Bits 24:16
|
||||
+ uint32_t tREFIx9 : 7; // Bits 31:25
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
+union tc_srftp_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t tXSDLL : 12; // Bits 11:0
|
||||
+ uint32_t tXS_offset : 4; // Bits 15:12
|
||||
+ uint32_t tZQOPER : 10; // Bits 25:16
|
||||
+ uint32_t : 2; // Bits 27:26
|
||||
+ uint32_t tMOD : 4; // Bits 31:28
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
union mcmain_command_rate_limit_reg {
|
||||
struct __packed {
|
||||
uint32_t enable_cmd_limit : 1; // Bits 0:0
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
|
||||
index a9d960f31b..20a05b359b 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
|
||||
@@ -1,13 +1,242 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
+#include <assert.h>
|
||||
+#include <commonlib/clamp.h>
|
||||
+#include <console/console.h>
|
||||
+#include <delay.h>
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+
|
||||
#include "raminit_native.h"
|
||||
|
||||
+#define BL 8 /* Burst length */
|
||||
+#define tCCD 4
|
||||
+#define tRPRE 1
|
||||
+#define tWPRE 1
|
||||
+#define tDLLK 512
|
||||
+
|
||||
+static bool is_sodimm(const enum spd_dimm_type_ddr3 type)
|
||||
+{
|
||||
+ return type == SPD_DDR3_DIMM_TYPE_SO_DIMM || type == SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM;
|
||||
+}
|
||||
+
|
||||
+static uint8_t get_odt_stretch(const struct sysinfo *const ctrl)
|
||||
+{
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ /* Only stretch with 2 DIMMs per channel */
|
||||
+ if (ctrl->dpc[channel] != 2)
|
||||
+ continue;
|
||||
+
|
||||
+ const struct raminit_dimm_info *dimms = ctrl->dimms[channel];
|
||||
+
|
||||
+ /* Only stretch when using SO-DIMMs */
|
||||
+ if (!is_sodimm(dimms[0].data.dimm_type) || !is_sodimm(dimms[1].data.dimm_type))
|
||||
+ continue;
|
||||
+
|
||||
+ /* Only stretch with mismatched card types */
|
||||
+ if (dimms[0].data.reference_card == dimms[1].data.reference_card)
|
||||
+ continue;
|
||||
+
|
||||
+ /* Stretch if one SO-DIMM is card F */
|
||||
+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
|
||||
+ if (dimms[slot].data.reference_card == 5)
|
||||
+ return 1;
|
||||
+ }
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+static union tc_bank_reg make_tc_bank(struct sysinfo *const ctrl)
|
||||
+{
|
||||
+ return (union tc_bank_reg) {
|
||||
+ .tRCD = ctrl->tRCD,
|
||||
+ .tRP = ctrl->tRP,
|
||||
+ .tRAS = ctrl->tRAS,
|
||||
+ .tRDPRE = ctrl->tRTP,
|
||||
+ .tWRPRE = 4 + ctrl->tCWL + ctrl->tWR,
|
||||
+ .tRRD = ctrl->tRRD,
|
||||
+ .tRPab_ext = 0, /** TODO: For LPDDR, this is ctrl->tRPab - ctrl->tRP **/
|
||||
+ };
|
||||
+}
|
||||
+
|
||||
+static union tc_bank_rank_a_reg make_tc_bankrank_a(struct sysinfo *ctrl, uint8_t odt_stretch)
|
||||
+{
|
||||
+ /* Use 3N mode for DDR during training, but always use 1N mode for LPDDR */
|
||||
+ const uint32_t tCMD = ctrl->lpddr ? 0 : 3;
|
||||
+ const uint32_t tRDRD_drdd = BL / 2 + 1 + tRPRE + odt_stretch + !!ctrl->lpddr;
|
||||
+
|
||||
+ return (union tc_bank_rank_a_reg) {
|
||||
+ .tCKE = get_tCKE(ctrl->mem_clock_mhz, ctrl->lpddr),
|
||||
+ .tFAW = ctrl->tFAW,
|
||||
+ .tRDRD_sr = tCCD,
|
||||
+ .tRDRD_dr = tRDRD_drdd,
|
||||
+ .tRDRD_dd = tRDRD_drdd,
|
||||
+ .tRDPDEN = ctrl->tAA + BL / 2 + 1,
|
||||
+ .cmd_3st_dis = 1, /* Disable command tri-state before training */
|
||||
+ .cmd_stretch = tCMD,
|
||||
+ };
|
||||
+}
|
||||
+
|
||||
+static union tc_bank_rank_b_reg make_tc_bankrank_b(struct sysinfo *const ctrl)
|
||||
+{
|
||||
+ const uint8_t tWRRD_drdd = ctrl->tCWL - ctrl->tAA + BL / 2 + 2 + tRPRE;
|
||||
+ const uint8_t tWRWR_drdd = BL / 2 + 2 + tWPRE;
|
||||
+
|
||||
+ return (union tc_bank_rank_b_reg) {
|
||||
+ .tWRRD_sr = tCCD + ctrl->tCWL + ctrl->tWTR + 2,
|
||||
+ .tWRRD_dr = ctrl->lpddr ? 8 : tWRRD_drdd,
|
||||
+ .tWRRD_dd = ctrl->lpddr ? 8 : tWRRD_drdd,
|
||||
+ .tWRWR_sr = tCCD,
|
||||
+ .tWRWR_dr = tWRWR_drdd,
|
||||
+ .tWRWR_dd = tWRWR_drdd,
|
||||
+ .tWRPDEN = ctrl->tWR + ctrl->tCWL + BL / 2,
|
||||
+ .dec_wrd = ctrl->tCWL >= 6,
|
||||
+ };
|
||||
+}
|
||||
+
|
||||
+static uint32_t get_tRDWR_sr(const struct sysinfo *ctrl)
|
||||
+{
|
||||
+ if (ctrl->lpddr) {
|
||||
+ const uint32_t tdqsck_max = DIV_ROUND_UP(5500, ctrl->qclkps * 2);
|
||||
+ return ctrl->tAA - ctrl->tCWL + tCCD + tWPRE + tdqsck_max + 1;
|
||||
+ } else {
|
||||
+ const bool fast_clock = ctrl->mem_clock_mhz > 666;
|
||||
+ return ctrl->tAA - ctrl->tCWL + tCCD + tWPRE + 2 + fast_clock;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static union tc_bank_rank_c_reg make_tc_bankrank_c(struct sysinfo *ctrl, uint8_t odt_stretch)
|
||||
+{
|
||||
+ const uint32_t tRDWR_sr = get_tRDWR_sr(ctrl);
|
||||
+ const uint32_t tRDWR_drdd = tRDWR_sr + odt_stretch;
|
||||
+
|
||||
+ return (union tc_bank_rank_c_reg) {
|
||||
+ .tXPDLL = get_tXPDLL(ctrl->mem_clock_mhz),
|
||||
+ .tXP = MAX(ctrl->tXP, 7), /* Use a higher tXP for training */
|
||||
+ .tAONPD = get_tAONPD(ctrl->mem_clock_mhz),
|
||||
+ .tRDWR_sr = tRDWR_sr,
|
||||
+ .tRDWR_dr = tRDWR_drdd,
|
||||
+ .tRDWR_dd = tRDWR_drdd,
|
||||
+ };
|
||||
+}
|
||||
+
|
||||
+static union tc_bank_rank_d_reg make_tc_bankrank_d(struct sysinfo *ctrl, uint8_t odt_stretch)
|
||||
+{
|
||||
+ const uint32_t odt_rd_delay = ctrl->tAA - ctrl->tCWL;
|
||||
+ if (!ctrl->lpddr) {
|
||||
+ return (union tc_bank_rank_d_reg) {
|
||||
+ .tAA = ctrl->tAA,
|
||||
+ .tCWL = ctrl->tCWL,
|
||||
+ .tCPDED = 1,
|
||||
+ .tPRPDEN = 1,
|
||||
+ .odt_read_delay = odt_rd_delay,
|
||||
+ .odt_read_duration = odt_stretch,
|
||||
+ };
|
||||
+ }
|
||||
+
|
||||
+ /* tCWL has 1 extra clock because of tDQSS, subtract it here */
|
||||
+ const uint32_t tCWL_lpddr = ctrl->tCWL - 1;
|
||||
+ const uint32_t odt_wr_delay = tCWL_lpddr + DIV_ROUND_UP(3500, ctrl->qclkps * 2);
|
||||
+ const uint32_t odt_wr_duration = DIV_ROUND_UP(3500 - 1750, ctrl->qclkps * 2) + 1;
|
||||
+
|
||||
+ return (union tc_bank_rank_d_reg) {
|
||||
+ .tAA = ctrl->tAA,
|
||||
+ .tCWL = tCWL_lpddr,
|
||||
+ .tCPDED = 2, /* Required by JEDEC LPDDR3 spec */
|
||||
+ .tPRPDEN = 1,
|
||||
+ .odt_read_delay = odt_rd_delay,
|
||||
+ .odt_read_duration = odt_stretch,
|
||||
+ .odt_write_delay = odt_wr_delay,
|
||||
+ .odt_write_duration = odt_wr_duration,
|
||||
+ .odt_always_rank_0 = ctrl->lpddr_dram_odt
|
||||
+ };
|
||||
+}
|
||||
+
|
||||
+/* ZQCS period values, in (tREFI * 128) units */
|
||||
+#define ZQCS_PERIOD_DDR3 128 /* tREFI * 128 = 7.8 us * 128 = 1ms */
|
||||
+#define ZQCS_PERIOD_LPDDR3 256 /* tREFI * 128 = 3.9 us * 128 = 0.5ms */
|
||||
+
|
||||
+static uint32_t make_tc_zqcal(const struct sysinfo *const ctrl)
|
||||
+{
|
||||
+ const uint32_t zqcs_period = ctrl->lpddr ? ZQCS_PERIOD_LPDDR3 : ZQCS_PERIOD_DDR3;
|
||||
+ const uint32_t tZQCS = get_tZQCS(ctrl->mem_clock_mhz, ctrl->lpddr);
|
||||
+ return tZQCS << (is_hsw_ult() ? 10 : 8) | zqcs_period;
|
||||
+}
|
||||
+
|
||||
+static union tc_rftp_reg make_tc_rftp(const struct sysinfo *const ctrl)
|
||||
+{
|
||||
+ /*
|
||||
+ * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow
|
||||
+ * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024.
|
||||
+ */
|
||||
+ return (union tc_rftp_reg) {
|
||||
+ .tREFI = ctrl->tREFI,
|
||||
+ .tRFC = ctrl->tRFC,
|
||||
+ .tREFIx9 = ctrl->tREFI * 89 / 10240,
|
||||
+ };
|
||||
+}
|
||||
+
|
||||
+static union tc_srftp_reg make_tc_srftp(const struct sysinfo *const ctrl)
|
||||
+{
|
||||
+ return (union tc_srftp_reg) {
|
||||
+ .tXSDLL = tDLLK,
|
||||
+ .tXS_offset = get_tXS_offset(ctrl->mem_clock_mhz),
|
||||
+ .tZQOPER = get_tZQOPER(ctrl->mem_clock_mhz, ctrl->lpddr),
|
||||
+ .tMOD = get_tMOD(ctrl->mem_clock_mhz) - 8,
|
||||
+ };
|
||||
+}
|
||||
+
|
||||
void configure_timings(struct sysinfo *ctrl)
|
||||
{
|
||||
- /** TODO: Stub **/
|
||||
+ if (ctrl->lpddr)
|
||||
+ die("%s: Missing support for LPDDR\n");
|
||||
+
|
||||
+ const uint8_t odt_stretch = get_odt_stretch(ctrl);
|
||||
+ const union tc_bank_reg tc_bank = make_tc_bank(ctrl);
|
||||
+ const union tc_bank_rank_a_reg tc_bank_rank_a = make_tc_bankrank_a(ctrl, odt_stretch);
|
||||
+ const union tc_bank_rank_b_reg tc_bank_rank_b = make_tc_bankrank_b(ctrl);
|
||||
+ const union tc_bank_rank_c_reg tc_bank_rank_c = make_tc_bankrank_c(ctrl, odt_stretch);
|
||||
+ const union tc_bank_rank_d_reg tc_bank_rank_d = make_tc_bankrank_d(ctrl, odt_stretch);
|
||||
+
|
||||
+ const uint8_t wr_delay = tc_bank_rank_b.dec_wrd + 1;
|
||||
+ uint8_t sc_wr_add_delay = 0;
|
||||
+ sc_wr_add_delay |= wr_delay << 0;
|
||||
+ sc_wr_add_delay |= wr_delay << 2;
|
||||
+ sc_wr_add_delay |= wr_delay << 4;
|
||||
+ sc_wr_add_delay |= wr_delay << 6;
|
||||
+
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ ctrl->tc_bank[channel] = tc_bank;
|
||||
+ ctrl->tc_bankrank_a[channel] = tc_bank_rank_a;
|
||||
+ ctrl->tc_bankrank_b[channel] = tc_bank_rank_b;
|
||||
+ ctrl->tc_bankrank_c[channel] = tc_bank_rank_c;
|
||||
+ ctrl->tc_bankrank_d[channel] = tc_bank_rank_d;
|
||||
+
|
||||
+ mchbar_write32(TC_BANK_ch(channel), ctrl->tc_bank[channel].raw);
|
||||
+ mchbar_write32(TC_BANK_RANK_A_ch(channel), ctrl->tc_bankrank_a[channel].raw);
|
||||
+ mchbar_write32(TC_BANK_RANK_B_ch(channel), ctrl->tc_bankrank_b[channel].raw);
|
||||
+ mchbar_write32(TC_BANK_RANK_C_ch(channel), ctrl->tc_bankrank_c[channel].raw);
|
||||
+ mchbar_write32(TC_BANK_RANK_D_ch(channel), ctrl->tc_bankrank_d[channel].raw);
|
||||
+ mchbar_write8(SC_WR_ADD_DELAY_ch(channel), sc_wr_add_delay);
|
||||
+ }
|
||||
}
|
||||
|
||||
void configure_refresh(struct sysinfo *ctrl)
|
||||
{
|
||||
- /** TODO: Stub **/
|
||||
+ const union tc_srftp_reg tc_srftp = make_tc_srftp(ctrl);
|
||||
+ const union tc_rftp_reg tc_rftp = make_tc_rftp(ctrl);
|
||||
+ const uint32_t tc_zqcal = make_tc_zqcal(ctrl);
|
||||
+
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ mchbar_setbits32(TC_RFP_ch(channel), 0xff);
|
||||
+ mchbar_write32(TC_RFTP_ch(channel), tc_rftp.raw);
|
||||
+ mchbar_write32(TC_SRFTP_ch(channel), tc_srftp.raw);
|
||||
+ mchbar_write32(TC_ZQCAL_ch(channel), tc_zqcal);
|
||||
+ }
|
||||
}
|
||||
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
index 4c3f399b5d..2acc5cbbc8 100644
|
||||
--- a/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
@@ -86,9 +86,21 @@
|
||||
#define DDR_COMP_VSSHI_CONTROL 0x3a24
|
||||
|
||||
/* MCMAIN per-channel */
|
||||
+#define TC_BANK_ch(ch) _MCMAIN_C(0x4000, ch)
|
||||
+#define TC_BANK_RANK_A_ch(ch) _MCMAIN_C(0x4004, ch)
|
||||
+#define TC_BANK_RANK_B_ch(ch) _MCMAIN_C(0x4008, ch)
|
||||
+#define TC_BANK_RANK_C_ch(ch) _MCMAIN_C(0x400c, ch)
|
||||
#define COMMAND_RATE_LIMIT_ch(ch) _MCMAIN_C(0x4010, ch)
|
||||
+#define TC_BANK_RANK_D_ch(ch) _MCMAIN_C(0x4014, ch)
|
||||
+#define SC_ROUNDT_LAT_ch(ch) _MCMAIN_C(0x4024, ch)
|
||||
|
||||
+#define SC_WR_ADD_DELAY_ch(ch) _MCMAIN_C(0x40d0, ch)
|
||||
+
|
||||
+#define TC_ZQCAL_ch(ch) _MCMAIN_C(0x4290, ch)
|
||||
+#define TC_RFP_ch(ch) _MCMAIN_C(0x4294, ch)
|
||||
+#define TC_RFTP_ch(ch) _MCMAIN_C(0x4298, ch)
|
||||
#define MC_INIT_STATE_ch(ch) _MCMAIN_C(0x42a0, ch)
|
||||
+#define TC_SRFTP_ch(ch) _MCMAIN_C(0x42a4, ch)
|
||||
|
||||
/* MCMAIN broadcast */
|
||||
#define MCSCHEDS_CBIT 0x4c20
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,263 @@
|
||||
From f2f47233a17045d1fb2338ca62ce0b107fbdf765 Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sat, 7 May 2022 21:24:50 +0200
|
||||
Subject: [PATCH 05/15] haswell NRI: Program memory map
|
||||
|
||||
This is very similar to Sandy/Ivy Bridge, except that there's several
|
||||
registers to program in GDXCBAR. One of these GDXCBAR registers has a
|
||||
lock bit that must be set in order for the memory controller to allow
|
||||
normal access to DRAM. And it took me four months to realize this one
|
||||
bit was the only reason why native raminit did not work.
|
||||
|
||||
Change-Id: I3af73a018a7ba948701a542e661e7fefd57591fe
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../intel/haswell/native_raminit/Makefile.mk | 1 +
|
||||
.../intel/haswell/native_raminit/memory_map.c | 183 ++++++++++++++++++
|
||||
.../haswell/native_raminit/raminit_main.c | 1 +
|
||||
.../haswell/native_raminit/raminit_native.h | 1 +
|
||||
.../intel/haswell/registers/host_bridge.h | 2 +
|
||||
5 files changed, 188 insertions(+)
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/memory_map.c
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
index fc55277a65..37d527e972 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
@@ -4,6 +4,7 @@ romstage-y += configure_mc.c
|
||||
romstage-y += lookup_timings.c
|
||||
romstage-y += init_mpll.c
|
||||
romstage-y += io_comp_control.c
|
||||
+romstage-y += memory_map.c
|
||||
romstage-y += raminit_main.c
|
||||
romstage-y += raminit_native.c
|
||||
romstage-y += spd_bitmunching.c
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/memory_map.c b/src/northbridge/intel/haswell/native_raminit/memory_map.c
|
||||
new file mode 100644
|
||||
index 0000000000..e3aded2b37
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/memory_map.c
|
||||
@@ -0,0 +1,183 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+#include <southbridge/intel/lynxpoint/me.h>
|
||||
+#include <types.h>
|
||||
+
|
||||
+#include "raminit_native.h"
|
||||
+
|
||||
+/* GDXCBAR */
|
||||
+#define MPCOHTRK_GDXC_MOT_ADDRESS_LO 0x10
|
||||
+#define MPCOHTRK_GDXC_MOT_ADDRESS_HI 0x14
|
||||
+#define MPCOHTRK_GDXC_MOT_REGION 0x18
|
||||
+
|
||||
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_LO 0x20
|
||||
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_HI 0x24
|
||||
+#define MPCOHTRK_GDXC_OCLA_REGION 0x28
|
||||
+
|
||||
+/* This lock bit made me lose what little sanity I had left. - Angel Pons */
|
||||
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK BIT(2)
|
||||
+
|
||||
+static inline uint32_t gdxcbar_read32(const uintptr_t offset)
|
||||
+{
|
||||
+ return read32p((mchbar_read32(GDXCBAR) & ~1) + offset);
|
||||
+}
|
||||
+
|
||||
+static inline void gdxcbar_write32(const uintptr_t offset, const uint32_t value)
|
||||
+{
|
||||
+ write32p((mchbar_read32(GDXCBAR) & ~1) + offset, value);
|
||||
+}
|
||||
+
|
||||
+static inline void gdxcbar_clrsetbits32(const uintptr_t offset, uint32_t clear, uint32_t set)
|
||||
+{
|
||||
+ const uintptr_t address = (mchbar_read32(GDXCBAR) & ~1) + offset;
|
||||
+ clrsetbits32((void *)address, clear, set);
|
||||
+}
|
||||
+
|
||||
+#define gdxcbar_setbits32(offset, set) gdxcbar_clrsetbits32(offset, 0, set)
|
||||
+#define gdxcbar_clrbits32(offset, clear) gdxcbar_clrsetbits32(offset, clear, 0)
|
||||
+
|
||||
+/* All values stored in here (except the bool) are specified in MiB */
|
||||
+struct memory_map_data {
|
||||
+ uint32_t dpr_size;
|
||||
+ uint32_t tseg_size;
|
||||
+ uint32_t gtt_size;
|
||||
+ uint32_t gms_size;
|
||||
+ uint32_t me_stolen_size;
|
||||
+ uint32_t mmio_size;
|
||||
+ uint32_t touud;
|
||||
+ uint32_t remaplimit;
|
||||
+ uint32_t remapbase;
|
||||
+ uint32_t tom;
|
||||
+ uint32_t tom_minus_me;
|
||||
+ uint32_t tolud;
|
||||
+ uint32_t bdsm_base;
|
||||
+ uint32_t gtt_base;
|
||||
+ uint32_t tseg_base;
|
||||
+ bool reclaim_possible;
|
||||
+};
|
||||
+
|
||||
+static void compute_memory_map(struct memory_map_data *map)
|
||||
+{
|
||||
+ map->tom_minus_me = map->tom - map->me_stolen_size;
|
||||
+
|
||||
+ /*
|
||||
+ * MMIO size will actually be slightly smaller than computed,
|
||||
+ * but matches what MRC does and is more MTRR-friendly given
|
||||
+ * that TSEG is treated as WB, but SMRR makes TSEG UC anyway.
|
||||
+ */
|
||||
+ const uint32_t mmio_size = MIN(map->tom_minus_me, 4096) / 2;
|
||||
+ map->gtt_base = ALIGN_DOWN(mmio_size, map->tseg_size);
|
||||
+ map->tseg_base = map->gtt_base - map->tseg_size;
|
||||
+ map->bdsm_base = map->gtt_base + map->gtt_size;
|
||||
+ map->tolud = map->bdsm_base + map->gms_size;
|
||||
+ map->reclaim_possible = map->tom_minus_me > map->tolud;
|
||||
+
|
||||
+ if (map->reclaim_possible) {
|
||||
+ map->remapbase = MAX(4096, map->tom_minus_me);
|
||||
+ map->touud = MIN(4096, map->tom_minus_me) + map->remapbase - map->tolud;
|
||||
+ map->remaplimit = map->touud - 1;
|
||||
+ } else {
|
||||
+ map->remapbase = 0;
|
||||
+ map->remaplimit = 0;
|
||||
+ map->touud = map->tom_minus_me;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void display_memory_map(const struct memory_map_data *map)
|
||||
+{
|
||||
+ if (!CONFIG(DEBUG_RAM_SETUP))
|
||||
+ return;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "============ MEMORY MAP ============\n");
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ printk(BIOS_DEBUG, "dpr_size = %u MiB\n", map->dpr_size);
|
||||
+ printk(BIOS_DEBUG, "tseg_size = %u MiB\n", map->tseg_size);
|
||||
+ printk(BIOS_DEBUG, "gtt_size = %u MiB\n", map->gtt_size);
|
||||
+ printk(BIOS_DEBUG, "gms_size = %u MiB\n", map->gms_size);
|
||||
+ printk(BIOS_DEBUG, "me_stolen_size = %u MiB\n", map->me_stolen_size);
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ printk(BIOS_DEBUG, "touud = %u MiB\n", map->touud);
|
||||
+ printk(BIOS_DEBUG, "remaplimit = %u MiB\n", map->remaplimit);
|
||||
+ printk(BIOS_DEBUG, "remapbase = %u MiB\n", map->remapbase);
|
||||
+ printk(BIOS_DEBUG, "tom = %u MiB\n", map->tom);
|
||||
+ printk(BIOS_DEBUG, "tom_minus_me = %u MiB\n", map->tom_minus_me);
|
||||
+ printk(BIOS_DEBUG, "tolud = %u MiB\n", map->tolud);
|
||||
+ printk(BIOS_DEBUG, "bdsm_base = %u MiB\n", map->bdsm_base);
|
||||
+ printk(BIOS_DEBUG, "gtt_base = %u MiB\n", map->gtt_base);
|
||||
+ printk(BIOS_DEBUG, "tseg_base = %u MiB\n", map->tseg_base);
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ printk(BIOS_DEBUG, "reclaim_possible = %s\n", map->reclaim_possible ? "Yes" : "No");
|
||||
+}
|
||||
+
|
||||
+static void map_write_reg64(const uint16_t reg, const uint64_t size)
|
||||
+{
|
||||
+ const uint64_t value = size << 20;
|
||||
+ pci_write_config32(HOST_BRIDGE, reg + 4, value >> 32);
|
||||
+ pci_write_config32(HOST_BRIDGE, reg + 0, value >> 0);
|
||||
+}
|
||||
+
|
||||
+static void map_write_reg32(const uint16_t reg, const uint32_t size)
|
||||
+{
|
||||
+ const uint32_t value = size << 20;
|
||||
+ pci_write_config32(HOST_BRIDGE, reg, value);
|
||||
+}
|
||||
+
|
||||
+static void program_memory_map(const struct memory_map_data *map)
|
||||
+{
|
||||
+ map_write_reg64(TOUUD, map->touud);
|
||||
+ map_write_reg64(TOM, map->tom);
|
||||
+ if (map->reclaim_possible) {
|
||||
+ map_write_reg64(REMAPBASE, map->remapbase);
|
||||
+ map_write_reg64(REMAPLIMIT, map->remaplimit);
|
||||
+ }
|
||||
+ if (map->me_stolen_size) {
|
||||
+ map_write_reg64(MESEG_LIMIT, 0x80000 - map->me_stolen_size);
|
||||
+ map_write_reg64(MESEG_BASE, map->tom_minus_me);
|
||||
+ pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, ME_STLEN_EN);
|
||||
+ }
|
||||
+ map_write_reg32(TOLUD, map->tolud);
|
||||
+ map_write_reg32(BDSM, map->bdsm_base);
|
||||
+ map_write_reg32(BGSM, map->gtt_base);
|
||||
+ map_write_reg32(TSEG, map->tseg_base);
|
||||
+
|
||||
+ const uint32_t dpr_reg = map->tseg_base << 20 | map->dpr_size << 4;
|
||||
+ pci_write_config32(HOST_BRIDGE, DPR, dpr_reg);
|
||||
+
|
||||
+ const uint16_t gfx_stolen_size = GGC_IGD_MEM_IN_32MB_UNITS(map->gms_size / 32);
|
||||
+ const uint16_t ggc = map->gtt_size << 8 | gfx_stolen_size;
|
||||
+ pci_write_config16(HOST_BRIDGE, GGC, ggc);
|
||||
+
|
||||
+ /** TODO: Do not hardcode these? GDXC has weird alignment requirements, though. **/
|
||||
+ gdxcbar_write32(MPCOHTRK_GDXC_MOT_ADDRESS_LO, 0);
|
||||
+ gdxcbar_write32(MPCOHTRK_GDXC_MOT_ADDRESS_HI, 0);
|
||||
+ gdxcbar_write32(MPCOHTRK_GDXC_MOT_REGION, 0);
|
||||
+
|
||||
+ gdxcbar_write32(MPCOHTRK_GDXC_OCLA_ADDRESS_LO, 0);
|
||||
+ gdxcbar_write32(MPCOHTRK_GDXC_OCLA_ADDRESS_HI, 0);
|
||||
+ gdxcbar_write32(MPCOHTRK_GDXC_OCLA_REGION, 0);
|
||||
+
|
||||
+ gdxcbar_setbits32(MPCOHTRK_GDXC_OCLA_ADDRESS_HI, MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK);
|
||||
+}
|
||||
+
|
||||
+enum raminit_status configure_memory_map(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ struct memory_map_data memory_map = {
|
||||
+ .tom = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1],
|
||||
+ .dpr_size = CONFIG_INTEL_TXT_DPR_SIZE,
|
||||
+ .tseg_size = CONFIG_SMM_TSEG_SIZE >> 20,
|
||||
+ .me_stolen_size = intel_early_me_uma_size(),
|
||||
+ };
|
||||
+ /** FIXME: MRC hardcodes iGPU parameters, but we should not **/
|
||||
+ const bool igpu_on = pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN;
|
||||
+ if (CONFIG(ONBOARD_VGA_IS_PRIMARY) || igpu_on) {
|
||||
+ memory_map.gtt_size = 2;
|
||||
+ memory_map.gms_size = 64;
|
||||
+ pci_or_config32(HOST_BRIDGE, DEVEN, DEVEN_D2EN);
|
||||
+ }
|
||||
+ compute_memory_map(&memory_map);
|
||||
+ display_memory_map(&memory_map);
|
||||
+ program_memory_map(&memory_map);
|
||||
+ return 0;
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
index 3a773cfa19..136a8ba989 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
@@ -24,6 +24,7 @@ static const struct task_entry cold_boot[] = {
|
||||
{ initialise_mpll, true, "INITMPLL", },
|
||||
{ convert_timings, true, "CONVTIM", },
|
||||
{ configure_mc, true, "CONFMC", },
|
||||
+ { configure_memory_map, true, "MEMMAP", },
|
||||
};
|
||||
|
||||
/* Return a generic stepping value to make stepping checks simpler */
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index cd1f2eb2a5..4763b25e8d 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -202,6 +202,7 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl);
|
||||
enum raminit_status initialise_mpll(struct sysinfo *ctrl);
|
||||
enum raminit_status convert_timings(struct sysinfo *ctrl);
|
||||
enum raminit_status configure_mc(struct sysinfo *ctrl);
|
||||
+enum raminit_status configure_memory_map(struct sysinfo *ctrl);
|
||||
|
||||
void configure_timings(struct sysinfo *ctrl);
|
||||
void configure_refresh(struct sysinfo *ctrl);
|
||||
diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h
|
||||
index 1ee0ab2890..0228cf6bb9 100644
|
||||
--- a/src/northbridge/intel/haswell/registers/host_bridge.h
|
||||
+++ b/src/northbridge/intel/haswell/registers/host_bridge.h
|
||||
@@ -34,6 +34,8 @@
|
||||
|
||||
#define MESEG_BASE 0x70 /* Management Engine Base */
|
||||
#define MESEG_LIMIT 0x78 /* Management Engine Limit */
|
||||
+#define MELCK (1 << 10) /* ME Range Lock */
|
||||
+#define ME_STLEN_EN (1 << 11) /* ME Stolen Memory Enable */
|
||||
|
||||
#define PAM0 0x80
|
||||
#define PAM1 0x81
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+1038
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,384 @@
|
||||
From 1992c1119e36e7cdbfb676dc167157b0df22f7a4 Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sat, 7 May 2022 23:12:18 +0200
|
||||
Subject: [PATCH 07/15] haswell NRI: Add pre-training steps
|
||||
|
||||
Implement pre-training steps, which consist of enabling ECC I/O and
|
||||
filling the WDB (Write Data Buffer, stores test patterns) through a
|
||||
magic LDAT port.
|
||||
|
||||
Change-Id: Ie2e09e3b218c4569ed8de5c5e1b05d491032e0f1
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../intel/haswell/native_raminit/Makefile.mk | 1 +
|
||||
.../haswell/native_raminit/raminit_main.c | 34 ++++
|
||||
.../haswell/native_raminit/raminit_native.h | 24 +++
|
||||
.../haswell/native_raminit/reg_structs.h | 45 +++++
|
||||
.../intel/haswell/native_raminit/setup_wdb.c | 159 ++++++++++++++++++
|
||||
.../intel/haswell/registers/mchbar.h | 9 +
|
||||
6 files changed, 272 insertions(+)
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/setup_wdb.c
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
index e9212df9e6..8d7d4e4db0 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
@@ -10,5 +10,6 @@ romstage-y += memory_map.c
|
||||
romstage-y += raminit_main.c
|
||||
romstage-y += raminit_native.c
|
||||
romstage-y += reut.c
|
||||
+romstage-y += setup_wdb.c
|
||||
romstage-y += spd_bitmunching.c
|
||||
romstage-y += timings_refresh.c
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
index 73ff180b8c..5e4674957d 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
@@ -13,6 +13,39 @@
|
||||
|
||||
#include "raminit_native.h"
|
||||
|
||||
+static enum raminit_status pre_training(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ /* Skip on S3 resume */
|
||||
+ if (ctrl->bootmode == BOOTMODE_S3)
|
||||
+ return RAMINIT_STATUS_SUCCESS;
|
||||
+
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
|
||||
+ if (!rank_in_ch(ctrl, slot + slot, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(RAM_DEBUG, "C%uS%u:\n", channel, slot);
|
||||
+ printk(RAM_DEBUG, "\tMR0: 0x%04x\n", ctrl->mr0[channel][slot]);
|
||||
+ printk(RAM_DEBUG, "\tMR1: 0x%04x\n", ctrl->mr1[channel][slot]);
|
||||
+ printk(RAM_DEBUG, "\tMR2: 0x%04x\n", ctrl->mr2[channel][slot]);
|
||||
+ printk(RAM_DEBUG, "\tMR3: 0x%04x\n", ctrl->mr3[channel][slot]);
|
||||
+ printk(RAM_DEBUG, "\n");
|
||||
+ }
|
||||
+ if (ctrl->is_ecc) {
|
||||
+ union mad_dimm_reg mad_dimm = {
|
||||
+ .raw = mchbar_read32(MAD_DIMM(channel)),
|
||||
+ };
|
||||
+ /* Enable ECC I/O */
|
||||
+ mad_dimm.ecc_mode = 1;
|
||||
+ mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
|
||||
+ /* Wait 4 usec after enabling the ECC I/O, needed by HW */
|
||||
+ udelay(4);
|
||||
+ }
|
||||
+ }
|
||||
+ setup_wdb(ctrl);
|
||||
+ return RAMINIT_STATUS_SUCCESS;
|
||||
+}
|
||||
+
|
||||
struct task_entry {
|
||||
enum raminit_status (*task)(struct sysinfo *);
|
||||
bool is_enabled;
|
||||
@@ -26,6 +59,7 @@ static const struct task_entry cold_boot[] = {
|
||||
{ configure_mc, true, "CONFMC", },
|
||||
{ configure_memory_map, true, "MEMMAP", },
|
||||
{ do_jedec_init, true, "JEDECINIT", },
|
||||
+ { pre_training, true, "PRETRAIN", },
|
||||
};
|
||||
|
||||
/* Return a generic stepping value to make stepping checks simpler */
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index e3cf4254a0..f29c2ec366 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -35,6 +35,13 @@
|
||||
|
||||
#define RTTNOM_MASK (BIT(9) | BIT(6) | BIT(2))
|
||||
|
||||
+#define BASIC_VA_PAT_SPREAD_8 0x01010101
|
||||
+
|
||||
+#define WDB_CACHE_LINE_SIZE 8
|
||||
+
|
||||
+#define NUM_WDB_CL_MUX_SEEDS 3
|
||||
+#define NUM_CADB_MUX_SEEDS 3
|
||||
+
|
||||
/* ZQ calibration types */
|
||||
enum {
|
||||
ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */
|
||||
@@ -318,6 +325,23 @@ void reut_issue_mrs_all(
|
||||
|
||||
enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type);
|
||||
|
||||
+void write_wdb_fixed_pat(
|
||||
+ const struct sysinfo *ctrl,
|
||||
+ const uint8_t patterns[],
|
||||
+ const uint8_t pat_mask[],
|
||||
+ uint8_t spread,
|
||||
+ uint16_t start);
|
||||
+
|
||||
+void write_wdb_va_pat(
|
||||
+ const struct sysinfo *ctrl,
|
||||
+ uint32_t agg_mask,
|
||||
+ uint32_t vic_mask,
|
||||
+ uint8_t vic_rot,
|
||||
+ uint16_t start);
|
||||
+
|
||||
+void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup);
|
||||
+void setup_wdb(const struct sysinfo *ctrl);
|
||||
+
|
||||
uint8_t get_rx_bias(const struct sysinfo *ctrl);
|
||||
|
||||
uint8_t get_tCWL(uint32_t mem_clock_mhz);
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
index 9929f617fe..7aa8d8c8b2 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
@@ -335,6 +335,18 @@ union mcscheds_cbit_reg {
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
+union reut_pat_cl_mux_lmn_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t l_data_select : 1; // Bits 0:0
|
||||
+ uint32_t en_sweep_freq : 1; // Bits 1:1
|
||||
+ uint32_t : 6; // Bits 7:2
|
||||
+ uint32_t l_counter : 8; // Bits 15:8
|
||||
+ uint32_t m_counter : 8; // Bits 23:16
|
||||
+ uint32_t n_counter : 8; // Bits 31:24
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
union reut_pat_cadb_prog_reg {
|
||||
struct __packed {
|
||||
uint32_t addr : 16; // Bits 15:0
|
||||
@@ -439,6 +451,39 @@ union reut_misc_odt_ctrl_reg {
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
+union ldat_pdat_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t fast_addr : 12; // Bits 11:0
|
||||
+ uint32_t : 4; // Bits 15:12
|
||||
+ uint32_t addr_en : 1; // Bits 16:16
|
||||
+ uint32_t seq_en : 1; // Bits 17:17
|
||||
+ uint32_t pol_0 : 1; // Bits 18:18
|
||||
+ uint32_t pol_1 : 1; // Bits 19:19
|
||||
+ uint32_t cmd_a : 4; // Bits 23:20
|
||||
+ uint32_t cmd_b : 4; // Bits 27:24
|
||||
+ uint32_t cmd_c : 4; // Bits 31:28
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
+union ldat_sdat_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t bank_sel : 4; // Bits 3:0
|
||||
+ uint32_t : 1; // Bits 4:4
|
||||
+ uint32_t array_sel : 5; // Bits 9:5
|
||||
+ uint32_t cmp : 1; // Bits 10:10
|
||||
+ uint32_t replicate : 1; // Bits 11:11
|
||||
+ uint32_t dword : 4; // Bits 15:12
|
||||
+ uint32_t mode : 2; // Bits 17:16
|
||||
+ uint32_t mpmap : 6; // Bits 23:18
|
||||
+ uint32_t mpb_offset : 4; // Bits 27:24
|
||||
+ uint32_t stage_en : 1; // Bits 28:28
|
||||
+ uint32_t shadow : 2; // Bits 30:29
|
||||
+ uint32_t : 1; // Bits 31:31
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
union mcscheds_dft_misc_reg {
|
||||
struct __packed {
|
||||
uint32_t wdar : 1; // Bits 0:0
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/setup_wdb.c b/src/northbridge/intel/haswell/native_raminit/setup_wdb.c
|
||||
new file mode 100644
|
||||
index 0000000000..ec37c48415
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/setup_wdb.c
|
||||
@@ -0,0 +1,159 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+#include <types.h>
|
||||
+
|
||||
+#include "raminit_native.h"
|
||||
+
|
||||
+static void ldat_write_cacheline(
|
||||
+ const struct sysinfo *const ctrl,
|
||||
+ const uint8_t chunk,
|
||||
+ const uint16_t start,
|
||||
+ const uint64_t data)
|
||||
+{
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ /*
|
||||
+ * Do not do a 64-bit write here. The register is not aligned
|
||||
+ * to a 64-bit boundary, which could potentially cause issues.
|
||||
+ */
|
||||
+ mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 0), data & UINT32_MAX);
|
||||
+ mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 1), data >> 32);
|
||||
+ /*
|
||||
+ * Set REPLICATE = 0 as you don't want to replicate the data.
|
||||
+ * Set BANK_SEL to the chunk you want to write the 64 bits to.
|
||||
+ * Set ARRAY_SEL = 0 (the MC WDB) and MODE = 1.
|
||||
+ */
|
||||
+ const union ldat_sdat_reg ldat_sdat = {
|
||||
+ .bank_sel = chunk,
|
||||
+ .mode = 1,
|
||||
+ };
|
||||
+ mchbar_write32(QCLK_ch_LDAT_SDAT(channel), ldat_sdat.raw);
|
||||
+ /*
|
||||
+ * Finally, write the PDAT register indicating which cacheline
|
||||
+ * of the WDB you want to write to by setting FAST_ADDR field
|
||||
+ * to one of the 64 cache lines. Also set CMD_B in the PDAT
|
||||
+ * register to 4'b1000, indicating that this is a LDAT write.
|
||||
+ */
|
||||
+ const union ldat_pdat_reg ldat_pdat = {
|
||||
+ .fast_addr = MIN(start, 0xfff),
|
||||
+ .cmd_b = 8,
|
||||
+ };
|
||||
+ mchbar_write32(QCLK_ch_LDAT_PDAT(channel), ldat_pdat.raw);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void clear_ldat_mode(const struct sysinfo *const ctrl)
|
||||
+{
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
|
||||
+ mchbar_write32(QCLK_ch_LDAT_SDAT(channel), 0);
|
||||
+}
|
||||
+
|
||||
+void write_wdb_fixed_pat(
|
||||
+ const struct sysinfo *const ctrl,
|
||||
+ const uint8_t patterns[],
|
||||
+ const uint8_t pat_mask[],
|
||||
+ const uint8_t spread,
|
||||
+ const uint16_t start)
|
||||
+{
|
||||
+ for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
|
||||
+ uint64_t data = 0;
|
||||
+ for (uint8_t b = 0; b < 64; b++) {
|
||||
+ const uint8_t beff = b % spread;
|
||||
+ const uint8_t burst = patterns[pat_mask[beff]];
|
||||
+ if (burst & BIT(chunk))
|
||||
+ data |= 1ULL << b;
|
||||
+ }
|
||||
+ ldat_write_cacheline(ctrl, chunk, start, data);
|
||||
+ }
|
||||
+ clear_ldat_mode(ctrl);
|
||||
+}
|
||||
+
|
||||
+static inline uint32_t rol_u32(const uint32_t val)
|
||||
+{
|
||||
+ return (val << 1) | ((val >> 31) & 1);
|
||||
+}
|
||||
+
|
||||
+void write_wdb_va_pat(
|
||||
+ const struct sysinfo *const ctrl,
|
||||
+ const uint32_t agg_mask,
|
||||
+ const uint32_t vic_mask,
|
||||
+ const uint8_t vic_rot,
|
||||
+ const uint16_t start)
|
||||
+{
|
||||
+ static const uint8_t va_mask_to_compressed[4] = {0xaa, 0xc0, 0xcc, 0xf0};
|
||||
+ uint32_t v_mask = vic_mask;
|
||||
+ uint32_t a_mask = agg_mask;
|
||||
+ for (uint8_t v = 0; v < vic_rot; v++) {
|
||||
+ uint8_t compressed[32] = {0};
|
||||
+ /* Iterate through all 32 bits and create a compressed version of cacheline */
|
||||
+ for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++) {
|
||||
+ const uint8_t vic = !!(v_mask & BIT(b));
|
||||
+ const uint8_t agg = !!(a_mask & BIT(b));
|
||||
+ const uint8_t index = !vic << 1 | agg << 0;
|
||||
+ compressed[b] = va_mask_to_compressed[index];
|
||||
+ }
|
||||
+ for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
|
||||
+ uint32_t data = 0;
|
||||
+ for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++)
|
||||
+ data |= !!(compressed[b] & BIT(chunk)) << b;
|
||||
+
|
||||
+ const uint64_t data64 = (uint64_t)data << 32 | data;
|
||||
+ ldat_write_cacheline(ctrl, chunk, start + v, data64);
|
||||
+ }
|
||||
+ v_mask = rol_u32(v_mask);
|
||||
+ a_mask = rol_u32(a_mask);
|
||||
+ }
|
||||
+ clear_ldat_mode(ctrl);
|
||||
+}
|
||||
+
|
||||
+void program_wdb_lfsr(const struct sysinfo *ctrl, const bool cleanup)
|
||||
+{
|
||||
+ /* Cleanup LFSR seeds are sequential */
|
||||
+ const uint32_t cleanup_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xaaaaaa, 0xcccccc, 0xf0f0f0 };
|
||||
+ const uint32_t regular_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xa10ca1, 0xef0d08, 0xad0a1e };
|
||||
+ const uint32_t *seeds = cleanup ? cleanup_seeds : regular_seeds;
|
||||
+
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t i = 0; i < NUM_WDB_CL_MUX_SEEDS; i++) {
|
||||
+ mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_RD_x(channel, i), seeds[i]);
|
||||
+ mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_WR_x(channel, i), seeds[i]);
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+void setup_wdb(const struct sysinfo *ctrl)
|
||||
+{
|
||||
+ const uint32_t amask[9] = {
|
||||
+ 0x86186186, 0x18618618, 0x30c30c30,
|
||||
+ 0xa28a28a2, 0x8a28a28a, 0x14514514,
|
||||
+ 0x28a28a28, 0x92492492, 0x24924924,
|
||||
+ };
|
||||
+ const uint32_t vmask = 0x41041041;
|
||||
+
|
||||
+ /* Fill first 8 entries with simple 2-LFSR VA pattern */
|
||||
+ write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
|
||||
+
|
||||
+ /* Fill next 54 entries with 3-LFSR VA pattern */
|
||||
+ for (uint8_t a = 0; a < ARRAY_SIZE(amask); a++)
|
||||
+ write_wdb_va_pat(ctrl, amask[a], vmask, 6, 8 + a * 6);
|
||||
+
|
||||
+ program_wdb_lfsr(ctrl, false);
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ const union reut_pat_cl_mux_lmn_reg wdb_cl_mux_lmn = {
|
||||
+ .en_sweep_freq = 1,
|
||||
+ .l_counter = 1,
|
||||
+ .m_counter = 1,
|
||||
+ .n_counter = 10,
|
||||
+ };
|
||||
+ mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_LMN(channel), wdb_cl_mux_lmn.raw);
|
||||
+ }
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
index 4fc78a7f43..f8408e51a0 100644
|
||||
--- a/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
@@ -94,6 +94,11 @@
|
||||
#define TC_BANK_RANK_D_ch(ch) _MCMAIN_C(0x4014, ch)
|
||||
#define SC_ROUNDT_LAT_ch(ch) _MCMAIN_C(0x4024, ch)
|
||||
|
||||
+#define REUT_ch_PAT_WDB_CL_MUX_WR_x(ch, x) _MCMAIN_C_X(0x4048, ch, x) /* x in 0 .. 2 */
|
||||
+#define REUT_ch_PAT_WDB_CL_MUX_RD_x(ch, x) _MCMAIN_C_X(0x4054, ch, x) /* x in 0 .. 2 */
|
||||
+
|
||||
+#define REUT_ch_PAT_WDB_CL_MUX_LMN(ch) _MCMAIN_C(0x4078, ch)
|
||||
+
|
||||
#define SC_WR_ADD_DELAY_ch(ch) _MCMAIN_C(0x40d0, ch)
|
||||
|
||||
#define REUT_ch_MISC_CKE_CTRL(ch) _MCMAIN_C(0x4190, ch)
|
||||
@@ -110,6 +115,10 @@
|
||||
#define MC_INIT_STATE_ch(ch) _MCMAIN_C(0x42a0, ch)
|
||||
#define TC_SRFTP_ch(ch) _MCMAIN_C(0x42a4, ch)
|
||||
|
||||
+#define QCLK_ch_LDAT_PDAT(ch) _MCMAIN_C(0x42d0, ch)
|
||||
+#define QCLK_ch_LDAT_SDAT(ch) _MCMAIN_C(0x42d4, ch)
|
||||
+#define QCLK_ch_LDAT_DATA_IN_x(ch, x) _MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
|
||||
+
|
||||
#define REUT_GLOBAL_ERR 0x4804
|
||||
|
||||
#define REUT_ch_SEQ_CFG(ch) (0x48a8 + 8 * (ch))
|
||||
--
|
||||
2.39.2
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,222 @@
|
||||
From 3cd11e7e31e0416ead9782213d582aefc6461e94 Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sun, 8 May 2022 00:56:00 +0200
|
||||
Subject: [PATCH 09/15] haswell NRI: Add range tracking library
|
||||
|
||||
Implement a small library used to keep track of passing ranges. This
|
||||
will be used by 1D training algorithms when margining some parameter.
|
||||
|
||||
Change-Id: I8718e85165160afd7c0c8e730b5ce6c9c00f8a60
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../intel/haswell/native_raminit/Makefile.mk | 1 +
|
||||
.../intel/haswell/native_raminit/ranges.c | 109 ++++++++++++++++++
|
||||
.../intel/haswell/native_raminit/ranges.h | 68 +++++++++++
|
||||
3 files changed, 178 insertions(+)
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.c
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.h
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
index 6e1b365602..2da950771d 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
@@ -9,6 +9,7 @@ romstage-y += io_comp_control.c
|
||||
romstage-y += memory_map.c
|
||||
romstage-y += raminit_main.c
|
||||
romstage-y += raminit_native.c
|
||||
+romstage-y += ranges.c
|
||||
romstage-y += reut.c
|
||||
romstage-y += setup_wdb.c
|
||||
romstage-y += spd_bitmunching.c
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/ranges.c b/src/northbridge/intel/haswell/native_raminit/ranges.c
|
||||
new file mode 100644
|
||||
index 0000000000..cdebc1fa66
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/ranges.c
|
||||
@@ -0,0 +1,109 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <types.h>
|
||||
+
|
||||
+#include "ranges.h"
|
||||
+
|
||||
+void linear_record_pass(
|
||||
+ struct linear_train_data *const data,
|
||||
+ const bool pass,
|
||||
+ const int32_t value,
|
||||
+ const int32_t start,
|
||||
+ const int32_t step)
|
||||
+{
|
||||
+ /* If this is the first time, initialize all values */
|
||||
+ if (value == start) {
|
||||
+ /*
|
||||
+ * If value passed, create a zero-length region for the current value,
|
||||
+ * which may be extended as long as the successive values are passing.
|
||||
+ *
|
||||
+ * Otherwise, create a zero-length range for the preceding value. This
|
||||
+ * range cannot be extended by other passing values, which is desired.
|
||||
+ */
|
||||
+ data->current.start = start - (pass ? 0 : step);
|
||||
+ data->current.end = data->current.start;
|
||||
+ data->largest = data->current;
|
||||
+ } else if (pass) {
|
||||
+ /* If this pass is not contiguous, it belongs to a new region */
|
||||
+ if (data->current.end != (value - step))
|
||||
+ data->current.start = value;
|
||||
+
|
||||
+ /* Update end of current region */
|
||||
+ data->current.end = value;
|
||||
+
|
||||
+ /* Update largest region */
|
||||
+ if (range_width(data->current) > range_width(data->largest))
|
||||
+ data->largest = data->current;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+void phase_record_pass(
|
||||
+ struct phase_train_data *const data,
|
||||
+ const bool pass,
|
||||
+ const int32_t value,
|
||||
+ const int32_t start,
|
||||
+ const int32_t step)
|
||||
+{
|
||||
+ /* If this is the first time, initialize all values */
|
||||
+ if (value == start) {
|
||||
+ /*
|
||||
+ * If value passed, create a zero-length region for the current value,
|
||||
+ * which may be extended as long as the successive values are passing.
|
||||
+ *
|
||||
+ * Otherwise, create a zero-length range for the preceding value. This
|
||||
+ * range cannot be extended by other passing values, which is desired.
|
||||
+ */
|
||||
+ data->current.start = start - (pass ? 0 : step);
|
||||
+ data->current.end = data->current.start;
|
||||
+ data->largest = data->current;
|
||||
+ data->initial = data->current;
|
||||
+ return;
|
||||
+ }
|
||||
+ if (!pass)
|
||||
+ return;
|
||||
+
|
||||
+ /* Update initial region */
|
||||
+ if (data->initial.end == (value - step))
|
||||
+ data->initial.end = value;
|
||||
+
|
||||
+ /* If this pass is not contiguous, it belongs to a new region */
|
||||
+ if (data->current.end != (value - step))
|
||||
+ data->current.start = value;
|
||||
+
|
||||
+ /* Update end of current region */
|
||||
+ data->current.end = value;
|
||||
+
|
||||
+ /* Update largest region */
|
||||
+ if (range_width(data->current) > range_width(data->largest))
|
||||
+ data->largest = data->current;
|
||||
+}
|
||||
+
|
||||
+void phase_append_initial_to_current(
|
||||
+ struct phase_train_data *const data,
|
||||
+ const int32_t start,
|
||||
+ const int32_t step)
|
||||
+{
|
||||
+ /* If initial region is valid and does not overlap, append it */
|
||||
+ if (data->initial.start == start && data->initial.end != data->current.end)
|
||||
+ data->current.end += step + range_width(data->initial);
|
||||
+
|
||||
+ /* Update largest region */
|
||||
+ if (range_width(data->current) > range_width(data->largest))
|
||||
+ data->largest = data->current;
|
||||
+}
|
||||
+
|
||||
+void phase_append_current_to_initial(
|
||||
+ struct phase_train_data *const data,
|
||||
+ const int32_t start,
|
||||
+ const int32_t step)
|
||||
+{
|
||||
+ /* If initial region is valid and does not overlap, append it */
|
||||
+ if (data->initial.start == start && data->initial.end != data->current.end) {
|
||||
+ data->initial.start -= (step + range_width(data->current));
|
||||
+ data->current = data->initial;
|
||||
+ }
|
||||
+
|
||||
+ /* Update largest region */
|
||||
+ if (range_width(data->current) > range_width(data->largest))
|
||||
+ data->largest = data->current;
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/ranges.h b/src/northbridge/intel/haswell/native_raminit/ranges.h
|
||||
new file mode 100644
|
||||
index 0000000000..235392df96
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/ranges.h
|
||||
@@ -0,0 +1,68 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#ifndef HASWELL_RAMINIT_RANGES_H
|
||||
+#define HASWELL_RAMINIT_RANGES_H
|
||||
+
|
||||
+#include <types.h>
|
||||
+
|
||||
+/*
|
||||
+ * Many algorithms shmoo some parameter to determine the largest passing
|
||||
+ * range. Provide a common implementation to avoid redundant boilerplate.
|
||||
+ */
|
||||
+struct passing_range {
|
||||
+ int32_t start;
|
||||
+ int32_t end;
|
||||
+};
|
||||
+
|
||||
+/* Structure for linear parameters, such as roundtrip delays */
|
||||
+struct linear_train_data {
|
||||
+ struct passing_range current;
|
||||
+ struct passing_range largest;
|
||||
+};
|
||||
+
|
||||
+/*
|
||||
+ * Phase ranges are "circular": the first and last indices are contiguous.
|
||||
+ * To correctly determine the largest passing range, one has to combine
|
||||
+ * the initial range and the current range when processing the last index.
|
||||
+ */
|
||||
+struct phase_train_data {
|
||||
+ struct passing_range initial;
|
||||
+ struct passing_range current;
|
||||
+ struct passing_range largest;
|
||||
+};
|
||||
+
|
||||
+static inline int32_t range_width(const struct passing_range range)
|
||||
+{
|
||||
+ return range.end - range.start;
|
||||
+}
|
||||
+
|
||||
+static inline int32_t range_center(const struct passing_range range)
|
||||
+{
|
||||
+ return range.start + range_width(range) / 2;
|
||||
+}
|
||||
+
|
||||
+void linear_record_pass(
|
||||
+ struct linear_train_data *data,
|
||||
+ bool pass,
|
||||
+ int32_t value,
|
||||
+ int32_t start,
|
||||
+ int32_t step);
|
||||
+
|
||||
+void phase_record_pass(
|
||||
+ struct phase_train_data *data,
|
||||
+ bool pass,
|
||||
+ int32_t value,
|
||||
+ int32_t start,
|
||||
+ int32_t step);
|
||||
+
|
||||
+void phase_append_initial_to_current(
|
||||
+ struct phase_train_data *data,
|
||||
+ int32_t start,
|
||||
+ int32_t step);
|
||||
+
|
||||
+void phase_append_current_to_initial(
|
||||
+ struct phase_train_data *data,
|
||||
+ int32_t start,
|
||||
+ int32_t step);
|
||||
+
|
||||
+#endif
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,294 @@
|
||||
From 9d416f00d53bda9f074b9f843fef4a6d4537202a Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sun, 8 May 2022 01:11:03 +0200
|
||||
Subject: [PATCH 10/15] haswell NRI: Add library to change margins
|
||||
|
||||
Implement a library to change Rx/Tx margins. It will be expanded later.
|
||||
|
||||
Change-Id: I0b55aba428d8b4d4e16d2fbdec57235ce3ce8adf
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../intel/haswell/native_raminit/Makefile.mk | 1 +
|
||||
.../haswell/native_raminit/change_margin.c | 154 ++++++++++++++++++
|
||||
.../haswell/native_raminit/raminit_native.h | 50 ++++++
|
||||
.../intel/haswell/registers/mchbar.h | 9 +
|
||||
4 files changed, 214 insertions(+)
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/change_margin.c
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
index 2da950771d..ebe9e9b762 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
@@ -1,5 +1,6 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
+romstage-y += change_margin.c
|
||||
romstage-y += configure_mc.c
|
||||
romstage-y += ddr3.c
|
||||
romstage-y += jedec_reset.c
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
|
||||
new file mode 100644
|
||||
index 0000000000..12da59580f
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
|
||||
@@ -0,0 +1,154 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <commonlib/clamp.h>
|
||||
+#include <console/console.h>
|
||||
+#include <delay.h>
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+#include <timer.h>
|
||||
+
|
||||
+#include "raminit_native.h"
|
||||
+
|
||||
+void update_rxt(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ const uint8_t channel,
|
||||
+ const uint8_t rank,
|
||||
+ const uint8_t byte,
|
||||
+ const enum rxt_subfield subfield,
|
||||
+ const int32_t value)
|
||||
+{
|
||||
+ union ddr_data_rx_train_rank_reg rxt = {
|
||||
+ .rcven = ctrl->rcven[channel][rank][byte],
|
||||
+ .dqs_p = ctrl->rxdqsp[channel][rank][byte],
|
||||
+ .rx_eq = ctrl->rx_eq[channel][rank][byte],
|
||||
+ .dqs_n = ctrl->rxdqsn[channel][rank][byte],
|
||||
+ .vref = ctrl->rxvref[channel][rank][byte],
|
||||
+ };
|
||||
+ int32_t new_value;
|
||||
+ switch (subfield) {
|
||||
+ case RXT_RCVEN:
|
||||
+ new_value = clamp_s32(0, value, 511);
|
||||
+ rxt.rcven = new_value;
|
||||
+ break;
|
||||
+ case RXT_RXDQS_P:
|
||||
+ new_value = clamp_s32(0, value, 63);
|
||||
+ rxt.dqs_p = new_value;
|
||||
+ break;
|
||||
+ case RXT_RX_EQ:
|
||||
+ new_value = clamp_s32(0, value, 31);
|
||||
+ rxt.rx_eq = new_value;
|
||||
+ break;
|
||||
+ case RXT_RXDQS_N:
|
||||
+ new_value = clamp_s32(0, value, 63);
|
||||
+ rxt.dqs_n = new_value;
|
||||
+ break;
|
||||
+ case RXT_RX_VREF:
|
||||
+ new_value = clamp_s32(-32, value, 31);
|
||||
+ rxt.vref = new_value;
|
||||
+ break;
|
||||
+ case RXT_RXDQS_BOTH:
|
||||
+ new_value = clamp_s32(0, value, 63);
|
||||
+ rxt.dqs_p = new_value;
|
||||
+ rxt.dqs_n = new_value;
|
||||
+ break;
|
||||
+ case RXT_RESTORE:
|
||||
+ new_value = value;
|
||||
+ break;
|
||||
+ default:
|
||||
+ die("%s: Unhandled subfield index %u\n", __func__, subfield);
|
||||
+ }
|
||||
+
|
||||
+ if (new_value != value) {
|
||||
+ printk(BIOS_ERR, "%s: Overflow for subfield %u: %d ---> %d\n",
|
||||
+ __func__, subfield, value, new_value);
|
||||
+ }
|
||||
+ mchbar_write32(RX_TRAIN_ch_r_b(channel, rank, byte), rxt.raw);
|
||||
+ download_regfile(ctrl, channel, false, rank, REG_FILE_USE_RANK, byte, true, false);
|
||||
+}
|
||||
+
|
||||
+void update_txt(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ const uint8_t channel,
|
||||
+ const uint8_t rank,
|
||||
+ const uint8_t byte,
|
||||
+ const enum txt_subfield subfield,
|
||||
+ const int32_t value)
|
||||
+{
|
||||
+ union ddr_data_tx_train_rank_reg txt = {
|
||||
+ .dq_delay = ctrl->tx_dq[channel][rank][byte],
|
||||
+ .dqs_delay = ctrl->txdqs[channel][rank][byte],
|
||||
+ .tx_eq = ctrl->tx_eq[channel][rank][byte],
|
||||
+ };
|
||||
+ int32_t new_value;
|
||||
+ switch (subfield) {
|
||||
+ case TXT_TX_DQ:
|
||||
+ new_value = clamp_s32(0, value, 511);
|
||||
+ txt.dq_delay = new_value;
|
||||
+ break;
|
||||
+ case TXT_TXDQS:
|
||||
+ new_value = clamp_s32(0, value, 511);
|
||||
+ txt.dqs_delay = new_value;
|
||||
+ break;
|
||||
+ case TXT_TX_EQ:
|
||||
+ new_value = clamp_s32(0, value, 63);
|
||||
+ txt.tx_eq = new_value;
|
||||
+ break;
|
||||
+ case TXT_DQDQS_OFF:
|
||||
+ new_value = value;
|
||||
+ txt.dqs_delay += new_value;
|
||||
+ txt.dq_delay += new_value;
|
||||
+ break;
|
||||
+ case TXT_RESTORE:
|
||||
+ new_value = value;
|
||||
+ break;
|
||||
+ default:
|
||||
+ die("%s: Unhandled subfield index %u\n", __func__, subfield);
|
||||
+ }
|
||||
+ if (new_value != value) {
|
||||
+ printk(BIOS_ERR, "%s: Overflow for subfield %u: %d ---> %d\n",
|
||||
+ __func__, subfield, value, new_value);
|
||||
+ }
|
||||
+ mchbar_write32(TX_TRAIN_ch_r_b(channel, rank, byte), txt.raw);
|
||||
+ download_regfile(ctrl, channel, false, rank, REG_FILE_USE_RANK, byte, false, true);
|
||||
+}
|
||||
+
|
||||
+void download_regfile(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ const uint8_t channel,
|
||||
+ const bool multicast,
|
||||
+ const uint8_t rank,
|
||||
+ const enum regfile_mode regfile,
|
||||
+ const uint8_t byte,
|
||||
+ const bool read_rf_rd,
|
||||
+ const bool read_rf_wr)
|
||||
+{
|
||||
+ union reut_seq_base_addr_reg reut_seq_base_addr;
|
||||
+ switch (regfile) {
|
||||
+ case REG_FILE_USE_START:
|
||||
+ reut_seq_base_addr.raw = mchbar_read64(REUT_ch_SEQ_ADDR_START(channel));
|
||||
+ break;
|
||||
+ case REG_FILE_USE_CURRENT:
|
||||
+ reut_seq_base_addr.raw = mchbar_read64(REUT_ch_SEQ_ADDR_CURRENT(channel));
|
||||
+ break;
|
||||
+ case REG_FILE_USE_RANK:
|
||||
+ reut_seq_base_addr.raw = 0;
|
||||
+ if (rank >= NUM_SLOTRANKS)
|
||||
+ die("%s: bad rank %u\n", __func__, rank);
|
||||
+ break;
|
||||
+ default:
|
||||
+ die("%s: Invalid regfile param %u\n", __func__, regfile);
|
||||
+ }
|
||||
+ uint8_t phys_rank = rank;
|
||||
+ if (reut_seq_base_addr.raw != 0) {
|
||||
+ /* Map REUT logical rank to physical rank */
|
||||
+ const uint32_t log_to_phys = mchbar_read32(REUT_ch_RANK_LOG_TO_PHYS(channel));
|
||||
+ phys_rank = log_to_phys >> (reut_seq_base_addr.rank_addr * 4) & 0x3;
|
||||
+ }
|
||||
+ uint32_t reg = multicast ? DDR_DATA_ch_CONTROL_0(channel) : DQ_CONTROL_0(channel, byte);
|
||||
+ union ddr_data_control_0_reg ddr_data_control_0 = {
|
||||
+ .raw = mchbar_read32(reg),
|
||||
+ };
|
||||
+ ddr_data_control_0.read_rf_rd = read_rf_rd;
|
||||
+ ddr_data_control_0.read_rf_wr = read_rf_wr;
|
||||
+ ddr_data_control_0.read_rf_rank = phys_rank;
|
||||
+ mchbar_write32(reg, ddr_data_control_0.raw);
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index 56df36ca8d..7c1a786780 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -117,6 +117,30 @@ enum test_stop {
|
||||
ALSOE = 3, /* Stop on all lanes error */
|
||||
};
|
||||
|
||||
+enum rxt_subfield {
|
||||
+ RXT_RCVEN = 0,
|
||||
+ RXT_RXDQS_P = 1,
|
||||
+ RXT_RX_EQ = 2,
|
||||
+ RXT_RXDQS_N = 3,
|
||||
+ RXT_RX_VREF = 4,
|
||||
+ RXT_RXDQS_BOTH = 5,
|
||||
+ RXT_RESTORE = 255,
|
||||
+};
|
||||
+
|
||||
+enum txt_subfield {
|
||||
+ TXT_TX_DQ = 0,
|
||||
+ TXT_TXDQS = 1,
|
||||
+ TXT_TX_EQ = 2,
|
||||
+ TXT_DQDQS_OFF = 3,
|
||||
+ TXT_RESTORE = 255,
|
||||
+};
|
||||
+
|
||||
+enum regfile_mode {
|
||||
+ REG_FILE_USE_RANK, /* Used when changing parameters for each rank */
|
||||
+ REG_FILE_USE_START, /* Used when changing parameters before the test */
|
||||
+ REG_FILE_USE_CURRENT, /* Used when changing parameters after the test */
|
||||
+};
|
||||
+
|
||||
struct wdb_pat {
|
||||
uint32_t start_ptr; /* Starting pointer in WDB */
|
||||
uint32_t stop_ptr; /* Stopping pointer in WDB */
|
||||
@@ -452,6 +476,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas
|
||||
void run_mpr_io_test(bool clear_errors);
|
||||
uint8_t run_io_test(struct sysinfo *ctrl, uint8_t chanmask, uint8_t dq_pat, bool clear_errors);
|
||||
|
||||
+void update_rxt(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ uint8_t channel,
|
||||
+ uint8_t rank,
|
||||
+ uint8_t byte,
|
||||
+ enum rxt_subfield subfield,
|
||||
+ int32_t value);
|
||||
+
|
||||
+void update_txt(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ uint8_t channel,
|
||||
+ uint8_t rank,
|
||||
+ uint8_t byte,
|
||||
+ enum txt_subfield subfield,
|
||||
+ int32_t value);
|
||||
+
|
||||
+void download_regfile(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ uint8_t channel,
|
||||
+ bool multicast,
|
||||
+ uint8_t rank,
|
||||
+ enum regfile_mode regfile,
|
||||
+ uint8_t byte,
|
||||
+ bool read_rf_rd,
|
||||
+ bool read_rf_wr);
|
||||
+
|
||||
uint8_t get_rx_bias(const struct sysinfo *ctrl);
|
||||
|
||||
uint8_t get_tCWL(uint32_t mem_clock_mhz);
|
||||
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
index 817a9f8bf8..a81559bb1e 100644
|
||||
--- a/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
@@ -15,7 +15,11 @@
|
||||
/* Register definitions */
|
||||
|
||||
/* DDR DATA per-channel per-bytelane */
|
||||
+#define RX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0000, ch, rank, byte)
|
||||
+#define TX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0020, ch, rank, byte)
|
||||
+
|
||||
#define DQ_CONTROL_2(ch, byte) _DDRIO_C_R_B(0x0064, ch, 0, byte)
|
||||
+#define DQ_CONTROL_0(ch, byte) _DDRIO_C_R_B(0x0074, ch, 0, byte)
|
||||
|
||||
/* DDR CKE per-channel */
|
||||
#define DDR_CKE_ch_CMD_COMP_OFFSET(ch) _DDRIO_C_R_B(0x1204, ch, 0, 0)
|
||||
@@ -38,6 +42,9 @@
|
||||
#define DDR_SCRAMBLE_ch(ch) (0x2000 + 4 * (ch))
|
||||
#define DDR_SCRAM_MISC_CONTROL 0x2008
|
||||
|
||||
+/* DDR DATA per-channel multicast */
|
||||
+#define DDR_DATA_ch_CONTROL_0(ch) _DDRIO_C_R_B(0x3074, ch, 0, 0)
|
||||
+
|
||||
/* DDR CMDN/CMDS per-channel (writes go to both CMDN and CMDS fubs) */
|
||||
#define DDR_CMD_ch_COMP_OFFSET(ch) _DDRIO_C_R_B(0x3204, ch, 0, 0)
|
||||
#define DDR_CMD_ch_PI_CODING(ch) _DDRIO_C_R_B(0x3208, ch, 0, 0)
|
||||
@@ -147,6 +154,8 @@
|
||||
|
||||
#define REUT_ch_SEQ_ADDR_WRAP(ch) (0x48e8 + 8 * (ch))
|
||||
|
||||
+#define REUT_ch_SEQ_ADDR_CURRENT(ch) (0x48f8 + 8 * (ch))
|
||||
+
|
||||
#define REUT_ch_SEQ_MISC_CTL(ch) (0x4908 + 4 * (ch))
|
||||
|
||||
#define REUT_ch_SEQ_ADDR_INC_CTL(ch) (0x4910 + 8 * (ch))
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,708 @@
|
||||
From 770d4ea91297f76038e9351f4611def640df2137 Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sun, 8 May 2022 00:05:41 +0200
|
||||
Subject: [PATCH 11/15] haswell NRI: Add RcvEn training
|
||||
|
||||
Implement the RcvEn (Receive Enable) calibration procedure.
|
||||
|
||||
Change-Id: Ifbfa520f3e0486c56d0988ce67af2ddb9cf29888
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../intel/haswell/native_raminit/Makefile.mk | 1 +
|
||||
.../haswell/native_raminit/raminit_main.c | 1 +
|
||||
.../haswell/native_raminit/raminit_native.h | 14 +
|
||||
.../haswell/native_raminit/reg_structs.h | 13 +
|
||||
.../native_raminit/train_receive_enable.c | 561 ++++++++++++++++++
|
||||
.../intel/haswell/registers/mchbar.h | 3 +
|
||||
6 files changed, 593 insertions(+)
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
index ebe9e9b762..e2fbfb4211 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
@@ -16,3 +16,4 @@ romstage-y += setup_wdb.c
|
||||
romstage-y += spd_bitmunching.c
|
||||
romstage-y += testing_io.c
|
||||
romstage-y += timings_refresh.c
|
||||
+romstage-y += train_receive_enable.c
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
index 5e4674957d..7d444659c3 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = {
|
||||
{ configure_memory_map, true, "MEMMAP", },
|
||||
{ do_jedec_init, true, "JEDECINIT", },
|
||||
{ pre_training, true, "PRETRAIN", },
|
||||
+ { train_receive_enable, true, "RCVET", },
|
||||
};
|
||||
|
||||
/* Return a generic stepping value to make stepping checks simpler */
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index 7c1a786780..a36ebfacd1 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -42,6 +42,9 @@
|
||||
#define NUM_WDB_CL_MUX_SEEDS 3
|
||||
#define NUM_CADB_MUX_SEEDS 3
|
||||
|
||||
+/* Specified in PI ticks. 64 PI ticks == 1 qclk */
|
||||
+#define tDQSCK_DRIFT 64
|
||||
+
|
||||
/* ZQ calibration types */
|
||||
enum {
|
||||
ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */
|
||||
@@ -188,6 +191,7 @@ enum raminit_status {
|
||||
RAMINIT_STATUS_MPLL_INIT_FAILURE,
|
||||
RAMINIT_STATUS_POLL_TIMEOUT,
|
||||
RAMINIT_STATUS_REUT_ERROR,
|
||||
+ RAMINIT_STATUS_RCVEN_FAILURE,
|
||||
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
|
||||
};
|
||||
|
||||
@@ -270,6 +274,10 @@ struct sysinfo {
|
||||
|
||||
union ddr_data_vref_adjust_reg dimm_vref;
|
||||
|
||||
+ uint8_t io_latency[NUM_CHANNELS][NUM_SLOTRANKS];
|
||||
+ uint8_t rt_latency[NUM_CHANNELS][NUM_SLOTRANKS];
|
||||
+ uint32_t rt_io_comp[NUM_CHANNELS];
|
||||
+
|
||||
uint32_t data_offset_train[NUM_CHANNELS][NUM_LANES];
|
||||
uint32_t data_offset_comp[NUM_CHANNELS][NUM_LANES];
|
||||
|
||||
@@ -344,6 +352,11 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl)
|
||||
memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train));
|
||||
}
|
||||
|
||||
+static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint8_t byte)
|
||||
+{
|
||||
+ return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte));
|
||||
+}
|
||||
+
|
||||
/* Number of ticks to wait in units of 69.841279 ns (citation needed) */
|
||||
static inline void tick_delay(const uint32_t delay)
|
||||
{
|
||||
@@ -401,6 +414,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
|
||||
enum raminit_status configure_mc(struct sysinfo *ctrl);
|
||||
enum raminit_status configure_memory_map(struct sysinfo *ctrl);
|
||||
enum raminit_status do_jedec_init(struct sysinfo *ctrl);
|
||||
+enum raminit_status train_receive_enable(struct sysinfo *ctrl);
|
||||
|
||||
void configure_timings(struct sysinfo *ctrl);
|
||||
void configure_refresh(struct sysinfo *ctrl);
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
index b943259b91..b099f4bb82 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
@@ -297,6 +297,19 @@ union ddr_scram_misc_control_reg {
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
+union sc_io_latency_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t iolat_rank0 : 4; // Bits 3:0
|
||||
+ uint32_t iolat_rank1 : 4; // Bits 7:4
|
||||
+ uint32_t iolat_rank2 : 4; // Bits 11:8
|
||||
+ uint32_t iolat_rank3 : 4; // Bits 15:12
|
||||
+ uint32_t rt_iocomp : 6; // Bits 21:16
|
||||
+ uint32_t : 9; // Bits 30:22
|
||||
+ uint32_t dis_rt_clk_gate : 1; // Bits 31:31
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
union mcscheds_cbit_reg {
|
||||
struct __packed {
|
||||
uint32_t dis_opp_cas : 1; // Bits 0:0
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
|
||||
new file mode 100644
|
||||
index 0000000000..576c6bc21e
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
|
||||
@@ -0,0 +1,561 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <console/console.h>
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+#include <types.h>
|
||||
+
|
||||
+#include "raminit_native.h"
|
||||
+#include "ranges.h"
|
||||
+
|
||||
+#define RCVEN_PLOT RAM_DEBUG
|
||||
+
|
||||
+static enum raminit_status change_rcven_timing(struct sysinfo *ctrl, const uint8_t channel)
|
||||
+{
|
||||
+ int16_t max_rcven = -4096;
|
||||
+ int16_t min_rcven = 4096;
|
||||
+ int16_t max_rcven_rank[NUM_SLOTRANKS];
|
||||
+ int16_t min_rcven_rank[NUM_SLOTRANKS];
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ max_rcven_rank[rank] = max_rcven;
|
||||
+ min_rcven_rank[rank] = min_rcven;
|
||||
+ }
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ int16_t new_rcven = ctrl->rcven[channel][rank][byte];
|
||||
+ new_rcven -= ctrl->io_latency[channel][rank] * 64;
|
||||
+ if (max_rcven_rank[rank] < new_rcven)
|
||||
+ max_rcven_rank[rank] = new_rcven;
|
||||
+
|
||||
+ if (min_rcven_rank[rank] > new_rcven)
|
||||
+ min_rcven_rank[rank] = new_rcven;
|
||||
+ }
|
||||
+ if (max_rcven < max_rcven_rank[rank])
|
||||
+ max_rcven = max_rcven_rank[rank];
|
||||
+
|
||||
+ if (min_rcven > min_rcven_rank[rank])
|
||||
+ min_rcven = min_rcven_rank[rank];
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * Determine how far we are from the ideal center point for RcvEn timing.
|
||||
+ * (PiIdeal - AveRcvEn) / 64 is the ideal number of cycles we should have
|
||||
+ * for IO latency. command training will reduce this by 64, so plan for
|
||||
+ * that now in the ideal value. Round to closest integer.
|
||||
+ */
|
||||
+ const int16_t rre_pi_ideal = 256 + 64;
|
||||
+ const int16_t pi_reserve = 64;
|
||||
+ const int16_t rcven_center = (max_rcven + min_rcven) / 2;
|
||||
+ const int8_t iolat_target = DIV_ROUND_CLOSEST(rre_pi_ideal - rcven_center, 64);
|
||||
+
|
||||
+ int8_t io_g_offset = 0;
|
||||
+ int8_t io_lat[NUM_SLOTRANKS] = { 0 };
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ io_lat[rank] = iolat_target;
|
||||
+
|
||||
+ /* Check for RcvEn underflow/overflow */
|
||||
+ const int16_t rcven_lower = 64 * io_lat[rank] + min_rcven_rank[rank];
|
||||
+ if (rcven_lower < pi_reserve)
|
||||
+ io_lat[rank] += DIV_ROUND_UP(pi_reserve - rcven_lower, 64);
|
||||
+
|
||||
+ const int16_t rcven_upper = 64 * io_lat[rank] + max_rcven_rank[rank];
|
||||
+ if (rcven_upper > 511 - pi_reserve)
|
||||
+ io_lat[rank] -= DIV_ROUND_UP(rcven_upper - (511 - pi_reserve), 64);
|
||||
+
|
||||
+ /* Check for IO latency over/underflow */
|
||||
+ if (io_lat[rank] - io_g_offset > 14)
|
||||
+ io_g_offset = io_lat[rank] - 14;
|
||||
+
|
||||
+ if (io_lat[rank] - io_g_offset < 1)
|
||||
+ io_g_offset = io_lat[rank] - 1;
|
||||
+
|
||||
+ const int8_t cycle_offset = io_lat[rank] - ctrl->io_latency[channel][rank];
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ ctrl->rcven[channel][rank][byte] += 64 * cycle_offset;
|
||||
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /* Calculate new IO comp latency */
|
||||
+ union sc_io_latency_reg sc_io_lat = {
|
||||
+ .raw = mchbar_read32(SC_IO_LATENCY_ch(channel)),
|
||||
+ };
|
||||
+
|
||||
+ /* Check if we are underflowing or overflowing this field */
|
||||
+ if (io_g_offset < 0 && sc_io_lat.rt_iocomp < -io_g_offset) {
|
||||
+ printk(BIOS_ERR, "%s: IO COMP underflow\n", __func__);
|
||||
+ printk(BIOS_ERR, "io_g_offset: %d\n", io_g_offset);
|
||||
+ printk(BIOS_ERR, "rt_iocomp: %u\n", sc_io_lat.rt_iocomp);
|
||||
+ return RAMINIT_STATUS_RCVEN_FAILURE;
|
||||
+ }
|
||||
+ if (io_g_offset > 0 && io_g_offset > 0x3f - sc_io_lat.rt_iocomp) {
|
||||
+ printk(BIOS_ERR, "%s: IO COMP overflow\n", __func__);
|
||||
+ printk(BIOS_ERR, "io_g_offset: %d\n", io_g_offset);
|
||||
+ printk(BIOS_ERR, "rt_iocomp: %u\n", sc_io_lat.rt_iocomp);
|
||||
+ return RAMINIT_STATUS_RCVEN_FAILURE;
|
||||
+ }
|
||||
+ sc_io_lat.rt_iocomp += io_g_offset;
|
||||
+ ctrl->rt_io_comp[channel] = sc_io_lat.rt_iocomp;
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (ctrl->rankmap[channel] & BIT(rank))
|
||||
+ ctrl->io_latency[channel][rank] = io_lat[rank] - io_g_offset;
|
||||
+
|
||||
+ const uint8_t shift = rank * 4;
|
||||
+ sc_io_lat.raw &= ~(0xf << shift);
|
||||
+ sc_io_lat.raw |= ctrl->io_latency[channel][rank] << shift;
|
||||
+ }
|
||||
+ mchbar_write32(SC_IO_LATENCY_ch(channel), sc_io_lat.raw);
|
||||
+ return RAMINIT_STATUS_SUCCESS;
|
||||
+}
|
||||
+
|
||||
+#define RL_START (256 + 24)
|
||||
+#define RL_STOP (384 + 24)
|
||||
+#define RL_STEP 8
|
||||
+
|
||||
+#define RE_NUM_SAMPLES 6
|
||||
+
|
||||
+static enum raminit_status verify_high_region(const int32_t center, const int32_t lwidth)
|
||||
+{
|
||||
+ if (center > RL_STOP) {
|
||||
+ /* Check if center of high was found where it should be */
|
||||
+ printk(BIOS_ERR, "RcvEn: Center of high (%d) higher than expected\n", center);
|
||||
+ return RAMINIT_STATUS_RCVEN_FAILURE;
|
||||
+ }
|
||||
+ if (lwidth <= 32) {
|
||||
+ /* Check if width is large enough */
|
||||
+ printk(BIOS_ERR, "RcvEn: Width of high region (%d) too small\n", lwidth);
|
||||
+ return RAMINIT_STATUS_RCVEN_FAILURE;
|
||||
+ }
|
||||
+ if (lwidth >= 96) {
|
||||
+ /* Since we're calibrating a phase, a too large region is a problem */
|
||||
+ printk(BIOS_ERR, "RcvEn: Width of high region (%d) too large\n", lwidth);
|
||||
+ return RAMINIT_STATUS_RCVEN_FAILURE;
|
||||
+ }
|
||||
+ return RAMINIT_STATUS_SUCCESS;
|
||||
+}
|
||||
+
|
||||
+static void program_io_latency(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
|
||||
+{
|
||||
+ const uint8_t shift = rank * 4;
|
||||
+ const uint8_t iolat = ctrl->io_latency[channel][rank];
|
||||
+ mchbar_clrsetbits32(SC_IO_LATENCY_ch(channel), 0xf << shift, iolat << shift);
|
||||
+}
|
||||
+
|
||||
+static void program_rl_delays(struct sysinfo *ctrl, const uint8_t rank, const uint16_t rl_delay)
|
||||
+{
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ update_rxt(ctrl, channel, rank, byte, RXT_RCVEN, rl_delay);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static bool sample_dqs(const uint8_t channel, const uint8_t byte)
|
||||
+{
|
||||
+ return (get_data_train_feedback(channel, byte) & 0x1ff) >= BIT(RE_NUM_SAMPLES - 1);
|
||||
+}
|
||||
+
|
||||
+enum raminit_status train_receive_enable(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ const struct reut_box reut_addr = {
|
||||
+ .col = {
|
||||
+ .start = 0,
|
||||
+ .stop = 1023,
|
||||
+ .inc_rate = 0,
|
||||
+ .inc_val = 1,
|
||||
+ },
|
||||
+ };
|
||||
+ const struct wdb_pat wdb_pattern = {
|
||||
+ .start_ptr = 0,
|
||||
+ .stop_ptr = 9,
|
||||
+ .inc_rate = 32,
|
||||
+ .dq_pattern = BASIC_VA,
|
||||
+ };
|
||||
+
|
||||
+ const uint16_t bytemask = BIT(ctrl->lanes) - 1;
|
||||
+ const uint8_t fine_step = 1;
|
||||
+
|
||||
+ const uint8_t rt_delta = is_hsw_ult() ? 4 : 2;
|
||||
+ const uint8_t rt_io_comp = 21 + rt_delta;
|
||||
+ const uint8_t rt_latency = 16 + rt_delta;
|
||||
+ setup_io_test(
|
||||
+ ctrl,
|
||||
+ ctrl->chanmap,
|
||||
+ PAT_RD,
|
||||
+ 2,
|
||||
+ RE_NUM_SAMPLES + 1,
|
||||
+ &reut_addr,
|
||||
+ 0,
|
||||
+ &wdb_pattern,
|
||||
+ 0,
|
||||
+ 8);
|
||||
+
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ union ddr_data_control_2_reg data_control_2 = {
|
||||
+ .raw = ctrl->dq_control_2[channel][byte],
|
||||
+ };
|
||||
+ data_control_2.force_rx_on = 1;
|
||||
+ mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
|
||||
+ }
|
||||
+ union ddr_data_control_0_reg data_control_0 = {
|
||||
+ .raw = ctrl->dq_control_0[channel],
|
||||
+ };
|
||||
+ if (ctrl->lpddr) {
|
||||
+ /**
|
||||
+ * W/A for b4618574 - @todo: remove for HSW ULT C0
|
||||
+ * Can't have force_odt_on together with leaker, disable LPDDR
|
||||
+ * mode during this training step. lpddr_mode is restored
|
||||
+ * at the end of this function from the host structure.
|
||||
+ */
|
||||
+ data_control_0.lpddr_mode = 0;
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
|
||||
+ }
|
||||
+ data_control_0.force_odt_on = 1;
|
||||
+ data_control_0.rl_training_mode = 1;
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
|
||||
+ mchbar_write32(SC_IO_LATENCY_ch(channel), (union sc_io_latency_reg) {
|
||||
+ .rt_iocomp = rt_io_comp,
|
||||
+ }.raw);
|
||||
+ }
|
||||
+ enum raminit_status status = RAMINIT_STATUS_SUCCESS;
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (!does_rank_exist(ctrl, rank))
|
||||
+ continue;
|
||||
+
|
||||
+ /*
|
||||
+ * Set initial roundtrip latency values. Assume -4 QCLK for worst board
|
||||
+ * layout. This is calculated as HW_ROUNDT_LAT_DEFAULT_VALUE plus:
|
||||
+ *
|
||||
+ * DDR3: Default + (2 * tAA) + 4 QCLK + PI_CLK + N-mode value * 2
|
||||
+ * LPDDR3: Default + (2 * tAA) + 4 QCLK + PI_CLK + tDQSCK_max
|
||||
+ *
|
||||
+ * N-mode is 3 during training mode. Both channels use the same timings.
|
||||
+ */
|
||||
+ /** TODO: differs for LPDDR **/
|
||||
+ const uint32_t tmp = MAX(ctrl->multiplier, 4) + 5 + 2 * ctrl->tAA;
|
||||
+ const uint32_t initial_rt_latency = MIN(rt_latency + tmp, 0x3f);
|
||||
+
|
||||
+ uint8_t chanmask = 0;
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ ctrl->io_latency[channel][rank] = 0;
|
||||
+ mchbar_write8(SC_ROUNDT_LAT_ch(channel) + rank, initial_rt_latency);
|
||||
+ ctrl->rt_latency[channel][rank] = initial_rt_latency;
|
||||
+ }
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Rank %u\n", rank);
|
||||
+ printk(BIOS_DEBUG, "Steps 1 and 2: Find middle of high region\n");
|
||||
+ printk(RCVEN_PLOT, "Byte");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(RCVEN_PLOT, "\t");
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ printk(RCVEN_PLOT, "%u ", byte);
|
||||
+ }
|
||||
+ printk(RCVEN_PLOT, "\nRcvEn\n");
|
||||
+ struct phase_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
|
||||
+ for (uint16_t rl_delay = RL_START; rl_delay < RL_STOP; rl_delay += RL_STEP) {
|
||||
+ printk(RCVEN_PLOT, " % 3d", rl_delay);
|
||||
+ program_rl_delays(ctrl, rank, rl_delay);
|
||||
+ run_io_test(ctrl, chanmask, BASIC_VA, true);
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(RCVEN_PLOT, "\t");
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ const bool high = sample_dqs(channel, byte);
|
||||
+ printk(RCVEN_PLOT, high ? ". " : "# ");
|
||||
+ phase_record_pass(
|
||||
+ ®ion_data[channel][byte],
|
||||
+ high,
|
||||
+ rl_delay,
|
||||
+ RL_START,
|
||||
+ RL_STEP);
|
||||
+ }
|
||||
+ }
|
||||
+ printk(RCVEN_PLOT, "\n");
|
||||
+ }
|
||||
+ printk(RCVEN_PLOT, "\n");
|
||||
+ printk(BIOS_DEBUG, "Update RcvEn timing to be in the center of high region\n");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\n",
|
||||
+ channel, rank);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ struct phase_train_data *const curr_data =
|
||||
+ ®ion_data[channel][byte];
|
||||
+ phase_append_current_to_initial(curr_data, RL_START, RL_STEP);
|
||||
+ const int32_t lwidth = range_width(curr_data->largest);
|
||||
+ const int32_t center = range_center(curr_data->largest);
|
||||
+ printk(BIOS_DEBUG, " B%u: \t%d\t%d\t%d\t%d\n",
|
||||
+ byte,
|
||||
+ curr_data->largest.start,
|
||||
+ curr_data->largest.end,
|
||||
+ lwidth,
|
||||
+ center);
|
||||
+
|
||||
+ status = verify_high_region(center, lwidth);
|
||||
+ if (status) {
|
||||
+ printk(BIOS_ERR,
|
||||
+ "RcvEn problems on channel %u, byte %u\n",
|
||||
+ channel, byte);
|
||||
+ goto clean_up;
|
||||
+ }
|
||||
+ ctrl->rcven[channel][rank][byte] = center;
|
||||
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ }
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Step 3: Quarter preamble - Walk backwards\n");
|
||||
+ printk(RCVEN_PLOT, "Byte");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(RCVEN_PLOT, "\t");
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ printk(RCVEN_PLOT, "%u ", byte);
|
||||
+ }
|
||||
+ printk(RCVEN_PLOT, "\nIOLAT\n");
|
||||
+ bool done = false;
|
||||
+ while (!done) {
|
||||
+ run_io_test(ctrl, chanmask, BASIC_VA, true);
|
||||
+ done = true;
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(RCVEN_PLOT, " %2u\t", ctrl->io_latency[channel][rank]);
|
||||
+ uint16_t highs = 0;
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ const bool high = sample_dqs(channel, byte);
|
||||
+ printk(RCVEN_PLOT, high ? "H " : "L ");
|
||||
+ if (high)
|
||||
+ highs |= BIT(byte);
|
||||
+ }
|
||||
+ if (!highs)
|
||||
+ continue;
|
||||
+
|
||||
+ done = false;
|
||||
+
|
||||
+ /* If all bytes sample high, adjust timing globally */
|
||||
+ if (highs == bytemask && ctrl->io_latency[channel][rank] < 14) {
|
||||
+ ctrl->io_latency[channel][rank] += 2;
|
||||
+ ctrl->io_latency[channel][rank] %= 16;
|
||||
+ program_io_latency(ctrl, channel, rank);
|
||||
+ continue;
|
||||
+ }
|
||||
+
|
||||
+ /* Otherwise, adjust individual bytes */
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ if (!(highs & BIT(byte)))
|
||||
+ continue;
|
||||
+
|
||||
+ if (ctrl->rcven[channel][rank][byte] < 128) {
|
||||
+ printk(BIOS_ERR,
|
||||
+ "RcvEn underflow: walking backwards\n");
|
||||
+ printk(BIOS_ERR,
|
||||
+ "For channel %u, rank %u, byte %u\n",
|
||||
+ channel, rank, byte);
|
||||
+ status = RAMINIT_STATUS_RCVEN_FAILURE;
|
||||
+ goto clean_up;
|
||||
+ }
|
||||
+ ctrl->rcven[channel][rank][byte] -= 128;
|
||||
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
|
||||
+ }
|
||||
+ }
|
||||
+ printk(RCVEN_PLOT, "\n");
|
||||
+ }
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "\nC%u: Preamble\n", channel);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ printk(BIOS_DEBUG,
|
||||
+ " B%u: %u\n", byte, ctrl->rcven[channel][rank][byte]);
|
||||
+ }
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Step 4: Add 1 qclk\n");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ ctrl->rcven[channel][rank][byte] += 64;
|
||||
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
|
||||
+ }
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Step 5: Walk forward to find rising edge\n");
|
||||
+ printk(RCVEN_PLOT, "Byte");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(RCVEN_PLOT, "\t");
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ printk(RCVEN_PLOT, "%u ", byte);
|
||||
+ }
|
||||
+ printk(RCVEN_PLOT, "\n inc\n");
|
||||
+ uint16_t ch_result[NUM_CHANNELS] = { 0 };
|
||||
+ uint8_t inc_preamble[NUM_CHANNELS][NUM_LANES] = { 0 };
|
||||
+ for (uint8_t inc = 0; inc < 64; inc += fine_step) {
|
||||
+ printk(RCVEN_PLOT, " %2u\t", inc);
|
||||
+ run_io_test(ctrl, chanmask, BASIC_VA, true);
|
||||
+ done = true;
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ if (ch_result[channel] & BIT(byte)) {
|
||||
+ /* Skip bytes that are already done */
|
||||
+ printk(RCVEN_PLOT, ". ");
|
||||
+ continue;
|
||||
+ }
|
||||
+ const bool pass = sample_dqs(channel, byte);
|
||||
+ printk(RCVEN_PLOT, pass ? ". " : "# ");
|
||||
+ if (pass) {
|
||||
+ ch_result[channel] |= BIT(byte);
|
||||
+ continue;
|
||||
+ }
|
||||
+ ctrl->rcven[channel][rank][byte] += fine_step;
|
||||
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
|
||||
+ inc_preamble[channel][byte] = inc;
|
||||
+ }
|
||||
+ printk(RCVEN_PLOT, "\t");
|
||||
+ if (ch_result[channel] != bytemask)
|
||||
+ done = false;
|
||||
+ }
|
||||
+ printk(RCVEN_PLOT, "\n");
|
||||
+ if (done)
|
||||
+ break;
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ if (!done) {
|
||||
+ printk(BIOS_ERR, "Error: Preamble edge not found for all bytes\n");
|
||||
+ printk(BIOS_ERR, "The final RcvEn results are as follows:\n");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(BIOS_ERR, "Channel %u Rank %u: preamble\n",
|
||||
+ channel, rank);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ printk(BIOS_ERR, " Byte %u: %u%s\n", byte,
|
||||
+ ctrl->rcven[channel][rank][byte],
|
||||
+ (ch_result[channel] ^ bytemask) & BIT(byte)
|
||||
+ ? ""
|
||||
+ : " *** Check this byte! ***");
|
||||
+ }
|
||||
+ }
|
||||
+ status = RAMINIT_STATUS_RCVEN_FAILURE;
|
||||
+ goto clean_up;
|
||||
+ }
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Step 6: center on preamble and clean up rank\n");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "C%u: Preamble increment\n", channel);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ /*
|
||||
+ * For Traditional, pull in RcvEn by 64. For ULT, take the DQS
|
||||
+ * drift into account to the specified guardband: tDQSCK_DRIFT.
|
||||
+ */
|
||||
+ ctrl->rcven[channel][rank][byte] -= tDQSCK_DRIFT;
|
||||
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
|
||||
+ printk(BIOS_DEBUG, " B%u: %u %u\n", byte,
|
||||
+ ctrl->rcven[channel][rank][byte],
|
||||
+ inc_preamble[channel][byte]);
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ }
|
||||
+
|
||||
+clean_up:
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ if (ctrl->lpddr) {
|
||||
+ /**
|
||||
+ * W/A for b4618574 - @todo: remove for HSW ULT C0
|
||||
+ * Can't have force_odt_on together with leaker, disable LPDDR mode for
|
||||
+ * this training step. This write will disable force_odt_on while still
|
||||
+ * keeping LPDDR mode disabled. Second write will restore LPDDR mode.
|
||||
+ */
|
||||
+ union ddr_data_control_0_reg data_control_0 = {
|
||||
+ .raw = ctrl->dq_control_0[channel],
|
||||
+ };
|
||||
+ data_control_0.lpddr_mode = 0;
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
|
||||
+ }
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ mchbar_write32(DQ_CONTROL_2(channel, byte),
|
||||
+ ctrl->dq_control_2[channel][byte]);
|
||||
+ }
|
||||
+ }
|
||||
+ io_reset();
|
||||
+ if (status)
|
||||
+ return status;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Step 7: Sync IO latency across all ranks\n");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ status = change_rcven_timing(ctrl, channel);
|
||||
+ if (status)
|
||||
+ return status;
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\nFinal Receive Enable and IO latency settings:\n");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ const union sc_io_latency_reg sc_io_latency = {
|
||||
+ .raw = mchbar_read32(SC_IO_LATENCY_ch(channel)),
|
||||
+ };
|
||||
+ printk(BIOS_DEBUG, " C%u.R%u: IOLAT = %u rt_iocomp = %u\n", channel,
|
||||
+ rank, ctrl->io_latency[channel][rank], sc_io_latency.rt_iocomp);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ printk(BIOS_DEBUG, " B%u: %u\n", byte,
|
||||
+ ctrl->rcven[channel][rank][byte]);
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ }
|
||||
+ }
|
||||
+ return status;
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
index a81559bb1e..9172d4f2b0 100644
|
||||
--- a/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
@@ -18,6 +18,8 @@
|
||||
#define RX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0000, ch, rank, byte)
|
||||
#define TX_TRAIN_ch_r_b(ch, rank, byte) _DDRIO_C_R_B(0x0020, ch, rank, byte)
|
||||
|
||||
+#define DDR_DATA_TRAIN_FEEDBACK(ch, byte) _DDRIO_C_R_B(0x0054, ch, 0, byte)
|
||||
+
|
||||
#define DQ_CONTROL_2(ch, byte) _DDRIO_C_R_B(0x0064, ch, 0, byte)
|
||||
#define DQ_CONTROL_0(ch, byte) _DDRIO_C_R_B(0x0074, ch, 0, byte)
|
||||
|
||||
@@ -100,6 +102,7 @@
|
||||
#define COMMAND_RATE_LIMIT_ch(ch) _MCMAIN_C(0x4010, ch)
|
||||
#define TC_BANK_RANK_D_ch(ch) _MCMAIN_C(0x4014, ch)
|
||||
#define SC_ROUNDT_LAT_ch(ch) _MCMAIN_C(0x4024, ch)
|
||||
+#define SC_IO_LATENCY_ch(ch) _MCMAIN_C(0x4028, ch)
|
||||
|
||||
#define REUT_ch_PAT_WDB_CL_MUX_CFG(ch) _MCMAIN_C(0x4040, ch)
|
||||
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+272
@@ -0,0 +1,272 @@
|
||||
From be7b1c72cff3403ecfd746255fccb80c8cee6403 Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sun, 8 May 2022 11:58:59 +0200
|
||||
Subject: [PATCH 12/15] haswell NRI: Add function to change margins
|
||||
|
||||
Implement a function to change margin parameters. Haswell provides a
|
||||
register to apply an offset to margin parameters during training, so
|
||||
make use of it. There are other margin parameters that have not been
|
||||
implemented yet, as they are not needed for now and special handling
|
||||
is needed to provide offset training functionality.
|
||||
|
||||
Change-Id: I5392380e13de3c44e77b7bc9f3b819e2661d1e2d
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../haswell/native_raminit/change_margin.c | 136 ++++++++++++++++++
|
||||
.../haswell/native_raminit/raminit_native.h | 39 +++++
|
||||
.../haswell/native_raminit/reg_structs.h | 12 ++
|
||||
.../intel/haswell/registers/mchbar.h | 1 +
|
||||
4 files changed, 188 insertions(+)
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
|
||||
index 12da59580f..4ba9cfa5c6 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
|
||||
@@ -1,5 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
+#include <assert.h>
|
||||
#include <commonlib/clamp.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
@@ -152,3 +153,138 @@ void download_regfile(
|
||||
ddr_data_control_0.read_rf_rank = phys_rank;
|
||||
mchbar_write32(reg, ddr_data_control_0.raw);
|
||||
}
|
||||
+
|
||||
+static void update_data_offset_train(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ const uint8_t param,
|
||||
+ const uint8_t en_multicast,
|
||||
+ const uint8_t channel_in,
|
||||
+ const uint8_t rank,
|
||||
+ const uint8_t byte_in,
|
||||
+ const bool update_ctrl,
|
||||
+ const enum regfile_mode regfile,
|
||||
+ const uint32_t value)
|
||||
+{
|
||||
+ bool is_rd = false;
|
||||
+ bool is_wr = false;
|
||||
+ switch (param) {
|
||||
+ case RdT:
|
||||
+ case RdV:
|
||||
+ case RcvEna:
|
||||
+ is_rd = true;
|
||||
+ break;
|
||||
+ case WrT:
|
||||
+ case WrDqsT:
|
||||
+ is_wr = true;
|
||||
+ break;
|
||||
+ default:
|
||||
+ die("%s: Invalid margin parameter %u\n", __func__, param);
|
||||
+ }
|
||||
+ if (en_multicast) {
|
||||
+ mchbar_write32(DDR_DATA_OFFSET_TRAIN, value);
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ download_regfile(ctrl, channel, true, rank, regfile, 0, is_rd, is_wr);
|
||||
+ if (update_ctrl) {
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ ctrl->data_offset_train[channel][byte] = value;
|
||||
+ }
|
||||
+ }
|
||||
+ } else {
|
||||
+ mchbar_write32(DDR_DATA_OFFSET_TRAIN_ch_b(channel_in, byte_in), value);
|
||||
+ download_regfile(ctrl, channel_in, false, rank, regfile, byte_in, is_rd, is_wr);
|
||||
+ if (update_ctrl)
|
||||
+ ctrl->data_offset_train[channel_in][byte_in] = value;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static uint32_t get_max_margin(const enum margin_parameter param)
|
||||
+{
|
||||
+ switch (param) {
|
||||
+ case RcvEna:
|
||||
+ case RdT:
|
||||
+ case WrT:
|
||||
+ case WrDqsT:
|
||||
+ return MAX_POSSIBLE_TIME;
|
||||
+ case RdV:
|
||||
+ return MAX_POSSIBLE_VREF;
|
||||
+ default:
|
||||
+ die("%s: Invalid margin parameter %u\n", __func__, param);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+void change_margin(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ const enum margin_parameter param,
|
||||
+ const int32_t value0,
|
||||
+ const bool en_multicast,
|
||||
+ const uint8_t channel,
|
||||
+ const uint8_t rank,
|
||||
+ const uint8_t byte,
|
||||
+ const bool update_ctrl,
|
||||
+ const enum regfile_mode regfile)
|
||||
+{
|
||||
+ /** FIXME: Remove this **/
|
||||
+ if (rank == 0xff)
|
||||
+ die("%s: rank is 0xff\n", __func__);
|
||||
+
|
||||
+ if (!en_multicast && !does_ch_exist(ctrl, channel))
|
||||
+ die("%s: Tried to change margin of empty channel %u\n", __func__, channel);
|
||||
+
|
||||
+ const uint32_t max_value = get_max_margin(param);
|
||||
+ const int32_t v0 = clamp_s32(-max_value, value0, max_value);
|
||||
+
|
||||
+ union ddr_data_offset_train_reg ddr_data_offset_train = {
|
||||
+ .raw = en_multicast ? 0 : ctrl->data_offset_train[channel][byte],
|
||||
+ };
|
||||
+ bool update_offset_train = false;
|
||||
+ switch (param) {
|
||||
+ case RcvEna:
|
||||
+ ddr_data_offset_train.rcven = v0;
|
||||
+ update_offset_train = true;
|
||||
+ break;
|
||||
+ case RdT:
|
||||
+ ddr_data_offset_train.rx_dqs = v0;
|
||||
+ update_offset_train = true;
|
||||
+ break;
|
||||
+ case WrT:
|
||||
+ ddr_data_offset_train.tx_dq = v0;
|
||||
+ update_offset_train = true;
|
||||
+ break;
|
||||
+ case WrDqsT:
|
||||
+ ddr_data_offset_train.tx_dqs = v0;
|
||||
+ update_offset_train = true;
|
||||
+ break;
|
||||
+ case RdV:
|
||||
+ ddr_data_offset_train.vref = v0;
|
||||
+ update_offset_train = true;
|
||||
+ break;
|
||||
+ default:
|
||||
+ die("%s: Invalid margin parameter %u\n", __func__, param);
|
||||
+ }
|
||||
+ if (update_offset_train) {
|
||||
+ update_data_offset_train(
|
||||
+ ctrl,
|
||||
+ param,
|
||||
+ en_multicast,
|
||||
+ channel,
|
||||
+ rank,
|
||||
+ byte,
|
||||
+ update_ctrl,
|
||||
+ regfile,
|
||||
+ ddr_data_offset_train.raw);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+void change_1d_margin_multicast(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ const enum margin_parameter param,
|
||||
+ const int32_t value0,
|
||||
+ const uint8_t rank,
|
||||
+ const bool update_ctrl,
|
||||
+ const enum regfile_mode regfile)
|
||||
+{
|
||||
+ change_margin(ctrl, param, value0, true, 0, rank, 0, update_ctrl, regfile);
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index a36ebfacd1..500fc28909 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -35,6 +35,18 @@
|
||||
|
||||
#define RTTNOM_MASK (BIT(9) | BIT(6) | BIT(2))
|
||||
|
||||
+/* Margin parameter limits */
|
||||
+#define MAX_POSSIBLE_TIME 31
|
||||
+#define MAX_POSSIBLE_VREF 54
|
||||
+
|
||||
+#define MAX_POSSIBLE_BOTH MAX_POSSIBLE_VREF
|
||||
+
|
||||
+#define MIN_TIME (-MAX_POSSIBLE_TIME)
|
||||
+#define MAX_TIME (MAX_POSSIBLE_TIME)
|
||||
+
|
||||
+#define MIN_VREF (-MAX_POSSIBLE_VREF)
|
||||
+#define MAX_VREF (MAX_POSSIBLE_VREF)
|
||||
+
|
||||
#define BASIC_VA_PAT_SPREAD_8 0x01010101
|
||||
|
||||
#define WDB_CACHE_LINE_SIZE 8
|
||||
@@ -45,6 +57,14 @@
|
||||
/* Specified in PI ticks. 64 PI ticks == 1 qclk */
|
||||
#define tDQSCK_DRIFT 64
|
||||
|
||||
+enum margin_parameter {
|
||||
+ RcvEna,
|
||||
+ RdT,
|
||||
+ WrT,
|
||||
+ WrDqsT,
|
||||
+ RdV,
|
||||
+};
|
||||
+
|
||||
/* ZQ calibration types */
|
||||
enum {
|
||||
ZQ_INIT, /* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init with tZQinit */
|
||||
@@ -516,6 +536,25 @@ void download_regfile(
|
||||
bool read_rf_rd,
|
||||
bool read_rf_wr);
|
||||
|
||||
+void change_margin(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ const enum margin_parameter param,
|
||||
+ const int32_t value0,
|
||||
+ const bool en_multicast,
|
||||
+ const uint8_t channel,
|
||||
+ const uint8_t rank,
|
||||
+ const uint8_t byte,
|
||||
+ const bool update_ctrl,
|
||||
+ const enum regfile_mode regfile);
|
||||
+
|
||||
+void change_1d_margin_multicast(
|
||||
+ struct sysinfo *ctrl,
|
||||
+ const enum margin_parameter param,
|
||||
+ const int32_t value0,
|
||||
+ const uint8_t rank,
|
||||
+ const bool update_ctrl,
|
||||
+ const enum regfile_mode regfile);
|
||||
+
|
||||
uint8_t get_rx_bias(const struct sysinfo *ctrl);
|
||||
|
||||
uint8_t get_tCWL(uint32_t mem_clock_mhz);
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
index b099f4bb82..a0e36ed082 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
@@ -25,6 +25,18 @@ union ddr_data_tx_train_rank_reg {
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
+union ddr_data_offset_train_reg {
|
||||
+ struct __packed {
|
||||
+ int32_t rcven : 6; // Bits 5:0
|
||||
+ int32_t rx_dqs : 6; // Bits 11:6
|
||||
+ int32_t tx_dq : 6; // Bits 17:12
|
||||
+ int32_t tx_dqs : 6; // Bits 23:18
|
||||
+ int32_t vref : 7; // Bits 30:24
|
||||
+ int32_t : 1; // Bits 31:31
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
union ddr_data_control_0_reg {
|
||||
struct __packed {
|
||||
uint32_t rx_training_mode : 1; // Bits 0:0
|
||||
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
index 9172d4f2b0..0acafbc826 100644
|
||||
--- a/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
@@ -21,6 +21,7 @@
|
||||
#define DDR_DATA_TRAIN_FEEDBACK(ch, byte) _DDRIO_C_R_B(0x0054, ch, 0, byte)
|
||||
|
||||
#define DQ_CONTROL_2(ch, byte) _DDRIO_C_R_B(0x0064, ch, 0, byte)
|
||||
+#define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte) _DDRIO_C_R_B(0x0070, ch, 0, byte)
|
||||
#define DQ_CONTROL_0(ch, byte) _DDRIO_C_R_B(0x0074, ch, 0, byte)
|
||||
|
||||
/* DDR CKE per-channel */
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,331 @@
|
||||
From ec3dd2a40834e363a5ddaef5e8093e1baa1af56e Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sun, 8 May 2022 11:35:49 +0200
|
||||
Subject: [PATCH 13/15] haswell NRI: Add read MPR training
|
||||
|
||||
Implement read training using DDR3 MPR (Multi-Purpose Register).
|
||||
|
||||
Change-Id: Id17cb2c4c399ac9bcc937b595b58f863c152461b
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../intel/haswell/native_raminit/Makefile.mk | 1 +
|
||||
.../haswell/native_raminit/raminit_main.c | 1 +
|
||||
.../haswell/native_raminit/raminit_native.h | 4 +
|
||||
.../haswell/native_raminit/train_read_mpr.c | 240 ++++++++++++++++++
|
||||
.../intel/haswell/registers/mchbar.h | 2 +-
|
||||
5 files changed, 247 insertions(+), 1 deletion(-)
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
index e2fbfb4211..c442be0728 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
@@ -16,4 +16,5 @@ romstage-y += setup_wdb.c
|
||||
romstage-y += spd_bitmunching.c
|
||||
romstage-y += testing_io.c
|
||||
romstage-y += timings_refresh.c
|
||||
+romstage-y += train_read_mpr.c
|
||||
romstage-y += train_receive_enable.c
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
index 7d444659c3..264d1468f5 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
@@ -61,6 +61,7 @@ static const struct task_entry cold_boot[] = {
|
||||
{ do_jedec_init, true, "JEDECINIT", },
|
||||
{ pre_training, true, "PRETRAIN", },
|
||||
{ train_receive_enable, true, "RCVET", },
|
||||
+ { train_read_mpr, true, "RDMPRT", },
|
||||
};
|
||||
|
||||
/* Return a generic stepping value to make stepping checks simpler */
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index 500fc28909..a7551ad63c 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -27,6 +27,8 @@
|
||||
/* Always use 12 legs for emphasis (not trained) */
|
||||
#define TXEQFULLDRV (3 << 4)
|
||||
|
||||
+#define LOOPCOUNT_INFINITE 0xff
|
||||
+
|
||||
/* DDR3 mode register bits */
|
||||
#define MR0_DLL_RESET BIT(8)
|
||||
|
||||
@@ -212,6 +214,7 @@ enum raminit_status {
|
||||
RAMINIT_STATUS_POLL_TIMEOUT,
|
||||
RAMINIT_STATUS_REUT_ERROR,
|
||||
RAMINIT_STATUS_RCVEN_FAILURE,
|
||||
+ RAMINIT_STATUS_RMPR_FAILURE,
|
||||
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
|
||||
};
|
||||
|
||||
@@ -435,6 +438,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
|
||||
enum raminit_status configure_memory_map(struct sysinfo *ctrl);
|
||||
enum raminit_status do_jedec_init(struct sysinfo *ctrl);
|
||||
enum raminit_status train_receive_enable(struct sysinfo *ctrl);
|
||||
+enum raminit_status train_read_mpr(struct sysinfo *ctrl);
|
||||
|
||||
void configure_timings(struct sysinfo *ctrl);
|
||||
void configure_refresh(struct sysinfo *ctrl);
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
|
||||
new file mode 100644
|
||||
index 0000000000..0225e1a384
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
|
||||
@@ -0,0 +1,240 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <commonlib/clamp.h>
|
||||
+#include <console/console.h>
|
||||
+#include <delay.h>
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+#include <types.h>
|
||||
+
|
||||
+#include "raminit_native.h"
|
||||
+#include "ranges.h"
|
||||
+
|
||||
+#define RMPR_START (-32)
|
||||
+#define RMPR_STOP (32)
|
||||
+#define RMPR_STEP 1
|
||||
+
|
||||
+#define RMPR_MIN_WIDTH 12
|
||||
+
|
||||
+#define RMPR_PLOT RAM_DEBUG
|
||||
+
|
||||
+/*
|
||||
+ * Clear rx_training_mode. For LPDDR, we first need to disable odt_samp_extend_en,
|
||||
+ * then disable rx_training_mode, and finally re-enable odt_samp_extend_en.
|
||||
+ */
|
||||
+static void clear_rx_training_mode(struct sysinfo *ctrl, const uint8_t channel)
|
||||
+{
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ mchbar_write32(DQ_CONTROL_2(channel, byte), ctrl->dq_control_2[channel][byte]);
|
||||
+
|
||||
+ if (ctrl->lpddr) {
|
||||
+ union ddr_data_control_0_reg data_control_0 = {
|
||||
+ .raw = mchbar_read32(DDR_DATA_ch_CONTROL_0(channel)),
|
||||
+ };
|
||||
+ data_control_0.odt_samp_extend_en = 0;
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
|
||||
+ tick_delay(1);
|
||||
+ data_control_0.rx_training_mode = 0;
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
|
||||
+ tick_delay(1);
|
||||
+ }
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
|
||||
+}
|
||||
+
|
||||
+static void set_rxdqs_edges_to_midpoint(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ update_rxt(ctrl, channel, rank, byte, RXT_RXDQS_BOTH, 32);
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void enter_mpr_train_ddr_mode(struct sysinfo *ctrl, const uint8_t rank)
|
||||
+{
|
||||
+ /* Program MR3 and mask RAS/WE to prevent scheduler from issuing non-read commands */
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ if (!ctrl->lpddr)
|
||||
+ reut_issue_mrs(ctrl, channel, BIT(rank), 3, 1 << 2);
|
||||
+
|
||||
+ union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
|
||||
+ .raw = mchbar_read32(REUT_ch_MISC_ODT_CTRL(channel)),
|
||||
+ };
|
||||
+ reut_misc_odt_ctrl.mpr_train_ddr_on = 1;
|
||||
+ mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void leave_mpr_train_ddr_mode(struct sysinfo *ctrl, const uint8_t rank)
|
||||
+{
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ /*
|
||||
+ * The mpr_train_ddr_on bit will force a special command.
|
||||
+ * Therefore, clear it before issuing the MRS command.
|
||||
+ */
|
||||
+ union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
|
||||
+ .raw = mchbar_read32(REUT_ch_MISC_ODT_CTRL(channel)),
|
||||
+ };
|
||||
+ reut_misc_odt_ctrl.mpr_train_ddr_on = 0;
|
||||
+ mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
|
||||
+ if (!ctrl->lpddr)
|
||||
+ reut_issue_mrs(ctrl, channel, BIT(rank), 3, 0 << 2);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+enum raminit_status train_read_mpr(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ set_rxdqs_edges_to_midpoint(ctrl);
|
||||
+ clear_data_offset_train_all(ctrl);
|
||||
+ setup_io_test_mpr(ctrl, ctrl->chanmap, LOOPCOUNT_INFINITE, NSOE);
|
||||
+ enum raminit_status status = RAMINIT_STATUS_SUCCESS;
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (!does_rank_exist(ctrl, rank))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Rank %u\n", rank);
|
||||
+ printk(RMPR_PLOT, "Channel");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(RMPR_PLOT, "\t%u\t\t", channel);
|
||||
+ }
|
||||
+ printk(RMPR_PLOT, "\nByte");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(RMPR_PLOT, "\t");
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ printk(RMPR_PLOT, "%u ", byte);
|
||||
+ }
|
||||
+ enter_mpr_train_ddr_mode(ctrl, rank);
|
||||
+ struct linear_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
|
||||
+ select_reut_ranks(ctrl, channel, BIT(rank));
|
||||
+
|
||||
+ printk(RMPR_PLOT, "\nDqsDelay\n");
|
||||
+ int8_t dqs_delay;
|
||||
+ for (dqs_delay = RMPR_START; dqs_delay < RMPR_STOP; dqs_delay += RMPR_STEP) {
|
||||
+ printk(RMPR_PLOT, "% 5d", dqs_delay);
|
||||
+ const enum regfile_mode regfile = REG_FILE_USE_START;
|
||||
+ change_1d_margin_multicast(ctrl, RdT, dqs_delay, 0, false, regfile);
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ union ddr_data_control_2_reg data_control_2 = {
|
||||
+ .raw = ctrl->dq_control_2[channel][byte],
|
||||
+ };
|
||||
+ data_control_2.force_bias_on = 1;
|
||||
+ data_control_2.force_rx_on = 1;
|
||||
+ data_control_2.leaker_comp = 0;
|
||||
+ mchbar_write32(DQ_CONTROL_2(channel, byte),
|
||||
+ data_control_2.raw);
|
||||
+ }
|
||||
+ union ddr_data_control_0_reg data_control_0 = {
|
||||
+ .raw = ctrl->dq_control_0[channel],
|
||||
+ };
|
||||
+ data_control_0.rx_training_mode = 1;
|
||||
+ data_control_0.force_odt_on = !ctrl->lpddr;
|
||||
+ data_control_0.en_read_preamble = 0;
|
||||
+ data_control_0.odt_samp_extend_en = ctrl->lpddr;
|
||||
+ const uint32_t reg_offset = DDR_DATA_ch_CONTROL_0(channel);
|
||||
+ mchbar_write32(reg_offset, data_control_0.raw);
|
||||
+ }
|
||||
+ run_mpr_io_test(false);
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(RMPR_PLOT, "\t");
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ uint32_t fb = get_data_train_feedback(channel, byte);
|
||||
+ const bool pass = fb == 1;
|
||||
+ printk(RMPR_PLOT, pass ? ". " : "# ");
|
||||
+ linear_record_pass(
|
||||
+ ®ion_data[channel][byte],
|
||||
+ pass,
|
||||
+ dqs_delay,
|
||||
+ RMPR_START,
|
||||
+ RMPR_STEP);
|
||||
+ }
|
||||
+ }
|
||||
+ printk(RMPR_PLOT, "\n");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ clear_rx_training_mode(ctrl, channel);
|
||||
+ }
|
||||
+ io_reset();
|
||||
+ }
|
||||
+ printk(RMPR_PLOT, "\n");
|
||||
+ leave_mpr_train_ddr_mode(ctrl, rank);
|
||||
+ clear_data_offset_train_all(ctrl);
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\tRxDqsPN\n",
|
||||
+ channel, rank);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ struct linear_train_data *data = ®ion_data[channel][byte];
|
||||
+ const int32_t lwidth = range_width(data->largest);
|
||||
+ if (lwidth <= RMPR_MIN_WIDTH) {
|
||||
+ printk(BIOS_ERR,
|
||||
+ "Bad eye (lwidth %d <= min %d) for byte %u\n",
|
||||
+ lwidth, RMPR_MIN_WIDTH, byte);
|
||||
+ status = RAMINIT_STATUS_RMPR_FAILURE;
|
||||
+ }
|
||||
+ /*
|
||||
+ * The MPR center may not be ideal on certain platforms for
|
||||
+ * unknown reasons. If so, adjust it with a magical number.
|
||||
+ * For Haswell, the magical number is zero. Hell knows why.
|
||||
+ */
|
||||
+ const int32_t center = range_center(data->largest);
|
||||
+ ctrl->rxdqsp[channel][rank][byte] = center - RMPR_START;
|
||||
+ ctrl->rxdqsn[channel][rank][byte] = center - RMPR_START;
|
||||
+ printk(BIOS_DEBUG, " B%u: \t%d\t%d\t%d\t%d\t%u\n", byte,
|
||||
+ data->largest.start, data->largest.end, lwidth,
|
||||
+ center, ctrl->rxdqsp[channel][rank][byte]);
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * Now program the DQS center values on populated ranks. data is taken from
|
||||
+ * the host struct. We need to do it after all ranks are trained, because we
|
||||
+ * need to keep the same DQS value on all ranks during the training procedure.
|
||||
+ */
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
|
||||
+ }
|
||||
+ }
|
||||
+ change_1d_margin_multicast(ctrl, RdT, 0, 0, false, REG_FILE_USE_CURRENT);
|
||||
+ io_reset();
|
||||
+ return status;
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
index 0acafbc826..6a31d3a32c 100644
|
||||
--- a/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
@@ -122,7 +122,7 @@
|
||||
#define REUT_ch_ERR_DATA_MASK(ch) _MCMAIN_C(0x40d8, ch)
|
||||
|
||||
#define REUT_ch_MISC_CKE_CTRL(ch) _MCMAIN_C(0x4190, ch)
|
||||
-
|
||||
+#define REUT_ch_MISC_ODT_CTRL(ch) _MCMAIN_C(0x4194, ch)
|
||||
#define REUT_ch_MISC_PAT_CADB_CTRL(ch) _MCMAIN_C(0x4198, ch)
|
||||
#define REUT_ch_PAT_CADB_MRS(ch) _MCMAIN_C(0x419c, ch)
|
||||
#define REUT_ch_PAT_CADB_MUX_CTRL(ch) _MCMAIN_C(0x41a0, ch)
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,688 @@
|
||||
From f091b29ba192afe0eb90a737613ec0735c876830 Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sun, 8 May 2022 12:56:04 +0200
|
||||
Subject: [PATCH 14/15] haswell NRI: Add write leveling
|
||||
|
||||
Implement JEDEC write leveling, which is done in two steps. The first
|
||||
step uses the JEDEC procedure to do "fine" write leveling, i.e. align
|
||||
the DQS phase to the clock signal. The second step performs a regular
|
||||
read-write test to correct "coarse" cycle errors.
|
||||
|
||||
Change-Id: I27678523fe22c38173a688e2a4751c259a20f009
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
.../intel/haswell/native_raminit/Makefile.mk | 1 +
|
||||
.../haswell/native_raminit/raminit_main.c | 1 +
|
||||
.../haswell/native_raminit/raminit_native.h | 10 +
|
||||
.../train_jedec_write_leveling.c | 580 ++++++++++++++++++
|
||||
.../intel/haswell/registers/mchbar.h | 2 +
|
||||
5 files changed, 594 insertions(+)
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
index c442be0728..40c2f5e014 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
@@ -16,5 +16,6 @@ romstage-y += setup_wdb.c
|
||||
romstage-y += spd_bitmunching.c
|
||||
romstage-y += testing_io.c
|
||||
romstage-y += timings_refresh.c
|
||||
+romstage-y += train_jedec_write_leveling.c
|
||||
romstage-y += train_read_mpr.c
|
||||
romstage-y += train_receive_enable.c
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
index 264d1468f5..1ff23be615 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
@@ -62,6 +62,7 @@ static const struct task_entry cold_boot[] = {
|
||||
{ pre_training, true, "PRETRAIN", },
|
||||
{ train_receive_enable, true, "RCVET", },
|
||||
{ train_read_mpr, true, "RDMPRT", },
|
||||
+ { train_jedec_write_leveling, true, "JWRL", },
|
||||
};
|
||||
|
||||
/* Return a generic stepping value to make stepping checks simpler */
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index a7551ad63c..666b233c45 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -59,6 +59,9 @@
|
||||
/* Specified in PI ticks. 64 PI ticks == 1 qclk */
|
||||
#define tDQSCK_DRIFT 64
|
||||
|
||||
+/* Maximum additional latency */
|
||||
+#define MAX_ADD_DELAY 2
|
||||
+
|
||||
enum margin_parameter {
|
||||
RcvEna,
|
||||
RdT,
|
||||
@@ -215,6 +218,7 @@ enum raminit_status {
|
||||
RAMINIT_STATUS_REUT_ERROR,
|
||||
RAMINIT_STATUS_RCVEN_FAILURE,
|
||||
RAMINIT_STATUS_RMPR_FAILURE,
|
||||
+ RAMINIT_STATUS_JWRL_FAILURE,
|
||||
RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
|
||||
};
|
||||
|
||||
@@ -380,6 +384,11 @@ static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint
|
||||
return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte));
|
||||
}
|
||||
|
||||
+static inline uint16_t get_byte_group_errors(const uint8_t channel)
|
||||
+{
|
||||
+ return mchbar_read32(4 + REUT_ch_ERR_MISC_STATUS(channel)) & 0x1ff;
|
||||
+}
|
||||
+
|
||||
/* Number of ticks to wait in units of 69.841279 ns (citation needed) */
|
||||
static inline void tick_delay(const uint32_t delay)
|
||||
{
|
||||
@@ -439,6 +448,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
|
||||
enum raminit_status do_jedec_init(struct sysinfo *ctrl);
|
||||
enum raminit_status train_receive_enable(struct sysinfo *ctrl);
|
||||
enum raminit_status train_read_mpr(struct sysinfo *ctrl);
|
||||
+enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
|
||||
|
||||
void configure_timings(struct sysinfo *ctrl);
|
||||
void configure_refresh(struct sysinfo *ctrl);
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
|
||||
new file mode 100644
|
||||
index 0000000000..1ba28a3bd4
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
|
||||
@@ -0,0 +1,580 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <assert.h>
|
||||
+#include <console/console.h>
|
||||
+#include <delay.h>
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+#include <types.h>
|
||||
+
|
||||
+#include "raminit_native.h"
|
||||
+#include "ranges.h"
|
||||
+
|
||||
+#define JWLC_PLOT RAM_DEBUG
|
||||
+#define JWRL_PLOT RAM_DEBUG
|
||||
+
|
||||
+static void reset_dram_dll(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
|
||||
+{
|
||||
+ reut_issue_mrs(ctrl, channel, BIT(rank), 0, ctrl->mr0[channel][rank] | MR0_DLL_RESET);
|
||||
+}
|
||||
+
|
||||
+static void program_wdb_pattern(struct sysinfo *ctrl, const bool invert)
|
||||
+{
|
||||
+ /* Pattern to keep DQ-DQS simple but detect any failures. Same as NHM/WSM. */
|
||||
+ const uint8_t pat[4][2] = {
|
||||
+ { 0x00, 0xff },
|
||||
+ { 0xff, 0x00 },
|
||||
+ { 0xc3, 0x3c },
|
||||
+ { 0x3c, 0xc3 },
|
||||
+ };
|
||||
+ const uint8_t pmask[2][8] = {
|
||||
+ { 0, 0, 1, 1, 1, 1, 0, 0 },
|
||||
+ { 1, 1, 0, 0, 0, 0, 1, 1 },
|
||||
+ };
|
||||
+ for (uint8_t s = 0; s < ARRAY_SIZE(pat); s++)
|
||||
+ write_wdb_fixed_pat(ctrl, pat[s], pmask[invert], ARRAY_SIZE(pmask[invert]), s);
|
||||
+}
|
||||
+
|
||||
+static int16_t set_add_delay(uint32_t *add_delay, uint8_t rank, int8_t target_off)
|
||||
+{
|
||||
+ const uint8_t shift = rank * 2;
|
||||
+ if (target_off > MAX_ADD_DELAY) {
|
||||
+ *add_delay &= ~(3 << shift);
|
||||
+ *add_delay |= MAX_ADD_DELAY << shift;
|
||||
+ return 128 * (target_off - MAX_ADD_DELAY);
|
||||
+ } else if (target_off < 0) {
|
||||
+ *add_delay &= ~(3 << shift);
|
||||
+ *add_delay |= 0 << shift;
|
||||
+ return 128 * target_off;
|
||||
+ } else {
|
||||
+ *add_delay &= ~(3 << shift);
|
||||
+ *add_delay |= target_off << shift;
|
||||
+ return 0;
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static enum raminit_status train_jedec_write_leveling_cleanup(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ const struct reut_box reut_addr = {
|
||||
+ .col = {
|
||||
+ .start = 0,
|
||||
+ .stop = 1023,
|
||||
+ .inc_val = 1,
|
||||
+ },
|
||||
+ };
|
||||
+ const struct wdb_pat wdb_pattern = {
|
||||
+ .start_ptr = 0,
|
||||
+ .stop_ptr = 3,
|
||||
+ .inc_rate = 1,
|
||||
+ .dq_pattern = BASIC_VA,
|
||||
+ };
|
||||
+ const int8_t offsets[] = { 0, 1, -1, 2, 3 };
|
||||
+ const int8_t dq_offsets[] = { 0, -10, 10, -5, 5, -15, 15 };
|
||||
+ const uint8_t dq_offset_max = ARRAY_SIZE(dq_offsets);
|
||||
+
|
||||
+ /* Set LFSR seeds to be sequential */
|
||||
+ program_wdb_lfsr(ctrl, true);
|
||||
+ setup_io_test(
|
||||
+ ctrl,
|
||||
+ ctrl->chanmap,
|
||||
+ PAT_WR_RD,
|
||||
+ 2,
|
||||
+ 4,
|
||||
+ &reut_addr,
|
||||
+ NSOE,
|
||||
+ &wdb_pattern,
|
||||
+ 0,
|
||||
+ 0);
|
||||
+
|
||||
+ const union reut_pat_wdb_cl_mux_cfg_reg reut_wdb_cl_mux_cfg = {
|
||||
+ .mux_0_control = REUT_MUX_BTBUFFER,
|
||||
+ .mux_1_control = REUT_MUX_BTBUFFER,
|
||||
+ .mux_2_control = REUT_MUX_BTBUFFER,
|
||||
+ .ecc_data_source_sel = 1,
|
||||
+ };
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_CFG(channel), reut_wdb_cl_mux_cfg.raw);
|
||||
+ }
|
||||
+
|
||||
+ int8_t byte_off[NUM_CHANNELS][NUM_LANES] = { 0 };
|
||||
+ uint32_t add_delay[NUM_CHANNELS] = { 0 };
|
||||
+ enum raminit_status status = RAMINIT_STATUS_SUCCESS;
|
||||
+ bool invert = false;
|
||||
+ const uint16_t valid_byte_mask = BIT(ctrl->lanes) - 1;
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ uint8_t chanmask = 0;
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
|
||||
+ chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
|
||||
+
|
||||
+ if (!chanmask)
|
||||
+ continue;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "Rank %u\n", rank);
|
||||
+ printk(JWLC_PLOT, "Channel");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(JWLC_PLOT, "\t\t%u\t", channel);
|
||||
+ }
|
||||
+ printk(JWLC_PLOT, "\nByte\t");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(JWLC_PLOT, "\t");
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ printk(JWLC_PLOT, "%u ", byte);
|
||||
+ }
|
||||
+ printk(JWLC_PLOT, "\nDelay DqOffset");
|
||||
+ bool done = false;
|
||||
+ int8_t byte_sum[NUM_CHANNELS] = { 0 };
|
||||
+ uint16_t byte_pass[NUM_CHANNELS] = { 0 };
|
||||
+ for (uint8_t off = 0; off < ARRAY_SIZE(offsets); off++) {
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ const int16_t global_byte_off =
|
||||
+ set_add_delay(&add_delay[channel], rank, offsets[off]);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ update_txt(ctrl, channel, rank, byte, TXT_DQDQS_OFF,
|
||||
+ global_byte_off);
|
||||
+ }
|
||||
+ mchbar_write32(SC_WR_ADD_DELAY_ch(channel),
|
||||
+ add_delay[channel]);
|
||||
+ }
|
||||
+ /* Reset FIFOs and DRAM DLL (Micron workaround) */
|
||||
+ if (!ctrl->lpddr) {
|
||||
+ io_reset();
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ reset_dram_dll(ctrl, channel, rank);
|
||||
+ }
|
||||
+ udelay(1);
|
||||
+ }
|
||||
+ for (uint8_t dq_offset = 0; dq_offset < dq_offset_max; dq_offset++) {
|
||||
+ printk(JWLC_PLOT, "\n% 3d\t% 3d",
|
||||
+ offsets[off], dq_offsets[dq_offset]);
|
||||
+ change_1d_margin_multicast(
|
||||
+ ctrl,
|
||||
+ WrT,
|
||||
+ dq_offsets[dq_offset],
|
||||
+ rank,
|
||||
+ false,
|
||||
+ REG_FILE_USE_RANK);
|
||||
+
|
||||
+ /*
|
||||
+ * Re-program the WDB pattern. Change the pattern
|
||||
+ * for the next test to avoid false pass issues.
|
||||
+ */
|
||||
+ program_wdb_pattern(ctrl, invert);
|
||||
+ invert = !invert;
|
||||
+ run_io_test(ctrl, chanmask, BASIC_VA, true);
|
||||
+ done = true;
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(JWLC_PLOT, "\t");
|
||||
+ uint16_t result = get_byte_group_errors(channel);
|
||||
+ result &= valid_byte_mask;
|
||||
+
|
||||
+ /* Skip bytes that have failed or already passed */
|
||||
+ const uint16_t skip_me = result | byte_pass[channel];
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ const bool pass = result & BIT(byte);
|
||||
+ printk(JWLC_PLOT, pass ? "# " : ". ");
|
||||
+ if (skip_me & BIT(byte))
|
||||
+ continue;
|
||||
+
|
||||
+ byte_pass[channel] |= BIT(byte);
|
||||
+ byte_off[channel][byte] = offsets[off];
|
||||
+ byte_sum[channel] += offsets[off];
|
||||
+ }
|
||||
+ if (byte_pass[channel] != valid_byte_mask)
|
||||
+ done = false;
|
||||
+ }
|
||||
+ if (done)
|
||||
+ break;
|
||||
+ }
|
||||
+ if (done)
|
||||
+ break;
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n\n");
|
||||
+ if (!done) {
|
||||
+ printk(BIOS_ERR, "JWLC: Could not find a pass for all bytes\n");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(BIOS_ERR, "Channel %u, rank %u fail:", channel, rank);
|
||||
+ const uint16_t passing_mask = byte_pass[channel];
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ if (BIT(byte) & passing_mask)
|
||||
+ continue;
|
||||
+
|
||||
+ printk(BIOS_ERR, " %u", byte);
|
||||
+ }
|
||||
+ printk(BIOS_ERR, "\n");
|
||||
+ }
|
||||
+ status = RAMINIT_STATUS_JWRL_FAILURE;
|
||||
+ break;
|
||||
+ }
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ /* Refine target offset to make sure it works for all bytes */
|
||||
+ int8_t target_off = DIV_ROUND_CLOSEST(byte_sum[channel], ctrl->lanes);
|
||||
+ int16_t global_byte_off = 0;
|
||||
+ uint8_t all_good_loops = 0;
|
||||
+ bool all_good = 0;
|
||||
+ while (!all_good) {
|
||||
+ global_byte_off =
|
||||
+ set_add_delay(&add_delay[channel], rank, target_off);
|
||||
+ all_good = true;
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ int16_t local_offset;
|
||||
+ local_offset = byte_off[channel][byte] - target_off;
|
||||
+ local_offset = local_offset * 128 + global_byte_off;
|
||||
+ const uint16_t tx_dq = ctrl->tx_dq[channel][rank][byte];
|
||||
+ if (tx_dq + local_offset >= (512 - 64)) {
|
||||
+ all_good = false;
|
||||
+ all_good_loops++;
|
||||
+ target_off++;
|
||||
+ break;
|
||||
+ }
|
||||
+ const uint16_t txdqs = ctrl->tx_dq[channel][rank][byte];
|
||||
+ if (txdqs + local_offset < 96) {
|
||||
+ all_good = false;
|
||||
+ all_good_loops++;
|
||||
+ target_off--;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+ /* Avoid an infinite loop */
|
||||
+ if (all_good_loops > 3)
|
||||
+ break;
|
||||
+ }
|
||||
+ if (!all_good) {
|
||||
+ printk(BIOS_ERR, "JWLC: Target offset refining failed\n");
|
||||
+ status = RAMINIT_STATUS_JWRL_FAILURE;
|
||||
+ break;
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "C%u.R%u: Offset\tFinalEdge\n", channel, rank);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ int16_t local_offset;
|
||||
+ local_offset = byte_off[channel][byte] - target_off;
|
||||
+ local_offset = local_offset * 128 + global_byte_off;
|
||||
+ ctrl->tx_dq[channel][rank][byte] += local_offset;
|
||||
+ ctrl->txdqs[channel][rank][byte] += local_offset;
|
||||
+ update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
|
||||
+ printk(BIOS_DEBUG, " B%u: %d\t%d\n", byte, local_offset,
|
||||
+ ctrl->txdqs[channel][rank][byte]);
|
||||
+ }
|
||||
+ mchbar_write32(SC_WR_ADD_DELAY_ch(channel), add_delay[channel]);
|
||||
+ if (!ctrl->lpddr) {
|
||||
+ reset_dram_dll(ctrl, channel, rank);
|
||||
+ udelay(1);
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ }
|
||||
+
|
||||
+ /* Restore WDB after test */
|
||||
+ write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
|
||||
+ program_wdb_lfsr(ctrl, false);
|
||||
+ mchbar_write32(DDR_DATA_OFFSET_TRAIN, 0);
|
||||
+
|
||||
+ /** TODO: Do full JEDEC init instead? **/
|
||||
+ io_reset();
|
||||
+ return status;
|
||||
+}
|
||||
+
|
||||
+static enum raminit_status verify_wl_width(const int32_t lwidth)
|
||||
+{
|
||||
+ if (lwidth <= 32) {
|
||||
+ /* Check if width is valid */
|
||||
+ printk(BIOS_ERR, "WrLevel: Width region (%d) too small\n", lwidth);
|
||||
+ return RAMINIT_STATUS_JWRL_FAILURE;
|
||||
+ }
|
||||
+ if (lwidth >= 96) {
|
||||
+ /* Since we're calibrating a phase, a too large region is a problem */
|
||||
+ printk(BIOS_ERR, "WrLevel: Width region (%d) too large\n", lwidth);
|
||||
+ return RAMINIT_STATUS_JWRL_FAILURE;
|
||||
+ }
|
||||
+ return 0;
|
||||
+}
|
||||
+
|
||||
+enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ /*
|
||||
+ * Enabling WL mode causes DQS to toggle for 1024 QCLK.
|
||||
+ * Wait for this to stop. Round up to nearest microsecond.
|
||||
+ */
|
||||
+ const bool wl_long_delay = ctrl->lpddr;
|
||||
+ const uint32_t dqs_toggle_time = wl_long_delay ? 2048 : 1024;
|
||||
+ const uint32_t wait_time_us = DIV_ROUND_UP(ctrl->qclkps * dqs_toggle_time, 1000 * 1000);
|
||||
+
|
||||
+ const uint16_t wl_start = 192;
|
||||
+ const uint16_t wl_stop = 192 + 128;
|
||||
+ const uint16_t wl_step = 2;
|
||||
+
|
||||
+ /* Do not use cached MR values */
|
||||
+ const bool save_restore_mrs = ctrl->restore_mrs;
|
||||
+ ctrl->restore_mrs = 0;
|
||||
+
|
||||
+ /* Propagate delay values (without a write command) */
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ /* Propagate delay values from rank 0 to prevent assertion failures in RTL */
|
||||
+ union ddr_data_control_0_reg data_control_0 = {
|
||||
+ .raw = ctrl->dq_control_0[channel],
|
||||
+ };
|
||||
+ data_control_0.read_rf_rd = 0;
|
||||
+ data_control_0.read_rf_wr = 1;
|
||||
+ data_control_0.read_rf_rank = 0;
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ union ddr_data_control_2_reg data_control_2 = {
|
||||
+ .raw = ctrl->dq_control_2[channel][byte],
|
||||
+ };
|
||||
+ data_control_2.force_bias_on = 1;
|
||||
+ data_control_2.force_rx_on = 0;
|
||||
+ data_control_2.wl_long_delay = wl_long_delay;
|
||||
+ mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (ctrl->lpddr)
|
||||
+ die("%s: Missing LPDDR support\n", __func__);
|
||||
+
|
||||
+ if (!ctrl->lpddr)
|
||||
+ ddr3_program_mr1(ctrl, 0, 1);
|
||||
+
|
||||
+ enum raminit_status status = RAMINIT_STATUS_SUCCESS;
|
||||
+ struct phase_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (!does_rank_exist(ctrl, rank))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ /** TODO: Differs for LPDDR **/
|
||||
+ uint16_t mr1reg = ctrl->mr1[channel][rank];
|
||||
+ mr1reg &= ~MR1_QOFF_ENABLE;
|
||||
+ mr1reg |= MR1_WL_ENABLE;
|
||||
+ if (is_hsw_ult()) {
|
||||
+ mr1reg &= ~RTTNOM_MASK;
|
||||
+ mr1reg |= encode_ddr3_rttnom(120);
|
||||
+ } else if (ctrl->dpc[channel] == 2) {
|
||||
+ mr1reg &= ~RTTNOM_MASK;
|
||||
+ mr1reg |= encode_ddr3_rttnom(60);
|
||||
+ }
|
||||
+ reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
|
||||
+
|
||||
+ /* Assert ODT for myself */
|
||||
+ uint8_t odt_matrix = BIT(rank);
|
||||
+ if (ctrl->dpc[channel] == 2) {
|
||||
+ /* Assert ODT for non-target DIMM */
|
||||
+ const uint8_t other_dimm = ((rank + 2) / 2) & 1;
|
||||
+ odt_matrix |= BIT(2 * other_dimm);
|
||||
+ }
|
||||
+
|
||||
+ union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
|
||||
+ .raw = 0,
|
||||
+ };
|
||||
+ if (ctrl->lpddr) {
|
||||
+ /* Only one ODT pin for ULT */
|
||||
+ reut_misc_odt_ctrl.odt_on = 1;
|
||||
+ reut_misc_odt_ctrl.odt_override = 1;
|
||||
+ } else if (!is_hsw_ult()) {
|
||||
+ reut_misc_odt_ctrl.odt_on = odt_matrix;
|
||||
+ reut_misc_odt_ctrl.odt_override = 0xf;
|
||||
+ }
|
||||
+ mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
|
||||
+ }
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ /*
|
||||
+ * Enable write leveling mode in DDR and propagate delay
|
||||
+ * values (without a write command). Stay in WL mode.
|
||||
+ */
|
||||
+ union ddr_data_control_0_reg data_control_0 = {
|
||||
+ .raw = ctrl->dq_control_0[channel],
|
||||
+ };
|
||||
+ data_control_0.wl_training_mode = 1;
|
||||
+ data_control_0.tx_pi_on = 1;
|
||||
+ data_control_0.read_rf_rd = 0;
|
||||
+ data_control_0.read_rf_wr = 1;
|
||||
+ data_control_0.read_rf_rank = rank;
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\nRank %u\n", rank);
|
||||
+ printk(JWRL_PLOT, "Channel\t");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(JWRL_PLOT, "%u", channel);
|
||||
+ if (channel > 0)
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ printk(JWRL_PLOT, "\t");
|
||||
+ }
|
||||
+ printk(JWRL_PLOT, "\nByte");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ printk(JWRL_PLOT, "\t%u", byte);
|
||||
+ }
|
||||
+ printk(JWRL_PLOT, "\nWlDelay");
|
||||
+ for (uint16_t wl_delay = wl_start; wl_delay < wl_stop; wl_delay += wl_step) {
|
||||
+ printk(JWRL_PLOT, "\n %3u:", wl_delay);
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ update_txt(ctrl, channel, rank, byte, TXT_TXDQS,
|
||||
+ wl_delay);
|
||||
+ }
|
||||
+ }
|
||||
+ /* Wait for the first burst to finish */
|
||||
+ if (wl_delay == wl_start)
|
||||
+ udelay(wait_time_us);
|
||||
+
|
||||
+ io_reset();
|
||||
+ udelay(wait_time_us);
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ const uint32_t feedback =
|
||||
+ get_data_train_feedback(channel, byte);
|
||||
+ const bool pass = (feedback & 0x1ff) >= 16;
|
||||
+ printk(JWRL_PLOT, "\t%c%u", pass ? '.' : '#', feedback);
|
||||
+ phase_record_pass(
|
||||
+ ®ion_data[channel][byte],
|
||||
+ pass,
|
||||
+ wl_delay,
|
||||
+ wl_start,
|
||||
+ wl_step);
|
||||
+ }
|
||||
+ }
|
||||
+ }
|
||||
+ printk(JWRL_PLOT, "\n");
|
||||
+ printk(BIOS_DEBUG, "\n\tInitSt\tInitEn\tCurrSt\tCurrEn\tLargSt\tLargEn\n");
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "C%u\n", channel);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ struct phase_train_data *data = ®ion_data[channel][byte];
|
||||
+
|
||||
+ phase_append_initial_to_current(data, wl_start, wl_step);
|
||||
+ printk(BIOS_DEBUG, " B%u:\t%d\t%d\t%d\t%d\t%d\t%d\n",
|
||||
+ byte,
|
||||
+ data->initial.start,
|
||||
+ data->initial.end,
|
||||
+ data->current.start,
|
||||
+ data->current.end,
|
||||
+ data->largest.start,
|
||||
+ data->largest.end);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ /*
|
||||
+ * Clean up after test. Very coarsely adjust for
|
||||
+ * any cycle errors. Program values for TxDQS.
|
||||
+ */
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ /* Clear ODT before MRS (JEDEC spec) */
|
||||
+ mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), 0);
|
||||
+
|
||||
+ /** TODO: Differs for LPDDR **/
|
||||
+ const uint16_t mr1reg = ctrl->mr1[channel][rank] | MR1_QOFF_ENABLE;
|
||||
+ reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
|
||||
+
|
||||
+ printk(BIOS_DEBUG, "\nC%u.R%u: LftEdge Width\n", channel, rank);
|
||||
+ const bool rank_x16 = ctrl->dimms[channel][rank / 2].data.width == 16;
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ struct phase_train_data *data = ®ion_data[channel][byte];
|
||||
+ const int32_t lwidth = range_width(data->largest);
|
||||
+ int32_t tx_start = data->largest.start;
|
||||
+ printk(BIOS_DEBUG, " B%u: %d\t%d\n", byte, tx_start, lwidth);
|
||||
+ status = verify_wl_width(lwidth);
|
||||
+ if (status) {
|
||||
+ printk(BIOS_ERR,
|
||||
+ "WrLevel problems on channel %u, byte %u\n",
|
||||
+ channel, byte);
|
||||
+ goto clean_up;
|
||||
+ }
|
||||
+
|
||||
+ /* Align byte pairs if DIMM is x16 */
|
||||
+ if (rank_x16 && (byte & 1)) {
|
||||
+ const struct phase_train_data *const ref_data =
|
||||
+ ®ion_data[channel][byte - 1];
|
||||
+
|
||||
+ if (tx_start > ref_data->largest.start + 64)
|
||||
+ tx_start -= 128;
|
||||
+
|
||||
+ if (tx_start < ref_data->largest.start - 64)
|
||||
+ tx_start += 128;
|
||||
+ }
|
||||
+
|
||||
+ /* Fix for b4618067 - need to add 1 QCLK to DQS PI */
|
||||
+ if (is_hsw_ult())
|
||||
+ tx_start += 64;
|
||||
+
|
||||
+ assert(tx_start >= 0);
|
||||
+ ctrl->txdqs[channel][rank][byte] = tx_start;
|
||||
+ ctrl->tx_dq[channel][rank][byte] = tx_start + 32;
|
||||
+ update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
|
||||
+ }
|
||||
+ }
|
||||
+ printk(BIOS_DEBUG, "\n");
|
||||
+ }
|
||||
+
|
||||
+clean_up:
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ mchbar_write32(DQ_CONTROL_2(channel, byte),
|
||||
+ ctrl->dq_control_2[channel][byte]);
|
||||
+ }
|
||||
+ }
|
||||
+ if (!ctrl->lpddr)
|
||||
+ ddr3_program_mr1(ctrl, 0, 0);
|
||||
+
|
||||
+ ctrl->restore_mrs = save_restore_mrs;
|
||||
+
|
||||
+ if (status)
|
||||
+ return status;
|
||||
+
|
||||
+ /** TODO: If this step fails and dec_wrd is set, clear it and try again **/
|
||||
+ return train_jedec_write_leveling_cleanup(ctrl);
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
index 6a31d3a32c..7c0b5a49de 100644
|
||||
--- a/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
@@ -121,6 +121,8 @@
|
||||
|
||||
#define REUT_ch_ERR_DATA_MASK(ch) _MCMAIN_C(0x40d8, ch)
|
||||
|
||||
+#define REUT_ch_ERR_MISC_STATUS(ch) _MCMAIN_C(0x40e8, ch)
|
||||
+
|
||||
#define REUT_ch_MISC_CKE_CTRL(ch) _MCMAIN_C(0x4190, ch)
|
||||
#define REUT_ch_MISC_ODT_CTRL(ch) _MCMAIN_C(0x4194, ch)
|
||||
#define REUT_ch_MISC_PAT_CADB_CTRL(ch) _MCMAIN_C(0x4198, ch)
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,570 @@
|
||||
From 94230b02f22d871af5de5c83e2efc6204394475e Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Sun, 8 May 2022 14:29:05 +0200
|
||||
Subject: [PATCH 15/15] haswell NRI: Add final raminit steps
|
||||
|
||||
Implement the remaining raminit steps. Although many training steps are
|
||||
missing, this is enough to boot on the Asrock B85M Pro4.
|
||||
|
||||
Change-Id: I94f3b65f0218d4da4fda4d84592dfd91f77f8f21
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
src/northbridge/intel/haswell/Kconfig | 4 +-
|
||||
.../intel/haswell/native_raminit/Makefile.mk | 1 +
|
||||
.../haswell/native_raminit/activate_mc.c | 388 ++++++++++++++++++
|
||||
.../haswell/native_raminit/raminit_main.c | 5 +-
|
||||
.../haswell/native_raminit/raminit_native.c | 5 +-
|
||||
.../haswell/native_raminit/raminit_native.h | 2 +
|
||||
.../haswell/native_raminit/reg_structs.h | 12 +
|
||||
.../intel/haswell/registers/mchbar.h | 7 +
|
||||
8 files changed, 416 insertions(+), 8 deletions(-)
|
||||
create mode 100644 src/northbridge/intel/haswell/native_raminit/activate_mc.c
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
|
||||
index 4b83a25bc1..c6ab27184e 100644
|
||||
--- a/src/northbridge/intel/haswell/Kconfig
|
||||
+++ b/src/northbridge/intel/haswell/Kconfig
|
||||
@@ -11,12 +11,12 @@ config NORTHBRIDGE_INTEL_HASWELL
|
||||
if NORTHBRIDGE_INTEL_HASWELL
|
||||
|
||||
config USE_NATIVE_RAMINIT
|
||||
- bool "[NOT WORKING] Use native raminit"
|
||||
+ bool "[NOT COMPLETE] Use native raminit"
|
||||
default n
|
||||
select HAVE_DEBUG_RAM_SETUP
|
||||
help
|
||||
Select if you want to use coreboot implementation of raminit rather than
|
||||
- MRC.bin. Currently incomplete and does not boot.
|
||||
+ MRC.bin. Currently incomplete and does not support S3 resume.
|
||||
|
||||
config HASWELL_VBOOT_IN_BOOTBLOCK
|
||||
depends on VBOOT
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
index 40c2f5e014..d97da72890 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
|
||||
@@ -1,5 +1,6 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-or-later
|
||||
|
||||
+romstage-y += activate_mc.c
|
||||
romstage-y += change_margin.c
|
||||
romstage-y += configure_mc.c
|
||||
romstage-y += ddr3.c
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
|
||||
new file mode 100644
|
||||
index 0000000000..78a7ad27ef
|
||||
--- /dev/null
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
|
||||
@@ -0,0 +1,388 @@
|
||||
+/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
+
|
||||
+#include <console/console.h>
|
||||
+#include <delay.h>
|
||||
+#include <device/pci_ops.h>
|
||||
+#include <northbridge/intel/haswell/haswell.h>
|
||||
+#include <timer.h>
|
||||
+#include <types.h>
|
||||
+
|
||||
+#include "raminit_native.h"
|
||||
+
|
||||
+static void update_internal_clocks_on(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ bool clocks_on = false;
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ const union ddr_data_control_1_reg data_control_1 = {
|
||||
+ .raw = ctrl->dq_control_1[channel][byte],
|
||||
+ };
|
||||
+ const int8_t o_on = data_control_1.odt_delay;
|
||||
+ const int8_t s_on = data_control_1.sense_amp_delay;
|
||||
+ const int8_t o_off = data_control_1.odt_duration;
|
||||
+ const int8_t s_off = data_control_1.sense_amp_duration;
|
||||
+ if (o_on + o_off >= 7 || s_on + s_off >= 7) {
|
||||
+ clocks_on = true;
|
||||
+ break;
|
||||
+ }
|
||||
+ }
|
||||
+ union ddr_data_control_0_reg data_control_0 = {
|
||||
+ .raw = ctrl->dq_control_0[channel],
|
||||
+ };
|
||||
+ data_control_0.internal_clocks_on = clocks_on;
|
||||
+ ctrl->dq_control_0[channel] = data_control_0.raw;
|
||||
+ mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+/* Switch off unused segments of the SDLL to save power */
|
||||
+static void update_sdll_length(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ uint8_t max_pi = 0;
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ const uint8_t rx_dqs_p = ctrl->rxdqsp[channel][rank][byte];
|
||||
+ const uint8_t rx_dqs_n = ctrl->rxdqsn[channel][rank][byte];
|
||||
+ max_pi = MAX(max_pi, MAX(rx_dqs_p, rx_dqs_n));
|
||||
+ }
|
||||
+ /* Update SDLL length for power savings */
|
||||
+ union ddr_data_control_1_reg data_control_1 = {
|
||||
+ .raw = ctrl->dq_control_1[channel][byte],
|
||||
+ };
|
||||
+ /* Calculate which segments to turn off */
|
||||
+ data_control_1.sdll_segment_disable = (7 - (max_pi >> 3)) & ~1;
|
||||
+ ctrl->dq_control_1[channel][byte] = data_control_1.raw;
|
||||
+ mchbar_write32(DQ_CONTROL_1(channel, byte), data_control_1.raw);
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+static void set_rx_clk_stg_num(struct sysinfo *ctrl, const uint8_t channel)
|
||||
+{
|
||||
+ const uint8_t rcven_drift = ctrl->lpddr ? DIV_ROUND_UP(tDQSCK_DRIFT, ctrl->qclkps) : 1;
|
||||
+ uint8_t max_rcven = 0;
|
||||
+ for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
|
||||
+ if (!rank_in_ch(ctrl, rank, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
|
||||
+ max_rcven = MAX(max_rcven, ctrl->rcven[channel][rank][byte] / 64);
|
||||
+ }
|
||||
+ const union ddr_data_control_1_reg ddr_data_control_1 = {
|
||||
+ .raw = ctrl->dq_control_1[channel][0],
|
||||
+ };
|
||||
+ const bool lpddr_long_odt = ddr_data_control_1.lpddr_long_odt_en;
|
||||
+ const uint8_t rcven_turnoff = max_rcven + 18 + 2 * rcven_drift + lpddr_long_odt;
|
||||
+ const union ddr_data_control_0_reg ddr_data_control_0 = {
|
||||
+ .raw = ctrl->dq_control_0[channel],
|
||||
+ };
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ union ddr_data_control_2_reg ddr_data_control_2 = {
|
||||
+ .raw = ctrl->dq_control_2[channel][byte],
|
||||
+ };
|
||||
+ if (ddr_data_control_0.odt_samp_extend_en) {
|
||||
+ if (ddr_data_control_2.rx_clk_stg_num < rcven_turnoff)
|
||||
+ ddr_data_control_2.rx_clk_stg_num = rcven_turnoff;
|
||||
+ } else {
|
||||
+ const int8_t o_on = ddr_data_control_1.odt_delay;
|
||||
+ const int8_t o_off = ddr_data_control_1.odt_duration;
|
||||
+ ddr_data_control_2.rx_clk_stg_num = MAX(17, o_on + o_off + 14);
|
||||
+ }
|
||||
+ ctrl->dq_control_2[channel][byte] = ddr_data_control_2.raw;
|
||||
+ mchbar_write32(DQ_CONTROL_2(channel, byte), ddr_data_control_2.raw);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+#define SELF_REFRESH_IDLE_COUNT 0x200
|
||||
+
|
||||
+static void enter_sr(void)
|
||||
+{
|
||||
+ mchbar_write32(PM_SREF_CONFIG, SELF_REFRESH_IDLE_COUNT | BIT(16));
|
||||
+ udelay(1);
|
||||
+}
|
||||
+
|
||||
+enum power_down_mode {
|
||||
+ PDM_NO_PD = 0,
|
||||
+ PDM_APD = 1,
|
||||
+ PDM_PPD = 2,
|
||||
+ PDM_PPD_DLL_OFF = 6,
|
||||
+};
|
||||
+
|
||||
+static void power_down_config(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ const enum power_down_mode pd_mode = ctrl->lpddr ? PDM_PPD : PDM_PPD_DLL_OFF;
|
||||
+ mchbar_write32(PM_PDWN_CONFIG, pd_mode << 12 | 0x40);
|
||||
+}
|
||||
+
|
||||
+static void train_power_modes_post(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ /* Adjust tCPDED and tPRPDEN */
|
||||
+ if (ctrl->mem_clock_mhz >= 933)
|
||||
+ ctrl->tc_bankrank_d[channel].tCPDED = 2;
|
||||
+
|
||||
+ if (ctrl->mem_clock_mhz >= 1066)
|
||||
+ ctrl->tc_bankrank_d[channel].tPRPDEN = 2;
|
||||
+
|
||||
+ mchbar_write32(TC_BANK_RANK_D_ch(channel), ctrl->tc_bankrank_d[channel].raw);
|
||||
+ }
|
||||
+ power_down_config(ctrl);
|
||||
+ mchbar_write32(MCDECS_CBIT, BIT(30)); /* dis_msg_clk_gate */
|
||||
+}
|
||||
+
|
||||
+static uint8_t compute_burst_end_odt_delay(const struct sysinfo *const ctrl)
|
||||
+{
|
||||
+ /* Must be disabled for LPDDR */
|
||||
+ if (ctrl->lpddr)
|
||||
+ return 0;
|
||||
+
|
||||
+ const uint8_t beod = MIN(7, DIV_ROUND_CLOSEST(14300 * 20 / 100, ctrl->qclkps));
|
||||
+ if (beod < 3)
|
||||
+ return 0;
|
||||
+
|
||||
+ if (beod < 4)
|
||||
+ return 4;
|
||||
+
|
||||
+ return beod;
|
||||
+}
|
||||
+
|
||||
+static void program_burst_end_odt_delay(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ /* Program burst_end_odt_delay - it should be zero during training steps */
|
||||
+ const uint8_t beod = compute_burst_end_odt_delay(ctrl);
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
|
||||
+ union ddr_data_control_1_reg ddr_data_control_1 = {
|
||||
+ .raw = ctrl->dq_control_1[channel][byte],
|
||||
+ };
|
||||
+ ddr_data_control_1.burst_end_odt_delay = beod;
|
||||
+ ctrl->dq_control_1[channel][byte] = ddr_data_control_1.raw;
|
||||
+ mchbar_write32(DQ_CONTROL_1(channel, byte), ddr_data_control_1.raw);
|
||||
+ }
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
+/*
|
||||
+ * Return a random value to use for scrambler seeds. Try to use RDRAND
|
||||
+ * first and fall back to hardcoded values if RDRAND does not succeed.
|
||||
+ */
|
||||
+static uint16_t get_random_number(const uint8_t channel)
|
||||
+{
|
||||
+ /* The RDRAND instruction is only available 100k cycles after reset */
|
||||
+ for (size_t i = 0; i < 100000; i++) {
|
||||
+ uint32_t status;
|
||||
+ uint32_t random;
|
||||
+ /** TODO: Clean up asm **/
|
||||
+ __asm__ __volatile__(
|
||||
+ "\n\t .byte 0x0F, 0xC7, 0xF0"
|
||||
+ "\n\t movl %%eax, %0"
|
||||
+ "\n\t pushf"
|
||||
+ "\n\t pop %%eax"
|
||||
+ "\n\t movl %%eax, %1"
|
||||
+ : "=m"(random),
|
||||
+ "=m"(status)
|
||||
+ : /* No inputs */
|
||||
+ : "eax", "cc");
|
||||
+
|
||||
+ /* Only consider non-zero random values as valid */
|
||||
+ if (status & 1 && random)
|
||||
+ return random;
|
||||
+ }
|
||||
+
|
||||
+ /* https://xkcd.com/221 */
|
||||
+ if (channel)
|
||||
+ return 0x28f4;
|
||||
+ else
|
||||
+ return 0x893e;
|
||||
+}
|
||||
+
|
||||
+/* Work around "error: 'typeof' applied to a bit-field" */
|
||||
+static inline uint32_t max(const uint32_t a, const uint32_t b)
|
||||
+{
|
||||
+ return MAX(a, b);
|
||||
+}
|
||||
+
|
||||
+enum raminit_status activate_mc(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ const bool enable_scrambling = true;
|
||||
+ const bool enable_cmd_tristate = true;
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ if (enable_scrambling && ctrl->stepping < STEPPING_C0) {
|
||||
+ /* Make sure tRDRD_(sr, dr, dd) are at least 6 for scrambler W/A */
|
||||
+ union tc_bank_rank_a_reg tc_bank_rank_a = {
|
||||
+ .raw = mchbar_read32(TC_BANK_RANK_A_ch(channel)),
|
||||
+ };
|
||||
+ tc_bank_rank_a.tRDRD_sr = max(tc_bank_rank_a.tRDRD_sr, 6);
|
||||
+ tc_bank_rank_a.tRDRD_dr = max(tc_bank_rank_a.tRDRD_dr, 6);
|
||||
+ tc_bank_rank_a.tRDRD_dd = max(tc_bank_rank_a.tRDRD_dd, 6);
|
||||
+ mchbar_write32(TC_BANK_RANK_A_ch(channel), tc_bank_rank_a.raw);
|
||||
+ }
|
||||
+ if (enable_scrambling) {
|
||||
+ const union ddr_scramble_reg ddr_scramble = {
|
||||
+ .scram_key = get_random_number(channel),
|
||||
+ .scram_en = 1,
|
||||
+ };
|
||||
+ mchbar_write32(DDR_SCRAMBLE_ch(channel), ddr_scramble.raw);
|
||||
+ }
|
||||
+ if (ctrl->tCMD == 1) {
|
||||
+ /* If we are in 1N mode, enable and set command rate limit to 3 */
|
||||
+ union mcmain_command_rate_limit_reg cmd_rate_limit = {
|
||||
+ .raw = mchbar_read32(COMMAND_RATE_LIMIT_ch(channel)),
|
||||
+ };
|
||||
+ cmd_rate_limit.enable_cmd_limit = 1;
|
||||
+ cmd_rate_limit.cmd_rate_limit = 3;
|
||||
+ mchbar_write32(COMMAND_RATE_LIMIT_ch(channel), cmd_rate_limit.raw);
|
||||
+ }
|
||||
+ if (enable_cmd_tristate) {
|
||||
+ /* Enable command tri-state at the end of training */
|
||||
+ union tc_bank_rank_a_reg tc_bank_rank_a = {
|
||||
+ .raw = mchbar_read32(TC_BANK_RANK_A_ch(channel)),
|
||||
+ };
|
||||
+ tc_bank_rank_a.cmd_3st_dis = 0;
|
||||
+ mchbar_write32(TC_BANK_RANK_A_ch(channel), tc_bank_rank_a.raw);
|
||||
+ }
|
||||
+ /* Set MC to normal mode and clean the ODT and CKE */
|
||||
+ mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12);
|
||||
+ /* Set again the rank occupancy */
|
||||
+ mchbar_write8(MC_INIT_STATE_ch(channel), ctrl->rankmap[channel]);
|
||||
+ if (ctrl->is_ecc) {
|
||||
+ /* Enable ECC I/O and logic */
|
||||
+ union mad_dimm_reg mad_dimm = {
|
||||
+ .raw = mchbar_read32(MAD_DIMM(channel)),
|
||||
+ };
|
||||
+ mad_dimm.ecc_mode = 3;
|
||||
+ mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
|
||||
+ }
|
||||
+ }
|
||||
+
|
||||
+ if (!is_hsw_ult())
|
||||
+ update_internal_clocks_on(ctrl);
|
||||
+
|
||||
+ update_sdll_length(ctrl);
|
||||
+
|
||||
+ program_burst_end_odt_delay(ctrl);
|
||||
+
|
||||
+ if (is_hsw_ult()) {
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ if (!does_ch_exist(ctrl, channel))
|
||||
+ continue;
|
||||
+
|
||||
+ set_rx_clk_stg_num(ctrl, channel);
|
||||
+ }
|
||||
+ /** TODO: Program DDRPL_CR_DDR_TX_DELAY if Memory Trace is enabled **/
|
||||
+ }
|
||||
+
|
||||
+ /* Enable periodic COMP */
|
||||
+ mchbar_write32(M_COMP, (union pcu_comp_reg) {
|
||||
+ .comp_interval = COMP_INT,
|
||||
+ }.raw);
|
||||
+
|
||||
+ /* Enable the power mode before PCU starts working */
|
||||
+ train_power_modes_post(ctrl);
|
||||
+
|
||||
+ /* Set idle timer and self refresh enable bits */
|
||||
+ enter_sr();
|
||||
+
|
||||
+ /** FIXME: Do not hardcode power weights and RAPL settings **/
|
||||
+ mchbar_write32(0x5888, 0x00000d0d);
|
||||
+ mchbar_write32(0x5884, 0x00000004); /* 58.2 pJ */
|
||||
+
|
||||
+ mchbar_write32(0x58e0, 0);
|
||||
+ mchbar_write32(0x58e4, 0);
|
||||
+
|
||||
+ mchbar_write32(0x5890, 0xffff);
|
||||
+ mchbar_write32(0x5894, 0xffff);
|
||||
+ mchbar_write32(0x5898, 0xffff);
|
||||
+ mchbar_write32(0x589c, 0xffff);
|
||||
+ mchbar_write32(0x58d0, 0xffff);
|
||||
+ mchbar_write32(0x58d4, 0xffff);
|
||||
+ mchbar_write32(0x58d8, 0xffff);
|
||||
+ mchbar_write32(0x58dc, 0xffff);
|
||||
+
|
||||
+ /* Overwrite thermal parameters */
|
||||
+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
|
||||
+ mchbar_write32(_MCMAIN_C(0x42ec, channel), 0x0000000f);
|
||||
+ mchbar_write32(_MCMAIN_C(0x42f0, channel), 0x00000009);
|
||||
+ mchbar_write32(_MCMAIN_C(0x42f4, channel), 0x00000093);
|
||||
+ mchbar_write32(_MCMAIN_C(0x42f8, channel), 0x00000087);
|
||||
+ mchbar_write32(_MCMAIN_C(0x42fc, channel), 0x000000de);
|
||||
+
|
||||
+ /** TODO: Differs for LPDDR **/
|
||||
+ mchbar_write32(PM_THRT_CKE_MIN_ch(channel), 0x30);
|
||||
+ }
|
||||
+ mchbar_write32(PCU_DDR_PTM_CTL, 0x40);
|
||||
+ return RAMINIT_STATUS_SUCCESS;
|
||||
+}
|
||||
+
|
||||
+static void mc_lockdown(void)
|
||||
+{
|
||||
+ /* Lock memory controller registers */
|
||||
+ mchbar_write32(MC_LOCK, 0x8f);
|
||||
+
|
||||
+ /* MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK is set when programming the memory map */
|
||||
+
|
||||
+ /* Lock memory map registers */
|
||||
+ pci_or_config16(HOST_BRIDGE, GGC, 1 << 0);
|
||||
+ pci_or_config32(HOST_BRIDGE, DPR, 1 << 0);
|
||||
+ pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, 1 << 10);
|
||||
+ pci_or_config32(HOST_BRIDGE, REMAPBASE, 1 << 0);
|
||||
+ pci_or_config32(HOST_BRIDGE, REMAPLIMIT, 1 << 0);
|
||||
+ pci_or_config32(HOST_BRIDGE, TOM, 1 << 0);
|
||||
+ pci_or_config32(HOST_BRIDGE, TOUUD, 1 << 0);
|
||||
+ pci_or_config32(HOST_BRIDGE, BDSM, 1 << 0);
|
||||
+ pci_or_config32(HOST_BRIDGE, BGSM, 1 << 0);
|
||||
+ pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0);
|
||||
+}
|
||||
+
|
||||
+enum raminit_status raminit_done(struct sysinfo *ctrl)
|
||||
+{
|
||||
+ union mc_init_state_g_reg mc_init_state_g = {
|
||||
+ .raw = mchbar_read32(MC_INIT_STATE_G),
|
||||
+ };
|
||||
+ mc_init_state_g.refresh_enable = 1;
|
||||
+ mc_init_state_g.pu_mrc_done = 1;
|
||||
+ mc_init_state_g.mrc_done = 1;
|
||||
+ mchbar_write32(MC_INIT_STATE_G, mc_init_state_g.raw);
|
||||
+
|
||||
+ /* Lock the memory controller to enable normal operation */
|
||||
+ mc_lockdown();
|
||||
+
|
||||
+ /* Poll for mc_init_done_ack to make sure memory initialization is complete */
|
||||
+ printk(BIOS_DEBUG, "Waiting for mc_init_done acknowledgement... ");
|
||||
+
|
||||
+ struct stopwatch timer;
|
||||
+ stopwatch_init_msecs_expire(&timer, 2000);
|
||||
+ do {
|
||||
+ mc_init_state_g.raw = mchbar_read32(MC_INIT_STATE_G);
|
||||
+
|
||||
+ /* DRAM will NOT work without the acknowledgement. There is no hope. */
|
||||
+ if (stopwatch_expired(&timer))
|
||||
+ die("\nTimed out waiting for mc_init_done acknowledgement\n");
|
||||
+
|
||||
+ } while (mc_init_state_g.mc_init_done_ack == 0);
|
||||
+ printk(BIOS_DEBUG, "DONE!\n");
|
||||
+
|
||||
+ /* Provide some data for the graphics driver. Yes, it's hardcoded. */
|
||||
+ mchbar_write32(SSKPD + 0, 0x05a2404f);
|
||||
+ mchbar_write32(SSKPD + 4, 0x140000a0);
|
||||
+ return RAMINIT_STATUS_SUCCESS;
|
||||
+}
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
index 1ff23be615..3a65fb01fb 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
|
||||
@@ -63,6 +63,8 @@ static const struct task_entry cold_boot[] = {
|
||||
{ train_receive_enable, true, "RCVET", },
|
||||
{ train_read_mpr, true, "RDMPRT", },
|
||||
{ train_jedec_write_leveling, true, "JWRL", },
|
||||
+ { activate_mc, true, "ACTIVATE", },
|
||||
+ { raminit_done, true, "RAMINITEND", },
|
||||
};
|
||||
|
||||
/* Return a generic stepping value to make stepping checks simpler */
|
||||
@@ -143,7 +145,4 @@ void raminit_main(const enum raminit_boot_mode bootmode)
|
||||
|
||||
if (status != RAMINIT_STATUS_SUCCESS)
|
||||
die("Memory initialization was met with utmost failure and misery\n");
|
||||
-
|
||||
- /** TODO: Implement the required magic **/
|
||||
- die("NATIVE RAMINIT: More Magic (tm) required.\n");
|
||||
}
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
|
||||
index ffb5e825f0..6bf7e7cdfb 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
|
||||
@@ -200,8 +200,6 @@ void perform_raminit(const int s3resume)
|
||||
else
|
||||
me_status = ME_INIT_STATUS_SUCCESS;
|
||||
|
||||
- /** TODO: Remove this once raminit is implemented **/
|
||||
- me_status = ME_INIT_STATUS_ERROR;
|
||||
intel_early_me_init_done(me_status);
|
||||
}
|
||||
|
||||
@@ -215,7 +213,8 @@ void perform_raminit(const int s3resume)
|
||||
}
|
||||
|
||||
/* Save training data on non-S3 resumes */
|
||||
- if (!s3resume)
|
||||
+ /** TODO: Enable this once training data is populated **/
|
||||
+ if (0 && !s3resume)
|
||||
save_mrc_data(&md);
|
||||
|
||||
/** TODO: setup_sdram_meminfo **/
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index 666b233c45..98e39cb76e 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -449,6 +449,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
|
||||
enum raminit_status train_receive_enable(struct sysinfo *ctrl);
|
||||
enum raminit_status train_read_mpr(struct sysinfo *ctrl);
|
||||
enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
|
||||
+enum raminit_status activate_mc(struct sysinfo *ctrl);
|
||||
+enum raminit_status raminit_done(struct sysinfo *ctrl);
|
||||
|
||||
void configure_timings(struct sysinfo *ctrl);
|
||||
void configure_refresh(struct sysinfo *ctrl);
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
index a0e36ed082..0d9aaa1f7c 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
|
||||
@@ -294,6 +294,18 @@ union ddr_cke_ctl_controls_reg {
|
||||
uint32_t raw;
|
||||
};
|
||||
|
||||
+union ddr_scramble_reg {
|
||||
+ struct __packed {
|
||||
+ uint32_t scram_en : 1; // Bits 0:0
|
||||
+ uint32_t scram_key : 16; // Bits 16:1
|
||||
+ uint32_t clk_gate_ab : 2; // Bits 18:17
|
||||
+ uint32_t clk_gate_c : 2; // Bits 20:19
|
||||
+ uint32_t en_dbi_ab : 1; // Bits 21:21
|
||||
+ uint32_t : 10; // Bits 31:17
|
||||
+ };
|
||||
+ uint32_t raw;
|
||||
+};
|
||||
+
|
||||
union ddr_scram_misc_control_reg {
|
||||
struct __packed {
|
||||
uint32_t wl_wake_cycles : 2; // Bits 1:0
|
||||
diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
index 7c0b5a49de..49a215aa71 100644
|
||||
--- a/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
|
||||
@@ -20,6 +20,7 @@
|
||||
|
||||
#define DDR_DATA_TRAIN_FEEDBACK(ch, byte) _DDRIO_C_R_B(0x0054, ch, 0, byte)
|
||||
|
||||
+#define DQ_CONTROL_1(ch, byte) _DDRIO_C_R_B(0x0060, ch, 0, byte)
|
||||
#define DQ_CONTROL_2(ch, byte) _DDRIO_C_R_B(0x0064, ch, 0, byte)
|
||||
#define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte) _DDRIO_C_R_B(0x0070, ch, 0, byte)
|
||||
#define DQ_CONTROL_0(ch, byte) _DDRIO_C_R_B(0x0074, ch, 0, byte)
|
||||
@@ -147,6 +148,8 @@
|
||||
#define QCLK_ch_LDAT_SDAT(ch) _MCMAIN_C(0x42d4, ch)
|
||||
#define QCLK_ch_LDAT_DATA_IN_x(ch, x) _MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
|
||||
|
||||
+#define PM_THRT_CKE_MIN_ch(ch) _MCMAIN_C(0x4328, ch)
|
||||
+
|
||||
#define REUT_GLOBAL_CTL 0x4800
|
||||
#define REUT_GLOBAL_ERR 0x4804
|
||||
|
||||
@@ -175,6 +178,8 @@
|
||||
|
||||
#define MCSCHEDS_DFT_MISC 0x4c30
|
||||
|
||||
+#define PM_PDWN_CONFIG 0x4cb0
|
||||
+
|
||||
#define REUT_ERR_DATA_STATUS 0x4ce0
|
||||
|
||||
#define REUT_MISC_CKE_CTRL 0x4d90
|
||||
@@ -186,8 +191,10 @@
|
||||
#define MAD_CHNL 0x5000 /* Address Decoder Channel Configuration */
|
||||
#define MAD_DIMM(ch) (0x5004 + (ch) * 4)
|
||||
#define MAD_ZR 0x5014
|
||||
+#define MCDECS_CBIT 0x501c
|
||||
#define MC_INIT_STATE_G 0x5030
|
||||
#define MRC_REVISION 0x5034 /* MRC Revision */
|
||||
+#define PM_SREF_CONFIG 0x5060
|
||||
|
||||
#define RCOMP_TIMER 0x5084
|
||||
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,109 @@
|
||||
From 0310d8b3fcf8f305f655dacc3322de60bdc2adc4 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Mon, 8 Apr 2024 00:38:18 +0100
|
||||
Subject: [PATCH 1/1] haswell NRI: include commonlib/bsd/clamp.h
|
||||
|
||||
the location of clamp.h changed. these sources were rebased
|
||||
from an older coreboot revision. update to match new code.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/northbridge/intel/haswell/native_raminit/change_margin.c | 2 +-
|
||||
src/northbridge/intel/haswell/native_raminit/configure_mc.c | 2 +-
|
||||
src/northbridge/intel/haswell/native_raminit/init_mpll.c | 2 +-
|
||||
src/northbridge/intel/haswell/native_raminit/io_comp_control.c | 2 +-
|
||||
src/northbridge/intel/haswell/native_raminit/lookup_timings.c | 2 +-
|
||||
src/northbridge/intel/haswell/native_raminit/timings_refresh.c | 2 +-
|
||||
src/northbridge/intel/haswell/native_raminit/train_read_mpr.c | 2 +-
|
||||
7 files changed, 7 insertions(+), 7 deletions(-)
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
|
||||
index 4ba9cfa5c6..299c44a6b0 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
|
||||
@@ -1,7 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <assert.h>
|
||||
-#include <commonlib/clamp.h>
|
||||
+#include <commonlib/bsd/clamp.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <northbridge/intel/haswell/haswell.h>
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/configure_mc.c b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
|
||||
index 2a667b075b..003fa0e941 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/configure_mc.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/configure_mc.c
|
||||
@@ -1,7 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <assert.h>
|
||||
-#include <commonlib/clamp.h>
|
||||
+#include <commonlib/bsd/clamp.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <lib.h>
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
|
||||
index 2faa183724..1f3f2c29a9 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/init_mpll.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
|
||||
@@ -1,6 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
-#include <commonlib/clamp.h>
|
||||
+#include <commonlib/bsd/clamp.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <device/pci_ops.h>
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
|
||||
index ad8c848e57..8a55fd81b2 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
|
||||
@@ -1,6 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
-#include <commonlib/clamp.h>
|
||||
+#include <commonlib/bsd/clamp.h>
|
||||
#include <console/console.h>
|
||||
#include <northbridge/intel/haswell/haswell.h>
|
||||
#include <timer.h>
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
|
||||
index afe2c615d2..b8d6c1ef40 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
|
||||
@@ -1,6 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
-#include <commonlib/clamp.h>
|
||||
+#include <commonlib/bsd/clamp.h>
|
||||
#include <types.h>
|
||||
|
||||
#include "raminit_native.h"
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
|
||||
index 20a05b359b..820bb336b0 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
|
||||
@@ -1,7 +1,7 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
#include <assert.h>
|
||||
-#include <commonlib/clamp.h>
|
||||
+#include <commonlib/bsd/clamp.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <device/pci_ops.h>
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
|
||||
index 0225e1a384..86f79942d3 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
|
||||
@@ -1,6 +1,6 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-or-later */
|
||||
|
||||
-#include <commonlib/clamp.h>
|
||||
+#include <commonlib/bsd/clamp.h>
|
||||
#include <console/console.h>
|
||||
#include <delay.h>
|
||||
#include <northbridge/intel/haswell/haswell.h>
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,81 @@
|
||||
From 2728c87b7f792aa8e4db29d4dc3d2d2f71f6dafd Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Mon, 8 Apr 2024 00:54:44 +0100
|
||||
Subject: [PATCH 1/1] haswell NRI: mitigate compiler warnings
|
||||
|
||||
Random -Werror warnings. I'd rather patch these up
|
||||
than disable warnings-as-errors in the code.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
.../intel/haswell/native_raminit/raminit_native.h | 1 +
|
||||
src/northbridge/intel/haswell/native_raminit/reut.c | 5 +++--
|
||||
src/northbridge/intel/haswell/native_raminit/testing_io.c | 2 +-
|
||||
.../intel/haswell/native_raminit/timings_refresh.c | 2 +-
|
||||
4 files changed, 6 insertions(+), 4 deletions(-)
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
index 98e39cb76e..76a74d6569 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
|
||||
@@ -397,6 +397,7 @@ static inline void tick_delay(const uint32_t delay)
|
||||
/* Just perform reads to a random register */
|
||||
for (uint32_t start = 0; start <= delay; start++)
|
||||
junk = mchbar_read32(REUT_ERR_DATA_STATUS);
|
||||
+ (void)junk; /* mitigate -Werror=unused-but-set-variable */
|
||||
}
|
||||
|
||||
/*
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/reut.c b/src/northbridge/intel/haswell/native_raminit/reut.c
|
||||
index c55cdd9c7e..c861528a92 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/reut.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/reut.c
|
||||
@@ -153,7 +153,7 @@ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_
|
||||
{
|
||||
/** TODO: Issuing ZQ commands differs for LPDDR **/
|
||||
if (ctrl->lpddr)
|
||||
- die("%s: LPDDR not yet supported in ZQ calibration\n");
|
||||
+ die("LPDDR not yet supported in ZQ calibration\n");
|
||||
|
||||
uint8_t opcode; /* NOTE: Only used for LPDDR */
|
||||
uint16_t zq = 0;
|
||||
@@ -173,8 +173,9 @@ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_
|
||||
opcode = 0xc3;
|
||||
break;
|
||||
default:
|
||||
- die("%s: ZQ type %u is invalid\n", zq_type);
|
||||
+ die("ZQ type %u is invalid\n", zq_type);
|
||||
}
|
||||
+ (void)opcode; /* Mitigate -Werror=unused-but-set-variable */
|
||||
|
||||
/* ZQCS on single-channel needs a longer delay */
|
||||
const uint8_t delay = zq_type == ZQ_SHORT && (!ctrl->dpc[0] || !ctrl->dpc[1]) ? 7 : 1;
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/testing_io.c b/src/northbridge/intel/haswell/native_raminit/testing_io.c
|
||||
index 7716fc4285..63ae59c33e 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/testing_io.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/testing_io.c
|
||||
@@ -221,7 +221,7 @@ void setup_io_test(
|
||||
const uint8_t subseq_wait)
|
||||
{
|
||||
if (!chanmask)
|
||||
- die("\n%s: invalid chanmask\n", __func__, chanmask);
|
||||
+ die("\n%d: invalid chanmask\n", chanmask);
|
||||
|
||||
/*
|
||||
* Prepare variables needed for both channels.
|
||||
diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
|
||||
index 820bb336b0..e5d8088912 100644
|
||||
--- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
|
||||
+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
|
||||
@@ -189,7 +189,7 @@ static union tc_srftp_reg make_tc_srftp(const struct sysinfo *const ctrl)
|
||||
void configure_timings(struct sysinfo *ctrl)
|
||||
{
|
||||
if (ctrl->lpddr)
|
||||
- die("%s: Missing support for LPDDR\n");
|
||||
+ die("Missing support for LPDDR\n");
|
||||
|
||||
const uint8_t odt_stretch = get_odt_stretch(ctrl);
|
||||
const union tc_bank_reg tc_bank = make_tc_bank(ctrl);
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,2 @@
|
||||
tree="default"
|
||||
rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"
|
||||
+203
@@ -0,0 +1,203 @@
|
||||
From 4fbd327df271d613d4a56a36eafd88d9d642ec6b Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 19 Feb 2023 18:21:43 +0000
|
||||
Subject: [PATCH 1/9] util/ifdtool: add --nuke flag (all 0xFF on region)
|
||||
|
||||
When this option is used, the region's contents are overwritten
|
||||
with all ones (0xFF).
|
||||
|
||||
Example:
|
||||
|
||||
./ifdtool --nuke gbe coreboot.rom
|
||||
./ifdtool --nuke bios coreboot.com
|
||||
./ifdtool --nuke me coreboot.com
|
||||
|
||||
Rebased since the last revision update in lbmk.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
|
||||
1 file changed, 81 insertions(+), 31 deletions(-)
|
||||
|
||||
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
|
||||
index 191b3216de..38132b4a28 100644
|
||||
--- a/util/ifdtool/ifdtool.c
|
||||
+++ b/util/ifdtool/ifdtool.c
|
||||
@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
|
||||
" tgl - Tiger Lake\n"
|
||||
" wbg - Wellsburg\n"
|
||||
" -S | --setpchstrap Write a PCH strap\n"
|
||||
+ " -N | --nuke <region> Overwrite the specified region with 0xFF (all ones)\n"
|
||||
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
|
||||
" -v | --version: print the version\n"
|
||||
" -h | --help: print this help\n\n"
|
||||
@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
|
||||
"\n");
|
||||
}
|
||||
|
||||
+static int
|
||||
+get_region_type_string(const char *region_type_string)
|
||||
+{
|
||||
+ if (!strcasecmp("Descriptor", region_type_string))
|
||||
+ return 0;
|
||||
+ else if (!strcasecmp("BIOS", region_type_string))
|
||||
+ return 1;
|
||||
+ else if (!strcasecmp("ME", region_type_string))
|
||||
+ return 2;
|
||||
+ else if (!strcasecmp("GbE", region_type_string))
|
||||
+ return 3;
|
||||
+ else if (!strcasecmp("Platform Data", region_type_string))
|
||||
+ return 4;
|
||||
+ else if (!strcasecmp("Device Exp1", region_type_string))
|
||||
+ return 5;
|
||||
+ else if (!strcasecmp("Secondary BIOS", region_type_string))
|
||||
+ return 6;
|
||||
+ else if (!strcasecmp("Reserved", region_type_string))
|
||||
+ return 7;
|
||||
+ else if (!strcasecmp("EC", region_type_string))
|
||||
+ return 8;
|
||||
+ else if (!strcasecmp("Device Exp2", region_type_string))
|
||||
+ return 9;
|
||||
+ else if (!strcasecmp("IE", region_type_string))
|
||||
+ return 10;
|
||||
+ else if (!strcasecmp("10GbE_0", region_type_string))
|
||||
+ return 11;
|
||||
+ else if (!strcasecmp("10GbE_1", region_type_string))
|
||||
+ return 12;
|
||||
+ else if (!strcasecmp("PTT", region_type_string))
|
||||
+ return 15;
|
||||
+ return -1;
|
||||
+}
|
||||
+
|
||||
+static void
|
||||
+nuke(const char *filename, char *image, int size, int region_type)
|
||||
+{
|
||||
+ int i;
|
||||
+ struct region region;
|
||||
+ const struct frba *frba = find_frba(image, size);
|
||||
+ if (!frba)
|
||||
+ exit(EXIT_FAILURE);
|
||||
+
|
||||
+ region = get_region(frba, region_type);
|
||||
+ if (region.size > 0) {
|
||||
+ for (i = region.base; i <= region.limit; i++) {
|
||||
+ if ((i + 1) > (size))
|
||||
+ break;
|
||||
+ image[i] = 0xFF;
|
||||
+ }
|
||||
+ write_image(filename, image, size);
|
||||
+ }
|
||||
+}
|
||||
+
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int opt, option_index = 0;
|
||||
@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
|
||||
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
|
||||
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
|
||||
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
|
||||
+ int mode_nuke = 0;
|
||||
int mode_gpr0_disable = 0;
|
||||
char *region_type_string = NULL, *region_fname = NULL;
|
||||
const char *layout_fname = NULL;
|
||||
@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
|
||||
{"validate", 0, NULL, 't'},
|
||||
{"setpchstrap", 1, NULL, 'S'},
|
||||
{"newvalue", 1, NULL, 'V'},
|
||||
+ {"nuke", 1, NULL, 'N'},
|
||||
{0, 0, 0, 0}
|
||||
};
|
||||
|
||||
@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
|
||||
region_fname++;
|
||||
// Descriptor, BIOS, ME, GbE, Platform
|
||||
// valid type?
|
||||
- if (!strcasecmp("Descriptor", region_type_string))
|
||||
- region_type = 0;
|
||||
- else if (!strcasecmp("BIOS", region_type_string))
|
||||
- region_type = 1;
|
||||
- else if (!strcasecmp("ME", region_type_string))
|
||||
- region_type = 2;
|
||||
- else if (!strcasecmp("GbE", region_type_string))
|
||||
- region_type = 3;
|
||||
- else if (!strcasecmp("Platform Data", region_type_string))
|
||||
- region_type = 4;
|
||||
- else if (!strcasecmp("Device Exp1", region_type_string))
|
||||
- region_type = 5;
|
||||
- else if (!strcasecmp("Secondary BIOS", region_type_string))
|
||||
- region_type = 6;
|
||||
- else if (!strcasecmp("Reserved", region_type_string))
|
||||
- region_type = 7;
|
||||
- else if (!strcasecmp("EC", region_type_string))
|
||||
- region_type = 8;
|
||||
- else if (!strcasecmp("Device Exp2", region_type_string))
|
||||
- region_type = 9;
|
||||
- else if (!strcasecmp("IE", region_type_string))
|
||||
- region_type = 10;
|
||||
- else if (!strcasecmp("10GbE_0", region_type_string))
|
||||
- region_type = 11;
|
||||
- else if (!strcasecmp("10GbE_1", region_type_string))
|
||||
- region_type = 12;
|
||||
- else if (!strcasecmp("PTT", region_type_string))
|
||||
- region_type = 15;
|
||||
- if (region_type == -1) {
|
||||
+ if ((region_type =
|
||||
+ get_region_type_string(region_type_string)) == -1) {
|
||||
fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
region_type_string);
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
|
||||
case 't':
|
||||
mode_validate = 1;
|
||||
break;
|
||||
+ case 'N':
|
||||
+ region_type_string = strdup(optarg);
|
||||
+ if (!region_type_string) {
|
||||
+ fprintf(stderr, "No region specified\n");
|
||||
+ print_usage(argv[0]);
|
||||
+ exit(EXIT_FAILURE);
|
||||
+ }
|
||||
+ if ((region_type =
|
||||
+ get_region_type_string(region_type_string)) == -1) {
|
||||
+ fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
+ region_type_string);
|
||||
+ print_usage(argv[0]);
|
||||
+ exit(EXIT_FAILURE);
|
||||
+ }
|
||||
+ mode_nuke = 1;
|
||||
+ break;
|
||||
case 'v':
|
||||
print_version();
|
||||
exit(EXIT_SUCCESS);
|
||||
@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
|
||||
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
|
||||
- mode_gpr0_disable) > 1) {
|
||||
+ mode_gpr0_disable + mode_nuke) > 1) {
|
||||
fprintf(stderr, "You may not specify more than one mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
|
||||
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
|
||||
- mode_validate + mode_gpr0_disable) == 0) {
|
||||
+ mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
|
||||
fprintf(stderr, "You need to specify a mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
|
||||
write_image(new_filename, image, size);
|
||||
}
|
||||
|
||||
+ if (mode_nuke) {
|
||||
+ nuke(new_filename, image, size, region_type);
|
||||
+ }
|
||||
+
|
||||
if (mode_altmedisable) {
|
||||
struct fpsba *fpsba = find_fpsba(image, size);
|
||||
struct fmsba *fmsba = find_fmsba(image, size);
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+47
@@ -0,0 +1,47 @@
|
||||
From 362e86f89b3980699e7e794df9b98018397fe2d8 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Wed, 1 Dec 2021 02:53:00 +0000
|
||||
Subject: [PATCH 2/9] fix speedstep on x200/t400: Revert
|
||||
"cpu/intel/model_1067x: enable PECI"
|
||||
|
||||
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
|
||||
|
||||
Enabling PECI without microcode updates loaded causes the CPUID feature set
|
||||
to become corrupted. And one consequence is broken SpeedStep. At least, that's
|
||||
my understanding looking at Intel Errata. This revert is not a fix, because
|
||||
upstream is correct (upstream assumes microcode updates). We will simply
|
||||
maintain this revert patch in Libreboot, from now on.
|
||||
---
|
||||
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
|
||||
1 file changed, 9 deletions(-)
|
||||
|
||||
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
index 315e7c36fc..1423fd72bc 100644
|
||||
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
|
||||
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
|
||||
}
|
||||
|
||||
-#define IA32_PECI_CTL 0x5a0
|
||||
-
|
||||
static void configure_misc(const int eist, const int tm2, const int emttm)
|
||||
{
|
||||
msr_t msr;
|
||||
@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
|
||||
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
|
||||
wrmsr(IA32_MISC_ENABLE, msr);
|
||||
}
|
||||
-
|
||||
- /* Enable PECI
|
||||
- WARNING: due to Erratum AW67 described in Intel document #318733
|
||||
- the microcode must be updated before this MSR is written to. */
|
||||
- msr = rdmsr(IA32_PECI_CTL);
|
||||
- msr.lo |= 1;
|
||||
- wrmsr(IA32_PECI_CTL, msr);
|
||||
}
|
||||
|
||||
#define PIC_SENS_CFG 0x1aa
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,173 @@
|
||||
From 883455573f07551eaf2b12ab80bedcd2b4904a17 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 17 Apr 2023 15:49:57 +0100
|
||||
Subject: [PATCH 3/9] GM45-type CPUs: don't enable alternative SMRR
|
||||
|
||||
This reverts the changes in coreboot revision:
|
||||
df7aecd92643d207feaf7fd840f8835097346644
|
||||
|
||||
While this fix is *technically correct*, the one in
|
||||
coreboot, it breaks rebooting as tested on several
|
||||
GM45 ThinkPads e.g. X200, T400, when microcode
|
||||
updates are not applied.
|
||||
|
||||
Since November 2022, Libreboot includes microcode
|
||||
updates by default, but it tells users how to remove
|
||||
it from the ROM (with cbfstool) if they wish.
|
||||
|
||||
Well, with Libreboot 20221214, 20230319 and 20230413,
|
||||
mitigations present in Libreboot 20220710 (which did
|
||||
not have microcode updates) do not exist.
|
||||
|
||||
This patch, along with the other patch to remove PECI
|
||||
support (which breaks speedstep when microcode updates
|
||||
are not applied) have now been re-added to Libreboot.
|
||||
|
||||
It is still best to use microcode updates by default.
|
||||
These patches in coreboot are not critically urgent,
|
||||
and you can use the machines with or without them,
|
||||
regardless of ucode.
|
||||
|
||||
I'll probably re-write this and the other patch at
|
||||
some point, applying the change conditionally upon
|
||||
whether or not microcode is applied.
|
||||
|
||||
Pragmatism is a good thing. I recommend it.
|
||||
---
|
||||
src/cpu/intel/model_1067x/model_1067x_init.c | 4 +++
|
||||
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
|
||||
src/cpu/intel/model_106cx/model_106cx_init.c | 4 +++
|
||||
src/cpu/intel/model_6ex/model_6ex_init.c | 4 +++
|
||||
src/cpu/intel/model_6fx/model_6fx_init.c | 4 +++
|
||||
5 files changed, 16 insertions(+), 26 deletions(-)
|
||||
|
||||
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
index 1423fd72bc..d1f98ca43a 100644
|
||||
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
|
||||
@@ -8,6 +8,7 @@
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/name.h>
|
||||
#include <cpu/intel/smm_reloc.h>
|
||||
+#include <cpu/intel/common/common.h>
|
||||
|
||||
#define MSR_BBL_CR_CTL3 0x11e
|
||||
|
||||
@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
|
||||
fill_processor_name(processor_name);
|
||||
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
|
||||
|
||||
+ /* Set virtualization based on Kconfig option */
|
||||
+ set_vmx_and_lock();
|
||||
+
|
||||
/* Configure C States */
|
||||
configure_c_states(quad);
|
||||
|
||||
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
|
||||
index bc53214310..72f40f6762 100644
|
||||
--- a/src/cpu/intel/model_1067x/mp_init.c
|
||||
+++ b/src/cpu/intel/model_1067x/mp_init.c
|
||||
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
|
||||
smm_initialize();
|
||||
}
|
||||
|
||||
-#define SMRR_SUPPORTED (1 << 11)
|
||||
-
|
||||
static void per_cpu_smm_trigger(void)
|
||||
{
|
||||
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
|
||||
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
|
||||
- set_feature_ctrl_vmx();
|
||||
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
|
||||
- /* We don't care if the lock is already setting
|
||||
- as our smm relocation handler is able to handle
|
||||
- setups where SMRR is not enabled here. */
|
||||
- if (ia32_ft_ctrl.lo & (1 << 0)) {
|
||||
- /* IA32_FEATURE_CONTROL locked. If we set it again we
|
||||
- get an illegal instruction. */
|
||||
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
|
||||
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
|
||||
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
|
||||
- } else {
|
||||
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
|
||||
- printk(BIOS_INFO,
|
||||
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
|
||||
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
|
||||
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
|
||||
- }
|
||||
- } else {
|
||||
- set_vmx_and_lock();
|
||||
- }
|
||||
-
|
||||
/* Relocate the SMM handler. */
|
||||
smm_relocate();
|
||||
}
|
||||
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
|
||||
index 05f5f327cc..0450c2ad83 100644
|
||||
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
|
||||
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <cpu/intel/speedstep.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/name.h>
|
||||
+#include <cpu/intel/common/common.h>
|
||||
|
||||
#define HIGHEST_CLEVEL 3
|
||||
static void configure_c_states(void)
|
||||
@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
|
||||
fill_processor_name(processor_name);
|
||||
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
|
||||
|
||||
+ /* Set virtualization based on Kconfig option */
|
||||
+ set_vmx_and_lock();
|
||||
+
|
||||
/* Configure C States */
|
||||
configure_c_states();
|
||||
|
||||
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
|
||||
index 5bd1c32815..f3bb08cde3 100644
|
||||
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
|
||||
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <cpu/intel/speedstep.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/name.h>
|
||||
+#include <cpu/intel/common/common.h>
|
||||
|
||||
#define HIGHEST_CLEVEL 3
|
||||
static void configure_c_states(void)
|
||||
@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
|
||||
/* Setup Page Attribute Tables (PAT) */
|
||||
// TODO set up PAT
|
||||
|
||||
+ /* Set virtualization based on Kconfig option */
|
||||
+ set_vmx_and_lock();
|
||||
+
|
||||
/* Configure C States */
|
||||
configure_c_states();
|
||||
|
||||
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
|
||||
index 535fb8fae7..f7b05facd2 100644
|
||||
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
|
||||
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <cpu/intel/speedstep.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/x86/name.h>
|
||||
+#include <cpu/intel/common/common.h>
|
||||
|
||||
#define HIGHEST_CLEVEL 3
|
||||
static void configure_c_states(void)
|
||||
@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
|
||||
/* Setup Page Attribute Tables (PAT) */
|
||||
// TODO set up PAT
|
||||
|
||||
+ /* Set virtualization based on Kconfig option */
|
||||
+ set_vmx_and_lock();
|
||||
+
|
||||
/* Configure C States */
|
||||
configure_c_states();
|
||||
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+28
@@ -0,0 +1,28 @@
|
||||
From 458fe39e9cd2536cfa8671427e6f557396143339 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sat, 6 May 2023 15:53:41 -0600
|
||||
Subject: [PATCH 4/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
|
||||
models
|
||||
|
||||
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
---
|
||||
src/mainboard/dell/e6400/devicetree.cb | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
|
||||
index bb954cbd7b..e9f3915d17 100644
|
||||
--- a/src/mainboard/dell/e6400/devicetree.cb
|
||||
+++ b/src/mainboard/dell/e6400/devicetree.cb
|
||||
@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
|
||||
ops gm45_pci_domain_ops
|
||||
|
||||
device pci 00.0 on end # host bridge
|
||||
- device pci 01.0 off end
|
||||
+ device pci 01.0 on end
|
||||
device pci 02.0 on end # VGA
|
||||
device pci 02.1 on end # Display
|
||||
device pci 03.0 on end # ME
|
||||
--
|
||||
2.39.2
|
||||
|
||||
+39
@@ -0,0 +1,39 @@
|
||||
From de4eeaf6d44cb05c60c0b0d54b43cdb88686b998 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Fri, 12 May 2023 19:55:15 -0600
|
||||
Subject: [PATCH 5/9] Remove warning for coreboot images built without a
|
||||
payload
|
||||
|
||||
I added this in upstream to prevent people from accidentally flashing
|
||||
roms without a payload resulting in a no boot situation, but in
|
||||
libreboot lbmk handles the payload and thus this warning always comes
|
||||
up. This has caused confusion and concern so just patch it out.
|
||||
---
|
||||
payloads/Makefile.mk | 13 +------------
|
||||
1 file changed, 1 insertion(+), 12 deletions(-)
|
||||
|
||||
diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
|
||||
index a2336aa876..4f1692a873 100644
|
||||
--- a/payloads/Makefile.mk
|
||||
+++ b/payloads/Makefile.mk
|
||||
@@ -49,16 +49,5 @@ distclean-payloads:
|
||||
print-repo-info-payloads:
|
||||
-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
|
||||
|
||||
-ifeq ($(CONFIG_PAYLOAD_NONE),y)
|
||||
-show_notices:: warn_no_payload
|
||||
-endif
|
||||
-
|
||||
-warn_no_payload:
|
||||
- printf "\n\t** WARNING **\n"
|
||||
- printf "coreboot has been built without a payload. Writing\n"
|
||||
- printf "a coreboot image without a payload to your board's\n"
|
||||
- printf "flash chip will result in a non-booting system. You\n"
|
||||
- printf "can use cbfstool to add a payload to the image.\n\n"
|
||||
-
|
||||
.PHONY: force-payload coreinfo nvramcui
|
||||
-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
|
||||
+.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,39 @@
|
||||
From 261454e47783b973b088e9dbea47bda02758dcb4 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 22 Oct 2023 15:02:25 +0100
|
||||
Subject: [PATCH 6/9] don't use github for the acpica download
|
||||
|
||||
i have the tarball from a previous download, and i placed
|
||||
it on libreboot rsync, which then got mirrored to princeton.
|
||||
|
||||
today, github's ssl cert was b0rking the hell out and i really
|
||||
really wanted to finish a build, and didn't want to wait for
|
||||
github to fix their httpd.
|
||||
|
||||
so i'm now hosting this specific acpica tarball on rsync.
|
||||
|
||||
this patch makes that URL be used, instead of the github one.
|
||||
|
||||
that's the 2nd time i've had to patch coreboot's acpica download!
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/crossgcc/buildgcc | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
|
||||
index 23a5caf2bb..36565a906c 100755
|
||||
--- a/util/crossgcc/buildgcc
|
||||
+++ b/util/crossgcc/buildgcc
|
||||
@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
|
||||
MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
|
||||
GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
|
||||
BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
|
||||
-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
|
||||
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
|
||||
# CLANG toolchain archive locations
|
||||
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
|
||||
CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,36 @@
|
||||
From 622daa7c46de01530de60a7be32c8b9e48b356fd Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 5 Nov 2023 22:57:08 +0000
|
||||
Subject: [PATCH 7/9] use mirrorservice.org for gcc downloads
|
||||
|
||||
the gnu.org 302 redirect often fails
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/crossgcc/buildgcc | 10 +++++-----
|
||||
1 file changed, 5 insertions(+), 5 deletions(-)
|
||||
|
||||
diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
|
||||
index 36565a906c..4d4ca06113 100755
|
||||
--- a/util/crossgcc/buildgcc
|
||||
+++ b/util/crossgcc/buildgcc
|
||||
@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
|
||||
# to the jenkins build as well, or the builder won't download it.
|
||||
|
||||
# GCC toolchain archive locations
|
||||
-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
|
||||
-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
|
||||
-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
|
||||
-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
|
||||
-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
|
||||
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
|
||||
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
|
||||
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
|
||||
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
|
||||
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
|
||||
IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
|
||||
# CLANG toolchain archive locations
|
||||
LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,223 @@
|
||||
From f26df5dff7be4b0c9d8dced1cf6ed07472a174c7 Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Mon, 10 May 2021 22:40:59 +0200
|
||||
Subject: [PATCH 8/9] nb/intel/gm45: Make DDR2 raminit work
|
||||
|
||||
List of changes:
|
||||
- Update some timing and ODT values
|
||||
- Patch RCOMP calibration to better match what MRC binaries do
|
||||
- Replay a hardcoded list of RCOMP codes after RcvEn
|
||||
|
||||
This makes raminit work at DDR2-800 speeds and fixes S3 resume as well.
|
||||
Tested on Toshiba Satellite A300-1ME with two 2 GiB DDR2-800 SO-DIMMs.
|
||||
|
||||
Change-Id: Ibaee524b8ff652ddadd66cb0eb680401b988ff7c
|
||||
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
---
|
||||
src/northbridge/intel/gm45/gm45.h | 2 +-
|
||||
src/northbridge/intel/gm45/raminit.c | 90 +++++++++++++++++--
|
||||
.../intel/gm45/raminit_rcomp_calibration.c | 27 ++++--
|
||||
3 files changed, 106 insertions(+), 13 deletions(-)
|
||||
|
||||
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
|
||||
index d929533d92..997f8a0e5a 100644
|
||||
--- a/src/northbridge/intel/gm45/gm45.h
|
||||
+++ b/src/northbridge/intel/gm45/gm45.h
|
||||
@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
|
||||
int raminit_read_vco_index(void);
|
||||
u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
|
||||
|
||||
-void raminit_rcomp_calibration(stepping_t stepping);
|
||||
+void raminit_rcomp_calibration(int ddr_type, stepping_t stepping);
|
||||
void raminit_reset_readwrite_pointers(void);
|
||||
void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
|
||||
void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
|
||||
diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
|
||||
index b7e013959a..df8f46fbbc 100644
|
||||
--- a/src/northbridge/intel/gm45/raminit.c
|
||||
+++ b/src/northbridge/intel/gm45/raminit.c
|
||||
@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping,
|
||||
}
|
||||
|
||||
/* Perform RCOMP calibration for DDR3. */
|
||||
- raminit_rcomp_calibration(stepping);
|
||||
+ raminit_rcomp_calibration(spd_type, stepping);
|
||||
|
||||
/* Run initial RCOMP. */
|
||||
mchbar_setbits32(0x418, 1 << 17);
|
||||
@@ -1117,7 +1117,7 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
|
||||
reg = (reg & ~(0xf << 10)) | (2 << 10);
|
||||
else
|
||||
reg = (reg & ~(0xf << 10)) | (3 << 10);
|
||||
- reg = (reg & ~(0x7 << 5)) | (3 << 5);
|
||||
+ reg = (reg & ~(0x7 << 5)) | (2 << 5);
|
||||
} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
|
||||
reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
|
||||
reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
|
||||
@@ -1286,11 +1286,11 @@ static void ddr2_odt_setup(const timings_t *const timings, const int sff)
|
||||
reg = (reg & ~(0xf << (44 - 32))) | (8 << (44 - 32));
|
||||
reg = (reg & ~(0xf << (40 - 32))) | (7 << (40 - 32));
|
||||
if (timings->mem_clock == MEM_CLOCK_667MT) {
|
||||
- reg = (reg & ~(0xf << (36 - 32))) | (4 << (36 - 32));
|
||||
- reg = (reg & ~(0xf << (32 - 32))) | (4 << (32 - 32));
|
||||
+ reg = (reg & ~(0xf << (36 - 32))) | (8 << (36 - 32));
|
||||
+ reg = (reg & ~(0xf << (32 - 32))) | (8 << (32 - 32));
|
||||
} else {
|
||||
- reg = (reg & ~(0xf << (36 - 32))) | (5 << (36 - 32));
|
||||
- reg = (reg & ~(0xf << (32 - 32))) | (5 << (32 - 32));
|
||||
+ reg = (reg & ~(0xf << (36 - 32))) | (9 << (36 - 32));
|
||||
+ reg = (reg & ~(0xf << (32 - 32))) | (9 << (32 - 32));
|
||||
}
|
||||
mchbar_write32(CxODT_HIGH(ch), reg);
|
||||
|
||||
@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
|
||||
raminit_write_training(timings->mem_clock, dimms, s3resume);
|
||||
}
|
||||
|
||||
+ /*
|
||||
+ * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
|
||||
+ * after receiver enable calibration, otherwise raminit sometimes
|
||||
+ * completes with non-working memory.
|
||||
+ */
|
||||
+ mchbar_write32(0x0530, 0x06060005);
|
||||
+ mchbar_write32(0x0680, 0x06060606);
|
||||
+ mchbar_write32(0x0684, 0x08070606);
|
||||
+ mchbar_write32(0x0688, 0x0e0e0c0a);
|
||||
+ mchbar_write32(0x068c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0698, 0x06060606);
|
||||
+ mchbar_write32(0x069c, 0x08070606);
|
||||
+ mchbar_write32(0x06a0, 0x0c0c0b0a);
|
||||
+ mchbar_write32(0x06a4, 0x0c0c0c0c);
|
||||
+
|
||||
+ mchbar_write32(0x06c0, 0x02020202);
|
||||
+ mchbar_write32(0x06c4, 0x03020202);
|
||||
+ mchbar_write32(0x06c8, 0x04040403);
|
||||
+ mchbar_write32(0x06cc, 0x04040404);
|
||||
+ mchbar_write32(0x06d8, 0x02020202);
|
||||
+ mchbar_write32(0x06dc, 0x03020202);
|
||||
+ mchbar_write32(0x06e0, 0x04040403);
|
||||
+ mchbar_write32(0x06e4, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0700, 0x02020202);
|
||||
+ mchbar_write32(0x0704, 0x03020202);
|
||||
+ mchbar_write32(0x0708, 0x04040403);
|
||||
+ mchbar_write32(0x070c, 0x04040404);
|
||||
+ mchbar_write32(0x0718, 0x02020202);
|
||||
+ mchbar_write32(0x071c, 0x03020202);
|
||||
+ mchbar_write32(0x0720, 0x04040403);
|
||||
+ mchbar_write32(0x0724, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0740, 0x02020202);
|
||||
+ mchbar_write32(0x0744, 0x03020202);
|
||||
+ mchbar_write32(0x0748, 0x04040403);
|
||||
+ mchbar_write32(0x074c, 0x04040404);
|
||||
+ mchbar_write32(0x0758, 0x02020202);
|
||||
+ mchbar_write32(0x075c, 0x03020202);
|
||||
+ mchbar_write32(0x0760, 0x04040403);
|
||||
+ mchbar_write32(0x0764, 0x04040404);
|
||||
+
|
||||
+ mchbar_write32(0x0780, 0x06060606);
|
||||
+ mchbar_write32(0x0784, 0x09070606);
|
||||
+ mchbar_write32(0x0788, 0x0e0e0c0b);
|
||||
+ mchbar_write32(0x078c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0798, 0x06060606);
|
||||
+ mchbar_write32(0x079c, 0x09070606);
|
||||
+ mchbar_write32(0x07a0, 0x0d0d0c0b);
|
||||
+ mchbar_write32(0x07a4, 0x0d0d0d0d);
|
||||
+
|
||||
+ mchbar_write32(0x07c0, 0x06060606);
|
||||
+ mchbar_write32(0x07c4, 0x09070606);
|
||||
+ mchbar_write32(0x07c8, 0x0e0e0c0b);
|
||||
+ mchbar_write32(0x07cc, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x07d8, 0x06060606);
|
||||
+ mchbar_write32(0x07dc, 0x09070606);
|
||||
+ mchbar_write32(0x07e0, 0x0d0d0c0b);
|
||||
+ mchbar_write32(0x07e4, 0x0d0d0d0d);
|
||||
+
|
||||
+ mchbar_write32(0x0840, 0x06060606);
|
||||
+ mchbar_write32(0x0844, 0x08070606);
|
||||
+ mchbar_write32(0x0848, 0x0e0e0c0a);
|
||||
+ mchbar_write32(0x084c, 0x0e0e0e0e);
|
||||
+ mchbar_write32(0x0858, 0x06060606);
|
||||
+ mchbar_write32(0x085c, 0x08070606);
|
||||
+ mchbar_write32(0x0860, 0x0c0c0b0a);
|
||||
+ mchbar_write32(0x0864, 0x0c0c0c0c);
|
||||
+
|
||||
+ mchbar_write32(0x0880, 0x02020202);
|
||||
+ mchbar_write32(0x0884, 0x03020202);
|
||||
+ mchbar_write32(0x0888, 0x04040403);
|
||||
+ mchbar_write32(0x088c, 0x04040404);
|
||||
+ mchbar_write32(0x0898, 0x02020202);
|
||||
+ mchbar_write32(0x089c, 0x03020202);
|
||||
+ mchbar_write32(0x08a0, 0x04040403);
|
||||
+ mchbar_write32(0x08a4, 0x04040404);
|
||||
+
|
||||
igd_compute_ggc(sysinfo);
|
||||
|
||||
/* Program final memory map (with real values). */
|
||||
diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
index aef863f05a..b74765fd9c 100644
|
||||
--- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
|
||||
@@ -161,11 +161,13 @@ static void lookup_and_write(const int a1step,
|
||||
mchbar += 4;
|
||||
}
|
||||
}
|
||||
-void raminit_rcomp_calibration(const stepping_t stepping) {
|
||||
+void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
|
||||
const int a1step = stepping >= STEPPING_CONVERSION_A1;
|
||||
|
||||
int i;
|
||||
|
||||
+ char magic_comp[2] = {0};
|
||||
+
|
||||
enum {
|
||||
PULL_UP = 0,
|
||||
PULL_DOWN = 1,
|
||||
@@ -196,6 +198,10 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
|
||||
reg = mchbar_read32(0x518);
|
||||
lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
|
||||
lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
|
||||
+ if (i == 1) {
|
||||
+ magic_comp[0] = (reg >> 8) & 0x3f;
|
||||
+ magic_comp[1] = (reg >> 0) & 0x3f;
|
||||
+ }
|
||||
}
|
||||
/* Cleanup? */
|
||||
mchbar_setbits32(0x400, 1 << 3);
|
||||
@@ -216,13 +222,19 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
|
||||
for (channel = 0; channel < 2; ++channel) {
|
||||
for (group = 0; group < 6; ++group) {
|
||||
for (pu_pd = PULL_DOWN; pu_pd >= PULL_UP; --pu_pd) {
|
||||
- lookup_and_write(
|
||||
- a1step,
|
||||
- lut_idx[channel][group][pu_pd] - 7,
|
||||
- ddr3_lookup_schedule[group][pu_pd],
|
||||
- mchbar);
|
||||
+ if (ddr_type == DDR3) {
|
||||
+ lookup_and_write(
|
||||
+ a1step,
|
||||
+ lut_idx[channel][group][pu_pd] - 7,
|
||||
+ ddr3_lookup_schedule[group][pu_pd],
|
||||
+ mchbar);
|
||||
+ }
|
||||
mchbar += 0x0018;
|
||||
}
|
||||
+ if (ddr_type == DDR2) {
|
||||
+ mchbar_clrsetbits32(mchbar + 0, 0x7f << 24, lut_idx[channel][group][PULL_DOWN] << 24);
|
||||
+ mchbar_clrsetbits32(mchbar + 4, 0x7f << 0, lut_idx[channel][group][PULL_UP] << 0);
|
||||
+ }
|
||||
mchbar += 0x0010;
|
||||
/* Channel B knows only the first two groups. */
|
||||
if ((1 == channel) && (1 == group))
|
||||
@@ -230,4 +242,7 @@ void raminit_rcomp_calibration(const stepping_t stepping) {
|
||||
}
|
||||
mchbar += 0x0040;
|
||||
}
|
||||
+
|
||||
+ mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
|
||||
+ mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
|
||||
}
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,23 @@
|
||||
From f318da0563ecb2386ac368e04bad88a8aacbc83d Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Wed, 1 Nov 2023 16:33:11 +0000
|
||||
Subject: [PATCH 9/9] dell/e6400: crank up vram to 256MB (max)
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
src/mainboard/dell/e6400/cmos.default | 2 +-
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
|
||||
index eeb6f47364..25dfa38cb5 100644
|
||||
--- a/src/mainboard/dell/e6400/cmos.default
|
||||
+++ b/src/mainboard/dell/e6400/cmos.default
|
||||
@@ -2,4 +2,4 @@ boot_option=Fallback
|
||||
debug_level=Debug
|
||||
power_on_after_fail=Disable
|
||||
sata_mode=AHCI
|
||||
-gfx_uma_size=32M
|
||||
+gfx_uma_size=256M
|
||||
--
|
||||
2.39.2
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
tree="dell"
|
||||
tree_depend="default"
|
||||
xtree="default"
|
||||
rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"
|
||||
@@ -0,0 +1,634 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,631 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,7 @@
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_seabios_grubonly="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="ahci"
|
||||
@@ -0,0 +1,636 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x10000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_HAVE_MRC=y
|
||||
CONFIG_MRC_FILE="../../../mrc/haswell/mrc.bin"
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
# CONFIG_USE_NATIVE_RAMINIT is not set
|
||||
# CONFIG_USE_BROADWELL_MRC is not set
|
||||
# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,633 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x10000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_HAVE_MRC=y
|
||||
CONFIG_MRC_FILE="../../../mrc/haswell/mrc.bin"
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
# CONFIG_USE_NATIVE_RAMINIT is not set
|
||||
# CONFIG_USE_BROADWELL_MRC is not set
|
||||
# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,7 @@
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_seabios_grubonly="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="ahci"
|
||||
@@ -0,0 +1,636 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x10000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_EHCI_BAR=0xd8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_HAVE_MRC=y
|
||||
CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin"
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
# CONFIG_USE_NATIVE_RAMINIT is not set
|
||||
CONFIG_USE_BROADWELL_MRC=y
|
||||
# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,633 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 MT"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE="overridetree_mt.cb"
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x10000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 MT"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_EHCI_BAR=0xd8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_HAVE_MRC=y
|
||||
CONFIG_MRC_FILE="../../../mrc/broadwell/mrc.bin"
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
# CONFIG_USE_NATIVE_RAMINIT is not set
|
||||
CONFIG_USE_BROADWELL_MRC=y
|
||||
# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,7 @@
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_seabios_grubonly="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="ahci"
|
||||
@@ -0,0 +1,634 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,631 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x40000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x20000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
CONFIG_VGA_TEXT_FRAMEBUFFER=y
|
||||
# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
CONFIG_VGA=y
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_RAM_SETUP=y
|
||||
# CONFIG_DEBUG_RAM_SETUP is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
@@ -0,0 +1,7 @@
|
||||
tree="default"
|
||||
xarch="i386-elf"
|
||||
payload_seabios="y"
|
||||
payload_seabios_withgrub="y"
|
||||
payload_seabios_grubonly="y"
|
||||
payload_memtest="y"
|
||||
grub_scan_disk="ahci"
|
||||
@@ -0,0 +1,636 @@
|
||||
#
|
||||
# Automatically generated file; DO NOT EDIT.
|
||||
# coreboot configuration
|
||||
#
|
||||
|
||||
#
|
||||
# General setup
|
||||
#
|
||||
CONFIG_COREBOOT_BUILD=y
|
||||
CONFIG_LOCALVERSION=""
|
||||
CONFIG_CBFS_PREFIX="fallback"
|
||||
CONFIG_COMPILER_GCC=y
|
||||
# CONFIG_COMPILER_LLVM_CLANG is not set
|
||||
CONFIG_ARCH_SUPPORTS_CLANG=y
|
||||
# CONFIG_ANY_TOOLCHAIN is not set
|
||||
# CONFIG_CCACHE is not set
|
||||
# CONFIG_IWYU is not set
|
||||
# CONFIG_FMD_GENPARSER is not set
|
||||
# CONFIG_UTIL_GENPARSER is not set
|
||||
# CONFIG_OPTION_BACKEND_NONE is not set
|
||||
CONFIG_USE_OPTION_TABLE=y
|
||||
CONFIG_STATIC_OPTION_TABLE=y
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
|
||||
CONFIG_USE_BLOBS=y
|
||||
# CONFIG_USE_AMD_BLOBS is not set
|
||||
# CONFIG_USE_QC_BLOBS is not set
|
||||
# CONFIG_COVERAGE is not set
|
||||
# CONFIG_UBSAN is not set
|
||||
CONFIG_HAVE_ASAN_IN_ROMSTAGE=y
|
||||
CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
|
||||
# CONFIG_ASAN is not set
|
||||
CONFIG_NO_STAGE_CACHE=y
|
||||
# CONFIG_TSEG_STAGE_CACHE is not set
|
||||
# CONFIG_UPDATE_IMAGE is not set
|
||||
# CONFIG_BOOTSPLASH_IMAGE is not set
|
||||
# CONFIG_FW_CONFIG is not set
|
||||
|
||||
#
|
||||
# Software Bill Of Materials (SBOM)
|
||||
#
|
||||
# CONFIG_SBOM is not set
|
||||
# end of Software Bill Of Materials (SBOM)
|
||||
# end of General setup
|
||||
|
||||
#
|
||||
# Mainboard
|
||||
#
|
||||
|
||||
#
|
||||
# Important: Run 'make distclean' before switching boards
|
||||
#
|
||||
# CONFIG_VENDOR_51NB is not set
|
||||
# CONFIG_VENDOR_ACER is not set
|
||||
# CONFIG_VENDOR_ADLINK is not set
|
||||
# CONFIG_VENDOR_AMD is not set
|
||||
# CONFIG_VENDOR_AOPEN is not set
|
||||
# CONFIG_VENDOR_APPLE is not set
|
||||
# CONFIG_VENDOR_ASROCK is not set
|
||||
# CONFIG_VENDOR_ASUS is not set
|
||||
# CONFIG_VENDOR_BIOSTAR is not set
|
||||
# CONFIG_VENDOR_BOSTENTECH is not set
|
||||
# CONFIG_VENDOR_BYTEDANCE is not set
|
||||
# CONFIG_VENDOR_CAVIUM is not set
|
||||
# CONFIG_VENDOR_CLEVO is not set
|
||||
# CONFIG_VENDOR_COMPULAB is not set
|
||||
CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_EMULATION is not set
|
||||
# CONFIG_VENDOR_EXAMPLE is not set
|
||||
# CONFIG_VENDOR_FACEBOOK is not set
|
||||
# CONFIG_VENDOR_FOXCONN is not set
|
||||
# CONFIG_VENDOR_GETAC is not set
|
||||
# CONFIG_VENDOR_GIGABYTE is not set
|
||||
# CONFIG_VENDOR_GOOGLE is not set
|
||||
# CONFIG_VENDOR_HP is not set
|
||||
# CONFIG_VENDOR_IBASE is not set
|
||||
# CONFIG_VENDOR_IBM is not set
|
||||
# CONFIG_VENDOR_INTEL is not set
|
||||
# CONFIG_VENDOR_INVENTEC is not set
|
||||
# CONFIG_VENDOR_KONTRON is not set
|
||||
# CONFIG_VENDOR_LENOVO is not set
|
||||
# CONFIG_VENDOR_LIBRETREND is not set
|
||||
# CONFIG_VENDOR_MSI is not set
|
||||
# CONFIG_VENDOR_OCP is not set
|
||||
# CONFIG_VENDOR_OPENCELLULAR is not set
|
||||
# CONFIG_VENDOR_PACKARDBELL is not set
|
||||
# CONFIG_VENDOR_PCENGINES is not set
|
||||
# CONFIG_VENDOR_PINE64 is not set
|
||||
# CONFIG_VENDOR_PORTWELL is not set
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
# CONFIG_VENDOR_SAMSUNG is not set
|
||||
# CONFIG_VENDOR_SAPPHIRE is not set
|
||||
# CONFIG_VENDOR_SIEMENS is not set
|
||||
# CONFIG_VENDOR_SIFIVE is not set
|
||||
# CONFIG_VENDOR_STARLABS is not set
|
||||
# CONFIG_VENDOR_SUPERMICRO is not set
|
||||
# CONFIG_VENDOR_SYSTEM76 is not set
|
||||
# CONFIG_VENDOR_TI is not set
|
||||
# CONFIG_VENDOR_UP is not set
|
||||
CONFIG_BOARD_SPECIFIC_OPTIONS=y
|
||||
CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_MAINBOARD_VERSION="1.0"
|
||||
CONFIG_MAINBOARD_DIR="dell/optiplex_9020"
|
||||
CONFIG_VGA_BIOS_ID="8086,0166"
|
||||
CONFIG_DIMM_MAX=4
|
||||
CONFIG_DIMM_SPD_SIZE=256
|
||||
CONFIG_FMDFILE=""
|
||||
# CONFIG_NO_POST is not set
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0x800000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=8
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
CONFIG_UART_FOR_CONSOLE=0
|
||||
CONFIG_DEVICETREE="devicetree.cb"
|
||||
# CONFIG_VBOOT is not set
|
||||
CONFIG_OVERRIDE_DEVICETREE=""
|
||||
# CONFIG_VGA_BIOS is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
|
||||
CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
|
||||
# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
|
||||
CONFIG_PS2K_EISAID="PNP0303"
|
||||
CONFIG_PS2M_EISAID="PNP0F13"
|
||||
CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
|
||||
CONFIG_ECAM_MMCONF_BUS_NUMBER=64
|
||||
CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
|
||||
CONFIG_DCACHE_RAM_BASE=0xff7c0000
|
||||
CONFIG_DCACHE_RAM_SIZE=0x10000
|
||||
CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
|
||||
CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
|
||||
CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
|
||||
CONFIG_HAVE_INTEL_FIRMWARE=y
|
||||
CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
|
||||
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_SPI_FLASH_WINBOND=y
|
||||
CONFIG_DRIVERS_INTEL_WIFI=y
|
||||
CONFIG_IFD_BIN_PATH="../../../config/ifd/dell9020mt/12_ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/t440p/me.bin"
|
||||
CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
# CONFIG_DEBUG_SMI is not set
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 7020/9020 SFF"
|
||||
CONFIG_HAVE_IFD_BIN=y
|
||||
CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
|
||||
CONFIG_TTYS0_BAUD=115200
|
||||
CONFIG_D3COLD_SUPPORT=y
|
||||
CONFIG_PCIEXP_ASPM=y
|
||||
CONFIG_PCIEXP_L1_SUB_STATE=y
|
||||
CONFIG_PCIEXP_CLK_PM=y
|
||||
CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB=12288
|
||||
CONFIG_ROM_SIZE=0x00c00000
|
||||
CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
|
||||
CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
|
||||
CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
|
||||
# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
|
||||
# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
|
||||
CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
|
||||
# end of Mainboard
|
||||
|
||||
#
|
||||
# Chipset
|
||||
#
|
||||
|
||||
#
|
||||
# SoC
|
||||
#
|
||||
CONFIG_CHIPSET_DEVICETREE=""
|
||||
CONFIG_CBFS_MCACHE_SIZE=0x4000
|
||||
CONFIG_ROMSTAGE_ADDR=0x2000000
|
||||
CONFIG_VERSTAGE_ADDR=0x2000000
|
||||
CONFIG_SMM_TSEG_SIZE=0x800000
|
||||
CONFIG_SMM_RESERVED_SIZE=0x100000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x400
|
||||
CONFIG_SERIRQ_CONTINUOUS_MODE=y
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_EHCI_BAR=0xe8000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
CONFIG_STACK_SIZE=0x2000
|
||||
CONFIG_IED_REGION_SIZE=0x400000
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
|
||||
CONFIG_HAVE_MRC=y
|
||||
CONFIG_MRC_FILE="../../../mrc/haswell/mrc.bin"
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x30000
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0x400
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
|
||||
#
|
||||
# CPU
|
||||
#
|
||||
CONFIG_CPU_INTEL_HASWELL=y
|
||||
CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
|
||||
CONFIG_CPU_INTEL_COMMON=y
|
||||
CONFIG_ENABLE_VMX=y
|
||||
CONFIG_SET_IA32_FC_LOCK_BIT=y
|
||||
CONFIG_SET_MSR_AESNI_LOCK_BIT=y
|
||||
CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
|
||||
CONFIG_CPU_INTEL_COMMON_VOLTAGE=y
|
||||
CONFIG_CPU_INTEL_COMMON_SMM=y
|
||||
CONFIG_PARALLEL_MP=y
|
||||
CONFIG_XAPIC_ONLY=y
|
||||
# CONFIG_X2APIC_ONLY is not set
|
||||
# CONFIG_X2APIC_RUNTIME is not set
|
||||
# CONFIG_X2APIC_LATE_WORKAROUND is not set
|
||||
CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
CONFIG_SSE=y
|
||||
CONFIG_SSE2=y
|
||||
CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
|
||||
CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
|
||||
CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
|
||||
# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
|
||||
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
# CONFIG_USE_NATIVE_RAMINIT is not set
|
||||
# CONFIG_USE_BROADWELL_MRC is not set
|
||||
# CONFIG_HASWELL_HIDE_PEG_FROM_MRC is not set
|
||||
|
||||
#
|
||||
# Southbridge
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
|
||||
CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
CONFIG_INTEL_CHIPSET_LOCKDOWN=y
|
||||
CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
|
||||
CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
|
||||
CONFIG_RCBA_LENGTH=0x4000
|
||||
|
||||
#
|
||||
# Super I/O
|
||||
#
|
||||
CONFIG_SUPERIO_SMSC_SCH555x=y
|
||||
|
||||
#
|
||||
# Embedded Controllers
|
||||
#
|
||||
|
||||
#
|
||||
# Intel Firmware
|
||||
#
|
||||
CONFIG_HAVE_ME_BIN=y
|
||||
# CONFIG_STITCH_ME_BIN is not set
|
||||
# CONFIG_CHECK_ME is not set
|
||||
# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
|
||||
# CONFIG_USE_ME_CLEANER is not set
|
||||
CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
|
||||
CONFIG_HAVE_GBE_BIN=y
|
||||
# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
|
||||
# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
|
||||
CONFIG_UNLOCK_FLASH_REGIONS=y
|
||||
CONFIG_ARCH_X86=y
|
||||
CONFIG_ARCH_BOOTBLOCK_X86_32=y
|
||||
CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
CONFIG_BOOTBLOCK_SIMPLE=y
|
||||
# CONFIG_BOOTBLOCK_NORMAL is not set
|
||||
CONFIG_COLLECT_TIMESTAMPS_TSC=y
|
||||
CONFIG_HAVE_CF9_RESET=y
|
||||
CONFIG_DEBUG_HW_BREAKPOINTS=y
|
||||
CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
|
||||
# CONFIG_DUMP_SMBIOS_TYPE17 is not set
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
# Devices
|
||||
#
|
||||
CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
|
||||
CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
|
||||
CONFIG_MAINBOARD_USE_LIBGFXINIT=y
|
||||
# CONFIG_VGA_ROM_RUN is not set
|
||||
# CONFIG_NO_GFX_INIT is not set
|
||||
CONFIG_NO_EARLY_GFX_INIT=y
|
||||
|
||||
#
|
||||
# Display
|
||||
#
|
||||
# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
|
||||
CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER=y
|
||||
# CONFIG_BOOTSPLASH is not set
|
||||
# end of Display
|
||||
|
||||
CONFIG_PCI=y
|
||||
CONFIG_ECAM_MMCONF_SUPPORT=y
|
||||
CONFIG_PCIX_PLUGIN_SUPPORT=y
|
||||
CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
|
||||
CONFIG_PCIEXP_PLUGIN_SUPPORT=y
|
||||
CONFIG_ECAM_MMCONF_LENGTH=0x04000000
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER=y
|
||||
CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
|
||||
CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
|
||||
# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
|
||||
# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
|
||||
# CONFIG_EARLY_PCI_BRIDGE is not set
|
||||
CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
|
||||
CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
|
||||
CONFIG_INTEL_GMA_HAVE_VBT=y
|
||||
CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_USE_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
# Generic Drivers
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_ELOG is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
# CONFIG_MRC_SETTINGS_PROTECT is not set
|
||||
# CONFIG_SMMSTORE is not set
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
|
||||
# CONFIG_SPI_FLASH_NO_FAST_READ is not set
|
||||
CONFIG_SPI_FLASH_ADESTO=y
|
||||
CONFIG_SPI_FLASH_AMIC=y
|
||||
CONFIG_SPI_FLASH_ATMEL=y
|
||||
CONFIG_SPI_FLASH_EON=y
|
||||
CONFIG_SPI_FLASH_MACRONIX=y
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_SPI_FLASH_SST=y
|
||||
CONFIG_SPI_FLASH_ISSI=y
|
||||
CONFIG_HAVE_EM100PRO_SPI_CONSOLE_SUPPORT=y
|
||||
CONFIG_DRIVERS_UART=y
|
||||
# CONFIG_DRIVERS_UART_OXPCIE is not set
|
||||
CONFIG_HAVE_USBDEBUG=y
|
||||
CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_USBDEBUG is not set
|
||||
# CONFIG_VPD is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
|
||||
# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
|
||||
CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
|
||||
CONFIG_GFX_GMA=y
|
||||
CONFIG_GFX_GMA_DYN_CPU=y
|
||||
CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
|
||||
# CONFIG_DRIVERS_SIL_3114 is not set
|
||||
CONFIG_DRIVERS_WIFI_GENERIC=y
|
||||
# end of Generic Drivers
|
||||
|
||||
#
|
||||
# Security
|
||||
#
|
||||
|
||||
#
|
||||
# CBFS verification
|
||||
#
|
||||
# CONFIG_CBFS_VERIFICATION is not set
|
||||
# end of CBFS verification
|
||||
|
||||
#
|
||||
# Verified Boot (vboot)
|
||||
#
|
||||
# end of Verified Boot (vboot)
|
||||
|
||||
#
|
||||
# Trusted Platform Module
|
||||
#
|
||||
CONFIG_NO_TPM=y
|
||||
CONFIG_PCR_BOOT_MODE=1
|
||||
CONFIG_PCR_HWID=1
|
||||
CONFIG_PCR_SRTM=2
|
||||
CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
|
||||
# end of Memory initialization
|
||||
|
||||
# CONFIG_STM is not set
|
||||
# CONFIG_INTEL_CBNT_SUPPORT is not set
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
|
||||
CONFIG_ACPI_SOC_NVS=y
|
||||
CONFIG_ACPI_NO_CUSTOM_MADT=y
|
||||
CONFIG_ACPI_COMMON_MADT_LAPIC=y
|
||||
CONFIG_ACPI_COMMON_MADT_IOAPIC=y
|
||||
CONFIG_HAVE_ACPI_TABLES=y
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH=y
|
||||
CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
|
||||
CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
|
||||
CONFIG_RTC=y
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
|
||||
#
|
||||
# Console
|
||||
#
|
||||
CONFIG_BOOTBLOCK_CONSOLE=y
|
||||
CONFIG_POSTCAR_CONSOLE=y
|
||||
CONFIG_SQUELCH_EARLY_SMP=y
|
||||
|
||||
#
|
||||
# I/O mapped, 8250-compatible
|
||||
#
|
||||
CONFIG_TTYS0_BASE=0x3f8
|
||||
|
||||
#
|
||||
# Serial port base address = 0x3f8
|
||||
#
|
||||
# CONFIG_CONSOLE_SERIAL_921600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_460800 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_230400 is not set
|
||||
CONFIG_CONSOLE_SERIAL_115200=y
|
||||
# CONFIG_CONSOLE_SERIAL_57600 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_38400 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_19200 is not set
|
||||
# CONFIG_CONSOLE_SERIAL_9600 is not set
|
||||
CONFIG_TTYS0_LCS=3
|
||||
# CONFIG_SPKMODEM is not set
|
||||
# CONFIG_CONSOLE_NE2K is not set
|
||||
CONFIG_CONSOLE_CBMEM=y
|
||||
# CONFIG_CONSOLE_SPI_FLASH is not set
|
||||
# CONFIG_CONSOLE_I2C_SMBUS is not set
|
||||
# CONFIG_EM100PRO_SPI_CONSOLE is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
|
||||
# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
|
||||
CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
|
||||
CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
|
||||
CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
|
||||
# CONFIG_CMOS_POST is not set
|
||||
CONFIG_POST_DEVICE_NONE=y
|
||||
# CONFIG_POST_DEVICE_LPC is not set
|
||||
# CONFIG_POST_DEVICE_PCI_PCIE is not set
|
||||
CONFIG_POST_IO_PORT=0x80
|
||||
CONFIG_HWBASE_DEBUG_CB=y
|
||||
# end of Console
|
||||
|
||||
CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
# System tables
|
||||
#
|
||||
CONFIG_GENERATE_SMBIOS_TABLES=y
|
||||
CONFIG_BIOS_VENDOR="coreboot"
|
||||
CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
|
||||
# end of System tables
|
||||
|
||||
#
|
||||
# Payload
|
||||
#
|
||||
CONFIG_PAYLOAD_NONE=y
|
||||
# end of Payload
|
||||
|
||||
#
|
||||
# Debugging
|
||||
#
|
||||
|
||||
#
|
||||
# CPU Debug Settings
|
||||
#
|
||||
# CONFIG_DISPLAY_MTRRS is not set
|
||||
|
||||
#
|
||||
# Vendorcode Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# BLOB Debug Settings
|
||||
#
|
||||
|
||||
#
|
||||
# General Debug Settings
|
||||
#
|
||||
# CONFIG_GDB_STUB is not set
|
||||
# CONFIG_FATAL_ASSERTS is not set
|
||||
# CONFIG_DEBUG_CBFS is not set
|
||||
CONFIG_HAVE_DEBUG_SMBUS=y
|
||||
# CONFIG_DEBUG_SMBUS is not set
|
||||
# CONFIG_DEBUG_MALLOC is not set
|
||||
# CONFIG_DEBUG_CONSOLE_INIT is not set
|
||||
# CONFIG_DEBUG_SPI_FLASH is not set
|
||||
# CONFIG_DEBUG_BOOT_STATE is not set
|
||||
# CONFIG_DEBUG_ADA_CODE is not set
|
||||
CONFIG_HAVE_EM100_SUPPORT=y
|
||||
# CONFIG_EM100 is not set
|
||||
# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
|
||||
# end of Debugging
|
||||
|
||||
CONFIG_RAMSTAGE_ADA=y
|
||||
CONFIG_RAMSTAGE_LIBHWBASE=y
|
||||
CONFIG_HWBASE_DYNAMIC_MMIO=y
|
||||
CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
|
||||
CONFIG_HWBASE_DIRECT_PCIDEV=y
|
||||
CONFIG_DECOMPRESS_OFAST=y
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_HAVE_BOOTBLOCK=y
|
||||
CONFIG_HAVE_ROMSTAGE=y
|
||||
CONFIG_HAVE_RAMSTAGE=y
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user