Add config for Dell OptiPlex 3050 Micro

This is using Mate Kukri's port, which was added in previous lbmk revisions. I've added an IFD that sets the HAP bit, and unlocks regions as standard. vcfg is set to 3050micro, which defines downloading of the MEv11 image and it will run deguard automatically. I made a small adjustment to vendor.sh, because the hotpatch logic for deguard uses -C in git, and when doing that, the specified directory path is relative to that Git repository; the .patch path has been adjusted accordingly. Also add 3rdparty/fsp to coreboot/default modules. This board requires the ifdtool option: -p sklkbl The -p option tells flashrom what quirks are present in a given IFD. We don't normally need this on other Libreboot targets that we currently support. The -p option was needed for creating this modified IFD, and it is therefore needed in the inject script. Therefore, an "IFD_platform" option is specified in a given board's target.cfg file. If this is set, another variable is set that makes -p be used. In this case, 3050's target.cfg says: IFD_platform="sklkbl" This option enables quirks for skylake/kabylake descriptors, as required when using ifdtool. Signed-off-by: Leah Rowe <leah@libreboot.org>
2026-07-11 14:02:52 +02:00 · 2024-09-24 23:47:33 +01:00
1088 changed files with 30899 additions and 81195 deletions
@@ -24,8 +24,6 @@
 /push
 /version
 /versiondate
-/.version
-/.versiondate
 /vendorfiles/
 *me.bin
 *sch5545ec.bin
@@ -36,12 +34,3 @@
 /todo.txt
 /lock
 /hash/
-/dump/
-/qrun*.sh
-*.tar.*
-/m
-/f
-/r
-/e
-/xbmkpath/
-/xbmkwd/
@@ -1,57 +1,123 @@
 Libreboot
 =========

-Documentation: [libreboot.org](https://libreboot.org)\
-Support: [\#libreboot](https://web.libera.chat/#libreboot) on
-  [Libera](https://libera.chat/) IRC
+Find libreboot documentation at <https://libreboot.org/>

-Libreboot provides 
-[libre](https://libreboot.org/freedom-status.html)
-boot firmware on
-[supported motherboards](https://libreboot.org/docs/install/#which-systems-are-supported-by-libreboot). It replaces proprietary vendor BIOS/UEFI implementations, by
-* Using coreboot to initialize the hardware (e.g. memory controller, CPU, etc.) while
-  minimizing unwanted functionality (e.g. backdoors such as the Intel Management Engine)
-* ... which runs a payload such as SeaBIOS, GRUB, or U-Boot
-* ... which loads your operating system's boot loader (BSD and Linux-based
-  [systems](systems) are supported).
+The `libreboot` project provides
+[libre](https://libreboot.org/freedom-status.html) *boot
+firmware* that initializes the hardware (e.g. memory controller, CPU,
+peripherals) on specific Intel/AMD x86 and ARM targets, which
+then starts a bootloader for your operating system. Linux/BSD are
+well-supported. It replaces proprietary BIOS/UEFI firmware. Help is available
+via [\#libreboot IRC](https://web.libera.chat/#libreboot)
+on [Libera](https://libera.chat/) IRC.

-Why use Libreboot, and what is coreboot?
----------------------------------------
+Why use Libreboot?
+==================

-A lot of users who use libre operating systems still use proprietary boot
-firmware, which often contain backdoors and bugs, hampering
-[user freedom](https://writefreesoftware.org) and
-[right to repair](https://www.eff.org/issues/right-to-repair).
+Why should you use *libreboot*?
+----------------------------

-[coreboot](https://coreboot.org) provides libre boot firmware by initializing
-the hardware then running a payload. However, coreboot is notoriously difficult
-to configure and install for most non-technical users, requiring detailed
-technical knowledge of hardware.
+Libreboot gives you freedoms that you otherwise can't get with most other
+boot firmware. It's extremely powerful and configurable for many use cases.

-Libreboot solves this by being **a coreboot distribution** (in the same way
-that Alpine Linux is a Linux distribution). It provides a fully automated build
-system that downloads and compiles pre-configured ROM images for supported
-motherboards, so end-users could easily fetch images to flash onto their
-devices.
+You have rights. The right to privacy, freedom of thought, freedom of speech
+and the right to read. In this context, Libreboot gives you these rights.
+Your freedom matters.
+[Right to repair](https://vid.puffyan.us/watch?v=Npd_xDuNi9k) matters.
+Many people use proprietary (non-libre)
+boot firmware, even if they use [a libre OS](https://www.openbsd.org/).
+Proprietary firmware often contains backdoors (more info on the FAQ), and it
+and can be buggy. The libreboot project was founded in December 2013,
+with the express purpose of making coreboot firmware accessible for
+non-technical users.

-Libreboot also produces documentation aimed at non-technical users and
-excellent user support via IRC.
+The `libreboot` project uses [coreboot](https://www.coreboot.org/) for [hardware
+initialisation](https://doc.coreboot.org/getting_started/architecture.html).
+Coreboot is notoriously difficult to install for most non-technical users; it
+handles only basic initialization and jumps to a separate
+[payload](https://doc.coreboot.org/payloads.html) program (e.g.
+[GRUB](https://www.gnu.org/software/grub/),
+[Tianocore](https://www.tianocore.org/)), which must also be configured.
+*The libreboot software solves this problem*; it is a *coreboot distribution* with
+an automated build system (named *lbmk*) that builds complete *ROM images*, for
+more robust installation. Documentation is provided.

-Contribute
----------
+How does Libreboot differ from coreboot?
+========================================
+
+In the same way that *Debian* is a GNU+Linux distribution, `libreboot` is
+a *coreboot distribution*. If you want to build a ROM image from scratch, you
+otherwise have to perform expert-level configuration of coreboot, GRUB and
+whatever other software you need, to prepare the ROM image. With *libreboot*,
+you can literally download from Git or a source archive, and run `make`, and it
+will build entire ROM images. An automated build system, named `lbmk`
+(Libreboot MaKe), builds these ROM images automatically, without any user input
+or intervention required. Configuration has already been performed in advance.
+
+If you were to build regular coreboot, without using libreboot's automated
+build system, it would require a lot more intervention and decent technical
+knowledge to produce a working configuration.
+
+Regular binary releases of `libreboot` provide these
+ROM images pre-compiled, and you can simply install them, with no special
+knowledge or skill except the ability to follow installation instructions
+and run commands BSD/Linux.
+
+Project goals
+=============
+
+-   *Support as much hardware as possible!* Libreboot aims to eventually
+    have *maintainers* for every board supported by coreboot, at every
+    point in time.
+-   *Make coreboot easy to use*. Coreboot is notoriously difficult
+    to install, due to an overall lack of user-focused documentation
+    and support. Most people will simply give up before attempting to
+    install coreboot. Libreboot's automated build system and user-friendly
+    installation instructions solves this problem.
+
+Libreboot attempts to bridge this divide by providing a build system
+automating much of the coreboot image creation and customization.
+Secondly, the project produces documentation aimed at non-technical users.
+Thirdly, the project attempts to provide excellent user support via IRC.
+
+Libreboot already comes with a payload (GRUB), flashprog and other
+needed parts. Everything is fully integrated, in a way where most of
+the complicated steps that are otherwise required, are instead done
+for the user in advance.
+
+You can download ROM images for your libreboot system and install
+them without having to build anything from source. If, however, you are
+interested in building your own image, the build system makes it relatively
+easy to do so.
+
+Not a coreboot fork!
+--------------------
+
+Libreboot is *not a fork of coreboot*. Every so often, the project
+re-bases on the latest version of coreboot, with the number of custom
+patches in use minimized. Tested, *stable* (static) releases are then provided
+in Libreboot, based on specific coreboot revisions.
+
+How to help
+===========

 You can check bugs listed on
 the [bug tracker](https://codeberg.org/libreboot/lbmk/issues).

-You may use Codeberg pull requests to send patches with bug fixes or other
-improvements. This repository hosts the code for the main build system.
-The website lives in [a separate repository](https://codeberg.org/libreboot/lbwww).
+If you spot a bug and have a fix, the website has instructions for how to send
+patches, and you can also report it. Also, this entire website is
+written in Markdown and hosted in a [separate
+repository](https://codeberg.org/libreboot/lbwww) where you can send patches.

-Development is also done on the IRC channel.
+Any and all development discussion and user support are all done on the IRC
+channel. More information is on <https://libreboot.org/contact.html>.

-License for this README
-----------------------
+LICENSE FOR THIS README
+=======================

-It's just a README file. It is released under
-[Creative Commons Zero, version 1.0](https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt).
+It's just a README file. This README file is released under the terms of the
+Creative Commons Zero license, version 1.0 of the license, which you can
+read here:

+<https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt>
@@ -0,0 +1,132 @@
+#!/usr/bin/env sh
+# SPDX-License-Identifier: GPL-3.0-or-later
+# Copyright (c) 2014-2015,2020-2024 Leah Rowe <leah@libreboot.org>
+# Copyright (c) 2015 Patrick "P. J." McDermott <pj@pehjota.net>
+# Copyright (c) 2015-2016 Klemens Nanni <contact@autoboot.org>
+# Copyright (c) 2022 Caleb La Grange <thonkpeasant@protonmail.com>
+
+set -u -e
+
+if [ "./${0##*/}" != "${0}" ] || [ ! -f "build" ] || [ -L "build" ]; then
+	printf "You must run this in the proper work directory.\n" 1>&2
+	exit 1
+fi
+
+. "include/lib.sh"
+. "include/vendor.sh"
+. "include/mrc.sh"
+
+eval `setvars "" vdir src_dirname srcdir mode xp ser`
+err="fail"
+
+main()
+{
+	[ $# -lt 1 ] && $err "bad command"
+	spath="script/$1"; shcmd="shift 1"
+	[ "${1#-*}" != "$1" ] && spath="script/trees" && shcmd=":"
+
+	for g in "which git" "git config --global user.name" \
+	    "git config --global user.email" "git_init"; do
+		eval "$g 1>/dev/null 2>/dev/null || $err \"Unconfigured: $g\""
+	done
+
+	case "${spath#script/}" in
+	version) printf "%s\nWebsite: %s\n" "$relname" "$projectsite" ;;
+	release) shift 1; mkrelease $@ ;;
+	inject) shift 1; vendor_inject $@ ;;
+	download) shift 1; vendor_download $@ ;;
+	roms)
+		[ $# -gt 1 ] && [ "$2" = "serprog" ] && \
+		    mk -b stm32-vserprog pico-serprog && return 0
+		shift 1; x_ ./mk -b coreboot $@ ;;
+	*)
+		[ -f "$spath" ] || $err "bad command"
+		$shcmd; "$spath" $@ || $err "excmd: $spath $(echo "$@")" ;;
+	esac
+	set -u -e # some commands disable them. turn them on!
+}
+
+git_init()
+{
+	[ -L ".git" ] && return 1
+	[ -e ".git" ] && return 0
+	eval `setvars "$(date -Rud @$versiondate)" cdate _nogit`
+
+	git init || return 1
+	git add -A . || return 1
+	git commit -m "$projectname $version" --date "$cdate" \
+	    --author="xbmk <xbmk@example.com>" || return 1
+	git tag -a "$version" -m "$projectname $version" || return 1
+}
+
+mkrelease()
+{
+	export XBMK_RELEASE="y"
+
+	vdir="release"
+	while getopts d:m: option; do
+		[ -z "$OPTARG" ] && $err "empty argument not allowed"
+		case "$option" in
+		d) vdir="$OPTARG" ;;
+		m) mode="$OPTARG" ;;
+		*) $err "invalid option '-$option'" ;;
+		esac
+	done
+
+	vdir="$vdir/$version"
+	src_dirname="${relname}_src"
+	srcdir="$vdir/$src_dirname"
+
+	[ -e "$vdir" ] && $err "already exists: \"$vdir\""
+	mkdir -p "$vdir" || $err "mkvdir: !mkdir -p \"$vdir\""
+	git clone . "$srcdir" || $err "mkdir: !gitclone \"$srcdir\""
+	touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
+
+	build_release
+
+	printf "\n\nDONE! Check release files under %s\n" "$vdir"
+}
+
+build_release()
+{
+	(
+	cd "$srcdir" || $err "$vdir: !cd \"$srcdir\""
+	./mk -f; x_ rm -Rf tmp; rmgit .
+	x_ mv src/docs docs
+	) || $err "can't create release files"
+
+	git log --graph --pretty=format:'%Cred%h%Creset %s %Creset' \
+	    --abbrev-commit > "$srcdir/CHANGELOG" || $err "!gitlog $srcdir"
+	rm -f "$srcdir/lock" || $err "can't remove lock file in $srcdir"
+
+	(
+	cd "${srcdir%/*}" || $err "$vdir: mktarball \"$srcdir\""
+	mktarball "${srcdir##*/}" "${srcdir##*/}.tar.xz" || $err "$vdir: mksrc"
+	) || $err "can't create src tarball"
+	[ "$mode" = "src" ] && return 0
+
+	touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
+	(
+	cd "$srcdir" || $err "$vdir: 2 !cd \"$srcdir\""
+	mk -b coreboot pico-serprog stm32-vserprog
+	x_ mv bin ../roms
+	) || $err "can't build rom images"
+
+	rm -Rf "$srcdir" || $err "!rm -Rf $srcdir"
+}
+
+fail()
+{
+	tmp_cleanup || printf "WARNING: can't rm tmpfiles: %s\n" "$TMPDIR" 1>&2
+	err_ "${1}"
+}
+
+tmp_cleanup()
+{
+	[ "$xbmk_parent" = "y" ] || return 0
+	[ "$TMPDIR" = "/tmp" ] || rm -Rf "$TMPDIR" || return 1
+	rm -f lock || return 1
+}
+
+main $@
+tmp_cleanup || err_ "can't rm TMPDIR upon non-zero exit: $TMPDIR"
@@ -0,0 +1,56 @@
+From f22f408956bf02609a96b7d72fb3321da159bfc6 Mon Sep 17 00:00:00 2001
+From: Nico Huber <nico.huber@secunet.com>
+Date: Tue, 22 Jun 2021 13:49:44 +0000
+Subject: [PATCH 1/1] cbfstool: Make use of spurious null-termination
+
+The null-termination of `filetypes` was added after the code was
+written, obviously resulting in NULL dereferences. As some more
+code has grown around the termination, it's hard to revert the
+regression, so let's update the code that still used the array
+length.
+
+This fixes commit 7f5f9331d1 (util/cbfstool: fix buffer over-read)
+which actually did fix something, but only one path while it broke
+two others. We should be careful with fixes, they can always break
+something else. Especially when a dumb tool triggered the patching
+it seems likely that fewer people looked into related code.
+
+Change-Id: If2ece1f5ad62952ed2e57769702e318ba5468f0c
+Signed-off-by: Nico Huber <nico.huber@secunet.com>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/55763
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Julius Werner <jwerner@chromium.org>
+---
+ util/cbfstool/common.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
+index e2ed38ffc4..539d0baccf 100644
+--- a/util/cbfstool/common.c
+++ b/util/cbfstool/common.c
+@@ -168,10 +168,10 @@ void print_supported_architectures(void)
+ 
+ void print_supported_filetypes(void)
+ {
+-	int i, number = ARRAY_SIZE(filetypes);
+	int i;
+ 
+-	for (i=0; i<number; i++) {
+-		printf(" %s%c", filetypes[i].name, (i==(number-1))?'\n':',');
+	for (i=0; filetypes[i].name; i++) {
+		printf(" %s%c", filetypes[i].name, filetypes[i + 1].name ? ',' : '\n');
+ 		if ((i%8) == 7)
+ 			printf("\n");
+ 	}
+@@ -180,7 +180,7 @@ void print_supported_filetypes(void)
+ uint64_t intfiletype(const char *name)
+ {
+ 	size_t i;
+-	for (i = 0; i < (sizeof(filetypes) / sizeof(struct typedesc_t)); i++)
+	for (i = 0; filetypes[i].name; i++)
+ 		if (strcmp(filetypes[i].name, name) == 0)
+ 			return filetypes[i].type;
+ 	return -1;
+-- 
+2.39.2
+
@@ -0,0 +1,2 @@
+tree="coreboot413"
+rev="5c186c6777c9438ff4681929c9c25c98dee28bef"
@@ -10,19 +10,17 @@ CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
 # CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
 CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
@@ -59,7 +57,6 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
 # CONFIG_VENDOR_BIOSTAR is not set
@@ -71,7 +68,6 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
@@ -79,19 +75,15 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_IBM is not set
 CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_INVENTEC is not set
 # CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
 # CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
 # CONFIG_VENDOR_PACKARDBELL is not set
@@ -112,9 +104,7 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
 # CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
 CONFIG_BOARD_SPECIFIC_OPTIONS=y
 CONFIG_MAINBOARD_PART_NUMBER="D510MO"
 CONFIG_MAINBOARD_VERSION="1.0"
@@ -130,26 +120,24 @@ CONFIG_MAX_CPUS=4
 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_POST_DEVICE=y
 CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_DEVICETREE="devicetree.cb"
 # CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_MAX_SOCKET=1
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=256
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_MAX_SOCKET=1
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_DCACHE_RAM_BASE=0xfefc0000
 CONFIG_DCACHE_RAM_SIZE=0x8000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -159,6 +147,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -193,7 +182,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_DQ67SW is not set
 # CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
 # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
-# CONFIG_BOARD_INTEL_FROST_CREEK is not set
 # CONFIG_BOARD_INTEL_GLKRVP is not set
 # CONFIG_BOARD_INTEL_HARCUVAR is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -209,14 +197,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
-
-#
-# Ptlrvp
-#
-# CONFIG_BOARD_INTEL_PTLRVP is not set
-# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
-# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
-# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
 # CONFIG_BOARD_INTEL_STRAGO is not set
@@ -224,6 +204,7 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
 CONFIG_PCIEXP_HOTPLUG_BUSES=32
 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
@@ -233,7 +214,10 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_HEAP_SIZE=0x100000
-# CONFIG_DRIVERS_EFI_FW_INFO is not set
+CONFIG_EC_GPE_SCI=0x50
+CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
+CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
+CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -272,9 +256,8 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_CPU_PT_ROM_MAP_GB=4
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -289,15 +272,11 @@ CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
 CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_CBFS_CACHE_ALIGN=8
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_UART_BITBANG_TX_DELAY_MS=5
+CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-# CONFIG_TOP_SWAP_REDUNDANCY is not set

 #
 # CPU
@@ -376,7 +355,6 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y
 #
 # Embedded Controllers
 #
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_ARCH_X86=y
 CONFIG_ARCH_BOOTBLOCK_X86_32=y
 CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -389,6 +367,7 @@ CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
 CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -400,9 +379,6 @@ CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
 CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
 # end of Chipset

 #
@@ -419,14 +395,12 @@ CONFIG_NO_EARLY_GFX_INIT=y
 # Display
 #
 CONFIG_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
 # end of Display

 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
 CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -445,18 +419,15 @@ CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 # CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_DRAM_SUPPORT_DDR3=y
-CONFIG_DRAM_SUPPORT_DDR2=y
+CONFIG_USE_DDR3=y
+CONFIG_USE_DDR2=y
 # end of Devices

 #
 # Generic Drivers
 #
 CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
 # CONFIG_ELOG is not set
-# CONFIG_DRIVERS_HWID_DMI is not set
-# CONFIG_DRIVERS_OPTION_CFR is not set
 # CONFIG_SMMSTORE is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -474,7 +445,6 @@ CONFIG_SPI_FLASH_ISSI=y
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -624,6 +594,7 @@ CONFIG_PAYLOAD_NONE=y
 #
 # General Debug Settings
 #
+# CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
@@ -637,17 +608,9 @@ CONFIG_HAVE_DEBUG_SMBUS=y
 # end of Debugging

 CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y
-CONFIG_GENERIC_GPIO_LIB=y
 CONFIG_HAVE_BOOTBLOCK=y
 CONFIG_HAVE_ROMSTAGE=y
 CONFIG_HAVE_RAMSTAGE=y
@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
 tree="default"
 xarch="i386-elf"
 payload_seabios="y"
@@ -10,19 +10,17 @@ CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
 # CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
 CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
@@ -59,7 +57,6 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
 # CONFIG_VENDOR_BIOSTAR is not set
@@ -71,7 +68,6 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
@@ -79,19 +75,15 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_IBM is not set
 CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_INVENTEC is not set
 # CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
 # CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
 # CONFIG_VENDOR_PACKARDBELL is not set
@@ -112,9 +104,7 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
 # CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
 CONFIG_BOARD_SPECIFIC_OPTIONS=y
 CONFIG_MAINBOARD_PART_NUMBER="D510MO"
 CONFIG_MAINBOARD_VERSION="1.0"
@@ -130,26 +120,24 @@ CONFIG_MAX_CPUS=4
 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_POST_DEVICE=y
 CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_DEVICETREE="devicetree.cb"
 # CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_MAX_SOCKET=1
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=256
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_MAX_SOCKET=1
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_DCACHE_RAM_BASE=0xfefc0000
 CONFIG_DCACHE_RAM_SIZE=0x8000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -159,6 +147,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -193,7 +182,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_DQ67SW is not set
 # CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
 # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
-# CONFIG_BOARD_INTEL_FROST_CREEK is not set
 # CONFIG_BOARD_INTEL_GLKRVP is not set
 # CONFIG_BOARD_INTEL_HARCUVAR is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -209,14 +197,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
-
-#
-# Ptlrvp
-#
-# CONFIG_BOARD_INTEL_PTLRVP is not set
-# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
-# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
-# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
 # CONFIG_BOARD_INTEL_STRAGO is not set
@@ -224,6 +204,7 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
 CONFIG_PCIEXP_HOTPLUG_BUSES=32
 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
@@ -233,7 +214,10 @@ CONFIG_D3COLD_SUPPORT=y
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_HEAP_SIZE=0x100000
-# CONFIG_DRIVERS_EFI_FW_INFO is not set
+CONFIG_EC_GPE_SCI=0x50
+CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
+CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
+CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -272,9 +256,8 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_CPU_PT_ROM_MAP_GB=4
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -289,15 +272,11 @@ CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
 CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_CBFS_CACHE_ALIGN=8
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_UART_BITBANG_TX_DELAY_MS=5
+CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-# CONFIG_TOP_SWAP_REDUNDANCY is not set

 #
 # CPU
@@ -376,7 +355,6 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y
 #
 # Embedded Controllers
 #
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_ARCH_X86=y
 CONFIG_ARCH_BOOTBLOCK_X86_32=y
 CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -389,6 +367,7 @@ CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
 CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -400,9 +379,6 @@ CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
 CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
 # end of Chipset

 #
@@ -419,14 +395,12 @@ CONFIG_NO_EARLY_GFX_INIT=y
 # Display
 #
 CONFIG_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
 # end of Display

 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
 CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x10000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -445,18 +419,15 @@ CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 # CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set
-CONFIG_DRAM_SUPPORT_DDR3=y
-CONFIG_DRAM_SUPPORT_DDR2=y
+CONFIG_USE_DDR3=y
+CONFIG_USE_DDR2=y
 # end of Devices

 #
 # Generic Drivers
 #
 CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
 # CONFIG_ELOG is not set
-# CONFIG_DRIVERS_HWID_DMI is not set
-# CONFIG_DRIVERS_OPTION_CFR is not set
 # CONFIG_SMMSTORE is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -474,7 +445,6 @@ CONFIG_SPI_FLASH_ISSI=y
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -624,6 +594,7 @@ CONFIG_PAYLOAD_NONE=y
 #
 # General Debug Settings
 #
+# CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
@@ -637,17 +608,9 @@ CONFIG_HAVE_DEBUG_SMBUS=y
 # end of Debugging

 CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y
-CONFIG_GENERIC_GPIO_LIB=y
 CONFIG_HAVE_BOOTBLOCK=y
 CONFIG_HAVE_ROMSTAGE=y
 CONFIG_HAVE_RAMSTAGE=y
@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
 tree="default"
 xarch="i386-elf"
 payload_seabios="y"
@@ -10,19 +10,17 @@ CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
 # CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
 CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
@@ -59,7 +57,6 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
 # CONFIG_VENDOR_BIOSTAR is not set
@@ -71,7 +68,6 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
@@ -79,19 +75,15 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_IBM is not set
 CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_INVENTEC is not set
 # CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
 # CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
 # CONFIG_VENDOR_PACKARDBELL is not set
@@ -112,9 +104,7 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
 # CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
 CONFIG_BOARD_SPECIFIC_OPTIONS=y
 CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
 CONFIG_MAINBOARD_VERSION="1.0"
@@ -130,27 +120,25 @@ CONFIG_MAX_CPUS=4
 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_POST_DEVICE=y
 CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_DEVICETREE="devicetree.cb"
 # CONFIG_VBOOT is not set
 CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_MAX_SOCKET=1
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_MAX_SOCKET=1
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_DCACHE_RAM_BASE=0xfefc0000
 CONFIG_DCACHE_RAM_SIZE=0x8000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -160,6 +148,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -194,7 +183,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_DQ67SW is not set
 # CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
 # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
-# CONFIG_BOARD_INTEL_FROST_CREEK is not set
 # CONFIG_BOARD_INTEL_GLKRVP is not set
 # CONFIG_BOARD_INTEL_HARCUVAR is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -210,14 +198,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
-
-#
-# Ptlrvp
-#
-# CONFIG_BOARD_INTEL_PTLRVP is not set
-# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
-# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
-# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
 # CONFIG_BOARD_INTEL_STRAGO is not set
@@ -225,6 +205,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
 CONFIG_PS2K_EISAID="PNP0303"
 CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
@@ -232,7 +213,10 @@ CONFIG_D3COLD_SUPPORT=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
 CONFIG_HEAP_SIZE=0x100000
-# CONFIG_DRIVERS_EFI_FW_INFO is not set
+CONFIG_EC_GPE_SCI=0x50
+CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
+CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
+CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_512=y
@@ -271,9 +255,8 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_CPU_PT_ROM_MAP_GB=4
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -288,15 +271,11 @@ CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
 CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_CBFS_CACHE_ALIGN=8
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_UART_BITBANG_TX_DELAY_MS=5
+CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-# CONFIG_TOP_SWAP_REDUNDANCY is not set

 #
 # CPU
@@ -375,7 +354,6 @@ CONFIG_SUPERIO_SMSC_LPC47M15X=y
 #
 # Embedded Controllers
 #
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_ARCH_X86=y
 CONFIG_ARCH_BOOTBLOCK_X86_32=y
 CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -388,6 +366,7 @@ CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
 CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -399,9 +378,6 @@ CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
 CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
 # end of Chipset

 #
@@ -418,14 +394,12 @@ CONFIG_NO_EARLY_GFX_INIT=y
 # Display
 #
 CONFIG_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
 # end of Display

 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
 CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -441,17 +415,14 @@ CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_DRAM_SUPPORT_DDR2=y
+CONFIG_USE_DDR2=y
 # end of Devices

 #
 # Generic Drivers
 #
 CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
 # CONFIG_ELOG is not set
-# CONFIG_DRIVERS_HWID_DMI is not set
-# CONFIG_DRIVERS_OPTION_CFR is not set
 # CONFIG_SMMSTORE is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -469,7 +440,6 @@ CONFIG_SPI_FLASH_ISSI=y
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -622,6 +592,7 @@ CONFIG_PAYLOAD_NONE=y
 #
 # General Debug Settings
 #
+# CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
@@ -636,17 +607,9 @@ CONFIG_HAVE_DEBUG_SMBUS=y
 # end of Debugging

 CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y
-CONFIG_GENERIC_GPIO_LIB=y
 CONFIG_HAVE_BOOTBLOCK=y
 CONFIG_HAVE_ROMSTAGE=y
 CONFIG_HAVE_RAMSTAGE=y
@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
 tree="default"
 xarch="i386-elf"
 payload_seabios="y"
@@ -10,19 +10,17 @@ CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
 # CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
 CONFIG_SEPARATE_ROMSTAGE=y
 CONFIG_INCLUDE_CONFIG_FILE=y
 CONFIG_COLLECT_TIMESTAMPS=y
@@ -59,7 +57,6 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
 # CONFIG_VENDOR_BIOSTAR is not set
@@ -71,7 +68,6 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
@@ -79,19 +75,15 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_IBM is not set
 CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_INVENTEC is not set
 # CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
 # CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
 # CONFIG_VENDOR_PACKARDBELL is not set
@@ -112,9 +104,7 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
 # CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
 CONFIG_BOARD_SPECIFIC_OPTIONS=y
 CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
 CONFIG_MAINBOARD_VERSION="1.0"
@@ -130,27 +120,25 @@ CONFIG_MAX_CPUS=4
 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_POST_DEVICE=y
 CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_DEVICETREE="devicetree.cb"
 # CONFIG_VBOOT is not set
 CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
 # CONFIG_PCIEXP_ASPM is not set
 # CONFIG_PCIEXP_L1_SUB_STATE is not set
 # CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_MAX_SOCKET=1
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_MAX_SOCKET=1
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_DCACHE_RAM_BASE=0xfefc0000
 CONFIG_DCACHE_RAM_SIZE=0x8000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -160,6 +148,7 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
+CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -194,7 +183,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_DQ67SW is not set
 # CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
 # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
-# CONFIG_BOARD_INTEL_FROST_CREEK is not set
 # CONFIG_BOARD_INTEL_GLKRVP is not set
 # CONFIG_BOARD_INTEL_HARCUVAR is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -210,14 +198,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
-
-#
-# Ptlrvp
-#
-# CONFIG_BOARD_INTEL_PTLRVP is not set
-# CONFIG_BOARD_INTEL_PTLRVP4ES is not set
-# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC is not set
-# CONFIG_BOARD_INTEL_PTLRVP_CHROMEEC4ES is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
 # CONFIG_BOARD_INTEL_STRAGO is not set
@@ -225,6 +205,7 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
 CONFIG_PS2K_EISAID="PNP0303"
 CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
@@ -232,7 +213,10 @@ CONFIG_D3COLD_SUPPORT=y
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
 CONFIG_HEAP_SIZE=0x100000
-# CONFIG_DRIVERS_EFI_FW_INFO is not set
+CONFIG_EC_GPE_SCI=0x50
+CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
+CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
+CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -271,9 +255,8 @@ CONFIG_ROMSTAGE_ADDR=0x2000000
 CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
-CONFIG_CPU_PT_ROM_MAP_GB=4
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -288,15 +271,11 @@ CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
 CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_CBFS_CACHE_ALIGN=8
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_UART_BITBANG_TX_DELAY_MS=5
+CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
 # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK is not set
 CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE=0x10000
-# CONFIG_TOP_SWAP_REDUNDANCY is not set

 #
 # CPU
@@ -375,7 +354,6 @@ CONFIG_SUPERIO_SMSC_LPC47M15X=y
 #
 # Embedded Controllers
 #
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_ARCH_X86=y
 CONFIG_ARCH_BOOTBLOCK_X86_32=y
 CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -388,6 +366,7 @@ CONFIG_AP_IN_SIPI_WAIT=y
 CONFIG_SIPI_VECTOR_IN_ROM=y
 CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
 CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
+CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
 CONFIG_PC80_SYSTEM=y
 CONFIG_HAVE_CMOS_DEFAULT=y
 CONFIG_POSTCAR_STAGE=y
@@ -399,9 +378,6 @@ CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
 CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
 # end of Chipset

 #
@@ -418,14 +394,12 @@ CONFIG_NO_EARLY_GFX_INIT=y
 # Display
 #
 CONFIG_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
 # end of Display

 CONFIG_PCI=y
 CONFIG_ECAM_MMCONF_SUPPORT=y
 CONFIG_PCIX_PLUGIN_SUPPORT=y
 CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_AZALIA_USE_LEGACY_VERB_TABLE=y
 CONFIG_PCIEXP_PLUGIN_SUPPORT=y
 CONFIG_ECAM_MMCONF_LENGTH=0x04000000
 CONFIG_PCI_ALLOW_BUS_MASTER=y
@@ -441,17 +415,14 @@ CONFIG_INTEL_GMA_ADD_VBT=y
 # CONFIG_SOFTWARE_I2C is not set
 CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
 CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_DRAM_SUPPORT_DDR2=y
+CONFIG_USE_DDR2=y
 # end of Devices

 #
 # Generic Drivers
 #
 CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
 # CONFIG_ELOG is not set
-# CONFIG_DRIVERS_HWID_DMI is not set
-# CONFIG_DRIVERS_OPTION_CFR is not set
 # CONFIG_SMMSTORE is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -469,7 +440,6 @@ CONFIG_SPI_FLASH_ISSI=y
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -622,6 +592,7 @@ CONFIG_PAYLOAD_NONE=y
 #
 # General Debug Settings
 #
+# CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
@@ -636,17 +607,9 @@ CONFIG_HAVE_DEBUG_SMBUS=y
 # end of Debugging

 CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y
-CONFIG_GENERIC_GPIO_LIB=y
 CONFIG_HAVE_BOOTBLOCK=y
 CONFIG_HAVE_ROMSTAGE=y
 CONFIG_HAVE_RAMSTAGE=y
@@ -1,5 +1,3 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
 tree="default"
 xarch="i386-elf"
 payload_seabios="y"
@@ -1,18 +0,0 @@
-3rdparty/fsp/EagleStreamFspBinPkg
-3rdparty/fsp/MeteorLakeFspBinPkg
-3rdparty/fsp/IceLakeFspBinPkg
-3rdparty/fsp/AmberLakeFspBinPkg
-3rdparty/fsp/DenvertonNSFspBinPkg
-3rdparty/fsp/TigerLakeFspBinPkg
-3rdparty/fsp/CedarIslandFspBinPkg
-3rdparty/fsp/ElkhartLakeFspBinPkg
-3rdparty/fsp/CometLakeFspBinPkg
-3rdparty/fsp/WhitleyFspBinPkg
-3rdparty/fsp/ArrowLakeFspBinPkg
-3rdparty/fsp/IdavilleFspBinPkg
-3rdparty/fsp/BraswellFspBinPkg
-3rdparty/fsp/CoffeeLakeFspBinPkg
-3rdparty/fsp/RaptorLakeFspBinPkg
-3rdparty/fsp/ApolloLakeFspBinPkg
-3rdparty/fsp/SkylakeFspBinPkg
-3rdparty/vboot/tests
@@ -0,0 +1,23 @@
+From 2d9f38a12b883e1ddcdae5de107f204e522146e2 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@retroboot.org>
+Date: Fri, 19 Mar 2021 05:54:58 +0000
+Subject: [PATCH 01/39] apple/macbook21: Set default VRAM to 64MiB instead of
+ 8MiB
+
+---
+ src/mainboard/apple/macbook21/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
+index b744b11cda..9749e26547 100644
+--- a/src/mainboard/apple/macbook21/cmos.default
+++ b/src/mainboard/apple/macbook21/cmos.default
+@@ -7,4 +7,4 @@ boot_devices=''
+ boot_default=0x40
+ cmos_defaults_loaded=Yes
+ lpt=Enable
+-gfx_uma_size=8M
+gfx_uma_size=64M
+-- 
+2.39.2
+
@@ -1,7 +1,7 @@
-From 4e350ac1b7d5f27ae0887bb016d748b0987ad14d Mon Sep 17 00:00:00 2001
+From e60ec1c7304e3f167fd2bf762f28b7eacd0b169a Mon Sep 17 00:00:00 2001
 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
 Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 01/41] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 02/39] add c3 and clockgen to apple/macbook21

 ---
 src/mainboard/apple/macbook21/Kconfig       |  1 +
@@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644
 	end
 end
 -- 
-2.47.3
+2.39.2

@@ -0,0 +1,23 @@
+From 9a0157b1459365cf52f90e66b78dd6b60a259587 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Sun, 3 Jan 2021 03:34:01 +0000
+Subject: [PATCH 03/39] lenovo/x60: 64MiB Video RAM changed to default
+ (previously it was 8MiB)
+
+---
+ src/mainboard/lenovo/x60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
+index 58825c8a36..8e0aaf427d 100644
+--- a/src/mainboard/lenovo/x60/cmos.default
+++ b/src/mainboard/lenovo/x60/cmos.default
+@@ -17,4 +17,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
+gfx_uma_size=64M
+-- 
+2.39.2
+
@@ -0,0 +1,22 @@
+From 5b2a26e72bce37f7b0a92f1ed93fd607cea8de9b Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Mon, 22 Feb 2021 22:16:59 +0000
+Subject: [PATCH 04/39] lenovo/t60: make 64MiB VRAM the default in cmos.default
+
+---
+ src/mainboard/lenovo/t60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
+index 283a5747ee..91f6c0e6e2 100644
+--- a/src/mainboard/lenovo/t60/cmos.default
+++ b/src/mainboard/lenovo/t60/cmos.default
+@@ -17,4 +17,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
+gfx_uma_size=64M
+-- 
+2.39.2
+
@@ -0,0 +1,23 @@
+From 945d84782e706e8f3effab57edca68d9463d21fc Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:10:33 +0100
+Subject: [PATCH 05/39] lenovo/t400: set VRAM to 256MiB VRAM by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/lenovo/t400/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
+index a16d386dd1..e7bb32306c 100644
+--- a/src/mainboard/lenovo/t400/cmos.default
+++ b/src/mainboard/lenovo/t400/cmos.default
+@@ -15,4 +15,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ hybrid_graphics_mode=Integrated Only
+-gfx_uma_size=32M
+gfx_uma_size=256M
+-- 
+2.39.2
+
@@ -0,0 +1,23 @@
+From 112470b4f7b046ec2656699336211ba63ff448fa Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:11:59 +0100
+Subject: [PATCH 06/39] lenovo/x200: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/lenovo/x200/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
+index 434af5d227..443ef54e41 100644
+--- a/src/mainboard/lenovo/x200/cmos.default
+++ b/src/mainboard/lenovo/x200/cmos.default
+@@ -14,4 +14,4 @@ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
+gfx_uma_size=256M
+-- 
+2.39.2
+
@@ -0,0 +1,23 @@
+From 37418629a56cb740cae2870317458ea52daad8c9 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:18:26 +0100
+Subject: [PATCH 07/39] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+index fe79c83570..4a1f97a9d8 100644
+--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+@@ -4,4 +4,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+-gfx_uma_size=64M
+gfx_uma_size=256M
+-- 
+2.39.2
+
@@ -0,0 +1,23 @@
+From e785387dffe382a02d4c0cb006cced48c235484c Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:21:39 +0100
+Subject: [PATCH 08/39] acer/g43t-am3: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/acer/g43t-am3/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
+index 23f0e55f3e..8d6c4db1ce 100644
+--- a/src/mainboard/acer/g43t-am3/cmos.default
+++ b/src/mainboard/acer/g43t-am3/cmos.default
+@@ -5,4 +5,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=64M
+gfx_uma_size=256M
+-- 
+2.39.2
+
@@ -1,7 +1,7 @@
-From 0322228c25be7d95e7dbcc905dec81960905152b Mon Sep 17 00:00:00 2001
+From 3659aec797baa40e4336e88361a705295fb72b0f Mon Sep 17 00:00:00 2001
 From: persmule <persmule@gmail.com>
 Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 02/41] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 09/39] lenovo/t400: Enable all SATA ports

 There are 2 SATA ports on the chassis of t400(s), but at least one dock for
 t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -15,7 +15,7 @@ This patch unmasked all SATA ports found within t400s with factory firmware.
 1 file changed, 2 insertions(+), 2 deletions(-)

 diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb
-index 9e056772e9..9361f330d2 100644
+index 259c3e1b21..3d007533a4 100644
 --- a/src/mainboard/lenovo/t400/devicetree.cb
 +++ b/src/mainboard/lenovo/t400/devicetree.cb
@@ -46,8 +46,8 @@ chip northbridge/intel/gm45
@@ -30,5 +30,5 @@ index 9e056772e9..9361f330d2 100644
 			register "sata_traffic_monitor"		= "0"
 
 -- 
-2.47.3
+2.39.2

@@ -0,0 +1,22 @@
+From 820c2d64a7415f7159fd7cdac4746049c91f89a2 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 20 Dec 2021 01:29:31 +0000
+Subject: [PATCH 10/39] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
+ default
+
+---
+ src/mainboard/lenovo/x230/cmos.default | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
+index 732e214b32..3bb78960b9 100644
+--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
+@@ -18,3 +18,4 @@ backlight=Both
+ usb_always_on=Disable
+ f1_to_f12_as_primary=Enable
+ me_state=Normal
+gfx_uma_size=224M
+-- 
+2.39.2
+
@@ -1,7 +1,7 @@
-From 4714f4388bf90fc7ff3d25dd62feec07de5f4c7e Mon Sep 17 00:00:00 2001
+From 6bc13399517009917538cd4ddb426c4b1550bfad Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 03/41] lenovo/x230: set me_state=Disabled in cmos.default
+Subject: [PATCH 11/39] lenovo/x230: set me_state=Disabled in cmos.default

 I only recently found out about this. It's possible to use me_cleaner to
 do the same thing, but some people might just flash coreboot and not do
@@ -23,15 +23,16 @@ Date:   Thu Nov 21 21:47:31 2019 +0300
 1 file changed, 1 insertion(+), 1 deletion(-)

 diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
-index 732e214b32..8454f0eac0 100644
+index 3bb78960b9..ae47202aac 100644
 --- a/src/mainboard/lenovo/x230/cmos.default
 +++ b/src/mainboard/lenovo/x230/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -17,5 +17,5 @@ trackpoint=Enable
 backlight=Both
 usb_always_on=Disable
 f1_to_f12_as_primary=Enable
 -me_state=Normal
 +me_state=Disabled
+ gfx_uma_size=224M
 -- 
-2.47.3
+2.39.2

@@ -1,7 +1,7 @@
-From 0d8c12b68060ebfe4df4cf0d7cb1abd4c2b2243b Mon Sep 17 00:00:00 2001
+From 72c9e1403fb93c025be75536f5520e2ef9d4da9e Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 04/41] set me_state=Disabled on all cmos.default files!
+Subject: [PATCH 12/39] set me_state=Disabled on all cmos.default files!

 yeah. why the hell isn't this the default

@@ -120,5 +120,5 @@ index d61046df6b..8c793fd1c3 100644
 -me_state=Enable
 +me_state=Disabled
 -- 
-2.47.3
+2.39.2

@@ -1,7 +1,7 @@
-From a3bc9753261ebd534df6c6752169b3edbb588a97 Mon Sep 17 00:00:00 2001
+From 70cf6905b54d39285025373dae1c897c9c727f83 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 05/41] util/ifdtool: add --nuke flag (all 0xFF on region)
+Subject: [PATCH 13/39] util/ifdtool: add --nuke flag (all 0xFF on region)

 When this option is used, the region's contents are overwritten
 with all ones (0xFF).
@@ -16,22 +16,22 @@ Rebased since the last revision update in lbmk.

 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
- util/ifdtool/ifdtool.c | 116 +++++++++++++++++++++++++++++------------
- 1 file changed, 84 insertions(+), 32 deletions(-)
+ util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
+ 1 file changed, 83 insertions(+), 31 deletions(-)

 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index 75238c73b2..ea8dfc788d 100644
+index 32b2081d93..1473cf058b 100644
 --- a/util/ifdtool/ifdtool.c
 +++ b/util/ifdtool/ifdtool.c
-@@ -2240,6 +2240,7 @@ static void print_usage(const char *name)
+@@ -2204,6 +2204,7 @@ static void print_usage(const char *name)
 	       "                                         tgl    - Tiger Lake\n"
 	       "                                         wbg    - Wellsburg\n"
 	       "   -S | --setpchstrap                    Write a PCH strap\n"
 +	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
- 	       "   -T | --topswapsize                    Set the Top Swap Block Size PCH strap value\n"
- 	       "                                         Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n"
-@@ -2251,6 +2252,60 @@ static void print_usage(const char *name)
+ 	       "   -v | --version:                       print the version\n"
+ 	       "   -h | --help:                          print this help\n\n"
+@@ -2212,6 +2213,60 @@ static void print_usage(const char *name)
 	       "\n");
 }
 
@@ -92,23 +92,23 @@ index 75238c73b2..ea8dfc788d 100644
 int main(int argc, char *argv[])
 {
 	int opt, option_index = 0;
-@@ -2258,6 +2313,7 @@ int main(int argc, char *argv[])
+@@ -2219,6 +2274,7 @@ int main(int argc, char *argv[])
 	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
 	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
 +	int mode_nuke = 0;
 	int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
- 	int mode_settopswapsize = 0;
- 	char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL;
-@@ -2294,6 +2350,7 @@ int main(int argc, char *argv[])
+ 	char *region_type_string = NULL, *region_fname = NULL;
+ 	const char *layout_fname = NULL;
+@@ -2254,6 +2310,7 @@ int main(int argc, char *argv[])
+ 		{"validate", 0, NULL, 't'},
 		{"setpchstrap", 1, NULL, 'S'},
 		{"newvalue", 1, NULL, 'V'},
- 		{"topswapsize", 1, NULL, 'T'},
 +		{"nuke", 1, NULL, 'N'},
 		{0, 0, 0, 0}
 	};
 
-@@ -2343,35 +2400,8 @@ int main(int argc, char *argv[])
+@@ -2303,35 +2360,8 @@ int main(int argc, char *argv[])
 			region_fname++;
 			// Descriptor, BIOS, ME, GbE, Platform
 			// valid type?
@@ -146,11 +146,10 @@ index 75238c73b2..ea8dfc788d 100644
 				fprintf(stderr, "No such region type: '%s'\n\n",
 					region_type_string);
 				fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
-@@ -2552,7 +2582,23 @@ int main(int argc, char *argv[])
- 			mode_settopswapsize = 1;
- 			top_swap_size_arg = optarg;
+@@ -2508,6 +2538,22 @@ int main(int argc, char *argv[])
+ 		case 't':
+ 			mode_validate = 1;
 			break;
-		case 'v':
 +               case 'N':
 +                       region_type_string = strdup(optarg);
 +                       if (!region_type_string) {
@@ -167,13 +166,12 @@ index 75238c73b2..ea8dfc788d 100644
 +                       }
 +                       mode_nuke = 1;
 +                       break;
-+		Case 'v':
+ 		case 'v':
 			print_version();
 			exit(EXIT_SUCCESS);
- 			break;
-@@ -2571,7 +2617,8 @@ int main(int argc, char *argv[])
+@@ -2524,7 +2570,8 @@ int main(int argc, char *argv[])
 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
- 			mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 |
+ 			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
 			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
 -			(mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
 +			(mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
@@ -181,9 +179,9 @@ index 75238c73b2..ea8dfc788d 100644
 		fprintf(stderr, "You may not specify more than one mode.\n\n");
 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
 		exit(EXIT_FAILURE);
-@@ -2580,7 +2627,8 @@ int main(int argc, char *argv[])
+@@ -2533,7 +2580,8 @@ int main(int argc, char *argv[])
 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
- 			mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 +
+ 			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
 			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
 -			mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
 +			mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
@@ -191,7 +189,7 @@ index 75238c73b2..ea8dfc788d 100644
 		fprintf(stderr, "You need to specify a mode.\n\n");
 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
 		exit(EXIT_FAILURE);
-@@ -2746,6 +2794,10 @@ int main(int argc, char *argv[])
+@@ -2646,6 +2694,10 @@ int main(int argc, char *argv[])
 		write_image(new_filename, image, size);
 	}
 
@@ -203,5 +201,5 @@ index 75238c73b2..ea8dfc788d 100644
 		struct fpsba *fpsba = find_fpsba(image, size);
 		struct fmsba *fmsba = find_fmsba(image, size);
 -- 
-2.47.3
+2.39.2

@@ -0,0 +1,47 @@
+From c53e5035b612710595abc93f0b4c3c65ca61ebad Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Wed, 1 Dec 2021 02:53:00 +0000
+Subject: [PATCH 14/39] fix speedstep on x200/t400: Revert
+ "cpu/intel/model_1067x: enable PECI"
+
+This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
+
+Enabling PECI without microcode updates loaded causes the CPUID feature set
+to become corrupted. And one consequence is broken SpeedStep. At least, that's
+my understanding looking at Intel Errata. This revert is not a fix, because
+upstream is correct (upstream assumes microcode updates). We will simply
+maintain this revert patch in Libreboot, from now on.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index d051e8915b..30ba2bf0c6 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
+ 	wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
+ }
+ 
+-#define IA32_PECI_CTL		0x5a0
+-
+ static void configure_misc(const int eist, const int tm2, const int emttm)
+ {
+ 	msr_t msr;
+@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
+ 		msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
+ 		wrmsr(IA32_MISC_ENABLE, msr);
+ 	}
+-
+-	/* Enable PECI
+-	   WARNING: due to Erratum AW67 described in Intel document #318733
+-	   the microcode must be updated before this MSR is written to. */
+-	msr = rdmsr(IA32_PECI_CTL);
+-	msr.lo |= 1;
+-	wrmsr(IA32_PECI_CTL, msr);
+ }
+ 
+ #define PIC_SENS_CFG	0x1aa
+-- 
+2.39.2
+
@@ -0,0 +1,173 @@
+From dabe942b006082f6e592a26f1d0f13a2586b53d6 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 17 Apr 2023 15:49:57 +0100
+Subject: [PATCH 15/39] GM45-type CPUs: don't enable alternative SMRR
+
+This reverts the changes in coreboot revision:
+df7aecd92643d207feaf7fd840f8835097346644
+
+While this fix is *technically correct*, the one in
+coreboot, it breaks rebooting as tested on several
+GM45 ThinkPads e.g. X200, T400, when microcode
+updates are not applied.
+
+Since November 2022, Libreboot includes microcode
+updates by default, but it tells users how to remove
+it from the ROM (with cbfstool) if they wish.
+
+Well, with Libreboot 20221214, 20230319 and 20230413,
+mitigations present in Libreboot 20220710 (which did
+not have microcode updates) do not exist.
+
+This patch, along with the other patch to remove PECI
+support (which breaks speedstep when microcode updates
+are not applied) have now been re-added to Libreboot.
+
+It is still best to use microcode updates by default.
+These patches in coreboot are not critically urgent,
+and you can use the machines with or without them,
+regardless of ucode.
+
+I'll probably re-write this and the other patch at
+some point, applying the change conditionally upon
+whether or not microcode is applied.
+
+Pragmatism is a good thing. I recommend it.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c |  4 +++
+ src/cpu/intel/model_1067x/mp_init.c          | 26 --------------------
+ src/cpu/intel/model_106cx/model_106cx_init.c |  4 +++
+ src/cpu/intel/model_6ex/model_6ex_init.c     |  4 +++
+ src/cpu/intel/model_6fx/model_6fx_init.c     |  4 +++
+ 5 files changed, 16 insertions(+), 26 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 30ba2bf0c6..312046901a 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -8,6 +8,7 @@
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
+ #include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
+ 
+ #define MSR_BBL_CR_CTL3		0x11e
+ 
+@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
+	/* Set virtualization based on Kconfig option */
+	set_vmx_and_lock();
+
+ 	/* Configure C States */
+ 	configure_c_states(quad);
+ 
+diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
+index bc53214310..72f40f6762 100644
+--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
+@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
+ 	smm_initialize();
+ }
+ 
+-#define SMRR_SUPPORTED (1 << 11)
+-
+ static void per_cpu_smm_trigger(void)
+ {
+-	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+-	if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
+-		set_feature_ctrl_vmx();
+-		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
+-		/* We don't care if the lock is already setting
+-		   as our smm relocation handler is able to handle
+-		   setups where SMRR is not enabled here. */
+-		if (ia32_ft_ctrl.lo & (1 << 0)) {
+-			/* IA32_FEATURE_CONTROL locked. If we set it again we
+-			   get an illegal instruction. */
+-			printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
+-			printk(BIOS_DEBUG, "SMRR status: %senabled\n",
+-			       ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
+-		} else {
+-			if (!CONFIG(SET_IA32_FC_LOCK_BIT))
+-				printk(BIOS_INFO,
+-				       "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
+-			ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
+-			wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
+-		}
+-	} else {
+-		set_vmx_and_lock();
+-	}
+-
+ 	/* Relocate the SMM handler. */
+ 	smm_relocate();
+ }
+diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
+index 05f5f327cc..0450c2ad83 100644
+--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
+	/* Set virtualization based on Kconfig option */
+	set_vmx_and_lock();
+
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
+index 5bd1c32815..f3bb08cde3 100644
+--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
+	/* Set virtualization based on Kconfig option */
+	set_vmx_and_lock();
+
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
+index 535fb8fae7..f7b05facd2 100644
+--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
+	/* Set virtualization based on Kconfig option */
+	set_vmx_and_lock();
+
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+-- 
+2.39.2
+
@@ -1,20 +1,20 @@
-From c3f93c58ddeb1e44daf76db9d67e33bcd2c54a62 Mon Sep 17 00:00:00 2001
+From 6426e07c7da50d588ee1ca30e0911040d89e4c96 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 06/41] mb/dell/e6400: Enable 01.0 device in devicetree for
+Subject: [PATCH 16/39] mb/dell/e6400: Enable 01.0 device in devicetree for
 dGPU models

 Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
 ---
- src/mainboard/dell/gm45_latitude/devicetree.cb | 2 +-
+ src/mainboard/dell/e6400/devicetree.cb | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

-diff --git a/src/mainboard/dell/gm45_latitude/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
-index 5919803be2..76dae87153 100644
--- a/src/mainboard/dell/gm45_latitude/devicetree.cb
-+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
-@@ -18,7 +18,7 @@ chip northbridge/intel/gm45
+diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
+index bb954cbd7b..e9f3915d17 100644
+--- a/src/mainboard/dell/e6400/devicetree.cb
+++ b/src/mainboard/dell/e6400/devicetree.cb
+@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
 		ops gm45_pci_domain_ops
 
 		device pci 00.0 on end # host bridge
@@ -24,5 +24,5 @@ index 5919803be2..76dae87153 100644
 		device pci 02.1 on end # Display
 		device pci 03.0 on end # ME
 -- 
-2.47.3
+2.39.2

@@ -1,7 +1,7 @@
-From 9c0234bac4d37670da6831e3ff9545a0c6119237 Mon Sep 17 00:00:00 2001
+From 29a654eaaa7bf924f9681a2520dbabfe12619269 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 07/41] Remove warning for coreboot images built without a
+Subject: [PATCH 17/39] Remove warning for coreboot images built without a
 payload

 I added this in upstream to prevent people from accidentally flashing
@@ -35,5 +35,5 @@ index 5f988dac1b..516133880f 100644
 -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
 +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
 -- 
-2.47.3
+2.39.2

@@ -0,0 +1,430 @@
+From 892b6244c27590cbf1d82125340c57273e42b911 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sat, 19 Aug 2023 16:19:10 -0600
+Subject: [PATCH 18/39] mb/dell: Add Latitude E6530 (Ivy Bridge)
+
+Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was
+not tested. I do not physically have this system; someone with physical
+access to one sent me the output of autoport which I then modified to
+produce this port.
+
+I was also sent the vbios obtained using intel_bios_dumper while running
+version A22 of the vendor firmware, which I then processed using
+`intelvbttool --inoprom vbios.bin --outvbt data.vbt` to obtain data.vbt.
+
+This was originally tested and found to be working as a standalone board
+port in Libreboot, though this variant based port in upstream coreboot
+has not been tested.
+
+This can be internally flashed by sending a command to the EC, which
+causes the EC to pull the FDO pin low and the firmware to skip setting
+up any chipset based write protections [1]. The EC is the SMSC MEC5055,
+which seems to be compatible with the existing MEC5035 code.
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |   8 +
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e6530/data.vbt  | Bin 0 -> 4280 bytes
+ .../variants/e6530/early_init.c               |  14 ++
+ .../snb_ivb_latitude/variants/e6530/gpio.c    | 192 ++++++++++++++++++
+ .../variants/e6530/hda_verb.c                 |  32 +++
+ .../variants/e6530/overridetree.cb            |  37 ++++
+ 7 files changed, 286 insertions(+)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index be9ac37845..03377275f0 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -23,6 +23,12 @@ config BOARD_DELL_LATITUDE_E6430
+ 	select MAINBOARD_USES_IFD_GBE_REGION
+ 	select SOUTHBRIDGE_INTEL_C216
+ 
+config BOARD_DELL_LATITUDE_E6530
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_12288
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOUTHBRIDGE_INTEL_C216
+
+ if BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 
+ config DRAM_RESET_GATE_GPIO
+@@ -33,6 +39,7 @@ config MAINBOARD_DIR
+ 
+ config MAINBOARD_PART_NUMBER
+ 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
+	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
+ 
+ config OVERRIDE_DEVICETREE
+ 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+@@ -42,6 +49,7 @@ config USBDEBUG_HCD_INDEX
+ 
+ config VARIANT_DIR
+ 	default "e6430" if BOARD_DELL_LATITUDE_E6430
+	default "e6530" if BOARD_DELL_LATITUDE_E6530
+ 
+ config VGA_BIOS_ID
+ 	default "8086,0166"
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index 183252630a..d89185d670 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -2,3 +2,6 @@
+ 
+ config BOARD_DELL_LATITUDE_E6430
+ 	bool "Latitude E6430"
+
+config BOARD_DELL_LATITUDE_E6530
+	bool "Latitude E6530"
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
+GIT binary patch
+literal 4280
+zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV
+zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU
+zIJ+cPr4+cc-@WIad+wQY&YW{+c1J!nPPgn&^^N3Hy*D37jg0=7CSl@*=mXr>x75gi
+zTMlK0$A=H4Mh~QKqCa92jz_;d3rtFqp(o-4gCnzxrJ2}Rw@^!haWp<ahv&+aDb5_3
+zE0-vq=pkms7Ves!pD#^PA#PF^_wjBTO=oC(ayR{asyKURiBdh3?x76Ll#Z5WXklvl
+z@M5XFK#OxUXqrdzedca+l4WK~_tG8Hv&HgsX`$Za3pnYy`CpW$@0?nsSh|}MrfK#j
+z%y^t^lPNt{p5INwGcz<MWEN<wv`{J^Eluv$Rb2&6%ZgV5Bp(6~Lz2Eoz~@C!!B)bs
+z1x-OrK~}*8L07Po(5+xZL6I<}phTEf5QRsVJYHa{f^AXPFaoSsnJ0feXUdB=CJ>Fv
+zr&_=Q6YubieL}zoiJ0a+c+(bGwFN5g1pz;^rGP1sM+lHB@UAPM2&F=RB&yv@$caXF
+ze~Io&3CQe=cMHr!e{yiokd?~p&F&k`jg99Ex7}WO=$8*Kx8wXv4eSa_CJqKVkyRr&
+zCdcqs*@M5!gD84e@fW{|5B#mDGTH;JFw`h^stQcTjf@V3pNe8&f$=NG?-+klRGea*
+zX1vOHi}4@EM~qJyfuM>e#%9J&Mjzt`j5OnB#;uGZ<1WTMj3vgSj3*esXZY{I`KqUa
+zfbB~~a>piTMAVDNyHR<{<v-=}gXhE(15|emxueb8Kv%5>0{F7}8pool{7_h6u?7yg
+zlyNm>-Eq_&WjW{0$9ZHq6x?~W8l2#1g0CyrtN#R-nbWG(?>iNG1zRiZgj;Lm_%rVe
+zwZ6i{g#sR5xudpbj~5H9TNIQ3gMikIG@l(Z4IR@^2|Vu|LZteLF5@$KH5`Pr&3_vn
+z^!Fn27&z6hSPR+*;D*&lm-)OE=ZgjK*(X&XdBq7RDUd7>|Lou?UMNg6lVCB;TPz{Z
+zN4-~p*Rr=uq8OYdlAy38{}dt5%2}aUax{}zWzDRgmsn2|!)=Bp)U35;Ld3H+Ye=*_
+z4S&0{5*TVI!OU-SWz$XUwrrnb%9?NHau^uhn>&;%&X#8O7mt)SIJr8D$u?NS=rUW6
+zCmnxV&FgUDAWX}gZ+1AH&-C4Q=3sl5RX9=OWPfCtcRZi4tkX44YYfRH*@?H7T=Kz=
+zG*i-wU2jbJMK%ChTMTXZFJEm~k;KCj*D60g=j!2ns8Q`g%jSRK^?=IwL^|I5-K2zH
+z8*A0-mL%Q`R#xatM^u^E=IrX+2&bc;3rv!NipS^G*6zlIRAV(JJDU($OBHuptd&1(
+zoNu>t*Q}|siS8#MYavR6j7&(~AEL#OaV(^+gy>YrSPiLfgy{2-p=xT2Mtd}4R8#XB
+z-LDysYw8J&{-GJKYwEiif07x7u5QsOr5oeA`ZJxDb>p|XdQzvCb>nSaeP1UfY_x~f
+z9bwuRHf|5Ahr{&iu<>+QeI`t=g^e>|^=z1;5o23K?TP5uo%2>aXQWCKr#dH;Qr0*j
+z3LecKKarw5`Xblzd$&H4oP%y&l3egyUc<=<Azs)*u}X^*n$F~s2O<-paSF?q*HB+n
+zqBfj5;J|x@hM`M(QD20jrkwi8`y3l;8qO;#l8A#CMI8Kg9E{ERsT>TGXaGC^5Cz)J
+z4?eb?Kub*nWYdmhV-4?j<o}k#pt-{wK;b3U(B^+`s7-`HYOZOxv<+RG^LulAxKL|9
+z3NH#9{Lg*7U1&gy<zHSG$;LMHby+V=ENlGFVLKjt%kkph7kP1M8|vebT=K5)*E>JW
+zjd{Tu*o*CE*QO)}{_J>haU5zn+1QJ^eBg|d5n5-%|DwS@1+<Mtvat=iZ3BF??pZXh
+zth4PnnWL*s%}k43fbe34>yaZ_2@Kj<UGt)`2G5>K>)nIBR-xB@+1PQ2*c$lV?Z13o
+zbX%CHpm`!1Z4$d28~9k{rfu-0w@xg6{q!u2{)Dm_))4RK$?#7P*t7V+g_9d<V!MD`
+zaj`t-?uy6zsjzp<-IdM6g(XhQX2iF<+p?Kmw6?a+f^VMex*PuetNfqf+4_FpD%8TW
+eZvUbDHC^NLu5~gtzg|!EqSkX2ep9pg!tpEeo1jDh
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c
+new file mode 100644
+index 0000000000..ff83db095b
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMB_LPC_EN | COMA_LPC_EN);
+	mec5035_early_init();
+}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c
+new file mode 100644
+index 0000000000..777570765a
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c
+@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c
+new file mode 100644
+index 0000000000..3ebccff81d
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76df,	/* Codec Vendor / Device ID: IDT */
+	0x10280535,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x10280535),
+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+	0x80862806,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb
+new file mode 100644
+index 0000000000..8b9c82fba4
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb
+@@ -0,0 +1,37 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x0535 inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x00000251"
+			register "gpu_pch_backlight" = "0x13121312"
+		end
+
+		chip southbridge/intel/bd82x6x
+			register "usb_port_config" = "{
+				{ 1, 1, 0 },
+				{ 1, 1, 0 },
+				{ 1, 1, 1 },
+				{ 1, 1, 1 },
+				{ 1, 1, 2 },
+				{ 1, 1, 2 },
+				{ 1, 0, 3 },
+				{ 1, 1, 3 },
+				{ 1, 1, 4 },
+				{ 1, 1, 4 },
+				{ 1, 1, 5 },
+				{ 1, 1, 5 },
+				{ 1, 2, 6 },
+				{ 1, 2, 6 },
+			}"
+
+			device ref xhci on
+				register "superspeed_capable_ports" = "0x0000000f"
+				register "xhci_overcurrent_mapping" = "0x00000c03"
+				register "xhci_switchable_ports" = "0x0000000f"
+			end
+		end
+	end
+end
+-- 
+2.39.2
+
@@ -0,0 +1,430 @@
+From 9b0766b86ac010b7edfe27d1f7edbb3f27dc742e Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Wed, 31 Jan 2024 22:57:07 -0700
+Subject: [PATCH 19/39] mb/dell: Add Latitude E5530 (Ivy Bridge)
+
+Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board;
+someone with physical access to one sent me the output of autoport which
+I then modified to produce this port. I was also sent the VBT binary,
+which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
+version A21 of the vendor firmware.
+
+This was originally tested and found to be working as a standalone board
+port in Libreboot, but this variant based port in upstream coreboot has
+not been tested.
+
+This can be internally flashed by sending a command to the EC, which
+causes the EC to pull the FDO pin low and the firmware to skip setting
+up any chipset based write protections [1]. The EC is the SMSC MEC5055,
+which seems to be compatible with the existing MEC5035 code.
+
+Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |   7 +
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e5530/data.vbt  | Bin 0 -> 6144 bytes
+ .../variants/e5530/early_init.c               |  14 ++
+ .../snb_ivb_latitude/variants/e5530/gpio.c    | 194 ++++++++++++++++++
+ .../variants/e5530/hda_verb.c                 |  32 +++
+ .../variants/e5530/overridetree.cb            |  39 ++++
+ 7 files changed, 289 insertions(+)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index 03377275f0..183a67bec3 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select SYSTEM_TYPE_LAPTOP
+ 	select USE_NATIVE_RAMINIT
+ 
+config BOARD_DELL_LATITUDE_E5530
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_12288
+	select SOUTHBRIDGE_INTEL_C216
+
+ config BOARD_DELL_LATITUDE_E6430
+ 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select BOARD_ROMSIZE_KB_12288
+@@ -38,6 +43,7 @@ config MAINBOARD_DIR
+ 	default "dell/snb_ivb_latitude"
+ 
+ config MAINBOARD_PART_NUMBER
+	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
+ 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
+ 
+@@ -48,6 +54,7 @@ config USBDEBUG_HCD_INDEX
+ 	default 2
+ 
+ config VARIANT_DIR
+	default "e5530" if BOARD_DELL_LATITUDE_E5530
+ 	default "e6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "e6530" if BOARD_DELL_LATITUDE_E6530
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index d89185d670..c15ef4028f 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -1,5 +1,8 @@
+ ## SPDX-License-Identifier: GPL-2.0-only
+ 
+config BOARD_DELL_LATITUDE_E5530
+	bool "Latitude E5530"
+
+ config BOARD_DELL_LATITUDE_E6430
+ 	bool "Latitude E6430"
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3
+GIT binary patch
+literal 6144
+zcmeHKU2Gdg5dO}0w$JA~+qs02q)iz56C9e5vuQ#oL0l3O+%|395Q2peO{y4(2uX0t
+zuMja1N)bPb1cE+5)fYsCK!89MFQAGChyWpk5PuR<K|G+sLmxmOR4}u5=Rg`mj70g7
+zvgdDic6N4dW^QKhynd)>kS^cR)3#-(r*-?zo-O^C(kLvv8XM<+Y3tdt^YY!P?!oTe
+zJ^ed-x6w0Lh5fN#jsv5TWE#mtd*_yky}9xDK(kOwLt+C7_AQAd#iwr=o0`gvQZ`{x
+z6ZeT`x^^;8+a~jSa^o~PF@8J6N5;o#dhCwebaM;!_oisw1#O9K={qQM<@Oeu$lXeN
+z#wJGcW4Y<2)-A{Bot(NoKX%>qdnw-AOi9bKT9Z~HL5|7PJDHz4kGlEx143q+26EH6
+z{4KfB^9;?<fTOaiNPy%=@LovL&q<^d1Qdi+Xex9SvIM^ZLq%9cP{A1rE>#dw(WfA;
+zBCR3@pCS1a;A|CZW1h7H*l#mW{%y{bf)9ofiz!EHzyiac@{RpMzz>O-<~{hx5tw%b
+z3ZJWD4_g-`iF`tUJb}+Vfe;XI1T2Y4_Y!iVk<<T4ce(^PWKh<?N^a`t+}vgNr25iZ
+z`!fTBL)ojYF5G?3y|eW=`9>MLB9et&!A7LDDE7&5ye#|hn%s#IWgagDEPNHHMUhb-
+ztc9t?uz{bD#kh#kpsE;AO-wWHV?4olPStRPag^~k<737bjBgm<GlC%vRgBe)4U9I%
+zg^XUtcE**A5ylOSn;A2V2N;hso?--U#>t|ufS}_`LGs2bcSKCVBh4s0>G7ZR_@NWx
+zkph}GhP}~YR?roT!61GqzQ?gBsuv3jY}UXbmr|alv^VxUqbz5<`5=!hhpaa*7DK~4
+zP4ad6dhH!>nYpc4{J&G-w{UiWo$zXnTz{tAq0|?c_`QJ7pKmCwIpe7Uix$P?9}v*1
+z(aVR6OkMkQ6oM}*UC@j78!~>7=OZCVYXeu|u0SiI4}w$uw6&0P09LF%Hp}O&IA3gl
+z4@ap0NfAe+q(ZVm{Bwe*Do~kbCc$Q!x7b3Sk9tLgVmsR<Q4H=9Nl;mmf2xpY<*d*-
+z`yI_BR#`La=Oxxt#qgS`3pER^nh^CZ%*qlq2N9@uSAtz-C7AhduB_U|{>#oOrY`tq
+z%|?L!zRd2-$V6^@$H<Mj3MXf#F<J+^8%<X2{tnmQTI*aK*ageBrm9^|<Ked3j_s;%
+zva<(Dob)BOwdcj8Z67UhYUAjbk==Of9W#D7k!DJobLx$$fXD_wuZyD&Kk-$EIY~S`
+zan1ANbFUW8hZ0pUw5)y??*}!;chdgq|0X5;s;m`@YdY{zs4z#z8e;13T6b4tC7gy$
+zTwszEQhk0!U$`3=Qi)ZbY^*|bAyvF>@ml^iaX;uzoVB3JA(|h9tcNKXHdA43N0|18
+z&3$2QE=)(l=6qQDAWT1oO-<KoblR+&{kk@!)1A8ch^`&b>2=+FU)Mg<35IDJ+8Tp;
+z40F)Xt}$rVFdsLxLk7KRn4cKhmj<a3vp%A&kI>eLd38j)HbM_Y%!3i_aD?8An8za8
+z@d(AD=Gv&%5;e{}p%i?_q(T*^IwzEx*Eu1wKHV9=lVUvjqv!B@cWER!2fe%`IqO?q
+z!=Wf4kzGUaLX8`m#*P^uL?%M#6qc9Qu(YT|ZMb#7UzCc_(DkQYEG<G&Q*QkX`CS`I
+z8cwQnl8A#CMH~W79L&{2*Jof_MD5t{bPTAszWUa20yPzD=*wW8)wHSu?avDhffu^!
+zL>Q#%k_O0@^DN5S@MXi$D;acJ>#cTV-(U@Offv4ACp4hO4$Ll!WO)s3P4=t9vpWBC
+zSckhlcD?xUuX=Gx96Dx{IsQ23r&;o1*+^Cp2RA3nd$A-RIHP2Q7uitC>c67FIR*5}
+zB3a%B!?6K=TJ$W+SJv@*9Lms{mTvWmU4Zanj_Z*lSqOGISzYp?yawOqLhVhRt#-E6
+zd)YW~h&meh-5prIE}Cr&7f?MMi&cqTt_^%Fa?>k(=`9jVoIf@}{g+WX#TpWuc+!2v
+zPG^>A|NZ2GlGsKdGqN{7>Fr7+Hc_^3z}uBhC4?nzOQ*!QyVugGjkK_~$bvtfY`h79
+z9rOI3;Mt}9)_G{zXTAPw`8T@6=Ut0r9R5;0#Zy|#8F;v4^UAmqft3iXL|`QXD-l?U
+Jz~2*rUjdP?m;3+#
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c
+new file mode 100644
+index 0000000000..ff83db095b
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMB_LPC_EN | COMA_LPC_EN);
+	mec5035_early_init();
+}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c
+new file mode 100644
+index 0000000000..0599f13921
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c
+@@ -0,0 +1,194 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_INPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+	.gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c
+new file mode 100644
+index 0000000000..3e89a6d75f
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76df,	/* Codec Vendor / Device ID: IDT */
+	0x1028053d,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x1028053d),
+	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0),
+
+	0x80862806,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb
+new file mode 100644
+index 0000000000..85c448d010
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb
+@@ -0,0 +1,39 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x053d inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x00000000"
+			register "gpu_pch_backlight" = "0x03d003d0"
+		end
+
+		chip southbridge/intel/bd82x6x
+			register "usb_port_config" = "{
+				{ 1, 1, 0 },
+				{ 1, 1, 0 },
+				{ 1, 1, 1 },
+				{ 1, 1, 1 },
+				{ 1, 1, 2 },
+				{ 1, 1, 2 },
+				{ 1, 1, 3 },
+				{ 1, 0, 3 },
+				{ 1, 2, 4 },
+				{ 1, 1, 4 },
+				{ 1, 1, 5 },
+				{ 1, 1, 5 },
+				{ 1, 0, 6 },
+				{ 1, 1, 6 },
+			}"
+
+			device ref xhci on
+				register "superspeed_capable_ports" = "0x0000000f"
+				register "xhci_overcurrent_mapping" = "0x00000c03"
+				register "xhci_switchable_ports" = "0x0000000f"
+			end
+			device ref gbe off end
+			device ref pcie_rp7 on end # BCM5761 Ethernet
+		end
+	end
+end
+-- 
+2.39.2
+
@@ -0,0 +1,435 @@
+From 5d8a651a71d19918130f58c637700539dd320789 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sun, 26 Nov 2023 17:08:52 -0700
+Subject: [PATCH 20/39] mb/dell: Add Latitude E6420 (Sandy Bridge)
+
+Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was
+not tested. I do not physically have this system; someone with physical
+access to one sent me the output of autoport which I then modified to
+produce this port. I was also sent the VBT binary, which was obtained
+from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the
+vendor firmware.
+
+This was originally tested and found to be working as a standalone board
+port in Libreboot, but this variant based port in upstream coreboot has
+not been tested.
+
+This can be internally flashed by sending a command to the EC, which
+causes the EC to pull the FDO pin low and the firmware to skip setting
+up any chipset based write protections [1]. The EC is the SMSC MEC5055,
+which seems to be compatible with the existing MEC5035 code.
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |  13 +-
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e6420/data.vbt  | Bin 0 -> 6144 bytes
+ .../variants/e6420/early_init.c               |  14 ++
+ .../snb_ivb_latitude/variants/e6420/gpio.c    | 191 ++++++++++++++++++
+ .../variants/e6420/hda_verb.c                 |  32 +++
+ .../variants/e6420/overridetree.cb            |  35 ++++
+ 7 files changed, 287 insertions(+), 1 deletion(-)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index 183a67bec3..d2786970ee 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -17,6 +17,12 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select SYSTEM_TYPE_LAPTOP
+ 	select USE_NATIVE_RAMINIT
+ 
+config BOARD_DELL_LATITUDE_E6420
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_10240
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOUTHBRIDGE_INTEL_BD82X6X
+
+ config BOARD_DELL_LATITUDE_E5530
+ 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select BOARD_ROMSIZE_KB_12288
+@@ -43,6 +49,7 @@ config MAINBOARD_DIR
+ 	default "dell/snb_ivb_latitude"
+ 
+ config MAINBOARD_PART_NUMBER
+	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
+ 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
+@@ -54,11 +61,15 @@ config USBDEBUG_HCD_INDEX
+ 	default 2
+ 
+ config VARIANT_DIR
+	default "e6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "e5530" if BOARD_DELL_LATITUDE_E5530
+ 	default "e6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "e6530" if BOARD_DELL_LATITUDE_E6530
+ 
+ config VGA_BIOS_ID
+-	default "8086,0166"
+	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
+	default "8086,0126" if BOARD_DELL_LATITUDE_E6420
+	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
+		|| BOARD_DELL_LATITUDE_E6530
+ 
+ endif
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index c15ef4028f..257d428a70 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -1,5 +1,8 @@
+ ## SPDX-License-Identifier: GPL-2.0-only
+ 
+config BOARD_DELL_LATITUDE_E6420
+	bool "Latitude E6420"
+
+ config BOARD_DELL_LATITUDE_E5530
+ 	bool "Latitude E5530"
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd
+GIT binary patch
+literal 6144
+zcmeHKeQZ-z6hE);wSBvNZ|mO1=*HLC2BQN8uVX6{N9eY)75ORymb$R8!YYuAZEgeE
+zKk|S@Fen*n41W-viAF;r%)~^EkpLz-B{2q##)LmGAtoY;7*Qhv_1yPbw$TC$2}G0K
+z=6Ao&x#ym9?z!i_&TOh(kLzky2cN8MTpny#R<;VU4Rkn?rBIz(YL~BBw<%b&zGhSH
+z$~AQ>@D0d=Xx6RE0BwSxspWdrW9y<FZGD@&x3_JL;p$p!;!BVdcKLkht0=-%(Jj&T
+z_GkyztZ%>#t7^)^(T-R<7W?O6ZTI%A+j=`<Jw3Q%dk6N!da<_?7oyiU3)^<~_TiSk
+zE$y+=RK3PGQ`gzmXYPRBx>C|f*UP9{h|4>ANrAe~?ymV*)83AaT#FuTjP=C2cg5P~
+zt4w78r$t#300cWY_k)mevmAmFI3&oBfytoAAPQiYK$XEIgHwV@5-gJ-Q-*p8yfTDj
+zaDz=1Y!X1B3`OpQ&Ik}bM|0xHn0gYNZw0rT=7AXS2in-q8K^?)0|el+Z6geW7i7MM
+zv~!|>HqL-|Fk}EYOa@)R<X)VQ7c}d8R1b@RTn5rq(90|QRg0?wwZZz(6Dz}w>zg9Y
+z8;!mD_V*XSjT33~$`o`s>zEGBq8AQ`HaH?y!Fh2QiX1v@aCo4LaENf&DZ_cE2A2qb
+z5@cC}X)=S^1RvpXLWs~v*hqMau$!=t@B-mg!XV)|;eEm>!Z6`H;R4|&!d1d`f|S7^
+zli+B98*!TfPE&6~NVM5j3v{N3OTjpnm_L@BPh(}esd(J!gj?~iJP?n|OZZOiTqlql
+zg<NWR@g&-*W-E%A7|*1Z_`sVO$K&iAP+VIj9{<1hT%SXsK}IBk8!daftR`6-)EUiS
+zvv*HR(#-ZwhA~7wcmxbe4%E?Y7P0y{1q|nqR1L29UR8v@#No^g5MH)7!>{%-$T|cR
+zZx5|xm>Fl>;@$m};P{0WC>O~<Nl1`*PLgPN_hP2a^h+L$ls&SYrkDYr+&l*%%S?^Q
+ziPSdtHE<LNEnr7cs=ihL-C>-p>*$9CpHRLgN|POkqD^UP4nw|4nf0bc8MOBk<;%js
+zfpCAWNzqSPlz@X%j9CGrwZDKUl@K{g6pzqiIIARDQ)#@^RW&0pmNG;XZ?!SlHB?L#
+zKRAMgq(R;aQd%@Gy38-LS@ix)fR**(P3B9wI=Uk^&cWmmwB<vf21<0#LBA!;qtAh(
+zYe5g_T{+gw^mi8QzPPraBoH~8oCz%r=$nVi1A)`Y8IKqIdqm6MihqxtpFaTggaPxu
+zQP07nf#&kPkPp}Cmk$F1g7q7QK;kz~80i&oDN}~wYbPUI6AtG5H+$T!@f5FzUhp21
+z^XiPT3rb%B@sA9g!n88R7BOsLS|?+D3}0v3dyIX|@JFWo&e%<c#V)PV#g@7-=F*;V
+zvAr&Q+ogTvVxPM3XP5Smi`f;Nt7uCU)}Y`HMcbpW=M_AuXlE35PQl+4O{7m66&I@7
+zGL@}Sai^*sP}va`KTx$VRQ8REf2*1+lTFH0=UkNx+eN|1rVyipl)Du=h=@%w+iQZG
+zT6@-PdW^oyFb44AG`HMZWEnP{&OQ+jC`N4emoS)x;EPN}uaSFOf-Mn8JRRO&LTWJc
+zn6%=L94~PR)%Ua_HTZcfTXD<p{%8p|<N<;Efw$Zb4$}{m8@7c((~<7^thaau&@Wx#
+zVGNL)lmH@{o=h*{muXGc!;nXrVgpp3;1V1stMj=4AtxyzX+?SoB~zN}!*r?9Qvs1P
+zmV_(CTmt0sY&6=F=_M>E34GYvuh1uQF+BUdWyQC5SaEM1QvKlHBMs13C}n{0SwRxW
+ziekMa&kvRFruRcKCevGy5)TxUBDlur@E{TtQ^NQ>nO+Cgl)&Ga(PxqVW?e3TLH-UY
+zdL3T{z^xdd`$(STFUb8R*cKa}r>n{Wk+MXRH~o-hN}#9OF*>T#>rfhiRs(Wc-R^9@
+z%F=<}dn(E}ADc03zJ>JvZe;_8f+WFLL4%qNYs`_aa`a$Pl5H;iO^Wt*cP3W(d=(g}
+zZ%nKT1$|r-tAv8($u2-BI2Uiz#%OT&!Q3b~Ru2P2j;Gem!@wfPsTR%J>W{8z)oq^J
+k^Qm&?O@bFkw4CTocwoW<6CRlGz=Q`TJTT#bN9KWl0rH4|j{pDw
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
+new file mode 100644
+index 0000000000..ff83db095b
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMB_LPC_EN | COMA_LPC_EN);
+	mec5035_early_init();
+}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
+new file mode 100644
+index 0000000000..943c743f48
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
+@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_NATIVE,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_GPIO,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_LOW,
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
+new file mode 100644
+index 0000000000..ede8445aaf
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
+	0x10280493,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x10280493),
+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+	0x80862805,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
+new file mode 100644
+index 0000000000..3012a3177f
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
+@@ -0,0 +1,35 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x0493 inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x0000054f"
+			register "gpu_pch_backlight" = "0x13121312"
+		end
+
+		chip southbridge/intel/bd82x6x
+			register "usb_port_config" = "{
+				{ 1, 1, 0 },
+				{ 1, 1, 0 },
+				{ 1, 1, 1 },
+				{ 1, 1, 1 },
+				{ 1, 0, 2 },
+				{ 1, 1, 2 },
+				{ 1, 1, 3 },
+				{ 1, 1, 3 },
+				{ 1, 1, 5 },
+				{ 1, 1, 5 },
+				{ 1, 1, 7 },
+				{ 1, 1, 6 },
+				{ 1, 0, 6 },
+				{ 1, 0, 7 },
+			}"
+
+			device ref sata1 on
+				register "sata_port_map" = "0x3b"
+			end
+		end
+	end
+end
+-- 
+2.39.2
+
@@ -1,332 +0,0 @@
-From c2a05f102ca378d8e23f0485d680845584efa290 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Thu, 26 Sep 2024 19:51:25 -0600
-Subject: [PATCH 20/41] mb/dell/gm45_latitudes: Add E4300 variant
-
-Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/gm45_latitude/Kconfig      |   5 +
- src/mainboard/dell/gm45_latitude/Kconfig.name |   3 +
- .../gm45_latitude/variants/e4300/data.vbt     | Bin 0 -> 3881 bytes
- .../variants/e4300/gma-mainboard.ads          |  17 +++
- .../dell/gm45_latitude/variants/e4300/gpio.c  | 138 ++++++++++++++++++
- .../gm45_latitude/variants/e4300/hda_verb.c   |  37 +++++
- .../variants/e4300/overridetree.cb            |  10 ++
- 7 files changed, 210 insertions(+)
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-
-diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
-index 5020744990..d27d5728a8 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig
-@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
- config BOARD_DELL_E6400
- 	select BOARD_DELL_GM45_LATITUDE_COMMON
- 
-+config BOARD_DELL_E4300
-+	select BOARD_DELL_GM45_LATITUDE_COMMON
-+
- if BOARD_DELL_GM45_LATITUDE_COMMON
- config INTEL_GMA_DPLL_REF_FREQ
- 	default 100000000
-@@ -30,12 +33,14 @@ config MAINBOARD_DIR
- 
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E6400" if BOARD_DELL_E6400
-+	default "Latitude E4300" if BOARD_DELL_E4300
- 
- config OVERRIDE_DEVICETREE
- 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
- 
- config VARIANT_DIR
- 	default "e6400" if BOARD_DELL_E6400
-+	default "e4300" if BOARD_DELL_E4300
- 
- config USBDEBUG_HCD_INDEX
- 	default 1
-diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
-index aefe777109..4dc95f46be 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig.name
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig.name
-@@ -1,4 +1,7 @@
- ## SPDX-License-Identifier: GPL-2.0-only
- 
-+config BOARD_DELL_E4300
-+	bool "Latitude E4300"
-+
- config BOARD_DELL_E6400
- 	bool "Latitude E6400"
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3
-GIT binary patch
-literal 3881
-zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+
-zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5a<biIGGii6#d8gP4#QmGpeGyBx))(i;53
-zx0(69nR)Nco0&Inc1d4HFVD7b?CrX@org342aOf$sh&<9U7NP<Sl8a$zN4diQ+5M?
-z9rN*fa`GZDAW257d6jcVwtw%wp<VsFPss9IbIT6VyT7@GKQuhTyNCDm-+uql-l6R9
-zaA9y{CEr#U=-)Ruz;_Pq?H?H$9GyPr&Fjey7akuO+O>Nhx3i7B*>RjEs#<v0-hG36
-zcy@TCu#&g$*~7O8nNhxFaCC5F|KPw%gBc7st!SzQND;)Ih9pfkBd$T$U~A~qu#ltO
-zMczfDhAs`eH4JHpsJLH4lZIP4`dyfi4M|pkg+SayZ(n(7kunGFvl<qe=w81$=+A#a
-zN=hgb2&njUcPLB!=P$(o-$={^mxQGIHvtVGBS4IU%YyNVhd3krw*m^es@B12UftTZ
-zHsf}zTi<zK_vS6VeYx!qdQTpH>PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC
-zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpD<v6uK&w=s5=N^P
-zn1nKYZrHyr#A-t5vRX$dPN$Pl=yivfA{67CP>h$)OQqAIh6jOwCxuw)qvS0N+Nk!?
-zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E
-z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u
-z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L<DD#SV;6@`cGC4?jgJ8YLq>~qi^
-z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I<Q#e&+8Yy!=BeKi&0@sfte<K0&
-zMgsgs0(vE~6cP&098SWEom4ZZF%<l!OeEuw4n?=)Y_tg#&wy^{e@5{s`F9qRm`5m;
-zi_|4iQq@4&R8mD)tJIvCw3$`@-B9JV=`1}s_;B_rjtcVXpQ!o`MAJ$M5w65C7t<Ku
-z%xfIo$p$+0N}Qe(C7MY#!0SQ1({^-qFj5ylEHjhwn>8}OhGtOw#1e$Fn9w<r1Zp}l
-zPz$#mOP$ow*1(UHvmCGVz;T^IRnSxa*6jz+_oSD)xmT|Cbl&YcJ5M&d?&+&NDI2Y0
-zO0ai&>sUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6
-z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e%
-zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D
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-zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG*
-zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg
-zI{c?gKNv~R$<jgIlQvzm9GD`y{Dh<T(H)!WlUUWvtFvzDqaVV>&eHj<So5w}UG%+7
-zt=J~1YHpT3TjRY{XlrmCz6QBZ$WqGr>8!uus22Br_GkCD$Q)pf!<P$30Ez;o=qDzr
-z7@f;LJ+ZPlo=?}4PvMm&OKLGLZ0h1&n7U8@9GP~;8!wz(OqQ<s6e;@8hfYU0ht*9>
-zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K<j&AXad#XeO8mgw(v
-z_Gj1VBJZIpZ<>`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692<oYlGx5_cte6LX
-JE5(FU=`RLB=-&VU
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
-new file mode 100644
-index 0000000000..89b81b3d69
--- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
-@@ -0,0 +1,17 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (DP2, -- dock DP
-+      Analog, -- mainboard VGA
-+      LVDS,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
-new file mode 100644
-index 0000000000..b50f8da0b5
--- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
-@@ -0,0 +1,138 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0  = GPIO_MODE_NATIVE,
-+	.gpio1  = GPIO_MODE_GPIO,
-+	.gpio2  = GPIO_MODE_GPIO,
-+	.gpio3  = GPIO_MODE_GPIO,
-+	.gpio4  = GPIO_MODE_GPIO,
-+	.gpio5  = GPIO_MODE_GPIO,
-+	.gpio6  = GPIO_MODE_GPIO,
-+	.gpio7  = GPIO_MODE_GPIO,
-+	.gpio8  = GPIO_MODE_GPIO,
-+	.gpio9  = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_NATIVE,
-+	.gpio16 = GPIO_MODE_NATIVE,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_GPIO,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_GPIO,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_NATIVE,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio1  = GPIO_DIR_INPUT,
-+	.gpio2  = GPIO_DIR_INPUT,
-+	.gpio3  = GPIO_DIR_INPUT,
-+	.gpio4  = GPIO_DIR_INPUT,
-+	.gpio5  = GPIO_DIR_INPUT,
-+	.gpio6  = GPIO_DIR_INPUT,
-+	.gpio7  = GPIO_DIR_INPUT,
-+	.gpio8  = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio18 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio20 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio1  = GPIO_INVERT,
-+	.gpio7  = GPIO_INVERT,
-+	.gpio8  = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_NATIVE,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_NATIVE,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_GPIO,
-+	.gpio54 = GPIO_MODE_NATIVE,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio53 = GPIO_DIR_INPUT,
-+	.gpio56 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode      = &pch_gpio_set1_mode,
-+		.direction = &pch_gpio_set1_direction,
-+		.level     = &pch_gpio_set1_level,
-+		.blink     = &pch_gpio_set1_blink,
-+		.invert    = &pch_gpio_set1_invert,
-+	},
-+	.set2 = {
-+		.mode      = &pch_gpio_set2_mode,
-+		.direction = &pch_gpio_set2_direction,
-+		.level     = &pch_gpio_set2_level,
-+	},
-+};
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
-new file mode 100644
-index 0000000000..a9948a93dd
--- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
-@@ -0,0 +1,37 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	/* coreboot specific header */
-+	0x111d76b2, /* IDT 92HD71B7X */
-+	0x1028024d, /* Subsystem ID */
-+	13,	    /* Number of entries */
-+
-+	/* Pin Widget Verb Table */
-+
-+	AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
-+	AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
-+	AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
-+	AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
-+	AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
-+	AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
-+};
-+
-+const u32 pc_beep_verbs[] = {
-+	0x00170500, /* power up codec */
-+	0x00d70500, /* power up speakers */
-+	0x00d70102, /* select mixer (input 0x2) for speakers */
-+	0x00d70740, /* enable speakers output */
-+	0x02770720, /* enable beep input */
-+	0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
-+	0x00d37000, /* unmute speakers */
-+};
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-new file mode 100644
-index 0000000000..20dfa245fb
--- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-@@ -0,0 +1,10 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/gm45
-+	device domain 0 on
-+		subsystemid 0x1028 0x024d inherit
-+		chip southbridge/intel/i82801ix
-+			device pci 1c.2 off end # PCIe Port #3
-+		end
-+	end
-+end
-- 
-2.47.3
-
@@ -0,0 +1,449 @@
+From 1111dcab65ca83f175f1bb9c0496cae24fbfb7c2 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Wed, 31 Jan 2024 22:07:25 -0700
+Subject: [PATCH 21/39] mb/dell: Add Latitude E6520 (Sandy Bridge)
+
+Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was
+not tested. I do not physically have this system; someone with physical
+access to one sent me the output of autoport which I then modified to
+produce this port. I was also sent the VBT binary, which was obtained
+from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the
+vendor firmware.
+
+This was originally tested and found to be working as a standalone board
+port in Libreboot, but this variant based port in upstream coreboot has
+not been tested.
+
+This can be internally flashed by sending a command to the EC, which
+causes the EC to pull the FDO pin low and the firmware to skip setting
+up any chipset based write protections [1]. The EC is the SMSC MEC5055,
+which seems to be compatible with the existing MEC5035 code.
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |   9 +
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e6520/data.vbt  | Bin 0 -> 6144 bytes
+ .../variants/e6520/early_init.c               |  31 +++
+ .../snb_ivb_latitude/variants/e6520/gpio.c    | 190 ++++++++++++++++++
+ .../variants/e6520/hda_verb.c                 |  32 +++
+ .../variants/e6520/overridetree.cb            |  35 ++++
+ 7 files changed, 300 insertions(+)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index d2786970ee..72bdc96c0a 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -23,6 +23,12 @@ config BOARD_DELL_LATITUDE_E6420
+ 	select MAINBOARD_USES_IFD_GBE_REGION
+ 	select SOUTHBRIDGE_INTEL_BD82X6X
+ 
+config BOARD_DELL_LATITUDE_E6520
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_10240
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOUTHBRIDGE_INTEL_BD82X6X
+
+ config BOARD_DELL_LATITUDE_E5530
+ 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select BOARD_ROMSIZE_KB_12288
+@@ -50,6 +56,7 @@ config MAINBOARD_DIR
+ 
+ config MAINBOARD_PART_NUMBER
+ 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
+	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
+ 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
+@@ -62,11 +69,13 @@ config USBDEBUG_HCD_INDEX
+ 
+ config VARIANT_DIR
+ 	default "e6420" if BOARD_DELL_LATITUDE_E6420
+	default "e6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "e5530" if BOARD_DELL_LATITUDE_E5530
+ 	default "e6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "e6530" if BOARD_DELL_LATITUDE_E6530
+ 
+ config VGA_BIOS_ID
+	default "8086,0116" if BOARD_DELL_LATITUDE_E6520
+ 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
+ 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420
+ 	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index 257d428a70..c7665ac263 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -3,6 +3,9 @@
+ config BOARD_DELL_LATITUDE_E6420
+ 	bool "Latitude E6420"
+ 
+config BOARD_DELL_LATITUDE_E6520
+	bool "Latitude E6520"
+
+ config BOARD_DELL_LATITUDE_E5530
+ 	bool "Latitude E5530"
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
+GIT binary patch
+literal 6144
+zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN)
+z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y
+z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+
+z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7
+zcXx+--0R}IwzW3-+`f2k?^Av5V7MpRO-q(9rn_R1@Xlz2Ztdy`$Gf6^w6~|bKi!!7
+z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ
+z)4V8f0Gt`D`+>9Fr~tnJ76EJ`5D_F1cn-`0$RgN9unI6kfYkzIiO?W`ON4+34lv1_
+zNdPDkq1cf$p8^EW;TS*O$CdzNo#1fbIG_Oi0T(ti0jwyt0le_p_HlvX^CFvr)>$b>
+zO-z8^CSU`w=mIK7Q)@9fR;XUzrFu{T=rRyygIZBpU9+Or>+?4R9%~G?Y-|g)Z`Sti
+z+do(U*Wb-xR~DzjS<75#=Us4sH^C9U2FCbND7L7u$>M|<;t=AnRfI9C0v8c~AVg7t
+zIU<3D2oK^>L;%r(*o=4*u?Mja@dDyi#4zFn;(f#^#3*76aUSs#;tJv#La-6YLRdQB
+zdcvfERkvH?k~GJlfM<HR476j(@nfm+47<!Ult@^ua5M3h6A}q=C0ognX9aX4mxq)U
+zXOhm=DbLene?C%_16Q)2NRV@Yacz`D;{V>Ve-1?&ZXy}n)YwnVAgNlz#zX;=IX)-F
+z)9LL3lbEdY5Co)LsK?vP)7s}G(5xduE!Y!#Wgh<IN3(3ey=-oWU(9aEJ_HzV53Jbq
+zj5B5RjzLUt>_T&xi$uUA#0e}X3D~`J(bHz;DgTa@GrpW6=>eZwJeNYYo*GjF=``;(
+zuoQ3|V5YoKd$j=KK{`uSX*DeU1oJg=+RT6)rLe6%2>Ci^!5ao=*gS}wFN=nUf`fTF
+zM?Gb5ycWjM7I?MJ!2;w|LFg=UoLq-ytr2iemG)AsW}bI4X9PK}T5UKsQi7anu=tD6
+zf|={kXkNeQBD>6bQ3taC8XJOJ^e40_ydyfr&a41L^1)jNrK<B_wV}+ZE`p;QK=rDz
+zTw`SJ+e`Oc*icaF4INF51Xg*~ts@m)@9ETt(*@N7yy0)Ddce%i9{^k2kbd8=Wns~P
+zWBD$~himxDharxF@f!ti^0$~9Zxt{tg`@Dbl_0Ki2Xp_MEw-<z6qgep;XYmR%Dl-F
+z%3cBfcN;Avikpz-gmw_6mymu!Unk0YgnUfsk3{*6kQ;=S*p(_fS!JhDyYh^k?6uRk
+z?8--W@~NHvY*+ra6SG9iC1s^V)<|@Rqzp*pd5NBslrs`JC(&Oeg~v}CnJ$x+)iP<8
+z=`LA0Ad@39{XkZ}kjXbP{YzHtS!70*yy%LcnJ#cz4u%*Wq!^d*AVMZdr&l=#Qgik~
+ze2l)cX+!kF9EaFhY;0^Uo_#VNC?7K2Tf=ZR1y5);b!mCGG?<cc#M0rtHKYeKi%BE?
+z@Y6|P8fx#li}c`Uv24UGyZaM0To;Ep<_AWZA1t~bFgI)uf}&Eq=L_Cs89=>wnT0Vx
+z-jp>o1ffJNommZ4?=TIPlePIw0hgQ706f*tBC`#pg>9&zRHe>J2%RxBTrOc6Adh9E
+ziJr`?VQH!N!_GkoKaoq|+3$^Ae0#sUxXlmM1Huq~g<=Ls?ILv+nQcH%PQedGOlH=Q
+z77rMcJlH4Mkc#U2(IDv>rsm1aHpsdL_RdT^i_ACcQUMIJcSus}*(?CIiy^#^=t=g1
+z+*^Zbh30&^#_bKclSy9pL$<B~pK8m*sLpIdnHM@W$nA7Ea@Z`x27K?aNK<@lCW(2L
+zb@kB3H8kKy4W3Hu)NN|kd!DL^o#iR9a{QYV-Wl&r&hmIFX{ezkIV<4zFiVUQ@K>ao
+z00DnFy~Uek!JRwhVX!of0)$Sa*X^S~LMQH0<E(UUx}L=|;Kgw(r(4q=nD)T52c|tR
+O?SW|zOncy=dEg(6JAK&z
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
+new file mode 100644
+index 0000000000..b6415a428b
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
+@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{ 1, 1, 0 },
+	{ 1, 1, 0 },
+	{ 1, 1, 1 },
+	{ 1, 1, 1 },
+	{ 1, 0, 2 },
+	{ 1, 1, 2 },
+	{ 1, 0, 3 },
+	{ 1, 0, 3 },
+	{ 1, 1, 5 },
+	{ 1, 1, 5 },
+	{ 1, 1, 7 },
+	{ 1, 1, 6 },
+	{ 1, 0, 6 },
+	{ 1, 0, 7 },
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMB_LPC_EN | COMA_LPC_EN);
+	mec5035_early_init();
+}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
+new file mode 100644
+index 0000000000..61f01816c4
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
+@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_NATIVE,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_GPIO,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_LOW,
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
+new file mode 100644
+index 0000000000..ae376691e7
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
+	0x10280494,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x10280494),
+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+	0x80862805,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
+new file mode 100644
+index 0000000000..f90f2dee1f
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
+@@ -0,0 +1,35 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x0494 inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x00001312"
+			register "gpu_pch_backlight" = "0x13121312"
+		end
+
+		chip southbridge/intel/bd82x6x
+			register "usb_port_config" = "{
+				{ 1, 1, 0 },
+				{ 1, 1, 0 },
+				{ 1, 1, 1 },
+				{ 1, 1, 1 },
+				{ 1, 0, 2 },
+				{ 1, 1, 2 },
+				{ 1, 1, 3 },
+				{ 1, 1, 3 },
+				{ 1, 1, 5 },
+				{ 1, 1, 5 },
+				{ 1, 1, 7 },
+				{ 1, 1, 6 },
+				{ 1, 0, 6 },
+				{ 1, 0, 7 },
+			}"
+
+			device ref sata1 on
+				register "sata_port_map" = "0x3b"
+			end
+		end
+	end
+end
+-- 
+2.39.2
+
@@ -1,70 +0,0 @@
-From 2305cfb93110003613caa1dec8c5f574b5e400bd Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 3 May 2024 16:31:12 -0600
-Subject: [PATCH 21/41] mb/dell: Add S3 SMI handler for Dell Latitudes
-
-Integrate the previously added mec5035_smi_sleep() function into
-mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
-The E6400 does not require the EC command to sucessfully suspend and
-resume from S3, though sending it does enable the breathing effect on
-the power LED while in S3. Without it, all LEDs turn off during S3.
-
-Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/gm45_latitude/smihandler.c    | 9 +++++++++
- src/mainboard/dell/haswell_latitude/smihandler.c | 9 +++++++++
- src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
- 3 files changed, 27 insertions(+)
- create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c
- create mode 100644 src/mainboard/dell/haswell_latitude/smihandler.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
-
-diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
--- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_smi_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/haswell_latitude/smihandler.c b/src/mainboard/dell/haswell_latitude/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
--- /dev/null
-+++ b/src/mainboard/dell/haswell_latitude/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_smi_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
--- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_smi_sleep(slp_typ);
-+}
-- 
-2.47.3
-
@@ -1,31 +0,0 @@
-From aafddebf91f185d9c72fa1492af9128ee4803239 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 31 Dec 2024 14:42:24 +0000
-Subject: [PATCH 22/41] Disable compression on refcode insertion
-
-Compression is not reliably reproducible. In an lbmk release
-context, this means we cannot rely on vendorfile insertion.
-
-Therefore, use uncompressed refcode.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- Makefile.mk | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/Makefile.mk b/Makefile.mk
-index 75787b32d4..3616f4fe68 100644
--- a/Makefile.mk
-+++ b/Makefile.mk
-@@ -1422,7 +1422,7 @@ endif
- cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
- $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
- $(CONFIG_CBFS_PREFIX)/refcode-type := stage
-$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG)
-+$(CONFIG_CBFS_PREFIX)/refcode-compression := none
- 
- cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
- vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
-- 
-2.47.3
-
@@ -0,0 +1,442 @@
+From 39dcb2dcada8821c49a3a042d9e70a6cda81a4ab Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Wed, 7 Feb 2024 10:23:38 -0700
+Subject: [PATCH 22/39] mb/dell: Add Latitude E5520 (Sandy Bridge)
+
+Mainboard is Krug 15". I do not physically have this system; someone
+with physical access to one sent me the output of autoport which I then
+modified to produce this port. I was also sent the VBT binary, which was
+obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
+A14 of the vendor firmware.
+
+This was originally tested and found to be working as a standalone
+board port in Libreboot, but this variant based port in upstream
+coreboot has not been tested.
+
+This can be internally flashed by sending a command to the EC, which
+causes the EC to pull the FDO pin low and the firmware to skip setting
+up any chipset based write protections [1]. The EC is the SMSC MEC5055,
+which seems to be compatible with the existing MEC5035 code.
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |  10 +-
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e5520/data.vbt  | Bin 0 -> 6144 bytes
+ .../variants/e5520/early_init.c               |  14 ++
+ .../snb_ivb_latitude/variants/e5520/gpio.c    | 195 ++++++++++++++++++
+ .../variants/e5520/hda_verb.c                 |  32 +++
+ .../variants/e5520/overridetree.cb            |  39 ++++
+ 7 files changed, 292 insertions(+), 1 deletion(-)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index 72bdc96c0a..4e94a7ef80 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select SYSTEM_TYPE_LAPTOP
+ 	select USE_NATIVE_RAMINIT
+ 
+config BOARD_DELL_LATITUDE_E5520
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_6144
+	select SOUTHBRIDGE_INTEL_BD82X6X
+
+ config BOARD_DELL_LATITUDE_E6420
+ 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select BOARD_ROMSIZE_KB_10240
+@@ -55,6 +60,7 @@ config MAINBOARD_DIR
+ 	default "dell/snb_ivb_latitude"
+ 
+ config MAINBOARD_PART_NUMBER
+	default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
+ 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
+@@ -68,6 +74,7 @@ config USBDEBUG_HCD_INDEX
+ 	default 2
+ 
+ config VARIANT_DIR
+	default "e5520" if BOARD_DELL_LATITUDE_E5520
+ 	default "e6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "e6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "e5530" if BOARD_DELL_LATITUDE_E5530
+@@ -77,7 +84,8 @@ config VARIANT_DIR
+ config VGA_BIOS_ID
+ 	default "8086,0116" if BOARD_DELL_LATITUDE_E6520
+ 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
+-	default "8086,0126" if BOARD_DELL_LATITUDE_E6420
+	default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
+		|| BOARD_DELL_LATITUDE_E5520
+ 	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
+ 		|| BOARD_DELL_LATITUDE_E6530
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index c7665ac263..7976691f21 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -1,5 +1,8 @@
+ ## SPDX-License-Identifier: GPL-2.0-only
+ 
+config BOARD_DELL_LATITUDE_E5520
+	bool "Latitude E5520"
+
+ config BOARD_DELL_LATITUDE_E6420
+ 	bool "Latitude E6420"
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729
+GIT binary patch
+literal 6144
+zcmeHKZ){Ul6hE);wSBvNZ|mL$bmQOM2BTvXUI!}^N9ejTij1vnu+)Wx6<c9(Y_%K6
+zzOV-@f<ehpWB5RHBpMBgG7}RuMuM2=l*E{6G$wq&gqTQ3#E2RZsOP@dvW*rP7>Fjj
+z&F`Lj?>YC}bI(2Z+}C+6zKyiGrosQXuW7A+&1%<rN+Y1ck(}dLrx)Ma#^x>lnvFGE
+zeD#gB>*#Tq4&j^|7Xcz1r^pp*)g#T}u1Me3ct>Pgls5Qi3!6e2W0%`a-Ic|3efWuR
+zXJ@#}wJyGMTXTcY<%@TBKh@(3hP$Gjv}E}rx-%9D_eLXhYe!c&-VyDg-Cdo1>Biji
+zNNsnlFW#|jdoOj?mZ43m>cVO%UE9@*E7x|%V~c4`XD4l9GCi~@+7pfMibfX8L?!^I
+zc~Rg1I5SxH1DAEZ0{jA41jrJBh#-l;b6^%g7QrThRe)&%tQH_!ggOD7A_PRRgGuI0
+z0zi=n#rCB66d-sO$M~^6wgeb$2fH1|0R`v}xUiWCU`4SF;Dyh&j|mK&6WJWJ&Pq9I
+zVgmFQfh+)vE}(KWwHA|Oh3fSkss|;2E(2i}s1?gRRV%8!K7U={vHD=s#+Fd)W^M1j
+z{R4$??VSvEWpgT=vCM&1-U$bI6CB~IV3Z$$Vv7o!EDnev4j~R(MHsazZ~^fLLKGF4
+zEfQFOa3dZ?1Q1P#&4?!vyAk^k&m&$z3?WV+-b0*1j37o4=MX<3E+eiYge(Ht2umAW
+zOPDmU>UL{flI9u|@JtVvfp#o8ek?VfVV9YP5(%pnZX~{PKq4WoWGmV8t$=Ri@{zLQ
+zNYYt4<$0Ry&qIoG;7s-t333)Nu8opN{NG!)&!I@eO(cVx8vBVEBvotJ7%yNl$7iQ_
+zI=xk30+V$ff`F6<wRoF(TK%j9nsr#H23umU%)_7jNOl%*FPU567qbg;4gtp711nj2
+z#+kHw`v4|5cA+`UMIvAl;slnH1nl0v=xH<al>1}ljxDE1dcda^&!do|r^eJkI?aC-
+zEQMSfm?<w*Unzumkj_w5>VYL6W4=aCiy4rk%xq~5LV?bi|GL2$G7li<%c7yd;6T34
+zQBN5huZ3~6`ChGkpb$Bg5ITb#2iK-qs|1`=sl6Dhn(Lj&8Agt?S{sTDmmtRj7Jm_1
+zFnt{w&FdFkWS3bl>OeL?eO+*i{)9G!cSI-InGt|U0eEYmRCOHm7|I;#LO8ksRIeJ#
+zGe+jTwPg4C4TYuN(9zULV3k+hI$YuPo=%N8oZ#u_4S!3Xelt6N0BmuC`hCNeg+&97
+z6*!>)uHvr%2004GZv?!_-y&|TRmil=9D%Q`1aXBsnD^gov3*UZI34&1_vn(B=T4kZ
+z_A>ClXVIBNaS^hd&^DrU6VgZMYeadMkdFxcktn|ra-Gl;n^I{bt86rCQ=YMry*B!$
+zP5ID9KDE)GZOY#^VwPyRq^y+48j0?ZlzxdkC()CV@`*&wO7vGr;qjA3rb}gIwM-gi
+zx>HsT$mEDj-<OpyWb%zn|B@A3Hkp<!FT5;hrt_SZiy?*wDaIu{h>%Ir=@rh7)SR;b
+zAEWQGv_X1)wq0y5Ha0c~&psIsln<Hiu3;#Lf;%*eI<@?p8cfMJV(IYi8q$NA#iS8`
+z_~|4t4b^wtMSAeFST^F8-Tm<zu8D&j^8=&I4;I}Im>aeSK~X8*^Z9SE44_`P#KIUL
+zf6^N2f>5HCPWM3N+f0MyWOV^kz~!-wVc4MRXOY>4Jsxd1RyBKEMzNf{RKhesKFdbq
+zJ(*d<l2Y#n?E?~iBA39P?~Pr2d#}5=#Sfl-VGzGUF$4U2KcqCIVlwkC(&7PQk_X!a
+z8}3Jgq-&U*Co|h1>l)ZQGyW_x->i#;FvQ*=Nv&nG0N5@D@jjv_Q}K}6MP?1A6`JGe
+zDwj9pN+x;T4>`I9e5x(uqdK#OGB31ikk@Xv=dxLb4fx(;ktX@rOb~M~?dYQQYiPia
+z8r;jUQ?sd2@3||-cb2Eb%JFYfxHsONoaJ^eqoKN{<g9?-%`7oWz+aJS0tEc!^d@hD
+z1-I{%hr!Y?0uVZpUbl__37xn@jkD6Z>3SATgBQlEoN7&ZV9Eni9+>jLln16fFy(=V
+H=7E0zE^L4Z
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c
+new file mode 100644
+index 0000000000..ff83db095b
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMB_LPC_EN | COMA_LPC_EN);
+	mec5035_early_init();
+}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c
+new file mode 100644
+index 0000000000..f76b93d9f0
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c
+@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_NATIVE,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_NATIVE,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_GPIO,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_NATIVE,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_GPIO,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_OUTPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_OUTPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	.gpio56 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio46 = GPIO_LEVEL_HIGH,
+	.gpio50 = GPIO_LEVEL_HIGH,
+	.gpio51 = GPIO_LEVEL_LOW,
+	.gpio55 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_NATIVE,
+	.gpio69 = GPIO_MODE_NATIVE,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c
+new file mode 100644
+index 0000000000..1373975352
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
+	0x1028049a,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x1028049a),
+	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+	0x80862805,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb
+new file mode 100644
+index 0000000000..479d1b696e
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb
+@@ -0,0 +1,39 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x049a inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x00000218"
+			register "gpu_pch_backlight" = "0x13121312"
+		end
+
+		chip southbridge/intel/bd82x6x
+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
+			register "usb_port_config" = "{
+				{ 1, 1, 0 },
+				{ 1, 1, 0 },
+				{ 1, 1, 1 },
+				{ 1, 1, 1 },
+				{ 1, 1, 2 },
+				{ 1, 1, 2 },
+				{ 1, 1, 3 },
+				{ 1, 1, 3 },
+				{ 1, 1, 5 },
+				{ 1, 1, 5 },
+				{ 1, 1, 7 },
+				{ 1, 1, 6 },
+				{ 1, 1, 6 },
+				{ 1, 1, 7 },
+			}"
+
+			device ref gbe off end
+			device ref pcie_rp4 off end
+			device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet
+			device ref sata1 on
+				register "sata_port_map" = "0x3b"
+			end
+		end
+	end
+end
+-- 
+2.39.2
+
@@ -0,0 +1,442 @@
+From 948221e226340c1c5852a73d005ada18120de393 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Mon, 4 Mar 2024 18:05:43 -0700
+Subject: [PATCH 23/39] mb/dell: Add Latitude E5420 (Sandy Bridge)
+
+Mainboard is Krug 14". I do not physically have this system; someone
+with physical access to one sent me the output of autoport which I then
+modified to produce this port. I was also sent the VBT binary, which was
+obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
+A02 of the vendor firmware.
+
+This was originally tested and found to be working as a standalone board
+port in Libreboot, but this variant based port in upstream coreboot has
+not been tested.
+
+This can be internally flashed by sending a command to the EC, which
+causes the EC to pull the FDO pin low and the firmware to skip setting
+up any chipset based write protections [1]. The EC is the SMSC MEC5055,
+which seems to be compatible with the existing MEC5035 code.
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I0283653156083768e1fd451bcf539b4e028589f4
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |  10 +-
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e5420/data.vbt  | Bin 0 -> 6144 bytes
+ .../variants/e5420/early_init.c               |  14 ++
+ .../snb_ivb_latitude/variants/e5420/gpio.c    | 195 ++++++++++++++++++
+ .../variants/e5420/hda_verb.c                 |  32 +++
+ .../variants/e5420/overridetree.cb            |  39 ++++
+ 7 files changed, 292 insertions(+), 1 deletion(-)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index 4e94a7ef80..e6a21ffb99 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select SYSTEM_TYPE_LAPTOP
+ 	select USE_NATIVE_RAMINIT
+ 
+config BOARD_DELL_LATITUDE_E5420
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_6144
+	select SOUTHBRIDGE_INTEL_BD82X6X
+
+ config BOARD_DELL_LATITUDE_E5520
+ 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select BOARD_ROMSIZE_KB_6144
+@@ -60,6 +65,7 @@ config MAINBOARD_DIR
+ 	default "dell/snb_ivb_latitude"
+ 
+ config MAINBOARD_PART_NUMBER
+	default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
+ 	default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
+ 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
+@@ -74,6 +80,7 @@ config USBDEBUG_HCD_INDEX
+ 	default 2
+ 
+ config VARIANT_DIR
+	default "e5420" if BOARD_DELL_LATITUDE_E5420
+ 	default "e5520" if BOARD_DELL_LATITUDE_E5520
+ 	default "e6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "e6520" if BOARD_DELL_LATITUDE_E6520
+@@ -82,7 +89,8 @@ config VARIANT_DIR
+ 	default "e6530" if BOARD_DELL_LATITUDE_E6530
+ 
+ config VGA_BIOS_ID
+-	default "8086,0116" if BOARD_DELL_LATITUDE_E6520
+	default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \
+		|| BOARD_DELL_LATITUDE_E5420
+ 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
+ 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
+ 		|| BOARD_DELL_LATITUDE_E5520
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index 7976691f21..a3fa2b1837 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -1,5 +1,8 @@
+ ## SPDX-License-Identifier: GPL-2.0-only
+ 
+config BOARD_DELL_LATITUDE_E5420
+	bool "Latitude E5420"
+
+ config BOARD_DELL_LATITUDE_E5520
+ 	bool "Latitude E5520"
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57
+GIT binary patch
+literal 6144
+zcmeHKeQZ-z6hE);wSBvNZ!2$ObQ^;MgV6zl*Rhp}BXnCCMZU^_r7jRwT!kfLo8?3H
+zk9)u(7?cb(hChhTM57@QFfmbMB!G!dNsO6BW5OSp5EGF^jHnTTdhUBI+h`e+1ft1q
+z^SfW?+;h)4_uO+|XEfEV$91)<gOArWE)OnSTD}Ug6?8a~vz+SmQn!4~y3N7b^|hPp
+zR<5aEfv-b8M00Lk251!oO|8(YA6XaeXzkt-Z)@Ee!_{@z#Fro^?DqN4SGjRIu8KYp
+zZEufuU@5MM@7jv%h;75FS}ezKv?JDzCH}d%tE)A-GuDb*+B%}~w%88r>}c;!*XQ5O
+z)OU7u$J@4U+lk)#GSW%c%c)v`%R6?`w)LIyu6bD7-j0o&X9qUMcEsYlW3BU4rZRvt
+zqAUpjf*qXuLCCsU0YM2I5@gB1WKd)f1+Yt?%HWd0DZxYumP(K<LxTif8A39+!KMl}
+z31FHG)7?qk5g>e?=ER{f^&}W<0k@mxff(?6+Stw+s6y%k1mM$cLk#^FWWI*9bE1GY
+z&VY9?WC1u#23^3^UYw5?H0x2S2gN`x18Fko6_x(#MKyuCU_<D!mEp$qO_An}#@>DV
+zdkf*li41yW3p$*0Oo3+63kO6S91*KwP#l2i4jnc)JkUirL^$k}VbH0;CBh#BS=OLf
+zW-yE3BRon75gG{_2~QIC5cUzCC%i)FCmbidM>tIwAPf>N5Pl?FC0r*+Sq!oXj!keQ
+zVKcyK>TL+gc7oLco$28+FpeeXkEP}_Sea=mk#IWUR^m$!BogvszLPu83FJm0k6K<l
+z$#$~YiXtY*GpHp#@FvHJ1UnBD*H%d+{_j24XE4nmBa*?5mOWiold28s3}>*}<HaeO
+z+1|-8g2)FCfkDZIdb-Ub);z0#;XEbPfGe?A72!{DAUg|$m+Z~(i@h9j4gtm611ni(
+z#u>ACcP}M4exU`*MKVwl5+t6JBpTkmm}xWflKUe~7}`!#%z#gAo{NxUrpDAndYktu
+zI0}VLU`J7^xmF1AFiz5S^uzp*DPI$%$qq!(ikh0kP+(GKzF|@N?Y%_#Vp@M+xHr$F
+z=%+18z`-fT%z)9-TS$~Dh@2yeN7!UIt0h`fWxUu`JvA_ra*8P48l%7KR0&c1;0R75
+z4f0oz(xQ3MWqz5>qW5M4tZWExHs8<H(e1G@4km@5wEzOOP^x<l`YmA|eKs6j3wl8B
+z%C%;uygh%<#kGZ{fymL+OlV0!-*T!V5IB>X@p!@CBU=7e{5^Jl{s7by`po-AJqM2l
+znk(=^0bHkF0rUw7)^7j;$=_UIs8`6P6b-;vPDZ#U9L)W1_PAYRDP9k~;5$stt5ZiV
+zD0>;i-?OlYY2}P9WVnfGos4xee2r=EGWHR}ADH$VV>cO=xU?!4TjIi)OMBYI_PX#b
+zm-eBHed5BOT-x6*W>;{IqAga~G6lCQT93k>Q}CpsomJR*1%FjEkv?fuT%c-8RklXO
+zU8;6KWk*zeU)4TW+1D!mrE0EhHZfbBeN{4S7X@Pig%};A99QTdA~wZruL*8y?K!jP
+zG5R*k=);S}Zn<T;W!Mxt`(!+z7_r@3LVpf|FESauM&4}+wqzXfba-zG>A}on(uzNF
+zyu>BcjA})C@bg%<;+Eh2;Sz4heFFCbZ@C{FrXMIbYzu>?Bi-|vZ}JSFU%JA>7$7et
+z0Yo%CnOVZm#ZA}4kWZOn15};h5*#OM3b+6vHzgruMP>=5MNJK1y42{YgveP-!j%#(
+z0rGe@8t%!=66Ti%K4|Gx=o7gFp83wQ;+s3H7+r^SKlpp3KKcr!3@|n;NCH_=qL=3T
+zq3WH?en`b+W-HR-fnrhw*9aZ%M}lHX7@H?E>!6wv_&YQFEHdA$%Z1R--yub>=c@p?
+z6@7Fc$&>sAxwiz{BE$1kb$K9Co=ozlA973y^i(^BM|EZ$$^y`0KyHiMJ%O*XbfEX1
+ziZaH>W(1pWL0bo|T!x__N$^$DpmxI=bL6WUK3JGyn?rw-qC4ZA$yGjIB}N(=ldD2O
+zAJ@bxp<qR-3lIv<!P~SE8r*#_Ckl?$0|1fZ>2>n}u*mUIYFd>}O_wuwBD^r9<#=!0
+X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c
+new file mode 100644
+index 0000000000..ff83db095b
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMB_LPC_EN | COMA_LPC_EN);
+	mec5035_early_init();
+}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c
+new file mode 100644
+index 0000000000..f76b93d9f0
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c
+@@ -0,0 +1,195 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_NATIVE,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_NATIVE,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_GPIO,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_GPIO,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_NATIVE,
+	.gpio50 = GPIO_MODE_GPIO,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_GPIO,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_GPIO,
+	.gpio56 = GPIO_MODE_GPIO,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_OUTPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio46 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio50 = GPIO_DIR_OUTPUT,
+	.gpio51 = GPIO_DIR_OUTPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio53 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio55 = GPIO_DIR_OUTPUT,
+	.gpio56 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_LOW,
+	.gpio37 = GPIO_LEVEL_LOW,
+	.gpio46 = GPIO_LEVEL_HIGH,
+	.gpio50 = GPIO_LEVEL_HIGH,
+	.gpio51 = GPIO_LEVEL_LOW,
+	.gpio55 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_NATIVE,
+	.gpio69 = GPIO_MODE_NATIVE,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_GPIO,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio74 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c
+new file mode 100644
+index 0000000000..0bc6c35a63
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
+	0x1028049b,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x1028049b),
+	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0xd5a30130),
+
+	0x80862805,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb
+new file mode 100644
+index 0000000000..3f55bfd49d
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb
+@@ -0,0 +1,39 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x049b inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x00000c31"
+			register "gpu_pch_backlight" = "0x13121312"
+		end
+
+		chip southbridge/intel/bd82x6x
+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
+			register "usb_port_config" = "{
+				{ 1, 1, 0 },
+				{ 1, 1, 0 },
+				{ 1, 1, 1 },
+				{ 1, 1, 1 },
+				{ 1, 1, 2 },
+				{ 1, 1, 2 },
+				{ 1, 1, 3 },
+				{ 1, 1, 3 },
+				{ 1, 1, 5 },
+				{ 1, 1, 5 },
+				{ 1, 1, 7 },
+				{ 1, 1, 6 },
+				{ 1, 1, 6 },
+				{ 1, 1, 7 },
+			}"
+
+			device ref gbe off end
+			device ref pcie_rp4 off end
+			device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet
+			device ref sata1 on
+				register "sata_port_map" = "0x3b"
+			end
+		end
+	end
+end
+-- 
+2.39.2
+
@@ -1,187 +0,0 @@
-From 09febfb85eb176c8bf0e416412ed0b971dc2cefc Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 21 Apr 2025 02:58:47 +0100
-Subject: [PATCH 23/41] nb/intel/*: Disable stack overflow debug options
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/northbridge/intel/e7505/Kconfig       |  9 +++++++++
- src/northbridge/intel/gm45/Kconfig        |  9 +++++++++
- src/northbridge/intel/haswell/Kconfig     |  9 +++++++++
- src/northbridge/intel/i440bx/Kconfig      | 13 +++++++++++++
- src/northbridge/intel/i945/Kconfig        |  9 +++++++++
- src/northbridge/intel/ironlake/Kconfig    |  9 +++++++++
- src/northbridge/intel/pineview/Kconfig    |  9 +++++++++
- src/northbridge/intel/sandybridge/Kconfig |  9 +++++++++
- src/northbridge/intel/x4x/Kconfig         |  9 +++++++++
- 9 files changed, 85 insertions(+)
-
-diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
-index 039a7396f8..ddcb986f10 100644
--- a/src/northbridge/intel/e7505/Kconfig
-+++ b/src/northbridge/intel/e7505/Kconfig
-@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505
- 	select NO_CBFS_MCACHE
- 	select SMM_TSEG
- 	select NEED_SMALL_2MB_PAGE_TABLES
-+
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
-index 35e89b0c88..c5456d0ddf 100644
--- a/src/northbridge/intel/gm45/Kconfig
-+++ b/src/northbridge/intel/gm45/Kconfig
-@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- 	default 0xfed19000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
-index c57f1ec380..0a5181b183 100644
--- a/src/northbridge/intel/haswell/Kconfig
-+++ b/src/northbridge/intel/haswell/Kconfig
-@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL
- 
- if NORTHBRIDGE_INTEL_HASWELL
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- config USE_NATIVE_RAMINIT
- 	bool "[NOT COMPLETE] Use native raminit"
- 	default n
-diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
-index dbb2d7436b..5e9418b6a9 100644
--- a/src/northbridge/intel/i440bx/Kconfig
-+++ b/src/northbridge/intel/i440bx/Kconfig
-@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM
- 	  If your board has 4 DIMM slots, you must use select this option, in
- 	  your Kconfig file of the board. On boards with 3 DIMM slots,
- 	  do _not_ select this option.
-+
-+if NORTHBRIDGE_INTEL_I440BX
-+
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
-+endif
-diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
-index c4e17f90bf..b12f5be091 100644
--- a/src/northbridge/intel/i945/Kconfig
-+++ b/src/northbridge/intel/i945/Kconfig
-@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- 	default 0xfed19000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
-index 39566a6e5f..f46acf6937 100644
--- a/src/northbridge/intel/ironlake/Kconfig
-+++ b/src/northbridge/intel/ironlake/Kconfig
-@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- 	default 0xfed19000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
-index a05b866dad..50e3a7cdb9 100644
--- a/src/northbridge/intel/pineview/Kconfig
-+++ b/src/northbridge/intel/pineview/Kconfig
-@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE
- config DOMAIN_RESOURCE_32BIT_LIMIT
- 	default 0xfec00000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
-index 9972a43da0..fe4ac5106c 100644
--- a/src/northbridge/intel/sandybridge/Kconfig
-+++ b/src/northbridge/intel/sandybridge/Kconfig
-@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX
- 	default 2 if IGD_DEFAULT_UMA_SIZE_96MB
- 	default 3 if IGD_DEFAULT_UMA_SIZE_128MB
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
-index 646af3510b..069fa0244d 100644
--- a/src/northbridge/intel/x4x/Kconfig
-+++ b/src/northbridge/intel/x4x/Kconfig
-@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- 	default 0xfed19000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-- 
-2.47.3
-
@@ -0,0 +1,435 @@
+From 5ebb21be501cf43d41d1690c29d047bd98fbc942 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Wed, 7 Feb 2024 15:23:46 -0700
+Subject: [PATCH 24/39] mb/dell: Add Latitude E6320 (Sandy Bridge)
+
+Mainboard is PAL70/LA-6611P. I do not physically have this system;
+someone with physical access to one sent me the output of autoport which
+I then modified to produce this port. I was also sent the VBT binary,
+which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
+version A22 of the vendor firmware. This port has not been tested.
+
+The EC is the SMSC MEC5055, which seems to be compatible with the
+existing MEC5035 code. As with the other Dell systems with this EC, this
+board is assumed to be internally flashable using an EC command that
+tells it to pull the FDO pin low on the next boot, which also tells the
+vendor firmware to disable all write protections to the flash [1].
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |  11 +-
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e6320/data.vbt  | Bin 0 -> 6144 bytes
+ .../variants/e6320/early_init.c               |  17 ++
+ .../snb_ivb_latitude/variants/e6320/gpio.c    | 190 ++++++++++++++++++
+ .../variants/e6320/hda_verb.c                 |  32 +++
+ .../variants/e6320/overridetree.cb            |  35 ++++
+ 7 files changed, 287 insertions(+), 1 deletion(-)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index e6a21ffb99..84ffe1d33a 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520
+ 	select BOARD_ROMSIZE_KB_6144
+ 	select SOUTHBRIDGE_INTEL_BD82X6X
+ 
+config BOARD_DELL_LATITUDE_E6320
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_10240
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOUTHBRIDGE_INTEL_BD82X6X
+
+ config BOARD_DELL_LATITUDE_E6420
+ 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select BOARD_ROMSIZE_KB_10240
+@@ -67,6 +73,7 @@ config MAINBOARD_DIR
+ config MAINBOARD_PART_NUMBER
+ 	default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
+ 	default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
+	default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320
+ 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
+@@ -82,6 +89,7 @@ config USBDEBUG_HCD_INDEX
+ config VARIANT_DIR
+ 	default "e5420" if BOARD_DELL_LATITUDE_E5420
+ 	default "e5520" if BOARD_DELL_LATITUDE_E5520
+	default "e6320" if BOARD_DELL_LATITUDE_E6320
+ 	default "e6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "e6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "e5530" if BOARD_DELL_LATITUDE_E5530
+@@ -93,7 +101,8 @@ config VGA_BIOS_ID
+ 		|| BOARD_DELL_LATITUDE_E5420
+ 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
+ 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
+-		|| BOARD_DELL_LATITUDE_E5520
+		|| BOARD_DELL_LATITUDE_E5520 \
+		|| BOARD_DELL_LATITUDE_E6320
+ 	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
+ 		|| BOARD_DELL_LATITUDE_E6530
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index a3fa2b1837..ef6a1329a9 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420
+ config BOARD_DELL_LATITUDE_E5520
+ 	bool "Latitude E5520"
+ 
+config BOARD_DELL_LATITUDE_E6320
+	bool "Latitude E6320"
+
+ config BOARD_DELL_LATITUDE_E6420
+ 	bool "Latitude E6420"
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..471a9e29da639dd496f3ecebd5d0754a9045c00b
+GIT binary patch
+literal 6144
+zcmeHKeP|p-6#wn*-rZ(yH@R-odPzTgZEU>S#_pv}j2iKhT+^%8_DtJw21|4GP8*0x
+zyw;EYW49Xozz<Rt@ek1mic(N32r8oZ0U9lcR8a)~s33wLV8yCftLK~DJJWb)8w-j;
+z=J?H<nfK<+n>TOX?48xuwV5_`Zb)3w)w?dSc1`nTL|NF_SMw&<<)v%g#!cH2otrzi
+zb*<mneJMSLdC1iK_7#v-6w7R}+t1&W8P4wBo*&F!lcNn?)F-EqWZV#oQEb%`x-4^5
+zW@sogOik1`n9Wc#r82|0A!=-0LD!FFGrMwG+CDg($q(js(#Y`8?s79ubEJD@ba#I6
+znjO0++P#czvh8NBR?)iQUA%txNPhHO>Kq!PUMaJadUHE-`5SWCb4_6i;5Aj(6hQGK
+zcq^2uUt5sS5YSMiL+CJcs0#cVOdTN|K@D>?tkF=dqenwjM^Z-^K2z~&z+xRs!o^Jx
+zkUGd?>QtXw8V(I09OiMb0DZy>`=tO^#BCssw{}bkOnj=#Ic!~!6!J*{`jbEv5O4)-
+zg-UBlIa$c9Pg4C;0_-wq3t+dbZfn1wBi@zhNnWx()w{Vb-G8OC_m*478gTrX3U*a1
+zHr@y<Lcbct?Wzy^)OH+FC$S`8V@n`{QN~@2dxJU-1ucBe_>rOO78dFPXES1q3mHj9
+zFXKwa)r^}Mw=nKzJjj?}>}NdBc$G29IK=pr@de`u;}}D$5~yYbw&Hlf=OF0X?I=Y$
+z$D`mgy>}U$hl}G6m&PmXveHnY5DenC!g~=E3i?HIrEpyk>_(-IsVtEqUEoqxrDFdq
+zrYwhOv0o^NgW$OKN}=$7Z-w5*Vuv?T3~uuFGwP92?Qr8n0iQp=u*7rep9Q8dW#?ZI
+zFly1ww^^l*+YC6t16l_{g}tVVpVZ0fDk%5+`|+*688vr-<Lw_SRc^+avHI{BCpdYb
+z70yLEI0-45%t;z||GKzov+|VFW6hab&NAG9FD+h6sBu$cX`r0eJ%T`kvK4+(wT`0=
+z$fxKG+om?Ge1-EhbNc*Xjy1opKZSaiv-EL~GvOa&&bx~z##3W;F2{b=<HQ4!<1CFk
+z17i)$X+`=C=0udOPOx3$IjzopqwQzLr*jT4C)(jmj2>uYP8$M=#caX6OWA1Ez395U
+z%x<yAs)6-Ascr5<x*>CIZibyRlE~I0-ianVaz~q|EMlL7hc1U5w?}Kekws6fyy@`e
+z4NdX%L#2`A#c_N4ftGmuwbDo=incwf=WnBJk6)fYz%6Cmy>HwK$Y|iP`Y7sgjDPhQ
+zR|wv367k}1g)-G@kXq(X;{Bjt998b9{cpD9zGhOQ5%$4OSMtc2(<dx@0O}7_G+$WF
+zLYyaPtFT6d*e&Q$VLd0r%Yr@=*7rjEDyT7JwT8sSA<BiU8$)7mh@K2tFNMULA^I|8
+z{Sp#>gO(fCMTS^w(6xrO#}IcK^sHgMZis^heP>uIf6|z=%Cy#)Vxvjdo7U~7*k{rU
+zruB{~J}~KL(+X9Kxz*-5M>NNGSaIfXi19({d4mrk?K50@R0%Wn*PP9d(MMIzI2~RX
+z)(4h&8(YL@UyKJ*)4o${n5ZGd(hDf+)cv8sSBxWen|f*u<-sgt(u+U-bkd}Tj+5@9
+zJosfSdvPo8zGnluemJg=E7A{=N<Rc#KYYEg?^p`+_?~aU(kEmFus{DshA~iA(onLY
+zvIfpBJt;KWP4n8&`n1##c($WnDo|=?rlHBz&}36&HPWwp8op_i8c-**(TSd{Y{SZ?
+z_=^K$27e+q;^vRNU3~a=cd;V{%O=iuo*&xwXyg19${Ap0yO@a|N-<e^7iIClF{vUn
+z&4$y_V7MA)=E=%7n63u!J9FY$RK8hXHDE%%Lx$ZgX902-<9r|4lkx>QwFch>PUO1w
+z=6JffnB-kQ)VLb>sSZdDrI@U2!?HLA9Mlek!*k>;&jx<)xfnBiY^I6DRt*l*`n8ly
+zu!h)b?sRV1==Nf*Cw9&&i7n^9Nts>wk>adaY&E5OdW*A?iI}v+E6GGlsR<+#%jpl^
+zGz<Q^vpj>qhDjj3zr60Bgh=l{NzJp$x#fCR%*8!ZR?fC&JuvHmSr5#5VAcb(9+>sO
+IzvhA80TAzedH?_b
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
+new file mode 100644
+index 0000000000..b0c4638858
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
+@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+};
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMB_LPC_EN | COMA_LPC_EN);
+	mec5035_early_init();
+}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
+new file mode 100644
+index 0000000000..61f01816c4
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
+@@ -0,0 +1,190 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_NATIVE,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_GPIO,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_LOW,
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
+new file mode 100644
+index 0000000000..2e3f7fa697
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
+	0x10280492,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x10280492),
+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+	0x80862805,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
+new file mode 100644
+index 0000000000..3bfe6b57ed
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
+@@ -0,0 +1,35 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x0492 inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x00000622"
+			register "gpu_pch_backlight" = "0x13121312"
+		end
+
+		chip southbridge/intel/bd82x6x
+			register "usb_port_config" = "{
+				{ 1, 1, 0 },
+				{ 1, 0, 0 },
+				{ 1, 1, 1 },
+				{ 1, 0, 1 },
+				{ 1, 1, 2 },
+				{ 1, 1, 2 },
+				{ 1, 1, 3 },
+				{ 1, 1, 3 },
+				{ 1, 0, 5 },
+				{ 1, 0, 5 },
+				{ 1, 1, 7 },
+				{ 1, 1, 6 },
+				{ 1, 0, 6 },
+				{ 1, 0, 7 },
+			}"
+
+			device ref sata1 on
+				register "sata_port_map" = "0x3b"
+			end
+		end
+	end
+end
+-- 
+2.39.2
+
@@ -1,708 +0,0 @@
-From 70f588b7cc66af2e427d9045d36ac2f5f4835dae Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Mon, 30 Sep 2024 20:44:38 -0400
-Subject: [PATCH 24/41] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
-
-Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/optiplex_780/Kconfig       |  40 ++++
- src/mainboard/dell/optiplex_780/Kconfig.name  |   4 +
- src/mainboard/dell/optiplex_780/Makefile.mk   |  10 +
- src/mainboard/dell/optiplex_780/acpi/ec.asl   |   5 +
- .../dell/optiplex_780/acpi/ich10_pci_irqs.asl |  32 ++++
- .../dell/optiplex_780/acpi/superio.asl        |  18 ++
- .../dell/optiplex_780/board_info.txt          |   6 +
- src/mainboard/dell/optiplex_780/cmos.default  |   8 +
- src/mainboard/dell/optiplex_780/cmos.layout   |  72 ++++++++
- src/mainboard/dell/optiplex_780/cstates.c     |   8 +
- src/mainboard/dell/optiplex_780/devicetree.cb |  63 +++++++
- src/mainboard/dell/optiplex_780/dsdt.asl      |  26 +++
- .../dell/optiplex_780/gma-mainboard.ads       |  16 ++
- .../optiplex_780/variants/780_mt/data.vbt     | Bin 0 -> 1917 bytes
- .../optiplex_780/variants/780_mt/early_init.c |  12 ++
- .../dell/optiplex_780/variants/780_mt/gpio.c  | 174 ++++++++++++++++++
- .../optiplex_780/variants/780_mt/hda_verb.c   |  26 +++
- .../variants/780_mt/overridetree.cb           |  10 +
- 18 files changed, 530 insertions(+)
- create mode 100644 src/mainboard/dell/optiplex_780/Kconfig
- create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name
- create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk
- create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl
- create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
- create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl
- create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt
- create mode 100644 src/mainboard/dell/optiplex_780/cmos.default
- create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout
- create mode 100644 src/mainboard/dell/optiplex_780/cstates.c
- create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb
- create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl
- create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
-
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
-new file mode 100644
-index 0000000000..2d06c75c9a
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/Kconfig
-@@ -0,0 +1,40 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+config BOARD_DELL_OPTIPLEX_780_COMMON
-+	def_bool n
-+	select BOARD_ROMSIZE_KB_8192
-+	select CPU_INTEL_SOCKET_LGA775
-+	select DRIVERS_I2C_CK505
-+	select HAVE_ACPI_RESUME
-+	select HAVE_ACPI_TABLES
-+	select HAVE_CMOS_DEFAULT
-+	select HAVE_OPTION_TABLE
-+	select INTEL_GMA_HAVE_VBT
-+	select MAINBOARD_HAS_LIBGFXINIT
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select NORTHBRIDGE_INTEL_X4X
-+	select PCIEXP_ASPM
-+	select PCIEXP_CLK_PM
-+	select SOUTHBRIDGE_INTEL_I82801JX
-+
-+config BOARD_DELL_OPTIPLEX_780_MT
-+	select BOARD_DELL_OPTIPLEX_780_COMMON
-+
-+if BOARD_DELL_OPTIPLEX_780_COMMON
-+
-+config VGA_BIOS_ID
-+	default "8086,2e22"
-+
-+config MAINBOARD_DIR
-+	default "dell/optiplex_780"
-+
-+config MAINBOARD_PART_NUMBER
-+	default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
-+
-+config OVERRIDE_DEVICETREE
-+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-+
-+config VARIANT_DIR
-+	default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
-+
-+endif # BOARD_DELL_OPTIPLEX_780_COMMON
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
-new file mode 100644
-index 0000000000..db7f2e8fe3
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
-@@ -0,0 +1,4 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+config BOARD_DELL_OPTIPLEX_780_MT
-+	bool "OptiPlex 780 MT"
-diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk
-new file mode 100644
-index 0000000000..d462995d75
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/Makefile.mk
-@@ -0,0 +1,10 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+
-+ramstage-y += cstates.c
-+romstage-y += variants/$(VARIANT_DIR)/gpio.c
-+
-+bootblock-y += variants/$(VARIANT_DIR)/early_init.c
-+romstage-y += variants/$(VARIANT_DIR)/early_init.c
-+
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
-diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl
-new file mode 100644
-index 0000000000..479296cb76
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl
-@@ -0,0 +1,5 @@
-+/* SPDX-License-Identifier: CC-PDDC */
-+
-+/* Please update the license if adding licensable material. */
-+
-+/* dummy */
-diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
-new file mode 100644
-index 0000000000..b7588dcc41
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+/* This is board specific information:
-+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
-+ */
-+
-+If (PICM) {
-+	Return (Package() {
-+		/* PCI slot */
-+		Package() { 0x0001ffff, 0, 0, 0x14},
-+		Package() { 0x0001ffff, 1, 0, 0x15},
-+		Package() { 0x0001ffff, 2, 0, 0x16},
-+		Package() { 0x0001ffff, 3, 0, 0x17},
-+
-+		Package() { 0x0002ffff, 0, 0, 0x15},
-+		Package() { 0x0002ffff, 1, 0, 0x16},
-+		Package() { 0x0002ffff, 2, 0, 0x17},
-+		Package() { 0x0002ffff, 3, 0, 0x14},
-+	})
-+} Else {
-+	Return (Package() {
-+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
-+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
-+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
-+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
-+
-+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
-+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
-+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
-+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
-+	})
-+}
-diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl
-new file mode 100644
-index 0000000000..9f3900b86c
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl
-@@ -0,0 +1,18 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#undef SUPERIO_DEV
-+#undef SUPERIO_PNP_BASE
-+#undef IT8720F_SHOW_SP1
-+#undef IT8720F_SHOW_SP2
-+#undef IT8720F_SHOW_EC
-+#undef IT8720F_SHOW_KBCK
-+#undef IT8720F_SHOW_KBCM
-+#undef IT8720F_SHOW_GPIO
-+#undef IT8720F_SHOW_CIR
-+#define SUPERIO_DEV		SIO0
-+#define SUPERIO_PNP_BASE	0x2e
-+#define IT8720F_SHOW_EC		1
-+#define IT8720F_SHOW_KBCK	1
-+#define IT8720F_SHOW_KBCM	1
-+#define IT8720F_SHOW_GPIO	1
-+#include <superio/ite/it8720f/acpi/superio.asl>
-diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt
-new file mode 100644
-index 0000000000..aaf657b583
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: desktop
-+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default
-new file mode 100644
-index 0000000000..23f0e55f3e
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/cmos.default
-@@ -0,0 +1,8 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+sata_mode=AHCI
-+gfx_uma_size=64M
-diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout
-new file mode 100644
-index 0000000000..9f5012adb4
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/cmos.layout
-@@ -0,0 +1,72 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0	120	r	0	reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384	1	e	4	boot_option
-+388	4	h	0	reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395	4	e	6	debug_level
-+
-+# coreboot config options: southbridge
-+408	1	e	10	sata_mode
-+409	2	e	7	power_on_after_fail
-+411	1	e	1	nmi
-+
-+# coreboot config options: cpu
-+
-+# coreboot config options: northbridge
-+432	4	e	11	gfx_uma_size
-+
-+# coreboot config options: check sums
-+984	16	h	0	check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID	value	text
-+1	0	Disable
-+1	1	Enable
-+2	0	Enable
-+2	1	Disable
-+4	0	Fallback
-+4	1	Normal
-+6	0	Emergency
-+6	1	Alert
-+6	2	Critical
-+6	3	Error
-+6	4	Warning
-+6	5	Notice
-+6	6	Info
-+6	7	Debug
-+6	8	Spew
-+7	0	Disable
-+7	1	Enable
-+7	2	Keep
-+10	0	AHCI
-+10	1	Compatible
-+11	1	4M
-+11	2	8M
-+11	3	16M
-+11	4	32M
-+11	5	48M
-+11	6	64M
-+11	7	128M
-+11	8	256M
-+11	9	96M
-+11	10	160M
-+11	11	224M
-+11	12	352M
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 983 984
-diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c
-new file mode 100644
-index 0000000000..4adf0edc63
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/cstates.c
-@@ -0,0 +1,8 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpigen.h>
-+
-+int get_cst_entries(const acpi_cstate_t **entries)
-+{
-+	return 0;
-+}
-diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb
-new file mode 100644
-index 0000000000..95e3bd517c
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/devicetree.cb
-@@ -0,0 +1,63 @@
-+# SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/x4x
-+	device cpu_cluster 0 on ops x4x_cpu_bus_ops end		# APIC cluster
-+	device domain 0 on
-+		ops x4x_pci_domain_ops		# PCI domain
-+		subsystemid 0x8086 0x0028 inherit
-+		device pci 0.0 on  end		# Host Bridge
-+		device pci 1.0 on  end		# PCIe x16 2.0 slot
-+		device pci 2.0 on  end		# Integrated graphics controller
-+		device pci 2.1 on  end		# Integrated graphics controller 2
-+		device pci 3.0 off end		# ME
-+		device pci 3.1 off end		# ME
-+		chip southbridge/intel/i82801jx	# ICH10
-+			register "gpe0_en" = "0x40"
-+
-+			# Set AHCI mode.
-+			register "sata_port_map"	= "0x3f"
-+			register "sata_clock_request"	= "1"
-+
-+			# Enable PCIe ports 0,1 as slots.
-+			register "pcie_slot_implemented" = "0x3"
-+
-+			device pci 19.0 on  end		# GBE
-+			device pci 1a.0 on  end		# USB
-+			device pci 1a.1 on  end		# USB
-+			device pci 1a.2 on  end		# USB
-+			device pci 1a.7 on  end		# USB
-+			device pci 1b.0 on  end		# Audio
-+			device pci 1c.0 off end		# PCIe 1
-+			device pci 1c.1 off end		# PCIe 2
-+			device pci 1c.2 off end		# PCIe 3
-+			device pci 1c.3 off end		# PCIe 4
-+			device pci 1c.4 off end		# PCIe 5
-+			device pci 1c.5 off end		# PCIe 6
-+			device pci 1d.0 on  end		# USB
-+			device pci 1d.1 on  end		# USB
-+			device pci 1d.2 on  end		# USB
-+			device pci 1d.7 on  end		# USB
-+			device pci 1e.0 on  end		# PCI bridge
-+			device pci 1f.0 on  end		# LPC bridge
-+			device pci 1f.2 on  end		# SATA (IDE: port 0-3, AHCI/RAID: 0-5)
-+			device pci 1f.3 on		# SMBus
-+				chip drivers/i2c/ck505	# IDT CV194
-+					register "mask" = "{ 0xff, 0xff, 0xff, 0xff,
-+							     0xff, 0xff, 0xff, 0xff,
-+							     0xff, 0xff, 0xff, 0xff,
-+							     0xff, 0xff, 0xff, 0xff,
-+							     0xff, 0xff, 0xff }"
-+					register "regs" = "{ 0x15, 0x82, 0xff, 0xff,
-+							     0xff, 0x00, 0x00, 0x95,
-+							     0x00, 0x65, 0x7d, 0x56,
-+							     0x13, 0xc0, 0x00, 0x07,
-+							     0x01, 0x0a, 0x64 }"
-+					device i2c 69 on end
-+				end
-+			end
-+			device pci 1f.4 off end
-+			device pci 1f.5 off end		# SATA 2 (for port 4-5 in IDE mode)
-+			device pci 1f.6 off end		# Thermal Subsystem
-+		end
-+	end
-+end
-diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl
-new file mode 100644
-index 0000000000..9ad70469de
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/dsdt.asl
-@@ -0,0 +1,26 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi.h>
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	ACPI_DSDT_REV_2,
-+	OEM_ID,
-+	ACPI_TABLE_CREATOR,
-+	0x20090811	// OEM revision
-+)
-+{
-+	#include <acpi/dsdt_top.asl>
-+
-+	OSYS = 2002
-+	// global NVS and variables
-+	#include <southbridge/intel/common/acpi/platform.asl>
-+
-+	Device (\_SB.PCI0)
-+	{
-+		#include <northbridge/intel/x4x/acpi/x4x.asl>
-+		#include <southbridge/intel/i82801jx/acpi/ich10.asl>
-+	}
-+
-+	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+}
-diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
-new file mode 100644
-index 0000000000..bc81cf4a40
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
-@@ -0,0 +1,16 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (DP2,
-+      Analog,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf
-GIT binary patch
-literal 1917
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-zTXq_i1Bwd~aNr{c4i)r(goF^M-nek+sY0sMa}Sk>xFFy_FTEfX^Y+7unt+OgkeJbX
-zznS;`v-5V=o<pVaS;}Q53%NpOI!8{cz{K0eVfK65_|*A}SF)Me%$4!N`H5-z90%~a
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-z&J)wlZ=a<yoJkutfwu4%aVXlu?i^8v?R77IyGvKcD|M`CFG$6FUmK8q<|o>3T9EmJ
-z2x?*GPeN%?=Fj3+fv~4%I(nv~XF7VOqi5RsAt%13JtW>q=<<<Gei4)FzWqGEt6P8D
-zA9m}s>;0IkLPSUGL%_1h)2kjaZzuV;`43yCV;I=#Jcyyw@xKE8GGX39@am|0GKhH`
-zawsKv^FvHqm+<DDPT)%}_kZ8^eT88YGmG-#)X3=RRB|L^Uj_{yd%JeO<1HRZVz=Fz
-z+aqUCWdF3_={#Q&&k)eF1i=WV`AbSlzo*bP?x?ir5BVVO`R34f89jWL{Z}or^BwmG
-z-E;A_iWVUUWnWQl3L|~0xA@rHJRA-;7V)Y6B5=@E8R@?(?5{Eh23RefpSOGX_F{8A
-z1PtU+iNng^h#C7J<vufJ9>c8*FfFsu??w)Oed@;Mg~21%rCZ%d{x!>-zmv4AyWL1E
-xfz+CGUnQ7Y^TD}&c_cQRYlBC+`?m?k6Nuw??s04gg4@4`<@FO{XEbO(<xf!`#Pk3F
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
-new file mode 100644
-index 0000000000..e2fa05cd8f
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <northbridge/intel/x4x/x4x.h>
-+
-+void mb_get_spd_map(u8 spd_map[4])
-+{
-+	// BTX form factor
-+	spd_map[0] = 0x53;
-+	spd_map[1] = 0x52;
-+	spd_map[2] = 0x51;
-+	spd_map[3] = 0x50;
-+}
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
-new file mode 100644
-index 0000000000..9993f17c55
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
-@@ -0,0 +1,174 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0  = GPIO_MODE_NATIVE,
-+	.gpio1  = GPIO_MODE_NATIVE,
-+	.gpio2  = GPIO_MODE_GPIO,
-+	.gpio3  = GPIO_MODE_GPIO,
-+	.gpio4  = GPIO_MODE_GPIO,
-+	.gpio5  = GPIO_MODE_GPIO,
-+	.gpio6  = GPIO_MODE_GPIO,
-+	.gpio7  = GPIO_MODE_NATIVE,
-+	.gpio8  = GPIO_MODE_NATIVE,
-+	.gpio9  = GPIO_MODE_GPIO,
-+	.gpio10 = GPIO_MODE_GPIO,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_NATIVE,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_NATIVE,
-+	.gpio18 = GPIO_MODE_GPIO,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_GPIO,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio2  = GPIO_DIR_INPUT,
-+	.gpio3  = GPIO_DIR_INPUT,
-+	.gpio4  = GPIO_DIR_INPUT,
-+	.gpio5  = GPIO_DIR_INPUT,
-+	.gpio6  = GPIO_DIR_INPUT,
-+	.gpio9  = GPIO_DIR_OUTPUT,
-+	.gpio10 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio18 = GPIO_DIR_OUTPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio20 = GPIO_DIR_OUTPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_INPUT,
-+	.gpio31 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio9  = GPIO_LEVEL_HIGH,
-+	.gpio18 = GPIO_LEVEL_HIGH,
-+	.gpio20 = GPIO_LEVEL_HIGH,
-+	.gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio13 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_GPIO,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_NATIVE,
-+	.gpio52 = GPIO_MODE_NATIVE,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio32 = GPIO_DIR_INPUT,
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_INPUT,
-+	.gpio35 = GPIO_DIR_OUTPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio56 = GPIO_DIR_OUTPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio35 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_HIGH,
-+	.gpio56 = GPIO_LEVEL_HIGH,
-+	.gpio60 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_NATIVE,
-+	.gpio69 = GPIO_MODE_NATIVE,
-+	.gpio70 = GPIO_MODE_NATIVE,
-+	.gpio71 = GPIO_MODE_NATIVE,
-+	.gpio72 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio72 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode      = &pch_gpio_set1_mode,
-+		.direction = &pch_gpio_set1_direction,
-+		.level     = &pch_gpio_set1_level,
-+		.blink     = &pch_gpio_set1_blink,
-+		.invert    = &pch_gpio_set1_invert,
-+	},
-+	.set2 = {
-+		.mode      = &pch_gpio_set2_mode,
-+		.direction = &pch_gpio_set2_direction,
-+		.level     = &pch_gpio_set2_level,
-+	},
-+	.set3 = {
-+		.mode      = &pch_gpio_set3_mode,
-+		.direction = &pch_gpio_set3_direction,
-+		.level     = &pch_gpio_set3_level,
-+	},
-+};
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
-new file mode 100644
-index 0000000000..4158bcf899
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
-@@ -0,0 +1,26 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	/* coreboot specific header */
-+	0x11d4194a, /* Analog Devices AD1984A */
-+	0xbfd40000, /*  Subsystem ID */
-+	10,         /* Number of entries */
-+
-+	/* Pin Widget Verb Table */
-+	AZALIA_PIN_CFG(0, 0x11, 0x032140f0),
-+	AZALIA_PIN_CFG(0, 0x12, 0x21214010),
-+	AZALIA_PIN_CFG(0, 0x13, 0x901701f0),
-+	AZALIA_PIN_CFG(0, 0x14, 0x03a190f0),
-+	AZALIA_PIN_CFG(0, 0x15, 0xb7a70121),
-+	AZALIA_PIN_CFG(0, 0x16, 0x9933012e),
-+	AZALIA_PIN_CFG(0, 0x17, 0x97a601f0),
-+	AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0),
-+	AZALIA_PIN_CFG(0, 0x1b, 0x014510f0),
-+	AZALIA_PIN_CFG(0, 0x1c, 0x21a19020),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
-new file mode 100644
-index 0000000000..555b1c1f5c
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
-@@ -0,0 +1,10 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/x4x
-+	device domain 0 on
-+		chip southbridge/intel/i82801jx
-+			device pci 1c.0 on  end		# PCIe 1
-+			device pci 1c.1 on  end		# PCIe 2
-+		end
-+	end
-+end
-- 
-2.47.3
-
@@ -0,0 +1,438 @@
+From fbe48205a55b4a03082affe9f66e81ee509d5f44 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 8 Mar 2024 09:27:36 -0700
+Subject: [PATCH 25/39] mb/dell: Add Latitude E6220 (Sandy Bridge)
+
+Mainboard is codenamed Vida. I do not physically have this system;
+someone with physical access to one sent me the output of autoport which
+I then modified to produce this port. The VBT was obtained using
+intelvbttool while running version A14 (latest available version) of the
+vendor firmware.
+
+Tested and found to boot as part of a libreboot build based on upstream
+coreboot commit b7341da191 with additional patches, though these do not
+appear to affect SNB/IVB. The base E6430 patch was tested against
+coreboot main.
+
+The EC is the SMSC MEC5055, which seems to be compatible with the
+existing MEC5035 code. As with the other Dell systems with this EC, this
+board is assumed to be internally flashable using an EC command that
+tells it to pull the FDO pin low on the next boot, which also tells the
+vendor firmware to disable all write protections to the flash [1].
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |   9 +
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e6220/data.vbt  | Bin 0 -> 3985 bytes
+ .../variants/e6220/early_init.c               |  14 ++
+ .../snb_ivb_latitude/variants/e6220/gpio.c    | 192 ++++++++++++++++++
+ .../variants/e6220/hda_verb.c                 |  32 +++
+ .../variants/e6220/overridetree.cb            |  37 ++++
+ 7 files changed, 287 insertions(+)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index 84ffe1d33a..baa83baa41 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520
+ 	select BOARD_ROMSIZE_KB_6144
+ 	select SOUTHBRIDGE_INTEL_BD82X6X
+ 
+config BOARD_DELL_LATITUDE_E6220
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_10240
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOUTHBRIDGE_INTEL_BD82X6X
+
+ config BOARD_DELL_LATITUDE_E6320
+ 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select BOARD_ROMSIZE_KB_10240
+@@ -73,6 +79,7 @@ config MAINBOARD_DIR
+ config MAINBOARD_PART_NUMBER
+ 	default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
+ 	default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
+	default "Latitude E6220" if BOARD_DELL_LATITUDE_E6220
+ 	default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320
+ 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
+@@ -89,6 +96,7 @@ config USBDEBUG_HCD_INDEX
+ config VARIANT_DIR
+ 	default "e5420" if BOARD_DELL_LATITUDE_E5420
+ 	default "e5520" if BOARD_DELL_LATITUDE_E5520
+	default "e6220" if BOARD_DELL_LATITUDE_E6220
+ 	default "e6320" if BOARD_DELL_LATITUDE_E6320
+ 	default "e6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "e6520" if BOARD_DELL_LATITUDE_E6520
+@@ -102,6 +110,7 @@ config VGA_BIOS_ID
+ 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
+ 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
+ 		|| BOARD_DELL_LATITUDE_E5520 \
+		|| BOARD_DELL_LATITUDE_E6220 \
+ 		|| BOARD_DELL_LATITUDE_E6320
+ 	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
+ 		|| BOARD_DELL_LATITUDE_E6530
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index ef6a1329a9..349ee7f79e 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420
+ config BOARD_DELL_LATITUDE_E5520
+ 	bool "Latitude E5520"
+ 
+config BOARD_DELL_LATITUDE_E6220
+	bool "Latitude E6220"
+
+ config BOARD_DELL_LATITUDE_E6320
+ 	bool "Latitude E6320"
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..548075a74500b5d159108089ee29cff802d07db7
+GIT binary patch
+literal 3985
+zcmdT{eP|p-6#wn*-rZ(yH@R-odPzTgZQ6LXjonL|7&YQ0xu#d`$C=h}21|4GP8*0x
+zyjE@hv0Dv(P?c0g{G(_DMJZ@22r8oZ0U9lcR8a)~s33wOSg|T<^?b8?XBzL?#)6`A
+z{N~Nfd-LYan>TOv7WZ{+rcIq264!S1u1&02-MpSC3mf}u-r~BvbgkXEX=|c$bLZBs
+zbsM{{q9-s1nVR3f2C|A`nJsqvC7UwC+1=angV`H%w4sao<P?&OTVpYbtz1OwGuLN^
+zhBCv{M16zV3^h|KGn^Zu#@6L@%V;*UGnb`pgTtBpU~UJE3=i!tH{%>fx<^KL=Lc`x
+zzLTQeOW7vdZsuwwtsUOU>vxajM=zqzp&{y(GCQa@w<DLoHJ81}6s7=PS9MJR6hDG@
+zLaF+#1qlrS4OKdX4nv2kz^}p75z-OVFk8cF4b?h&G(>eIb%fzF6`uwy)UhaB+ynus
+zBRr-~^|__t=m5fD9tR81r@XLV3UEc-2I6>o`;@@MXS$rj)&)r+pA?|K2vh+9SHM=N
+zw3d{Uh1~iK)juV`E`v4?cFU@^_DehBU5TFLmFrTyoBPuJ*ExIdxO1!lC!eceSG8i}
+z&A<Zmt5Mvo`mkSZ$5C|>ivl*T2}Cf;*vEJvsN-nR!WWDm8M<y^zAkV9BgVLlk!18T
+zu4CN5*u}VmaUbIm#suRa;|0cRj7i2(#%GK#8OIsFFtjRxYDQoSP8NI)g09_;Qlzsy
+z3O>^Zmcltu96wMRudvHXLxn;xh~EqEM^Gr}m&=vHbwRKjl{%)fM2d8tOI4MM{l!dK
+z4$)%2P!LDJaqX2t;s4$Wy@Q1gZ=x97<n3qFBc<Bm#;F26e|~<6=hD9lOk>K<zaU`L
+zqML8CN*#9@aDs=m4ulGOO%*?>lhsvF9`g6&TYocZ_JQN=A1hUE#+kAD@E9jJd7%}~
+zMLIYMDVoel8h1}$+_YJF%DJ&-O)X~`ZoroouO-yDsj)OrPU{{+ph4LJKdD;Bi3a3T
+zbe?Tf8&<r^`I<R>elW+H+t;5$y~|nhq{o@?k1^-Hg%jhcu{xJyzvgk`0m*Te#GQe$
+z2IjOP{U&oF$`&WsuJN2!=fTnT^W)PwhnW-Ya3)3%H!`OUfy6?#V9r%+wCY}TU0!Cl
+z*kjeex}MZl_aWVoxhXfp&Ur~>>k;onlO4II%~KY!FT|r)!;agdwcf~rXIAVwc6CEj
+zJpE{CBzZ;L-gdYp9)G<w5{aU1kLvl`XxrnL=MQj88F%j+w*oR6c&t8(di=t_dW<Us
+z?>C8f@wZ%=YBfkLb0_gZP%us?_tgG3TXJ7BDbWb~V23Mt{QT(?mOc#ihbo#YtY#rD
+z7PLiJBSP#J^tiB|7vdE`p9|}IA$}9o7_wSJ;))RELe^~|u{T6dhpd-F;;j&U6|#N}
+z3BN(h4C``3tTE^&!`fqrdks2dSZ^5Oh(X^Omdc+rCapBB)uz~J(k-TSw<-3U^rC6K
+zYl;s|`q{KX)nazFdEs%*@f}l~SsY?~kb2(WgGl=fm!43<O#L+%@MH9Gl`~Gq=7;rx
+zMc&31@YxsRfz-6`>>4I&2(k1$iaK?FYVZ}~h~1{1T|;>=%b4`yk3XF>siEVHyC@HS
+z8OvVW%DeB`K&~H7>f?&^gQU_A0oM<l8+N5oZ4)iV>;p0b*k61j!x*S5X(-unS`9rZ
+zG}=vb+R*x})DSq-Q7;uJwKLPuG`Ej6G}#nch4dSqhHo0B2Gq%HbgCyS+pwZ3{?fph
+z!Jo*Dxcw7v7a#rIU2IRmVn4KE$x~88+a7J4zd|_!%xo9z$+P;Q6qA*AQ5FvzlPW^f
+zY&aJUhO1#_o~&$x>1qJKGpC+K<(u_&1197<WZ2zu79e*q&i9c$DPNGYYw%s_L~d?x
+zj;EW8N#6BCjjMs5>VVWxipk10ERAEpLG3^|JWI~<Y~c5vi!sB;W|~-R<=`-_TSLhN
+zYlyAlPUkfn-CnHq)Xv2vv1R->DYG*_Qk)fwt)g^KZ*f*K5tEj9C7Ea`HGyPe8U4wd
+nX2Iz@%Q6UTm;}-X%j^D0i1fiT)I6)4TdrsMY}`L(<y7krryzQ}
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c
+new file mode 100644
+index 0000000000..ff83db095b
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMB_LPC_EN | COMA_LPC_EN);
+	mec5035_early_init();
+}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
+new file mode 100644
+index 0000000000..2306e4cf0a
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
+@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_GPIO,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_INPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+	.gpio30 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio30 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio1 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_OUTPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_LOW,
+	.gpio49 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
+new file mode 100644
+index 0000000000..0c69f0bd0e
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
+	0x102804a9,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x102804a9),
+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+	0x80862805,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
+new file mode 100644
+index 0000000000..9faf27e27b
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
+@@ -0,0 +1,37 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x04a9 inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x0000046a"
+			register "gpu_pch_backlight" = "0x13121312"
+		end
+
+		chip southbridge/intel/bd82x6x
+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
+			register "usb_port_config" = "{
+				{ 1, 1, 0 },
+				{ 1, 0, 0 },
+				{ 1, 1, 1 },
+				{ 1, 0, 1 },
+				{ 1, 1, 2 },
+				{ 1, 1, 2 },
+				{ 1, 1, 3 },
+				{ 1, 1, 3 },
+				{ 1, 0, 5 },
+				{ 1, 0, 5 },
+				{ 1, 1, 7 },
+				{ 1, 1, 6 },
+				{ 1, 0, 6 },
+				{ 1, 0, 7 },
+			}"
+
+			device ref pcie_rp4 off end
+			device ref sata1 on
+				register "sata_port_map" = "0x3b"
+			end
+		end
+	end
+end
+-- 
+2.39.2
+
@@ -1,326 +0,0 @@
-From 463148c9773f3dd44f60c2cf2ac17900c3e68619 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Wed, 30 Oct 2024 20:55:25 -0600
-Subject: [PATCH 25/41] mb/dell/optiplex_780: Add USFF variant
-
-Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/optiplex_780/Kconfig       |   5 +
- src/mainboard/dell/optiplex_780/Kconfig.name  |   3 +
- .../optiplex_780/variants/780_usff/data.vbt   | Bin 0 -> 1917 bytes
- .../variants/780_usff/early_init.c            |   9 +
- .../optiplex_780/variants/780_usff/gpio.c     | 166 ++++++++++++++++++
- .../optiplex_780/variants/780_usff/hda_verb.c |  26 +++
- .../variants/780_usff/overridetree.cb         |  10 ++
- 7 files changed, 219 insertions(+)
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
-
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
-index 2d06c75c9a..fc649e35d5 100644
--- a/src/mainboard/dell/optiplex_780/Kconfig
-+++ b/src/mainboard/dell/optiplex_780/Kconfig
-@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON
- config BOARD_DELL_OPTIPLEX_780_MT
- 	select BOARD_DELL_OPTIPLEX_780_COMMON
- 
-+config BOARD_DELL_OPTIPLEX_780_USFF
-+	select BOARD_DELL_OPTIPLEX_780_COMMON
-+
- if BOARD_DELL_OPTIPLEX_780_COMMON
- 
- config VGA_BIOS_ID
-@@ -30,11 +33,13 @@ config MAINBOARD_DIR
- 
- config MAINBOARD_PART_NUMBER
- 	default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
-+	default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF
- 
- config OVERRIDE_DEVICETREE
- 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
- 
- config VARIANT_DIR
- 	default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
-+	default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF
- 
- endif # BOARD_DELL_OPTIPLEX_780_COMMON
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
-index db7f2e8fe3..bc84c82a79 100644
--- a/src/mainboard/dell/optiplex_780/Kconfig.name
-+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
-@@ -2,3 +2,6 @@
- 
- config BOARD_DELL_OPTIPLEX_780_MT
- 	bool "OptiPlex 780 MT"
-+
-+config BOARD_DELL_OPTIPLEX_780_USFF
-+	bool "OptiPlex 780 USFF"
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7
-GIT binary patch
-literal 1917
-zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@i<uQKf!)+gO;|
-zveT#>P+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G
-z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX
-zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv
-zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB
-zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU<Iv53Rb6YTgMPOY8;~P1Yglh^6Fgt1^
-zCTz|SVPcSpZ44F@&oNPUMO@&BE3y(57YP_Y!4SZhE?GXYa7k+b0(X|s7u3GDRf^1#
-zOd2ZCCPO|I&sHEt;p8UshhHtYQ>7!7x2m<d`Gu2<r+Qc4|6pwd8&zFboH_W7XE7uU
-zWW-@Cim&mdY2!O{JANR)OTJG2z>LBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T
-z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`<pE+J?KFZ=&_JVP1YL=#z<-Q*24K4
-zn+$YxrHNJJc`k?_8N=Kres26_#E8GLn2{jfW5P%ge`kL(Btkt=>xo)V)Ow=U6P12c
-z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8
-zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE
-zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb
-zV99s{>`r76L#Hr6XW6r|<iq#4Jr?XsxKyeJKEj7;e4SZ^1B12u&iV_9M0*Kem@fmn
-z1C>>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq<Gj{q2D(
-z>&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a=
-T#w3FFBiyj<XAh$hb(enud`r7S
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
-new file mode 100644
-index 0000000000..2a55fc3a6e
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <northbridge/intel/x4x/x4x.h>
-+
-+void mb_get_spd_map(u8 spd_map[4])
-+{
-+	spd_map[0] = 0x50;
-+	spd_map[2] = 0x52;
-+}
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
-new file mode 100644
-index 0000000000..389f4077d7
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
-@@ -0,0 +1,166 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0  = GPIO_MODE_NATIVE,
-+	.gpio1  = GPIO_MODE_NATIVE,
-+	.gpio2  = GPIO_MODE_GPIO,
-+	.gpio3  = GPIO_MODE_GPIO,
-+	.gpio4  = GPIO_MODE_GPIO,
-+	.gpio5  = GPIO_MODE_GPIO,
-+	.gpio6  = GPIO_MODE_GPIO,
-+	.gpio7  = GPIO_MODE_NATIVE,
-+	.gpio8  = GPIO_MODE_NATIVE,
-+	.gpio9  = GPIO_MODE_GPIO,
-+	.gpio10 = GPIO_MODE_GPIO,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_NATIVE,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_NATIVE,
-+	.gpio18 = GPIO_MODE_GPIO,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_GPIO,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio2  = GPIO_DIR_INPUT,
-+	.gpio3  = GPIO_DIR_INPUT,
-+	.gpio4  = GPIO_DIR_INPUT,
-+	.gpio5  = GPIO_DIR_INPUT,
-+	.gpio6  = GPIO_DIR_INPUT,
-+	.gpio9  = GPIO_DIR_OUTPUT,
-+	.gpio10 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio18 = GPIO_DIR_OUTPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio20 = GPIO_DIR_OUTPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_INPUT,
-+	.gpio31 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio9  = GPIO_LEVEL_HIGH,
-+	.gpio18 = GPIO_LEVEL_HIGH,
-+	.gpio20 = GPIO_LEVEL_HIGH,
-+	.gpio28 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio13 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_GPIO,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_NATIVE,
-+	.gpio52 = GPIO_MODE_NATIVE,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio32 = GPIO_DIR_INPUT,
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_INPUT,
-+	.gpio35 = GPIO_DIR_OUTPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio56 = GPIO_DIR_OUTPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio35 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_HIGH,
-+	.gpio56 = GPIO_LEVEL_HIGH,
-+	.gpio60 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio72 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio72 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode      = &pch_gpio_set1_mode,
-+		.direction = &pch_gpio_set1_direction,
-+		.level     = &pch_gpio_set1_level,
-+		.blink     = &pch_gpio_set1_blink,
-+		.invert    = &pch_gpio_set1_invert,
-+	},
-+	.set2 = {
-+		.mode      = &pch_gpio_set2_mode,
-+		.direction = &pch_gpio_set2_direction,
-+		.level     = &pch_gpio_set2_level,
-+	},
-+	.set3 = {
-+		.mode      = &pch_gpio_set3_mode,
-+		.direction = &pch_gpio_set3_direction,
-+		.level     = &pch_gpio_set3_level,
-+	},
-+};
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
-new file mode 100644
-index 0000000000..c94e06b156
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
-@@ -0,0 +1,26 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	/* coreboot specific header */
-+	0x11d4194a, /* Analog Devices AD1984A */
-+	0x10280420, /*  Subsystem ID */
-+	10,         /* Number of entries */
-+
-+	/* Pin Widget Verb Table */
-+	AZALIA_PIN_CFG(0, 0x11, 0x02214040),
-+	AZALIA_PIN_CFG(0, 0x12, 0x01014010),
-+	AZALIA_PIN_CFG(0, 0x13, 0x991301f0),
-+	AZALIA_PIN_CFG(0, 0x14, 0x02a19020),
-+	AZALIA_PIN_CFG(0, 0x15, 0x01813030),
-+	AZALIA_PIN_CFG(0, 0x16, 0x413301f0),
-+	AZALIA_PIN_CFG(0, 0x17, 0x41a601f0),
-+	AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0),
-+	AZALIA_PIN_CFG(0, 0x1b, 0x414501f0),
-+	AZALIA_PIN_CFG(0, 0x1c, 0x413301f0),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
-new file mode 100644
-index 0000000000..555b1c1f5c
--- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
-@@ -0,0 +1,10 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/x4x
-+	device domain 0 on
-+		chip southbridge/intel/i82801jx
-+			device pci 1c.0 on  end		# PCIe 1
-+			device pci 1c.1 on  end		# PCIe 2
-+		end
-+	end
-+end
-- 
-2.47.3
-
@@ -0,0 +1,436 @@
+From 87e6f8bf38c5dcb4075d0df32507bf9151338b92 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 8 Mar 2024 09:33:03 -0700
+Subject: [PATCH 26/39] mb/dell: Add Latitude E6330 (Ivy Bridge)
+
+Mainboard is QAL70/LA-7741P. I do not physically have this system;
+someone with physical access to one sent me the output of autoport which
+I then modified to produce this port. I was also sent the VBT binary,
+which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
+version A21 of the vendor firmware. This port has not been tested.
+
+The EC is the SMSC MEC5055, which seems to be compatible with the
+existing MEC5035 code. As with the other Dell systems with this EC, this
+board is assumed to be internally flashable using an EC command that
+tells it to pull the FDO pin low on the next boot, which also tells the
+vendor firmware to disable all write protections to the flash [1].
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I827826e9ff8a9a534c50250458b399104478e06c
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |  11 +-
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e6330/data.vbt  | Bin 0 -> 6144 bytes
+ .../variants/e6330/early_init.c               |  14 ++
+ .../snb_ivb_latitude/variants/e6330/gpio.c    | 192 ++++++++++++++++++
+ .../variants/e6330/hda_verb.c                 |  32 +++
+ .../variants/e6330/overridetree.cb            |  37 ++++
+ 7 files changed, 288 insertions(+), 1 deletion(-)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index baa83baa41..49bf225fe2 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530
+ 	select BOARD_ROMSIZE_KB_12288
+ 	select SOUTHBRIDGE_INTEL_C216
+ 
+config BOARD_DELL_LATITUDE_E6330
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_12288
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOUTHBRIDGE_INTEL_C216
+
+ config BOARD_DELL_LATITUDE_E6430
+ 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select BOARD_ROMSIZE_KB_12288
+@@ -84,6 +90,7 @@ config MAINBOARD_PART_NUMBER
+ 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
+	default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330
+ 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
+ 
+@@ -101,13 +108,15 @@ config VARIANT_DIR
+ 	default "e6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "e6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "e5530" if BOARD_DELL_LATITUDE_E5530
+	default "e6330" if BOARD_DELL_LATITUDE_E6330
+ 	default "e6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "e6530" if BOARD_DELL_LATITUDE_E6530
+ 
+ config VGA_BIOS_ID
+ 	default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \
+ 		|| BOARD_DELL_LATITUDE_E5420
+-	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
+	default "8086,0166" if BOARD_DELL_LATITUDE_E5530 \
+		|| BOARD_DELL_LATITUDE_E6330
+ 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
+ 		|| BOARD_DELL_LATITUDE_E5520 \
+ 		|| BOARD_DELL_LATITUDE_E6220 \
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index 349ee7f79e..d6fc8eb224 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520
+ config BOARD_DELL_LATITUDE_E5530
+ 	bool "Latitude E5530"
+ 
+config BOARD_DELL_LATITUDE_E6330
+	bool "Latitude E6330"
+
+ config BOARD_DELL_LATITUDE_E6430
+ 	bool "Latitude E6430"
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..18856746656058651c571ecbb3708e0543b19d62
+GIT binary patch
+literal 6144
+zcmeHKU2GiH75-*tc6WAmW_LYygMSkDB*E^Q*zv5f7dLg)@$NQV2a{}!yImnfyvQ4D
+z;n-$v0!RpNi<_o@ktI-@2a590stC0zRi%iRR%stvi&hAs3R<K}X~hFddB_6@s8W`5
+zXJ!q~E{TOme<a`8@BW;7?l<?GIp@yo&H2<M-FZ0GKbBAR-Ekx}HvVOrhK1*2?{QsU
+zQe#K%JeC=q96gpAKa#$keu^D99ee*0FfB=@F_0J<9-Ch-&BZ5r1T6`{$;1%Fm+qfk
+zTr5pfAz@KB*NGlFzEGx2aqh%IxkQOuX*`{wy~+KQo+-}XSE7aaxko77OBtFgoh;4K
+z(#-7f<x+WxmKSK)vQFgtt^L+?s+Z<V57E7|^TqOPX{mn0n<VLl#Yf7s_suL*Jl#VB
+zmSyz~ScwEVTc-3vd2v6D&dt$;&{?91(o(5>vNXNl&<qW@AghW5NPYw#ha~-b0Dc7_
+z6}t(eHgpwn6<HNi1Vcp^p-07-iXve~MTs!0A_ku!`4nKciajxJYXsOYuuT4N%smA!
+zPazgl&bNRSrvAz|_6r3+B;r1=!7D;RUUw8Ke+vNt7E3`(BA-woPvJFBK^3Gzfh4Nk
+zOX!J0PJNB)Mk&Z_i?S2ez+iItz=)m79LydX&rM9`3wPaJ`T92=Uv0;g-!<4*M6z%+
+z*omwb#VI+CU&%iFS{_DGS;sE}7G4juqRMCww!+k6=+abJj4v>Dsr*z_6HAP5GJeST
+znX2JD;{xLa#;c6KGychVn-L6YXkv6Qx)}Y8&ok1DI~ZSM6dCt39%QUAzRh@o@gqjy
+zL0qZ&DhN8ZR3xu$a$Cd{oasU3DNp{CCl6f~PYlq!Hte;Ia0^wn8Vut7>Wl1)s`^E-
+z1DhGx<x<9D%6jd%)5>zr8&7h}dMJ3~YBe;)!vVf-T&?{PoMvvRR{!67;Xhz^g^loX
+zja+*c-KJJoxbsm3pTE4THs`cgD{Pt+ga3en-i$P#9Wsra(oqRMr;H$4{gxr)9eF(x
+zg0v@a7aj}rA^Kf#sNb*>at^>P)5li%ycOq*4e;3~RUj$i1e8=rHi&<Y^Hc>Y_gP4=
+zxz9^%q0dLXqC&Bq<&sDScZwvatjRxB=rcJJiYb?w#4Iy2KTk1F6T>T}E@(DNGa>5R
+z7&Yv)JdHrRI};pfsKLVj=FE=U*=*T4#ncVktknoGelT||SDY`+9WI_IZE<i@7SnC8
+zN6~Gyo=&><wpzE~>`_>@wb<-RI-lu(_~Oy_Zo6={Cdq!uw(fmyz_u^cB&~5IS7g`U
+zdUC}N$J5-C)|`CfUO+?xptr@*hJW$ZhBZk%JaMh_<8!ZGj)z*WU9fcg2`>dT##_?q
+z=Ksx}uxo3jTHTq%E1}97UECE@r}nt3I=3R(HOL7jNg>teSM-g$aU#`3jk}#qh;D?6
+zw=CYuA2#mS+vU%0P&u8RCn4)$8VH-2uy#01%VG0WSX&Fz`LMYj)?N<NyJ1t)wHBQY
+z=;pYt<#l>gH_zzWS)G2Pn=k3wYdU|DnWmxbG$>`5lZJMWL92%O14BD!(C-cNFNXFH
+zgVc!G9?@=&(4mNVcSJiLq3=b^rz6@k5qdFVUW{m$A{2|7d!kxz)VSrcQt@4sDoq^f
+z98hXm=YS~qbf<kwigD|YevaR}^`7Jy^x~4_g75ka=c0r}VJF2aEv{=ilPf-mNQBNI
+zEMK3YKB+`*xOu>iR|LbzHLa*mLXlH${^b4c9%>9%)HO-?LA1gT0mlz!M}8&;(;^x|
+z*H2<VyY>2;juB|7F+k?y(_2~3@STqQ@f^sqD2c8g3x>ciM%siMq~;pKwfE57kw2K@
+z!-ZN0QTVOP@aA5@fEGKjy2+D`t?2KzpPyRQ`JcmHJoc(<#h<UT;@W$t_d{|;S>vyF
+zewtgef*II~y;k>*B!+(8*blXsY-~kcJa9zG2yfcMCt+|-0ex$pY`h1<*#rEv=~*<+
+ztV``Um!q33-Aap9fUshX^N~GS2@X3^U9+MwgYQ74^?~6&yU^#oY#cvC9R_}P2d<wN
+zJvOE)Xr7A2n#3x14}2_g(YN^0+oYDbb#|V{ze3pzGb9FiF#6Ra&L}bT(ZOvswS7RY
+zxLjWFRwWXHR5&={t;%K+Vkd6NX2iF<SF)LXv@y472OmG!_W%Ni*ZDuev-S0%b!dfW
+wz4{IL!+uT9t2XI4@_L@?Ri*bc_<n8A+wHaowmq=zfo%_LdtloGpN<DU00~N<ApigX
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
+new file mode 100644
+index 0000000000..ff83db095b
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
+@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
+			| COMB_LPC_EN | COMA_LPC_EN);
+	mec5035_early_init();
+}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
+new file mode 100644
+index 0000000000..777570765a
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
+@@ -0,0 +1,192 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
+new file mode 100644
+index 0000000000..804733b172
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76df,	/* Codec Vendor / Device ID: IDT */
+	0x10280533,	/* Subsystem ID */
+	11,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x10280533),
+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+	0x80862806,	/* Codec Vendor / Device ID: Intel */
+	0x80860101,	/* Subsystem ID */
+	4,		/* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
+new file mode 100644
+index 0000000000..4125159367
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
+@@ -0,0 +1,37 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x0533 inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x00001312"
+			register "gpu_pch_backlight" = "0x13121312"
+		end
+
+		chip southbridge/intel/bd82x6x
+			register "usb_port_config" = "{
+				{ 1, 2, 0 },
+				{ 1, 0, 0 },
+				{ 1, 0, 1 },
+				{ 1, 1, 1 },
+				{ 1, 1, 2 },
+				{ 1, 1, 2 },
+				{ 1, 2, 3 },
+				{ 1, 2, 3 },
+				{ 1, 2, 4 },
+				{ 1, 1, 4 },
+				{ 1, 1, 5 },
+				{ 1, 1, 5 },
+				{ 1, 2, 6 },
+				{ 1, 0, 6 },
+			}"
+
+			device ref xhci on
+				register "superspeed_capable_ports" = "0x0000000f"
+				register "xhci_overcurrent_mapping" = "0x00000c03"
+				register "xhci_switchable_ports" = "0x0000000f"
+			end
+		end
+	end
+end
+-- 
+2.39.2
+
@@ -1,33 +0,0 @@
-From bf3c3df864cae045c82d1c032ced834a60239401 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 6 Jan 2025 01:53:53 +0000
-Subject: [PATCH 26/41] src/intel/x4x: Disable stack overflow debug
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/northbridge/intel/x4x/Kconfig | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
-index 069fa0244d..8c70344846 100644
--- a/src/northbridge/intel/x4x/Kconfig
-+++ b/src/northbridge/intel/x4x/Kconfig
-@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER
- 	int
- 	default 256
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+	bool
-+	default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+	bool
-+	default n
-+
- # This number must be equal or lower than what's reported in ACPI PCI _CRS
- config DOMAIN_RESOURCE_32BIT_LIMIT
- 	default 0xfec00000
-- 
-2.47.3
-
@@ -1,42 +0,0 @@
-From 0ad074869ec2a25508b1d6fc97c6ce61a9982fbd Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Tue, 22 Apr 2025 10:21:59 +0100
-Subject: [PATCH 27/41] hp/8300cmt: remove xhci_overcurrent_mapping
-
-No longer needed, as per the following commit:
-
-commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1
-Author: Keith Hui <buurin@gmail.com>
-Date:   Tue Dec 31 18:19:31 2024 -0500
-
-    sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping
-
-Removing this from the devicetree also allows the
-board to compile, otherwise an error is thrown:
-
-build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping'
-  147 |         .xhci_overcurrent_mapping = 0x00000c03,
-      |          ^~~~~~~~~~~~~~~~~~~~~~~~
-build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror]
-  147 |         .xhci_overcurrent_mapping = 0x00000c03,
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-index 3d21739b72..3a0b6d5c59 100644
--- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge
- 			register "spi_lvscc" = "0x2005"
- 			register "spi_uvscc" = "0x2005"
- 			register "superspeed_capable_ports" = "0x0000000f"
-			register "xhci_overcurrent_mapping" = "0x00000c03"
- 			register "xhci_switchable_ports" = "0x0000000f"
- 			register "usb_port_config" = "{
- 				{ 1, 0, 0 },
-- 
-2.47.3
-
@@ -0,0 +1,440 @@
+From 611b5b3b4794eeda7ffb0a1876e1033705c50545 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Thu, 26 Oct 2017 21:26:43 +0800
+Subject: [PATCH 27/39] mb/dell: Add Latitude E6230 (Ivy Bridge)
+
+This was adapted from CB:22693 from Iru Cai, which was based on
+autoport. I do not physically have this system. Someone with physical
+access to an E6230 running version A11 of the vendor firmware sent me
+the VBT after running the command `intelvbttool --inlegacy --outvbt
+data.vbt`. This new version of the port has not yet been tested.
+
+The EC is the SMSC MEC5055, which seems to be compatible with the
+existing MEC5035 code. As with the other Dell systems with this EC, this
+board is assumed to be internally flashable using an EC command that
+tells it to pull the FDO pin low on the next boot, which also tells the
+vendor firmware to disable all write protections to the flash [1].
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Original-Change-Id: I8cdc01e902e670310628809416290045c2102340
+Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/Kconfig   |  11 +-
+ .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
+ .../snb_ivb_latitude/variants/e6230/data.vbt  | Bin 0 -> 4280 bytes
+ .../variants/e6230/early_init.c               |  12 ++
+ .../snb_ivb_latitude/variants/e6230/gpio.c    | 193 ++++++++++++++++++
+ .../variants/e6230/hda_verb.c                 |  32 +++
+ .../variants/e6230/overridetree.cb            |  40 ++++
+ 7 files changed, 290 insertions(+), 1 deletion(-)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+index 49bf225fe2..f6e097930b 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
+@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530
+ 	select BOARD_ROMSIZE_KB_12288
+ 	select SOUTHBRIDGE_INTEL_C216
+ 
+config BOARD_DELL_LATITUDE_E6230
+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+	select BOARD_ROMSIZE_KB_12288
+	select MAINBOARD_USES_IFD_GBE_REGION
+	select SOUTHBRIDGE_INTEL_C216
+
+ config BOARD_DELL_LATITUDE_E6330
+ 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
+ 	select BOARD_ROMSIZE_KB_12288
+@@ -90,6 +96,7 @@ config MAINBOARD_PART_NUMBER
+ 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
+	default "Latitude E6230" if BOARD_DELL_LATITUDE_E6230
+ 	default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330
+ 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
+@@ -108,6 +115,7 @@ config VARIANT_DIR
+ 	default "e6420" if BOARD_DELL_LATITUDE_E6420
+ 	default "e6520" if BOARD_DELL_LATITUDE_E6520
+ 	default "e5530" if BOARD_DELL_LATITUDE_E5530
+	default "e6230" if BOARD_DELL_LATITUDE_E6230
+ 	default "e6330" if BOARD_DELL_LATITUDE_E6330
+ 	default "e6430" if BOARD_DELL_LATITUDE_E6430
+ 	default "e6530" if BOARD_DELL_LATITUDE_E6530
+@@ -121,7 +129,8 @@ config VGA_BIOS_ID
+ 		|| BOARD_DELL_LATITUDE_E5520 \
+ 		|| BOARD_DELL_LATITUDE_E6220 \
+ 		|| BOARD_DELL_LATITUDE_E6320
+-	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
+	default "8086,0166" if BOARD_DELL_LATITUDE_E6230 \
+		|| BOARD_DELL_LATITUDE_E6430 \
+ 		|| BOARD_DELL_LATITUDE_E6530
+ 
+ endif
+diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+index d6fc8eb224..cb7bbd5cdb 100644
+--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
+@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520
+ config BOARD_DELL_LATITUDE_E5530
+ 	bool "Latitude E5530"
+ 
+config BOARD_DELL_LATITUDE_E6230
+	bool "Latitude E6230"
+
+ config BOARD_DELL_LATITUDE_E6330
+ 	bool "Latitude E6330"
+ 
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..45ce8f435eea647a0bddaab3fd1e9282c87afc66
+GIT binary patch
+literal 4280
+zcmdT{Yiu0V75-*tAG5PFyX&zDekA7P<*tbx&o1`j23L%CmvkLWvN7(mLa6alZ?J`9
+zo3#m4YVlG`2;w12Ajppt<qra(R;8*G@uw*8gIcsg2vxi!q_pBkmGUD$s9IGi+jD1T
+zO`Kg43n@JA>~|mMp8L%`XU@4ZyCa_(r`z|Z`bP4p-rEkOMn-R;Ntk#o`b)0sOKRl6
+z?T0eM<HLtiqX*Kr(o5Kc<Iyk90h5ws=!y8i;K=M^X(l$-Eoeyyj>ZS*@LZWP#hD{>
+z<r2jcJ;b8e!oAb;^QB2D#7*krI^IpA=?ra8?xvqj6=&}$QL2a1J(QuD($UfkElf=x
+zUM!UtXmO4PP4h^;&)jWJvd(Pj0lIs7wpgAnE!1!MB1w8~{^#ZCd!`mCmhPs6X_~zW
+zGae^<%aoog&+n$;nHd@rItw&bS}2u|mL_-Ws;&ZOWW_51k`IALAW8pAz~@C!!B)bs
+z1x-OrK~}*8L07Po(5+xZL6I<}phTEf5QRsVJYHa{f^AWEV+2@lvrPVS%snsOn?N)w
+zpKbvwOnk&Q_6Y?aB;r1=!TYwts;yA@BnbFfECo!7JVJq7g^yhYMUV;wlBjksp(hI2
+z^<}E7r698{-pw!*{mH>SLslxYH@j~%H#VLx+<8~!;a@$n+>Q%xHrQ8KGI21_iL4sI
+zF*$}m$R7Mr9z@Z*ir@Q9eClsSmC+t(g`q~VQ&nIxZenav_^Buc78s8*o@e|<QE{4a
+zhVeGz1IFJN|784&5eTYiVstQeGWr-lWTY9lG45a#8TT^oXDl%uXFS9BHN$^DE>t}g
+z1Z-O>lG`>pEuvmL-HpmgSANo!2hWQq2B>Zua$8%tfvQ>!1n@=m9ri_4`H|Rx#SH9n
+zDdRF_-FDP&WjW`L$GK%a6x?yO8l2!^g0HJrtA7TknNzCO?|U!wCv2^-5pJ%LW6!+P
+z)anX%E>`gP%3Er4c6+J9x=Atk1{Abrr1|WSY3P`SO5j!R5F*vbbQ%AaSHnR_+x&Op
+zA%8C-Pk=-Hs+FL90B)E*y3FUTIA1J)&pxRF$tzAkNr7a6_-8v$@j~G~3keqYd5I<T
+z`Kb3Q@LKkANhE_aMG_R&<ewt+nVbp5l*3G7mYJEKr<kXS;TA&^G;5`q5b>;y8g^P<
+zfWO_D2@EyVVBxnpv*}hgTeeRzWz9BoISh>M%^k`WXG=5ti$_Wu99)~lWE-qubeXNk
+zla9Tu=Jhyn5T<3$H#?Hfm-`+(d$7IBDx9cEvNv1i-LEDr>r7438bfkPcKod+mwd22
+z%{^(w&NuG)MKl0fTMTXZFJEm~k;KCj*D60g=j!2jsP)<fOUGaEZa`&xE*)?FZuW#-
+z8!Of7<|N(^R#xcjmZ&nZ%~{pC5y_T*PB2LdDjuI#Te}-4Qccvj+u4N3TBx|oVy*mP
+z<9xfFziy4n?sPv3Sqo7jWMo3>{tzvOjAJ2nB}At~#%f4?FGT+d8LFnXXtYN&Mm06B
+z(JwUPX-z$$(d(M=uBLvh@h6#K=;~&jQo1p&t3TCgSvQ{3)l)jXr5hjW>fd!z!bW>o
+z-4UjJVdJi_dN@o^hK(1(>dRqzCv2PztLMTLjTqY^YEMMJ{=B#1IV)9~IMg|yl(NPF
+zQSfMX`?(b5)))B!zjy0B$ua20CCLTPl^IS&2=T&Zid9-1*K{VAJP?rxjYC+zGDCe*
+ziQI7VfF17@3`3W-qCN>lPC5CL_c?p0F<ekqB;g0q3P1R5KNubPsT>TGXaGB3i~{ZE
+zr=QtIprytDnU7C*Wj%x0k)O{Y%nUnl%}K%F|J_iVaD&ubW4Qbtx;pZEb9}f^Yd;Ea
+zI1Ha{7Yt~z{LAY++1QG{F6*_4WsUziY{x?%I9B}i5-Tphhk8FGm%J<d_0CUoV^%N&
+zTe02j+LXk=ZyWoe7L$#wsEY@VC>f!3d-ysG_9>uk%#)4xpxb+ZkJdel#+h}l9j9`1
+zt*M!5u?i4YtZ+WECo6$LJF06|G-mMZskGiV*lQJf-ItB+hltI<?{5E<^P=0rL<P+g
+z(P)!c<?MlvMK0O~UwZ4*;x|ms(&&#Vn_-4{KM#g~a=;$N2QD7mSX0{t<cf>sId@e&
+z-cN<SWA3VKCN6g3lx#+PySpWu*+pw}>vr(fgI)K*zkikg6TDJi?^}ghc*U*%A%EGg
+Y$$8Z}9a~<{Q@y10T!W`-d%n2+Kj)*Kg#Z8m
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
+new file mode 100644
+index 0000000000..24c1b32467
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
+@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <bootblock_common.h>
+#include <device/pci_ops.h>
+#include <ec/dell/mec5035/mec5035.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+void bootblock_mainboard_early_init(void)
+{
+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
+	mec5035_early_init();
+}
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
+new file mode 100644
+index 0000000000..c07e4b1c56
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
+@@ -0,0 +1,193 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_GPIO,
+	.gpio3 = GPIO_MODE_GPIO,
+	.gpio4 = GPIO_MODE_GPIO,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_NATIVE,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_GPIO,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_GPIO,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_GPIO,
+	.gpio22 = GPIO_MODE_GPIO,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio2 = GPIO_DIR_INPUT,
+	.gpio3 = GPIO_DIR_INPUT,
+	.gpio4 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio14 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_INPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_OUTPUT,
+	.gpio19 = GPIO_DIR_INPUT,
+	.gpio21 = GPIO_DIR_INPUT,
+	.gpio22 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_INPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio17 = GPIO_LEVEL_HIGH,
+	.gpio28 = GPIO_LEVEL_LOW,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
+	.gpio30 = GPIO_RESET_RSMRST,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio0 = GPIO_INVERT,
+	.gpio8 = GPIO_INVERT,
+	.gpio13 = GPIO_INVERT,
+	.gpio14 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_NATIVE,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_GPIO,
+	.gpio36 = GPIO_MODE_GPIO,
+	.gpio37 = GPIO_MODE_GPIO,
+	.gpio38 = GPIO_MODE_GPIO,
+	.gpio39 = GPIO_MODE_GPIO,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_GPIO,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_GPIO,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_GPIO,
+	.gpio52 = GPIO_MODE_GPIO,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_GPIO,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_GPIO,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio33 = GPIO_DIR_INPUT,
+	.gpio34 = GPIO_DIR_OUTPUT,
+	.gpio35 = GPIO_DIR_INPUT,
+	.gpio36 = GPIO_DIR_INPUT,
+	.gpio37 = GPIO_DIR_INPUT,
+	.gpio38 = GPIO_DIR_INPUT,
+	.gpio39 = GPIO_DIR_INPUT,
+	.gpio45 = GPIO_DIR_OUTPUT,
+	.gpio48 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio51 = GPIO_DIR_INPUT,
+	.gpio52 = GPIO_DIR_INPUT,
+	.gpio54 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+	.gpio60 = GPIO_DIR_OUTPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio34 = GPIO_LEVEL_HIGH,
+	.gpio45 = GPIO_LEVEL_LOW,
+	.gpio60 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_GPIO,
+	.gpio71 = GPIO_MODE_GPIO,
+	.gpio72 = GPIO_MODE_NATIVE,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio70 = GPIO_DIR_INPUT,
+	.gpio71 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+		.mode		= &pch_gpio_set1_mode,
+		.direction	= &pch_gpio_set1_direction,
+		.level		= &pch_gpio_set1_level,
+		.blink		= &pch_gpio_set1_blink,
+		.invert		= &pch_gpio_set1_invert,
+		.reset		= &pch_gpio_set1_reset,
+	},
+	.set2 = {
+		.mode		= &pch_gpio_set2_mode,
+		.direction	= &pch_gpio_set2_direction,
+		.level		= &pch_gpio_set2_level,
+		.reset		= &pch_gpio_set2_reset,
+	},
+	.set3 = {
+		.mode		= &pch_gpio_set3_mode,
+		.direction	= &pch_gpio_set3_direction,
+		.level		= &pch_gpio_set3_level,
+		.reset		= &pch_gpio_set3_reset,
+	},
+};
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
+new file mode 100644
+index 0000000000..f6876f9e09
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
+@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x111d76df, /* Codec Vendor / Device ID: IDT */
+	0x10280532, /* Subsystem ID */
+	11, /* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x10280532),
+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
+
+	0x80862806, /* Codec Vendor / Device ID: Intel */
+	0x80860101, /* Subsystem ID */
+	4, /* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
+new file mode 100644
+index 0000000000..3a0fa720da
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
+@@ -0,0 +1,40 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	device domain 0 on
+		subsystemid 0x1028 0x0532 inherit
+
+		device ref igd on
+			register "gpu_cpu_backlight" = "0x000009e9"
+			register "gpu_pch_backlight" = "0x13121312"
+		end
+
+		chip southbridge/intel/bd82x6x
+			register "usb_port_config" = "{
+				{ 1, 1, 0 },
+				{ 1, 1, 0 },
+				{ 1, 0, 1 },
+				{ 1, 2, 1 },
+				{ 1, 0, 2 },
+				{ 1, 0, 2 },
+				{ 1, 0, 3 },
+				{ 1, 1, 3 },
+				{ 1, 2, 4 },
+				{ 1, 1, 4 },
+				{ 1, 1, 5 },
+				{ 1, 1, 5 },
+				{ 1, 2, 6 },
+				{ 1, 0, 6 },
+			}"
+
+			device ref xhci on
+				register "superspeed_capable_ports" = "0x0000000f"
+				register "xhci_overcurrent_mapping" = "0x00000c03"
+				register "xhci_switchable_ports" = "0x0000000f"
+			end
+			device ref sata1 on
+				register "sata_port_map" = "0x31"
+			end
+		end
+	end
+end
+-- 
+2.39.2
+
@@ -1,7 +1,7 @@
-From 495eab54f7c2224a0ad3da3dc79905182eca6eee Mon Sep 17 00:00:00 2001
+From ea6e8749112dee4f458e9cf591e13e9097d56bab Mon Sep 17 00:00:00 2001
 From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
 Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH 08/41] HACK: Disable coreboot related BL31 features
+Subject: [PATCH 28/39] HACK: Disable coreboot related BL31 features

 I don't know why, but removing this BL31 make argument lets gru-kevin
 power off properly when shut down from Linux. Needs investigation.
@@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation.
 1 file changed, 3 deletions(-)

 diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
-index 279d31fb47..3d436179fe 100644
+index cb43897efd..a9e5ff399a 100644
 --- a/src/arch/arm64/Makefile.mk
 +++ b/src/arch/arm64/Makefile.mk
-@@ -162,9 +162,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
+@@ -173,9 +173,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
 # Always enable crash reporting, even on a release build
 BL31_MAKEARGS += CRASH_REPORTING=1
 
@@ -24,5 +24,5 @@ index 279d31fb47..3d436179fe 100644
 BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
 
 -- 
-2.47.3
+2.39.2

@@ -1,47 +0,0 @@
-From 4739f197ee3d4c95809ba48671bc5c409766b9c7 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Wed, 11 Dec 2024 01:06:01 +0000
-Subject: [PATCH 28/41] dell/3050micro: disable nvme hotplug
-
-in my testing, when running my 3050micro for a few days,
-the nvme would sometimes randomly rename.
-
-e.g. nvme0n1 renamed to nvme0n2
-
-this might cause crashes in linux, if booting only from the
-nvme. in my case, i was booting from mdraid (sata+nvme) and
-every few days, the nvme would rename at least once, causing
-my RAID to become unsynced. since i'm using RAID1, this was
-OK and I could simply re-sync the array, but this is quite
-precarious indeed. if you're using raid0, that will potentially
-corrupt your RAID array indefinitely.
-
-this same issue manifested on the T480/T480 thinkpads, and
-S3 resume would break because of that, when booting from nvme,
-because the nvme would be "unplugged" and appear to linux as a
-new device (the one that you booted from).
-
-the fix there was to disable hotplugging on that pci-e slot
-for the nvme, so apply the same fix here for 3050 micro
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- .../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
-index c5f1749b2c..ff48a8121a 100644
--- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
-+++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
-@@ -46,7 +46,7 @@ chip soc/intel/skylake
- 			register "PcieRpAdvancedErrorReporting[20]"     = "1"
- 			register "PcieRpLtrEnable[20]"                  = "true"
- 			register "PcieRpClkSrcNumber[20]"               = "3"
-			register "PcieRpHotPlug[20]"                    = "1"
-+			register "PcieRpHotPlug[20]"                    = "0"
- 		end
- 
- 	end
-- 
-2.47.3
-
@@ -1,61 +0,0 @@
-From a6fdf61bb4779775fa330fc3f9b79be651c6854a Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 6 Jan 2025 01:36:23 +0000
-Subject: [PATCH 29/41] src/intel/skylake: Disable stack overflow debug options
-
-The option was appearing in T480/3050micro configs of lbmk,
-after updating on the coreboot/next uprev for 20241206 rev8:
-
-CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y
-
-I did some digging. See coreboot commit:
-
-commit 51cc2bacb6b07279b97e9934d079060475481fb6
-Author: Subrata Banik <subratabanik@google.com>
-Date:   Fri Dec 13 13:07:28 2024 +0530
-
-    soc/intel/pantherlake: Disable stack overflow debug options
-
-Well now:
-
-I'm disabling this behaviour on Skylake, for the same
-behaviour, because I want as few behaviour changes in general,
-as possible, for the rev8 release.
-
-According to Subrata's patch, which was for Pantherlake,
-without this change, stack corruption can occur on verstage
-and romstage early on. Please look at that coreboot patch,
-referenced above, for clarity.
-
-I see no harm in disabling this option for Skylake, since
-the behaviour that it otherwise enables was not present
-before.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/soc/intel/skylake/Kconfig | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index 7c530f2c75..70c2a7643c 100644
--- a/src/soc/intel/skylake/Kconfig
-+++ b/src/soc/intel/skylake/Kconfig
-@@ -131,6 +131,15 @@ config DCACHE_RAM_SIZE
- 	  The size of the cache-as-ram region required during bootblock
- 	  and/or romstage.
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+	bool
-+	default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+	bool
-+	default n
-+
- config DCACHE_BSP_STACK_SIZE
- 	hex
- 	default 0x20400 if FSP_USES_CB_STACK
-- 
-2.47.3
-
@@ -0,0 +1,29 @@
+From 5c385ef4b4424ed8c37e549a00866edda960563f Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Wed, 31 Jul 2024 00:03:02 +0100
+Subject: [PATCH 29/39] use own mirror for acpica files
+
+intel likes to break links for no reason,
+so we host our own backups of acpica.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index ad756652ed..5faff337b4 100755
+--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
+@@ -74,7 +74,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+ GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+ BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+-IASL_BASE_URL="https://downloadmirror.intel.com/783534"
+IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+ CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+
@@ -0,0 +1,142 @@
+From c1065a638f2af40d8ef2c8586074bb82b96c02db Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Tue, 31 Oct 2023 18:24:39 +0000
+Subject: [PATCH 30/39] crank up vram allocation on more intel boards
+
+these were added to libreboot, and it's a policy of
+libreboot to max out the vram settings. this was
+overlooked, in prior revisions and releases.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/dell/e6400/cmos.default                | 2 +-
+ src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
+ src/mainboard/hp/compaq_8200_elite_sff/cmos.default  | 2 +-
+ src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
+ src/mainboard/hp/snb_ivb_laptops/cmos.default        | 1 +
+ src/mainboard/lenovo/t420/cmos.default               | 1 +
+ src/mainboard/lenovo/t420s/cmos.default              | 1 +
+ src/mainboard/lenovo/t430/cmos.default               | 1 +
+ src/mainboard/lenovo/t520/cmos.default               | 1 +
+ src/mainboard/lenovo/t530/cmos.default               | 1 +
+ src/mainboard/lenovo/x201/cmos.default               | 1 +
+ src/mainboard/lenovo/x220/cmos.default               | 1 +
+ 12 files changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
+index 744a599708..6b8d478f06 100644
+--- a/src/mainboard/dell/e6400/cmos.default
+++ b/src/mainboard/dell/e6400/cmos.default
+@@ -4,4 +4,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Disable
+ sata_mode=AHCI
+-gfx_uma_size=32M
+gfx_uma_size=256M
+diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
+index 76c16e6a8d..19364aae6e 100644
+--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
+++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
+@@ -5,5 +5,5 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=128M
+gfx_uma_size=224M
+ fan_full_speed=Disable
+diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+index 497ae92e1f..64d43a07f7 100644
+--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+@@ -5,5 +5,5 @@ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
+gfx_uma_size=224M
+ psu_fan_lvl=3
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+index f3dad88670..b60f28447b 100644
+--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+@@ -5,4 +5,4 @@ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
+gfx_uma_size=224M
+diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
+index e6042c0c27..a04026b70c 100644
+--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
+++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
+@@ -5,3 +5,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
+index 27a62d07b3..d1c9fcaaaf 100644
+--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
+@@ -17,3 +17,4 @@ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
+gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
+index 27a62d07b3..d1c9fcaaaf 100644
+--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
+@@ -17,3 +17,4 @@ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
+gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
+index 6d1e172056..c00b358314 100644
+--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
+@@ -18,3 +18,4 @@ backlight=Both
+ usb_always_on=Disable
+ hybrid_graphics_mode=Integrated Only
+ me_state=Disabled
+gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
+index ab1be1a678..c7ee9564f3 100644
+--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
+@@ -18,3 +18,4 @@ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
+gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
+index ab1be1a678..c7ee9564f3 100644
+--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
+@@ -18,3 +18,4 @@ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
+gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
+index 94f8e08a75..a1f2eacf11 100644
+--- a/src/mainboard/lenovo/x201/cmos.default
+++ b/src/mainboard/lenovo/x201/cmos.default
+@@ -17,3 +17,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ usb_always_on=Disable
+gfx_uma_size=128M
+diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
+index b318ab9772..82292ea5d6 100644
+--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
+@@ -16,3 +16,4 @@ fn_ctrl_swap=Disable
+ sticky_fn=Disable
+ trackpoint=Enable
+ me_state=Disabled
+gfx_uma_size=224M
+-- 
+2.39.2
+
@@ -1,36 +0,0 @@
-From 287a6d09ac6f5cdfc8255c2020e37441ddb870c7 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Thu, 26 Dec 2024 19:45:20 +0000
-Subject: [PATCH 30/41] soc/intel/skylake: Don't compress FSP-S
-
-Build systems like lbmk need to reproducibly insert
-certain vendor files on release images.
-
-Compression isn't always reproducible, and making it
-so costs a lot more time than simply disabling compression.
-
-With this change, the FSP-S module will now be inserted
-without compression, which means that there will now be
-about 40KB of extra space used in the flash.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- src/soc/intel/skylake/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index 70c2a7643c..a2854923e7 100644
--- a/src/soc/intel/skylake/Kconfig
-+++ b/src/soc/intel/skylake/Kconfig
-@@ -14,7 +14,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
- 	select DRAM_SUPPORT_DDR4
- 	select DRIVERS_USB_ACPI
- 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
-	select FSP_COMPRESS_FSP_S_LZ4
-+#	select FSP_COMPRESS_FSP_S_LZ4
- 	select FSP_M_XIP
- 	select GENERIC_GPIO_LIB
- 	select HAVE_FSP_GOP
-- 
-2.47.3
-
@@ -1,7 +1,7 @@
-From bf464f17367c0dfa7f2c667d699800f3c6e60040 Mon Sep 17 00:00:00 2001
+From dc02595f99566f71513ee16f1883e315b725241a Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 11:41:41 +0000
-Subject: [PATCH 09/41] dell/e6430: use ME Soft Temporary Disable
+Subject: [PATCH 31/39] dell/e6430: use ME Soft Temporary Disable

 i overlooked this. it's set on other boards.

@@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644
 -me_state=Normal
 +me_state=Disabled
 -- 
-2.47.3
+2.39.2

@@ -1,78 +0,0 @@
-From c0bb0e62f169e07ab11c434fbd79a6a26b4e7690 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Wed, 18 Dec 2024 02:06:18 +0000
-Subject: [PATCH 31/41] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
-
-This is used by lbmk to know where a tb.bin file goes,
-when extracting and padding TBT.bin from Lenovo ThunderBolt
-firmware updates on T480/T480s and other machines, grabbing
-Lenovo update files.
-
-Not used in any builds, so it's not relevant for ./mk inject
-
-However, the ThunderBolt firmware is now auto-downloaded on
-T480/T480s. This is not inserted, because it doesn't go in
-the main flash, but the resulting ROM image can be flashed
-on the TB controller's separate flash chip.
-
-Locations are as follows:
-
-vendorfiles/t480s/tb.bin
-vendorfiles/t480/tb.bin
-
-This can be used for other affected ThinkPads when they're
-added to Libreboot, but note that Lenovo provides different
-TB firmware files for each machine.
-
-Since I assume it's the same TB controller on all of those
-machines, I have to wonder: what difference is there between
-the various TBT.bin files provided by Lenovo, and how do they
-differ in terms of actual flashed configuration?
-
-We simply flash the padded TBT.bin when updating the firmware,
-flashing externally. That's what this patch is for, so that
-lbmk can auto-download them.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
---
- src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
-index 2ffbaab85f..512b326381 100644
--- a/src/mainboard/lenovo/Kconfig
-+++ b/src/mainboard/lenovo/Kconfig
-@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY
- 	string
- 	default MAINBOARD_PART_NUMBER
- 
-+config LENOVO_TBFW_BIN
-+	string "Lenovo ThunderBolt firmware bin file"
-+	default ""
-+	help
-+	  ThunderBolt firmware for certain ThinkPad models e.g. T480.
-+	  Not used in the actual build. Libreboot's build system uses this
-+	  along with config/vendor/*/pkg.cfg entries defining a URL to the
-+	  Lenovo download link and hash. The resulting file when processed by
-+	  lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device.
-+	  Earlier versions of this firmware had debug commands enabled that
-+	  sent logs to said flash IC, and it would quickly fill up, bricking
-+	  the ThunderBolt controller. With these updates, flashed externally,
-+	  you can fix the issue if present or otherwise prevent it. The benefit
-+	  here is that you then don't need to use Windows or a boot disk. You
-+	  can flash the TB firmware while flashing Libreboot firmware. Easy!
-+	  Look for these variables in lbmk:
-+	  TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and
-+	  CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file.
-+	  The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting
-+	  the firmware, putting it at that desired location. In this way, lbmk
-+	  can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb
-+	  and it appears at vendorfiles/t480/tb.bin fully padded and everything!
-+
-+	  Just leave this blank if you don't care about this option. It's not
-+	  useful for every ThinkPad, only certain models.
-+
- endif # VENDOR_LENOVO
-- 
-2.47.3
-
@@ -1,37 +0,0 @@
-From c25cf16fb0d278354c7e2c19f534a04e27ac46dd Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 21 Apr 2025 05:14:45 +0100
-Subject: [PATCH 32/41] Conditional TBFW setting for kabylake thinkpads
-
-Otherwise, other boards will define it, which
-might trigger the vendor download script, and
-lead to a non-zero exit.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/mainboard/lenovo/Kconfig | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
-index 512b326381..b2c7763198 100644
--- a/src/mainboard/lenovo/Kconfig
-+++ b/src/mainboard/lenovo/Kconfig
-@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY
- 	string
- 	default MAINBOARD_PART_NUMBER
- 
-+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580
-+
- config LENOVO_TBFW_BIN
- 	string "Lenovo ThunderBolt firmware bin file"
- 	default ""
-@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN
- 	  Just leave this blank if you don't care about this option. It's not
- 	  useful for every ThinkPad, only certain models.
- 
-+endif # BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_X280 || BOARD_LENOVO_T470S || BOARD_LENOVO_T580
-+
- endif # VENDOR_LENOVO
-- 
-2.47.3
-
@@ -0,0 +1,36 @@
+From adb6121970034aa63da8c6303292ff81f340d9db Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 5 Nov 2023 22:57:08 +0000
+Subject: [PATCH 32/39] use mirrorservice.org for gcc downloads
+
+the gnu.org 302 redirect often fails
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 5faff337b4..2743f96903 100755
+--- a/util/crossgcc/buildgcc
+++ b/util/crossgcc/buildgcc
+@@ -69,11 +69,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
+ # to the jenkins build as well, or the builder won't download it.
+ 
+ # GCC toolchain archive locations
+-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
+-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
+MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
+MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
+GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
+BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
+ IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+
@@ -1,7 +1,7 @@
-From 5c27543224963e7fa17ad18dea27d186685e9f13 Mon Sep 17 00:00:00 2001
+From 67b7a9e4d06d595adf8382ee83e82b5019e23afa Mon Sep 17 00:00:00 2001
 From: Riku Viitanen <riku.viitanen@protonmail.com>
 Date: Sat, 23 Dec 2023 19:02:10 +0200
-Subject: [PATCH 10/41] mb/hp: Add Compaq Elite 8300 CMT port
+Subject: [PATCH 1/1] mb/hp: Add Compaq Elite 8300 CMT port

 Based on autoport and Z220 SuperIO code.

@@ -868,5 +868,5 @@ index 0000000000..8dbd95ef96
 +	.enable_dev = mainboard_enable,
 +};
 -- 
-2.47.3
+2.39.2

@@ -1,30 +0,0 @@
-From 2c3a31547a14eb1b1145a5d153289b2eef6d71d8 Mon Sep 17 00:00:00 2001
-From: Riku Viitanen <riku.viitanen@protonmail.com>
-Date: Sat, 27 Sep 2025 23:30:46 +0300
-Subject: [PATCH 33/41] soc/intel/alderlake: Disable
- MRC_CACHE_USING_MRC_VERSION
-
-There's some issue with building against the FSP headers in src/vendorcode.
-Headers in 3rdparty/fsp work, but since FspProducerDataHeaer.h is missing
-from there, we need to disable MRC_CACHE_USING_MRC_VERSION by force.
-
-Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
---
- src/soc/intel/alderlake/Kconfig | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
-index 97c2ecca70..a2074fe05a 100644
--- a/src/soc/intel/alderlake/Kconfig
-+++ b/src/soc/intel/alderlake/Kconfig
-@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE
- 	select INTEL_GMA_VERSION_2
- 	select INTEL_TXT_LIB
- 	select MP_SERVICES_PPI_V2
-	select MRC_CACHE_USING_MRC_VERSION if (SOC_INTEL_ALDERLAKE_PCH_N || SOC_INTEL_RAPTORLAKE) && !FSP_USE_REPO
- 	select MRC_SETTINGS_PROTECT
- 	select PARALLEL_MP_AP_WORK
- 	select PLATFORM_USES_FSP2_2
-- 
-2.47.3
-
@@ -1,76 +0,0 @@
-From 8eeb1de057b19938f1221b85e00699c58de90069 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sun, 28 Sep 2025 03:17:50 +0100
-Subject: [PATCH 34/41] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks)
-
-if you pass -k (keep fptr modules), don't use -r, don't
-use -t, you can essentially just use me_cleaner to
-extract a ME image without changing it. this is useful
-when for example, you just want to set the HAP bit.
-
-however, me_cleaner still performs a FPTR check.
-
-on some newer ME versions, it's always invalid according
-to me_cleaner, because for example it doesn't handle
-ME16 very well yet.
-
-this patch adds an option to override the FPTR check
-
-either pass -p or --pass-fptr
-
-NOTE: we probably won't use this on coreboot's me_cleaner,
-which is the corna version. we only need it on the newer
-me_cleaner versions for e.g. ME16, on certain setups.
-still, it's best to have the patch here too, just in case.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- util/me_cleaner/me_cleaner.py | 14 ++++++++++----
- 1 file changed, 10 insertions(+), 4 deletions(-)
-
-diff --git a/util/me_cleaner/me_cleaner.py b/util/me_cleaner/me_cleaner.py
-index fae5e56732..228bac899f 100755
--- a/util/me_cleaner/me_cleaner.py
-+++ b/util/me_cleaner/me_cleaner.py
-@@ -246,8 +246,10 @@ def check_partition_signature(f, offset):
-     return "{:#x}".format(decrypted_sig).endswith(sha256.hexdigest())   # FIXME
- 
- 
-def print_check_partition_signature(f, offset):
-    if check_partition_signature(f, offset):
-+def print_check_partition_signature(f, offset, pass_fptr):
-+    if pass_fptr:
-+        print("Skipping FPTR checks because the user told us to")
-+    elif check_partition_signature(f, offset):
-         print("VALID")
-     else:
-         print("INVALID!!")
-@@ -486,6 +488,8 @@ if __name__ == "__main__":
-                         "--extract-me)", action="store_true")
-     parser.add_argument("-k", "--keep-modules", help="don't remove the FTPR "
-                         "modules, even when possible", action="store_true")
-+    parser.add_argument("-p", "--pass-fptr", help="skip FTPR signature checks"
-+                        "regardless of other operations", action="store_true")
-     bw_list.add_argument("-w", "--whitelist", metavar="whitelist",
-                          help="Comma separated list of additional partitions "
-                          "to keep in the final image. This can be used to "
-@@ -871,12 +875,14 @@ if __name__ == "__main__":
-             print("Checking the FTPR RSA signature of the extracted ME "
-                   "image... ", end="")
-             print_check_partition_signature(mef_copy,
-                                            ftpr_offset + ftpr_mn2_offset)
-+                                            ftpr_offset + ftpr_mn2_offset,
-+                                                args.pass_fptr)
-         mef_copy.close()
- 
-     if not me6_ignition:
-         print("Checking the FTPR RSA signature... ", end="")
-        print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset)
-+        print_check_partition_signature(mef, ftpr_offset + ftpr_mn2_offset,
-+                                                args.pass_fptr)
- 
-     f.close()
- 
-- 
-2.47.3
-
@@ -1,7 +1,7 @@
-From 062b28da685d1c9f7cbe8333e98257a83ce4ca82 Mon Sep 17 00:00:00 2001
+From eef3e0d517bde40d4761a9af3c004801a89db887 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 2 Mar 2024 22:51:09 +0000
-Subject: [PATCH 11/41] nb/intel/haswell: make IOMMU a runtime option
+Subject: [PATCH 34/39] nb/intel/haswell: make IOMMU a runtime option

 When I tested graphics cards on a coreboot port for Dell
 OptiPlex 9020 SFF, I could not use a graphics card unless
@@ -288,5 +288,5 @@ index e47deb5da6..1a7e0b1076 100644
 	if (capid0_a & VTD_DISABLE)
 		return;
 -- 
-2.47.3
+2.39.2

@@ -1,7 +1,7 @@
-From 5bd5bc755af744b51e0577970dc6f5214bd0cfee Mon Sep 17 00:00:00 2001
+From b7a80abe673c279e755efbe92851ec0600467fae Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 2 Mar 2024 23:00:09 +0000
-Subject: [PATCH 12/41] dell/optiplex_9020: Disable IOMMU by default
+Subject: [PATCH 35/39] dell/optiplex_9020: Disable IOMMU by default

 Needed to make graphics cards work. Turning it on is
 recommended if only using iGPU, otherwise leave it off
@@ -25,5 +25,5 @@ index 8000eea8c0..0700f971ee 100644
 -iommu=Enable
 +iommu=Disable
 -- 
-2.47.3
+2.39.2

@@ -1,35 +0,0 @@
-From be79f8b72a098dcd51639210935ba02d2f5ff808 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sat, 4 Oct 2025 21:57:43 +0100
-Subject: [PATCH 35/41] soc/intel/alderlake: Don't compress FSP-S
-
-Build systems like lbmk need to reproducibly insert
-certain vendor files on release images.
-
-Compression isn't always reproducible, and making it
-so costs a lot more time than simply disabling compression.
-
-With this change, FSP-S uses slightly more space inside
-the flash, but it's not that much.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/soc/intel/alderlake/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
-index a2074fe05a..08137d2706 100644
--- a/src/soc/intel/alderlake/Kconfig
-+++ b/src/soc/intel/alderlake/Kconfig
-@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE
- 	select DRAM_SUPPORT_DDR5
- 	select DRIVERS_USB_ACPI
- 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
-	select FSP_COMPRESS_FSP_S_LZ4
-+#	select FSP_COMPRESS_FSP_S_LZ4
- 	select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW
- 	select FSP_M_XIP
- 	select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN
-- 
-2.47.3
-
@@ -1,33 +0,0 @@
-From 226df168b34467ca8555e953b6d793f273c0b82c Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sat, 4 Oct 2025 22:20:11 +0100
-Subject: [PATCH 36/41] alderlake: don't require full fsp repo for fd path
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/soc/intel/alderlake/Kconfig | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
-diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
-index 08137d2706..67e47c2e36 100644
--- a/src/soc/intel/alderlake/Kconfig
-+++ b/src/soc/intel/alderlake/Kconfig
-@@ -417,7 +417,14 @@ config FSP_HEADER_PATH
- 
- config FSP_FD_PATH
- 	string
-	depends on FSP_USE_REPO
-+#	dependency removed for lbmk purposes, so that the path is present
-+#	in the config regardless of whether it's used. this is for ./mk -d
-+#	on alderlake boards, which is used by lbmk to manually split fsp,
-+#	even though the result is identical to what coreboot produces, because
-+#	this enables lbmk to strip the fsp in release archives, and re-insert
-+#	for compliance reasons (due to technicalities in intel's licensing),
-+#	and to enable lbmk's advanced checksum verification of vendor files
-+#	depends on FSP_USE_REPO
- 	default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd"   if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE
- 	default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd"   if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S
- 	default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd"     if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P
-- 
-2.47.3
-
@@ -1,7 +1,7 @@
-From 78da1e003a69a4cc6bd5e71e4bc43a4844d05f16 Mon Sep 17 00:00:00 2001
+From 4c0f0d139cdc0fbfadf76ee576d69503b81dc9dc Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 6 Apr 2024 01:22:47 +0100
-Subject: [PATCH 13/41] nb/haswell: Fully disable iGPU when dGPU is used
+Subject: [PATCH 36/39] nb/haswell: Fully disable iGPU when dGPU is used

 My earlier patch disabled decode *and* disabled the iGPU itself, but
 a subsequent revision disabled only VGA decode. Upon revisiting, I
@@ -47,5 +47,5 @@ index f7fad3183d..1b188e92e1 100644
 
 static struct device_operations gma_func0_ops = {
 -- 
-2.47.3
+2.39.2

@@ -1,37 +1,16 @@
-From 0a982ec4b606b6c236f71478350b69f532f30719 Mon Sep 17 00:00:00 2001
+From 7e921212d3113320b2d28e66cd6a6788533fcab7 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 3 May 2024 11:03:32 -0600
-Subject: [PATCH 14/41] ec/dell/mec5035: Add S3 suspend SMI handler
-
-This is necessary for S3 resume to work on SNB and newer Dell Latitude
-laptops. If a command isn't sent, the EC cuts power to the DIMMs,
-preventing the system from resuming. These commands were found using an
-FPGA to log all LPC bus transactions between the host and the EC and
-then narrowing down which ones were actually necessary.
-
-Interestingly, the command IDs appear to be identical to those in
-ec/google/wilco, the EC used on Dell Latitude Chromebooks, and that EC
-implements a similar S3 SMI handler as the one implemented in this
-commit. The Wilco EC Kconfig does suggest that its firmware is a
-modified version of Dell's usual Latitude EC firmware, so the
-similarities seem to be intentional.
-
-These similarities also identified a command to enable or disable wake
-sources like the power button and lid switch, and this was added to the
-SMI handler to disable lid wake as the system does not yet resume
-properly from a like wake with coreboot.
-
-Tested on the Latitude E6430 (Ivy Bridge) and the Precision M6800
-(Haswell, not yet pushed).
+Subject: [PATCH 37/39] ec/dell/mec5035: Add S3 suspend SMI handler

 Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
 ---
 src/ec/dell/mec5035/Makefile.mk  |  1 +
- src/ec/dell/mec5035/mec5035.c    | 13 +++++++++++++
- src/ec/dell/mec5035/mec5035.h    | 22 ++++++++++++++++++++++
+ src/ec/dell/mec5035/mec5035.c    | 14 ++++++++++++++
+ src/ec/dell/mec5035/mec5035.h    | 19 +++++++++++++++++++
 src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++
- 4 files changed, 53 insertions(+)
+ 4 files changed, 51 insertions(+)
 create mode 100644 src/ec/dell/mec5035/smihandler.c

 diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk
@@ -46,13 +25,20 @@ index 4ebdd811f9..be557e4599 100644
 
 endif
 diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 17ac2c1dab..c5067c16f6 100644
+index 68b6b2f7fb..33bf046634 100644
 --- a/src/ec/dell/mec5035/mec5035.c
 +++ b/src/ec/dell/mec5035/mec5035.c
-@@ -100,6 +100,19 @@ static void mec5035_power_button_route(enum ec_power_button_route target)
- 	write_mailbox_regs(&buf, 2, 1);
- 	ec_command(CMD_POWER_BUTTON_TO_HOST);
+@@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
+ 	ec_command(CMD_RADIO_CTRL);
 }
+ 
+void mec5035_sleep_enable(void)
+{
+	u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
+	write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
+	ec_command(CMD_SLEEP_ENABLE);
+}
+
 +void mec5035_change_wake(u8 source, enum ec_wake_change change)
 +{
 +	u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
@@ -60,17 +46,11 @@ index 17ac2c1dab..c5067c16f6 100644
 +	ec_command(CMD_ACPI_WAKEUP_CHANGE);
 +}
 +
-+void mec5035_sleep_enable(void)
-+{
-+	u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
-+	write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
-+	ec_command(CMD_SLEEP_ENABLE);
-+}
- 
 void mec5035_early_init(void)
 {
+ 	/* If this isn't sent the EC shuts down the system after about 15
 diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index 5fdf56631b..5cd907bf71 100644
+index fa15a9d621..069616fbc5 100644
 --- a/src/ec/dell/mec5035/mec5035.h
 +++ b/src/ec/dell/mec5035/mec5035.h
@@ -4,6 +4,7 @@
@@ -81,47 +61,37 @@ index 5fdf56631b..5cd907bf71 100644
 
 #define NUM_REGISTERS	32
 
-@@ -11,6 +12,8 @@ enum mec5035_cmd {
- 	CMD_MOUSE_TP = 0x1a,
- 	CMD_RADIO_CTRL = 0x2b,
- 	CMD_POWER_BUTTON_TO_HOST = 0x3e,
-+	CMD_ACPI_WAKEUP_CHANGE = 0x4a,
-+	CMD_SLEEP_ENABLE = 0x64,
- 	CMD_CPU_OK = 0xc2,
- };
- 
-@@ -39,9 +42,28 @@ enum ec_power_button_route {
- 	HOST
+@@ -29,9 +30,27 @@ enum ec_radio_state {
+ 	RADIO_ON
 };
 
+#define CMD_ACPI_WAKEUP_CHANGE 0x4a
 +#define ACPI_WAKEUP_NUM_ARGS 4
 +enum ec_wake_change {
 +	WAKE_OFF = 0,
 +	WAKE_ON
 +};
-+
-+/* Copied from ec/google/wilco/commands.h. Not sure if these all apply */
 +enum ec_acpi_wake_events {
 +	EC_ACPI_WAKE_PWRB = BIT(0),     /* Wake up by power button */
 +	EC_ACPI_WAKE_LID = BIT(1),      /* Wake up by lid switch */
 +	EC_ACPI_WAKE_RTC = BIT(5),      /* Wake up by RTC */
 +};
 +
+#define CMD_SLEEP_ENABLE 0x64
 +#define SLEEP_EN_NUM_ARGS 2
 +
- u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
+ u8 mec5035_mouse_touchpad(u8 setting);
 void mec5035_cpu_ok(void);
 void mec5035_early_init(void);
 void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
+void mec5035_sleep(int slp_type);
 +void mec5035_change_wake(u8 source, enum ec_wake_change change);
 +void mec5035_sleep_enable(void);
-+
-+void mec5035_smi_sleep(int slp_type);
 
 #endif /* _EC_DELL_MEC5035_H_ */
 diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c
 new file mode 100644
-index 0000000000..958733bf97
+index 0000000000..1db834773d
 --- /dev/null
 +++ b/src/ec/dell/mec5035/smihandler.c
@@ -0,0 +1,17 @@
@@ -132,7 +102,7 @@ index 0000000000..958733bf97
 +#include <ec/acpi/ec.h>
 +#include "mec5035.h"
 +
-+void mec5035_smi_sleep(int slp_type)
+void mec5035_sleep(int slp_type)
 +{
 +	switch (slp_type) {
 +	case ACPI_S3:
@@ -143,5 +113,5 @@ index 0000000000..958733bf97
 +	}
 +}
 -- 
-2.47.3
+2.39.2

@@ -1,46 +0,0 @@
-From 30366be45e5b7521b93475f68c7143bd683b25f3 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 6 Oct 2025 04:47:06 +0100
-Subject: [PATCH 37/41] soc/alderlake: disable stack overflow debug option
-
-same as on other boards. based on this commit:
-
-commit 51cc2bacb6b07279b97e9934d079060475481fb6
-Author: Subrata Banik <subratabanik@google.com>
-Author: Subrata Banik <subratabanik@google.com>
-Date:   Fri Dec 13 13:07:28 2024 +0530
-
-    soc/intel/pantherlake: Disable stack overflow debug options
-
-yeah, i've been replicating this change per platform.
-
-we do alderlake now in libreboot, so let's set that here too.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/soc/intel/alderlake/Kconfig | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
-index 67e47c2e36..e9c56fc6b9 100644
--- a/src/soc/intel/alderlake/Kconfig
-+++ b/src/soc/intel/alderlake/Kconfig
-@@ -331,6 +331,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ
- 	int
- 	default 19200000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+	bool
-+	default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+	bool
-+	default n
-+
- config DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ
- 	int
- 	default 133
-- 
-2.47.3
-
@@ -1,92 +0,0 @@
-From 90332fe96aca0de4d99d58d1593048c77e1bdecf Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 11 May 2025 15:41:22 -0600
-Subject: [PATCH 38/41] ec/dell/mec5035: Add command to disable EC-initiated
- thermal shutdown
-
-If command 0xBF isn't sent, the EC shuts down the system without warning
-as soon as the CPU temperature reaches about 87 degrees, without letting
-the CPU thermal throttle to try and reduce the temperature. With vendor
-firmware, the CPU is able to reach around 100 degrees before thermal
-throttling.
-
-This command was found by collecting EC commands by logging the LPC bus
-while running with vendor firmware and then replaying observed commands
-from coreboot. By systematically replaying subsets of commands in a
-binary search pattern and then stress testing the system, the command to
-disable the shutdown was isolated.
-
-The exact meaning of the parameters for this command are unknown at this
-time, but do seem to differ between different generations of these
-laptops. Due to this, the commmand should be called by mainboard
-specific code which passes the specific parameter value used.
-
-The Google Wilco EC code, which runs on Latitude Chromebooks and shares
-many commands with the standard Latitude ECs, suggests that command 0xBF
-tells the EC about the processors CPUID. However, the values observed in
-LPC bus logs do not seem to correspond with any CPUID values on the
-non-Chromebook systems I tested.
-
-Observed command parameter values (sent on mailbox registers 2-4):
- E6430 (Ivy Bridge): 0x07, 0x00, 0x00
- M6800 (Haswell): 0x14, 0x00, 0x00
-
-Change-Id: I42f09a3ef681007f64d9c5b1a29248b594737a86
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/ec/dell/mec5035/mec5035.c | 19 +++++++++++++++++++
- src/ec/dell/mec5035/mec5035.h |  2 ++
- 2 files changed, 21 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index c5067c16f6..b316fa4989 100644
--- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -114,6 +114,25 @@ void mec5035_sleep_enable(void)
- 	ec_command(CMD_SLEEP_ENABLE);
- }
- 
-+void mec5035_cmd_bf(u8 i)
-+{
-+	/*
-+	 * If this command isn't sent, the EC shuts down the system as soon as
-+	 * the CPU temperature reaches about 87 degrees. It is unknown exactly
-+	 * what the parameters represent. The Google Wilco EC code, which runs
-+	 * on Latitude Chromebooks and shares some commands with the standard
-+	 * Latitude EC code, suggests command 0xBF tells the EC the CPUID, but
-+	 * the values observed in LPC bus logs don't seem to match any CPUID
-+	 * values of the normal Latitudes this was tested with.
-+	 * Observed i values:
-+	 * - E6430 (Ivy Bridge): 0x7
-+	 * - M6800 (Haswell): 0x14
-+	 */
-+	u8 buf[3] = {i, 0, 0};
-+	write_mailbox_regs(buf, 2, 3);
-+	ec_command(CMD_BF);
-+}
-+
- void mec5035_early_init(void)
- {
- 	/* If this isn't sent the EC shuts down the system after about 15
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index 5cd907bf71..71d1a71075 100644
--- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -14,6 +14,7 @@ enum mec5035_cmd {
- 	CMD_POWER_BUTTON_TO_HOST = 0x3e,
- 	CMD_ACPI_WAKEUP_CHANGE = 0x4a,
- 	CMD_SLEEP_ENABLE = 0x64,
-+	CMD_BF = 0xbf,
- 	CMD_CPU_OK = 0xc2,
- };
- 
-@@ -65,5 +66,6 @@ void mec5035_change_wake(u8 source, enum ec_wake_change change);
- void mec5035_sleep_enable(void);
- 
- void mec5035_smi_sleep(int slp_type);
-+void mec5035_cmd_bf(u8 i);
- 
- #endif /* _EC_DELL_MEC5035_H_ */
-- 
-2.47.3
-
@@ -0,0 +1,31 @@
+From 53bddae0fc8436fe262ca7fc2e19049afa7a38f8 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 3 May 2024 16:31:12 -0600
+Subject: [PATCH 38/39] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes
+
+This should fix S3 suspend on these systems
+
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+ create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
+
+diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
+@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cpu/x86/smm.h>
+#include <ec/dell/mec5035/mec5035.h>
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+	mec5035_sleep(slp_typ);
+}
+-- 
+2.39.2
+
@@ -1,36 +0,0 @@
-From 68048f4afe369ece02143f9a4a7da2104ff2d10b Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 11 May 2025 16:28:23 -0600
-Subject: [PATCH 39/41] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown
- at 87 degrees
-
-If command 0xBF isn't sent, the EC will shut down the system without
-warning once the CPU reaches approximately 87 degrees, without the
-system thermal throttling first. Call the newly added function from the
-MEC5035 code to send this command and disable this behavior.
-
-Tested on the Latitude E6430.
-
-Change-Id: I2b2dc1e3ab115e05d05eaac06892343394d37fdf
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
- src/mainboard/dell/snb_ivb_latitude/early_init.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/early_init.c b/src/mainboard/dell/snb_ivb_latitude/early_init.c
-index ff83db095b..ef385a0a70 100644
--- a/src/mainboard/dell/snb_ivb_latitude/early_init.c
-+++ b/src/mainboard/dell/snb_ivb_latitude/early_init.c
-@@ -11,4 +11,9 @@ void bootblock_mainboard_early_init(void)
- 			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
- 			| COMB_LPC_EN | COMA_LPC_EN);
- 	mec5035_early_init();
-+
-+	/* Observed from LPC logs with vendor firmware. Seems to disable
-+	 * EC-initiated shutdown when the CPU reaches approximately 87 degrees.
-+	 * The exact meaning of the parameter is currently unknown. */
-+	mec5035_cmd_bf(0x07);
- }
-- 
-2.47.3
-
@@ -1,7 +1,7 @@
-From 9ca5c919339049518e842980041f528d48d79124 Mon Sep 17 00:00:00 2001
+From 919cbfa034db5d2ef9e56dd71ef329c38c5ede3c Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 4 May 2024 02:00:53 +0100
-Subject: [PATCH 15/41] nb/haswell: lock policy regs when disabling IOMMU
+Subject: [PATCH 39/39] nb/haswell: lock policy regs when disabling IOMMU

 Angel Pons told me I should do it. See comments here:
 https://review.coreboot.org/c/coreboot/+/81016
@@ -51,5 +51,5 @@ index 1a7e0b1076..e9506ee830 100644
 	/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
 	u32 reg32;
 -- 
-2.47.3
+2.39.2

@@ -1,7 +1,7 @@
-From e74c4ee6a62ef9f91a8efb257658f627498b91fa Mon Sep 17 00:00:00 2001
+From fe5e1655be8cdb8eff1659e5ce6acbd06b9a7620 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH 16/41] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH 1/3] nb/intel/gm45: Make DDR2 raminit work

 List of changes:
 - Update some timing and ODT values
@@ -20,7 +20,7 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
 3 files changed, 106 insertions(+), 13 deletions(-)

 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
-index f68bfdee7a..b76117bc3a 100644
+index 5d9ac56606..338260ea7a 100644
 --- a/src/northbridge/intel/gm45/gm45.h
 +++ b/src/northbridge/intel/gm45/gm45.h
@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
@@ -31,9 +31,9 @@ index f68bfdee7a..b76117bc3a 100644
 +void raminit_rcomp_calibration(int ddr_type, stepping_t stepping);
 void raminit_reset_readwrite_pointers(void);
 void raminit_receive_enable_calibration(int ddr_type, const timings_t *, const dimminfo_t *);
- void raminit_write_training(const mem_clock_t, const dimminfo_t *, bool s3resume);
+ void raminit_write_training(const mem_clock_t, const dimminfo_t *, int s3resume);
 diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
-index def9e1e331..7b091cc567 100644
+index b7e013959a..df8f46fbbc 100644
 --- a/src/northbridge/intel/gm45/raminit.c
 +++ b/src/northbridge/intel/gm45/raminit.c
@@ -1047,7 +1047,7 @@ static void rcomp_initialization(const int spd_type, const stepping_t stepping,
@@ -70,7 +70,7 @@ index def9e1e331..7b091cc567 100644
 		}
 		mchbar_write32(CxODT_HIGH(ch), reg);
 
-@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume)
+@@ -2209,6 +2209,84 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
 		raminit_write_training(timings->mem_clock, dimms, s3resume);
 	}
 
@@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644
 +	mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
 }
 -- 
-2.47.3
+2.39.2

@@ -1,7 +1,7 @@
-From da433a5d9a7d1d7856b55761b8392864343de5a8 Mon Sep 17 00:00:00 2001
+From 88a9c562b77316f1217139e62425f9af1c351c6f Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Tue, 6 Aug 2024 00:50:24 +0100
-Subject: [PATCH 17/41] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
+Subject: [PATCH 41/59] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards

 We add this patch:

@@ -32,7 +32,7 @@ Signed-off-by: Leah Rowe <info@minifree.org>
 2 files changed, 88 insertions(+), 82 deletions(-)

 diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
-index 7b091cc567..478898564a 100644
+index df8f46fbbc..433db3a68c 100644
 --- a/src/northbridge/intel/gm45/raminit.c
 +++ b/src/northbridge/intel/gm45/raminit.c
@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
@@ -47,7 +47,7 @@ index 7b091cc567..478898564a 100644
 		} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
 			reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
 			reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
-@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const bool s3resume)
+@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
 		raminit_write_training(timings->mem_clock, dimms, s3resume);
 	}
 
@@ -236,5 +236,5 @@ index b74765fd9c..5d4505e063 100644
 +	}
 }
 -- 
-2.47.3
+2.39.2

@@ -1,28 +0,0 @@
-From 6e084398d4e6847b0f64325dadd4cfee0b43d7ea Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sat, 20 Dec 2025 20:12:48 +0100
-Subject: [PATCH 1/1] fix ifdtool build
-
-not my mistake. someone messed up.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- util/ifdtool/ifdtool.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index ea8dfc788d..33f00436bc 100644
--- a/util/ifdtool/ifdtool.c
-+++ b/util/ifdtool/ifdtool.c
-@@ -2598,7 +2598,7 @@ int main(int argc, char *argv[])
-                        }
-                        mode_nuke = 1;
-                        break;
-		Case 'v':
-+		case 'v':
- 			print_version();
- 			exit(EXIT_SUCCESS);
- 			break;
-- 
-2.47.3
-
@@ -1,7 +1,7 @@
-From b4443cfe4b63a49b8170bdfb6dacbc8d52110eff Mon Sep 17 00:00:00 2001
+From b42ca30081b25cbabfb2659adca9d935ef3a8399 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Mon, 20 May 2024 10:24:16 -0600
-Subject: [PATCH 18/41] mb/dell/e6400: Use 100 MHz reference clock for display
+Subject: [PATCH 3/3] mb/dell/e6400: Use 100 MHz reference clock for display

 The E6400 uses a 100 MHz reference clock for spread spectrum support on
 LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
@@ -14,25 +14,26 @@ display in the pre-OS graphics environment provided by libgfxinit.

 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
 ---
- src/mainboard/dell/gm45_latitude/Kconfig | 2 ++
- src/northbridge/intel/gm45/Kconfig       | 4 ++++
- 2 files changed, 6 insertions(+)
+ src/mainboard/dell/e6400/Kconfig   | 3 +++
+ src/northbridge/intel/gm45/Kconfig | 4 ++++
+ 2 files changed, 7 insertions(+)

-diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
-index edc79b0d43..5020744990 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig
-@@ -22,6 +22,8 @@ config BOARD_DELL_E6400
- 	select BOARD_DELL_GM45_LATITUDE_COMMON
+diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
+index 417d95fd5d..6fe1b1c456 100644
+--- a/src/mainboard/dell/e6400/Kconfig
+++ b/src/mainboard/dell/e6400/Kconfig
+@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select INTEL_GMA_HAVE_VBT
+ 	select EC_DELL_MEC5035
 
- if BOARD_DELL_GM45_LATITUDE_COMMON
 +config INTEL_GMA_DPLL_REF_FREQ
 +	default 100000000
- 
+
 config MAINBOARD_DIR
- 	default "dell/gm45_latitude"
+ 	default "dell/e6400"
+ 
 diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
-index a776217475..35e89b0c88 100644
+index 8059e7ee80..5df5a93296 100644
 --- a/src/northbridge/intel/gm45/Kconfig
 +++ b/src/northbridge/intel/gm45/Kconfig
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
@@ -47,5 +48,5 @@ index a776217475..35e89b0c88 100644
 	select VBOOT_STARTS_IN_BOOTBLOCK
 
 -- 
-2.47.3
+2.39.2

@@ -0,0 +1,348 @@
+From 8b584165a99c69cc808f86efcdd55acb06a4464c Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Thu, 11 Apr 2024 17:25:07 +0200
+Subject: [PATCH 01/17] haswell NRI: Initialise MPLL
+
+Add code to initialise the MPLL (Memory PLL). The procedure is similar
+to the one for Sandy/Ivy Bridge, but it is not worth factoring out.
+
+Change-Id: I978c352de68f6d8cecc76f4ae3c12daaf4be9ed6
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   2 +
+ .../intel/haswell/native_raminit/init_mpll.c  | 210 ++++++++++++++++++
+ .../haswell/native_raminit/io_comp_control.c  |  22 ++
+ .../haswell/native_raminit/raminit_main.c     |   3 +-
+ .../haswell/native_raminit/raminit_native.h   |  11 +
+ .../intel/haswell/registers/mchbar.h          |   3 +
+ 6 files changed, 250 insertions(+), 1 deletion(-)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/init_mpll.c
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/io_comp_control.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index ebf7abc6ec..c125d84f0b 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -1,5 +1,7 @@
+ ## SPDX-License-Identifier: GPL-2.0-or-later
+ 
+romstage-y += init_mpll.c
+romstage-y += io_comp_control.c
+ romstage-y += raminit_main.c
+ romstage-y += raminit_native.c
+ romstage-y += spd_bitmunching.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/init_mpll.c b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
+new file mode 100644
+index 0000000000..1f3f2c29a9
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/init_mpll.c
+@@ -0,0 +1,210 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static uint32_t get_mem_multiplier(const struct sysinfo *ctrl)
+{
+	const uint32_t mult = NS2MHZ_DIV256 / (ctrl->tCK * ctrl->base_freq);
+
+	if (ctrl->base_freq == 100)
+		return clamp_u32(7, mult, 12);
+
+	if (ctrl->base_freq == 133)
+		return clamp_u32(3, mult, 10);
+
+	die("Unsupported base frequency\n");
+}
+
+static void normalize_tck(struct sysinfo *ctrl, const bool pll_ref100)
+{
+	/** TODO: Haswell supports up to DDR3-2600 **/
+	if (ctrl->tCK <= TCK_1200MHZ) {
+		ctrl->tCK = TCK_1200MHZ;
+		ctrl->base_freq = 133;
+		ctrl->mem_clock_mhz = 1200;
+
+	} else if (ctrl->tCK <= TCK_1100MHZ) {
+		ctrl->tCK = TCK_1100MHZ;
+		ctrl->base_freq = 100;
+		ctrl->mem_clock_mhz = 1100;
+
+	} else if (ctrl->tCK <= TCK_1066MHZ) {
+		ctrl->tCK = TCK_1066MHZ;
+		ctrl->base_freq = 133;
+		ctrl->mem_clock_mhz = 1066;
+
+	} else if (ctrl->tCK <= TCK_1000MHZ) {
+		ctrl->tCK = TCK_1000MHZ;
+		ctrl->base_freq = 100;
+		ctrl->mem_clock_mhz = 1000;
+
+	} else if (ctrl->tCK <= TCK_933MHZ) {
+		ctrl->tCK = TCK_933MHZ;
+		ctrl->base_freq = 133;
+		ctrl->mem_clock_mhz = 933;
+
+	} else if (ctrl->tCK <= TCK_900MHZ) {
+		ctrl->tCK = TCK_900MHZ;
+		ctrl->base_freq = 100;
+		ctrl->mem_clock_mhz = 900;
+
+	} else if (ctrl->tCK <= TCK_800MHZ) {
+		ctrl->tCK = TCK_800MHZ;
+		ctrl->base_freq = 133;
+		ctrl->mem_clock_mhz = 800;
+
+	} else if (ctrl->tCK <= TCK_700MHZ) {
+		ctrl->tCK = TCK_700MHZ;
+		ctrl->base_freq = 100;
+		ctrl->mem_clock_mhz = 700;
+
+	} else if (ctrl->tCK <= TCK_666MHZ) {
+		ctrl->tCK = TCK_666MHZ;
+		ctrl->base_freq = 133;
+		ctrl->mem_clock_mhz = 666;
+
+	} else if (ctrl->tCK <= TCK_533MHZ) {
+		ctrl->tCK = TCK_533MHZ;
+		ctrl->base_freq = 133;
+		ctrl->mem_clock_mhz = 533;
+
+	} else if (ctrl->tCK <= TCK_400MHZ) {
+		ctrl->tCK = TCK_400MHZ;
+		ctrl->base_freq = 133;
+		ctrl->mem_clock_mhz = 400;
+
+	} else {
+		ctrl->tCK = 0;
+		ctrl->base_freq = 1;
+		ctrl->mem_clock_mhz = 0;
+		return;
+	}
+	if (!pll_ref100 && ctrl->base_freq == 100) {
+		/* Skip unsupported frequency */
+		ctrl->tCK++;
+		normalize_tck(ctrl, pll_ref100);
+	}
+}
+
+#define MIN_CAS	4
+#define MAX_CAS	24
+
+static uint8_t find_compatible_cas(struct sysinfo *ctrl)
+{
+	printk(RAM_DEBUG, "With tCK %u, try CAS: ", ctrl->tCK);
+	const uint8_t cas_lower = MAX(MIN_CAS, DIV_ROUND_UP(ctrl->tAA, ctrl->tCK));
+	const uint8_t cas_upper = MIN(MAX_CAS, 19); /* JEDEC MR0 limit */
+
+	if (!(ctrl->cas_supported >> (cas_lower - MIN_CAS))) {
+		printk(RAM_DEBUG, "DIMMs do not support CAS >= %u\n", cas_lower);
+		ctrl->tCK++;
+		return 0;
+	}
+	for (uint8_t cas = cas_lower; cas <= cas_upper; cas++) {
+		printk(RAM_DEBUG, "%u ", cas);
+		if (ctrl->cas_supported & BIT(cas - MIN_CAS)) {
+			printk(RAM_DEBUG, "OK\n");
+			return cas;
+		}
+	}
+	return 0;
+}
+
+static enum raminit_status find_cas_tck(struct sysinfo *ctrl)
+{
+	/** TODO: Honor all possible PLL_REF100_CFG values **/
+	uint8_t pll_ref100 = (pci_read_config32(HOST_BRIDGE, CAPID0_B) >> 21) & 0x7;
+	printk(RAM_DEBUG, "PLL_REF100_CFG value: 0x%x\n", pll_ref100);
+	printk(RAM_DEBUG, "100MHz reference clock support: %s\n", pll_ref100 ? "yes" : "no");
+
+	uint8_t selected_cas;
+	while (true) {
+		/* Round tCK up so that it is a multiple of either 133 or 100 MHz */
+		normalize_tck(ctrl, pll_ref100);
+		if (!ctrl->tCK) {
+			printk(BIOS_ERR, "Couldn't find compatible clock / CAS settings\n");
+			return RAMINIT_STATUS_MPLL_INIT_FAILURE;
+		}
+		selected_cas = find_compatible_cas(ctrl);
+		if (selected_cas)
+			break;
+
+		ctrl->tCK++;
+	}
+	printk(BIOS_DEBUG, "Found compatible clock / CAS settings\n");
+	printk(BIOS_DEBUG, "Selected DRAM frequency: %u MHz\n", NS2MHZ_DIV256 / ctrl->tCK);
+	printk(BIOS_DEBUG, "Selected CAS latency   : %uT\n", selected_cas);
+	ctrl->multiplier = get_mem_multiplier(ctrl);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+enum raminit_status initialise_mpll(struct sysinfo *ctrl)
+{
+	if (ctrl->tCK > TCK_400MHZ) {
+		printk(BIOS_ERR, "tCK is too slow. Increasing to 400 MHz as last resort\n");
+		ctrl->tCK = TCK_400MHZ;
+	}
+	while (true) {
+		if (!ctrl->qclkps) {
+			const enum raminit_status status = find_cas_tck(ctrl);
+			if (status)
+				return status;
+		}
+
+		/*
+		 * Unlike previous generations, Haswell's MPLL won't shut down if the
+		 * requested frequency isn't supported. But we cannot reinitialize it.
+		 * Another different thing: MPLL registers are 4-bit instead of 8-bit.
+		 */
+
+		/** FIXME: Obtain current clock frequency if we want to skip this **/
+		//if (mchbar_read32(MC_BIOS_DATA) != 0)
+		//	break;
+
+		uint32_t mc_bios_req = ctrl->multiplier;
+		if (ctrl->base_freq == 100) {
+			/* Use 100 MHz reference clock */
+			mc_bios_req |= BIT(4);
+		}
+		mc_bios_req |= BIT(31);
+		printk(RAM_DEBUG, "MC_BIOS_REQ = 0x%08x\n", mc_bios_req);
+		printk(BIOS_DEBUG, "MPLL busy... ");
+		mchbar_write32(MC_BIOS_REQ, mc_bios_req);
+
+		for (unsigned int i = 0; i <= 5000; i++) {
+			if (!(mchbar_read32(MC_BIOS_REQ) & BIT(31))) {
+				printk(BIOS_DEBUG, "done in %u us\n", i);
+				break;
+			}
+			udelay(1);
+		}
+		if (mchbar_read32(MC_BIOS_REQ) & BIT(31))
+			printk(BIOS_DEBUG, "did not lock\n");
+
+		/* Verify locked frequency */
+		const uint32_t mc_bios_data = mchbar_read32(MC_BIOS_DATA);
+		printk(RAM_DEBUG, "MC_BIOS_DATA = 0x%08x\n", mc_bios_data);
+		if ((mc_bios_data & 0xf) >= ctrl->multiplier)
+			break;
+
+		printk(BIOS_DEBUG, "Retrying at a lower frequency\n\n");
+		ctrl->tCK++;
+	}
+	if (!ctrl->mem_clock_mhz) {
+		printk(BIOS_ERR, "Could not program MPLL frequency\n");
+		return RAMINIT_STATUS_MPLL_INIT_FAILURE;
+	}
+	printk(BIOS_DEBUG, "MPLL frequency is set to: %u MHz ", ctrl->mem_clock_mhz);
+	ctrl->mem_clock_fs = 1000000000 / ctrl->mem_clock_mhz;
+	printk(BIOS_DEBUG, "(period: %u femtoseconds)\n", ctrl->mem_clock_fs);
+	ctrl->qclkps = ctrl->mem_clock_fs / 2000;
+	printk(BIOS_DEBUG, "Quadrature clock period: %u picoseconds\n", ctrl->qclkps);
+	return wait_for_first_rcomp();
+}
+diff --git a/src/northbridge/intel/haswell/native_raminit/io_comp_control.c b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
+new file mode 100644
+index 0000000000..d45b608dd3
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/io_comp_control.c
+@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+enum raminit_status wait_for_first_rcomp(void)
+{
+	struct stopwatch timer;
+	stopwatch_init_msecs_expire(&timer, 2000);
+	do {
+		if (mchbar_read32(RCOMP_TIMER) & BIT(16))
+			return RAMINIT_STATUS_SUCCESS;
+
+	} while (!stopwatch_expired(&timer));
+	printk(BIOS_ERR, "Timed out waiting for RCOMP to complete\n");
+	return RAMINIT_STATUS_POLL_TIMEOUT;
+}
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index 19ec5859ac..bf745e943f 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -19,7 +19,8 @@ struct task_entry {
+ };
+ 
+ static const struct task_entry cold_boot[] = {
+-	{ collect_spd_info,           true, "PROCSPD",    },
+	{ collect_spd_info,                                       true, "PROCSPD",    },
+	{ initialise_mpll,                                        true, "INITMPLL",   },
+ };
+ 
+ /* Return a generic stepping value to make stepping checks simpler */
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 8078c9c386..15a1550424 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -24,6 +24,8 @@ enum raminit_status {
+ 	RAMINIT_STATUS_SUCCESS = 0,
+ 	RAMINIT_STATUS_NO_MEMORY_INSTALLED,
+ 	RAMINIT_STATUS_UNSUPPORTED_MEMORY,
+	RAMINIT_STATUS_MPLL_INIT_FAILURE,
+	RAMINIT_STATUS_POLL_TIMEOUT,
+ 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
+ };
+ 
+@@ -83,10 +85,19 @@ struct sysinfo {
+ 	uint8_t rankmap[NUM_CHANNELS];
+ 	uint8_t rank_mirrored[NUM_CHANNELS];
+ 	uint32_t channel_size_mb[NUM_CHANNELS];
+
+	uint8_t base_freq;		/* Memory base frequency, either 100 or 133 MHz */
+	uint32_t multiplier;
+	uint32_t mem_clock_mhz;
+	uint32_t mem_clock_fs;		/* Memory clock period in femtoseconds */
+	uint32_t qclkps;		/* Quadrature clock period in picoseconds */
+ };
+ 
+ void raminit_main(enum raminit_boot_mode bootmode);
+ 
+ enum raminit_status collect_spd_info(struct sysinfo *ctrl);
+enum raminit_status initialise_mpll(struct sysinfo *ctrl);
+
+enum raminit_status wait_for_first_rcomp(void);
+ 
+ #endif
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index 5610e7089a..45f8174995 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -13,6 +13,8 @@
+ #define MC_INIT_STATE_G		0x5030
+ #define MRC_REVISION		0x5034 /* MRC Revision */
+ 
+#define RCOMP_TIMER		0x5084
+
+ #define MC_LOCK			0x50fc /* Memory Controller Lock register */
+ 
+ #define GFXVTBAR		0x5400 /* Base address for IGD */
+@@ -61,6 +63,7 @@
+ 
+ #define BIOS_RESET_CPL		0x5da8 /* 8-bit */
+ 
+#define MC_BIOS_REQ		0x5e00 /* Memory frequency request register */
+ #define MC_BIOS_DATA		0x5e04 /* Miscellaneous information for BIOS */
+ #define SAPMCTL			0x5f00
+ 
+-- 
+2.39.2
+
@@ -0,0 +1,249 @@
+From adde2e8d038b2d07ab7287eedab5888d92a56a60 Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sat, 7 May 2022 16:29:55 +0200
+Subject: [PATCH 02/17] haswell NRI: Post-process selected timings
+
+Once the MPLL has been initialised, convert the timings from the SPD to
+be in DCLKs, which is what the hardware expects. In addition, calculate
+the values for tREFI and tXP.
+
+Change-Id: Id02caf858f75b9e08016762b3aefda282b274386
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/lookup_timings.c   |  62 +++++++++++
+ .../haswell/native_raminit/raminit_main.c     |   1 +
+ .../haswell/native_raminit/raminit_native.h   |   8 ++
+ .../haswell/native_raminit/spd_bitmunching.c  | 100 ++++++++++++++++++
+ 5 files changed, 172 insertions(+)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/lookup_timings.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index c125d84f0b..2769e0bbb4 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -1,5 +1,6 @@
+ ## SPDX-License-Identifier: GPL-2.0-or-later
+ 
+romstage-y += lookup_timings.c
+ romstage-y += init_mpll.c
+ romstage-y += io_comp_control.c
+ romstage-y += raminit_main.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
+new file mode 100644
+index 0000000000..8b81c7c341
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
+@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+struct timing_lookup {
+	uint32_t clock;
+	uint32_t value;
+};
+
+static uint32_t lookup_timing(
+	const uint32_t mem_clock_mhz,
+	const struct timing_lookup *const lookup,
+	const size_t length)
+{
+	/* Fall back to the last index */
+	size_t i;
+	for (i = 0; i < length - 1; i++) {
+		/* Account for imprecise frequency values */
+		if ((mem_clock_mhz - 5) <= lookup[i].clock)
+			break;
+	}
+	return lookup[i].value;
+}
+
+static const uint32_t fmax = UINT32_MAX;
+
+uint8_t get_tCWL(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  400,  5 },
+		{  533,  6 },
+		{  666,  7 },
+		{  800,  8 },
+		{  933,  9 },
+		{ 1066, 10 },
+		{ 1200, 11 },
+		{ fmax, 12 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+/* tREFI = 7800 ns * DDR MHz */
+uint32_t get_tREFI(const uint32_t mem_clock_mhz)
+{
+	return (mem_clock_mhz * 7800) / 1000;
+}
+
+uint32_t get_tXP(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  400,  3 },
+		{  666,  4 },
+		{  800,  5 },
+		{  933,  6 },
+		{ 1066,  7 },
+		{ fmax,  8 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index bf745e943f..2fea658415 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -21,6 +21,7 @@ struct task_entry {
+ static const struct task_entry cold_boot[] = {
+ 	{ collect_spd_info,                                       true, "PROCSPD",    },
+ 	{ initialise_mpll,                                        true, "INITMPLL",   },
+	{ convert_timings,                                        true, "CONVTIM",    },
+ };
+ 
+ /* Return a generic stepping value to make stepping checks simpler */
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 15a1550424..e0ebd3a2a7 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -79,6 +79,9 @@ struct sysinfo {
+ 	uint32_t tCWL;
+ 	uint32_t tCMD;
+ 
+	uint32_t tREFI;
+	uint32_t tXP;
+
+ 	uint8_t lanes;			/* 8 or 9 */
+ 	uint8_t chanmap;
+ 	uint8_t dpc[NUM_CHANNELS];	/* DIMMs per channel */
+@@ -97,7 +100,12 @@ void raminit_main(enum raminit_boot_mode bootmode);
+ 
+ enum raminit_status collect_spd_info(struct sysinfo *ctrl);
+ enum raminit_status initialise_mpll(struct sysinfo *ctrl);
+enum raminit_status convert_timings(struct sysinfo *ctrl);
+ 
+ enum raminit_status wait_for_first_rcomp(void);
+ 
+uint8_t get_tCWL(uint32_t mem_clock_mhz);
+uint32_t get_tREFI(uint32_t mem_clock_mhz);
+uint32_t get_tXP(uint32_t mem_clock_mhz);
+
+ #endif
+diff --git a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
+index eff993800b..4f7fe46494 100644
+--- a/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
+++ b/src/northbridge/intel/haswell/native_raminit/spd_bitmunching.c
+@@ -204,3 +204,103 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl)
+ 	get_spd_data(ctrl);
+ 	return find_common_spd_parameters(ctrl);
+ }
+
+#define MIN_CWL		5
+#define MAX_CWL		12
+
+/* Except for tCK, hardware expects all timing values in DCLKs, not nanoseconds */
+enum raminit_status convert_timings(struct sysinfo *ctrl)
+{
+	/*
+	 * Obtain all required timing values, in DCLKs.
+	 */
+
+	/* Convert primary timings from nanoseconds to DCLKs */
+	ctrl->tAA  = DIV_ROUND_UP(ctrl->tAA,  ctrl->tCK);
+	ctrl->tWR  = DIV_ROUND_UP(ctrl->tWR,  ctrl->tCK);
+	ctrl->tRCD = DIV_ROUND_UP(ctrl->tRCD, ctrl->tCK);
+	ctrl->tRRD = DIV_ROUND_UP(ctrl->tRRD, ctrl->tCK);
+	ctrl->tRP  = DIV_ROUND_UP(ctrl->tRP,  ctrl->tCK);
+	ctrl->tRAS = DIV_ROUND_UP(ctrl->tRAS, ctrl->tCK);
+	ctrl->tRC  = DIV_ROUND_UP(ctrl->tRC,  ctrl->tCK);
+	ctrl->tRFC = DIV_ROUND_UP(ctrl->tRFC, ctrl->tCK);
+	ctrl->tWTR = DIV_ROUND_UP(ctrl->tWTR, ctrl->tCK);
+	ctrl->tRTP = DIV_ROUND_UP(ctrl->tRTP, ctrl->tCK);
+	ctrl->tFAW = DIV_ROUND_UP(ctrl->tFAW, ctrl->tCK);
+	ctrl->tCWL = DIV_ROUND_UP(ctrl->tCWL, ctrl->tCK);
+	ctrl->tCMD = DIV_ROUND_UP(ctrl->tCMD, ctrl->tCK);
+
+	/* Constrain primary timings to hardware limits */
+	/** TODO: complain when clamping? **/
+	ctrl->tAA  = clamp_u32(4,  ctrl->tAA,  24);
+	ctrl->tWR  = clamp_u32(5,  ctrl->tWR,  16);
+	ctrl->tRCD = clamp_u32(4,  ctrl->tRCD, 20);
+	ctrl->tRRD = clamp_u32(4,  ctrl->tRRD, 65535);
+	ctrl->tRP  = clamp_u32(4,  ctrl->tRP,  15);
+	ctrl->tRAS = clamp_u32(10, ctrl->tRAS, 40);
+	ctrl->tRC  = clamp_u32(1,  ctrl->tRC,  4095);
+	ctrl->tRFC = clamp_u32(1,  ctrl->tRFC, 511);
+	ctrl->tWTR = clamp_u32(4,  ctrl->tWTR, 10);
+	ctrl->tRTP = clamp_u32(4,  ctrl->tRTP, 15);
+	ctrl->tFAW = clamp_u32(10, ctrl->tFAW, 54);
+
+	/** TODO: Honor tREFI from XMP **/
+	ctrl->tREFI = get_tREFI(ctrl->mem_clock_mhz);
+	ctrl->tXP   =   get_tXP(ctrl->mem_clock_mhz);
+
+	/*
+	 * Check some values, and adjust them if necessary.
+	 */
+
+	/* If tWR cannot be written into DDR3 MR0, adjust it */
+	switch (ctrl->tWR) {
+	case  9:
+	case 11:
+	case 13:
+	case 15:
+		ctrl->tWR++;
+	}
+
+	/* If tCWL is not supported or unspecified, look up a reasonable default */
+	if (ctrl->tCWL < MIN_CWL || ctrl->tCWL > MAX_CWL)
+		ctrl->tCWL = get_tCWL(ctrl->mem_clock_mhz);
+
+	/* This is needed to support ODT properly on 2DPC */
+	if (ctrl->tAA - ctrl->tCWL > 4)
+		ctrl->tCWL = ctrl->tAA - 4;
+
+	/* If tCMD is invalid, use a guesstimate default */
+	if (!ctrl->tCMD) {
+		ctrl->tCMD = MAX(ctrl->dpc[0], ctrl->dpc[1]);
+		printk(RAM_DEBUG, "tCMD was zero, picking a guesstimate value\n");
+	}
+	ctrl->tCMD = clamp_u32(1, ctrl->tCMD, 3);
+
+	/*
+	 * Print final timings.
+	 */
+
+	/* tCK is special */
+	printk(BIOS_DEBUG, "Selected tCK          : %u ps\n", ctrl->tCK * 1000 / 256);
+
+	/* Primary timings */
+	printk(BIOS_DEBUG, "Selected tAA          : %uT\n", ctrl->tAA);
+	printk(BIOS_DEBUG, "Selected tWR          : %uT\n", ctrl->tWR);
+	printk(BIOS_DEBUG, "Selected tRCD         : %uT\n", ctrl->tRCD);
+	printk(BIOS_DEBUG, "Selected tRRD         : %uT\n", ctrl->tRRD);
+	printk(BIOS_DEBUG, "Selected tRP          : %uT\n", ctrl->tRP);
+	printk(BIOS_DEBUG, "Selected tRAS         : %uT\n", ctrl->tRAS);
+	printk(BIOS_DEBUG, "Selected tRC          : %uT\n", ctrl->tRC);
+	printk(BIOS_DEBUG, "Selected tRFC         : %uT\n", ctrl->tRFC);
+	printk(BIOS_DEBUG, "Selected tWTR         : %uT\n", ctrl->tWTR);
+	printk(BIOS_DEBUG, "Selected tRTP         : %uT\n", ctrl->tRTP);
+	printk(BIOS_DEBUG, "Selected tFAW         : %uT\n", ctrl->tFAW);
+	printk(BIOS_DEBUG, "Selected tCWL         : %uT\n", ctrl->tCWL);
+	printk(BIOS_DEBUG, "Selected tCMD         : %uT\n", ctrl->tCMD);
+
+	/* Derived timings */
+	printk(BIOS_DEBUG, "Selected tREFI        : %uT\n", ctrl->tREFI);
+	printk(BIOS_DEBUG, "Selected tXP          : %uT\n", ctrl->tXP);
+
+	return RAMINIT_STATUS_SUCCESS;
+}
+-- 
+2.39.2
+
@@ -1,30 +0,0 @@
-From ca27517cb5752d078a3f8328ff6b220f652b0849 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Sat, 20 Dec 2025 22:36:18 +0100
-Subject: [PATCH 1/1] tests/Makefile.mk: use 3rdparty/cmocka by default
-
-(tests)
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- tests/Makefile.mk | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/tests/Makefile.mk b/tests/Makefile.mk
-index f3f122dd38..33bb2a2d07 100644
--- a/tests/Makefile.mk
-+++ b/tests/Makefile.mk
-@@ -25,7 +25,9 @@ TEST_LDFLAGS += --coverage
- endif
- 
- # Use system cmoka in default, or build from 3rdparty source code if requested
-USE_SYSTEM_CMOCKA ?= 1
-+# PATCH NOTE: lbmk sets it to 0 by default. You can still override it to 1
-+#             if you wish; upstream sets this to 1 by default, but we do 0
-+USE_SYSTEM_CMOCKA ?= 0
- ifeq ($(USE_SYSTEM_CMOCKA),1)
- ifeq ($(shell $(HOSTPKG_CONFIG) --exists cmocka || echo 1),1)
- $(warning No system cmocka, build from 3rdparty instead...)
-- 
-2.47.3
-
@@ -0,0 +1,541 @@
+From 44032c7df6f4537c43ba80ae2f4a239616bd8d2d Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sat, 7 May 2022 20:59:58 +0200
+Subject: [PATCH 04/17] haswell NRI: Add timings/refresh programming
+
+Program the registers with timing and refresh parameters.
+
+Change-Id: Id2ea339d2c9ea8b56c71d6e88ec76949653ff5c2
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../haswell/native_raminit/lookup_timings.c   | 102 ++++++++
+ .../haswell/native_raminit/raminit_native.h   |  14 ++
+ .../haswell/native_raminit/reg_structs.h      |  93 +++++++
+ .../haswell/native_raminit/timings_refresh.c  | 233 +++++++++++++++++-
+ .../intel/haswell/registers/mchbar.h          |  12 +
+ 5 files changed, 452 insertions(+), 2 deletions(-)
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
+index 8b81c7c341..b8d6c1ef40 100644
+--- a/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
+++ b/src/northbridge/intel/haswell/native_raminit/lookup_timings.c
+@@ -60,3 +60,105 @@ uint32_t get_tXP(const uint32_t mem_clock_mhz)
+ 	};
+ 	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+ }
+
+static uint32_t get_lpddr_tCKE(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  533,  4 },
+		{  666,  5 },
+		{ fmax,  6 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+static uint32_t get_ddr_tCKE(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  533,  3 },
+		{  800,  4 },
+		{  933,  5 },
+		{ 1200,  6 },
+		{ fmax,  7 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tCKE(const uint32_t mem_clock_mhz, const bool lpddr)
+{
+	return lpddr ? get_lpddr_tCKE(mem_clock_mhz) : get_ddr_tCKE(mem_clock_mhz);
+}
+
+uint32_t get_tXPDLL(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  400, 10 },
+		{  533, 13 },
+		{  666, 16 },
+		{  800, 20 },
+		{  933, 23 },
+		{ 1066, 26 },
+		{ 1200, 29 },
+		{ fmax, 32 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tAONPD(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  400,  4 },
+		{  533,  5 },
+		{  666,  6 },
+		{  800,  7 }, /* SNB had 8 */
+		{  933,  8 },
+		{ 1066, 10 },
+		{ 1200, 11 },
+		{ fmax, 12 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tMOD(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  800, 12 },
+		{  933, 14 },
+		{ 1066, 16 },
+		{ 1200, 18 },
+		{ fmax, 20 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+uint32_t get_tXS_offset(const uint32_t mem_clock_mhz)
+{
+	return DIV_ROUND_UP(mem_clock_mhz, 100);
+}
+
+static uint32_t get_lpddr_tZQOPER(const uint32_t mem_clock_mhz)
+{
+	return (mem_clock_mhz * 360) / 1000;
+}
+
+static uint32_t get_ddr_tZQOPER(const uint32_t mem_clock_mhz)
+{
+	const struct timing_lookup lut[] = {
+		{  800, 256 },
+		{  933, 299 },
+		{ 1066, 342 },
+		{ 1200, 384 },
+		{ fmax, 427 },
+	};
+	return lookup_timing(mem_clock_mhz, lut, ARRAY_SIZE(lut));
+}
+
+/* tZQOPER defines the period required for ZQCL after SR exit */
+uint32_t get_tZQOPER(const uint32_t mem_clock_mhz, const bool lpddr)
+{
+	return lpddr ? get_lpddr_tZQOPER(mem_clock_mhz) : get_ddr_tZQOPER(mem_clock_mhz);
+}
+
+uint32_t get_tZQCS(const uint32_t mem_clock_mhz, const bool lpddr)
+{
+	return DIV_ROUND_UP(get_tZQOPER(mem_clock_mhz, lpddr), 4);
+}
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index fffa6d5450..5915a2bab0 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -156,6 +156,12 @@ struct sysinfo {
+ 	uint8_t cke_cmd_pi_code[NUM_CHANNELS][NUM_GROUPS];
+ 	uint8_t cmd_north_pi_code[NUM_CHANNELS][NUM_GROUPS];
+ 	uint8_t cmd_south_pi_code[NUM_CHANNELS][NUM_GROUPS];
+
+	union tc_bank_reg tc_bank[NUM_CHANNELS];
+	union tc_bank_rank_a_reg tc_bankrank_a[NUM_CHANNELS];
+	union tc_bank_rank_b_reg tc_bankrank_b[NUM_CHANNELS];
+	union tc_bank_rank_c_reg tc_bankrank_c[NUM_CHANNELS];
+	union tc_bank_rank_d_reg tc_bankrank_d[NUM_CHANNELS];
+ };
+ 
+ static inline bool is_hsw_ult(void)
+@@ -201,6 +207,14 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
+ void configure_timings(struct sysinfo *ctrl);
+ void configure_refresh(struct sysinfo *ctrl);
+ 
+uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
+uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
+uint32_t get_tAONPD(uint32_t mem_clock_mhz);
+uint32_t get_tMOD(uint32_t mem_clock_mhz);
+uint32_t get_tXS_offset(uint32_t mem_clock_mhz);
+uint32_t get_tZQOPER(uint32_t mem_clock_mhz, bool lpddr);
+uint32_t get_tZQCS(uint32_t mem_clock_mhz, bool lpddr);
+
+ enum raminit_status wait_for_first_rcomp(void);
+ 
+ uint8_t get_rx_bias(const struct sysinfo *ctrl);
+diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+index d11cda4b3d..70487e1640 100644
+--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+@@ -335,6 +335,99 @@ union mcscheds_cbit_reg {
+ 	uint32_t raw;
+ };
+ 
+union tc_bank_reg {
+	struct __packed {
+		uint32_t tRCD      : 5; // Bits  4:0
+		uint32_t tRP       : 5; // Bits  9:5
+		uint32_t tRAS      : 6; // Bits 15:10
+		uint32_t tRDPRE    : 4; // Bits 19:16
+		uint32_t tWRPRE    : 6; // Bits 25:20
+		uint32_t tRRD      : 4; // Bits 29:26
+		uint32_t tRPab_ext : 2; // Bits 31:30
+	};
+	uint32_t raw;
+};
+
+union tc_bank_rank_a_reg {
+	struct __packed {
+		uint32_t tCKE        : 4; // Bits  3:0
+		uint32_t tFAW        : 8; // Bits 11:4
+		uint32_t tRDRD_sr    : 3; // Bits 14:12
+		uint32_t tRDRD_dr    : 4; // Bits 18:15
+		uint32_t tRDRD_dd    : 4; // Bits 22:19
+		uint32_t tRDPDEN     : 5; // Bits 27:23
+		uint32_t             : 1; // Bits 28:28
+		uint32_t cmd_3st_dis : 1; // Bits 29:29
+		uint32_t cmd_stretch : 2; // Bits 31:30
+	};
+	uint32_t raw;
+};
+
+union tc_bank_rank_b_reg {
+	struct __packed {
+		uint32_t tWRRD_sr : 6; // Bits  5:0
+		uint32_t tWRRD_dr : 4; // Bits  9:6
+		uint32_t tWRRD_dd : 4; // Bits 13:10
+		uint32_t tWRWR_sr : 3; // Bits 16:14
+		uint32_t tWRWR_dr : 4; // Bits 20:17
+		uint32_t tWRWR_dd : 4; // Bits 24:21
+		uint32_t tWRPDEN  : 6; // Bits 30:25
+		uint32_t dec_wrd  : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+union tc_bank_rank_c_reg {
+	struct __packed {
+		uint32_t tXPDLL   : 6; // Bits  5:0
+		uint32_t tXP      : 4; // Bits  9:6
+		uint32_t tAONPD   : 4; // Bits 13:10
+		uint32_t tRDWR_sr : 5; // Bits 18:14
+		uint32_t tRDWR_dr : 5; // Bits 23:19
+		uint32_t tRDWR_dd : 5; // Bits 28:24
+		uint32_t          : 3; // Bits 31:29
+	};
+	uint32_t raw;
+};
+
+/* NOTE: Non-ULT only implements the lower 21 bits (odt_write_delay is 2 bits) */
+union tc_bank_rank_d_reg {
+	struct __packed {
+		uint32_t tAA                : 5; // Bits  4:0
+		uint32_t tCWL               : 5; // Bits  9:5
+		uint32_t tCPDED             : 2; // Bits 11:10
+		uint32_t tPRPDEN            : 2; // Bits 13:12
+		uint32_t odt_read_delay     : 3; // Bits 16:14
+		uint32_t odt_read_duration  : 2; // Bits 18:17
+		uint32_t odt_write_duration : 3; // Bits 21:19
+		uint32_t odt_write_delay    : 3; // Bits 24:22
+		uint32_t odt_always_rank_0  : 1; // Bits 25:25
+		uint32_t cmd_delay          : 2; // Bits 27:26
+		uint32_t                    : 4; // Bits 31:28
+	};
+	uint32_t raw;
+};
+
+union tc_rftp_reg {
+	struct __packed {
+		uint32_t tREFI   : 16; // Bits 15:0
+		uint32_t tRFC    :  9; // Bits 24:16
+		uint32_t tREFIx9 :  7; // Bits 31:25
+	};
+	uint32_t raw;
+};
+
+union tc_srftp_reg {
+	struct __packed {
+		uint32_t tXSDLL     : 12; // Bits 11:0
+		uint32_t tXS_offset :  4; // Bits 15:12
+		uint32_t tZQOPER    : 10; // Bits 25:16
+		uint32_t            :  2; // Bits 27:26
+		uint32_t tMOD       :  4; // Bits 31:28
+	};
+	uint32_t raw;
+};
+
+ union mcmain_command_rate_limit_reg {
+ 	struct __packed {
+ 		uint32_t enable_cmd_limit :  1; // Bits  0:0
+diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
+index a9d960f31b..54fee0121d 100644
+--- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
+@@ -1,13 +1,242 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+#include <assert.h>
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+
+ #include "raminit_native.h"
+ 
+#define BL		8	/* Burst length */
+#define tCCD		4
+#define tRPRE		1
+#define tWPRE		1
+#define tDLLK		512
+
+static bool is_sodimm(const enum spd_dimm_type_ddr3 type)
+{
+	return type == SPD_DDR3_DIMM_TYPE_SO_DIMM || type == SPD_DDR3_DIMM_TYPE_72B_SO_UDIMM;
+}
+
+static uint8_t get_odt_stretch(const struct sysinfo *const ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		/* Only stretch with 2 DIMMs per channel */
+		if (ctrl->dpc[channel] != 2)
+			continue;
+
+		const struct raminit_dimm_info *dimms = ctrl->dimms[channel];
+
+		/* Only stretch when using SO-DIMMs */
+		if (!is_sodimm(dimms[0].data.dimm_type) || !is_sodimm(dimms[1].data.dimm_type))
+			continue;
+
+		/* Only stretch with mismatched card types */
+		if (dimms[0].data.reference_card == dimms[1].data.reference_card)
+			continue;
+
+		/* Stretch if one SO-DIMM is card F */
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+			if (dimms[slot].data.reference_card == 5)
+				return 1;
+		}
+	}
+	return 0;
+}
+
+static union tc_bank_reg make_tc_bank(struct sysinfo *const ctrl)
+{
+	return (union tc_bank_reg) {
+		.tRCD      = ctrl->tRCD,
+		.tRP       = ctrl->tRP,
+		.tRAS      = ctrl->tRAS,
+		.tRDPRE    = ctrl->tRTP,
+		.tWRPRE    = 4 + ctrl->tCWL + ctrl->tWR,
+		.tRRD      = ctrl->tRRD,
+		.tRPab_ext = 0,	/** TODO: For LPDDR, this is ctrl->tRPab - ctrl->tRP **/
+	};
+}
+
+static union tc_bank_rank_a_reg make_tc_bankrank_a(struct sysinfo *ctrl, uint8_t odt_stretch)
+{
+	/* Use 3N mode for DDR during training, but always use 1N mode for LPDDR */
+	const uint32_t tCMD = ctrl->lpddr ? 0 : 3;
+	const uint32_t tRDRD_drdd = BL / 2 + 1 + tRPRE + odt_stretch + !!ctrl->lpddr;
+
+	return (union tc_bank_rank_a_reg) {
+		.tCKE        = get_tCKE(ctrl->mem_clock_mhz, ctrl->lpddr),
+		.tFAW        = ctrl->tFAW,
+		.tRDRD_sr    = tCCD,
+		.tRDRD_dr    = tRDRD_drdd,
+		.tRDRD_dd    = tRDRD_drdd,
+		.tRDPDEN     = ctrl->tAA + BL / 2 + 1,
+		.cmd_3st_dis = 1,	/* Disable command tri-state before training */
+		.cmd_stretch = tCMD,
+	};
+}
+
+static union tc_bank_rank_b_reg make_tc_bankrank_b(struct sysinfo *const ctrl)
+{
+	const uint8_t tWRRD_drdd = ctrl->tCWL - ctrl->tAA + BL / 2 + 2 + tRPRE;
+	const uint8_t tWRWR_drdd = BL / 2 + 2 + tWPRE;
+
+	return (union tc_bank_rank_b_reg) {
+		.tWRRD_sr = tCCD + ctrl->tCWL + ctrl->tWTR + 2,
+		.tWRRD_dr = ctrl->lpddr ? 8 : tWRRD_drdd,
+		.tWRRD_dd = ctrl->lpddr ? 8 : tWRRD_drdd,
+		.tWRWR_sr = tCCD,
+		.tWRWR_dr = tWRWR_drdd,
+		.tWRWR_dd = tWRWR_drdd,
+		.tWRPDEN  = ctrl->tWR + ctrl->tCWL + BL / 2,
+		.dec_wrd  = ctrl->tCWL >= 6,
+	};
+}
+
+static uint32_t get_tRDWR_sr(const struct sysinfo *ctrl)
+{
+	if (ctrl->lpddr) {
+		const uint32_t tdqsck_max = DIV_ROUND_UP(5500, ctrl->qclkps * 2);
+		return ctrl->tAA - ctrl->tCWL + tCCD + tWPRE + tdqsck_max + 1;
+	} else {
+		const bool fast_clock = ctrl->mem_clock_mhz > 666;
+		return ctrl->tAA - ctrl->tCWL + tCCD + tWPRE + 2 + fast_clock;
+	}
+}
+
+static union tc_bank_rank_c_reg make_tc_bankrank_c(struct sysinfo *ctrl, uint8_t odt_stretch)
+{
+	const uint32_t tRDWR_sr = get_tRDWR_sr(ctrl);
+	const uint32_t tRDWR_drdd = tRDWR_sr + odt_stretch;
+
+	return (union tc_bank_rank_c_reg) {
+		.tXPDLL   = get_tXPDLL(ctrl->mem_clock_mhz),
+		.tXP      = MAX(ctrl->tXP, 7),	/* Use a higher tXP for training */
+		.tAONPD   = get_tAONPD(ctrl->mem_clock_mhz),
+		.tRDWR_sr = tRDWR_sr,
+		.tRDWR_dr = tRDWR_drdd,
+		.tRDWR_dd = tRDWR_drdd,
+	};
+}
+
+static union tc_bank_rank_d_reg make_tc_bankrank_d(struct sysinfo *ctrl, uint8_t odt_stretch)
+{
+	const uint32_t odt_rd_delay = ctrl->tAA - ctrl->tCWL;
+	if (!ctrl->lpddr) {
+		return (union tc_bank_rank_d_reg) {
+			.tAA               = ctrl->tAA,
+			.tCWL              = ctrl->tCWL,
+			.tCPDED            = 1,
+			.tPRPDEN           = 1,
+			.odt_read_delay    = odt_rd_delay,
+			.odt_read_duration = odt_stretch,
+		};
+	}
+
+	/* tCWL has 1 extra clock because of tDQSS, subtract it here */
+	const uint32_t tCWL_lpddr = ctrl->tCWL - 1;
+	const uint32_t odt_wr_delay = tCWL_lpddr + DIV_ROUND_UP(3500, ctrl->qclkps * 2);
+	const uint32_t odt_wr_duration = DIV_ROUND_UP(3500 - 1750, ctrl->qclkps * 2) + 1;
+
+	return (union tc_bank_rank_d_reg) {
+		.tAA                = ctrl->tAA,
+		.tCWL               = tCWL_lpddr,
+		.tCPDED             = 2,	/* Required by JEDEC LPDDR3 spec */
+		.tPRPDEN            = 1,
+		.odt_read_delay     = odt_rd_delay,
+		.odt_read_duration  = odt_stretch,
+		.odt_write_delay    = odt_wr_delay,
+		.odt_write_duration = odt_wr_duration,
+		.odt_always_rank_0  = ctrl->lpddr_dram_odt
+	};
+}
+
+/* ZQCS period values, in (tREFI * 128) units */
+#define ZQCS_PERIOD_DDR3	128	/* tREFI * 128 = 7.8 us * 128 = 1ms */
+#define ZQCS_PERIOD_LPDDR3	256	/* tREFI * 128 = 3.9 us * 128 = 0.5ms */
+
+static uint32_t make_tc_zqcal(const struct sysinfo *const ctrl)
+{
+	const uint32_t zqcs_period = ctrl->lpddr ? ZQCS_PERIOD_LPDDR3 : ZQCS_PERIOD_DDR3;
+	const uint32_t tZQCS = get_tZQCS(ctrl->mem_clock_mhz, ctrl->lpddr);
+	return tZQCS << (is_hsw_ult() ? 10 : 8) | zqcs_period;
+}
+
+static union tc_rftp_reg make_tc_rftp(const struct sysinfo *const ctrl)
+{
+	/*
+	 * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow
+	 * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024.
+	 */
+	return (union tc_rftp_reg) {
+		.tREFI   = ctrl->tREFI,
+		.tRFC    = ctrl->tRFC,
+		.tREFIx9 = ctrl->tREFI * 89 / 10240,
+	};
+}
+
+static union tc_srftp_reg make_tc_srftp(const struct sysinfo *const ctrl)
+{
+	return (union tc_srftp_reg) {
+		.tXSDLL     = tDLLK,
+		.tXS_offset = get_tXS_offset(ctrl->mem_clock_mhz),
+		.tZQOPER    = get_tZQOPER(ctrl->mem_clock_mhz, ctrl->lpddr),
+		.tMOD       = get_tMOD(ctrl->mem_clock_mhz) - 8,
+	};
+}
+
+ void configure_timings(struct sysinfo *ctrl)
+ {
+-	/** TODO: Stub **/
+	if (ctrl->lpddr)
+		die("%s: Missing support for LPDDR\n", __func__);
+
+	const uint8_t odt_stretch = get_odt_stretch(ctrl);
+	const union tc_bank_reg tc_bank = make_tc_bank(ctrl);
+	const union tc_bank_rank_a_reg tc_bank_rank_a = make_tc_bankrank_a(ctrl, odt_stretch);
+	const union tc_bank_rank_b_reg tc_bank_rank_b = make_tc_bankrank_b(ctrl);
+	const union tc_bank_rank_c_reg tc_bank_rank_c = make_tc_bankrank_c(ctrl, odt_stretch);
+	const union tc_bank_rank_d_reg tc_bank_rank_d = make_tc_bankrank_d(ctrl, odt_stretch);
+
+	const uint8_t wr_delay = tc_bank_rank_b.dec_wrd + 1;
+	uint8_t sc_wr_add_delay = 0;
+	sc_wr_add_delay |= wr_delay << 0;
+	sc_wr_add_delay |= wr_delay << 2;
+	sc_wr_add_delay |= wr_delay << 4;
+	sc_wr_add_delay |= wr_delay << 6;
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		ctrl->tc_bank[channel] = tc_bank;
+		ctrl->tc_bankrank_a[channel] = tc_bank_rank_a;
+		ctrl->tc_bankrank_b[channel] = tc_bank_rank_b;
+		ctrl->tc_bankrank_c[channel] = tc_bank_rank_c;
+		ctrl->tc_bankrank_d[channel] = tc_bank_rank_d;
+
+		mchbar_write32(TC_BANK_ch(channel), ctrl->tc_bank[channel].raw);
+		mchbar_write32(TC_BANK_RANK_A_ch(channel), ctrl->tc_bankrank_a[channel].raw);
+		mchbar_write32(TC_BANK_RANK_B_ch(channel), ctrl->tc_bankrank_b[channel].raw);
+		mchbar_write32(TC_BANK_RANK_C_ch(channel), ctrl->tc_bankrank_c[channel].raw);
+		mchbar_write32(TC_BANK_RANK_D_ch(channel), ctrl->tc_bankrank_d[channel].raw);
+		mchbar_write8(SC_WR_ADD_DELAY_ch(channel), sc_wr_add_delay);
+	}
+ }
+ 
+ void configure_refresh(struct sysinfo *ctrl)
+ {
+-	/** TODO: Stub **/
+	const union tc_srftp_reg tc_srftp = make_tc_srftp(ctrl);
+	const union tc_rftp_reg  tc_rftp  = make_tc_rftp(ctrl);
+	const uint32_t tc_zqcal = make_tc_zqcal(ctrl);
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		mchbar_setbits32(TC_RFP_ch(channel), 0xff);
+		mchbar_write32(TC_RFTP_ch(channel),  tc_rftp.raw);
+		mchbar_write32(TC_SRFTP_ch(channel), tc_srftp.raw);
+		mchbar_write32(TC_ZQCAL_ch(channel), tc_zqcal);
+	}
+ }
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index 4c3f399b5d..2acc5cbbc8 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -86,9 +86,21 @@
+ #define DDR_COMP_VSSHI_CONTROL			0x3a24
+ 
+ /* MCMAIN per-channel */
+#define TC_BANK_ch(ch)				_MCMAIN_C(0x4000, ch)
+#define TC_BANK_RANK_A_ch(ch)			_MCMAIN_C(0x4004, ch)
+#define TC_BANK_RANK_B_ch(ch)			_MCMAIN_C(0x4008, ch)
+#define TC_BANK_RANK_C_ch(ch)			_MCMAIN_C(0x400c, ch)
+ #define COMMAND_RATE_LIMIT_ch(ch)		_MCMAIN_C(0x4010, ch)
+#define TC_BANK_RANK_D_ch(ch)			_MCMAIN_C(0x4014, ch)
+#define SC_ROUNDT_LAT_ch(ch)			_MCMAIN_C(0x4024, ch)
+ 
+#define SC_WR_ADD_DELAY_ch(ch)			_MCMAIN_C(0x40d0, ch)
+
+#define TC_ZQCAL_ch(ch)				_MCMAIN_C(0x4290, ch)
+#define TC_RFP_ch(ch)				_MCMAIN_C(0x4294, ch)
+#define TC_RFTP_ch(ch)				_MCMAIN_C(0x4298, ch)
+ #define MC_INIT_STATE_ch(ch)			_MCMAIN_C(0x42a0, ch)
+#define TC_SRFTP_ch(ch)				_MCMAIN_C(0x42a4, ch)
+ 
+ /* MCMAIN broadcast */
+ #define MCSCHEDS_CBIT		0x4c20
+-- 
+2.39.2
+
@@ -1,51 +0,0 @@
-From 22076426d1de6d2e49b8728b3cf206bfcfc6742d Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Tue, 23 Dec 2025 18:41:27 +0100
-Subject: [PATCH 1/2] mb/dell/optiplex_780: use legacy HDA verb table
-
-See:
-
-commit 31fc5b06a6be62b30739d33eeabe6c2727679bb1
-Author: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
-Date:   Thu Aug 7 08:31:24 2025 +0900
-
-    device: Introduce reworked azalia verb table
-
-and:
-
-commit 50a59d4464917503847eeeb2df4320c35cf2f6cc
-Author: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
-Date:   Mon Sep 15 16:25:21 2025 +0900
-
-    device: Add Kconfig to prepare for reworked verb table implementation
-
-Without this change, lbmk gets the following error
-when building for Dell OptiPlex 780:
-
-i386-elf-ld.bfd: build/ramstage/device/azalia_device.o: in function `azalia_codecs_init':
-/path/to/corebootclone/src/device/azalia_device.c:318:(.text.azalia_codecs_init+0xa): undefined reference to `mainboard_azalia_codecs'
-
-This is a temporary fix. Upstream will require that the code
-be fully adapted at a future date. Therefore, one could consider
-the current functionality to be "deprecated".
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/mainboard/dell/optiplex_780/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
-index fc649e35d5..172bb2fa87 100644
--- a/src/mainboard/dell/optiplex_780/Kconfig
-+++ b/src/mainboard/dell/optiplex_780/Kconfig
-@@ -2,6 +2,7 @@
- 
- config BOARD_DELL_OPTIPLEX_780_COMMON
- 	def_bool n
-+	select AZALIA_USE_LEGACY_VERB_TABLE
- 	select BOARD_ROMSIZE_KB_8192
- 	select CPU_INTEL_SOCKET_LGA775
- 	select DRIVERS_I2C_CK505
-- 
-2.47.3
-
@@ -0,0 +1,263 @@
+From 406e474c7f9f83dc10c7c0fa7cd9765ae822ad4e Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sat, 7 May 2022 21:24:50 +0200
+Subject: [PATCH 05/17] haswell NRI: Program memory map
+
+This is very similar to Sandy/Ivy Bridge, except that there's several
+registers to program in GDXCBAR. One of these GDXCBAR registers has a
+lock bit that must be set in order for the memory controller to allow
+normal access to DRAM. And it took me four months to realize this one
+bit was the only reason why native raminit did not work.
+
+Change-Id: I3af73a018a7ba948701a542e661e7fefd57591fe
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../intel/haswell/native_raminit/memory_map.c | 183 ++++++++++++++++++
+ .../haswell/native_raminit/raminit_main.c     |   1 +
+ .../haswell/native_raminit/raminit_native.h   |   1 +
+ .../intel/haswell/registers/host_bridge.h     |   2 +
+ 5 files changed, 188 insertions(+)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/memory_map.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index fc55277a65..37d527e972 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -4,6 +4,7 @@ romstage-y += configure_mc.c
+ romstage-y += lookup_timings.c
+ romstage-y += init_mpll.c
+ romstage-y += io_comp_control.c
+romstage-y += memory_map.c
+ romstage-y += raminit_main.c
+ romstage-y += raminit_native.c
+ romstage-y += spd_bitmunching.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/memory_map.c b/src/northbridge/intel/haswell/native_raminit/memory_map.c
+new file mode 100644
+index 0000000000..e3aded2b37
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/memory_map.c
+@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <southbridge/intel/lynxpoint/me.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+/* GDXCBAR */
+#define MPCOHTRK_GDXC_MOT_ADDRESS_LO		0x10
+#define MPCOHTRK_GDXC_MOT_ADDRESS_HI		0x14
+#define MPCOHTRK_GDXC_MOT_REGION		0x18
+
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_LO		0x20
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_HI		0x24
+#define MPCOHTRK_GDXC_OCLA_REGION		0x28
+
+/* This lock bit made me lose what little sanity I had left. - Angel Pons */
+#define MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK	BIT(2)
+
+static inline uint32_t gdxcbar_read32(const uintptr_t offset)
+{
+	return read32p((mchbar_read32(GDXCBAR) & ~1) + offset);
+}
+
+static inline void gdxcbar_write32(const uintptr_t offset, const uint32_t value)
+{
+	write32p((mchbar_read32(GDXCBAR) & ~1) + offset, value);
+}
+
+static inline void gdxcbar_clrsetbits32(const uintptr_t offset, uint32_t clear, uint32_t set)
+{
+	const uintptr_t address = (mchbar_read32(GDXCBAR) & ~1) + offset;
+	clrsetbits32((void *)address, clear, set);
+}
+
+#define gdxcbar_setbits32(offset, set)		gdxcbar_clrsetbits32(offset, 0, set)
+#define gdxcbar_clrbits32(offset, clear)	gdxcbar_clrsetbits32(offset, clear, 0)
+
+/* All values stored in here (except the bool) are specified in MiB */
+struct memory_map_data {
+	uint32_t dpr_size;
+	uint32_t tseg_size;
+	uint32_t gtt_size;
+	uint32_t gms_size;
+	uint32_t me_stolen_size;
+	uint32_t mmio_size;
+	uint32_t touud;
+	uint32_t remaplimit;
+	uint32_t remapbase;
+	uint32_t tom;
+	uint32_t tom_minus_me;
+	uint32_t tolud;
+	uint32_t bdsm_base;
+	uint32_t gtt_base;
+	uint32_t tseg_base;
+	bool reclaim_possible;
+};
+
+static void compute_memory_map(struct memory_map_data *map)
+{
+	map->tom_minus_me = map->tom - map->me_stolen_size;
+
+	/*
+	 * MMIO size will actually be slightly smaller than computed,
+	 * but matches what MRC does and is more MTRR-friendly given
+	 * that TSEG is treated as WB, but SMRR makes TSEG UC anyway.
+	 */
+	const uint32_t mmio_size = MIN(map->tom_minus_me, 4096) / 2;
+	map->gtt_base = ALIGN_DOWN(mmio_size, map->tseg_size);
+	map->tseg_base = map->gtt_base - map->tseg_size;
+	map->bdsm_base = map->gtt_base + map->gtt_size;
+	map->tolud = map->bdsm_base + map->gms_size;
+	map->reclaim_possible = map->tom_minus_me > map->tolud;
+
+	if (map->reclaim_possible) {
+		map->remapbase  = MAX(4096, map->tom_minus_me);
+		map->touud      = MIN(4096, map->tom_minus_me) + map->remapbase - map->tolud;
+		map->remaplimit = map->touud - 1;
+	} else {
+		map->remapbase  = 0;
+		map->remaplimit = 0;
+		map->touud = map->tom_minus_me;
+	}
+}
+
+static void display_memory_map(const struct memory_map_data *map)
+{
+	if (!CONFIG(DEBUG_RAM_SETUP))
+		return;
+
+	printk(BIOS_DEBUG, "============ MEMORY MAP ============\n");
+	printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "dpr_size       = %u MiB\n", map->dpr_size);
+	printk(BIOS_DEBUG, "tseg_size      = %u MiB\n", map->tseg_size);
+	printk(BIOS_DEBUG, "gtt_size       = %u MiB\n", map->gtt_size);
+	printk(BIOS_DEBUG, "gms_size       = %u MiB\n", map->gms_size);
+	printk(BIOS_DEBUG, "me_stolen_size = %u MiB\n", map->me_stolen_size);
+	printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "touud          = %u MiB\n", map->touud);
+	printk(BIOS_DEBUG, "remaplimit     = %u MiB\n", map->remaplimit);
+	printk(BIOS_DEBUG, "remapbase      = %u MiB\n", map->remapbase);
+	printk(BIOS_DEBUG, "tom            = %u MiB\n", map->tom);
+	printk(BIOS_DEBUG, "tom_minus_me   = %u MiB\n", map->tom_minus_me);
+	printk(BIOS_DEBUG, "tolud          = %u MiB\n", map->tolud);
+	printk(BIOS_DEBUG, "bdsm_base      = %u MiB\n", map->bdsm_base);
+	printk(BIOS_DEBUG, "gtt_base       = %u MiB\n", map->gtt_base);
+	printk(BIOS_DEBUG, "tseg_base      = %u MiB\n", map->tseg_base);
+	printk(BIOS_DEBUG, "\n");
+	printk(BIOS_DEBUG, "reclaim_possible = %s\n", map->reclaim_possible ? "Yes" : "No");
+}
+
+static void map_write_reg64(const uint16_t reg, const uint64_t size)
+{
+	const uint64_t value = size << 20;
+	pci_write_config32(HOST_BRIDGE, reg + 4, value >> 32);
+	pci_write_config32(HOST_BRIDGE, reg + 0, value >>  0);
+}
+
+static void map_write_reg32(const uint16_t reg, const uint32_t size)
+{
+	const uint32_t value = size << 20;
+	pci_write_config32(HOST_BRIDGE, reg, value);
+}
+
+static void program_memory_map(const struct memory_map_data *map)
+{
+	map_write_reg64(TOUUD, map->touud);
+	map_write_reg64(TOM,   map->tom);
+	if (map->reclaim_possible) {
+		map_write_reg64(REMAPBASE,  map->remapbase);
+		map_write_reg64(REMAPLIMIT, map->remaplimit);
+	}
+	if (map->me_stolen_size) {
+		map_write_reg64(MESEG_LIMIT, 0x80000 - map->me_stolen_size);
+		map_write_reg64(MESEG_BASE, map->tom_minus_me);
+		pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, ME_STLEN_EN);
+	}
+	map_write_reg32(TOLUD, map->tolud);
+	map_write_reg32(BDSM,  map->bdsm_base);
+	map_write_reg32(BGSM,  map->gtt_base);
+	map_write_reg32(TSEG,  map->tseg_base);
+
+	const uint32_t dpr_reg = map->tseg_base << 20 | map->dpr_size << 4;
+	pci_write_config32(HOST_BRIDGE, DPR, dpr_reg);
+
+	const uint16_t gfx_stolen_size = GGC_IGD_MEM_IN_32MB_UNITS(map->gms_size / 32);
+	const uint16_t ggc = map->gtt_size << 8 | gfx_stolen_size;
+	pci_write_config16(HOST_BRIDGE, GGC, ggc);
+
+	/** TODO: Do not hardcode these? GDXC has weird alignment requirements, though. **/
+	gdxcbar_write32(MPCOHTRK_GDXC_MOT_ADDRESS_LO, 0);
+	gdxcbar_write32(MPCOHTRK_GDXC_MOT_ADDRESS_HI, 0);
+	gdxcbar_write32(MPCOHTRK_GDXC_MOT_REGION, 0);
+
+	gdxcbar_write32(MPCOHTRK_GDXC_OCLA_ADDRESS_LO, 0);
+	gdxcbar_write32(MPCOHTRK_GDXC_OCLA_ADDRESS_HI, 0);
+	gdxcbar_write32(MPCOHTRK_GDXC_OCLA_REGION, 0);
+
+	gdxcbar_setbits32(MPCOHTRK_GDXC_OCLA_ADDRESS_HI, MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK);
+}
+
+enum raminit_status configure_memory_map(struct sysinfo *ctrl)
+{
+	struct memory_map_data memory_map = {
+		.tom            = ctrl->channel_size_mb[0] + ctrl->channel_size_mb[1],
+		.dpr_size       = CONFIG_INTEL_TXT_DPR_SIZE,
+		.tseg_size      = CONFIG_SMM_TSEG_SIZE >> 20,
+		.me_stolen_size = intel_early_me_uma_size(),
+	};
+	/** FIXME: MRC hardcodes iGPU parameters, but we should not **/
+	const bool igpu_on = pci_read_config32(HOST_BRIDGE, DEVEN) & DEVEN_D2EN;
+	if (CONFIG(ONBOARD_VGA_IS_PRIMARY) || igpu_on) {
+		memory_map.gtt_size = 2;
+		memory_map.gms_size = 64;
+		pci_or_config32(HOST_BRIDGE, DEVEN, DEVEN_D2EN);
+	}
+	compute_memory_map(&memory_map);
+	display_memory_map(&memory_map);
+	program_memory_map(&memory_map);
+	return 0;
+}
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index fcc981ad04..559dfc3a4e 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -23,6 +23,7 @@ static const struct task_entry cold_boot[] = {
+ 	{ initialise_mpll,                                        true, "INITMPLL",   },
+ 	{ convert_timings,                                        true, "CONVTIM",    },
+ 	{ configure_mc,                                           true, "CONFMC",     },
+	{ configure_memory_map,                                   true, "MEMMAP",     },
+ };
+ 
+ /* Return a generic stepping value to make stepping checks simpler */
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 5915a2bab0..8f937c4ccd 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -203,6 +203,7 @@ enum raminit_status collect_spd_info(struct sysinfo *ctrl);
+ enum raminit_status initialise_mpll(struct sysinfo *ctrl);
+ enum raminit_status convert_timings(struct sysinfo *ctrl);
+ enum raminit_status configure_mc(struct sysinfo *ctrl);
+enum raminit_status configure_memory_map(struct sysinfo *ctrl);
+ 
+ void configure_timings(struct sysinfo *ctrl);
+ void configure_refresh(struct sysinfo *ctrl);
+diff --git a/src/northbridge/intel/haswell/registers/host_bridge.h b/src/northbridge/intel/haswell/registers/host_bridge.h
+index 1ee0ab2890..0228cf6bb9 100644
+--- a/src/northbridge/intel/haswell/registers/host_bridge.h
+++ b/src/northbridge/intel/haswell/registers/host_bridge.h
+@@ -34,6 +34,8 @@
+ 
+ #define MESEG_BASE	0x70	/* Management Engine Base */
+ #define MESEG_LIMIT	0x78	/* Management Engine Limit */
+#define  MELCK		(1 << 10)	/* ME Range Lock */
+#define  ME_STLEN_EN	(1 << 11)	/* ME Stolen Memory Enable */
+ 
+ #define PAM0		0x80
+ #define PAM1		0x81
+-- 
+2.39.2
+
@@ -1,30 +0,0 @@
-From 6cea443cf12eb94b3eafcbba4ce6370b31f716cc Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Tue, 23 Dec 2025 18:46:45 +0100
-Subject: [PATCH 2/2] hp8300cmt: use legacy verb table
-
-same as for the 780 optiplex patch
-
-coreboot is making some changes to the way verbs are
-handled. for now, this change is being made to adapt.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/mainboard/hp/compaq_elite_8300_cmt/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
-index d2bfd35dc4..30be7fb3fe 100644
--- a/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
-@@ -2,6 +2,7 @@ if BOARD_HP_COMPAQ_ELITE_8300_CMT
- 
- config BOARD_SPECIFIC_OPTIONS
- 	def_bool y
-+	select AZALIA_USE_LEGACY_VERB_TABLE
- 	select BOARD_ROMSIZE_KB_16384
- 	select HAVE_ACPI_RESUME
- 	select HAVE_ACPI_TABLES
-- 
-2.47.3
-
@@ -1,34 +0,0 @@
-From 3bb05d0486186400df8ed9ac66cfadcbff7a48a6 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Tue, 6 Jan 2026 21:42:21 +0000
-Subject: [PATCH 1/1] topton x2e n150: use old fsp
-
-i added the old fsp back, so that we didn't have to
-mess around with vendor files in lbmk, because coreboot
-upstream updated the fsp repo, which modified this
-fsp file.
-
-we know the old fsp worked. there's no point testing
-the new one yet, unless someone can tell me about
-real bugs that got fixed.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
---
- src/soc/intel/alderlake/Kconfig | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
-index e9c56fc6b9..43cd6f8efe 100644
--- a/src/soc/intel/alderlake/Kconfig
-+++ b/src/soc/intel/alderlake/Kconfig
-@@ -438,6 +438,7 @@ config FSP_FD_PATH
- 	default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd"   if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S
- 	default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd"     if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P
- 	default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd"     if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S
-+	default "3rdparty/fspcc36ae2b5775fa7400cb3282680afc0f6cb37a3c/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if BOARD_TOPTON_X2E_N150
- 	default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd"     if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N
- 	default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P
- 	default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S
-- 
-2.47.3
-
@@ -0,0 +1,392 @@
+From 19890277e3a0d411b016efbe1b54e511d4f36c0d Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sat, 7 May 2022 23:12:18 +0200
+Subject: [PATCH 07/17] haswell NRI: Add pre-training steps
+
+Implement pre-training steps, which consist of enabling ECC I/O and
+filling the WDB (Write Data Buffer, stores test patterns) through a
+magic LDAT port.
+
+Change-Id: Ie2e09e3b218c4569ed8de5c5e1b05d491032e0f1
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/raminit_main.c     |  35 ++++
+ .../haswell/native_raminit/raminit_native.h   |  24 +++
+ .../haswell/native_raminit/reg_structs.h      |  45 +++++
+ .../intel/haswell/native_raminit/setup_wdb.c  | 159 ++++++++++++++++++
+ .../intel/haswell/registers/mchbar.h          |   9 +
+ 6 files changed, 273 insertions(+)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/setup_wdb.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index e9212df9e6..8d7d4e4db0 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -10,5 +10,6 @@ romstage-y += memory_map.c
+ romstage-y += raminit_main.c
+ romstage-y += raminit_native.c
+ romstage-y += reut.c
+romstage-y += setup_wdb.c
+ romstage-y += spd_bitmunching.c
+ romstage-y += timings_refresh.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index 94b268468c..5e4674957d 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -3,6 +3,7 @@
+ #include <assert.h>
+ #include <console/console.h>
+ #include <cpu/intel/haswell/haswell.h>
+#include <delay.h>
+ #include <device/pci_ops.h>
+ #include <northbridge/intel/haswell/chip.h>
+ #include <northbridge/intel/haswell/haswell.h>
+@@ -12,6 +13,39 @@
+ 
+ #include "raminit_native.h"
+ 
+static enum raminit_status pre_training(struct sysinfo *ctrl)
+{
+	/* Skip on S3 resume */
+	if (ctrl->bootmode == BOOTMODE_S3)
+		return RAMINIT_STATUS_SUCCESS;
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
+			if (!rank_in_ch(ctrl, slot + slot, channel))
+				continue;
+
+			printk(RAM_DEBUG, "C%uS%u:\n", channel, slot);
+			printk(RAM_DEBUG, "\tMR0: 0x%04x\n", ctrl->mr0[channel][slot]);
+			printk(RAM_DEBUG, "\tMR1: 0x%04x\n", ctrl->mr1[channel][slot]);
+			printk(RAM_DEBUG, "\tMR2: 0x%04x\n", ctrl->mr2[channel][slot]);
+			printk(RAM_DEBUG, "\tMR3: 0x%04x\n", ctrl->mr3[channel][slot]);
+			printk(RAM_DEBUG, "\n");
+		}
+		if (ctrl->is_ecc) {
+			union mad_dimm_reg mad_dimm = {
+				.raw = mchbar_read32(MAD_DIMM(channel)),
+			};
+			/* Enable ECC I/O */
+			mad_dimm.ecc_mode = 1;
+			mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
+			/* Wait 4 usec after enabling the ECC I/O, needed by HW */
+			udelay(4);
+		}
+	}
+	setup_wdb(ctrl);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+ struct task_entry {
+ 	enum raminit_status (*task)(struct sysinfo *);
+ 	bool is_enabled;
+@@ -25,6 +59,7 @@ static const struct task_entry cold_boot[] = {
+ 	{ configure_mc,                                           true, "CONFMC",     },
+ 	{ configure_memory_map,                                   true, "MEMMAP",     },
+ 	{ do_jedec_init,                                          true, "JEDECINIT",  },
+	{ pre_training,                                           true, "PRETRAIN",   },
+ };
+ 
+ /* Return a generic stepping value to make stepping checks simpler */
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 759d755d6d..4d9487d79c 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -36,6 +36,13 @@
+ 
+ #define RTTNOM_MASK		(BIT(9) | BIT(6) | BIT(2))
+ 
+#define BASIC_VA_PAT_SPREAD_8	0x01010101
+
+#define WDB_CACHE_LINE_SIZE	8
+
+#define NUM_WDB_CL_MUX_SEEDS	3
+#define NUM_CADB_MUX_SEEDS	3
+
+ /* ZQ calibration types */
+ enum {
+ 	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
+@@ -317,6 +324,23 @@ void reut_issue_mrs_all(
+ 
+ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_t zq_type);
+ 
+void write_wdb_fixed_pat(
+	const struct sysinfo *ctrl,
+	const uint8_t patterns[],
+	const uint8_t pat_mask[],
+	uint8_t spread,
+	uint16_t start);
+
+void write_wdb_va_pat(
+	const struct sysinfo *ctrl,
+	uint32_t agg_mask,
+	uint32_t vic_mask,
+	uint8_t vic_rot,
+	uint16_t start);
+
+void program_wdb_lfsr(const struct sysinfo *ctrl, bool cleanup);
+void setup_wdb(const struct sysinfo *ctrl);
+
+ uint8_t get_rx_bias(const struct sysinfo *ctrl);
+ 
+ uint8_t get_tCWL(uint32_t mem_clock_mhz);
+diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+index 9929f617fe..7aa8d8c8b2 100644
+--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+@@ -335,6 +335,18 @@ union mcscheds_cbit_reg {
+ 	uint32_t raw;
+ };
+ 
+union reut_pat_cl_mux_lmn_reg {
+	struct __packed {
+		uint32_t l_data_select : 1; // Bits  0:0
+		uint32_t en_sweep_freq : 1; // Bits  1:1
+		uint32_t               : 6; // Bits  7:2
+		uint32_t l_counter     : 8; // Bits 15:8
+		uint32_t m_counter     : 8; // Bits 23:16
+		uint32_t n_counter     : 8; // Bits 31:24
+	};
+	uint32_t raw;
+};
+
+ union reut_pat_cadb_prog_reg {
+ 	struct __packed {
+ 		uint32_t addr : 16; // Bits 15:0
+@@ -439,6 +451,39 @@ union reut_misc_odt_ctrl_reg {
+ 	uint32_t raw;
+ };
+ 
+union ldat_pdat_reg {
+	struct __packed {
+		uint32_t fast_addr : 12; // Bits 11:0
+		uint32_t           :  4; // Bits 15:12
+		uint32_t addr_en   :  1; // Bits 16:16
+		uint32_t seq_en    :  1; // Bits 17:17
+		uint32_t pol_0     :  1; // Bits 18:18
+		uint32_t pol_1     :  1; // Bits 19:19
+		uint32_t cmd_a     :  4; // Bits 23:20
+		uint32_t cmd_b     :  4; // Bits 27:24
+		uint32_t cmd_c     :  4; // Bits 31:28
+	};
+	uint32_t raw;
+};
+
+union ldat_sdat_reg {
+	struct __packed {
+		uint32_t bank_sel   : 4; // Bits  3:0
+		uint32_t            : 1; // Bits  4:4
+		uint32_t array_sel  : 5; // Bits  9:5
+		uint32_t cmp        : 1; // Bits 10:10
+		uint32_t replicate  : 1; // Bits 11:11
+		uint32_t dword      : 4; // Bits 15:12
+		uint32_t mode       : 2; // Bits 17:16
+		uint32_t mpmap      : 6; // Bits 23:18
+		uint32_t mpb_offset : 4; // Bits 27:24
+		uint32_t stage_en   : 1; // Bits 28:28
+		uint32_t shadow     : 2; // Bits 30:29
+		uint32_t            : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+ union mcscheds_dft_misc_reg {
+ 	struct __packed {
+ 		uint32_t wdar                 :  1; // Bits  0:0
+diff --git a/src/northbridge/intel/haswell/native_raminit/setup_wdb.c b/src/northbridge/intel/haswell/native_raminit/setup_wdb.c
+new file mode 100644
+index 0000000000..ec37c48415
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/setup_wdb.c
+@@ -0,0 +1,159 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static void ldat_write_cacheline(
+	const struct sysinfo *const ctrl,
+	const uint8_t chunk,
+	const uint16_t start,
+	const uint64_t data)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		/*
+		 * Do not do a 64-bit write here. The register is not aligned
+		 * to a 64-bit boundary, which could potentially cause issues.
+		 */
+		mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 0), data & UINT32_MAX);
+		mchbar_write32(QCLK_ch_LDAT_DATA_IN_x(channel, 1), data >> 32);
+		/*
+		 * Set REPLICATE = 0 as you don't want to replicate the data.
+		 * Set BANK_SEL to the chunk you want to write the 64 bits to.
+		 * Set ARRAY_SEL = 0 (the MC WDB) and MODE = 1.
+		 */
+		const union ldat_sdat_reg ldat_sdat = {
+			.bank_sel = chunk,
+			.mode     = 1,
+		};
+		mchbar_write32(QCLK_ch_LDAT_SDAT(channel), ldat_sdat.raw);
+		/*
+		 * Finally, write the PDAT register indicating which cacheline
+		 * of the WDB you want to write to by setting FAST_ADDR field
+		 * to one of the 64 cache lines. Also set CMD_B in the PDAT
+		 * register to 4'b1000, indicating that this is a LDAT write.
+		 */
+		const union ldat_pdat_reg ldat_pdat = {
+			.fast_addr = MIN(start, 0xfff),
+			.cmd_b     = 8,
+		};
+		mchbar_write32(QCLK_ch_LDAT_PDAT(channel), ldat_pdat.raw);
+	}
+}
+
+static void clear_ldat_mode(const struct sysinfo *const ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
+		mchbar_write32(QCLK_ch_LDAT_SDAT(channel), 0);
+}
+
+void write_wdb_fixed_pat(
+	const struct sysinfo *const ctrl,
+	const uint8_t patterns[],
+	const uint8_t pat_mask[],
+	const uint8_t spread,
+	const uint16_t start)
+{
+	for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
+		uint64_t data = 0;
+		for (uint8_t b = 0; b < 64; b++) {
+			const uint8_t beff  = b % spread;
+			const uint8_t burst = patterns[pat_mask[beff]];
+			if (burst & BIT(chunk))
+				data |= 1ULL << b;
+		}
+		ldat_write_cacheline(ctrl, chunk, start, data);
+	}
+	clear_ldat_mode(ctrl);
+}
+
+static inline uint32_t rol_u32(const uint32_t val)
+{
+	return (val << 1) | ((val >> 31) & 1);
+}
+
+void write_wdb_va_pat(
+	const struct sysinfo *const ctrl,
+	const uint32_t agg_mask,
+	const uint32_t vic_mask,
+	const uint8_t vic_rot,
+	const uint16_t start)
+{
+	static const uint8_t va_mask_to_compressed[4] = {0xaa, 0xc0, 0xcc, 0xf0};
+	uint32_t v_mask = vic_mask;
+	uint32_t a_mask = agg_mask;
+	for (uint8_t v = 0; v < vic_rot; v++) {
+		uint8_t compressed[32] = {0};
+		/* Iterate through all 32 bits and create a compressed version of cacheline */
+		for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++) {
+			const uint8_t vic = !!(v_mask & BIT(b));
+			const uint8_t agg = !!(a_mask & BIT(b));
+			const uint8_t index = !vic << 1 | agg << 0;
+			compressed[b] = va_mask_to_compressed[index];
+		}
+		for (uint8_t chunk = 0; chunk < WDB_CACHE_LINE_SIZE; chunk++) {
+			uint32_t data = 0;
+			for (uint8_t b = 0; b < ARRAY_SIZE(compressed); b++)
+				data |= !!(compressed[b] & BIT(chunk)) << b;
+
+			const uint64_t data64 = (uint64_t)data << 32 | data;
+			ldat_write_cacheline(ctrl, chunk, start + v, data64);
+		}
+		v_mask = rol_u32(v_mask);
+		a_mask = rol_u32(a_mask);
+	}
+	clear_ldat_mode(ctrl);
+}
+
+void program_wdb_lfsr(const struct sysinfo *ctrl, const bool cleanup)
+{
+	/* Cleanup LFSR seeds are sequential */
+	const uint32_t cleanup_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xaaaaaa, 0xcccccc, 0xf0f0f0 };
+	const uint32_t regular_seeds[NUM_WDB_CL_MUX_SEEDS] = { 0xa10ca1, 0xef0d08, 0xad0a1e };
+	const uint32_t *seeds = cleanup ? cleanup_seeds : regular_seeds;
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t i = 0; i < NUM_WDB_CL_MUX_SEEDS; i++) {
+			mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_RD_x(channel, i), seeds[i]);
+			mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_WR_x(channel, i), seeds[i]);
+		}
+	}
+}
+
+void setup_wdb(const struct sysinfo *ctrl)
+{
+	const uint32_t amask[9] = {
+		0x86186186, 0x18618618, 0x30c30c30,
+		0xa28a28a2, 0x8a28a28a, 0x14514514,
+		0x28a28a28, 0x92492492, 0x24924924,
+	};
+	const uint32_t vmask = 0x41041041;
+
+	/* Fill first 8 entries with simple 2-LFSR VA pattern */
+	write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
+
+	/* Fill next 54 entries with 3-LFSR VA pattern */
+	for (uint8_t a = 0; a < ARRAY_SIZE(amask); a++)
+		write_wdb_va_pat(ctrl, amask[a], vmask, 6, 8 + a * 6);
+
+	program_wdb_lfsr(ctrl, false);
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		const union reut_pat_cl_mux_lmn_reg wdb_cl_mux_lmn = {
+			.en_sweep_freq = 1,
+			.l_counter     = 1,
+			.m_counter     = 1,
+			.n_counter     = 10,
+		};
+		mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_LMN(channel), wdb_cl_mux_lmn.raw);
+	}
+}
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index 4fc78a7f43..f8408e51a0 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -94,6 +94,11 @@
+ #define TC_BANK_RANK_D_ch(ch)			_MCMAIN_C(0x4014, ch)
+ #define SC_ROUNDT_LAT_ch(ch)			_MCMAIN_C(0x4024, ch)
+ 
+#define REUT_ch_PAT_WDB_CL_MUX_WR_x(ch, x)	_MCMAIN_C_X(0x4048, ch, x) /* x in 0 .. 2 */
+#define REUT_ch_PAT_WDB_CL_MUX_RD_x(ch, x)	_MCMAIN_C_X(0x4054, ch, x) /* x in 0 .. 2 */
+
+#define REUT_ch_PAT_WDB_CL_MUX_LMN(ch)		_MCMAIN_C(0x4078, ch)
+
+ #define SC_WR_ADD_DELAY_ch(ch)			_MCMAIN_C(0x40d0, ch)
+ 
+ #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
+@@ -110,6 +115,10 @@
+ #define MC_INIT_STATE_ch(ch)			_MCMAIN_C(0x42a0, ch)
+ #define TC_SRFTP_ch(ch)				_MCMAIN_C(0x42a4, ch)
+ 
+#define QCLK_ch_LDAT_PDAT(ch)			_MCMAIN_C(0x42d0, ch)
+#define QCLK_ch_LDAT_SDAT(ch)			_MCMAIN_C(0x42d4, ch)
+#define QCLK_ch_LDAT_DATA_IN_x(ch, x)		_MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
+
+ #define REUT_GLOBAL_ERR				0x4804
+ 
+ #define REUT_ch_SEQ_CFG(ch)			(0x48a8 + 8 * (ch))
+-- 
+2.39.2
+
@@ -1,31 +0,0 @@
-From 6c6b7a71bfb36f9639abe72066851de22aa4f1ca Mon Sep 17 00:00:00 2001
-From: Ron Nazarov <ron@noisytoot.org>
-Date: Sat, 14 Feb 2026 20:13:01 +0000
-Subject: [PATCH] mb/supermicro/x11-lga1151-series: Disable ME HECI in
- devicetree
-
-Since we always use me_cleaner, this speeds up boot time by preventing
-coreboot from wasting a few seconds waiting for HECI.
-
-Change-Id: Ifbb16ba9f09129795dabe7861260ea4d995c0350
-Signed-off-by: Ron Nazarov <ron@noisytoot.org>
---
- src/mainboard/supermicro/x11-lga1151-series/devicetree.cb | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
-index fbf896c6ae..aa09a41f2f 100644
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
-+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
-@@ -15,7 +15,7 @@ chip soc/intel/skylake
- 		device ref sa_thermal on end
- 		device ref south_xhci on end
- 		device ref thermal on end
-		device ref heci1 on end
-+		device ref heci1 off end
- 		device ref sata on
- 			register "SataSalpSupport" = "1"
- 			register "SataPortsEnable" = "{
-- 
-2.52.0
-
@@ -0,0 +1,222 @@
+From 07970f6dc64e5563c26013d842a929734e2bf8ed Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sun, 8 May 2022 00:56:00 +0200
+Subject: [PATCH 09/17] haswell NRI: Add range tracking library
+
+Implement a small library used to keep track of passing ranges. This
+will be used by 1D training algorithms when margining some parameter.
+
+Change-Id: I8718e85165160afd7c0c8e730b5ce6c9c00f8a60
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../intel/haswell/native_raminit/ranges.c     | 109 ++++++++++++++++++
+ .../intel/haswell/native_raminit/ranges.h     |  68 +++++++++++
+ 3 files changed, 178 insertions(+)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.c
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/ranges.h
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index 6e1b365602..2da950771d 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -9,6 +9,7 @@ romstage-y += io_comp_control.c
+ romstage-y += memory_map.c
+ romstage-y += raminit_main.c
+ romstage-y += raminit_native.c
+romstage-y += ranges.c
+ romstage-y += reut.c
+ romstage-y += setup_wdb.c
+ romstage-y += spd_bitmunching.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/ranges.c b/src/northbridge/intel/haswell/native_raminit/ranges.c
+new file mode 100644
+index 0000000000..cdebc1fa66
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/ranges.c
+@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <types.h>
+
+#include "ranges.h"
+
+void linear_record_pass(
+	struct linear_train_data *const data,
+	const bool pass,
+	const int32_t value,
+	const int32_t start,
+	const int32_t step)
+{
+	/* If this is the first time, initialize all values */
+	if (value == start) {
+		/*
+		 * If value passed, create a zero-length region for the current value,
+		 * which may be extended as long as the successive values are passing.
+		 *
+		 * Otherwise, create a zero-length range for the preceding value. This
+		 * range cannot be extended by other passing values, which is desired.
+		 */
+		data->current.start = start - (pass ? 0 : step);
+		data->current.end   = data->current.start;
+		data->largest       = data->current;
+	} else if (pass) {
+		/* If this pass is not contiguous, it belongs to a new region */
+		if (data->current.end != (value - step))
+			data->current.start = value;
+
+		/* Update end of current region */
+		data->current.end = value;
+
+		/* Update largest region */
+		if (range_width(data->current) > range_width(data->largest))
+			data->largest = data->current;
+	}
+}
+
+void phase_record_pass(
+	struct phase_train_data *const data,
+	const bool pass,
+	const int32_t value,
+	const int32_t start,
+	const int32_t step)
+{
+	/* If this is the first time, initialize all values */
+	if (value == start) {
+		/*
+		 * If value passed, create a zero-length region for the current value,
+		 * which may be extended as long as the successive values are passing.
+		 *
+		 * Otherwise, create a zero-length range for the preceding value. This
+		 * range cannot be extended by other passing values, which is desired.
+		 */
+		data->current.start = start - (pass ? 0 : step);
+		data->current.end   = data->current.start;
+		data->largest       = data->current;
+		data->initial       = data->current;
+		return;
+	}
+	if (!pass)
+		return;
+
+	/* Update initial region */
+	if (data->initial.end == (value - step))
+		data->initial.end = value;
+
+	/* If this pass is not contiguous, it belongs to a new region */
+	if (data->current.end != (value - step))
+		data->current.start = value;
+
+	/* Update end of current region */
+	data->current.end = value;
+
+	/* Update largest region */
+	if (range_width(data->current) > range_width(data->largest))
+		data->largest = data->current;
+}
+
+void phase_append_initial_to_current(
+	struct phase_train_data *const data,
+	const int32_t start,
+	const int32_t step)
+{
+	/* If initial region is valid and does not overlap, append it */
+	if (data->initial.start == start && data->initial.end != data->current.end)
+		data->current.end += step + range_width(data->initial);
+
+	/* Update largest region */
+	if (range_width(data->current) > range_width(data->largest))
+		data->largest = data->current;
+}
+
+void phase_append_current_to_initial(
+	struct phase_train_data *const data,
+	const int32_t start,
+	const int32_t step)
+{
+	/* If initial region is valid and does not overlap, append it */
+	if (data->initial.start == start && data->initial.end != data->current.end) {
+		data->initial.start -= (step + range_width(data->current));
+		data->current = data->initial;
+	}
+
+	/* Update largest region */
+	if (range_width(data->current) > range_width(data->largest))
+		data->largest = data->current;
+}
+diff --git a/src/northbridge/intel/haswell/native_raminit/ranges.h b/src/northbridge/intel/haswell/native_raminit/ranges.h
+new file mode 100644
+index 0000000000..235392df96
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/ranges.h
+@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef HASWELL_RAMINIT_RANGES_H
+#define HASWELL_RAMINIT_RANGES_H
+
+#include <types.h>
+
+/*
+ * Many algorithms shmoo some parameter to determine the largest passing
+ * range. Provide a common implementation to avoid redundant boilerplate.
+ */
+struct passing_range {
+	int32_t start;
+	int32_t end;
+};
+
+/* Structure for linear parameters, such as roundtrip delays */
+struct linear_train_data {
+	struct passing_range current;
+	struct passing_range largest;
+};
+
+/*
+ * Phase ranges are "circular": the first and last indices are contiguous.
+ * To correctly determine the largest passing range, one has to combine
+ * the initial range and the current range when processing the last index.
+ */
+struct phase_train_data {
+	struct passing_range initial;
+	struct passing_range current;
+	struct passing_range largest;
+};
+
+static inline int32_t range_width(const struct passing_range range)
+{
+	return range.end - range.start;
+}
+
+static inline int32_t range_center(const struct passing_range range)
+{
+	return range.start + range_width(range) / 2;
+}
+
+void linear_record_pass(
+	struct linear_train_data *data,
+	bool pass,
+	int32_t value,
+	int32_t start,
+	int32_t step);
+
+void phase_record_pass(
+	struct phase_train_data *data,
+	bool pass,
+	int32_t value,
+	int32_t start,
+	int32_t step);
+
+void phase_append_initial_to_current(
+	struct phase_train_data *data,
+	int32_t start,
+	int32_t step);
+
+void phase_append_current_to_initial(
+	struct phase_train_data *data,
+	int32_t start,
+	int32_t step);
+
+#endif
+-- 
+2.39.2
+
@@ -0,0 +1,294 @@
+From 66db8447d6cf724c4b25618c94d5a53d501f214e Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sun, 8 May 2022 01:11:03 +0200
+Subject: [PATCH 10/17] haswell NRI: Add library to change margins
+
+Implement a library to change Rx/Tx margins. It will be expanded later.
+
+Change-Id: I0b55aba428d8b4d4e16d2fbdec57235ce3ce8adf
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/change_margin.c    | 154 ++++++++++++++++++
+ .../haswell/native_raminit/raminit_native.h   |  50 ++++++
+ .../intel/haswell/registers/mchbar.h          |   9 +
+ 4 files changed, 214 insertions(+)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/change_margin.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index 2da950771d..ebe9e9b762 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -1,5 +1,6 @@
+ ## SPDX-License-Identifier: GPL-2.0-or-later
+ 
+romstage-y += change_margin.c
+ romstage-y += configure_mc.c
+ romstage-y += ddr3.c
+ romstage-y += jedec_reset.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
+new file mode 100644
+index 0000000000..055c666eee
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
+@@ -0,0 +1,154 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+
+#include "raminit_native.h"
+
+void update_rxt(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t rank,
+	const uint8_t byte,
+	const enum rxt_subfield subfield,
+	const int32_t value)
+{
+	union ddr_data_rx_train_rank_reg rxt = {
+		.rcven =  ctrl->rcven[channel][rank][byte],
+		.dqs_p = ctrl->rxdqsp[channel][rank][byte],
+		.rx_eq =  ctrl->rx_eq[channel][rank][byte],
+		.dqs_n = ctrl->rxdqsn[channel][rank][byte],
+		.vref  = ctrl->rxvref[channel][rank][byte],
+	};
+	int32_t new_value;
+	switch (subfield) {
+	case RXT_RCVEN:
+		new_value = clamp_s32(0, value, 511);
+		rxt.rcven = new_value;
+		break;
+	case RXT_RXDQS_P:
+		new_value = clamp_s32(0, value, 63);
+		rxt.dqs_p = new_value;
+		break;
+	case RXT_RX_EQ:
+		new_value = clamp_s32(0, value, 31);
+		rxt.rx_eq = new_value;
+		break;
+	case RXT_RXDQS_N:
+		new_value = clamp_s32(0, value, 63);
+		rxt.dqs_n = new_value;
+		break;
+	case RXT_RX_VREF:
+		new_value = clamp_s32(-32, value, 31);
+		rxt.vref = new_value;
+		break;
+	case RXT_RXDQS_BOTH:
+		new_value = clamp_s32(0, value, 63);
+		rxt.dqs_p = new_value;
+		rxt.dqs_n = new_value;
+		break;
+	case RXT_RESTORE:
+		new_value = value;
+		break;
+	default:
+		die("%s: Unhandled subfield index %u\n", __func__, subfield);
+	}
+
+	if (new_value != value) {
+		printk(BIOS_ERR, "%s: Overflow for subfield %u: %d ---> %d\n",
+			__func__, subfield, value, new_value);
+	}
+	mchbar_write32(RX_TRAIN_ch_r_b(channel, rank, byte), rxt.raw);
+	download_regfile(ctrl, channel, false, rank, REG_FILE_USE_RANK, byte, true, false);
+}
+
+void update_txt(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const uint8_t rank,
+	const uint8_t byte,
+	const enum txt_subfield subfield,
+	const int32_t value)
+{
+	union ddr_data_tx_train_rank_reg txt = {
+		.dq_delay  = ctrl->tx_dq[channel][rank][byte],
+		.dqs_delay = ctrl->txdqs[channel][rank][byte],
+		.tx_eq     = ctrl->tx_eq[channel][rank][byte],
+	};
+	int32_t new_value;
+	switch (subfield) {
+	case TXT_TX_DQ:
+		new_value = clamp_s32(0, value, 511);
+		txt.dq_delay = new_value;
+		break;
+	case TXT_TXDQS:
+		new_value = clamp_s32(0, value, 511);
+		txt.dqs_delay = new_value;
+		break;
+	case TXT_TX_EQ:
+		new_value = clamp_s32(0, value, 63);
+		txt.tx_eq = new_value;
+		break;
+	case TXT_DQDQS_OFF:
+		new_value = value;
+		txt.dqs_delay += new_value;
+		txt.dq_delay  += new_value;
+		break;
+	case TXT_RESTORE:
+		new_value = value;
+		break;
+	default:
+		die("%s: Unhandled subfield index %u\n", __func__, subfield);
+	}
+	if (new_value != value) {
+		printk(BIOS_ERR, "%s: Overflow for subfield %u: %d ---> %d\n",
+			__func__, subfield, value, new_value);
+	}
+	mchbar_write32(TX_TRAIN_ch_r_b(channel, rank, byte), txt.raw);
+	download_regfile(ctrl, channel, false, rank, REG_FILE_USE_RANK, byte, false, true);
+}
+
+void download_regfile(
+	struct sysinfo *ctrl,
+	const uint8_t channel,
+	const bool multicast,
+	const uint8_t rank,
+	const enum regfile_mode regfile,
+	const uint8_t byte,
+	const bool read_rf_rd,
+	const bool read_rf_wr)
+{
+	union reut_seq_base_addr_reg reut_seq_base_addr;
+	switch (regfile) {
+	case REG_FILE_USE_START:
+		reut_seq_base_addr.raw = mchbar_read64(REUT_ch_SEQ_ADDR_START(channel));
+		break;
+	case REG_FILE_USE_CURRENT:
+		reut_seq_base_addr.raw = mchbar_read64(REUT_ch_SEQ_ADDR_CURRENT(channel));
+		break;
+	case REG_FILE_USE_RANK:
+		reut_seq_base_addr.raw = 0;
+		if (rank >= NUM_SLOTRANKS)
+			die("%s: bad rank %u\n", __func__, rank);
+		break;
+	default:
+		die("%s: Invalid regfile param %u\n", __func__, regfile);
+	}
+	uint8_t phys_rank = rank;
+	if (reut_seq_base_addr.raw != 0) {
+		/* Map REUT logical rank to physical rank */
+		const uint32_t log_to_phys = mchbar_read32(REUT_ch_RANK_LOG_TO_PHYS(channel));
+		phys_rank = log_to_phys >> (reut_seq_base_addr.rank_addr * 4) & 0x3;
+	}
+	uint32_t reg = multicast ? DDR_DATA_ch_CONTROL_0(channel) : DQ_CONTROL_0(channel, byte);
+	union ddr_data_control_0_reg ddr_data_control_0 = {
+		.raw = mchbar_read32(reg),
+	};
+	ddr_data_control_0.read_rf_rd   = read_rf_rd;
+	ddr_data_control_0.read_rf_wr   = read_rf_wr;
+	ddr_data_control_0.read_rf_rank = phys_rank;
+	mchbar_write32(reg, ddr_data_control_0.raw);
+}
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index f029e7f076..8707257b27 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -118,6 +118,30 @@ enum test_stop {
+ 	ALSOE  = 3,	/* Stop on all lanes error */
+ };
+ 
+enum rxt_subfield {
+	RXT_RCVEN	= 0,
+	RXT_RXDQS_P	= 1,
+	RXT_RX_EQ	= 2,
+	RXT_RXDQS_N	= 3,
+	RXT_RX_VREF	= 4,
+	RXT_RXDQS_BOTH	= 5,
+	RXT_RESTORE	= 255,
+};
+
+enum txt_subfield {
+	TXT_TX_DQ	= 0,
+	TXT_TXDQS	= 1,
+	TXT_TX_EQ	= 2,
+	TXT_DQDQS_OFF	= 3,
+	TXT_RESTORE	= 255,
+};
+
+enum regfile_mode {
+	REG_FILE_USE_RANK,	/* Used when changing parameters for each rank */
+	REG_FILE_USE_START,	/* Used when changing parameters before the test */
+	REG_FILE_USE_CURRENT,	/* Used when changing parameters after the test */
+};
+
+ struct wdb_pat {
+ 	uint32_t start_ptr;	/* Starting pointer in WDB */
+ 	uint32_t stop_ptr;	/* Stopping pointer in WDB */
+@@ -451,6 +475,32 @@ uint8_t select_reut_ranks(struct sysinfo *ctrl, uint8_t channel, uint8_t rankmas
+ void run_mpr_io_test(bool clear_errors);
+ uint8_t run_io_test(struct sysinfo *ctrl, uint8_t chanmask, uint8_t dq_pat, bool clear_errors);
+ 
+void update_rxt(
+	struct sysinfo *ctrl,
+	uint8_t channel,
+	uint8_t rank,
+	uint8_t byte,
+	enum rxt_subfield subfield,
+	int32_t value);
+
+void update_txt(
+	struct sysinfo *ctrl,
+	uint8_t channel,
+	uint8_t rank,
+	uint8_t byte,
+	enum txt_subfield subfield,
+	int32_t value);
+
+void download_regfile(
+	struct sysinfo *ctrl,
+	uint8_t channel,
+	bool multicast,
+	uint8_t rank,
+	enum regfile_mode regfile,
+	uint8_t byte,
+	bool read_rf_rd,
+	bool read_rf_wr);
+
+ uint8_t get_rx_bias(const struct sysinfo *ctrl);
+ 
+ uint8_t get_tCWL(uint32_t mem_clock_mhz);
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index 817a9f8bf8..a81559bb1e 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -15,7 +15,11 @@
+ /* Register definitions */
+ 
+ /* DDR DATA per-channel per-bytelane */
+#define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
+#define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
+
+ #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
+#define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
+ 
+ /* DDR CKE per-channel */
+ #define DDR_CKE_ch_CMD_COMP_OFFSET(ch)		_DDRIO_C_R_B(0x1204, ch, 0, 0)
+@@ -38,6 +42,9 @@
+ #define DDR_SCRAMBLE_ch(ch)			(0x2000 + 4 * (ch))
+ #define DDR_SCRAM_MISC_CONTROL			0x2008
+ 
+/* DDR DATA per-channel multicast */
+#define DDR_DATA_ch_CONTROL_0(ch)		_DDRIO_C_R_B(0x3074, ch, 0, 0)
+
+ /* DDR CMDN/CMDS per-channel (writes go to both CMDN and CMDS fubs) */
+ #define DDR_CMD_ch_COMP_OFFSET(ch)		_DDRIO_C_R_B(0x3204, ch, 0, 0)
+ #define DDR_CMD_ch_PI_CODING(ch)		_DDRIO_C_R_B(0x3208, ch, 0, 0)
+@@ -147,6 +154,8 @@
+ 
+ #define REUT_ch_SEQ_ADDR_WRAP(ch)		(0x48e8 + 8 * (ch))
+ 
+#define REUT_ch_SEQ_ADDR_CURRENT(ch)		(0x48f8 + 8 * (ch))
+
+ #define REUT_ch_SEQ_MISC_CTL(ch)		(0x4908 + 4 * (ch))
+ 
+ #define REUT_ch_SEQ_ADDR_INC_CTL(ch)		(0x4910 + 8 * (ch))
+-- 
+2.39.2
+
@@ -0,0 +1,708 @@
+From 0826d1e9ba50daad13c3d5adccba4b180c82296b Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sun, 8 May 2022 00:05:41 +0200
+Subject: [PATCH 11/17] haswell NRI: Add RcvEn training
+
+Implement the RcvEn (Receive Enable) calibration procedure.
+
+Change-Id: Ifbfa520f3e0486c56d0988ce67af2ddb9cf29888
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/raminit_main.c     |   1 +
+ .../haswell/native_raminit/raminit_native.h   |  14 +
+ .../haswell/native_raminit/reg_structs.h      |  13 +
+ .../native_raminit/train_receive_enable.c     | 561 ++++++++++++++++++
+ .../intel/haswell/registers/mchbar.h          |   3 +
+ 6 files changed, 593 insertions(+)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index ebe9e9b762..e2fbfb4211 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -16,3 +16,4 @@ romstage-y += setup_wdb.c
+ romstage-y += spd_bitmunching.c
+ romstage-y += testing_io.c
+ romstage-y += timings_refresh.c
+romstage-y += train_receive_enable.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index 5e4674957d..7d444659c3 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = {
+ 	{ configure_memory_map,                                   true, "MEMMAP",     },
+ 	{ do_jedec_init,                                          true, "JEDECINIT",  },
+ 	{ pre_training,                                           true, "PRETRAIN",   },
+	{ train_receive_enable,                                   true, "RCVET",      },
+ };
+ 
+ /* Return a generic stepping value to make stepping checks simpler */
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 8707257b27..eaaaedad1e 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -43,6 +43,9 @@
+ #define NUM_WDB_CL_MUX_SEEDS	3
+ #define NUM_CADB_MUX_SEEDS	3
+ 
+/* Specified in PI ticks. 64 PI ticks == 1 qclk */
+#define tDQSCK_DRIFT		64
+
+ /* ZQ calibration types */
+ enum {
+ 	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
+@@ -189,6 +192,7 @@ enum raminit_status {
+ 	RAMINIT_STATUS_MPLL_INIT_FAILURE,
+ 	RAMINIT_STATUS_POLL_TIMEOUT,
+ 	RAMINIT_STATUS_REUT_ERROR,
+	RAMINIT_STATUS_RCVEN_FAILURE,
+ 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
+ };
+ 
+@@ -271,6 +275,10 @@ struct sysinfo {
+ 
+ 	union ddr_data_vref_adjust_reg dimm_vref;
+ 
+	uint8_t io_latency[NUM_CHANNELS][NUM_SLOTRANKS];
+	uint8_t rt_latency[NUM_CHANNELS][NUM_SLOTRANKS];
+	uint32_t rt_io_comp[NUM_CHANNELS];
+
+ 	uint32_t data_offset_train[NUM_CHANNELS][NUM_LANES];
+ 	uint32_t data_offset_comp[NUM_CHANNELS][NUM_LANES];
+ 
+@@ -345,6 +353,11 @@ static inline void clear_data_offset_train_all(struct sysinfo *ctrl)
+ 	memset(ctrl->data_offset_train, 0, sizeof(ctrl->data_offset_train));
+ }
+ 
+static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint8_t byte)
+{
+	return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte));
+}
+
+ /* Number of ticks to wait in units of 69.841279 ns (citation needed) */
+ static inline void tick_delay(const uint32_t delay)
+ {
+@@ -400,6 +413,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
+ enum raminit_status configure_mc(struct sysinfo *ctrl);
+ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
+ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+enum raminit_status train_receive_enable(struct sysinfo *ctrl);
+ 
+ void configure_timings(struct sysinfo *ctrl);
+ void configure_refresh(struct sysinfo *ctrl);
+diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+index b943259b91..b099f4bb82 100644
+--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+@@ -297,6 +297,19 @@ union ddr_scram_misc_control_reg {
+ 	uint32_t raw;
+ };
+ 
+union sc_io_latency_reg {
+	struct __packed {
+		uint32_t iolat_rank0     : 4; // Bits  3:0
+		uint32_t iolat_rank1     : 4; // Bits  7:4
+		uint32_t iolat_rank2     : 4; // Bits 11:8
+		uint32_t iolat_rank3     : 4; // Bits 15:12
+		uint32_t rt_iocomp       : 6; // Bits 21:16
+		uint32_t                 : 9; // Bits 30:22
+		uint32_t dis_rt_clk_gate : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+ union mcscheds_cbit_reg {
+ 	struct __packed {
+ 		uint32_t dis_opp_cas    : 1; // Bits  0:0
+diff --git a/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
+new file mode 100644
+index 0000000000..576c6bc21e
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_receive_enable.c
+@@ -0,0 +1,561 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+#include "ranges.h"
+
+#define RCVEN_PLOT	RAM_DEBUG
+
+static enum raminit_status change_rcven_timing(struct sysinfo *ctrl, const uint8_t channel)
+{
+	int16_t max_rcven = -4096;
+	int16_t min_rcven = 4096;
+	int16_t max_rcven_rank[NUM_SLOTRANKS];
+	int16_t min_rcven_rank[NUM_SLOTRANKS];
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		max_rcven_rank[rank] = max_rcven;
+		min_rcven_rank[rank] = min_rcven;
+	}
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			int16_t new_rcven = ctrl->rcven[channel][rank][byte];
+			new_rcven -= ctrl->io_latency[channel][rank] * 64;
+			if (max_rcven_rank[rank] < new_rcven)
+				max_rcven_rank[rank] = new_rcven;
+
+			if (min_rcven_rank[rank] > new_rcven)
+				min_rcven_rank[rank] = new_rcven;
+		}
+		if (max_rcven < max_rcven_rank[rank])
+			max_rcven = max_rcven_rank[rank];
+
+		if (min_rcven > min_rcven_rank[rank])
+			min_rcven = min_rcven_rank[rank];
+	}
+
+	/*
+	 * Determine how far we are from the ideal center point for RcvEn timing.
+	 * (PiIdeal - AveRcvEn) / 64 is the ideal number of cycles we should have
+	 * for IO latency. command training will reduce this by 64, so plan for
+	 * that now in the ideal value. Round to closest integer.
+	 */
+	const int16_t rre_pi_ideal = 256 + 64;
+	const int16_t pi_reserve = 64;
+	const int16_t rcven_center = (max_rcven + min_rcven) / 2;
+	const int8_t iolat_target = DIV_ROUND_CLOSEST(rre_pi_ideal - rcven_center, 64);
+
+	int8_t io_g_offset = 0;
+	int8_t io_lat[NUM_SLOTRANKS] = { 0 };
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		io_lat[rank] = iolat_target;
+
+		/* Check for RcvEn underflow/overflow */
+		const int16_t rcven_lower = 64 * io_lat[rank] + min_rcven_rank[rank];
+		if (rcven_lower < pi_reserve)
+			io_lat[rank] += DIV_ROUND_UP(pi_reserve - rcven_lower, 64);
+
+		const int16_t rcven_upper = 64 * io_lat[rank] + max_rcven_rank[rank];
+		if (rcven_upper > 511 - pi_reserve)
+			io_lat[rank] -= DIV_ROUND_UP(rcven_upper - (511 - pi_reserve), 64);
+
+		/* Check for IO latency over/underflow */
+		if (io_lat[rank] - io_g_offset > 14)
+			io_g_offset = io_lat[rank] - 14;
+
+		if (io_lat[rank] - io_g_offset < 1)
+			io_g_offset = io_lat[rank] - 1;
+
+		const int8_t cycle_offset = io_lat[rank] - ctrl->io_latency[channel][rank];
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			ctrl->rcven[channel][rank][byte] += 64 * cycle_offset;
+			update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+		}
+	}
+
+	/* Calculate new IO comp latency */
+	union sc_io_latency_reg sc_io_lat = {
+		.raw = mchbar_read32(SC_IO_LATENCY_ch(channel)),
+	};
+
+	/* Check if we are underflowing or overflowing this field */
+	if (io_g_offset < 0 && sc_io_lat.rt_iocomp < -io_g_offset) {
+		printk(BIOS_ERR, "%s: IO COMP underflow\n", __func__);
+		printk(BIOS_ERR, "io_g_offset: %d\n", io_g_offset);
+		printk(BIOS_ERR, "rt_iocomp: %u\n", sc_io_lat.rt_iocomp);
+		return RAMINIT_STATUS_RCVEN_FAILURE;
+	}
+	if (io_g_offset > 0 && io_g_offset > 0x3f - sc_io_lat.rt_iocomp) {
+		printk(BIOS_ERR, "%s: IO COMP overflow\n", __func__);
+		printk(BIOS_ERR, "io_g_offset: %d\n", io_g_offset);
+		printk(BIOS_ERR, "rt_iocomp: %u\n", sc_io_lat.rt_iocomp);
+		return RAMINIT_STATUS_RCVEN_FAILURE;
+	}
+	sc_io_lat.rt_iocomp += io_g_offset;
+	ctrl->rt_io_comp[channel] = sc_io_lat.rt_iocomp;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (ctrl->rankmap[channel] & BIT(rank))
+			ctrl->io_latency[channel][rank] = io_lat[rank] - io_g_offset;
+
+		const uint8_t shift = rank * 4;
+		sc_io_lat.raw &= ~(0xf << shift);
+		sc_io_lat.raw |= ctrl->io_latency[channel][rank] << shift;
+	}
+	mchbar_write32(SC_IO_LATENCY_ch(channel), sc_io_lat.raw);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+#define RL_START (256 + 24)
+#define RL_STOP  (384 + 24)
+#define RL_STEP  8
+
+#define RE_NUM_SAMPLES	6
+
+static enum raminit_status verify_high_region(const int32_t center, const int32_t lwidth)
+{
+	if (center > RL_STOP) {
+		/* Check if center of high was found where it should be */
+		printk(BIOS_ERR, "RcvEn: Center of high (%d) higher than expected\n", center);
+		return RAMINIT_STATUS_RCVEN_FAILURE;
+	}
+	if (lwidth <= 32) {
+		/* Check if width is large enough */
+		printk(BIOS_ERR, "RcvEn: Width of high region (%d) too small\n", lwidth);
+		return RAMINIT_STATUS_RCVEN_FAILURE;
+	}
+	if (lwidth >= 96) {
+		/* Since we're calibrating a phase, a too large region is a problem */
+		printk(BIOS_ERR, "RcvEn: Width of high region (%d) too large\n", lwidth);
+		return RAMINIT_STATUS_RCVEN_FAILURE;
+	}
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+static void program_io_latency(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
+{
+	const uint8_t shift = rank * 4;
+	const uint8_t iolat = ctrl->io_latency[channel][rank];
+	mchbar_clrsetbits32(SC_IO_LATENCY_ch(channel), 0xf << shift, iolat << shift);
+}
+
+static void program_rl_delays(struct sysinfo *ctrl, const uint8_t rank, const uint16_t rl_delay)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			update_rxt(ctrl, channel, rank, byte, RXT_RCVEN, rl_delay);
+	}
+}
+
+static bool sample_dqs(const uint8_t channel, const uint8_t byte)
+{
+	return (get_data_train_feedback(channel, byte) & 0x1ff) >= BIT(RE_NUM_SAMPLES - 1);
+}
+
+enum raminit_status train_receive_enable(struct sysinfo *ctrl)
+{
+	const struct reut_box reut_addr = {
+		.col = {
+			.start    = 0,
+			.stop     = 1023,
+			.inc_rate = 0,
+			.inc_val  = 1,
+		},
+	};
+	const struct wdb_pat wdb_pattern = {
+		.start_ptr  = 0,
+		.stop_ptr   = 9,
+		.inc_rate   = 32,
+		.dq_pattern = BASIC_VA,
+	};
+
+	const uint16_t bytemask = BIT(ctrl->lanes) - 1;
+	const uint8_t fine_step = 1;
+
+	const uint8_t rt_delta = is_hsw_ult() ? 4 : 2;
+	const uint8_t rt_io_comp = 21 + rt_delta;
+	const uint8_t rt_latency = 16 + rt_delta;
+	setup_io_test(
+		ctrl,
+		ctrl->chanmap,
+		PAT_RD,
+		2,
+		RE_NUM_SAMPLES + 1,
+		&reut_addr,
+		0,
+		&wdb_pattern,
+		0,
+		8);
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			union ddr_data_control_2_reg data_control_2 = {
+				.raw = ctrl->dq_control_2[channel][byte],
+			};
+			data_control_2.force_rx_on = 1;
+			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
+		}
+		union ddr_data_control_0_reg data_control_0 = {
+			.raw = ctrl->dq_control_0[channel],
+		};
+		if (ctrl->lpddr) {
+			/**
+			 * W/A for b4618574 - @todo: remove for HSW ULT C0
+			 * Can't have force_odt_on together with leaker, disable LPDDR
+			 * mode during this training step. lpddr_mode is restored
+			 * at the end of this function from the host structure.
+			 */
+			data_control_0.lpddr_mode = 0;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		}
+		data_control_0.force_odt_on     = 1;
+		data_control_0.rl_training_mode = 1;
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		mchbar_write32(SC_IO_LATENCY_ch(channel), (union sc_io_latency_reg) {
+			.rt_iocomp = rt_io_comp,
+		}.raw);
+	}
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!does_rank_exist(ctrl, rank))
+			continue;
+
+		/*
+		 * Set initial roundtrip latency values. Assume -4 QCLK for worst board
+		 * layout. This is calculated as HW_ROUNDT_LAT_DEFAULT_VALUE plus:
+		 *
+		 *   DDR3: Default + (2 * tAA) + 4 QCLK + PI_CLK + N-mode value * 2
+		 * LPDDR3: Default + (2 * tAA) + 4 QCLK + PI_CLK + tDQSCK_max
+		 *
+		 * N-mode is 3 during training mode. Both channels use the same timings.
+		 */
+		/** TODO: differs for LPDDR **/
+		const uint32_t tmp = MAX(ctrl->multiplier, 4) + 5 + 2 * ctrl->tAA;
+		const uint32_t initial_rt_latency = MIN(rt_latency + tmp, 0x3f);
+
+		uint8_t chanmask = 0;
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			ctrl->io_latency[channel][rank] = 0;
+			mchbar_write8(SC_ROUNDT_LAT_ch(channel) + rank, initial_rt_latency);
+			ctrl->rt_latency[channel][rank] = initial_rt_latency;
+		}
+
+		printk(BIOS_DEBUG, "Rank %u\n", rank);
+		printk(BIOS_DEBUG, "Steps 1 and 2: Find middle of high region\n");
+		printk(RCVEN_PLOT, "Byte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(RCVEN_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(RCVEN_PLOT, "%u ", byte);
+		}
+		printk(RCVEN_PLOT, "\nRcvEn\n");
+		struct phase_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
+		for (uint16_t rl_delay = RL_START; rl_delay < RL_STOP; rl_delay += RL_STEP) {
+			printk(RCVEN_PLOT, " % 3d", rl_delay);
+			program_rl_delays(ctrl, rank, rl_delay);
+			run_io_test(ctrl, chanmask, BASIC_VA, true);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				printk(RCVEN_PLOT, "\t");
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					const bool high = sample_dqs(channel, byte);
+					printk(RCVEN_PLOT, high ? ". " : "# ");
+					phase_record_pass(
+						&region_data[channel][byte],
+						high,
+						rl_delay,
+						RL_START,
+						RL_STEP);
+				}
+			}
+			printk(RCVEN_PLOT, "\n");
+		}
+		printk(RCVEN_PLOT, "\n");
+		printk(BIOS_DEBUG, "Update RcvEn timing to be in the center of high region\n");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(BIOS_DEBUG, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\n",
+				channel, rank);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				struct phase_train_data *const curr_data =
+						&region_data[channel][byte];
+				phase_append_current_to_initial(curr_data, RL_START, RL_STEP);
+				const int32_t lwidth = range_width(curr_data->largest);
+				const int32_t center = range_center(curr_data->largest);
+				printk(BIOS_DEBUG, "   B%u: \t%d\t%d\t%d\t%d\n",
+					byte,
+					curr_data->largest.start,
+					curr_data->largest.end,
+					lwidth,
+					center);
+
+				status = verify_high_region(center, lwidth);
+				if (status) {
+					printk(BIOS_ERR,
+						"RcvEn problems on channel %u, byte %u\n",
+						channel, byte);
+					goto clean_up;
+				}
+				ctrl->rcven[channel][rank][byte] = center;
+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+			}
+			printk(BIOS_DEBUG, "\n");
+		}
+
+		printk(BIOS_DEBUG, "Step 3: Quarter preamble - Walk backwards\n");
+		printk(RCVEN_PLOT, "Byte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(RCVEN_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(RCVEN_PLOT, "%u ", byte);
+		}
+		printk(RCVEN_PLOT, "\nIOLAT\n");
+		bool done = false;
+		while (!done) {
+			run_io_test(ctrl, chanmask, BASIC_VA, true);
+			done = true;
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				printk(RCVEN_PLOT, "  %2u\t", ctrl->io_latency[channel][rank]);
+				uint16_t highs = 0;
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					const bool high = sample_dqs(channel, byte);
+					printk(RCVEN_PLOT, high ? "H " : "L ");
+					if (high)
+						highs |= BIT(byte);
+				}
+				if (!highs)
+					continue;
+
+				done = false;
+
+				/* If all bytes sample high, adjust timing globally */
+				if (highs == bytemask && ctrl->io_latency[channel][rank] < 14) {
+					ctrl->io_latency[channel][rank] += 2;
+					ctrl->io_latency[channel][rank] %= 16;
+					program_io_latency(ctrl, channel, rank);
+					continue;
+				}
+
+				/* Otherwise, adjust individual bytes */
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					if (!(highs & BIT(byte)))
+						continue;
+
+					if (ctrl->rcven[channel][rank][byte] < 128) {
+						printk(BIOS_ERR,
+							"RcvEn underflow: walking backwards\n");
+						printk(BIOS_ERR,
+							"For channel %u, rank %u, byte %u\n",
+							channel, rank, byte);
+						status = RAMINIT_STATUS_RCVEN_FAILURE;
+						goto clean_up;
+					}
+					ctrl->rcven[channel][rank][byte] -= 128;
+					update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+				}
+			}
+			printk(RCVEN_PLOT, "\n");
+		}
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(BIOS_DEBUG, "\nC%u:  Preamble\n", channel);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				printk(BIOS_DEBUG,
+					" B%u: %u\n", byte, ctrl->rcven[channel][rank][byte]);
+			}
+		}
+		printk(BIOS_DEBUG, "\n");
+
+		printk(BIOS_DEBUG, "Step 4: Add 1 qclk\n");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				ctrl->rcven[channel][rank][byte] += 64;
+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+			}
+		}
+		printk(BIOS_DEBUG, "\n");
+
+		printk(BIOS_DEBUG, "Step 5: Walk forward to find rising edge\n");
+		printk(RCVEN_PLOT, "Byte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(RCVEN_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(RCVEN_PLOT, "%u ", byte);
+		}
+		printk(RCVEN_PLOT, "\n inc\n");
+		uint16_t ch_result[NUM_CHANNELS] = { 0 };
+		uint8_t inc_preamble[NUM_CHANNELS][NUM_LANES] = { 0 };
+		for (uint8_t inc = 0; inc < 64; inc += fine_step) {
+			printk(RCVEN_PLOT, " %2u\t", inc);
+			run_io_test(ctrl, chanmask, BASIC_VA, true);
+			done = true;
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					if (ch_result[channel] & BIT(byte)) {
+						/* Skip bytes that are already done */
+						printk(RCVEN_PLOT, ". ");
+						continue;
+					}
+					const bool pass = sample_dqs(channel, byte);
+					printk(RCVEN_PLOT, pass ? ". " : "# ");
+					if (pass) {
+						ch_result[channel] |= BIT(byte);
+						continue;
+					}
+					ctrl->rcven[channel][rank][byte] += fine_step;
+					update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+					inc_preamble[channel][byte] = inc;
+				}
+				printk(RCVEN_PLOT, "\t");
+				if (ch_result[channel] != bytemask)
+					done = false;
+			}
+			printk(RCVEN_PLOT, "\n");
+			if (done)
+				break;
+		}
+		printk(BIOS_DEBUG, "\n");
+		if (!done) {
+			printk(BIOS_ERR, "Error: Preamble edge not found for all bytes\n");
+			printk(BIOS_ERR, "The final RcvEn results are as follows:\n");
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				printk(BIOS_ERR, "Channel %u Rank %u:  preamble\n",
+					channel, rank);
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					printk(BIOS_ERR, " Byte %u: %u%s\n", byte,
+						ctrl->rcven[channel][rank][byte],
+						(ch_result[channel] ^ bytemask) & BIT(byte)
+							? ""
+							: " *** Check this byte! ***");
+				}
+			}
+			status = RAMINIT_STATUS_RCVEN_FAILURE;
+			goto clean_up;
+		}
+
+		printk(BIOS_DEBUG, "Step 6: center on preamble and clean up rank\n");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(BIOS_DEBUG, "C%u:  Preamble increment\n", channel);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				/*
+				 * For Traditional, pull in RcvEn by 64. For ULT, take the DQS
+				 * drift into account to the specified guardband: tDQSCK_DRIFT.
+				 */
+				ctrl->rcven[channel][rank][byte] -= tDQSCK_DRIFT;
+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+				printk(BIOS_DEBUG, " B%u: %u      %u\n", byte,
+					ctrl->rcven[channel][rank][byte],
+					inc_preamble[channel][byte]);
+			}
+			printk(BIOS_DEBUG, "\n");
+		}
+		printk(BIOS_DEBUG, "\n");
+	}
+
+clean_up:
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		if (ctrl->lpddr) {
+			/**
+			 * W/A for b4618574 - @todo: remove for HSW ULT C0
+			 * Can't have force_odt_on together with leaker, disable LPDDR mode for
+			 * this training step. This write will disable force_odt_on while still
+			 * keeping LPDDR mode disabled. Second write will restore LPDDR mode.
+			 */
+			union ddr_data_control_0_reg data_control_0 = {
+				.raw = ctrl->dq_control_0[channel],
+			};
+			data_control_0.lpddr_mode = 0;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		}
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			mchbar_write32(DQ_CONTROL_2(channel, byte),
+					ctrl->dq_control_2[channel][byte]);
+		}
+	}
+	io_reset();
+	if (status)
+		return status;
+
+	printk(BIOS_DEBUG, "Step 7: Sync IO latency across all ranks\n");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		status = change_rcven_timing(ctrl, channel);
+		if (status)
+			return status;
+	}
+	printk(BIOS_DEBUG, "\nFinal Receive Enable and IO latency settings:\n");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			const union sc_io_latency_reg sc_io_latency = {
+				.raw = mchbar_read32(SC_IO_LATENCY_ch(channel)),
+			};
+			printk(BIOS_DEBUG, "  C%u.R%u: IOLAT = %u  rt_iocomp = %u\n", channel,
+				rank, ctrl->io_latency[channel][rank], sc_io_latency.rt_iocomp);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				printk(BIOS_DEBUG, "   B%u:   %u\n", byte,
+					ctrl->rcven[channel][rank][byte]);
+			}
+			printk(BIOS_DEBUG, "\n");
+		}
+	}
+	return status;
+}
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index a81559bb1e..9172d4f2b0 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -18,6 +18,8 @@
+ #define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
+ #define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
+ 
+#define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
+
+ #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
+ #define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
+ 
+@@ -100,6 +102,7 @@
+ #define COMMAND_RATE_LIMIT_ch(ch)		_MCMAIN_C(0x4010, ch)
+ #define TC_BANK_RANK_D_ch(ch)			_MCMAIN_C(0x4014, ch)
+ #define SC_ROUNDT_LAT_ch(ch)			_MCMAIN_C(0x4024, ch)
+#define SC_IO_LATENCY_ch(ch)			_MCMAIN_C(0x4028, ch)
+ 
+ #define REUT_ch_PAT_WDB_CL_MUX_CFG(ch)		_MCMAIN_C(0x4040, ch)
+ 
+-- 
+2.39.2
+
@@ -0,0 +1,272 @@
+From 36ec2cfa730ba720ef7ded21cc3e84c47f4e2623 Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sun, 8 May 2022 11:58:59 +0200
+Subject: [PATCH 12/17] haswell NRI: Add function to change margins
+
+Implement a function to change margin parameters. Haswell provides a
+register to apply an offset to margin parameters during training, so
+make use of it. There are other margin parameters that have not been
+implemented yet, as they are not needed for now and special handling
+is needed to provide offset training functionality.
+
+Change-Id: I5392380e13de3c44e77b7bc9f3b819e2661d1e2d
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../haswell/native_raminit/change_margin.c    | 136 ++++++++++++++++++
+ .../haswell/native_raminit/raminit_native.h   |  39 +++++
+ .../haswell/native_raminit/reg_structs.h      |  12 ++
+ .../intel/haswell/registers/mchbar.h          |   1 +
+ 4 files changed, 188 insertions(+)
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/change_margin.c b/src/northbridge/intel/haswell/native_raminit/change_margin.c
+index 055c666eee..299c44a6b0 100644
+--- a/src/northbridge/intel/haswell/native_raminit/change_margin.c
+++ b/src/northbridge/intel/haswell/native_raminit/change_margin.c
+@@ -1,5 +1,6 @@
+ /* SPDX-License-Identifier: GPL-2.0-or-later */
+ 
+#include <assert.h>
+ #include <commonlib/bsd/clamp.h>
+ #include <console/console.h>
+ #include <delay.h>
+@@ -152,3 +153,138 @@ void download_regfile(
+ 	ddr_data_control_0.read_rf_rank = phys_rank;
+ 	mchbar_write32(reg, ddr_data_control_0.raw);
+ }
+
+static void update_data_offset_train(
+	struct sysinfo *ctrl,
+	const uint8_t param,
+	const uint8_t en_multicast,
+	const uint8_t channel_in,
+	const uint8_t rank,
+	const uint8_t byte_in,
+	const bool update_ctrl,
+	const enum regfile_mode regfile,
+	const uint32_t value)
+{
+	bool is_rd = false;
+	bool is_wr = false;
+	switch (param) {
+	case RdT:
+	case RdV:
+	case RcvEna:
+		is_rd = true;
+		break;
+	case WrT:
+	case WrDqsT:
+		is_wr = true;
+		break;
+	default:
+		die("%s: Invalid margin parameter %u\n", __func__, param);
+	}
+	if (en_multicast) {
+		mchbar_write32(DDR_DATA_OFFSET_TRAIN, value);
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			download_regfile(ctrl, channel, true, rank, regfile, 0, is_rd, is_wr);
+			if (update_ctrl) {
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+					ctrl->data_offset_train[channel][byte] = value;
+			}
+		}
+	} else {
+		mchbar_write32(DDR_DATA_OFFSET_TRAIN_ch_b(channel_in, byte_in), value);
+		download_regfile(ctrl, channel_in, false, rank, regfile, byte_in, is_rd, is_wr);
+		if (update_ctrl)
+			ctrl->data_offset_train[channel_in][byte_in] = value;
+	}
+}
+
+static uint32_t get_max_margin(const enum margin_parameter param)
+{
+	switch (param) {
+	case RcvEna:
+	case RdT:
+	case WrT:
+	case WrDqsT:
+		return MAX_POSSIBLE_TIME;
+	case RdV:
+		return MAX_POSSIBLE_VREF;
+	default:
+		die("%s: Invalid margin parameter %u\n", __func__, param);
+	}
+}
+
+void change_margin(
+	struct sysinfo *ctrl,
+	const enum margin_parameter param,
+	const int32_t value0,
+	const bool en_multicast,
+	const uint8_t channel,
+	const uint8_t rank,
+	const uint8_t byte,
+	const bool update_ctrl,
+	const enum regfile_mode regfile)
+{
+	/** FIXME: Remove this **/
+	if (rank == 0xff)
+		die("%s: rank is 0xff\n", __func__);
+
+	if (!en_multicast && !does_ch_exist(ctrl, channel))
+		die("%s: Tried to change margin of empty channel %u\n", __func__, channel);
+
+	const uint32_t max_value = get_max_margin(param);
+	const int32_t v0 = clamp_s32(-max_value, value0, max_value);
+
+	union ddr_data_offset_train_reg ddr_data_offset_train = {
+		.raw = en_multicast ? 0 : ctrl->data_offset_train[channel][byte],
+	};
+	bool update_offset_train = false;
+	switch (param) {
+	case RcvEna:
+		ddr_data_offset_train.rcven = v0;
+		update_offset_train = true;
+		break;
+	case RdT:
+		ddr_data_offset_train.rx_dqs = v0;
+		update_offset_train = true;
+		break;
+	case WrT:
+		ddr_data_offset_train.tx_dq = v0;
+		update_offset_train = true;
+		break;
+	case WrDqsT:
+		ddr_data_offset_train.tx_dqs = v0;
+		update_offset_train = true;
+		break;
+	case RdV:
+		ddr_data_offset_train.vref = v0;
+		update_offset_train = true;
+		break;
+	default:
+		die("%s: Invalid margin parameter %u\n", __func__, param);
+	}
+	if (update_offset_train) {
+		update_data_offset_train(
+			ctrl,
+			param,
+			en_multicast,
+			channel,
+			rank,
+			byte,
+			update_ctrl,
+			regfile,
+			ddr_data_offset_train.raw);
+	}
+}
+
+void change_1d_margin_multicast(
+	struct sysinfo *ctrl,
+	const enum margin_parameter param,
+	const int32_t value0,
+	const uint8_t rank,
+	const bool update_ctrl,
+	const enum regfile_mode regfile)
+{
+	change_margin(ctrl, param, value0, true, 0, rank, 0, update_ctrl, regfile);
+}
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index eaaaedad1e..1c8473056b 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -36,6 +36,18 @@
+ 
+ #define RTTNOM_MASK		(BIT(9) | BIT(6) | BIT(2))
+ 
+/* Margin parameter limits */
+#define MAX_POSSIBLE_TIME	31
+#define MAX_POSSIBLE_VREF	54
+
+#define MAX_POSSIBLE_BOTH	MAX_POSSIBLE_VREF
+
+#define MIN_TIME		(-MAX_POSSIBLE_TIME)
+#define MAX_TIME		(MAX_POSSIBLE_TIME)
+
+#define MIN_VREF		(-MAX_POSSIBLE_VREF)
+#define MAX_VREF		(MAX_POSSIBLE_VREF)
+
+ #define BASIC_VA_PAT_SPREAD_8	0x01010101
+ 
+ #define WDB_CACHE_LINE_SIZE	8
+@@ -46,6 +58,14 @@
+ /* Specified in PI ticks. 64 PI ticks == 1 qclk */
+ #define tDQSCK_DRIFT		64
+ 
+enum margin_parameter {
+	RcvEna,
+	RdT,
+	WrT,
+	WrDqsT,
+	RdV,
+};
+
+ /* ZQ calibration types */
+ enum {
+ 	ZQ_INIT,	/* DDR3: ZQCL with tZQinit, LPDDR3: ZQ Init  with tZQinit  */
+@@ -515,6 +535,25 @@ void download_regfile(
+ 	bool read_rf_rd,
+ 	bool read_rf_wr);
+ 
+void change_margin(
+	struct sysinfo *ctrl,
+	const enum margin_parameter param,
+	const int32_t value0,
+	const bool en_multicast,
+	const uint8_t channel,
+	const uint8_t rank,
+	const uint8_t byte,
+	const bool update_ctrl,
+	const enum regfile_mode regfile);
+
+void change_1d_margin_multicast(
+	struct sysinfo *ctrl,
+	const enum margin_parameter param,
+	const int32_t value0,
+	const uint8_t rank,
+	const bool update_ctrl,
+	const enum regfile_mode regfile);
+
+ uint8_t get_rx_bias(const struct sysinfo *ctrl);
+ 
+ uint8_t get_tCWL(uint32_t mem_clock_mhz);
+diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+index b099f4bb82..a0e36ed082 100644
+--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+@@ -25,6 +25,18 @@ union ddr_data_tx_train_rank_reg {
+ 	uint32_t raw;
+ };
+ 
+union ddr_data_offset_train_reg {
+	struct __packed {
+		int32_t rcven  : 6; // Bits  5:0
+		int32_t rx_dqs : 6; // Bits 11:6
+		int32_t tx_dq  : 6; // Bits 17:12
+		int32_t tx_dqs : 6; // Bits 23:18
+		int32_t vref   : 7; // Bits 30:24
+		int32_t        : 1; // Bits 31:31
+	};
+	uint32_t raw;
+};
+
+ union ddr_data_control_0_reg {
+ 	struct __packed {
+ 		uint32_t rx_training_mode      : 1; // Bits  0:0
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index 9172d4f2b0..0acafbc826 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -21,6 +21,7 @@
+ #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
+ 
+ #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
+#define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte)	_DDRIO_C_R_B(0x0070, ch, 0, byte)
+ #define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
+ 
+ /* DDR CKE per-channel */
+-- 
+2.39.2
+
@@ -0,0 +1,332 @@
+From 87015f060aa208f37481deef460b3545ce2d757f Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sun, 8 May 2022 11:35:49 +0200
+Subject: [PATCH 13/17] haswell NRI: Add read MPR training
+
+Implement read training using DDR3 MPR (Multi-Purpose Register).
+
+Change-Id: Id17cb2c4c399ac9bcc937b595b58f863c152461b
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/raminit_main.c     |   1 +
+ .../haswell/native_raminit/raminit_native.h   |   4 +
+ .../haswell/native_raminit/train_read_mpr.c   | 241 ++++++++++++++++++
+ .../intel/haswell/registers/mchbar.h          |   2 +-
+ 5 files changed, 248 insertions(+), 1 deletion(-)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index e2fbfb4211..c442be0728 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -16,4 +16,5 @@ romstage-y += setup_wdb.c
+ romstage-y += spd_bitmunching.c
+ romstage-y += testing_io.c
+ romstage-y += timings_refresh.c
+romstage-y += train_read_mpr.c
+ romstage-y += train_receive_enable.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index 7d444659c3..264d1468f5 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -61,6 +61,7 @@ static const struct task_entry cold_boot[] = {
+ 	{ do_jedec_init,                                          true, "JEDECINIT",  },
+ 	{ pre_training,                                           true, "PRETRAIN",   },
+ 	{ train_receive_enable,                                   true, "RCVET",      },
+	{ train_read_mpr,                                         true, "RDMPRT",     },
+ };
+ 
+ /* Return a generic stepping value to make stepping checks simpler */
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 1c8473056b..7a486479ea 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -28,6 +28,8 @@
+ /* Always use 12 legs for emphasis (not trained) */
+ #define TXEQFULLDRV		(3 << 4)
+ 
+#define LOOPCOUNT_INFINITE	0xff
+
+ /* DDR3 mode register bits */
+ #define MR0_DLL_RESET		BIT(8)
+ 
+@@ -213,6 +215,7 @@ enum raminit_status {
+ 	RAMINIT_STATUS_POLL_TIMEOUT,
+ 	RAMINIT_STATUS_REUT_ERROR,
+ 	RAMINIT_STATUS_RCVEN_FAILURE,
+	RAMINIT_STATUS_RMPR_FAILURE,
+ 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
+ };
+ 
+@@ -434,6 +437,7 @@ enum raminit_status configure_mc(struct sysinfo *ctrl);
+ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
+ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+ enum raminit_status train_receive_enable(struct sysinfo *ctrl);
+enum raminit_status train_read_mpr(struct sysinfo *ctrl);
+ 
+ void configure_timings(struct sysinfo *ctrl);
+ void configure_refresh(struct sysinfo *ctrl);
+diff --git a/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
+new file mode 100644
+index 0000000000..ade1e36148
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_read_mpr.c
+@@ -0,0 +1,241 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+#include "ranges.h"
+
+#define RMPR_START	(-32)
+#define RMPR_STOP	(32)
+#define RMPR_STEP	1
+
+#define RMPR_MIN_WIDTH	12
+
+#define RMPR_PLOT	RAM_DEBUG
+
+/*
+ * Clear rx_training_mode. For LPDDR, we first need to disable odt_samp_extend_en,
+ * then disable rx_training_mode, and finally re-enable odt_samp_extend_en.
+ */
+static void clear_rx_training_mode(struct sysinfo *ctrl, const uint8_t channel)
+{
+	for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+		mchbar_write32(DQ_CONTROL_2(channel, byte), ctrl->dq_control_2[channel][byte]);
+
+	if (ctrl->lpddr) {
+		union ddr_data_control_0_reg data_control_0 = {
+			.raw = mchbar_read32(DDR_DATA_ch_CONTROL_0(channel)),
+		};
+		data_control_0.odt_samp_extend_en = 0;
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		tick_delay(1);
+		data_control_0.rx_training_mode = 0;
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		tick_delay(1);
+	}
+	mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+}
+
+static void set_rxdqs_edges_to_midpoint(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				update_rxt(ctrl, channel, rank, byte, RXT_RXDQS_BOTH, 32);
+		}
+	}
+}
+
+static void enter_mpr_train_ddr_mode(struct sysinfo *ctrl, const uint8_t rank)
+{
+	/* Program MR3 and mask RAS/WE to prevent scheduler from issuing non-read commands */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		if (!ctrl->lpddr)
+			reut_issue_mrs(ctrl, channel, BIT(rank), 3, 1 << 2);
+
+		union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
+			.raw = mchbar_read32(REUT_ch_MISC_ODT_CTRL(channel)),
+		};
+		reut_misc_odt_ctrl.mpr_train_ddr_on = 1;
+		mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
+	}
+}
+
+static void leave_mpr_train_ddr_mode(struct sysinfo *ctrl, const uint8_t rank)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		/*
+		 * The mpr_train_ddr_on bit will force a special command.
+		 * Therefore, clear it before issuing the MRS command.
+		 */
+		union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
+			.raw = mchbar_read32(REUT_ch_MISC_ODT_CTRL(channel)),
+		};
+		reut_misc_odt_ctrl.mpr_train_ddr_on = 0;
+		mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
+		if (!ctrl->lpddr)
+			reut_issue_mrs(ctrl, channel, BIT(rank), 3, 0 << 2);
+	}
+}
+
+enum raminit_status train_read_mpr(struct sysinfo *ctrl)
+{
+	set_rxdqs_edges_to_midpoint(ctrl);
+	clear_data_offset_train_all(ctrl);
+	setup_io_test_mpr(ctrl, ctrl->chanmap, LOOPCOUNT_INFINITE, NSOE);
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!does_rank_exist(ctrl, rank))
+			continue;
+
+		printk(BIOS_DEBUG, "Rank %u\n", rank);
+		printk(RMPR_PLOT, "Channel");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(RMPR_PLOT, "\t%u\t\t", channel);
+		}
+		printk(RMPR_PLOT, "\nByte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(RMPR_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(RMPR_PLOT, "%u ", byte);
+		}
+		enter_mpr_train_ddr_mode(ctrl, rank);
+		struct linear_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
+			select_reut_ranks(ctrl, channel, BIT(rank));
+
+		printk(RMPR_PLOT, "\nDqsDelay\n");
+		int8_t dqs_delay;
+		for (dqs_delay = RMPR_START; dqs_delay < RMPR_STOP; dqs_delay += RMPR_STEP) {
+			printk(RMPR_PLOT, "% 5d", dqs_delay);
+			const enum regfile_mode regfile = REG_FILE_USE_START;
+			/* Looks like MRC uses rank 0 here, but it feels wrong */
+			change_1d_margin_multicast(ctrl, RdT, dqs_delay, rank, false, regfile);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					union ddr_data_control_2_reg data_control_2 = {
+						.raw = ctrl->dq_control_2[channel][byte],
+					};
+					data_control_2.force_bias_on = 1;
+					data_control_2.force_rx_on   = 1;
+					data_control_2.leaker_comp   = 0;
+					mchbar_write32(DQ_CONTROL_2(channel, byte),
+						data_control_2.raw);
+				}
+				union ddr_data_control_0_reg data_control_0 = {
+					.raw = ctrl->dq_control_0[channel],
+				};
+				data_control_0.rx_training_mode   = 1;
+				data_control_0.force_odt_on       = !ctrl->lpddr;
+				data_control_0.en_read_preamble   = 0;
+				data_control_0.odt_samp_extend_en = ctrl->lpddr;
+				const uint32_t reg_offset = DDR_DATA_ch_CONTROL_0(channel);
+				mchbar_write32(reg_offset, data_control_0.raw);
+			}
+			run_mpr_io_test(false);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				printk(RMPR_PLOT, "\t");
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					uint32_t fb = get_data_train_feedback(channel, byte);
+					const bool pass = fb == 1;
+					printk(RMPR_PLOT, pass ? ". " : "# ");
+					linear_record_pass(
+						&region_data[channel][byte],
+						pass,
+						dqs_delay,
+						RMPR_START,
+						RMPR_STEP);
+				}
+			}
+			printk(RMPR_PLOT, "\n");
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				clear_rx_training_mode(ctrl, channel);
+			}
+			io_reset();
+		}
+		printk(RMPR_PLOT, "\n");
+		leave_mpr_train_ddr_mode(ctrl, rank);
+		clear_data_offset_train_all(ctrl);
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(BIOS_DEBUG, "C%u.R%u: \tLeft\tRight\tWidth\tCenter\tRxDqsPN\n",
+				channel, rank);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				struct linear_train_data *data = &region_data[channel][byte];
+				const int32_t lwidth = range_width(data->largest);
+				if (lwidth <= RMPR_MIN_WIDTH) {
+					printk(BIOS_ERR,
+						"Bad eye (lwidth %d <= min %d) for byte %u\n",
+						lwidth, RMPR_MIN_WIDTH, byte);
+					status = RAMINIT_STATUS_RMPR_FAILURE;
+				}
+				/*
+				 * The MPR center may not be ideal on certain platforms for
+				 * unknown reasons. If so, adjust it with a magical number.
+				 * For Haswell, the magical number is zero. Hell knows why.
+				 */
+				const int32_t center = range_center(data->largest);
+				ctrl->rxdqsp[channel][rank][byte] = center - RMPR_START;
+				ctrl->rxdqsn[channel][rank][byte] = center - RMPR_START;
+				printk(BIOS_DEBUG, "  B%u: \t%d\t%d\t%d\t%d\t%u\n", byte,
+					data->largest.start, data->largest.end, lwidth,
+					center, ctrl->rxdqsp[channel][rank][byte]);
+			}
+			printk(BIOS_DEBUG, "\n");
+		}
+	}
+
+	/*
+	 * Now program the DQS center values on populated ranks. data is taken from
+	 * the host struct. We need to do it after all ranks are trained, because we
+	 * need to keep the same DQS value on all ranks during the training procedure.
+	 */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+		}
+	}
+	change_1d_margin_multicast(ctrl, RdT, 0, 0, false, REG_FILE_USE_CURRENT);
+	io_reset();
+	return status;
+}
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index 0acafbc826..6a31d3a32c 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -122,7 +122,7 @@
+ #define REUT_ch_ERR_DATA_MASK(ch)		_MCMAIN_C(0x40d8, ch)
+ 
+ #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
+-
+#define REUT_ch_MISC_ODT_CTRL(ch)		_MCMAIN_C(0x4194, ch)
+ #define REUT_ch_MISC_PAT_CADB_CTRL(ch)		_MCMAIN_C(0x4198, ch)
+ #define REUT_ch_PAT_CADB_MRS(ch)		_MCMAIN_C(0x419c, ch)
+ #define REUT_ch_PAT_CADB_MUX_CTRL(ch)		_MCMAIN_C(0x41a0, ch)
+-- 
+2.39.2
+
@@ -0,0 +1,689 @@
+From ce0ed94f993506e75b711c214b49ba480037e7d3 Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sun, 8 May 2022 12:56:04 +0200
+Subject: [PATCH 14/17] haswell NRI: Add write leveling
+
+Implement JEDEC write leveling, which is done in two steps. The first
+step uses the JEDEC procedure to do "fine" write leveling, i.e. align
+the DQS phase to the clock signal. The second step performs a regular
+read-write test to correct "coarse" cycle errors.
+
+Change-Id: I27678523fe22c38173a688e2a4751c259a20f009
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/raminit_main.c     |   1 +
+ .../haswell/native_raminit/raminit_native.h   |  10 +
+ .../train_jedec_write_leveling.c              | 581 ++++++++++++++++++
+ .../intel/haswell/registers/mchbar.h          |   2 +
+ 5 files changed, 595 insertions(+)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index c442be0728..40c2f5e014 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -16,5 +16,6 @@ romstage-y += setup_wdb.c
+ romstage-y += spd_bitmunching.c
+ romstage-y += testing_io.c
+ romstage-y += timings_refresh.c
+romstage-y += train_jedec_write_leveling.c
+ romstage-y += train_read_mpr.c
+ romstage-y += train_receive_enable.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index 264d1468f5..1ff23be615 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -62,6 +62,7 @@ static const struct task_entry cold_boot[] = {
+ 	{ pre_training,                                           true, "PRETRAIN",   },
+ 	{ train_receive_enable,                                   true, "RCVET",      },
+ 	{ train_read_mpr,                                         true, "RDMPRT",     },
+	{ train_jedec_write_leveling,                             true, "JWRL",       },
+ };
+ 
+ /* Return a generic stepping value to make stepping checks simpler */
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 7a486479ea..d6b11b9d3c 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -60,6 +60,9 @@
+ /* Specified in PI ticks. 64 PI ticks == 1 qclk */
+ #define tDQSCK_DRIFT		64
+ 
+/* Maximum additional latency */
+#define MAX_ADD_DELAY		2
+
+ enum margin_parameter {
+ 	RcvEna,
+ 	RdT,
+@@ -216,6 +219,7 @@ enum raminit_status {
+ 	RAMINIT_STATUS_REUT_ERROR,
+ 	RAMINIT_STATUS_RCVEN_FAILURE,
+ 	RAMINIT_STATUS_RMPR_FAILURE,
+	RAMINIT_STATUS_JWRL_FAILURE,
+ 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
+ };
+ 
+@@ -381,6 +385,11 @@ static inline uint32_t get_data_train_feedback(const uint8_t channel, const uint
+ 	return mchbar_read32(DDR_DATA_TRAIN_FEEDBACK(channel, byte));
+ }
+ 
+static inline uint16_t get_byte_group_errors(const uint8_t channel)
+{
+	return mchbar_read32(4 + REUT_ch_ERR_MISC_STATUS(channel)) & 0x1ff;
+}
+
+ /* Number of ticks to wait in units of 69.841279 ns (citation needed) */
+ static inline void tick_delay(const uint32_t delay)
+ {
+@@ -438,6 +447,7 @@ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
+ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+ enum raminit_status train_receive_enable(struct sysinfo *ctrl);
+ enum raminit_status train_read_mpr(struct sysinfo *ctrl);
+enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+ 
+ void configure_timings(struct sysinfo *ctrl);
+ void configure_refresh(struct sysinfo *ctrl);
+diff --git a/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
+new file mode 100644
+index 0000000000..ef6483e2bd
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_jedec_write_leveling.c
+@@ -0,0 +1,581 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <console/console.h>
+#include <delay.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+#include "ranges.h"
+
+#define JWLC_PLOT	RAM_DEBUG
+#define JWRL_PLOT	RAM_DEBUG
+
+static void reset_dram_dll(struct sysinfo *ctrl, const uint8_t channel, const uint8_t rank)
+{
+	const uint16_t mr0reg = ctrl->mr0[channel][rank / 2];
+	reut_issue_mrs(ctrl, channel, BIT(rank), 0, mr0reg | MR0_DLL_RESET);
+}
+
+static void program_wdb_pattern(struct sysinfo *ctrl, const bool invert)
+{
+	/* Pattern to keep DQ-DQS simple but detect any failures. Same as NHM/WSM. */
+	const uint8_t pat[4][2] = {
+		{ 0x00, 0xff },
+		{ 0xff, 0x00 },
+		{ 0xc3, 0x3c },
+		{ 0x3c, 0xc3 },
+	};
+	const uint8_t pmask[2][8] = {
+		{ 0, 0, 1, 1, 1, 1, 0, 0 },
+		{ 1, 1, 0, 0, 0, 0, 1, 1 },
+	};
+	for (uint8_t s = 0; s < ARRAY_SIZE(pat); s++)
+		write_wdb_fixed_pat(ctrl, pat[s], pmask[invert], ARRAY_SIZE(pmask[invert]), s);
+}
+
+static int16_t set_add_delay(uint32_t *add_delay, uint8_t rank, int8_t target_off)
+{
+	const uint8_t shift = rank * 2;
+	if (target_off > MAX_ADD_DELAY) {
+		*add_delay &= ~(3 << shift);
+		*add_delay |= MAX_ADD_DELAY << shift;
+		return 128 * (target_off - MAX_ADD_DELAY);
+	} else if (target_off < 0) {
+		*add_delay &= ~(3 << shift);
+		*add_delay |= 0 << shift;
+		return 128 * target_off;
+	} else {
+		*add_delay &= ~(3 << shift);
+		*add_delay |= target_off << shift;
+		return 0;
+	}
+}
+
+static enum raminit_status train_jedec_write_leveling_cleanup(struct sysinfo *ctrl)
+{
+	const struct reut_box reut_addr = {
+		.col = {
+			.start   = 0,
+			.stop    = 1023,
+			.inc_val = 1,
+		},
+	};
+	const struct wdb_pat wdb_pattern = {
+		.start_ptr  = 0,
+		.stop_ptr   = 3,
+		.inc_rate   = 1,
+		.dq_pattern = BASIC_VA,
+	};
+	const int8_t offsets[] = { 0, 1, -1, 2, 3 };
+	const int8_t dq_offsets[] = { 0, -10, 10, -5, 5, -15, 15 };
+	const uint8_t dq_offset_max = ARRAY_SIZE(dq_offsets);
+
+	/* Set LFSR seeds to be sequential */
+	program_wdb_lfsr(ctrl, true);
+	setup_io_test(
+		ctrl,
+		ctrl->chanmap,
+		PAT_WR_RD,
+		2,
+		4,
+		&reut_addr,
+		NSOE,
+		&wdb_pattern,
+		0,
+		0);
+
+	const union reut_pat_wdb_cl_mux_cfg_reg reut_wdb_cl_mux_cfg = {
+		.mux_0_control       = REUT_MUX_BTBUFFER,
+		.mux_1_control       = REUT_MUX_BTBUFFER,
+		.mux_2_control       = REUT_MUX_BTBUFFER,
+		.ecc_data_source_sel = 1,
+	};
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		mchbar_write32(REUT_ch_PAT_WDB_CL_MUX_CFG(channel), reut_wdb_cl_mux_cfg.raw);
+	}
+
+	int8_t byte_off[NUM_CHANNELS][NUM_LANES] = { 0 };
+	uint32_t add_delay[NUM_CHANNELS] = { 0 };
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	bool invert = false;
+	const uint16_t valid_byte_mask = BIT(ctrl->lanes) - 1;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		uint8_t chanmask = 0;
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++)
+			chanmask |= select_reut_ranks(ctrl, channel, BIT(rank));
+
+		if (!chanmask)
+			continue;
+
+		printk(BIOS_DEBUG, "Rank %u\n", rank);
+		printk(JWLC_PLOT, "Channel");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(JWLC_PLOT, "\t\t%u\t", channel);
+		}
+		printk(JWLC_PLOT, "\nByte\t");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(JWLC_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(JWLC_PLOT, "%u ", byte);
+		}
+		printk(JWLC_PLOT, "\nDelay DqOffset");
+		bool done = false;
+		int8_t byte_sum[NUM_CHANNELS] = { 0 };
+		uint16_t byte_pass[NUM_CHANNELS] = { 0 };
+		for (uint8_t off = 0; off < ARRAY_SIZE(offsets); off++) {
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				const int16_t global_byte_off =
+					set_add_delay(&add_delay[channel], rank, offsets[off]);
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					update_txt(ctrl, channel, rank, byte, TXT_DQDQS_OFF,
+						global_byte_off);
+				}
+				mchbar_write32(SC_WR_ADD_DELAY_ch(channel),
+						add_delay[channel]);
+			}
+			/* Reset FIFOs and DRAM DLL (Micron workaround) */
+			if (!ctrl->lpddr) {
+				io_reset();
+				for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+					if (!rank_in_ch(ctrl, rank, channel))
+						continue;
+
+					reset_dram_dll(ctrl, channel, rank);
+				}
+				udelay(1);
+			}
+			for (uint8_t dq_offset = 0; dq_offset < dq_offset_max; dq_offset++) {
+				printk(JWLC_PLOT, "\n% 3d\t% 3d",
+					offsets[off], dq_offsets[dq_offset]);
+				change_1d_margin_multicast(
+					ctrl,
+					WrT,
+					dq_offsets[dq_offset],
+					rank,
+					false,
+					REG_FILE_USE_RANK);
+
+				/*
+				 * Re-program the WDB pattern. Change the pattern
+				 * for the next test to avoid false pass issues.
+				 */
+				program_wdb_pattern(ctrl, invert);
+				invert = !invert;
+				run_io_test(ctrl, chanmask, BASIC_VA, true);
+				done = true;
+				for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+					if (!rank_in_ch(ctrl, rank, channel))
+						continue;
+
+					printk(JWLC_PLOT, "\t");
+					uint16_t result = get_byte_group_errors(channel);
+					result &= valid_byte_mask;
+
+					/* Skip bytes that have failed or already passed */
+					const uint16_t skip_me = result | byte_pass[channel];
+					for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+						const bool pass = result & BIT(byte);
+						printk(JWLC_PLOT, pass ? "# " : ". ");
+						if (skip_me & BIT(byte))
+							continue;
+
+						byte_pass[channel] |= BIT(byte);
+						byte_off[channel][byte] = offsets[off];
+						byte_sum[channel] += offsets[off];
+					}
+					if (byte_pass[channel] != valid_byte_mask)
+						done = false;
+				}
+				if (done)
+					break;
+			}
+			if (done)
+				break;
+		}
+		printk(BIOS_DEBUG, "\n\n");
+		if (!done) {
+			printk(BIOS_ERR, "JWLC: Could not find a pass for all bytes\n");
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				printk(BIOS_ERR, "Channel %u, rank %u fail:", channel, rank);
+				const uint16_t passing_mask = byte_pass[channel];
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					if (BIT(byte) & passing_mask)
+						continue;
+
+					printk(BIOS_ERR, " %u", byte);
+				}
+				printk(BIOS_ERR, "\n");
+			}
+			status = RAMINIT_STATUS_JWRL_FAILURE;
+			break;
+		}
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			/* Refine target offset to make sure it works for all bytes */
+			int8_t target_off = DIV_ROUND_CLOSEST(byte_sum[channel], ctrl->lanes);
+			int16_t global_byte_off = 0;
+			uint8_t all_good_loops = 0;
+			bool all_good = 0;
+			while (!all_good) {
+				global_byte_off =
+					set_add_delay(&add_delay[channel], rank, target_off);
+				all_good = true;
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					int16_t local_offset;
+					local_offset = byte_off[channel][byte] - target_off;
+					local_offset = local_offset * 128 + global_byte_off;
+					const uint16_t tx_dq = ctrl->tx_dq[channel][rank][byte];
+					if (tx_dq + local_offset >= (512 - 64)) {
+						all_good = false;
+						all_good_loops++;
+						target_off++;
+						break;
+					}
+					const uint16_t txdqs = ctrl->tx_dq[channel][rank][byte];
+					if (txdqs + local_offset < 96) {
+						all_good = false;
+						all_good_loops++;
+						target_off--;
+						break;
+					}
+				}
+				/* Avoid an infinite loop */
+				if (all_good_loops > 3)
+					break;
+			}
+			if (!all_good) {
+				printk(BIOS_ERR, "JWLC: Target offset refining failed\n");
+				status = RAMINIT_STATUS_JWRL_FAILURE;
+				break;
+			}
+			printk(BIOS_DEBUG, "C%u.R%u:  Offset\tFinalEdge\n", channel, rank);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				int16_t local_offset;
+				local_offset = byte_off[channel][byte] - target_off;
+				local_offset = local_offset * 128 + global_byte_off;
+				ctrl->tx_dq[channel][rank][byte] += local_offset;
+				ctrl->txdqs[channel][rank][byte] += local_offset;
+				update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
+				printk(BIOS_DEBUG, "  B%u:   %d\t%d\n", byte, local_offset,
+					ctrl->txdqs[channel][rank][byte]);
+			}
+			mchbar_write32(SC_WR_ADD_DELAY_ch(channel), add_delay[channel]);
+			if (!ctrl->lpddr) {
+				reset_dram_dll(ctrl, channel, rank);
+				udelay(1);
+			}
+			printk(BIOS_DEBUG, "\n");
+		}
+		printk(BIOS_DEBUG, "\n");
+	}
+
+	/* Restore WDB after test */
+	write_wdb_va_pat(ctrl, 0, BASIC_VA_PAT_SPREAD_8, 8, 0);
+	program_wdb_lfsr(ctrl, false);
+	mchbar_write32(DDR_DATA_OFFSET_TRAIN, 0);
+
+	/** TODO: Do full JEDEC init instead? **/
+	io_reset();
+	return status;
+}
+
+static enum raminit_status verify_wl_width(const int32_t lwidth)
+{
+	if (lwidth <= 32) {
+		/* Check if width is valid */
+		printk(BIOS_ERR, "WrLevel: Width region (%d) too small\n", lwidth);
+		return RAMINIT_STATUS_JWRL_FAILURE;
+	}
+	if (lwidth >= 96) {
+		/* Since we're calibrating a phase, a too large region is a problem */
+		printk(BIOS_ERR, "WrLevel: Width region (%d) too large\n", lwidth);
+		return RAMINIT_STATUS_JWRL_FAILURE;
+	}
+	return 0;
+}
+
+enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl)
+{
+	/*
+	 * Enabling WL mode causes DQS to toggle for 1024 QCLK.
+	 * Wait for this to stop. Round up to nearest microsecond.
+	 */
+	const bool wl_long_delay = ctrl->lpddr;
+	const uint32_t dqs_toggle_time = wl_long_delay ? 2048 : 1024;
+	const uint32_t wait_time_us = DIV_ROUND_UP(ctrl->qclkps * dqs_toggle_time, 1000 * 1000);
+
+	const uint16_t wl_start = 192;
+	const uint16_t wl_stop  = 192 + 128;
+	const uint16_t wl_step  = 2;
+
+	/* Do not use cached MR values */
+	const bool save_restore_mrs = ctrl->restore_mrs;
+	ctrl->restore_mrs = 0;
+
+	/* Propagate delay values (without a write command) */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		/* Propagate delay values from rank 0 to prevent assertion failures in RTL */
+		union ddr_data_control_0_reg data_control_0 = {
+			.raw = ctrl->dq_control_0[channel],
+		};
+		data_control_0.read_rf_rd   = 0;
+		data_control_0.read_rf_wr   = 1;
+		data_control_0.read_rf_rank = 0;
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			union ddr_data_control_2_reg data_control_2 = {
+				.raw = ctrl->dq_control_2[channel][byte],
+			};
+			data_control_2.force_bias_on = 1;
+			data_control_2.force_rx_on   = 0;
+			data_control_2.wl_long_delay = wl_long_delay;
+			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
+		}
+	}
+
+	if (ctrl->lpddr)
+		die("%s: Missing LPDDR support\n", __func__);
+
+	if (!ctrl->lpddr)
+		ddr3_program_mr1(ctrl, 0, 1);
+
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	struct phase_train_data region_data[NUM_CHANNELS][NUM_LANES] = { 0 };
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!does_rank_exist(ctrl, rank))
+			continue;
+
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			/** TODO: Differs for LPDDR **/
+			uint16_t mr1reg = ctrl->mr1[channel][rank / 2];
+			mr1reg &= ~MR1_QOFF_ENABLE;
+			mr1reg |= MR1_WL_ENABLE;
+			if (is_hsw_ult()) {
+				mr1reg &= ~RTTNOM_MASK;
+				mr1reg |= encode_ddr3_rttnom(120);
+			} else if (ctrl->dpc[channel] == 2) {
+				mr1reg &= ~RTTNOM_MASK;
+				mr1reg |= encode_ddr3_rttnom(60);
+			}
+			reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
+
+			/* Assert ODT for myself */
+			uint8_t odt_matrix = BIT(rank);
+			if (ctrl->dpc[channel] == 2) {
+				/* Assert ODT for non-target DIMM */
+				const uint8_t other_dimm = ((rank + 2) / 2) & 1;
+				odt_matrix |= BIT(2 * other_dimm);
+			}
+
+			union reut_misc_odt_ctrl_reg reut_misc_odt_ctrl = {
+				.raw = 0,
+			};
+			if (ctrl->lpddr) {
+				/* Only one ODT pin for ULT */
+				reut_misc_odt_ctrl.odt_on       = 1;
+				reut_misc_odt_ctrl.odt_override = 1;
+			} else if (!is_hsw_ult()) {
+				reut_misc_odt_ctrl.odt_on       = odt_matrix;
+				reut_misc_odt_ctrl.odt_override = 0xf;
+			}
+			mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), reut_misc_odt_ctrl.raw);
+		}
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			/*
+			 * Enable write leveling mode in DDR and propagate delay
+			 * values (without a write command). Stay in WL mode.
+			 */
+			union ddr_data_control_0_reg data_control_0 = {
+				.raw = ctrl->dq_control_0[channel],
+			};
+			data_control_0.wl_training_mode = 1;
+			data_control_0.tx_pi_on         = 1;
+			data_control_0.read_rf_rd       = 0;
+			data_control_0.read_rf_wr       = 1;
+			data_control_0.read_rf_rank     = rank;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		}
+		printk(BIOS_DEBUG, "\nRank %u\n", rank);
+		printk(JWRL_PLOT, "Channel\t");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(JWRL_PLOT, "%u", channel);
+			if (channel > 0)
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(JWRL_PLOT, "\t");
+		}
+		printk(JWRL_PLOT, "\nByte");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+				printk(JWRL_PLOT, "\t%u", byte);
+		}
+		printk(JWRL_PLOT, "\nWlDelay");
+		for (uint16_t wl_delay = wl_start; wl_delay < wl_stop; wl_delay += wl_step) {
+			printk(JWRL_PLOT, "\n %3u:", wl_delay);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					update_txt(ctrl, channel, rank, byte, TXT_TXDQS,
+						wl_delay);
+				}
+			}
+			/* Wait for the first burst to finish */
+			if (wl_delay == wl_start)
+				udelay(wait_time_us);
+
+			io_reset();
+			udelay(wait_time_us);
+			for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+					const uint32_t feedback =
+						get_data_train_feedback(channel, byte);
+					const bool pass = (feedback & 0x1ff) >= 16;
+					printk(JWRL_PLOT, "\t%c%u", pass ? '.' : '#', feedback);
+					phase_record_pass(
+						&region_data[channel][byte],
+						pass,
+						wl_delay,
+						wl_start,
+						wl_step);
+				}
+			}
+		}
+		printk(JWRL_PLOT, "\n");
+		printk(BIOS_DEBUG, "\n\tInitSt\tInitEn\tCurrSt\tCurrEn\tLargSt\tLargEn\n");
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			printk(BIOS_DEBUG, "C%u\n", channel);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				struct phase_train_data *data = &region_data[channel][byte];
+
+				phase_append_initial_to_current(data, wl_start, wl_step);
+				printk(BIOS_DEBUG, "   B%u:\t%d\t%d\t%d\t%d\t%d\t%d\n",
+					byte,
+					data->initial.start,
+					data->initial.end,
+					data->current.start,
+					data->current.end,
+					data->largest.start,
+					data->largest.end);
+			}
+		}
+
+		/*
+		 * Clean up after test. Very coarsely adjust for
+		 * any cycle errors. Program values for TxDQS.
+		 */
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			/* Clear ODT before MRS (JEDEC spec) */
+			mchbar_write32(REUT_ch_MISC_ODT_CTRL(channel), 0);
+
+			/** TODO: Differs for LPDDR **/
+			const uint16_t mr1reg = ctrl->mr1[channel][rank / 2] | MR1_QOFF_ENABLE;
+			reut_issue_mrs(ctrl, channel, BIT(rank), 1, mr1reg);
+
+			printk(BIOS_DEBUG, "\nC%u.R%u:  LftEdge Width\n", channel, rank);
+			const bool rank_x16 = ctrl->dimms[channel][rank / 2].data.width == 16;
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				struct phase_train_data *data = &region_data[channel][byte];
+				const int32_t lwidth = range_width(data->largest);
+				int32_t tx_start = data->largest.start;
+				printk(BIOS_DEBUG, "  B%u:   %d\t%d\n", byte, tx_start, lwidth);
+				status = verify_wl_width(lwidth);
+				if (status) {
+					printk(BIOS_ERR,
+						"WrLevel problems on channel %u, byte %u\n",
+						channel, byte);
+					goto clean_up;
+				}
+
+				/* Align byte pairs if DIMM is x16 */
+				if (rank_x16 && (byte & 1)) {
+					const struct phase_train_data *const ref_data =
+							&region_data[channel][byte - 1];
+
+					if (tx_start > ref_data->largest.start + 64)
+						tx_start -= 128;
+
+					if (tx_start < ref_data->largest.start - 64)
+						tx_start += 128;
+				}
+
+				/* Fix for b4618067 - need to add 1 QCLK to DQS PI */
+				if (is_hsw_ult())
+					tx_start += 64;
+
+				assert(tx_start >= 0);
+				ctrl->txdqs[channel][rank][byte] = tx_start;
+				ctrl->tx_dq[channel][rank][byte] = tx_start + 32;
+				update_txt(ctrl, channel, rank, byte, TXT_RESTORE, 0);
+			}
+		}
+		printk(BIOS_DEBUG, "\n");
+	}
+
+clean_up:
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			mchbar_write32(DQ_CONTROL_2(channel, byte),
+				ctrl->dq_control_2[channel][byte]);
+		}
+	}
+	if (!ctrl->lpddr)
+		ddr3_program_mr1(ctrl, 0, 0);
+
+	ctrl->restore_mrs = save_restore_mrs;
+
+	if (status)
+		return status;
+
+	/** TODO: If this step fails and dec_wrd is set, clear it and try again **/
+	return train_jedec_write_leveling_cleanup(ctrl);
+}
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index 6a31d3a32c..7c0b5a49de 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -121,6 +121,8 @@
+ 
+ #define REUT_ch_ERR_DATA_MASK(ch)		_MCMAIN_C(0x40d8, ch)
+ 
+#define REUT_ch_ERR_MISC_STATUS(ch)		_MCMAIN_C(0x40e8, ch)
+
+ #define REUT_ch_MISC_CKE_CTRL(ch)		_MCMAIN_C(0x4190, ch)
+ #define REUT_ch_MISC_ODT_CTRL(ch)		_MCMAIN_C(0x4194, ch)
+ #define REUT_ch_MISC_PAT_CADB_CTRL(ch)		_MCMAIN_C(0x4198, ch)
+-- 
+2.39.2
+
@@ -0,0 +1,570 @@
+From e30c9c431ef11d87c6f46071ec43cc34391b8349 Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sun, 8 May 2022 14:29:05 +0200
+Subject: [PATCH 15/17] haswell NRI: Add final raminit steps
+
+Implement the remaining raminit steps. Although many training steps are
+missing, this is enough to boot on the Asrock B85M Pro4.
+
+Change-Id: I94f3b65f0218d4da4fda4d84592dfd91f77f8f21
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ src/northbridge/intel/haswell/Kconfig         |   4 +-
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/activate_mc.c      | 388 ++++++++++++++++++
+ .../haswell/native_raminit/raminit_main.c     |   5 +-
+ .../haswell/native_raminit/raminit_native.c   |   5 +-
+ .../haswell/native_raminit/raminit_native.h   |   2 +
+ .../haswell/native_raminit/reg_structs.h      |  12 +
+ .../intel/haswell/registers/mchbar.h          |   7 +
+ 8 files changed, 416 insertions(+), 8 deletions(-)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/activate_mc.c
+
+diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
+index 4b83a25bc1..c6ab27184e 100644
+--- a/src/northbridge/intel/haswell/Kconfig
+++ b/src/northbridge/intel/haswell/Kconfig
+@@ -11,12 +11,12 @@ config NORTHBRIDGE_INTEL_HASWELL
+ if NORTHBRIDGE_INTEL_HASWELL
+ 
+ config USE_NATIVE_RAMINIT
+-	bool "[NOT WORKING] Use native raminit"
+	bool "[NOT COMPLETE] Use native raminit"
+ 	default n
+ 	select HAVE_DEBUG_RAM_SETUP
+ 	help
+ 	  Select if you want to use coreboot implementation of raminit rather than
+-	  MRC.bin. Currently incomplete and does not boot.
+	  MRC.bin. Currently incomplete and does not support S3 resume.
+ 
+ config HASWELL_VBOOT_IN_BOOTBLOCK
+ 	depends on VBOOT
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index 40c2f5e014..d97da72890 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -1,5 +1,6 @@
+ ## SPDX-License-Identifier: GPL-2.0-or-later
+ 
+romstage-y += activate_mc.c
+ romstage-y += change_margin.c
+ romstage-y += configure_mc.c
+ romstage-y += ddr3.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
+new file mode 100644
+index 0000000000..78a7ad27ef
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
+@@ -0,0 +1,388 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/pci_ops.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <timer.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+static void update_internal_clocks_on(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		bool clocks_on = false;
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			const union ddr_data_control_1_reg data_control_1 = {
+				.raw = ctrl->dq_control_1[channel][byte],
+			};
+			const int8_t o_on = data_control_1.odt_delay;
+			const int8_t s_on = data_control_1.sense_amp_delay;
+			const int8_t o_off = data_control_1.odt_duration;
+			const int8_t s_off = data_control_1.sense_amp_duration;
+			if (o_on + o_off >= 7 || s_on + s_off >= 7) {
+				clocks_on = true;
+				break;
+			}
+		}
+		union ddr_data_control_0_reg data_control_0 = {
+			.raw = ctrl->dq_control_0[channel],
+		};
+		data_control_0.internal_clocks_on = clocks_on;
+		ctrl->dq_control_0[channel] = data_control_0.raw;
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+	}
+}
+
+/* Switch off unused segments of the SDLL to save power */
+static void update_sdll_length(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			uint8_t max_pi = 0;
+			for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				const uint8_t rx_dqs_p = ctrl->rxdqsp[channel][rank][byte];
+				const uint8_t rx_dqs_n = ctrl->rxdqsn[channel][rank][byte];
+				max_pi = MAX(max_pi, MAX(rx_dqs_p, rx_dqs_n));
+			}
+			/* Update SDLL length for power savings */
+			union ddr_data_control_1_reg data_control_1 = {
+				.raw = ctrl->dq_control_1[channel][byte],
+			};
+			/* Calculate which segments to turn off */
+			data_control_1.sdll_segment_disable = (7 - (max_pi >> 3)) & ~1;
+			ctrl->dq_control_1[channel][byte] = data_control_1.raw;
+			mchbar_write32(DQ_CONTROL_1(channel, byte), data_control_1.raw);
+		}
+	}
+}
+
+static void set_rx_clk_stg_num(struct sysinfo *ctrl, const uint8_t channel)
+{
+	const uint8_t rcven_drift = ctrl->lpddr ? DIV_ROUND_UP(tDQSCK_DRIFT, ctrl->qclkps) : 1;
+	uint8_t max_rcven = 0;
+	for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+		if (!rank_in_ch(ctrl, rank, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			max_rcven = MAX(max_rcven, ctrl->rcven[channel][rank][byte] / 64);
+	}
+	const union ddr_data_control_1_reg ddr_data_control_1 = {
+		.raw = ctrl->dq_control_1[channel][0],
+	};
+	const bool lpddr_long_odt = ddr_data_control_1.lpddr_long_odt_en;
+	const uint8_t rcven_turnoff = max_rcven + 18 + 2 * rcven_drift + lpddr_long_odt;
+	const union ddr_data_control_0_reg ddr_data_control_0 = {
+		.raw = ctrl->dq_control_0[channel],
+	};
+	for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+		union ddr_data_control_2_reg ddr_data_control_2 = {
+			.raw = ctrl->dq_control_2[channel][byte],
+		};
+		if (ddr_data_control_0.odt_samp_extend_en) {
+			if (ddr_data_control_2.rx_clk_stg_num < rcven_turnoff)
+				ddr_data_control_2.rx_clk_stg_num = rcven_turnoff;
+		} else {
+			const int8_t o_on = ddr_data_control_1.odt_delay;
+			const int8_t o_off = ddr_data_control_1.odt_duration;
+			ddr_data_control_2.rx_clk_stg_num = MAX(17, o_on + o_off + 14);
+		}
+		ctrl->dq_control_2[channel][byte] = ddr_data_control_2.raw;
+		mchbar_write32(DQ_CONTROL_2(channel, byte), ddr_data_control_2.raw);
+	}
+}
+
+#define SELF_REFRESH_IDLE_COUNT 0x200
+
+static void enter_sr(void)
+{
+	mchbar_write32(PM_SREF_CONFIG, SELF_REFRESH_IDLE_COUNT | BIT(16));
+	udelay(1);
+}
+
+enum power_down_mode {
+	PDM_NO_PD	= 0,
+	PDM_APD		= 1,
+	PDM_PPD		= 2,
+	PDM_PPD_DLL_OFF	= 6,
+};
+
+static void power_down_config(struct sysinfo *ctrl)
+{
+	const enum power_down_mode pd_mode = ctrl->lpddr ? PDM_PPD : PDM_PPD_DLL_OFF;
+	mchbar_write32(PM_PDWN_CONFIG, pd_mode << 12 | 0x40);
+}
+
+static void train_power_modes_post(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		/* Adjust tCPDED and tPRPDEN */
+		if (ctrl->mem_clock_mhz >= 933)
+			ctrl->tc_bankrank_d[channel].tCPDED = 2;
+
+		if (ctrl->mem_clock_mhz >= 1066)
+			ctrl->tc_bankrank_d[channel].tPRPDEN = 2;
+
+		mchbar_write32(TC_BANK_RANK_D_ch(channel), ctrl->tc_bankrank_d[channel].raw);
+	}
+	power_down_config(ctrl);
+	mchbar_write32(MCDECS_CBIT, BIT(30));	/* dis_msg_clk_gate */
+}
+
+static uint8_t compute_burst_end_odt_delay(const struct sysinfo *const ctrl)
+{
+	/* Must be disabled for LPDDR */
+	if (ctrl->lpddr)
+		return 0;
+
+	const uint8_t beod = MIN(7, DIV_ROUND_CLOSEST(14300 * 20 / 100, ctrl->qclkps));
+	if (beod < 3)
+		return 0;
+
+	if (beod < 4)
+		return 4;
+
+	return beod;
+}
+
+static void program_burst_end_odt_delay(struct sysinfo *ctrl)
+{
+	/* Program burst_end_odt_delay - it should be zero during training steps */
+	const uint8_t beod = compute_burst_end_odt_delay(ctrl);
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			union ddr_data_control_1_reg ddr_data_control_1 = {
+				.raw = ctrl->dq_control_1[channel][byte],
+			};
+			ddr_data_control_1.burst_end_odt_delay = beod;
+			ctrl->dq_control_1[channel][byte] = ddr_data_control_1.raw;
+			mchbar_write32(DQ_CONTROL_1(channel, byte), ddr_data_control_1.raw);
+		}
+	}
+}
+
+/*
+ * Return a random value to use for scrambler seeds. Try to use RDRAND
+ * first and fall back to hardcoded values if RDRAND does not succeed.
+ */
+static uint16_t get_random_number(const uint8_t channel)
+{
+	/* The RDRAND instruction is only available 100k cycles after reset */
+	for (size_t i = 0; i < 100000; i++) {
+		uint32_t status;
+		uint32_t random;
+		/** TODO: Clean up asm **/
+		__asm__ __volatile__(
+			"\n\t .byte 0x0F, 0xC7, 0xF0"
+			"\n\t movl %%eax, %0"
+			"\n\t pushf"
+			"\n\t pop %%eax"
+			"\n\t movl %%eax, %1"
+			: "=m"(random),
+			  "=m"(status)
+			: /* No inputs */
+			: "eax", "cc");
+
+		/* Only consider non-zero random values as valid */
+		if (status & 1 && random)
+			return random;
+	}
+
+	/* https://xkcd.com/221 */
+	if (channel)
+		return 0x28f4;
+	else
+		return 0x893e;
+}
+
+/* Work around "error: 'typeof' applied to a bit-field" */
+static inline uint32_t max(const uint32_t a, const uint32_t b)
+{
+	return MAX(a, b);
+}
+
+enum raminit_status activate_mc(struct sysinfo *ctrl)
+{
+	const bool enable_scrambling = true;
+	const bool enable_cmd_tristate = true;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		if (enable_scrambling && ctrl->stepping < STEPPING_C0) {
+			/* Make sure tRDRD_(sr, dr, dd) are at least 6 for scrambler W/A */
+			union tc_bank_rank_a_reg tc_bank_rank_a = {
+				.raw = mchbar_read32(TC_BANK_RANK_A_ch(channel)),
+			};
+			tc_bank_rank_a.tRDRD_sr = max(tc_bank_rank_a.tRDRD_sr, 6);
+			tc_bank_rank_a.tRDRD_dr = max(tc_bank_rank_a.tRDRD_dr, 6);
+			tc_bank_rank_a.tRDRD_dd = max(tc_bank_rank_a.tRDRD_dd, 6);
+			mchbar_write32(TC_BANK_RANK_A_ch(channel), tc_bank_rank_a.raw);
+		}
+		if (enable_scrambling) {
+			const union ddr_scramble_reg ddr_scramble = {
+				.scram_key = get_random_number(channel),
+				.scram_en  = 1,
+			};
+			mchbar_write32(DDR_SCRAMBLE_ch(channel), ddr_scramble.raw);
+		}
+		if (ctrl->tCMD == 1) {
+			/* If we are in 1N mode, enable and set command rate limit to 3 */
+			union mcmain_command_rate_limit_reg cmd_rate_limit = {
+				.raw = mchbar_read32(COMMAND_RATE_LIMIT_ch(channel)),
+			};
+			cmd_rate_limit.enable_cmd_limit = 1;
+			cmd_rate_limit.cmd_rate_limit   = 3;
+			mchbar_write32(COMMAND_RATE_LIMIT_ch(channel), cmd_rate_limit.raw);
+		}
+		if (enable_cmd_tristate) {
+			/* Enable command tri-state at the end of training */
+			union tc_bank_rank_a_reg tc_bank_rank_a = {
+				.raw = mchbar_read32(TC_BANK_RANK_A_ch(channel)),
+			};
+			tc_bank_rank_a.cmd_3st_dis = 0;
+			mchbar_write32(TC_BANK_RANK_A_ch(channel), tc_bank_rank_a.raw);
+		}
+		/* Set MC to normal mode and clean the ODT and CKE */
+		mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12);
+		/* Set again the rank occupancy */
+		mchbar_write8(MC_INIT_STATE_ch(channel), ctrl->rankmap[channel]);
+		if (ctrl->is_ecc) {
+			/* Enable ECC I/O and logic */
+			union mad_dimm_reg mad_dimm = {
+				.raw = mchbar_read32(MAD_DIMM(channel)),
+			};
+			mad_dimm.ecc_mode = 3;
+			mchbar_write32(MAD_DIMM(channel), mad_dimm.raw);
+		}
+	}
+
+	if (!is_hsw_ult())
+		update_internal_clocks_on(ctrl);
+
+	update_sdll_length(ctrl);
+
+	program_burst_end_odt_delay(ctrl);
+
+	if (is_hsw_ult()) {
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			set_rx_clk_stg_num(ctrl, channel);
+		}
+		/** TODO: Program DDRPL_CR_DDR_TX_DELAY if Memory Trace is enabled **/
+	}
+
+	/* Enable periodic COMP */
+	mchbar_write32(M_COMP, (union pcu_comp_reg) {
+		.comp_interval = COMP_INT,
+	}.raw);
+
+	/* Enable the power mode before PCU starts working */
+	train_power_modes_post(ctrl);
+
+	/* Set idle timer and self refresh enable bits */
+	enter_sr();
+
+	/** FIXME: Do not hardcode power weights and RAPL settings **/
+	mchbar_write32(0x5888, 0x00000d0d);
+	mchbar_write32(0x5884, 0x00000004);	/* 58.2 pJ */
+
+	mchbar_write32(0x58e0, 0);
+	mchbar_write32(0x58e4, 0);
+
+	mchbar_write32(0x5890, 0xffff);
+	mchbar_write32(0x5894, 0xffff);
+	mchbar_write32(0x5898, 0xffff);
+	mchbar_write32(0x589c, 0xffff);
+	mchbar_write32(0x58d0, 0xffff);
+	mchbar_write32(0x58d4, 0xffff);
+	mchbar_write32(0x58d8, 0xffff);
+	mchbar_write32(0x58dc, 0xffff);
+
+	/* Overwrite thermal parameters */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		mchbar_write32(_MCMAIN_C(0x42ec, channel), 0x0000000f);
+		mchbar_write32(_MCMAIN_C(0x42f0, channel), 0x00000009);
+		mchbar_write32(_MCMAIN_C(0x42f4, channel), 0x00000093);
+		mchbar_write32(_MCMAIN_C(0x42f8, channel), 0x00000087);
+		mchbar_write32(_MCMAIN_C(0x42fc, channel), 0x000000de);
+
+		/** TODO: Differs for LPDDR **/
+		mchbar_write32(PM_THRT_CKE_MIN_ch(channel), 0x30);
+	}
+	mchbar_write32(PCU_DDR_PTM_CTL, 0x40);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+static void mc_lockdown(void)
+{
+	/* Lock memory controller registers */
+	mchbar_write32(MC_LOCK, 0x8f);
+
+	/* MPCOHTRK_GDXC_OCLA_ADDRESS_HI_LOCK is set when programming the memory map */
+
+	/* Lock memory map registers */
+	pci_or_config16(HOST_BRIDGE, GGC,         1 <<  0);
+	pci_or_config32(HOST_BRIDGE, DPR,         1 <<  0);
+	pci_or_config32(HOST_BRIDGE, MESEG_LIMIT, 1 << 10);
+	pci_or_config32(HOST_BRIDGE, REMAPBASE,   1 <<  0);
+	pci_or_config32(HOST_BRIDGE, REMAPLIMIT,  1 <<  0);
+	pci_or_config32(HOST_BRIDGE, TOM,         1 <<  0);
+	pci_or_config32(HOST_BRIDGE, TOUUD,       1 <<  0);
+	pci_or_config32(HOST_BRIDGE, BDSM,        1 <<  0);
+	pci_or_config32(HOST_BRIDGE, BGSM,        1 <<  0);
+	pci_or_config32(HOST_BRIDGE, TOLUD,       1 <<  0);
+}
+
+enum raminit_status raminit_done(struct sysinfo *ctrl)
+{
+	union mc_init_state_g_reg mc_init_state_g = {
+		.raw = mchbar_read32(MC_INIT_STATE_G),
+	};
+	mc_init_state_g.refresh_enable = 1;
+	mc_init_state_g.pu_mrc_done    = 1;
+	mc_init_state_g.mrc_done       = 1;
+	mchbar_write32(MC_INIT_STATE_G, mc_init_state_g.raw);
+
+	/* Lock the memory controller to enable normal operation */
+	mc_lockdown();
+
+	/* Poll for mc_init_done_ack to make sure memory initialization is complete */
+	printk(BIOS_DEBUG, "Waiting for mc_init_done acknowledgement... ");
+
+	struct stopwatch timer;
+	stopwatch_init_msecs_expire(&timer, 2000);
+	do {
+		mc_init_state_g.raw = mchbar_read32(MC_INIT_STATE_G);
+
+		/* DRAM will NOT work without the acknowledgement. There is no hope. */
+		if (stopwatch_expired(&timer))
+			die("\nTimed out waiting for mc_init_done acknowledgement\n");
+
+	} while (mc_init_state_g.mc_init_done_ack == 0);
+	printk(BIOS_DEBUG, "DONE!\n");
+
+	/* Provide some data for the graphics driver. Yes, it's hardcoded. */
+	mchbar_write32(SSKPD + 0, 0x05a2404f);
+	mchbar_write32(SSKPD + 4, 0x140000a0);
+	return RAMINIT_STATUS_SUCCESS;
+}
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index 1ff23be615..3a65fb01fb 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -63,6 +63,8 @@ static const struct task_entry cold_boot[] = {
+ 	{ train_receive_enable,                                   true, "RCVET",      },
+ 	{ train_read_mpr,                                         true, "RDMPRT",     },
+ 	{ train_jedec_write_leveling,                             true, "JWRL",       },
+	{ activate_mc,                                            true, "ACTIVATE",   },
+	{ raminit_done,                                           true, "RAMINITEND", },
+ };
+ 
+ /* Return a generic stepping value to make stepping checks simpler */
+@@ -143,7 +145,4 @@ void raminit_main(const enum raminit_boot_mode bootmode)
+ 
+ 	if (status != RAMINIT_STATUS_SUCCESS)
+ 		die("Memory initialization was met with utmost failure and misery\n");
+-
+-	/** TODO: Implement the required magic **/
+-	die("NATIVE RAMINIT: More Magic (tm) required.\n");
+ }
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+index 2fed93de5b..5f7ceec222 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+@@ -199,8 +199,6 @@ void perform_raminit(const int s3resume)
+ 		else
+ 			me_status = ME_INIT_STATUS_SUCCESS;
+ 
+-		/** TODO: Remove this once raminit is implemented **/
+-		me_status = ME_INIT_STATUS_ERROR;
+ 		intel_early_me_init_done(me_status);
+ 	}
+ 
+@@ -214,7 +212,8 @@ void perform_raminit(const int s3resume)
+ 	}
+ 
+ 	/* Save training data on non-S3 resumes */
+-	if (!s3resume)
+	/** TODO: Enable this once training data is populated **/
+	if (0 && !s3resume)
+ 		save_mrc_data(&md);
+ 
+ 	/** TODO: setup_sdram_meminfo **/
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index d6b11b9d3c..a0a913f926 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -448,6 +448,8 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+ enum raminit_status train_receive_enable(struct sysinfo *ctrl);
+ enum raminit_status train_read_mpr(struct sysinfo *ctrl);
+ enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+enum raminit_status activate_mc(struct sysinfo *ctrl);
+enum raminit_status raminit_done(struct sysinfo *ctrl);
+ 
+ void configure_timings(struct sysinfo *ctrl);
+ void configure_refresh(struct sysinfo *ctrl);
+diff --git a/src/northbridge/intel/haswell/native_raminit/reg_structs.h b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+index a0e36ed082..0d9aaa1f7c 100644
+--- a/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+++ b/src/northbridge/intel/haswell/native_raminit/reg_structs.h
+@@ -294,6 +294,18 @@ union ddr_cke_ctl_controls_reg {
+ 	uint32_t raw;
+ };
+ 
+union ddr_scramble_reg {
+	struct __packed {
+		uint32_t scram_en    :  1; // Bits  0:0
+		uint32_t scram_key   : 16; // Bits 16:1
+		uint32_t clk_gate_ab :  2; // Bits 18:17
+		uint32_t clk_gate_c  :  2; // Bits 20:19
+		uint32_t en_dbi_ab   :  1; // Bits 21:21
+		uint32_t             : 10; // Bits 31:17
+	};
+	uint32_t raw;
+};
+
+ union ddr_scram_misc_control_reg {
+ 	struct __packed {
+ 		uint32_t wl_wake_cycles       :  2; // Bits  1:0
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index 7c0b5a49de..49a215aa71 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -20,6 +20,7 @@
+ 
+ #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
+ 
+#define DQ_CONTROL_1(ch, byte)			_DDRIO_C_R_B(0x0060, ch, 0, byte)
+ #define DQ_CONTROL_2(ch, byte)			_DDRIO_C_R_B(0x0064, ch, 0, byte)
+ #define DDR_DATA_OFFSET_TRAIN_ch_b(ch, byte)	_DDRIO_C_R_B(0x0070, ch, 0, byte)
+ #define DQ_CONTROL_0(ch, byte)			_DDRIO_C_R_B(0x0074, ch, 0, byte)
+@@ -147,6 +148,8 @@
+ #define QCLK_ch_LDAT_SDAT(ch)			_MCMAIN_C(0x42d4, ch)
+ #define QCLK_ch_LDAT_DATA_IN_x(ch, x)		_MCMAIN_C_X(0x42dc, ch, x) /* x in 0 .. 1 */
+ 
+#define PM_THRT_CKE_MIN_ch(ch)			_MCMAIN_C(0x4328, ch)
+
+ #define REUT_GLOBAL_CTL				0x4800
+ #define REUT_GLOBAL_ERR				0x4804
+ 
+@@ -175,6 +178,8 @@
+ 
+ #define MCSCHEDS_DFT_MISC	0x4c30
+ 
+#define PM_PDWN_CONFIG		0x4cb0
+
+ #define REUT_ERR_DATA_STATUS	0x4ce0
+ 
+ #define REUT_MISC_CKE_CTRL	0x4d90
+@@ -186,8 +191,10 @@
+ #define MAD_CHNL		0x5000 /* Address Decoder Channel Configuration */
+ #define MAD_DIMM(ch)		(0x5004 + (ch) * 4)
+ #define MAD_ZR			0x5014
+#define MCDECS_CBIT		0x501c
+ #define MC_INIT_STATE_G		0x5030
+ #define MRC_REVISION		0x5034 /* MRC Revision */
+#define PM_SREF_CONFIG		0x5060
+ 
+ #define RCOMP_TIMER		0x5084
+ 
+-- 
+2.39.2
+
@@ -0,0 +1,722 @@
+From 50c9d184cc89cd718c1cb95e1a3cabed24e09e1e Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Sat, 13 Apr 2024 01:16:30 +0200
+Subject: [PATCH 16/17] Haswell NRI: Implement fast boot path
+
+When the memory configuration hasn't changed, there is no need to do
+full memory training. Instead, boot firmware can use saved training
+data to reinitialise the memory controller and memory.
+
+Unlike native RAM init for other platforms, Haswell does not save the
+main structure (the "mighty ctrl" struct) to flash. Instead, separate
+structures define the data to be saved, which can be smaller than the
+main structure.
+
+This makes S3 suspend and resume work: RAM contents MUST be preserved
+for a S3 resume to succeed, but RAM training destroys RAM contents.
+
+Change-Id: I06f6cd39ceecdca104fae89159f28e85cf7ff4e6
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/activate_mc.c      |  17 +
+ .../intel/haswell/native_raminit/ddr3.c       |  41 ++
+ .../haswell/native_raminit/raminit_main.c     |  34 +-
+ .../haswell/native_raminit/raminit_native.c   |  30 +-
+ .../haswell/native_raminit/raminit_native.h   |  18 +
+ .../haswell/native_raminit/save_restore.c     | 387 ++++++++++++++++++
+ 7 files changed, 504 insertions(+), 24 deletions(-)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/save_restore.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index d97da72890..8fdd17c542 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -13,6 +13,7 @@ romstage-y += raminit_main.c
+ romstage-y += raminit_native.c
+ romstage-y += ranges.c
+ romstage-y += reut.c
+romstage-y += save_restore.c
+ romstage-y += setup_wdb.c
+ romstage-y += spd_bitmunching.c
+ romstage-y += testing_io.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
+index 78a7ad27ef..0b3eb917da 100644
+--- a/src/northbridge/intel/haswell/native_raminit/activate_mc.c
+++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
+@@ -333,6 +333,23 @@ enum raminit_status activate_mc(struct sysinfo *ctrl)
+ 	return RAMINIT_STATUS_SUCCESS;
+ }
+ 
+enum raminit_status normal_state(struct sysinfo *ctrl)
+{
+	/* Enable periodic COMP */
+	mchbar_write32(M_COMP, (union pcu_comp_reg) {
+		.comp_interval = COMP_INT,
+	}.raw);
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		/* Set MC to normal mode and clean the ODT and CKE */
+		mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12);
+	}
+	power_down_config(ctrl);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+ static void mc_lockdown(void)
+ {
+ 	/* Lock memory controller registers */
+diff --git a/src/northbridge/intel/haswell/native_raminit/ddr3.c b/src/northbridge/intel/haswell/native_raminit/ddr3.c
+index 6ddb11488b..9b6368edb1 100644
+--- a/src/northbridge/intel/haswell/native_raminit/ddr3.c
+++ b/src/northbridge/intel/haswell/native_raminit/ddr3.c
+@@ -2,6 +2,7 @@
+ 
+ #include <assert.h>
+ #include <console/console.h>
+#include <delay.h>
+ #include <northbridge/intel/haswell/haswell.h>
+ #include <types.h>
+ 
+@@ -215,3 +216,43 @@ enum raminit_status ddr3_jedec_init(struct sysinfo *ctrl)
+ 	ddr3_program_mr0(ctrl, 1);
+ 	return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT);
+ }
+
+enum raminit_status exit_selfrefresh(struct sysinfo *ctrl)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		/* Fields in ctrl aren't populated on a warm boot */
+		union ddr_data_control_0_reg data_control_0 = {
+			.raw = mchbar_read32(DQ_CONTROL_0(channel, 0)),
+		};
+		data_control_0.read_rf_rd = 1;
+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+			if (!rank_in_ch(ctrl, rank, channel))
+				continue;
+
+			data_control_0.read_rf_rank = rank;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		}
+	}
+
+	/* Time needed to stabilize the DCLK (~6 us) */
+	udelay(6);
+
+	/* Pull the DIMMs out of self refresh by asserting CKE high */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		const union reut_misc_cke_ctrl_reg reut_misc_cke_ctrl = {
+			.cke_on = ctrl->rankmap[channel],
+		};
+		mchbar_write32(REUT_ch_MISC_CKE_CTRL(channel), reut_misc_cke_ctrl.raw);
+	}
+	mchbar_write32(REUT_MISC_ODT_CTRL, 0);
+
+	const enum raminit_status status = reut_issue_zq(ctrl, ctrl->chanmap, ZQ_LONG);
+	if (status) {
+		/* ZQCL errors don't seem to be a fatal problem here */
+		printk(BIOS_ERR, "ZQ Long failed during S3 resume or warm reset flow\n");
+	}
+	return RAMINIT_STATUS_SUCCESS;
+}
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index 3a65fb01fb..056dde1adc 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -64,6 +64,22 @@ static const struct task_entry cold_boot[] = {
+ 	{ train_read_mpr,                                         true, "RDMPRT",     },
+ 	{ train_jedec_write_leveling,                             true, "JWRL",       },
+ 	{ activate_mc,                                            true, "ACTIVATE",   },
+	{ save_training_values,                                   true, "SAVE_TRAIN", },
+	{ save_non_training,                                      true, "SAVE_NONT",  },
+	{ raminit_done,                                           true, "RAMINITEND", },
+};
+
+static const struct task_entry fast_boot[] = {
+	{ collect_spd_info,                                       true, "PROCSPD",    },
+	{ restore_non_training,                                   true, "RST_NONT",   },
+	{ initialise_mpll,                                        true, "INITMPLL",   },
+	{ configure_mc,                                           true, "CONFMC",     },
+	{ configure_memory_map,                                   true, "MEMMAP",     },
+	{ do_jedec_init,                                          true, "JEDECINIT",  },
+	{ pre_training,                                           true, "PRETRAIN",   },
+	{ restore_training_values,                                true, "RST_TRAIN",  },
+	{ exit_selfrefresh,                                       true, "EXIT_SR",    },
+	{ normal_state,                                           true, "NORMALMODE", },
+ 	{ raminit_done,                                           true, "RAMINITEND", },
+ };
+ 
+@@ -102,11 +118,11 @@ static void initialize_ctrl(struct sysinfo *ctrl)
+ 	ctrl->bootmode = bootmode;
+ }
+ 
+-static enum raminit_status try_raminit(struct sysinfo *ctrl)
+static enum raminit_status try_raminit(
+	struct sysinfo *ctrl,
+	const struct task_entry *const schedule,
+	const size_t length)
+ {
+-	const struct task_entry *const schedule = cold_boot;
+-	const size_t length = ARRAY_SIZE(cold_boot);
+-
+ 	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
+ 
+ 	for (size_t i = 0; i < length; i++) {
+@@ -140,8 +156,16 @@ void raminit_main(const enum raminit_boot_mode bootmode)
+ 	mighty_ctrl.bootmode = bootmode;
+ 	initialize_ctrl(&mighty_ctrl);
+ 
+	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
+
+	if (bootmode != BOOTMODE_COLD) {
+		status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot));
+		if (status == RAMINIT_STATUS_SUCCESS)
+			return;
+	}
+
+ 	/** TODO: Try more than once **/
+-	enum raminit_status status = try_raminit(&mighty_ctrl);
+	status = try_raminit(&mighty_ctrl, cold_boot, ARRAY_SIZE(cold_boot));
+ 
+ 	if (status != RAMINIT_STATUS_SUCCESS)
+ 		die("Memory initialization was met with utmost failure and misery\n");
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+index 5f7ceec222..3ad8ce29e7 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
+@@ -54,23 +54,17 @@ static bool early_init_native(enum raminit_boot_mode bootmode)
+ 	return cpu_replaced;
+ }
+ 
+-#define MRC_CACHE_VERSION 1
+-
+-struct mrc_data {
+-	const void *buffer;
+-	size_t buffer_len;
+-};
+-
+-static void save_mrc_data(struct mrc_data *md)
+static void save_mrc_data(void)
+ {
+-	mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len);
+	mrc_cache_stash_data(MRC_TRAINING_DATA, reg_frame_rev(),
+			     reg_frame_ptr(), reg_frame_size());
+ }
+ 
+ static struct mrc_data prepare_mrc_cache(void)
+ {
+ 	struct mrc_data md = {0};
+ 	md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
+-						MRC_CACHE_VERSION,
+						reg_frame_rev(),
+ 						&md.buffer_len);
+ 	return md;
+ }
+@@ -94,14 +88,15 @@ static void raminit_reset(void)
+ }
+ 
+ static enum raminit_boot_mode do_actual_raminit(
+-	struct mrc_data *md,
+ 	const bool s3resume,
+ 	const bool cpu_replaced,
+ 	const enum raminit_boot_mode orig_bootmode)
+ {
+	struct mrc_data md = prepare_mrc_cache();
+
+ 	enum raminit_boot_mode bootmode = orig_bootmode;
+ 
+-	bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/
+	bool save_data_valid = md.buffer && md.buffer_len == reg_frame_size();
+ 
+ 	if (s3resume) {
+ 		if (bootmode == BOOTMODE_COLD) {
+@@ -154,7 +149,7 @@ static enum raminit_boot_mode do_actual_raminit(
+ 	assert(save_data_valid != (bootmode == BOOTMODE_COLD));
+ 	if (save_data_valid) {
+ 		printk(BIOS_INFO, "Using cached memory parameters\n");
+-		die("RAMINIT: Fast boot is not yet implemented\n");
+		memcpy(reg_frame_ptr(), md.buffer, reg_frame_size());
+ 	}
+ 	printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]);
+ 	printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]);
+@@ -181,10 +176,8 @@ void perform_raminit(const int s3resume)
+ 	wait_txt_clear();
+ 	wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
+ 
+-	struct mrc_data md = prepare_mrc_cache();
+-
+ 	const enum raminit_boot_mode bootmode =
+-			do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode);
+			do_actual_raminit(s3resume, cpu_replaced, orig_bootmode);
+ 
+ 	/** TODO: report_memory_config **/
+ 
+@@ -212,9 +205,8 @@ void perform_raminit(const int s3resume)
+ 	}
+ 
+ 	/* Save training data on non-S3 resumes */
+-	/** TODO: Enable this once training data is populated **/
+-	if (0 && !s3resume)
+-		save_mrc_data(&md);
+	if (!s3resume)
+		save_mrc_data();
+ 
+ 	/** TODO: setup_sdram_meminfo **/
+ }
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index a0a913f926..2ac16eaad3 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -170,6 +170,8 @@ enum regfile_mode {
+ 	REG_FILE_USE_CURRENT,	/* Used when changing parameters after the test */
+ };
+ 
+struct register_save_frame;
+
+ struct wdb_pat {
+ 	uint32_t start_ptr;	/* Starting pointer in WDB */
+ 	uint32_t stop_ptr;	/* Stopping pointer in WDB */
+@@ -220,6 +222,7 @@ enum raminit_status {
+ 	RAMINIT_STATUS_RCVEN_FAILURE,
+ 	RAMINIT_STATUS_RMPR_FAILURE,
+ 	RAMINIT_STATUS_JWRL_FAILURE,
+	RAMINIT_STATUS_INVALID_CACHE,
+ 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
+ };
+ 
+@@ -229,6 +232,11 @@ enum generic_stepping {
+ 	STEPPING_C0 = 3,
+ };
+ 
+struct mrc_data {
+	const void *buffer;
+	size_t buffer_len;
+};
+
+ struct raminit_dimm_info {
+ 	spd_ddr3_raw_data raw_spd;
+ 	struct dimm_attr_ddr3_st data;
+@@ -448,12 +456,22 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+ enum raminit_status train_receive_enable(struct sysinfo *ctrl);
+ enum raminit_status train_read_mpr(struct sysinfo *ctrl);
+ enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+enum raminit_status save_training_values(struct sysinfo *ctrl);
+enum raminit_status restore_training_values(struct sysinfo *ctrl);
+enum raminit_status save_non_training(struct sysinfo *ctrl);
+enum raminit_status restore_non_training(struct sysinfo *ctrl);
+enum raminit_status exit_selfrefresh(struct sysinfo *ctrl);
+enum raminit_status normal_state(struct sysinfo *ctrl);
+ enum raminit_status activate_mc(struct sysinfo *ctrl);
+ enum raminit_status raminit_done(struct sysinfo *ctrl);
+ 
+ void configure_timings(struct sysinfo *ctrl);
+ void configure_refresh(struct sysinfo *ctrl);
+ 
+struct register_save_frame *reg_frame_ptr(void);
+size_t reg_frame_size(void);
+uint32_t reg_frame_rev(void);
+
+ uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
+ uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
+ uint32_t get_tAONPD(uint32_t mem_clock_mhz);
+diff --git a/src/northbridge/intel/haswell/native_raminit/save_restore.c b/src/northbridge/intel/haswell/native_raminit/save_restore.c
+new file mode 100644
+index 0000000000..f1f50e3ff8
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/save_restore.c
+@@ -0,0 +1,387 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <console/console.h>
+#include <northbridge/intel/haswell/haswell.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+uint32_t reg_frame_rev(void)
+{
+	/*
+	 * Equivalent to MRC_CACHE_REVISION, but hidden via abstraction.
+	 * The structures that get saved to flash are contained within
+	 * this translation unit, so changes outside this file shouldn't
+	 * require invalidating the cache.
+	 */
+	return 1;
+}
+
+struct register_save {
+	uint16_t lower;
+	uint16_t upper;
+};
+
+/** TODO: Haswell DDRIO aliases writes: 0x80 .. 0xff => 0x00 .. 0x7f **/
+static const struct register_save ddrio_per_byte_list[] = {
+	{0x0000, 0x003c}, /* 16 registers */
+//	{0x0048, 0x0084}, /* 16 registers */	/** TODO: BDW support **/
+	{0x0048, 0x004c}, /*  2 registers */
+	{0x005c, 0x0078}, /*  8 registers */
+};
+#define DDRIO_PER_BYTE_REGISTER_COUNT	(16 + 2 + 8)
+
+static const struct register_save ddrio_per_ch_list[] = {
+	/* CKE */
+	{0x1204, 0x1208}, /* 2 registers */
+	{0x1214, 0x121c}, /* 3 registers */
+	/* CMD North */
+	{0x1404, 0x140c}, /* 3 registers */
+	/* CLK */
+	{0x1808, 0x1810}, /* 3 registers */
+	/* CMD South */
+	{0x1a04, 0x1a0c}, /* 3 registers */
+	/* CTL */
+	{0x1c14, 0x1c1c}, /* 3 registers */
+};
+#define DDRIO_PER_CH_REGISTER_COUNT	(2 + 3 * 5)
+
+static const struct register_save ddrio_common_list[] = {
+	{0x2000, 0x2008}, /* 3 registers */
+	{0x3a14, 0x3a1c}, /* 3 registers */
+	{0x3a24, 0x3a24}, /* 1 registers */
+};
+
+#define DDRIO_COMMON_REGISTER_COUNT	(3 + 3 + 1)
+
+static const struct register_save mcmain_per_ch_list[] = {
+	{0x4000, 0x4014}, /* 6 registers */
+	{0x4024, 0x4028}, /* 2 registers */
+	{0x40d0, 0x40d0}, /* 1 registers */
+	{0x4220, 0x4224}, /* 2 registers */
+	{0x4294, 0x4294}, /* 1 registers */
+	{0x429c, 0x42a0}, /* 2 registers */
+	{0x42ec, 0x42fc}, /* 5 registers */
+	{0x4328, 0x4328}, /* 1 registers */
+	{0x438c, 0x4390}, /* 2 registers */
+};
+#define MCMAIN_PER_CH_REGISTER_COUNT	(6 + 2 + 1 + 2 + 1 + 2 + 5 + 1 + 2)
+
+static const struct register_save misc_common_list[] = {
+	{0x5884, 0x5888}, /*  2 registers */
+	{0x5890, 0x589c}, /*  4 registers */
+	{0x58a4, 0x58a4}, /*  1 registers */
+	{0x58d0, 0x58e4}, /*  6 registers */
+	{0x5880, 0x5880}, /*  1 registers */
+	{0x5000, 0x50dc}, /* 56 registers */
+	{0x59b8, 0x59b8}  /*  1 registers */
+};
+#define MISC_COMMON_REGISTER_COUNT	(2 + 4 + 1 + 6 + 1 + 56 + 1)
+
+struct save_params {
+	bool is_initialised;
+
+	/* Memory base frequency, either 100 or 133 MHz */
+	uint8_t base_freq;
+
+	/* Multiplier */
+	uint32_t multiplier;
+
+	/* Memory clock in MHz */
+	uint32_t mem_clock_mhz;
+
+	/* Memory clock in femtoseconds */
+	uint32_t mem_clock_fs;
+
+	/* Quadrature clock in picoseconds */
+	uint16_t qclkps;
+
+	/* Bitfield of supported CAS latencies */
+	uint16_t cas_supported;
+
+	/* CPUID value */
+	uint32_t cpu;
+
+	/* Cached CPU stepping value */
+	uint8_t stepping;
+
+	uint16_t vdd_mv;
+
+	union dimm_flags_ddr3_st flags;
+
+	/* Except for tCK, everything is stored in DCLKs */
+	uint32_t tCK;
+	uint32_t tAA;
+	uint32_t tWR;
+	uint32_t tRCD;
+	uint32_t tRRD;
+	uint32_t tRP;
+	uint32_t tRAS;
+	uint32_t tRC;
+	uint32_t tRFC;
+	uint32_t tWTR;
+	uint32_t tRTP;
+	uint32_t tFAW;
+	uint32_t tCWL;
+	uint32_t tCMD;
+
+	uint32_t tREFI;
+	uint32_t tXP;
+
+	uint8_t lpddr_cke_rank_map[NUM_CHANNELS];
+
+	struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS];
+
+	uint8_t chanmap;
+
+	uint32_t channel_size_mb[NUM_CHANNELS];
+
+	/* DIMMs per channel */
+	uint8_t dpc[NUM_CHANNELS];
+
+	uint8_t rankmap[NUM_CHANNELS];
+
+	/* Whether a rank is mirrored or not (only rank 1 of each DIMM can be) */
+	uint8_t rank_mirrored[NUM_CHANNELS];
+
+	/*
+	 * FIXME: LPDDR support is incomplete. The largest chunks are missing,
+	 * but some LPDDR-specific variations in algorithms have been handled.
+	 * LPDDR-specific functions have stubs which will halt upon execution.
+	 */
+	bool lpddr;
+
+	uint8_t lanes;
+
+	/* FIXME: ECC support missing */
+	bool is_ecc;
+};
+
+struct register_save_frame {
+	uint32_t ddrio_per_byte[NUM_CHANNELS][NUM_LANES][DDRIO_PER_BYTE_REGISTER_COUNT];
+	uint32_t ddrio_per_ch[NUM_CHANNELS][DDRIO_PER_CH_REGISTER_COUNT];
+	uint32_t ddrio_common[DDRIO_COMMON_REGISTER_COUNT];
+	uint32_t mcmain_per_ch[NUM_CHANNELS][MCMAIN_PER_CH_REGISTER_COUNT];
+	uint32_t misc_common[MISC_COMMON_REGISTER_COUNT];
+	struct save_params params;
+};
+
+struct register_save_frame *reg_frame_ptr(void)
+{
+	/* The chonky register save frame struct, used for fast boot and S3 resume */
+	static struct register_save_frame register_frame = { 0 };
+	return &register_frame;
+}
+
+size_t reg_frame_size(void)
+{
+	return sizeof(struct register_save_frame);
+}
+
+typedef void (*reg_func_t)(const uint16_t offset, uint32_t *const value);
+
+static void save_value(const uint16_t offset, uint32_t *const value)
+{
+	*value = mchbar_read32(offset);
+}
+
+static void restore_value(const uint16_t offset, uint32_t *const value)
+{
+	mchbar_write32(offset, *value);
+}
+
+static void save_restore(
+	uint32_t *reg_frame,
+	const uint16_t g_offset,
+	const struct register_save *reg_save_list,
+	const size_t reg_save_length,
+	reg_func_t handle_reg)
+{
+	for (size_t i = 0; i < reg_save_length; i++) {
+		const struct register_save *entry = &reg_save_list[i];
+		for (uint16_t offset = entry->lower; offset <= entry->upper; offset += 4) {
+			handle_reg(offset + g_offset, reg_frame++);
+		}
+	}
+}
+
+static void save_restore_all(struct register_save_frame *reg_frame, reg_func_t handle_reg)
+{
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		for (uint8_t byte = 0; byte < NUM_LANES; byte++) {
+			const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, byte);
+			save_restore(
+				reg_frame->ddrio_per_byte[channel][byte],
+				g_offset,
+				ddrio_per_byte_list,
+				ARRAY_SIZE(ddrio_per_byte_list),
+				handle_reg);
+		}
+	}
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, 0);
+		save_restore(
+			reg_frame->ddrio_per_ch[channel],
+			g_offset,
+			ddrio_per_ch_list,
+			ARRAY_SIZE(ddrio_per_ch_list),
+			handle_reg);
+	}
+	save_restore(
+		reg_frame->ddrio_common,
+		0,
+		ddrio_common_list,
+		ARRAY_SIZE(ddrio_common_list),
+		handle_reg);
+
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		const uint16_t g_offset = _MCMAIN_C(0, channel);
+		save_restore(
+			reg_frame->mcmain_per_ch[channel],
+			g_offset,
+			mcmain_per_ch_list,
+			ARRAY_SIZE(mcmain_per_ch_list),
+			handle_reg);
+	}
+	save_restore(
+		reg_frame->misc_common,
+		0,
+		misc_common_list,
+		ARRAY_SIZE(misc_common_list),
+		handle_reg);
+}
+
+enum raminit_status save_training_values(struct sysinfo *ctrl)
+{
+	save_restore_all(reg_frame_ptr(), save_value);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+enum raminit_status restore_training_values(struct sysinfo *ctrl)
+{
+	save_restore_all(reg_frame_ptr(), restore_value);
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+enum raminit_status save_non_training(struct sysinfo *ctrl)
+{
+	struct register_save_frame *reg_frame = reg_frame_ptr();
+	struct save_params *params = &reg_frame->params;
+
+	params->is_initialised = true;
+
+	params->base_freq     = ctrl->base_freq;
+	params->multiplier    = ctrl->multiplier;
+	params->mem_clock_mhz = ctrl->mem_clock_mhz;
+	params->mem_clock_fs  = ctrl->mem_clock_fs;
+	params->qclkps        = ctrl->qclkps;
+	params->cas_supported = ctrl->cas_supported;
+	params->cpu           = ctrl->cpu;
+	params->stepping      = ctrl->stepping;
+	params->vdd_mv        = ctrl->vdd_mv;
+	params->flags         = ctrl->flags;
+
+	params->tCK       = ctrl->tCK;
+	params->tAA       = ctrl->tAA;
+	params->tWR       = ctrl->tWR;
+	params->tRCD      = ctrl->tRCD;
+	params->tRRD      = ctrl->tRRD;
+	params->tRP       = ctrl->tRP;
+	params->tRAS      = ctrl->tRAS;
+	params->tRC       = ctrl->tRC;
+	params->tRFC      = ctrl->tRFC;
+	params->tWTR      = ctrl->tWTR;
+	params->tRTP      = ctrl->tRTP;
+	params->tFAW      = ctrl->tFAW;
+	params->tCWL      = ctrl->tCWL;
+	params->tCMD      = ctrl->tCMD;
+	params->tREFI     = ctrl->tREFI;
+	params->tXP       = ctrl->tXP;
+
+	params->chanmap = ctrl->chanmap;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		params->lpddr_cke_rank_map[channel] = ctrl->lpddr_cke_rank_map[channel];
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++)
+			params->dimms[channel][slot] = ctrl->dimms[channel][slot];
+	}
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		params->dpc[channel] = ctrl->dpc[channel];
+		params->rankmap[channel] = ctrl->rankmap[channel];
+		params->rank_mirrored[channel] = ctrl->rank_mirrored[channel];
+		params->channel_size_mb[channel] = ctrl->channel_size_mb[channel];
+	}
+	params->lpddr = ctrl->lpddr;
+	params->lanes = ctrl->lanes;
+	params->is_ecc = ctrl->is_ecc;
+	return RAMINIT_STATUS_SUCCESS;
+}
+
+#define RAMINIT_COMPARE(_s1, _s2) \
+	((sizeof(_s1) == sizeof(_s2)) && !memcmp(_s1, _s2, sizeof(_s1)))
+
+enum raminit_status restore_non_training(struct sysinfo *ctrl)
+{
+	struct register_save_frame *reg_frame = reg_frame_ptr();
+	struct save_params *params = &reg_frame->params;
+
+	if (!params->is_initialised) {
+		printk(BIOS_WARNING, "Cannot fast boot: saved data is invalid\n");
+		return RAMINIT_STATUS_INVALID_CACHE;
+	}
+
+	if (!RAMINIT_COMPARE(ctrl->dimms, params->dimms)) {
+		printk(BIOS_WARNING, "Cannot fast boot: DIMMs have changed\n");
+		return RAMINIT_STATUS_INVALID_CACHE;
+	}
+
+	if (ctrl->cpu != params->cpu) {
+		printk(BIOS_WARNING, "Cannot fast boot: CPU has changed\n");
+		return RAMINIT_STATUS_INVALID_CACHE;
+	}
+
+	ctrl->base_freq     = params->base_freq;
+	ctrl->multiplier    = params->multiplier;
+	ctrl->mem_clock_mhz = params->mem_clock_mhz;
+	ctrl->mem_clock_fs  = params->mem_clock_fs;
+	ctrl->qclkps        = params->qclkps;
+	ctrl->cas_supported = params->cas_supported;
+	ctrl->cpu           = params->cpu;
+	ctrl->stepping      = params->stepping;
+	ctrl->vdd_mv        = params->vdd_mv;
+	ctrl->flags         = params->flags;
+
+	ctrl->tCK       = params->tCK;
+	ctrl->tAA       = params->tAA;
+	ctrl->tWR       = params->tWR;
+	ctrl->tRCD      = params->tRCD;
+	ctrl->tRRD      = params->tRRD;
+	ctrl->tRP       = params->tRP;
+	ctrl->tRAS      = params->tRAS;
+	ctrl->tRC       = params->tRC;
+	ctrl->tRFC      = params->tRFC;
+	ctrl->tWTR      = params->tWTR;
+	ctrl->tRTP      = params->tRTP;
+	ctrl->tFAW      = params->tFAW;
+	ctrl->tCWL      = params->tCWL;
+	ctrl->tCMD      = params->tCMD;
+	ctrl->tREFI     = params->tREFI;
+	ctrl->tXP       = params->tXP;
+
+	ctrl->chanmap = params->chanmap;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		ctrl->lpddr_cke_rank_map[channel] = params->lpddr_cke_rank_map[channel];
+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++)
+			ctrl->dimms[channel][slot] = params->dimms[channel][slot];
+	}
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		ctrl->dpc[channel] = params->dpc[channel];
+		ctrl->rankmap[channel] = params->rankmap[channel];
+		ctrl->rank_mirrored[channel] = params->rank_mirrored[channel];
+		ctrl->channel_size_mb[channel] = params->channel_size_mb[channel];
+	}
+	ctrl->lpddr = params->lpddr;
+	ctrl->lanes = params->lanes;
+	ctrl->is_ecc = params->is_ecc;
+	return RAMINIT_STATUS_SUCCESS;
+}
+-- 
+2.39.2
+
@@ -0,0 +1,476 @@
+From 8528c7aa2a3cfcf0fe494a515a2e531ff0f1dab8 Mon Sep 17 00:00:00 2001
+From: Angel Pons <th3fanbus@gmail.com>
+Date: Wed, 17 Apr 2024 13:20:32 +0200
+Subject: [PATCH 17/17] haswell NRI: Do sense amplifier offset training
+
+Quoting Wikipedia:
+
+  A sense amplifier is a circuit that is used to amplify and detect
+  small signals in electronic systems. It is commonly used in memory
+  circuits, such as dynamic random access memory (DRAM), to read and
+  amplify the weak signals stored in memory cells.
+
+In this case, we're calibrating the sense amplifiers in the memory
+controller. This training procedure uses a magic "sense amp offset
+cancel" mode of the DDRIO to observe the sampled logic levels, and
+sweeps Vref to find the low-high transition for each bit lane. The
+procedure consists of two stages: the first stage centers per-byte
+Vref (to ensure per-bit Vref offsets are as small as possible) and
+the second stage centers per-bit Vref.
+
+Because this procedure uses the "sense amp offset cancel" mode, it
+does not rely on DRAM being trained. It is assumed that the memory
+controller simply makes sense amp output levels observable via the
+`DDR_DATA_TRAIN_FEEDBACK` register and that the memory bus is idle
+during this training step (so the lane voltage is Vdd / 2).
+
+Note: This procedure will need to be adapted for Broadwell because
+it has per-rank per-bit RxVref registers, whereas Haswell only has
+a single per-bit RxVref register for all ranks.
+
+Change-Id: Ia07db68763f90e9701c8a376e01279ada8dbbe07
+Signed-off-by: Angel Pons <th3fanbus@gmail.com>
+---
+ .../intel/haswell/native_raminit/Makefile.mk  |   1 +
+ .../haswell/native_raminit/raminit_main.c     |   1 +
+ .../haswell/native_raminit/raminit_native.h   |  12 +
+ .../native_raminit/train_sense_amp_offset.c   | 341 ++++++++++++++++++
+ .../intel/haswell/registers/mchbar.h          |   2 +
+ 5 files changed, 357 insertions(+)
+ create mode 100644 src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
+
+diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+index 8fdd17c542..4bd668a2d6 100644
+--- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
+@@ -21,3 +21,4 @@ romstage-y += timings_refresh.c
+ romstage-y += train_jedec_write_leveling.c
+ romstage-y += train_read_mpr.c
+ romstage-y += train_receive_enable.c
+romstage-y += train_sense_amp_offset.c
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+index 056dde1adc..ce637e2d03 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
+@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = {
+ 	{ configure_memory_map,                                   true, "MEMMAP",     },
+ 	{ do_jedec_init,                                          true, "JEDECINIT",  },
+ 	{ pre_training,                                           true, "PRETRAIN",   },
+	{ train_sense_amp_offset,                                 true, "SOT",        },
+ 	{ train_receive_enable,                                   true, "RCVET",      },
+ 	{ train_read_mpr,                                         true, "RDMPRT",     },
+ 	{ train_jedec_write_leveling,                             true, "JWRL",       },
+diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+index 2ac16eaad3..07eea98831 100644
+--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+@@ -23,6 +23,8 @@
+ #define NUM_LANES		9
+ #define NUM_LANES_NO_ECC	8
+ 
+#define NUM_BITS		8
+
+ #define COMP_INT		10
+ 
+ /* Always use 12 legs for emphasis (not trained) */
+@@ -219,6 +221,7 @@ enum raminit_status {
+ 	RAMINIT_STATUS_MPLL_INIT_FAILURE,
+ 	RAMINIT_STATUS_POLL_TIMEOUT,
+ 	RAMINIT_STATUS_REUT_ERROR,
+	RAMINIT_STATUS_SAMP_OFFSET_FAILURE,
+ 	RAMINIT_STATUS_RCVEN_FAILURE,
+ 	RAMINIT_STATUS_RMPR_FAILURE,
+ 	RAMINIT_STATUS_JWRL_FAILURE,
+@@ -244,6 +247,12 @@ struct raminit_dimm_info {
+ 	bool valid;
+ };
+ 
+struct vref_margin {
+	uint8_t low;
+	uint8_t center;
+	uint8_t high;
+};
+
+ struct sysinfo {
+ 	enum raminit_boot_mode bootmode;
+ 	enum generic_stepping stepping;
+@@ -331,6 +340,8 @@ struct sysinfo {
+ 	uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ 	int8_t  rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
+ 
+	struct vref_margin rxdqvrefpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
+
+ 	uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
+ 	uint8_t ctl_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
+ 	uint8_t cke_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
+@@ -453,6 +464,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
+ enum raminit_status configure_mc(struct sysinfo *ctrl);
+ enum raminit_status configure_memory_map(struct sysinfo *ctrl);
+ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
+enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl);
+ enum raminit_status train_receive_enable(struct sysinfo *ctrl);
+ enum raminit_status train_read_mpr(struct sysinfo *ctrl);
+ enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
+diff --git a/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
+new file mode 100644
+index 0000000000..d4f199fefb
+--- /dev/null
+++ b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
+@@ -0,0 +1,341 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <assert.h>
+#include <commonlib/bsd/clamp.h>
+#include <console/console.h>
+#include <delay.h>
+#include <lib.h>
+#include <types.h>
+
+#include "raminit_native.h"
+
+#define VREF_OFFSET_PLOT	RAM_DEBUG
+#define SAMP_OFFSET_PLOT	RAM_DEBUG
+
+struct vref_train_data {
+	int8_t best_sum;
+	int8_t best_vref;
+	int8_t sum_bits;
+	uint8_t high_mask;
+	uint8_t low_mask;
+};
+
+static enum raminit_status train_vref_offset(struct sysinfo *ctrl)
+{
+	const int8_t vref_start = -15;
+	const int8_t vref_stop  = 15;
+	const struct vref_train_data initial_vref_values = {
+		.best_sum  = -NUM_LANES,
+		.best_vref = 0,
+		.high_mask = 0,
+		.low_mask  = 0xff,
+	};
+	struct vref_train_data vref_data[NUM_CHANNELS][NUM_LANES];
+
+	printk(VREF_OFFSET_PLOT, "Plot of sum_bits across Vref settings\nChannel");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		printk(VREF_OFFSET_PLOT, "\t%u\t\t", channel);
+	}
+
+	printk(VREF_OFFSET_PLOT, "\nByte");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		printk(VREF_OFFSET_PLOT, "\t");
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			printk(VREF_OFFSET_PLOT, "%u ", byte);
+			vref_data[channel][byte] = initial_vref_values;
+			union ddr_data_control_2_reg data_control_2 = {
+				.raw = ctrl->dq_control_2[channel][byte],
+			};
+			data_control_2.force_bias_on = 1;
+			data_control_2.force_rx_on   = 1;
+			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
+		}
+	}
+
+	/* Sweep through Vref settings and find point SampOffset of +/- 7 passes */
+	printk(VREF_OFFSET_PLOT, "\n1/2 Vref");
+	for (int8_t vref = vref_start; vref <= vref_stop; vref++) {
+		printk(VREF_OFFSET_PLOT, "\n% 3d", vref);
+
+		/*
+		 * To perform this test, enable offset cancel mode and enable ODT.
+		 * Check results and update variables. Ideal result is all zeroes.
+		 * Clear offset cancel mode at end of test to write RX_OFFSET_VDQ.
+		 */
+		change_1d_margin_multicast(ctrl, RdV, vref, 0, false, REG_FILE_USE_RANK);
+
+		/* Program settings for Vref and SampOffset = 7 (8 + 7) */
+		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0xffffffff);
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			/* Propagate delay values (without a read command) */
+			union ddr_data_control_0_reg data_control_0 = {
+				.raw = ctrl->dq_control_0[channel],
+			};
+			data_control_0.read_rf_rd      = 1;
+			data_control_0.read_rf_wr      = 0;
+			data_control_0.read_rf_rank    = 0;
+			data_control_0.force_odt_on    = 1;
+			data_control_0.samp_train_mode = 1;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+			udelay(1);
+			data_control_0.samp_train_mode = 0;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				const uint8_t feedback = get_data_train_feedback(channel, byte);
+				struct vref_train_data *curr_data = &vref_data[channel][byte];
+				curr_data->low_mask &= feedback;
+				curr_data->sum_bits = -popcnt(feedback);
+			}
+		}
+
+		/* Program settings for Vref and SampOffset = -7 (8 - 7) */
+		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0x11111111);
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			/* Propagate delay values (without a read command) */
+			union ddr_data_control_0_reg data_control_0 = {
+				.raw = ctrl->dq_control_0[channel],
+			};
+			data_control_0.read_rf_rd      = 1;
+			data_control_0.read_rf_wr      = 0;
+			data_control_0.read_rf_rank    = 0;
+			data_control_0.force_odt_on    = 1;
+			data_control_0.samp_train_mode = 1;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+			udelay(1);
+			data_control_0.samp_train_mode = 0;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+			printk(VREF_OFFSET_PLOT, "\t");
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				const uint8_t feedback = get_data_train_feedback(channel, byte);
+				struct vref_train_data *curr_data = &vref_data[channel][byte];
+				curr_data->high_mask |= feedback;
+				curr_data->sum_bits += popcnt(feedback);
+				printk(VREF_OFFSET_PLOT, "%d ", curr_data->sum_bits);
+				if (curr_data->sum_bits > curr_data->best_sum) {
+					curr_data->best_sum  = curr_data->sum_bits;
+					curr_data->best_vref = vref;
+					ctrl->rxvref[channel][0][byte] = vref;
+				} else if (curr_data->sum_bits == curr_data->best_sum) {
+					curr_data->best_vref = vref;
+				}
+			}
+		}
+	}
+	printk(BIOS_DEBUG, "\n\nHi-Lo (XOR):");
+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		printk(BIOS_DEBUG, "\n  C%u:", channel);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			struct vref_train_data *const curr_data = &vref_data[channel][byte];
+			const uint8_t bit_xor = curr_data->high_mask ^ curr_data->low_mask;
+			printk(BIOS_DEBUG, "\t0x%02x", bit_xor);
+			if (bit_xor == 0xff)
+				continue;
+
+			/* Report an error if any bit did not change */
+			status = RAMINIT_STATUS_SAMP_OFFSET_FAILURE;
+		}
+	}
+	if (status)
+		printk(BIOS_ERR, "\nUnexpected bit error in Vref offset training\n");
+
+	printk(BIOS_DEBUG, "\n\nRdVref:");
+	change_1d_margin_multicast(ctrl, RdV, 0, 0, false, REG_FILE_USE_RANK);
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		printk(BIOS_DEBUG, "\n  C%u:", channel);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			struct vref_train_data *const curr_data = &vref_data[channel][byte];
+			const int8_t vref_width =
+				curr_data->best_vref - ctrl->rxvref[channel][0][byte];
+
+			/*
+			 * Step size for Rx Vref in DATA_OFFSET_TRAIN is about 3.9 mV
+			 * whereas Rx Vref step size in RX_TRAIN_RANK is about 7.8 mV
+			 */
+			int8_t vref = ctrl->rxvref[channel][0][byte] + vref_width / 2;
+			if (vref < 0)
+				vref--;
+			else
+				vref++;
+
+			for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
+				if (!rank_in_ch(ctrl, rank, channel))
+					continue;
+
+				ctrl->rxvref[channel][rank][byte] = vref / 2;
+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
+			}
+			printk(BIOS_DEBUG, "\t% 4d", ctrl->rxvref[channel][0][byte]);
+		}
+	}
+	printk(BIOS_DEBUG, "\n\n");
+	return status;
+}
+
+/**
+ * LPDDR has an additional bit for DQS per each byte.
+ *
+ * TODO: The DQS value must be written into Data Control 2.
+ */
+#define NUM_OFFSET_TRAIN_BITS	(NUM_BITS + 1)
+
+#define PLOT_CH_SPACE		"  "
+
+struct samp_train_data {
+	uint8_t first_zero;
+	uint8_t last_one;
+};
+
+static void train_samp_offset(struct sysinfo *ctrl)
+{
+	const uint8_t max_train_bits = ctrl->lpddr ? NUM_OFFSET_TRAIN_BITS : NUM_BITS;
+
+	struct samp_train_data samp_data[NUM_CHANNELS][NUM_LANES][NUM_OFFSET_TRAIN_BITS] = {0};
+
+	printk(BIOS_DEBUG, "Channel ");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		printk(BIOS_DEBUG, "%u ", channel); /* Same length as PLOT_CH_SPACE */
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			printk(BIOS_DEBUG, "        %s ", ctrl->lpddr ? " " : "");
+	}
+	printk(BIOS_DEBUG, "\nByte    ");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			printk(BIOS_DEBUG, "%u       %s ", byte, ctrl->lpddr ? " " : "");
+
+		printk(BIOS_DEBUG, PLOT_CH_SPACE);
+	}
+	printk(SAMP_OFFSET_PLOT, "\nBits    ");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			printk(SAMP_OFFSET_PLOT, "01234567%s ", ctrl->lpddr ? "S" : "");
+
+		printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
+	}
+	printk(SAMP_OFFSET_PLOT, "\n SAmp\n");
+	for (uint8_t samp_offset = 1; samp_offset <= 15; samp_offset++) {
+		printk(SAMP_OFFSET_PLOT, "% 5d\t", samp_offset);
+
+		uint32_t rx_offset_vdq = 0;
+		for (uint8_t bit = 0; bit < NUM_BITS; bit++) {
+			rx_offset_vdq += samp_offset << (4 * bit);
+		}
+		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, rx_offset_vdq);
+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+			if (!does_ch_exist(ctrl, channel))
+				continue;
+
+			/* Propagate delay values (without a read command) */
+			union ddr_data_control_0_reg data_control_0 = {
+				.raw = ctrl->dq_control_0[channel],
+			};
+			data_control_0.read_rf_rd      = 1;
+			data_control_0.read_rf_wr      = 0;
+			data_control_0.read_rf_rank    = 0;
+			data_control_0.force_odt_on    = 1;
+			data_control_0.samp_train_mode = 1;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+			udelay(1);
+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+				const uint32_t feedback =
+					get_data_train_feedback(channel, byte);
+
+				for (uint8_t bit = 0; bit < max_train_bits; bit++) {
+					struct samp_train_data *const curr_data =
+							&samp_data[channel][byte][bit];
+					const bool result = feedback & BIT(bit);
+					if (result) {
+						curr_data->last_one = samp_offset;
+					} else if (curr_data->first_zero == 0) {
+						curr_data->first_zero = samp_offset;
+					}
+					printk(SAMP_OFFSET_PLOT, result ? "." : "#");
+				}
+				printk(SAMP_OFFSET_PLOT, " ");
+			}
+			printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
+			data_control_0.samp_train_mode = 0;
+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
+		}
+		printk(SAMP_OFFSET_PLOT, "\n");
+	}
+	printk(BIOS_DEBUG, "\nBitSAmp ");
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
+			uint32_t rx_offset_vdq = 0;
+			for (uint8_t bit = 0; bit < max_train_bits; bit++) {
+				struct samp_train_data *const curr_data =
+						&samp_data[channel][byte][bit];
+
+				uint8_t vref = curr_data->first_zero + curr_data->last_one;
+				vref = clamp_u8(0, vref / 2, 15);
+				/*
+				 * Check for saturation conditions to make sure
+				 * we are as close as possible to Vdd/2 (750 mV).
+				 */
+				if (curr_data->first_zero == 0)
+					vref = 15;
+				if (curr_data->last_one == 0)
+					vref = 0;
+
+				ctrl->rxdqvrefpb[channel][0][byte][bit].center = vref;
+				rx_offset_vdq += vref & 0xf << (4 * bit);
+				printk(BIOS_DEBUG, "%x", vref);
+			}
+			mchbar_write32(RX_OFFSET_VDQ(channel, byte), rx_offset_vdq);
+			printk(BIOS_DEBUG, " ");
+			download_regfile(ctrl, channel, 1, 0, REG_FILE_USE_RANK, 0, 1, 0);
+		}
+		printk(BIOS_DEBUG, PLOT_CH_SPACE);
+	}
+	printk(BIOS_DEBUG, "\n");
+}
+
+enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl)
+{
+	printk(BIOS_DEBUG, "Stage 1: Vref offset training\n");
+	const enum raminit_status status = train_vref_offset(ctrl);
+
+	printk(BIOS_DEBUG, "Stage 2: Samp offset training\n");
+	train_samp_offset(ctrl);
+
+	/* Clean up after test */
+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
+		if (!does_ch_exist(ctrl, channel))
+			continue;
+
+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
+			mchbar_write32(DQ_CONTROL_2(channel, byte),
+				ctrl->dq_control_2[channel][byte]);
+	}
+	io_reset();
+	return status;
+}
+diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
+index 49a215aa71..1a168a3fc8 100644
+--- a/src/northbridge/intel/haswell/registers/mchbar.h
+++ b/src/northbridge/intel/haswell/registers/mchbar.h
+@@ -18,6 +18,8 @@
+ #define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
+ #define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
+ 
+#define RX_OFFSET_VDQ(ch, byte)			_DDRIO_C_R_B(0x004c, ch, 0, byte)
+
+ #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
+ 
+ #define DQ_CONTROL_1(ch, byte)			_DDRIO_C_R_B(0x0060, ch, 0, byte)
+-- 
+2.39.2
+
@@ -1,7 +1,7 @@
-From d3d97fccab40cfe50eac92796bb7f16bd245b189 Mon Sep 17 00:00:00 2001
+From f52188b46ce60383b67aeea2bda7ec52d631c822 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Mon, 12 Aug 2024 02:15:24 +0100
-Subject: [PATCH 19/41] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
+Subject: [PATCH 1/1] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ

 set it to 96MHz. fixes the following build error when
 building for x4x boards e.g. gigabyte ga-g41m-es2l:
@@ -33,7 +33,7 @@ Signed-off-by: Leah Rowe <info@minifree.org>
 1 file changed, 4 insertions(+)

 diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
-index 6fa4551957..646af3510b 100644
+index 9af063819b..93ba575b95 100644
 --- a/src/northbridge/intel/x4x/Kconfig
 +++ b/src/northbridge/intel/x4x/Kconfig
@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
@@ -48,5 +48,5 @@ index 6fa4551957..646af3510b 100644
 	default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
 
 -- 
-2.47.3
+2.39.2

--- a/Show More
+++ b/Show More