also de-rainbow the u-boot menu

boring is good

Signed-off-by: Leah Rowe <leah@libreboot.org>

.gitignore

@@ -36,3 +36,6 @@
 /hash/
 /dump/
 /qrun*.sh
+*.tar.*
+/m
+/f

config/coreboot/next/patches/0010-dell-3050micro-disable-nvme-hotplug.patch

@@ -0,0 +1,57 @@
+From adfeaeabcf98878814b463f14aba7871721d7606 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Wed, 11 Dec 2024 01:06:01 +0000
+Subject: [PATCH 1/1] dell/3050micro: disable nvme hotplug
+
+in my testing, when running my 3050micro for a few days,
+the nvme would sometimes randomly rename.
+
+e.g. nvme0n1 renamed to nvme0n2
+
+this might cause crashes in linux, if booting only from the
+nvme. in my case, i was booting from mdraid (sata+nvme) and
+every few days, the nvme would rename at least once, causing
+my RAID to become unsynced. since i'm using RAID1, this was
+OK and I could simply re-sync the array, but this is quite
+precarious indeed. if you're using raid0, that will potentially
+corrupt your RAID array indefinitely.
+
+this same issue manifested on the T480/T480 thinkpads, and
+S3 resume would break because of that, when booting from nvme,
+because the nvme would be "unplugged" and appear to linux as a
+new device (the one that you booted from).
+
+the fix there was to disable hotplugging on that pci-e slot
+for the nvme, so apply the same fix here for 3050 micro
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ 3rdparty/vboot                                 | 2 +-
+ src/mainboard/dell/optiplex_3050/devicetree.cb | 4 +++-
+ 2 files changed, 4 insertions(+), 2 deletions(-)
+
+diff --git a/3rdparty/vboot b/3rdparty/vboot
+index f1f70f46dc..902fe8af96 160000
+--- a/3rdparty/vboot
++++ b/3rdparty/vboot
+@@ -1 +1 @@
+-Subproject commit f1f70f46dc5482bb7c654e53ed58d4001e386df2
++Subproject commit 902fe8af96ad662fac127cb8f51596491cf8272f
+diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb
+index 039709aa4a..0678ed1765 100644
+--- a/src/mainboard/dell/optiplex_3050/devicetree.cb
++++ b/src/mainboard/dell/optiplex_3050/devicetree.cb
+@@ -45,7 +45,9 @@ chip soc/intel/skylake
+ 			register "PcieRpAdvancedErrorReporting[20]"     = "1"
+ 			register "PcieRpLtrEnable[20]"                  = "1"
+ 			register "PcieRpClkSrcNumber[20]"               = "3"
+-			register "PcieRpHotPlug[20]"                    = "1"
++# disable hotplug on nvme to prevent renaming e.g. nvme0n1 rename to nvme0n2,
++# which could cause crashes in linux if booting from nvme
++			register "PcieRpHotPlug[20]"                    = "0"
+ 		end
+ 
+ 		# Realtek LAN
+-- 
+2.39.5
+

config/coreboot/next/patches/0010-drivers-intel-dtbt-Add-discrete-Thunderbolt-driver.patch

@@ -1,265 +0,0 @@
-From 0db8646d574c07c40793bad5e5ab768da6161628 Mon Sep 17 00:00:00 2001
-From: Jeremy Soller <jeremy@system76.com>
-Date: Thu, 5 Dec 2024 20:35:23 +0000
-Subject: [PATCH 1/2] drivers/intel/dtbt: Add discrete Thunderbolt driver
-
-Add a new driver for discrete Thunderbolt controllers. This allows using
-e.g. Maple Ridge devices on Raptor Point PCH.
-
-Ref: Titan Ridge BIOS Implementation Guide v1.4
-Ref: Maple Ridge BIOS Implementation Guide v1.6 (#632472)
-Change-Id: Ib78ce43740956fa2c93b9ebddb0eeb319dcc0364
-Signed-off-by: Jeremy Soller <jeremy@system76.com>
-Signed-off-by: Tim Crawford <tcrawford@system76.com>
----
- src/drivers/intel/dtbt/Kconfig     |   4 +
- src/drivers/intel/dtbt/Makefile.mk |   3 +
- src/drivers/intel/dtbt/chip.h      |   8 ++
- src/drivers/intel/dtbt/dtbt.c      | 199 +++++++++++++++++++++++++++++
- 4 files changed, 214 insertions(+)
- create mode 100644 src/drivers/intel/dtbt/Kconfig
- create mode 100644 src/drivers/intel/dtbt/Makefile.mk
- create mode 100644 src/drivers/intel/dtbt/chip.h
- create mode 100644 src/drivers/intel/dtbt/dtbt.c
-
-diff --git a/src/drivers/intel/dtbt/Kconfig b/src/drivers/intel/dtbt/Kconfig
-new file mode 100644
-index 0000000000..5c03a97db9
---- /dev/null
-+++ b/src/drivers/intel/dtbt/Kconfig
-@@ -0,0 +1,4 @@
-+config DRIVERS_INTEL_DTBT
-+	def_bool n
-+	help
-+	  Support for discrete Thunderbolt controllers
-diff --git a/src/drivers/intel/dtbt/Makefile.mk b/src/drivers/intel/dtbt/Makefile.mk
-new file mode 100644
-index 0000000000..1b5252dda0
---- /dev/null
-+++ b/src/drivers/intel/dtbt/Makefile.mk
-@@ -0,0 +1,3 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+
-+ramstage-$(CONFIG_DRIVERS_INTEL_DTBT) += dtbt.c
-diff --git a/src/drivers/intel/dtbt/chip.h b/src/drivers/intel/dtbt/chip.h
-new file mode 100644
-index 0000000000..2b1dfa70a5
---- /dev/null
-+++ b/src/drivers/intel/dtbt/chip.h
-@@ -0,0 +1,8 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#ifndef _DRIVERS_INTEL_DTBT_CHIP_H_
-+#define _DRIVERS_INTEL_DTBT_CHIP_H_
-+
-+struct drivers_intel_dtbt_config {};
-+
-+#endif /* _DRIVERS_INTEL_DTBT_CHIP_H_ */
-diff --git a/src/drivers/intel/dtbt/dtbt.c b/src/drivers/intel/dtbt/dtbt.c
-new file mode 100644
-index 0000000000..a54f0e213d
---- /dev/null
-+++ b/src/drivers/intel/dtbt/dtbt.c
-@@ -0,0 +1,199 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include "chip.h"
-+#include <acpi/acpigen.h>
-+#include <console/console.h>
-+#include <delay.h>
-+#include <device/device.h>
-+#include <device/pci.h>
-+#include <device/pciexp.h>
-+#include <device/pci_ids.h>
-+#include <timer.h>
-+
-+#define PCIE2TBT 0x54C
-+#define PCIE2TBT_VALID BIT(0)
-+#define PCIE2TBT_GO2SX			2
-+#define PCIE2TBT_GO2SX_NO_WAKE		3
-+#define PCIE2TBT_SX_EXIT_TBT_CONNECTED	4
-+#define PCIE2TBT_OS_UP			6
-+#define PCIE2TBT_SET_SECURITY_LEVEL	8
-+#define PCIE2TBT_GET_SECURITY_LEVEL	9
-+#define PCIE2TBT_BOOT_ON		24
-+#define PCIE2TBT_USB_ON			25
-+#define PCIE2TBT_GET_ENUMERATION_METHOD	26
-+#define PCIE2TBT_SET_ENUMERATION_METHOD	27
-+#define PCIE2TBT_POWER_CYCLE		28
-+#define PCIE2TBT_SX_START		29
-+#define PCIE2TBT_ACL_BOOT		30
-+#define PCIE2TBT_CONNECT_TOPOLOGY	31
-+
-+#define TBT2PCIE 0x548
-+#define TBT2PCIE_DONE BIT(0)
-+
-+// Default timeout for mailbox commands unless otherwise specified.
-+#define TIMEOUT_MS 1000
-+// Default timeout for controller to ack GO2SX/GO2SX_NO_WAKE mailbox command.
-+#define GO2SX_TIMEOUT_MS 600
-+
-+static void dtbt_cmd(struct device *dev, u32 command, u32 data, u32 timeout)
-+{
-+	u32 reg = (data << 8) | (command << 1) | PCIE2TBT_VALID;
-+	u32 status;
-+
-+	printk(BIOS_DEBUG, "dTBT send command %08x\n", command);
-+	pci_write_config32(dev, PCIE2TBT, reg);
-+
-+	if (!wait_ms(timeout, (status = pci_read_config32(dev, TBT2PCIE)) & TBT2PCIE_DONE)) {
-+		printk(BIOS_ERR, "dTBT command %08x send timeout %08x\n", command, status);
-+	}
-+
-+	pci_write_config32(dev, PCIE2TBT, 0);
-+	if (!wait_ms(timeout, !(pci_read_config32(dev, TBT2PCIE) & TBT2PCIE_DONE))) {
-+		printk(BIOS_ERR, "dTBT command %08x clear timeout\n", command);
-+	}
-+}
-+
-+static void dtbt_write_dsd(void)
-+{
-+	struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
-+
-+	acpi_device_add_hotplug_support_in_d3(dsd);
-+	acpi_device_add_external_facing_port(dsd);
-+	acpi_dp_write(dsd);
-+}
-+
-+static void dtbt_write_opregion(const struct bus *bus)
-+{
-+	uintptr_t mmconf_base = (uintptr_t)CONFIG_ECAM_MMCONF_BASE_ADDRESS
-+			+ (((uintptr_t)(bus->secondary)) << 20);
-+	const struct opregion opregion = OPREGION("PXCS", SYSTEMMEMORY, mmconf_base, 0x1000);
-+	const struct fieldlist fieldlist[] = {
-+		FIELDLIST_OFFSET(TBT2PCIE),
-+		FIELDLIST_NAMESTR("TB2P", 32),
-+		FIELDLIST_OFFSET(PCIE2TBT),
-+		FIELDLIST_NAMESTR("P2TB", 32),
-+	};
-+
-+	acpigen_write_opregion(&opregion);
-+	acpigen_write_field("PXCS", fieldlist, ARRAY_SIZE(fieldlist),
-+			    FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE);
-+}
-+
-+static void dtbt_fill_ssdt(const struct device *dev)
-+{
-+	struct bus *bus;
-+	struct device *parent;
-+	const char *parent_scope;
-+	const char *dev_name = acpi_device_name(dev);
-+
-+	bus = dev->upstream;
-+	if (!bus) {
-+		printk(BIOS_ERR, "dTBT bus invalid\n");
-+		return;
-+	}
-+
-+	parent = bus->dev;
-+	if (!parent || parent->path.type != DEVICE_PATH_PCI) {
-+		printk(BIOS_ERR, "dTBT parent invalid\n");
-+		return;
-+	}
-+
-+	parent_scope = acpi_device_path(parent);
-+	if (!parent_scope) {
-+		printk(BIOS_ERR, "dTBT parent scope not valid\n");
-+		return;
-+	}
-+
-+	/* Scope */
-+	acpigen_write_scope(parent_scope);
-+	dtbt_write_dsd();
-+
-+	/* Device */
-+	acpigen_write_device(dev_name);
-+	acpigen_write_name_integer("_ADR", 0);
-+	dtbt_write_opregion(bus);
-+
-+	/* Method */
-+	acpigen_write_method_serialized("PTS", 0);
-+
-+	acpigen_write_debug_string("dTBT prepare to sleep");
-+	acpigen_write_store_int_to_namestr(PCIE2TBT_GO2SX_NO_WAKE << 1, "P2TB");
-+	acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", PCIE2TBT_GO2SX_NO_WAKE << 1);
-+
-+	acpigen_write_debug_namestr("TB2P");
-+	acpigen_write_store_int_to_namestr(0, "P2TB");
-+	acpigen_write_delay_until_namestr_int(GO2SX_TIMEOUT_MS, "TB2P", 0);
-+	acpigen_write_debug_namestr("TB2P");
-+
-+	acpigen_write_method_end();
-+	acpigen_write_device_end();
-+	acpigen_write_scope_end();
-+
-+	printk(BIOS_DEBUG, "dTBT fill SSDT\n");
-+	printk(BIOS_DEBUG, "  Dev %s\n", dev_path(dev));
-+	//printk(BIOS_DEBUG, "  Bus %s\n", bus_path(bus));
-+	printk(BIOS_DEBUG, "  Parent %s\n", dev_path(parent));
-+	printk(BIOS_DEBUG, "  Scope %s\n", parent_scope);
-+	printk(BIOS_DEBUG, "    Device %s\n", dev_name);
-+
-+	// \.TBTS Method
-+	acpigen_write_scope("\\");
-+	acpigen_write_method("TBTS", 0);
-+	acpigen_emit_namestring(acpi_device_path_join(dev, "PTS"));
-+	acpigen_write_method_end();
-+	acpigen_write_scope_end();
-+}
-+
-+static const char *dtbt_acpi_name(const struct device *dev)
-+{
-+	return "DTBT";
-+}
-+
-+static struct pci_operations dtbt_device_ops_pci = {
-+	.set_subsystem = 0,
-+};
-+
-+static struct device_operations dtbt_device_ops = {
-+	.read_resources   = pci_bus_read_resources,
-+	.set_resources    = pci_dev_set_resources,
-+	.enable_resources = pci_bus_enable_resources,
-+	.acpi_fill_ssdt   = dtbt_fill_ssdt,
-+	.acpi_name        = dtbt_acpi_name,
-+	.scan_bus         = pciexp_scan_bridge,
-+	.reset_bus        = pci_bus_reset,
-+	.ops_pci          = &dtbt_device_ops_pci,
-+};
-+
-+static void dtbt_enable(struct device *dev)
-+{
-+	if (!is_dev_enabled(dev) || dev->path.type != DEVICE_PATH_PCI)
-+		return;
-+
-+	if (pci_read_config16(dev, PCI_VENDOR_ID) != PCI_VID_INTEL)
-+		return;
-+
-+	// TODO: check device ID
-+
-+	dev->ops = &dtbt_device_ops;
-+
-+	printk(BIOS_INFO, "dTBT controller found at %s\n", dev_path(dev));
-+
-+	// XXX: Recommendation is to set SL1 ("User Authorization")
-+	printk(BIOS_DEBUG, "dTBT set security level SL0\n");
-+	dtbt_cmd(dev, PCIE2TBT_SET_SECURITY_LEVEL, 0, TIMEOUT_MS);
-+	// XXX: Must verify change or rollback all controllers
-+
-+	if (acpi_is_wakeup_s3()) {
-+		printk(BIOS_DEBUG, "dTBT SX exit\n");
-+		dtbt_cmd(dev, PCIE2TBT_SX_EXIT_TBT_CONNECTED, 0, TIMEOUT_MS);
-+		// TODO: "wait for fast link bring-up" loop (timeout: 5s)
-+	} else {
-+		printk(BIOS_DEBUG, "dTBT boot on\n");
-+		dtbt_cmd(dev, PCIE2TBT_BOOT_ON, 0, TIMEOUT_MS);
-+	}
-+}
-+
-+struct chip_operations drivers_intel_dtbt_ops = {
-+	.name = "Intel Discrete Thunderbolt",
-+	.enable_dev = dtbt_enable,
-+};
--- 
-2.39.5
-

config/coreboot/next/patches/0011-thunderbolt-fix-ish.patch

@@ -1,136 +0,0 @@
-From dbc0c75d666045eb0716e2ad0656a29b562c8f66 Mon Sep 17 00:00:00 2001
-From: Mate Kukri <km@mkukri.xyz>
-Date: Thu, 5 Dec 2024 20:42:40 +0000
-Subject: [PATCH 2/2] thunderbolt fix-ish
-
-it shows up, but resume is no dice.
-
-Change-Id: I2d91a1d290b35e7ea3a1193b4be7b4ba936e4a15
----
- src/mainboard/lenovo/sklkbl_thinkpad/Kconfig        |  1 +
- src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl       | 13 +++++++++++++
- .../lenovo/sklkbl_thinkpad/variants/t480/gpio.c     |  8 ++++----
- .../sklkbl_thinkpad/variants/t480/overridetree.cb   |  4 ++++
- .../lenovo/sklkbl_thinkpad/variants/t480s/gpio.c    |  8 ++++----
- .../sklkbl_thinkpad/variants/t480s/overridetree.cb  |  4 ++++
- 6 files changed, 30 insertions(+), 8 deletions(-)
-
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
-index 21076315ab..0766c03716 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
-@@ -19,6 +19,7 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
- 	select SOC_INTEL_COMMON_BLOCK_HDA_VERB
- 	select SPD_READ_BY_WORD
- 	select SYSTEM_TYPE_LAPTOP
-+	select DRIVERS_INTEL_DTBT
- 
- config BOARD_LENOVO_E460
- 	bool
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
-index 237500775f..849540d32d 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
-@@ -35,4 +35,17 @@ DefinitionBlock(
- 	}
- 
- 	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+
-+	Scope (\_SB)
-+	{
-+		External (\TBTS, MethodObj)
-+
-+		Method (MPTS, 1, Serialized)
-+		{
-+			If (CondRefOf (\TBTS))
-+			{
-+				\TBTS()
-+			}
-+		}
-+	}
- }
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
-index f7c29e1f39..edfa09fbb7 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
-@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = {
- 	PAD_NC(GPP_C18, NONE),
- 	PAD_NC(GPP_C19, NONE),
- 	PAD_CFG_GPO(GPP_C20, 0, DEEP),					/* EPRIVACY_ON */
--	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
-+	PAD_CFG_GPO(GPP_C21, 1, DEEP),					/* TBT_FORCE_PWR */
- 	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
- 	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
- 
-@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = {
- 	PAD_NC(GPP_G1, NONE),
- 	PAD_NC(GPP_G2, NONE),
- 	PAD_NC(GPP_G3, NONE),
--	PAD_CFG_GPO(GPP_G4, 0, DEEP),					/* TBT_RTD3_PWR_EN */
--	PAD_CFG_GPO(GPP_G5, 0, DEEP),					/* TBT_FORCE_USB_PWR */
--	PAD_CFG_GPO(GPP_G6, 0, DEEP),					/* -TBT_PERST */
-+	PAD_CFG_GPO(GPP_G4, 1, DEEP),					/* TBT_RTD3_PWR_EN */
-+	PAD_CFG_GPO(GPP_G5, 1, DEEP),					/* TBT_FORCE_USB_PWR (TBT_RTD3_USB_PWR_EN) */
-+	PAD_CFG_GPO(GPP_G6, 1, DEEP),					/* -TBT_PERST */
- 	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
- };
- 
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
-index 2f0b20d91a..6d8725ad5a 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
-@@ -106,6 +106,10 @@ chip soc/intel/skylake
- 			register "PcieRpAdvancedErrorReporting[8]"	= "1"
- 			register "PcieRpLtrEnable[8]"			= "1"
- 			register "PcieRpHotPlug[8]"			= "1"
-+
-+			chip drivers/intel/dtbt
-+				device pci 0.0 on end
-+			end
- 		end
- 
- 		# M.2 2280 caddy - x2
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
-index a98dd2bc4e..732917ebfa 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
-@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = {
- 	PAD_NC(GPP_C18, NONE),
- 	PAD_NC(GPP_C19, NONE),
- 	PAD_CFG_GPO(GPP_C20, 0, DEEP),					/* EPRIVACY_ON */
--	PAD_CFG_GPO(GPP_C21, 0, DEEP),					/* TBT_FORCE_PWR */
-+	PAD_CFG_GPO(GPP_C21, 1, DEEP),					/* TBT_FORCE_PWR */
- 	PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_SCI */
- 	PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT),	/* -EC_WAKE */
- 
-@@ -187,9 +187,9 @@ static const struct pad_config gpio_table[] = {
- 	PAD_NC(GPP_G1, NONE),
- 	PAD_NC(GPP_G2, NONE),
- 	PAD_NC(GPP_G3, NONE),
--	PAD_CFG_GPO(GPP_G4, 0, DEEP),					/* TBT_RTD3_PWR_EN */
--	PAD_CFG_GPO(GPP_G5, 0, DEEP),					/* TBT_FORCE_USB_PWR */
--	PAD_CFG_GPO(GPP_G6, 0, DEEP),					/* -TBT_PERST */
-+	PAD_CFG_GPO(GPP_G4, 1, DEEP),					/* TBT_RTD3_PWR_EN */
-+	PAD_CFG_GPO(GPP_G5, 1, DEEP),					/* TBT_FORCE_USB_PWR (TBT_RTD3_USB_PWR_EN) */
-+	PAD_CFG_GPO(GPP_G6, 1, DEEP),					/* -TBT_PERST */
- 	PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT),		/* -TBT_PCIE_WAKE */
- };
- 
-diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
-index cea5e485d2..9b952215c5 100644
---- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
-+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
-@@ -106,6 +106,10 @@ chip soc/intel/skylake
- 			register "PcieRpAdvancedErrorReporting[4]"	= "1"
- 			register "PcieRpLtrEnable[4]"			= "1"
- 			register "PcieRpHotPlug[4]"			= "1"
-+
-+			chip drivers/intel/dtbt
-+				device pci 0.0 on end
-+			end
- 		end
- 
- 		# M.2 2280 SSD - x2
--- 
-2.39.5
-

config/coreboot/t480_fsp_16mb/config/libgfxinit_corebootfb

@@ -625,7 +625,6 @@ CONFIG_DRIVERS_UART=y
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
 CONFIG_DRIVERS_I2C_DESIGNWARE=y
 # CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_DRIVERS_INTEL_DTBT=y
 CONFIG_FSP_USE_REPO=y
 # CONFIG_DISPLAY_HOBS is not set
 # CONFIG_DISPLAY_UPD_DATA is not set

config/coreboot/t480_fsp_16mb/config/libgfxinit_txtmode

@@ -617,7 +617,6 @@ CONFIG_DRIVERS_UART=y
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
 CONFIG_DRIVERS_I2C_DESIGNWARE=y
 # CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_DRIVERS_INTEL_DTBT=y
 CONFIG_FSP_USE_REPO=y
 # CONFIG_DISPLAY_HOBS is not set
 # CONFIG_DISPLAY_UPD_DATA is not set

config/coreboot/t480s_fsp_16mb/config/libgfxinit_corebootfb

@@ -625,7 +625,6 @@ CONFIG_DRIVERS_UART=y
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
 CONFIG_DRIVERS_I2C_DESIGNWARE=y
 # CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_DRIVERS_INTEL_DTBT=y
 CONFIG_FSP_USE_REPO=y
 # CONFIG_DISPLAY_HOBS is not set
 # CONFIG_DISPLAY_UPD_DATA is not set

config/coreboot/t480s_fsp_16mb/config/libgfxinit_txtmode

@@ -617,7 +617,6 @@ CONFIG_DRIVERS_UART=y
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
 CONFIG_DRIVERS_I2C_DESIGNWARE=y
 # CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_DRIVERS_INTEL_DTBT=y
 CONFIG_FSP_USE_REPO=y
 # CONFIG_DISPLAY_HOBS is not set
 # CONFIG_DISPLAY_UPD_DATA is not set

config/u-boot/default/patches/0008-change-the-logo-back-to-the-plain-libreboot-one.patch

@@ -0,0 +1,157 @@
+From d721edb391618fca096ec7f63a2fbc9df0af9231 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Tue, 17 Dec 2024 12:59:54 +0000
+Subject: [PATCH 1/1] change the logo back to the plain libreboot one
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ drivers/video/u_boot_logo.bmp | Bin 27350 -> 27350 bytes
+ 1 file changed, 0 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/u_boot_logo.bmp b/drivers/video/u_boot_logo.bmp
+index bc9ae001badb25bc900058c167a47247ef91dc7c..c9262cd206cc3cf5297daa94b696fcf102fc22b5 100644
+GIT binary patch
+literal 27350
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+
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+
+-- 
+2.39.5
+

config/u-boot/x86/patches/0007-change-the-logo-back-to-the-plain-libreboot-one.patch

@@ -0,0 +1,157 @@
+From d721edb391618fca096ec7f63a2fbc9df0af9231 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Tue, 17 Dec 2024 12:59:54 +0000
+Subject: [PATCH 1/1] change the logo back to the plain libreboot one
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ drivers/video/u_boot_logo.bmp | Bin 27350 -> 27350 bytes
+ 1 file changed, 0 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/u_boot_logo.bmp b/drivers/video/u_boot_logo.bmp
+index bc9ae001badb25bc900058c167a47247ef91dc7c..c9262cd206cc3cf5297daa94b696fcf102fc22b5 100644
+GIT binary patch
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+
+-- 
+2.39.5
+

config/u-boot/x86_64/patches/0007-change-the-logo-back-to-the-plain-libreboot-one.patch

@@ -0,0 +1,157 @@
+From d721edb391618fca096ec7f63a2fbc9df0af9231 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Tue, 17 Dec 2024 12:59:54 +0000
+Subject: [PATCH 1/1] change the logo back to the plain libreboot one
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ drivers/video/u_boot_logo.bmp | Bin 27350 -> 27350 bytes
+ 1 file changed, 0 insertions(+), 0 deletions(-)
+
+diff --git a/drivers/video/u_boot_logo.bmp b/drivers/video/u_boot_logo.bmp
+index bc9ae001badb25bc900058c167a47247ef91dc7c..c9262cd206cc3cf5297daa94b696fcf102fc22b5 100644
+GIT binary patch
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+zj^STgg%;&$mk;t4iYc!b#2LXQ5f~VNxs2DQg@t_it2n`E5|HJCdVZ@oLyti3|Kmdd
+zRj7<@A({l_u}!Q>!p<n?y)e}n+8{)^g@_G{vf83O3uElCuZqLeTGY=`8sJNV+F5$G
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+zdGGF>+`ovvR8dt{iT?NK&#eU@`hVc<<x2mr+}|qtoMB0-EzHlrXTxAckz4!q%lq{!
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+zYT8b_DIU)?*iuLN*q`p<{XD%6!#nrjo!jw_3cMqeKB65|Cf-kM0~~|q)V6L*(mb(A
+z7m$v>Z}#VxFaLKY7E{j>{j=fa%YS_L^5s9TW3Bv8L{Dm*@Bio;(ZauBdxLXZ^i})<
+z?=aEBUgx&*Z-_d+!UXY;JIiXz#C7<$o%$_Xi2kRAC~z(Q%FKV^NB*UXZrI2B>BjFd
+h=Y>|w|C6Zk68;X)R-AjChtJK+<qqA3JjSNqzW{|XuQ>n!
+
+-- 
+2.39.5
+

include/rom.sh

@@ -44,8 +44,7 @@ mkpayload_grub()
 	    --fonts= --themes= --locales=  --modules="$grub_modules" \
 	    --install-modules="$grub_install_modules" \
 	    "/boot/grub/grub_default.cfg=${srcdir}/.config" \
-	    "/boot/grub/grub.cfg=$grubdata/memdisk.cfg" \
-	    "/background.png=$grubdata/background/background1280x800.png" || \
+	    "/boot/grub/grub.cfg=$grubdata/memdisk.cfg" || \
 	    $err "$tree: cannot build grub.elf"; return 0
 }
 
@@ -165,6 +164,9 @@ add_grub()
 	printf "set grub_scan_disk=\"%s\"\n" "$grub_scan_disk" \
 	    > "$TMPDIR/tmpcfg" || $err "$target: !insert scandisk"
 	cbfs "$tmprom" "$TMPDIR/tmpcfg" scan.cfg raw
+	[ "$initmode" != "normal" ] && [ "$displaymode" != "txtmode" ] && \
+	    cbfs "$tmprom" "$grubdata/background/background1280x800.png" \
+	    "background.png" raw; :
 }
 
 mkseagrub()