mirror of
https://codeberg.org/libreboot/lbmk.git
synced 2026-07-17 18:34:57 +02:00
Leah Rowe
99a88ebfa2
Use patchset 15 instead of 14:
config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch
Rebase the verb patch; patchset 15 modified the Makefile:
config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch
We were using patchset 14 for the 3050 micro:
https://review.coreboot.org/c/coreboot/+/82053/14
Now we use patchset 15:
https://review.coreboot.org/c/coreboot/+/82053/15
Without this patch, the fans are always on a low setting, on
the Dell OptiPlex 3050 Micro, even under stress conditions. With
this patch, the fans change speed according to CPU temperature.
I had to rebase my verb patch, because Mate modified the Makefile
to add his sch5555 handler, on the same line where I add hda_verb.
Mate tells me he will merge my verb and vbt patches into a further
patchset later on. For now, I've simply rebased these patches on
top of Mate's newer work; I've told him he can use them in his port.
I'm probably going to now issue a new revision ROM image for
Libreboot 20241008, so that users can get this fix sooner.
Signed-off-by: Leah Rowe <leah@libreboot.org>
436 lines
15 KiB
Diff
436 lines
15 KiB
Diff
From 85a0905b600c1f532c462047941da6e7c2bb47c2 Mon Sep 17 00:00:00 2001
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From: Nicholas Chin <nic.c3.14@gmail.com>
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Date: Wed, 7 Feb 2024 15:23:46 -0700
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Subject: [PATCH 24/65] mb/dell: Add Latitude E6320 (Sandy Bridge)
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Mainboard is PAL70/LA-6611P. I do not physically have this system;
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someone with physical access to one sent me the output of autoport which
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I then modified to produce this port. I was also sent the VBT binary,
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which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
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version A22 of the vendor firmware. This port has not been tested.
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The EC is the SMSC MEC5055, which seems to be compatible with the
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existing MEC5035 code. As with the other Dell systems with this EC, this
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board is assumed to be internally flashable using an EC command that
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tells it to pull the FDO pin low on the next boot, which also tells the
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vendor firmware to disable all write protections to the flash [1].
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[1] https://gitlab.com/nic3-14159/dell-flash-unlock
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Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46
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Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
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---
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src/mainboard/dell/snb_ivb_latitude/Kconfig | 11 +-
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.../dell/snb_ivb_latitude/Kconfig.name | 3 +
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.../snb_ivb_latitude/variants/e6320/data.vbt | Bin 0 -> 6144 bytes
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.../variants/e6320/early_init.c | 17 ++
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.../snb_ivb_latitude/variants/e6320/gpio.c | 190 ++++++++++++++++++
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.../variants/e6320/hda_verb.c | 32 +++
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.../variants/e6320/overridetree.cb | 35 ++++
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7 files changed, 287 insertions(+), 1 deletion(-)
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
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diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
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index e6a21ffb99..84ffe1d33a 100644
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--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
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+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
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@@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520
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select BOARD_ROMSIZE_KB_6144
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select SOUTHBRIDGE_INTEL_BD82X6X
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+config BOARD_DELL_LATITUDE_E6320
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+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
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+ select BOARD_ROMSIZE_KB_10240
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+ select MAINBOARD_USES_IFD_GBE_REGION
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+ select SOUTHBRIDGE_INTEL_BD82X6X
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+
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config BOARD_DELL_LATITUDE_E6420
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select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
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select BOARD_ROMSIZE_KB_10240
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@@ -67,6 +73,7 @@ config MAINBOARD_DIR
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config MAINBOARD_PART_NUMBER
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default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
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default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
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+ default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320
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default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
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default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
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default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
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@@ -82,6 +89,7 @@ config USBDEBUG_HCD_INDEX
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config VARIANT_DIR
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default "e5420" if BOARD_DELL_LATITUDE_E5420
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default "e5520" if BOARD_DELL_LATITUDE_E5520
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+ default "e6320" if BOARD_DELL_LATITUDE_E6320
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default "e6420" if BOARD_DELL_LATITUDE_E6420
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default "e6520" if BOARD_DELL_LATITUDE_E6520
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default "e5530" if BOARD_DELL_LATITUDE_E5530
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@@ -93,7 +101,8 @@ config VGA_BIOS_ID
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|| BOARD_DELL_LATITUDE_E5420
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default "8086,0166" if BOARD_DELL_LATITUDE_E5530
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default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
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- || BOARD_DELL_LATITUDE_E5520
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+ || BOARD_DELL_LATITUDE_E5520 \
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+ || BOARD_DELL_LATITUDE_E6320
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default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
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|| BOARD_DELL_LATITUDE_E6530
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diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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index a3fa2b1837..ef6a1329a9 100644
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--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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@@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420
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config BOARD_DELL_LATITUDE_E5520
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bool "Latitude E5520"
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+config BOARD_DELL_LATITUDE_E6320
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+ bool "Latitude E6320"
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+
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config BOARD_DELL_LATITUDE_E6420
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bool "Latitude E6420"
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt
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new file mode 100644
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index 0000000000000000000000000000000000000000..471a9e29da639dd496f3ecebd5d0754a9045c00b
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GIT binary patch
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literal 6144
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zcmeHKeP|p-6#wn*-rZ(yH@R-odPzTgZEU>S#_pv}j2iKhT+^%8_DtJw21|4GP8*0x
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zyw;EYW49Xozz<Rt@ek1mic(N32r8oZ0U9lcR8a)~s33wLV8yCftLK~DJJWb)8w-j;
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z=J?H<nfK<+n>TOX?48xuwV5_`Zb)3w)w?dSc1`nTL|NF_SMw&<<)v%g#!cH2otrzi
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zb*<mneJMSLdC1iK_7#v-6w7R}+t1&W8P4wBo*&F!lcNn?)F-EqWZV#oQEb%`x-4^5
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zW@sogOik1`n9Wc#r82|0A!=-0LD!FFGrMwG+CDg($q(js(#Y`8?s79ubEJD@ba#I6
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znjO0++P#czvh8NBR?)iQUA%txNPhHO>Kq!PUMaJadUHE-`5SWCb4_6i;5Aj(6hQGK
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zcq^2uUt5sS5YSMiL+CJcs0#cVOdTN|K@D>?tkF=dqenwjM^Z-^K2z~&z+xRs!o^Jx
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zkUGd?>QtXw8V(I09OiMb0DZy>`=tO^#BCssw{}bkOnj=#Ic!~!6!J*{`jbEv5O4)-
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zg-UBlIa$c9Pg4C;0_-wq3t+dbZfn1wBi@zhNnWx()w{Vb-G8OC_m*478gTrX3U*a1
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zHr@y<Lcbct?Wzy^)OH+FC$S`8V@n`{QN~@2dxJU-1ucBe_>rOO78dFPXES1q3mHj9
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zFXKwa)r^}Mw=nKzJjj?}>}NdBc$G29IK=pr@de`u;}}D$5~yYbw&Hlf=OF0X?I=Y$
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z$D`mgy>}U$hl}G6m&PmXveHnY5DenC!g~=E3i?HIrEpyk>_(-IsVtEqUEoqxrDFdq
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zrYwhOv0o^NgW$OKN}=$7Z-w5*Vuv?T3~uuFGwP92?Qr8n0iQp=u*7rep9Q8dW#?ZI
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zFly1ww^^l*+YC6t16l_{g}tVVpVZ0fDk%5+`|+*688vr-<Lw_SRc^+avHI{BCpdYb
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z70yLEI0-45%t;z||GKzov+|VFW6hab&NAG9FD+h6sBu$cX`r0eJ%T`kvK4+(wT`0=
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z$fxKG+om?Ge1-EhbNc*Xjy1opKZSaiv-EL~GvOa&&bx~z##3W;F2{b=<HQ4!<1CFk
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z17i)$X+`=C=0udOPOx3$IjzopqwQzLr*jT4C)(jmj2>uYP8$M=#caX6OWA1Ez395U
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z%x<yAs)6-Ascr5<x*>CIZibyRlE~I0-ianVaz~q|EMlL7hc1U5w?}Kekws6fyy@`e
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z4NdX%L#2`A#c_N4ftGmuwbDo=incwf=WnBJk6)fYz%6Cmy>HwK$Y|iP`Y7sgjDPhQ
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zR|wv367k}1g)-G@kXq(X;{Bjt998b9{cpD9zGhOQ5%$4OSMtc2(<dx@0O}7_G+$WF
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zLYyaPtFT6d*e&Q$VLd0r%Yr@=*7rjEDyT7JwT8sSA<BiU8$)7mh@K2tFNMULA^I|8
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z{Sp#>gO(fCMTS^w(6xrO#}IcK^sHgMZis^heP>uIf6|z=%Cy#)Vxvjdo7U~7*k{rU
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zruB{~J}~KL(+X9Kxz*-5M>NNGSaIfXi19({d4mrk?K50@R0%Wn*PP9d(MMIzI2~RX
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z)(4h&8(YL@UyKJ*)4o${n5ZGd(hDf+)cv8sSBxWen|f*u<-sgt(u+U-bkd}Tj+5@9
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zJosfSdvPo8zGnluemJg=E7A{=N<Rc#KYYEg?^p`+_?~aU(kEmFus{DshA~iA(onLY
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zvIfpBJt;KWP4n8&`n1##c($WnDo|=?rlHBz&}36&HPWwp8op_i8c-**(TSd{Y{SZ?
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z_=^K$27e+q;^vRNU3~a=cd;V{%O=iuo*&xwXyg19${Ap0yO@a|N-<e^7iIClF{vUn
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z&4$y_V7MA)=E=%7n63u!J9FY$RK8hXHDE%%Lx$ZgX902-<9r|4lkx>QwFch>PUO1w
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z=6JffnB-kQ)VLb>sSZdDrI@U2!?HLA9Mlek!*k>;&jx<)xfnBiY^I6DRt*l*`n8ly
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zu!h)b?sRV1==Nf*Cw9&&i7n^9Nts>wk>adaY&E5OdW*A?iI}v+E6GGlsR<+#%jpl^
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zGz<Q^vpj>qhDjj3zr60Bgh=l{NzJp$x#fCR%*8!ZR?fC&JuvHmSr5#5VAcb(9+>sO
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IzvhA80TAzedH?_b
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literal 0
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HcmV?d00001
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
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new file mode 100644
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index 0000000000..b0c4638858
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--- /dev/null
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+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
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@@ -0,0 +1,17 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <bootblock_common.h>
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+#include <device/pci_ops.h>
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+#include <ec/dell/mec5035/mec5035.h>
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+#include <southbridge/intel/bd82x6x/pch.h>
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+
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+const struct southbridge_usb_port mainboard_usb_ports[] = {
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+};
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+
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+void bootblock_mainboard_early_init(void)
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+{
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+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
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+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
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+ | COMB_LPC_EN | COMA_LPC_EN);
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+ mec5035_early_init();
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+}
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
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new file mode 100644
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index 0000000000..61f01816c4
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--- /dev/null
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+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
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@@ -0,0 +1,190 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <southbridge/intel/common/gpio.h>
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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+ .gpio0 = GPIO_MODE_GPIO,
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+ .gpio1 = GPIO_MODE_NATIVE,
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+ .gpio2 = GPIO_MODE_GPIO,
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+ .gpio3 = GPIO_MODE_NATIVE,
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+ .gpio4 = GPIO_MODE_GPIO,
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+ .gpio5 = GPIO_MODE_NATIVE,
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+ .gpio6 = GPIO_MODE_GPIO,
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+ .gpio7 = GPIO_MODE_GPIO,
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+ .gpio8 = GPIO_MODE_GPIO,
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+ .gpio9 = GPIO_MODE_NATIVE,
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+ .gpio10 = GPIO_MODE_NATIVE,
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+ .gpio11 = GPIO_MODE_NATIVE,
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+ .gpio12 = GPIO_MODE_NATIVE,
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+ .gpio13 = GPIO_MODE_GPIO,
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+ .gpio14 = GPIO_MODE_GPIO,
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+ .gpio15 = GPIO_MODE_GPIO,
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+ .gpio16 = GPIO_MODE_GPIO,
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+ .gpio17 = GPIO_MODE_GPIO,
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+ .gpio18 = GPIO_MODE_NATIVE,
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+ .gpio19 = GPIO_MODE_GPIO,
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+ .gpio20 = GPIO_MODE_NATIVE,
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+ .gpio21 = GPIO_MODE_GPIO,
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+ .gpio22 = GPIO_MODE_GPIO,
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+ .gpio23 = GPIO_MODE_NATIVE,
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+ .gpio24 = GPIO_MODE_GPIO,
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+ .gpio25 = GPIO_MODE_NATIVE,
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+ .gpio26 = GPIO_MODE_NATIVE,
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+ .gpio27 = GPIO_MODE_GPIO,
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+ .gpio28 = GPIO_MODE_GPIO,
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+ .gpio29 = GPIO_MODE_GPIO,
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+ .gpio30 = GPIO_MODE_GPIO,
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+ .gpio31 = GPIO_MODE_NATIVE,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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+ .gpio0 = GPIO_DIR_INPUT,
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+ .gpio2 = GPIO_DIR_INPUT,
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+ .gpio4 = GPIO_DIR_INPUT,
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+ .gpio6 = GPIO_DIR_INPUT,
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+ .gpio7 = GPIO_DIR_INPUT,
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+ .gpio8 = GPIO_DIR_INPUT,
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+ .gpio13 = GPIO_DIR_INPUT,
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+ .gpio14 = GPIO_DIR_INPUT,
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+ .gpio15 = GPIO_DIR_INPUT,
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+ .gpio16 = GPIO_DIR_INPUT,
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+ .gpio17 = GPIO_DIR_INPUT,
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+ .gpio19 = GPIO_DIR_INPUT,
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+ .gpio21 = GPIO_DIR_INPUT,
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+ .gpio22 = GPIO_DIR_INPUT,
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+ .gpio24 = GPIO_DIR_INPUT,
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+ .gpio27 = GPIO_DIR_INPUT,
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+ .gpio28 = GPIO_DIR_INPUT,
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+ .gpio29 = GPIO_DIR_INPUT,
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+ .gpio30 = GPIO_DIR_OUTPUT,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_level = {
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+ .gpio30 = GPIO_LEVEL_HIGH,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
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+ .gpio0 = GPIO_INVERT,
|
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+ .gpio8 = GPIO_INVERT,
|
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+ .gpio14 = GPIO_INVERT,
|
|
+};
|
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
|
+ .gpio32 = GPIO_MODE_NATIVE,
|
|
+ .gpio33 = GPIO_MODE_GPIO,
|
|
+ .gpio34 = GPIO_MODE_GPIO,
|
|
+ .gpio35 = GPIO_MODE_GPIO,
|
|
+ .gpio36 = GPIO_MODE_GPIO,
|
|
+ .gpio37 = GPIO_MODE_GPIO,
|
|
+ .gpio38 = GPIO_MODE_GPIO,
|
|
+ .gpio39 = GPIO_MODE_GPIO,
|
|
+ .gpio40 = GPIO_MODE_NATIVE,
|
|
+ .gpio41 = GPIO_MODE_NATIVE,
|
|
+ .gpio42 = GPIO_MODE_NATIVE,
|
|
+ .gpio43 = GPIO_MODE_NATIVE,
|
|
+ .gpio44 = GPIO_MODE_NATIVE,
|
|
+ .gpio45 = GPIO_MODE_GPIO,
|
|
+ .gpio46 = GPIO_MODE_NATIVE,
|
|
+ .gpio47 = GPIO_MODE_NATIVE,
|
|
+ .gpio48 = GPIO_MODE_GPIO,
|
|
+ .gpio49 = GPIO_MODE_GPIO,
|
|
+ .gpio50 = GPIO_MODE_NATIVE,
|
|
+ .gpio51 = GPIO_MODE_GPIO,
|
|
+ .gpio52 = GPIO_MODE_GPIO,
|
|
+ .gpio53 = GPIO_MODE_NATIVE,
|
|
+ .gpio54 = GPIO_MODE_GPIO,
|
|
+ .gpio55 = GPIO_MODE_NATIVE,
|
|
+ .gpio56 = GPIO_MODE_NATIVE,
|
|
+ .gpio57 = GPIO_MODE_GPIO,
|
|
+ .gpio58 = GPIO_MODE_NATIVE,
|
|
+ .gpio59 = GPIO_MODE_NATIVE,
|
|
+ .gpio60 = GPIO_MODE_GPIO,
|
|
+ .gpio61 = GPIO_MODE_NATIVE,
|
|
+ .gpio62 = GPIO_MODE_NATIVE,
|
|
+ .gpio63 = GPIO_MODE_NATIVE,
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
|
+ .gpio33 = GPIO_DIR_INPUT,
|
|
+ .gpio34 = GPIO_DIR_OUTPUT,
|
|
+ .gpio35 = GPIO_DIR_INPUT,
|
|
+ .gpio36 = GPIO_DIR_INPUT,
|
|
+ .gpio37 = GPIO_DIR_INPUT,
|
|
+ .gpio38 = GPIO_DIR_INPUT,
|
|
+ .gpio39 = GPIO_DIR_INPUT,
|
|
+ .gpio45 = GPIO_DIR_OUTPUT,
|
|
+ .gpio48 = GPIO_DIR_INPUT,
|
|
+ .gpio49 = GPIO_DIR_OUTPUT,
|
|
+ .gpio51 = GPIO_DIR_INPUT,
|
|
+ .gpio52 = GPIO_DIR_INPUT,
|
|
+ .gpio54 = GPIO_DIR_INPUT,
|
|
+ .gpio57 = GPIO_DIR_INPUT,
|
|
+ .gpio60 = GPIO_DIR_OUTPUT,
|
|
+};
|
|
+
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+static const struct pch_gpio_set2 pch_gpio_set2_level = {
|
|
+ .gpio34 = GPIO_LEVEL_HIGH,
|
|
+ .gpio45 = GPIO_LEVEL_LOW,
|
|
+ .gpio49 = GPIO_LEVEL_LOW,
|
|
+ .gpio60 = GPIO_LEVEL_HIGH,
|
|
+};
|
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+
|
|
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
|
+ .gpio64 = GPIO_MODE_NATIVE,
|
|
+ .gpio65 = GPIO_MODE_NATIVE,
|
|
+ .gpio66 = GPIO_MODE_NATIVE,
|
|
+ .gpio67 = GPIO_MODE_NATIVE,
|
|
+ .gpio68 = GPIO_MODE_GPIO,
|
|
+ .gpio69 = GPIO_MODE_GPIO,
|
|
+ .gpio70 = GPIO_MODE_GPIO,
|
|
+ .gpio71 = GPIO_MODE_GPIO,
|
|
+ .gpio72 = GPIO_MODE_NATIVE,
|
|
+ .gpio73 = GPIO_MODE_NATIVE,
|
|
+ .gpio74 = GPIO_MODE_NATIVE,
|
|
+ .gpio75 = GPIO_MODE_NATIVE,
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
|
+ .gpio68 = GPIO_DIR_INPUT,
|
|
+ .gpio69 = GPIO_DIR_INPUT,
|
|
+ .gpio70 = GPIO_DIR_INPUT,
|
|
+ .gpio71 = GPIO_DIR_INPUT,
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
|
+};
|
|
+
|
|
+const struct pch_gpio_map mainboard_gpio_map = {
|
|
+ .set1 = {
|
|
+ .mode = &pch_gpio_set1_mode,
|
|
+ .direction = &pch_gpio_set1_direction,
|
|
+ .level = &pch_gpio_set1_level,
|
|
+ .blink = &pch_gpio_set1_blink,
|
|
+ .invert = &pch_gpio_set1_invert,
|
|
+ .reset = &pch_gpio_set1_reset,
|
|
+ },
|
|
+ .set2 = {
|
|
+ .mode = &pch_gpio_set2_mode,
|
|
+ .direction = &pch_gpio_set2_direction,
|
|
+ .level = &pch_gpio_set2_level,
|
|
+ .reset = &pch_gpio_set2_reset,
|
|
+ },
|
|
+ .set3 = {
|
|
+ .mode = &pch_gpio_set3_mode,
|
|
+ .direction = &pch_gpio_set3_direction,
|
|
+ .level = &pch_gpio_set3_level,
|
|
+ .reset = &pch_gpio_set3_reset,
|
|
+ },
|
|
+};
|
|
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
|
|
new file mode 100644
|
|
index 0000000000..2e3f7fa697
|
|
--- /dev/null
|
|
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
|
|
@@ -0,0 +1,32 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0-only */
|
|
+
|
|
+#include <device/azalia_device.h>
|
|
+
|
|
+const u32 cim_verb_data[] = {
|
|
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
|
|
+ 0x10280492, /* Subsystem ID */
|
|
+ 11, /* Number of 4 dword sets */
|
|
+ AZALIA_SUBVENDOR(0, 0x10280492),
|
|
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
|
|
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
|
|
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
|
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
|
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
|
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
|
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
|
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
|
|
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
|
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
|
|
+
|
|
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
|
|
+ 0x80860101, /* Subsystem ID */
|
|
+ 4, /* Number of 4 dword sets */
|
|
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
|
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
|
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
|
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
|
+};
|
|
+
|
|
+const u32 pc_beep_verbs[0] = {};
|
|
+
|
|
+AZALIA_ARRAY_SIZES;
|
|
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
|
|
new file mode 100644
|
|
index 0000000000..3bfe6b57ed
|
|
--- /dev/null
|
|
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
|
|
@@ -0,0 +1,35 @@
|
|
+## SPDX-License-Identifier: GPL-2.0-or-later
|
|
+
|
|
+chip northbridge/intel/sandybridge
|
|
+ device domain 0 on
|
|
+ subsystemid 0x1028 0x0492 inherit
|
|
+
|
|
+ device ref igd on
|
|
+ register "gpu_cpu_backlight" = "0x00000622"
|
|
+ register "gpu_pch_backlight" = "0x13121312"
|
|
+ end
|
|
+
|
|
+ chip southbridge/intel/bd82x6x
|
|
+ register "usb_port_config" = "{
|
|
+ { 1, 1, 0 },
|
|
+ { 1, 0, 0 },
|
|
+ { 1, 1, 1 },
|
|
+ { 1, 0, 1 },
|
|
+ { 1, 1, 2 },
|
|
+ { 1, 1, 2 },
|
|
+ { 1, 1, 3 },
|
|
+ { 1, 1, 3 },
|
|
+ { 1, 0, 5 },
|
|
+ { 1, 0, 5 },
|
|
+ { 1, 1, 7 },
|
|
+ { 1, 1, 6 },
|
|
+ { 1, 0, 6 },
|
|
+ { 1, 0, 7 },
|
|
+ }"
|
|
+
|
|
+ device ref sata1 on
|
|
+ register "sata_port_map" = "0x3b"
|
|
+ end
|
|
+ end
|
|
+ end
|
|
+end
|
|
--
|
|
2.39.5
|
|
|