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https://codeberg.org/libreboot/lbmk.git
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Leah Rowe
c716341c13
I realised that the Dell OptiPlex 3050 Micro has NVRAM available. Use that backend, and hardcode power_on_after_fail to Disable, which is already done in cmos.default. The Lenovo ThinkPad T480 currently has no option table in coreboot, besides the CBFS one. For this, the CBFS option table has been enabled, and the build system has been modified to insert a relevant config for power_on_after_fail. Nicholas Chin informs me that Kabylake generally has legacy NVRAM, so enabling it for the T480/T480s should work, but we'll need to use it in the future anyway; better to just use CBFS now. I *could* use the CBFS backend on 3050micro as well. Signed-off-by: Leah Rowe <leah@libreboot.org>
56 lines
2.0 KiB
Diff
56 lines
2.0 KiB
Diff
From 4a24221fc735117e521cbd7e08d71b6e6a061517 Mon Sep 17 00:00:00 2001
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From: Leah Rowe <info@minifree.org>
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Date: Sat, 4 May 2024 02:00:53 +0100
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Subject: [PATCH 15/40] nb/haswell: lock policy regs when disabling IOMMU
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Angel Pons told me I should do it. See comments here:
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https://review.coreboot.org/c/coreboot/+/81016
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I see no harm in complying with the request. I'll merge
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this into the main patch at a later date and try to
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get this upstreamed.
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Just a reminder: on Optiplex 9020 variants, Xorg locks up
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under Linux when tested with a graphics card; disabling
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IOMMU works around the issue. Intel graphics work just fine
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with IOMMU turned on. Libreboot disables IOMMU by default,
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on the 9020, so that users can install graphics cards easily.
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Signed-off-by: Leah Rowe <info@minifree.org>
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---
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src/northbridge/intel/haswell/early_init.c | 15 +++++++--------
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1 file changed, 7 insertions(+), 8 deletions(-)
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diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
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index 1a7e0b1076..e9506ee830 100644
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--- a/src/northbridge/intel/haswell/early_init.c
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+++ b/src/northbridge/intel/haswell/early_init.c
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@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void)
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const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
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u8 enable_iommu = get_uint_option("iommu", 1);
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- if (!enable_iommu)
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- return;
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-
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if (capid0_a & VTD_DISABLE)
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return;
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- /* Setup BARs: zeroize top 32 bits; set enable bit */
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- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
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- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
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- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
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- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
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+ if (enable_iommu) {
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+ /* Setup BARs: zeroize top 32 bits; set enable bit */
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+ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
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+ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
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+ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
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+ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
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+ }
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/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
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u32 reg32;
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--
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2.47.3
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