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lbmk/config/coreboot/default/patches/0028-mb-lenovo-Add-ThinkPad-T480-and-ThinkPad-T480s.patch
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Leah Rowe dd65f55b29 coreboot/default: bump rev 812d0e2f62, 5 Apr 2025 
There are *many* excellent changes. These changes are of note,
for Haswell mainboards (raminit improvements, courtesy Angel Pons):

* d5854e4139 Haswell NRI: Implement COMP offset optimisation
* f14880934b Haswell NRI: Use final timings after basic training
* ab29f52ee2 Haswell NRI: Measure per-task execution time
* 4ae9a79d8d Haswell NRI: Remove unused `SPD_LEN` define
* 0c5286ba34 Haswell NRI: Tidy up REUT subsequence programming
* 7766228798 Haswell NRI: Deduplicate PCODE mailbox functions

My GMP fixes have been removed, because upstream did
similar fixes which accomplish the same result.

This brings in the following upstream changes:

* 812d0e2f62 Documentation/lib: Update Timestamp documentation
* d461627668 payloads/Kconfig: Allow compression for Linux payloads
* f3ca3aa16b util/cbfstool/cbfs-payload-linux: Copy segments when compression fails
* 29440057b0 mb/starlabs/{adl_n,twl}: Don't use the IOT FSP
* eaf76d2dd1 vc/intel/fsp2_0/twinlake: Update FSP headers
* d5854e4139 Haswell NRI: Implement COMP offset optimisation
* 2739c4b773 SBOM: Change makefile to get versions from build.h
* a4156f99ff soc/intel/ptl: Add Wildcat Lake CPU ID to platform reporting
* 9f73b04074 soc/intel/pantherlake: Add new MCH ID for Wildcat Lake
* 167c771bc5 mb/google/fatcat/var/francka: Enable audio codec ALC722/ALC1320
* d8455dfbf6 mb/trulo/var/pujjolo: Change wifi SAR id fw config bits
* a9e97268fe crossgcc: Fix acpica base url version
* dabc200abb mb/lenovo/m900_tiny: enable power LED blink in S3 and S4
* cb86b9a089 mb/lenovo/m900_tiny: Put options in CFR cbtable
* 26d6da4533 mb/lattepanda/mu: Correct UART1 pinmux for native mode
* 2ec9a9f17d mb/lattepanda/mu: Update eDP/HDMI in devicetree
* 3cfa24c1bf mb/lattepanda/mu: Enable PMC drivers
* c3dba4da2b mb/lattepanda/mu: Add flashmap definition
* b5db9bcc9d soc/intel/alderlake: Enable USB3 HSIO related parameters for USB3 GEN2 support
* da49da6c82 soc/intel: Add Arrow Lake-S/HX IDs
* 8cec500968 mb/google/skywalker: Configure firmware display for eDP panel
* 78a89d4d70 soc/mediatek/mt8189: Extract code to disable secure mode from DDP driver
* 8d8d0f9746 soc/qualcomm/x1p42100: Add Clock support for x1p42100
* 20c2813891 soc/qualcomm/common: Update QUP register structure for QUP v3.2
* d24c4086e1 Documentation: Add Ramstage Bootstates
* 10d01fc2de Documentation: Add Threads
* faf0f29f8d mb/google/ocelot: Update EC host command range for variants
* ac4dfa5762 mb/hp/snb_ivb_desktops: Add Compaq Pro 6300 MT/SFF variant
* 984c64295b drivers/crb/tpm: Add new method to retrieve base address
* 1e8e5d902a mb/starlabs/starlite_adl: Add support for MXC6655 accelerometer
* 5993dd6ef5 Documentation: Add Timers, Stopwatch, and Delays
* 4f1f502fd5 soc/mediatek/mt8189: Add PI image loader in ramstage
* e3ffa3c14f soc/meidatek/mt8196: Move PI image related code to common
* e96bf7e094 soc/qc/x1p42100: Support to generate Bootblock as multi ELF
* ae5810e358 util/qualcomm: Add MBN v7 format support
* 626c5364b8 tree: Use boolean for PcieRpSlotImplemented[]
* a90a7e0aed mb/google/bluey: Specify ROM size per board variant
* 0c9204046a mb/google/bluey: Update SPI flash vendor selection
* d636b38577 soc/qualcomm/x1p42100: Select ARM64_USE_ARM_TRUSTED_FIRMWARE
* 17abedaef6 include/smp/node: Drop unused is_smp_boot
* c0413336bc acpi/acpi.h: Use boolean
* 9be383b855 drivers/lenovo/hybrid_graphics/chip: Use boolean when appropriate
* f33507c1d8 mb/{google/zork,novacustom/mtl-h}: Use true/false for boolean
* ae282fe502 drivers/generic/bayhub: Use boolean for power_saving
* 0a94fcd2db crossgcc: upgrade binutils from version 2.43 to 2.44
* 316f76635f soc/mediatek/mt8189: Use pmif_spmi_v2 for MT8189
* f3bd8b7a07 soc/mediatek/pmif_spmi: Move pmif_spmi_force_normal_mode() to common
* ef10e93e0a tree: Replace scan-build by clang-tidy
* 6707e9281c mb/google/brox: Update cpu power limits
* f1aa0a175b util/crossgcc: Build compiler-rt using runtimes
* b0e0c688c8 buildgcc: Use -d to check libstdc++ include directory
* f2fed71533 crossgcc: Upgrade acpica from 20241212 to 20250404
* 07a8737cbd crossgcc:Initialize OPT_LDFLAGS to avoid unset variable in IASL build
* ad9bfd4243 crossgcc: Always update HOSTCFLAGS from GMP headers if already built
* c3f5d7c1ee crossgcc: Upgrade MPFR from 4.2.1 to 4.2.2
* a3ea1cb542 util/crossgcc: Upgrade CMake from 3.31.3 to 4.0.3
* f9cde87f5a crossgcc/buildgcc: Fix GMP-6.3.0 build with GCC 15 using proper prototypes
* 35d6ee9223 crossgcc/buildgcc: Remove invalid option for CMake
* bd36a4a465 util/lint: Remove missing dirs from checkpatch linter
* a0f2e42879 util/lint: Improve final newline check
* 6cb9efa19a util/lint: Ignore opensil for Kconfig linter
* 5228b3ef7b util/lint: Ignore binary files for cb lowercase linter
* 58d450d2dc util/crossgcc/buildgcc: Reorganize toolchain version variables
* baf28f8668 mb/trulo/var/pujjolo: Add GPE configuration
* eb749f2416 spd/lp5: Add SPD for MT62F2G32D4DS-023 WT:C
* 731bea2fc1 mb/lattepanda/mu: Make VBT compatible with ADL-N FSP IPU25.3
* 6b7f697309 util/amdfwtool/amdfwread.c: Properly error out in relative_offset()
* 4a99023e0f util/amdfwtool/amdfwread.c: Remove APOB_NV special case
* 000ac2cc38 util/amdfwtool/amdfwtool.c: Use physical address for APOB_NV
* d0355cb647 util/amdfwtool: Move APOB_NV quirk to amdfwtool.c
* 6fa44461e7 mb/google/fatcat/var/kinmen: Add Fn key scancode
* dd7956bfc5 mb/google/ocelot: Update GPIO table
* 1222c704b5 mb/google/fatcat/var/felino: Add pull high setting on GPP_V12 and NC_LOCK GPP_F09
* 61d74dc8f7 payloads: Propagate SPI flash address mode flag to libpayload
* 8dec5fcaf8 drivers/spi: Add 4-byte address mode flag to lb_spi_flash
* a01c368a8a drivers/spi: Refactor 4-byte addressing mode handling in SPI flash
* 30e7e604fb mb/google/fatcat/var/fatcat Align I2S and DMIC pad configuration
* 9fe1546ffe Docs/releases: Update 25.06 release notes
* 5c281529ea mb/trulo/var/pujjolo: Add FW_CONFIG for mipi camera
* e5e79de8cc mb/trulo/var/pujjoquince: Add Fingerprint function
* 0dcea61e7c cbfstool: Add multi ELF support
* 6a02f2d4a7 util/qualcomm: Add script to concatenate ELF images
* 3a0b6f625a mb/google/trulo/var/pujjocento: Enable WiFi SAR table
* 64a79d23e8 mb/trulo/var/pujjoquince: Add SD card function
* b726a9c7e9 mb/google/fatcat: Create new fatcatite4es variant
* e7984f39eb mb/google/fatcat: Create new fatcatnuvo4es variant
* cdf0c76dc8 mb/google/fatcat: Create new fatcat4es variant
* 8e5bdde028 mb/intel/ptlrvp: Add support for H58G66BK7BX067 memory
* 110aebb4d2 mb/google/nissa/var/riven: Add focaltech touchscreen support
* bc8876d56d Revert "soc/intel/xeon_sp/uncore.c: mark TSEG/SMM region as reserved"
* 64d4888349 mb/google/dedede/var/magolor: Generate SPD ID for CXMT CXDB4CBAM-ML-A
* cc116e08aa mb/google/nissa/var/quandiso: Add touchscreen FTSC1000 support
* 35648dc37b acpi: Add _func suffix for callback functions
* 03be570994 mb/google/rauru: Remove unused get_oled_description
* cc0a410ff5 soc/mediatek/dp: Correct eDP register settings for dptx_v2
* 056405a10d mb/google/ocelot: convert variants for use with ES silicon
* 4ef51ffbd7 mb/google/skywalker: Add panel driver in mainboard
* cdb49c4d2e soc/mediatek/mt8189: Add ddp driver to support eDP output
* d8fc5eba2d soc/mediatek/mt8189: Add eDP driver
* cfd0b4dd20 soc/mediatek/mt8189: Change msdcpll default freq to 384MHz
* a60c5d205b mb/google/nissa/var/meliks: Initialize display signals on user mode
* f846ec1e37 mainboard/google/fatcat: Set OEM footer logo bottom margin
* 97f92d5c69 drivers/intel: Add support for configurable footer logo bottom margin
* 3e0d8a2f2c mb/google/bluey: Enable 4-byte addressing mode
* 5568bee055 drivers/spi: Support forced 4-byte address mode via 0xB7 command
* a66d2d41f5 mb/lenovo/m900/devicetree.cb: Use OC6 enum
* f14880934b Haswell NRI: Use final timings after basic training
* 0e5d1d29bd soc/intel/skylake: Expand USB OC pins enum to OC7
* 1f28803dcd mb/trulo/var/kaladin: Create kaladin variant
* 1c2978dba6 mb/google/dedede/var/awasuki: Add ChangXin modules to RAM id table
* 912161e52d spd/lp4x: Modify parameters of SPD for NT6AP1024F32BL-J1
* 47f1b798e4 util/amdfwtool/amdfwtool.c: Remove APOB_NV src address check
* c7fe471482 mb/novacustom/mtl-h/var/dgpu: Add NVIDIA dGPU ASL code
* 24d8e6f35e Revert "mb/google/brox: Handle GPI_INT pin lower to GPI_WAKE"
* cf7159af64 mb/siemens/mc_ehl3: Limit eMMC speed mode to DDR50
* 68ede7b860 mb/google/nissa/var/meliks: Configure Acoustic noise mitigation
* ea3cc3231c mb/intel/ptlrvp: Remove power limit constraints
* cae47dfd44 soc/intel/pantherlake: Correct DRHC and SATC in DMAR table
* e58883aace soc/intel/pantherlake: Refactor VR Fast Vmode I_TRIP threshold settings
* abbf549558 mb/google/fatcat: Add support for new Panther Lake IDs
* 57bffed893 soc/intel/pantherlake: Add new PCI and CPU IDs
* 59fce656b1 soc/intel/pantherlake: Enable Thermal Design Current for various SKUs
* 5a2de49baa soc/intel/cmn/blk/power_limit: Add helper functions to romstage
* 2207a4b59a vc/intel/fsp/fsp2_0/pantherlake: Add TDC current limit configuration
* efa24540b0 drivers/wifi/generic: Implement Bluetooth PRR DSM functions
* d92b6163e7 drivers/wifi/generic: Implement Wi-Fi PRR DSM functions
* 81d7bc386e soc/intel/cmn/blk/cnvi: Set WFDL default value to 50 ms
* 1be1ccb42e soc/intel/cmn/blk/cnvi: Use WFDL field for Wi-Fi PLDR reset delay
* ff46501d6d soc/intel/cmn/blk/cnvi: Correct generated ACPI code in comments
* 782ae11bc7 soc/intel/cmn/blk/cnvi: Add _PRR method for Bluetooth CNVi Reset
* 23f5df6eae mb/google/nissa/var/yavilla: Add H58G66CK8BX147 to RAM ID table
* 4a2c61a8a0 soc/qc/x1p42100: Allow building QC platform without upstream blobs
* 2a09db3c29 drivers/intel: Refactor logo rendering with helper functions
* 57d29ebd74 vc/google/chromeos: Don't pack `cb_plus_logo.bmp` if footer is present
* ef051256dc mainboard/google/fatcat: Drop logo_valignment selection
* dfeaead9f2 drivers/intel: Add horizontal logo alignment for splash screen
* ced9f91ae9 soc/intel/cmn: Improve comments for fw_splash_vertical_alignment enum
* d309a9dfa8 drivers/intel/fsp2_0: Suppress OEM footer in low-battery mode
* 4373eea5d8 {lib, drivers/intel}: Add splash screen footer
* be5609bdaf lib: Introduce a new function `bmp_load_logo_by_type()`
* a1dbb4076c lib: Add support for different bootsplash types
* f48865ab9a drivers/intel/fsp2_0: Refactor bitmap loading and GOP BLT conversion
* f3f9c0bd8e soc/intel/ptl: Add PCIe ACPI support for Wildcat Lake SoC
* ba715b3d25 mb/google/nissa/var/guren: Add SPD ID for MT62F512M32D2DR-031 WT:B
* 43b6f44e22 soc/mediatek/mt8189: Remove ulposc1 hardware calibration
* f63016c36f soc/mediatek: Unify DPTX swing/preemphasis API
* df91698b11 soc/mediatek/mt8196: Refactor mt8196 eDP driver for better code sharing
* 03fca0f0b4 mb/google/brox: Enable support for Realtek EC
* c8eb52c10c ec/google/chromeec: Modify Realtek EC initialization timing
* e2ac46bcc7 spd/lp5: Add SPD for hynix H58G66CK8BX147
* 812379f500 soc/mediatek/common: Move map_to_lpddr_dram_type() to common for reuse
* 7c19b1fa58 mb/google/skywalker: Run MTK FSP binary in ramstage
* 89e4fff2d3 crossgcc/buildgcc: introduce RISCV_ISA_SPEC for RISC-V ISA specification
* 620c8d9f71 mb/google/brask/var/constitution: Generate RAM ID for B3221XM3BDGVI
* 57b12d2171 spd/lp4x: Generate initial SPD for B3221XM3BDGVI
* 7c0da94aeb mb/google/brya/var/pujjoga: Add and select VBT
* bcd569faf1 mb/google/skywalker: Create variant Baze
* fb2c834f7c mb/trulo/var/pujjolo: Fix p-sensor function
* a7cd5c8c6b mb/trulo/var/pujjolo: Enable USB3 functions
* 2c53151c0c mb/trulo/var/pujjolo: Enable Ax211 wifi function
* ad78fc535a mb/trulo/var/pujjolo: Add single ram configuration
* f941b51e0e soc/mediatek/mt8189: Correct MFG MUX OPP init setting
* a1d9b69f47 soc/qc/x1p42100: Add metadata files for shrm and cpucp
* b369756680 util/qualcomm: Add script to extract a segment from ELF
* 19d1604fd7 mb/google/bluey: Update flash layout
* b9aae6180b mb/google/nissa/var/meliks: Link touchscreen device with display panel
* 6e58c0148b Reland "libpayload: arm64: Reduce DMA allocator space to 1MB"
* f18420b6a9 mb/google/fatcat: Create new felino4es variant
* 992ba78142 mb/google/fatcat: Create `felino` model for easier variant integration
* afbc9126f9 mb/trulo/var/pujjolo: Update GPIOs and probe SD card to fix S0ix suspend
* b3b1809764 mb/google/octopus: Correct channel count for DMIC
* 9accaa7238 mb/google/poppy: Correct channel count for DMIC
* 41e09a5c59 mb/google/fizz/var/karma: Correct channel count for DMIC
* fed7ad967a mb/google/reef: Correct channel count for DMIC
* 686dea9883 mb/google/glados: Correct channel count for DMIC
* ea6f150d9d soc/intel/cmd/blk/cnvi: Correct conditional logic for CNVI readiness
* 29dd511628 soc/intel: Move CNVI sideband definitions to SoC-specific files
* ea8a3e685f soc/intel/cmn/blk/cnvi: Add descriptive comments for PRRS and RSTT
* d17ace2c1b soc/intel/cmn/blk/cnvi: Remove hardcoded offset in OperationRegion
* bb3a484e36 soc/intel/*/acpi: Move the BASE ACPI method to northbridge
* 3c88e629d9 mb/google/brox/var/lotso: Generate RAM IDs for lotso
* 1bdf89d78c device/device_util.c: Complete function documentation
* bc84e1ba42 soc/intel/cmn/acpi: Refactor `SPCO` ASL method
* 4bf0f4fab3 mb/google/fatcat/var/felino: Add PIXART touchpad to devicetree
* 8269a89d32 mb/google/fatcat/var/felino: Add Synaptics touchpad to devicetree
* 4d9dfb63bd Documentation: fix broken flashrom.org link
* 3696fea4e0 mb/google/ocelot: add BOARD_GOOGLE_OCELOTMCHP
* 6ebd30bf7d mb/google/ocelot: add BOARD_GOOGLE_OCELOTITE
* da122fe8f5 mb/starlabs/*: Use PLTRST for PCH Strap GPIOs
* 7f03e3bd6c drivers/efi/efivars: Change printk level from ERROR to DEBUG
* c740786f12 drivers/gfx/generic: Use 'noop_read_resources'
* b1759c9bd6 mb/starlabs/starlite: Adjust the Flash Map to match the Twin Lake IFD
* cc1f0e5c90 mb/starlabs/starbook: Disable TME_KEY_REGENERATION_ON_WARM_BOOT
* 9381dd0cbf soc/intel/meteorlake: Make TME_KEY_REGENERATION_ON_WARM_BOOT selectable
* 9b91d50fc1 mb/siemens/mc_rpl1: Add GPIO configuration
* f44b19f2dc soc/intel/pantherlake: Fix ACPI can't tag data node error
* fad0064377 soc/intel/ptl: Add UFS support for Wildcat Lake SOC
* 3a065dbbfc mb/google/nissa/var/yavilla: Add H58G56CK8BX146 to RAM ID table
* 98f1886c89 mb/google/nissa/var/yaviks: Add H58G56CK8BX146 to RAM ID table
* 3711be4e18 soc/intel/xeon_sp: Use Kconfig to define SPI_BASE_ADDRESS
* ad05c65d72 soc/intel/xeon_sp: Initialize SPI before using it
* b4f2a51533 libpayload/arch/arm64/mmu: Fix missing CBMEM in used ranges
* 6da913bd46 docs/security/vboot: Update supported board list
* a0e6fd9a95 Documentation: Add coreboot release 25.09 template
* d4a33638f5 mb/trulo/var/pujjolo: Change dram id table
* 2ee72eaab1 soc/intel/pantherlake: Update CONSOLE_UART_BASE_ADDRESS Kconfig value
* 25385df017 vc/intel/fsp/ptl: Update PTL header files to FSP 3182_01
* 2286134002 mb/google/fatcat/var/felino: Configure CAM_VDD_EN_SOC GPIO to restore camera function
* 486604360c mb/google/ocelot: add BOARD_GOOGLE_MODEL_OCELOT
* f6926dc8a5 mb/google/nissa/var/pujjoniru: Update DTT settings for thermal control
* bb022f18d5 mb/google/dedede/var/awasuki: Add 2 NANYA modules to RAM id table
* 4ef1258436 spd/lp4x: Add Nanya memory part
* 99c138ec50 soc/mediatek: Don't attempt de-assert PERST# without pci_root_bus
* b9754131a6 mb/google/ocelot/var/ocelot: Update initial overridetree settings
* 4199351c1b Revert "libpayload: arm64: Reduce DMA allocator space to 1MB"
* a11eacc204 mb/msi/{ms7d25,ms7e06}/devicetree.cb: Add fan control config
* a069c920f5 mb/msi/{ms7d25,ms7e06}: Mimic the vendor BIOS early SIO init
* 3c23d7b3a9 src/superio/nuvoton: Add HWM initialization code
* ace18dea15 mainboard: Add 2S Intel Birch Stream MiTAC Computing R520G6SB
* 4569adeedc mainboard: Add 1S Intel Birch Stream MiTAC Computing SC513G6
* ab29f52ee2 Haswell NRI: Measure per-task execution time
* 925845c38c mb/google/ocelot: Update Kconfig
* c796c68dec mb/google/ocelot: Update MAINBOARD_PART_NUMBER
* b322d30944 mb/google/brya/var/moxie: Enable RTD3 for SSD to resolve S0ix issue
* f85f7d7aed mb/intel/beechnutcity_crb: Use host address for BiosRegionBase
* 4d3dc433f9 mb/intel/avenuecity_crb: Use host address for BiosRegionBase
* 881fe9cef6 soc/intel/alderlake: Add cpuid_to_adl mapping for Core 3 N350 SoC
* 08c8a74170 mb/trulo/var/pujjolo: Add MB usb-a port3 function.
* 317affb0ad mb/trulo/var/pujjolo: Enable Elan touchscreen function.
* de259ad970 mb/trulo/var/pujjolo: Enable s0ix function
* 712dfb3761 Revert "util/cbmem: Consolidate CBMEM and coreboot table access"
* 30865c2fb1 mb/amd/birman_plus: Skip i2c_early init
* f2e488cfbf mb/google/fatcat: Add power limit overrides for H204 and H404 SKUs
* 1537c89e8d soc/intel/cmn/block/power_limit: Enforce variant PL4 for Fast VMode
* d9c5cef7f0 soc/intel/pantherlake: Add Fast VMode PL4 Power Limit configuration
* b879342fe6 soc/intel/pantherlake: Add support for the H204 SKU
* b42842bbe5 mb/google/brox: Add brox_rtk_ec variant
* 73cc8a413a treewide: Work around GCC 15 Werror=unterminated-string-initialization
* d00f5c2d8c mb/google/skywalker: Reset xsphy0 in mainboard_init
* 40bf6c28f8 soc/mediatek/mt8189: Add support for USB port 0 reset
* 26fd33a92a mb/starlabs/starlite_adl/acpi: Fix _GPE callback type
* d14a3e23da mb/starlabs/starlite_adl: Clarify pmc_gpe0_dw0 mapping in devicetree
* 2c0417ea06 mb/starlabs/starlite_adl: Remove duplicate GPP_E12 entry
* 7e711a5bef Reland "soc/mediatek/mt8196: Specify MTKLIB_PATH for building BL31"
* 47f2c17961 mb/starlabs/*: Add CFR option to enable/disable S0ix
* dc3d524d19 mb/starlabs/starlite_adl: Use SoC common CFR forms
* 808c982104 mb/starlabs/starfighter: Use SoC common CFR forms
* 644fd7b7f5 mb/starlabs/starbook: Use SoC common CFR forms
* c7a1539d87 mb/starlabs/lite: Use SoC common CFR forms
* 3f16609ba2 mb/starlabs/byte: Use SoC common CFR forms
* c3be703b71 soc/intel/common/cfr: Add bool option for auto power on
* b3ac5ecdac soc/intel/cmn/block/cfr: Add CFR form for pciexp_aspm_cpu
* 9f8e5ab661 soc/intel/cmn/block/aspm: Use separate option variable for CPU RP
* 4247128e39 soc/intel/cmn/block/aspm: Fix ASPM control for CPU root ports
* b66b7f7860 commonlib/device_tree.c: Add a function that reads FDT ints
* c776d2dbd6 ec/google: Add support for Realtek EC in ChromeOS EC
* 8b54428200 mb/google/nissa: Override GPIO_PCH_WP for pujjocento variant
* 2060f24d60 mb/system76/mtl: Add Darter Pro 11 variants
* c2496bc62e drivers/analogix/anx7625: Add a retry mechanism to decode EDID
* 7b1eac4192 soc/mediatek/mt8189: Enable MUXes for improved peripheral stability
* da54093bb9 Update arm-trusted-firmware submodule to upstream master
* 40c84c2577 mb/starlabs/*: Tidy up the devicetree files
* cb7d2ebe5c mb/starlabs/starbook/{kbl,cml,tgl}: Remove generic.detect from the touchpad
* c4eb645a0b update_submodules: Fix submodule path handling
* 581af94115 ec/dasharo/ec: Add DTT power and battery participants
* f6dd8f534f MAINTAINERS: Add Dinesh as intel/pantherlake and google/fatcat maintainer
* f2310ab35e update_submodules: Prefix commit title with relative path
* 5fcbc709ec mb/google/fatcat/fmap: Add 1 MB from SI_BIOS to SI_All
* 24778a25de mb/trulo/var/pujjolo: Fix gtx functions.
* 619699648f soc/intel/pantherlake: Simplify P2SB and P2SB2 device operations
* beafbfd29a soc/intel/pantherlake: Remove IOE support and references
* 5277bc4efc soc/intel/pantherlake: Resolve memory corruption by using P2SB2 driver
* 61ac238bb5 soc/intel/common/block/p2sb: Add driver for second P2SB device
* 8961f6681f soc/intel/common/acpi/pcie_clk: Fix ACPI conditional compilation error
* 471df8ca5e util/crossgcc/buildgcc: Fix GMP build on GCC 15
* c24a12db86 util/cbmem: Consolidate CBMEM and coreboot table access
* 99e5a386c2 mb/amd/birman_plus/glinda: Add onboard devices
* 033810a7db payloads/libpayload/Makefile.mk: Replace nm with $(NM)
* a1738e87b5 soc/intel/panterlake: avoid SPI access delay
* 359ae67668 elog: Handle elog in later boot phase
* bf330f2dd0 security/vboot: Back up CMOS data later boot phase
* 45febdec26 mb/starlabs/starfighter: Add reset GPIO for the USB Bluetooth
* a9a51f9916 mb/starlabs/starfighter: Add missing ASPM config for the SSD
* 644ebf5ebc mb/starlabs/starbook/{adl,rpl}: Add generic Graphics driver config
* 902df45eab mb/starlabs/starfighter: Remove the overcurrent config
* b872c50f90 mb/starlabs/starfighter: Add generic Graphics driver config
* cfdf5906fd mb/starlabs/starfighter: Tidy comments for board ID GPIOs
* 9950825a2b mb/starlabs/starlite_adl: Remove extra lines
* 6d079d45d1 mb/starlabs/byte_adl: Remove comments for disconnected GPIOs
* f6a45f6856 mb/starlabs/byte_adl: Re-organise GPIOs
* 63f781b508 mb/starlabs/byte_adl: Disconnect unused GPIOs
* 6aeebc4b4b mb/starlabs/byte_adl: Reconfigure PCH Strap GPIOs
* 5f9046cbb4 mb/starlabs/byte_adl: Remove vGPIO configuration
* c589142c28 mb/starlabs/byte_adl: Add the Byte Mk III variant
* 2cb9c3ee46 mb/starlabs/byte_adl: Update the VBT to the Twin Lake version
* ad8ccf4822 Update arm-trusted-firmware submodule to upstream master
* c615de7248 soc/amd/glinda: Don't let OS put debug UART into D3
* 0251e98e9e util/amdfwtool: Do not attempt to continue processing `--help`
* 0af68855c0 mb/google/nissa/var/pujjoniru: Config AUX gpio to correct TCSS port
* bba9d27145 mb/google/ocelot: Remove power limit override functionality
* b3776e23a7 ec/google/chromeec: Add SPI/I2C EC communication files to bootblock
* be6787a55e mb/google/skywalker: Add storage types to fw_config
* 0a41779e2e mb/google/skywalker: Add eMMC configuration
* 3e6b47980a mb/google/skywalker: Add support for getting storage id
* de251dd677 soc/mediatek/mt8189: Add support AUXADC
* a283246ef7 soc/mediatek/common: Refactor auxadc driver to support new platform
* 94686e581a mb/google/skywalker: Add DVFS support in romstage
* 8ede4bc67b soc/mediatek/mt8189: Add DVFS driver
* 096ce4b244 soc/mediatek/mt8196: Move dvfs_init() declaration to dvfs_common.h
* 0b1bc3df2c mb/trulo/var/pujjocento: Support x32 memory configuration
* 7690442d88 mb/starlabs/byte_adl: Tidy the Kconfig selections
* ab8339770e 3rdparty/fsp: Update submodule to upstream master
* 8e3adf778b soc/mediatek: Add data_version to ddr_base_info struct
* 0cdd4125be mb/trulo/var/pujjolo: Fix touchscreen function and boot up issue
* 99e0484000 mb/google/bluey: Increase bootblock size to 120KB
* 1840fb49e0 mb/google/trulo/var/pujjocento: Update gpio setting for DDI-B
* 69a067a9d6 mb/google/skywalker: Add RT1019 support for beep sound
* 4caf5131b9 mb/google/skywalker: Add ALC5645 support for beep sound
* 623caa537f mb/google/skywalker: Add RT9123 support for beep sound
* 16ff3b33ce mb/google/skywalker: Add SD card configurations
* 3b68408693 mb/google/trulo/var/pujjocento: Configure USB related settings
* 6c87853a83 mb/google/bluey: Implement board and SKU ID retrieval
* 830a887ecb mb/google/bluey: Add WLAN and SSD PCI devices to devicetree
* 891c208835 soc/qualcomm/x1p42100: Enable basic PCIe support
* a5d99a814a soc/qc/x1p42100: Perform `soc_mmu_init` inside early bootblock init
* 481001e13b soc/qualcomm/x1p42100: Add placeholder for early clock initialization
* 77c6104645 Revert "mb/google/rex: Enable use_gpio_for_status for touchscreen"
* 715e7e51c5 mb/google/fatcat/var/francka: Add support for DMIC0
* c16891ecbd soc/intel/meteorlake: Use CACHE_TMP_RAMTOP for TME exclusion range
* 394dfcaa7b mb/intel/ptlrvp: Handle GPIO support for DDR5 configuration
* 58165618da mb/google/byra/var/craask: Add VBT for HDMI variant
* ab160ca301 mb/google/byra/var/teliks: Add default VBT
* 4d5b32f7f7 mb/google/ocelot/var/ocelot: remove unused gpios
* 0e5757bfa7 mb/google/trulo/var/pujjocento: Update DTT settings for thermal control
* c34baacc72 soc/mediatek/common: Add UFS2.2 and eMMC definitions to storage.h
* f325409784 soc/mediatek/mt8189: Add SD card support
* ae435c014c soc/mediatek/mt8189: Configure and early initialize eMMC
* 91ebbb8d35 mb/trulo/var/pujjolo: Modify pujjolo variant
* aea05e51a7 mb/google/trulo/var/pujjocento: Enable WWAN function
* 47133a716d mb/google/trulo/var/pujjocento: Add P-sensor support
* 04c0527aba soc/mediatek/mt8189: Support different PMIC soluitons for MT8189(G/H)
* 80149f55f7 soc/mediatek/common: Convert spmi_dev_cnt to a function
* dcf403e43a mb/google/skywalker: Configure fingerprint pins
* 508d910ed4 libpayload/arch/mock: Select ARCH_HAS_NDELAY for ARCH_MOCK
* 96ac0224ab pci: Add support for assigning resources to SR-IOV VF BARs
* ba8be19122 mb/intel/ptlrvp: Update Kconfig for PTLRVP_CHROMEEC
* 7cbbf786cc update_submodules: Use relative paths to submodules
* dcc8400e27 mb/google/fatcat/var/felino: Modify GPIOs config
* 99af85ad36 mb/google/puff: Add VBTs for Moonbuggy and Scout variants
* 4ae9a79d8d Haswell NRI: Remove unused `SPD_LEN` define
* 0c5286ba34 Haswell NRI: Tidy up REUT subsequence programming
* 7766228798 Haswell NRI: Deduplicate PCODE mailbox functions
* ae68ef3684 cpu/intel/haswell: Export PCODE mailbox functions
* ddce240d34 cpu/intel/haswell: Clean up Makefile
* 2117ed850f mb/google/ocelot/var/ocelot: fix storage configs for ocelot
* c5488c0d6d mb/google/ocelot/var/ocelot: update gpios
* 6602a4462b mb/google/ocelot/var/ocelot: Enable hda device for AUDIO_ALC721_SNDW.
* 99b6ff25d4 soc/mediatek/mt8189: Add MTK FSP loader in ramstage
* c4fe5e2483 mb/google/skywalker: Pass reset GPIO parameter to BL31
* f59ced2c7c mb/google/fatcat/var/francka: boot up by pressing power button in S5
* df0221e62a libpayload: Protect against trying to use weak symbols in the wrong way
* d27e8ef460 update_submodules: Add an empty log line between each iteration
* d9bd7ce89f mb/google/fatcat/var/francka: Enable audio codec ALC721
* 48fbd99223 mb/google/fatcat/var/francka: Set the default HDA GPIO pin to an NC pin
* 3b975f92c7 soc/intel/pantherlake: Select TME support for the SoC
* 8408bd4863 soc/intel/pantherlake: Add TME configuration
* dc36a725d6 3rdparty/fsp: Update submodule to upstream master
* 1f47b0e018 3rdparty/intel-microcode: Update submodule to upstream main
* 4c446751c6 {commonlib, drivers}: Track firmware splash screen rendering completion
* ccb8b34194 Revert "mb/var/uldrenite: Use VBT with limited resolution for 4GBx32 memory"
* 1a00629ae2 mb/google/skywalker: Set up open-drain ChromeOS pins
* 0f2942b513 mb/google/skywalker: Raise little core CPU frequency to 2.0 GHz
* 0ba0d03140 mb/google/skywalker: Implement regulator interface
* 090bce1042 soc/mediatek/common: Add VMODEM and VSRAM_MD bucks support for MT6359
* c74610afae soc/mediatek/mt8189: Shut down PMIC on power key long press
* d1f7565403 mb/google/skywalker: Notify EC that AP is in S0
* da45a88dd3 util/abuild: Fix checking of missing_arches
* cdcbb71936 mb/google/link: Use chromeec_smi_sleep()
* 885aacf004 mb/google/byra/var/teliks: Add VBT for 11" panel option
* 2ce777f178 mb/google/byra/var/yaviks: Add VBT for yavilla
* 0db4444446 mb/google/byra/var/pujjo: Add VBT for pujjo1e
* 8c3e6ea319 mb/google/nissa/var/pujjocento: Enable touchpad
* 643bba345c mb/google/trulo/var/pujjocento: Enable touchscreen
* 3ecaf04dad mb/var/uldrenite: Use VBT with limited resolution for 4GBx32 memory
* 71ae2c7366 mb/google/octopus: Add VBTs for DOOD and FOOB variants
* 7a703fc1fb mb/google/rex: Select IOM_ACPI_DEVICE_VISIBLE
* 0121d0e3e0 ec/google/chromeec/smi: Clear events before enabling wake mask
* 5a947da94e mb/google/sarien: Update VBT from v221 to v228
* 0fba735482 soc/intel/cmn/blk: Refactor CSE status flag and optimize forced sync
* bb8d069dd3 vc/google/chromeos: Move pvmfw cbmem and enable
* f562992da1 mb/google/trulo/var/pujjocento: Enable EC keyboard backlight
* d281a3c559 mb/google/trulo/var/pujjocento: Configure tcss_aux_ori
* 7150c5e2fe mb/google/skywalker: Create variant Anakin
* aedc177f00 libpayload: arm64: Reduce DMA allocator space to 1MB
* 4ccb4a78c4 libpayload: Use Kconfig instead of weak symbol for arch_ndelay()
* 37513297d3 libpayload: Use Kconfig for architecture memcpy, not weak symbols
* bcbe17dea3 mb/google/skywalker: Configure TPM
* 3d40b7d018 soc/mediatek/mt8189: Increase bootblock size from 60KB to 70KB
* 8d25cf3ae7 soc/mediatek/mt8189: Add SSPM loader
* 8ab9f56470 mb/google/skywalker: Set up SPM in mainboard
* 368eeb7da4 soc/mediatek/mt8189: Add MCUPM loader
* bc3af56fdd soc/mediatek/mt8189: Add SPM loader
* 98782a59e9 mb/google/fatcat/var/kinmen: Add overridetree
* bbcb222f0b mb/google/fatcat/var/kinmen: Update GPIO table
* 743e3a07f5 mb/google/brya/var/nissa: Remove duplicate ACPI device GFX0
* 87110309d4 mt8196: Remove mcupm_plat.h header from mcupm_plat.h
* d6fe379e9c mb/google/ocelot: Enable LP5 and DDR5 memory configuration
* 2985af84c3 mb/google/trulo/var/pujjocento: Add Fn key scancode
* dafd7d6eb9 mb/google/nissa/var/dirks: Deassert RTL8111H's ISOLATE_ODL earlier
* c1df30db18 mb/siemens/mc_rpl: Delete fw_config since it is not used
* 7fbea3175d mb/siemens/mc_rpl: Remove unused gpio and devicetree files
* 8fdf8694e3 mb/siemens/mc_rpl: Remove Chrome OS and EC as they are not used
* e020979993 mb/siemens/mc_rpl: Adjust the flash map file
* 71fb8f63e0 mb/siemens/mc_rpl: Add new mainboard based on Intel's Alder Lake RVP
* 918f21b72d drivers/spi/winbond.c: Add W25Q64JV signature
* 278a6d2682 mb/google/trulo/var/pujjocento: update hda_verb table for ALC257
* 43f7c537f8 mb/google/trulo/var/pujjocento: update GPP_R4/GPP_R5 setting
* e4fc00adbe soc/amd/common/block: Enable MMCONF first
* cbbf380fa4 soc/amd/common/block/lpc: Use ROM3 window if possible
* 9d878fc6c0 soc/intel/xeon_sp: Add support for Emerald Rapids (5th Gen Xeon-SP) CPUs
* bd66b8cdd2 mb/google/nissa/var/rull: Enable VBOOT_EC_SYNC_ESOL for rull device
* 3155b2f64c mb/dell/haswell_latitude: Correct BOARD_ROMSIZE_KB_* for E7240
* 4d30d06637 mainboard/google/ocelot: Configure middle logo vertical alignment
* 583bf972c5 mb/google/ocelot: Remove NPK device
* 2bec5a9d9a soc/mediatek/mt8189: Check eFuse ECC in WDT init
* a89406790a mb/google/nissa/var/meliks: Set vccin_aux_imon_iccmax to 25A
* ccd4d1d1db mb/var/uldrenite: Make two pins NC to reduce S0ix power consumption
* e2baa9c7ed mb/google/bluey: Create Quenbi variant
* a98511fd23 mb/google/bluey: Only select EC_GOOGLE_CHROMEEC_SWITCHES with VBOOT
* 756d02f779 mb/google/fatcat: Remove extraneous space in Felino Kconfig name
* 8de02842d5 soc/intel/common/block/cpu: Execute post_cpus_init at BS_DEV_ENABLE
* 0baf47e03b vc/intel/fsp/ptl: Update header files from FSP 3071_00 to FSP 3144_01
* 61f043de4a mb/google/skywalker: Initialize DPM in ramstage
* 3f8702a0d6 soc/mediatek/mt8189: Add DPM v2 driver configuration
* d5bfa1c697 soc/mediatek/common: Add DPM V2 non-broadcast mode support
* 24ab31f477 mb/google/skywalker: Enable RTC boot init
* b288aaee85 soc/mediatek/mt8189: Use common RTC driver MT6359
* 12d6d0606c mb/google/skywalker: Initialize PMIC in romstage
* 2a3fd0659d soc/mediatek/mt8189: Add PMIC MT6315 driver
* 42ac3ccff4 soc/mediatek/mt8189: Add PMIC MT6359 driver
* a2010cf5ee mb/novacustom/mtl-h/Makefile.mk: include tas5825m.c in the build
* 2033075753 intel/alderlake/romstage: Implement eSOL during EC software sync
* e6a7666bcd cpu/intel/car: Skip EC software sync in common code
* ac4503d0dd security/vboot: Introduce VBOOT_EC_SYNC_ESOL Kconfig option
* 8a4b3e1346 cpu/intel/microcode: Add error handling if microcode directory is empty
* cb77cafbb4 soc/mediatek/mt8189: Add SPMI and PWRAP driver
* b9a4d6ede1 soc/mediatek/common: Correct MT6359 RTC EOSC setting
* ae2f3ab153 mb/system76: Add SMBIOS slot descriptions
* c0113106fa nb/amd/pi/00730F01/northbridge: skip IVRS when IOMMU is disabled
* 5e2aee4474 soc/mediatek/mt8196: Move sspm_enable_sram() to common code
* c81b08c4ba util/abuild: Fix building ChromeOS boards
* 62b823f69e mb/google/bluey: Increase flash size to 64MB for W25Q512NWEIM
* 276eb20b04 mb/google/bluey: Limit SPI flash support to Winbond
* 47c171a157 mb/google/bluey: Make Chrome EC optional
* 139a5b6fe0 mb/google/bluey: Select MISSING_BOARD_RESET due to lack of Chrome EC
* f9d933db36 mb/google/bluey: Introduce MAINBOARD_HAS_GOOGLE_TPM Kconfig
* e8450f78a0 mb/google/bluey: Make GPIO setups conditional on Kconfig options
* 4e8ea210bb mb/google/fatcat/var/felino: Add pull high setting on GPP_C03/GPP_C04 in gpio.c
* 65523e98a6 soc/mediatek: Extract DPM common code
* aaf373c253 mb/google/skywalker: Implement sku_id()
* be675e5369 mb/google/skywalker: Configure GPIO XHCI_INIT_DONE as output
* 9a60da5297 mb/google/skywalker: Enable ChromeOS EC
* c443478509 mb/trulo/var/pujjolo: Create pujjolo variant
* 24757047e5 util/abuild: Fix merge error
* d93f7f01a6 mb/topton/adl: Use CFR setup menu to manage options
* b59fef9678 soc/intel/cmn/cse: Add Kconfig to set ME default CFR option state
* 50a5fe77de soc/intel/meteorlake: Add CFR objects for existing options
* d53f00fbd9 soc/intel/meteorlake: Hook up the VT-d setting to option API
* e356483eb6 soc/intel/jasperlake: Add CFR objects for existing options
* 87663d1c0a soc/intel/jasperlake: Hook up the VT-d setting to option API
* 2c0c2f46d7 soc/intel/tigerlake: Add CFR objects for existing options
* d06c8dde58 soc/intel/tigerlake: Hook up the VT-d setting to option API
* 3cfb24a326 soc/intel/alderlake: Hook up the VT-d setting to option API
* 6f9df7ace4 soc/intel/cannonlake: Add/use enums for IGD config
* c8199f26e0 soc/intel/skylake: Add/use enums for IGD config
* 947dd07823 soc/intel/jasperlake: Hook up IGD config to option API
* 09adda95b9 soc/intel/meteorlake: Hook up IGD config to option API
* dcbb5771c9 soc/intel/tigerlake: Hook up IGD config to option API
* d930a3542c soc/intel/alderlake: Hook up IGD config to option API
* 9faf7ce4f4 soc/intel/alderlake: Add CFR objects for existing options
* 011baca89d cpu/x86/smm/smm_module_loader: Install bigger page tables
* aa121a9bbe payloads/external/edk2/Makefile: Set OemId Pcd
* ca9616b984 ec/system76/ec: Add config for 2nd fan without GPU
* f1f58b20b9 soc/mediatek/mt8189: Add SPI driver support
* d4a759a068 mb/system76/mtl: darp10: Add TCSS configs
* 85972101e6 commonlib/device_tree: Make *path const in dt_find_node()
* de9d76c761 mb/starlabs/starbook/tgl: Configure the eSPI GPIOs
* af7fb83ed0 soc/intel/apollolake: Hook up S0ix setting to option API
* 9979be7482 drivers/intel/fsp2_0: Remove redundant NULL checks and simplify code
* 6f9de346ae Revert "soc/amd/glinda/Makefile.mk: Use relative address for APOB_NV"
* d263e0bd92 soc/amd/glinda/Makefile.mk: Use relative address for APOB_NV
* 4f7ea3667c mb/google/rex/var/kanix: Tune camera I2C timing
* f0ad05b57e mb/google/brya/var/uldrenite: Fix USB_OC1 for USB3 A0 port
* 1140891211 mb/google/bluey: Initialize I2C, SPI, and GPIOs in bootblock
* ba8407f0c1 soc/intel: Add Arrow Lake-H/U IDs
* 3e1f96a0f4 mb/system76/mtl: Add Lemur Pro 13
* 3008b8de53 soc/intel/skylake: Show that SMRAM is unconditionally locked
* e6dc71fe9f util/superiotool: Dump one more NCT6779D register
* b50ceba64a mb/amd: Increase ROM size on boards, incorrectly limited to 16 MB
* 850703b32b mb/google/bluey: Configure FPMCU power, reset, and QUPv3 peripherals
* b4c6984a40 soc/qualcomm/x1p42100: Initialize QSPI and QUPv3 in bootblock
* fe34206442 soc/mediatek/mt8189: Add audio/display bus protection release functions
* c2b17a083d soc/mediatek/mt8189: Add PLL and clock init support
* e4cbd9ea9f soc/mediatek/mt8189: Add MTCMOS init support
* 5cf460dce9 soc/mediatek/mt8196: Fix RTC protection register unlock failure
* 2c986d016e MAINTAINERS: Add Google Bluey and Qualcomm SOC maintainers
* 64fe6fd94a util/abuild: fix TODO and update targets variable to an array
* 902288db22 util/abuild: Update version and date string
* 8504c796fc util/abuild: Remove obsolete FIXME
* a8e1113e3b util/abuild: Check functions directly instead of with $?
* b128abcdad util/abuild: Add quotes around variables
* 52b932df3b util/abuild: Group printfs to timestamps file together
* ad19c94d87 util/abuild: Fix shellcheck warnings about local vars
* d88ea14e8d util/abuild: Remove unused debug() function
* 82dea9d6d1 util/abuild: Disable shellcheck warning on interrupt()
* a2baaec067 util/abuild: Use ${} around variable names
* 9ddb54e6ad util/abuild: Update syntax from 'function func' to 'func()'
* f66c7c1037 util/abuild: Update echo to printf for consistency.
* 49ae935b37 util/abuild: Change [...] to [[...]] for consistency
* ea32e30a18 mb/starlabs/*/cfr: Remove `reboot_counter` CFR option
* d4cb553986 mb/starlabs/*/cfr: Remove `boot_option` CFR option
* 452e179727 mb/starlabs/*/cfr: Use global console CFR object
* aebef78622 xcompile: Use Walloc-size GCC option
* 074dd4f6f5 mb/google/fatcat: Set logo vertical alignment to middle for variants
* 02ca72b2d4 soc/intel/meteorlake: Hook up Pch Sleep Assertion widths
* 166f0ea146 util/abuild: Identify abuild builds with an env variable
* 511872dae3 mb/dell: Convert Latitude E7240 into a variant
* b5581d556b drivers/mrc_cache: Measure MRC cache as runtime data
* 05eb3e3716 mb/google/skywalker: Create variant Yoda
* c8ddae9ebe mb/google/puff: Use CFR setup menu to manage options
* dc19824e56 mb/google/fizz: Use CFR setup menu to manage options
* 1d62a1e857 mb/google/jecht: Clean up makefile
* 4112c77919 mb/google/jecht: Use CFR setup menu to manage options
* 6eddde31bb mb/google/beltino: Clean up makefile
* 445575525c mb/google/beltino: Use CFR setup menu to manage options
* 376a5acc24 util/lint: Add lint file for gofmt
* 4456c125f6 soc/mediatek/common: Move PMIF SPI macros to per-SoC's header
* 8efdbf0c34 mb/google/nissa/var/meliks: Use default domain_vr_config[] settings
* f07a1a76f3 mb/google/brya: Enable GNA scoring accelerator
* 6c830088da mb/google/rex/var/screebo: Generate RAM IDs
* ac2bd75817 spd/lp5: Add SPD for K3KL9L90EM-MGCU
* 66873a3812 vc/amd/fsp/glinda: Update SMBIOS Type 17 information
* b23db384a9 vc/amd/fsp: Update SMBIOS Type 17 PartNumber size
* 0b120de7c0 Documentation: Update documentation for Topton X2F-N100
* d50019d432 mb/starlabs/starbook_mtl: Select SKIP_SEND_CONNECT_TOPOLOGY_CMD
* 4aa1861fbb mb/starlabs/starbook/mtl: Configure sleep assertion times
* 183c414577 soc/intel/meteorlake: Add Kconfig to skip FSP TBT connect topology
* aa1eba2f25 drivers/intel/fsp2_0: Enable firmware splash using 24-bit BMP logo
* da29107572 mb/google/fatcat/var/francka: Reduce generic reset delay to 10ms
* 60916d0f10 mb/trulo/var/uldrenite: Support different ISH UART mappings
* 3fe4b00966 mb/trulo/var/uldrenite: Swap ISH UART from UART1 to UART0
* 407c7d0da3 Documentation: Add Device Operations
* 20d7eaeb0f Documentation: Add chip operations
* bf38f8eddc vc/intel/fsp2: Drop superfluous header for Raptor Lake S
* eec228987e mb/intel/coffelake_rvp: Make use of chipset devicetree
* c9f4cfa463 AUTHORS: Update list to 25.03
* da5101fde4 cpu/x86/smm: Drop unused label
* 9154070320 mb/asus/h61-series: Add H61M-A/USB3
* e8c724fe1a mb/lenovo/m900_tiny: Update VBT to build 1037 with Kaby Lake gfx support
* 21ca6701ff mb/google/{drallion,hatch,sarien}: Skip adding DTT/TCPU to SSDT
* 5bf88a44e9 drivers/smmstore: Support 64-bit MMIO addresses
* 2706ce0266 mb/intel/ptlrvp: Add GPIO support for T4 LP5 board
* 40b62ff6c4 mb/intel/ptlrvp: Add memory configuration support for T4 LP5 board
* 7f826fddc5 mb/intel/ptlrvp: Compile variant.c in ramstage for ptlrvp
* 0ca46ac0d2 soc/intel/pantherlake: Enable coreboot native logo rendering
* 210371e25b mainboard/google/fatcat: Configure middle logo vertical alignment
* e446c1f917 drivers/intel/fsp2_0: Introduce coreboot native logo rendering
* 2f23896299 soc/intel/intelblocks/cfg: Add splash screen vertical alignment options
* 78d15d9a12 drivers/intel/fsp2_0: Add Kconfig to select FSP for BMP rendering
* 5f941893ef cpu/x86/mtrr: Introduce mtrrlib with common MTRR helper functions
* e180971560 drivers/intel/fsp2_0: Move graphics info struct/GUID to FSP header
* 18b4349422 mb/var/uldrenite: Fix fw_config_gpio_padbased_override not being called
* a6be271e63 arch/x86: Unify GDT entries
* 1e7e4e943f soc/intel/tigerlake: Hook up S0ix setting to option API
* ba4b26c4fc soc/intel/meteorlake: Hook up S0ix setting to option API
* 514ad949e3 soc/intel/jasperlake: Hook up S0ix setting to option API
* 55afbe250d soc/intel/elkhartlake: Hook up S0ix setting to option API
* 3cc728110d soc/intel/alderlake: Hook up S0ix setting to option API
* 245cba6795 cpu/x86/smm: Add support for exception handling
* 2e27ceed67 mb/google/volteer/var/elemi: Check FP presence against SKU ID
* 663dbd462a soc/amd/phoenix: Remove outdated TODO comments
* b1b8b0e8e1 mb/starlabs/starbook/tgl: Reconfigure PCH Strap GPIOs
* 36ac6226ff util/autoport: Add function to create empty files
* f8071719e7 soc/intel/ptl: Add Wildcat Lake platform reporting
* db4162adce soc/intel/ptl: Add Wildcat Lake PCIe Device details
* 1baf0baf58 soc/intel/ptl: Add Wildcat Lake SoC device tree
* 2fc246cd2d mb/google/ocelot: Remove unused devices from devicetree
* 3278551f8c drivers/intel/fsp2_0: Include coreboot_tables.h in fsp_gop_blt.h
* 18172b6009 mb/google/bluey: Add SoundWire amp and SD card GPIOs to lb_gpios
* 80901a4494 mb/google/bluey: Add GPIOs for Soundwire, Display, and SD Card
* 1015d4332f mainboard/google/bluey: Add fingerprint sensor GPIO entries
* a85b9a21b2 mb/intel/ptlrvp: Add support for DDR5 configuration
* c1bcb43f7c cbgfx: Prevent divide-by-zero edge case in Lanczos kernel
* 565c768c20 soc/intel/alderlake: only add wifi Mitigation if DRIVERS_WIFI_GENERIC
* ac948173ad mb/starlabs/starfighter/rpl: Add ramstage.c to makefile
* f1509a467c mb/starlabs/starfighter: Add CFR option to use native panel resolution
* 3593314cf5 mb/starlabs/starlite_adl: Add CFR option to use native panel resolution
* d13afbbbca mb/starlabs/starbook: Add CFR option to use native panel resolution
* 8fa84d9111 mb/starlabs/*: Add CFR entry for Bluetooth RTD3
* d2b0220a38 allocator_v4: Re-enable top-down allocation for edk2
* 4d7b56cdaa soc/intel/cmn/cse_lite: Fix handling of soft disable state
* 33b3269d91 soc/intel/cmn/cse: Add function to check if ME state is M3_NO_UMA
* 30a4fec86e mb/google/fatcat/var/kinmen: Generate SPD ID for Micron modules
* cf5696834b soc/intel/ptl: Refactor Panther Lake SoC configuration
* e99532d99b soc/mediatek/common: Update SPMI calibration process
* f83fb11e5f soc/mediatek/mt8189: Add CPU segment ID support
* 7b27b1ca99 soc/mediatek/mt8189: Fix incorrect GPIO register address
* f2cf732997 libpayload: usbmsc: Correctly deal with disks larger than 2TB
* 173c5d0aad src/arch/x86/c_start: Delete duplicated code masking stack pointer
* 1166f9be0d include/console: Add CFR object for setting the logging level
* 0f0d5fc725 soc/intel/apollolake/acpi: Add function to get PCIe BAR
* 5d3664ce3b mb/starlabs/starbook/adl_n: Update VBT to fix HDMI output
* 4b765fdd98 mb/google/fatcat: Disable EnableFastVmode on Panther Lake H SoC
* f63c3bb297 soc/intel/cannonlake: Hook up DPTF device to devicetree
* b7d59185ab soc/intel/common/dtt: Add Kconfig to skip SSDT generation
* 094f75162f cpu/x86/64bit/pt: Fix integer arithmethic in assembly
* bbd8f0aef8 soc/intel/ptl: Refactoring NUM_COMx_GRP_PADS calculation
* cf47edb173 ec/google/wilco/acpi: Add UCSI port data
* 89e915e981 ec/google/wilco/acpi: Fix S3/S4 support
* 4a89d1b77d soc/intel/ptl: Add GPIO ACPI support for Wildcat Lake SoC
* a4a2cdeb17 soc/intel/ptl: Add GPIOs for Wildcat Lake SoC
* 2ce567f1d0 soc/intel/common/block/cse: Prevent HECI commands when flash descriptor override is set
* 9660279966 drivers/usb/intel_bluetooth: Hook RTD3 up to the option API
* e2705d93d8 soc/intel/pantherlake: Reduce IGD stolen memory size from 128MB to 64MB
* 9f98a2a78a mb/asus/p8z77-v_le_plus: Use additional rt8168 MAC programming
* 2b598a9472 drivers/net/r8168.c: Add option to program MAC address to ERI registers
* 4b871c6314 ec/intel: read board ID one time from EC per stage
* 08722cd9f9 mb/google/dedede/var/beadrix: Add Ziliatech part to RAM ID table
* c0920396d0 mb/google/bluey: Make GSC_AP_INT GPIO configurable via Kconfig
* 2e387e13f5 mb/google/fatcat/var/francka: Conditionally init HDA
* e545494f6d mb/google/fatcat/var/fatcat: Conditionally init ALC256 HDA
* 03d2ef67d7 soc/intel/cmn/hda: Introduce mainboard hook for HDA initialization
* 85c65b0c20 mb/google/fatcat: Remove NPK device from fatcat and francka variants
* 92955fbfa6 mb/google/trulo/var/uldrenite: Configure GPP_E9 as NF2
* aafcb01ec4 mb/intel/ptlrvp: Synchronize codebase with fatcat
* effd1ffdad mb/google/ocelot: Update Ocelot board
* 1044f03878 payloads/external/edk2: Set StatusD register to work around failing AMD boot
* 2170ad0c60 Documentation/lib/timestamp.md: Reformat to 72 characters per line
* 22118a137b mb/google/fatcat/var/kinmen: Add memory settings
* 54c87dbed0 mb/google/trulo/var/uldrenite: Update DPTF parameters
* 9ef62ad64c mb/intel/ptlrvp: Introduce PTL RVP External and Internal EC Configurations
* 7c965f9df0 MAINTAINERS: Add Nick, Avi, and Pranava for new google/ocelot entry
* d2e698056e mb/google/bluey: Set correct Kconfig defaults for peripherals
* 34d6bc8784 soc/qualcomm/x1p42100: Set correct Kconfig defaults for peripherals
* 2201f57493 soc/qualcomm/x1p42100: Add QUP Serial Engine (SE) entries
* 6a503fe5a4 mb/google/var/uldrenite: Configure GPP_A16 as NF4
* c2c95fbd24 sb/intel/lynxpoint: Add CFR objects for existing options
* 96fd20c5e0 soc/intel/broadwell: Add CFR objects for existing options
* ce6f7820f4 ec/google/chromeec: Increase EC status timeout to 30 seconds
* 17347eedc3 soc/intel/cannonlake: Add CFR objects for existing options
* ad704e0500 soc/intel/cannonlake: Hook up the VT-d setting to option API
* 7f8d1f2086 mb/google/nissa/var/pujjoniru: Support x32 memory configuration
* fe881c990c mb/google/brya: Create pujjocento variant
* 7da36ad79a mb/google/bluey: Add initial support for Bluey
* 57d7957e3c soc/qualcomm/x1p42100: Add initial SoC skeleton for X1P-42-100
* c82f5fe133 soc/amd/glinda: Select SOC_FILL_CPU_CACHE_INFO
* ee76692571 payload/external/edk2: Add Kconfig to support use of PCIe OpROMs
* fb3f025ea6 soc/amd/common/cpu/noncar: Add SMBIOS helper
* 36f01c3481 mb/google/fatcat/var/felino: Add Write Protect GPIO to cros_gpios
* 934fcfb6a0 soc/mediatek/mt8189: Add I2C driver support
* b3bdffa475 soc/mediatek/common: Move I2C functions to common code
* 1e0941c295 mb/google/ocelot: Select Wildcat Lake(WCL) SoC config
* b249275e3d mb/amd/crater: Fix some ec defines
* 443f514365 mb/amd/crater: Add touchscreen support
* 4e55225f2c mb/amd/crater: Add missing dxio descriptors
* 608db150f1 smmrelocate: Drop unused parameter
* 157b7ae778 payloads/edk2: Update default branch for MrChromebox repo to 2025-02
* 76a1e81b10 mb/starlabs/*: Unify Sleep S3 and S4 GPIO configurations
* fed584e100 soc/intel: Add Wildcat Lake CPU and PCIe device IDs
* 5d7e2b4c0c mb/google/fatcat: Disable VR settings on Panther Lake H SoC
* 8be95806a6 mb/google/ocelot/var/ocelot: update gpios
* 92f9c8a985 mb/google/ocelot: update FW_CONFIG
* 49bf8f94a0 soc/intel/common: Add CFR objects for existing options
* 509b01c3b6 soc/intel/cannonlake: Hook up S0ix setting to option API
* b830fdc2d7 soc/intel/cannonlake: Hook up IGD config to option API
* 5efb54d371 soc/intel/broadwell: Allow ME enable/disable to be set via option
* 42379e7f76 sb/intel/lynxpoint: Allow ME enable/disable via option
* 204aae207d mb/samsung/stumpy: Clean up makefile
* e3d3fc5b4a mb/samsung/stumpy: Use CFR setup menu to manage options
* 936ca8404a drivers/option/cfr: Select EFI variable store when edk2 payload used
* 20ceed1929 drivers/efi/fw_info: Select necessary UDK binding as needed
* c0e3f6d1d2 drivers/efi/variable_store: Select necessary UDK binding as needed
* a899359720 sb/intel/bd82x6x: Add CFR objects for existing options
* ada6b98766 nb/intel/sandybridge: Add CFR objects for existing options
* f14aa06606 soc/intel/skylake: Add CFR objects for existing options
* f51c0bb090 soc/intel/skylake: Hook up IGD config to option API
* 32c78b7e22 soc/intel/skylake: Hook up S0ix setting to option API
* 73b095d5ea mb/starlabs/*: Select DRIVERS_OPTION_CFR_ENABLED
* 4eba4e3f26 superio/ite/it8772f: Program power state after failure
* fbca3e6806 superio/ite/*: Move setting of power state to common code
* 60b414fc13 soc/intel/cannonlake: Drop redundant PcieRpEnable
* ee30558c49 soc/intel/skylake: Drop redundant PcieRpEnable
* 439d7fb7d0 mb/google/brya: Create epic variant
* c4e6050146 mb/google/skywalker: Create variant Obiwan
* 0cc0e6996c drivers/smmstore: allow full flash access for capsule updates
* 7814b8a6be Revert "soc/mediatek/mt8196: Specify MTKLIB_PATH for building BL31"
* 14b66cb01b soc/intel/pantherlake: Add new SoC config for Intel Wildcat Lake(WCL)
* d14ebe3957 mb/google/fatcat/var/felino: Use GPP_C08 for GPIO_PCH_WP
* 6322be7992 sb/intel/bd82x6x/me.h: Add missing definitions
* 2f62dd8a6b mb/google/brya/var/uldrenite: Configure ISH_GP5 GPIO
* 3ce612194c mb/google/rex: Generate RAM IDs
* 430ab9257b spd/lp5: Add SPD for K3KL8L80EM-MGCU
* c7a450ba7d Documentation/mainboard/asrock/imb-1222.md: Update information
* ac7717a7b0 mainboard/asrock/imb-1222: Enable USB3 port in WWAN slot
* eb68ff66eb mb/asrock/imb-1222: Update GPIO config using new intelp2m
* a1210875e9 mb/imb-1222: Update some GPIOs according to new vendor config
* fc8e88da9b drivers/intel/mipi_camera: Rework info print output
* d04d7d80b0 drivers/intel/mipi_camera: Only generate ADR if no HID supplied
* 36c89598a7 mb/erying/tgl: fsp_params: Replace half_populated with statement
* 0307f52cd9 soc/mediatek/mt8196: Move SPM loader functions to common part

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-07-06 19:18:50 +01:00

2233 lines
79 KiB
Diff
Raw Blame History

From a2f4492e8680d96f328846e3eba85d5aebec8d09 Mon Sep 17 00:00:00 2001
From: Mate Kukri <km@mkukri.xyz>
Date: Tue, 31 Dec 2024 22:49:15 +0000
Subject: [PATCH 28/41] mb/lenovo: Add ThinkPad T480 and ThinkPad T480s
These machine have BootGuard fused and requires deguard to
boot coreboot.
Known issues:
- Alpine Ridge Thunderbolt 3 controller does not work
- Some Fn+F{1-12} keys aren't handled correctly
- Nvidia dGPU is finicky
- Needs option ROM
- Power enable code is buggy
- Nouveau only works on linux 6.8-6.9
- Headphone jack isn't detected as plugged in despite correct verbs
Thanks to Leah Rowe for helping with the T480s.
Signed-off-by: Mate Kukri <km@mkukri.xyz>
Change-Id: I19d421412c771c1f242f6ff39453f824fa866163
---
src/device/pci_rom.c | 4 +-
src/ec/lenovo/h8/acpi/ec.asl | 2 +-
src/ec/lenovo/h8/bluetooth.c | 6 +-
src/ec/lenovo/h8/wwan.c | 6 +-
src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 57 +++++
.../lenovo/sklkbl_thinkpad/Kconfig.name | 7 +
.../lenovo/sklkbl_thinkpad/Makefile.mk | 73 +++++++
.../lenovo/sklkbl_thinkpad/acpi/ec.asl | 12 ++
.../lenovo/sklkbl_thinkpad/acpi/superio.asl | 3 +
.../lenovo/sklkbl_thinkpad/bootblock.c | 60 ++++++
.../lenovo/sklkbl_thinkpad/devicetree.cb | 71 ++++++
src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl | 33 +++
src/mainboard/lenovo/sklkbl_thinkpad/ec.c | 153 +++++++++++++
src/mainboard/lenovo/sklkbl_thinkpad/ec.h | 99 +++++++++
src/mainboard/lenovo/sklkbl_thinkpad/gpio.h | 8 +
.../lenovo/sklkbl_thinkpad/ramstage.c | 105 +++++++++
.../sklkbl_thinkpad/variants/t480/data.vbt | Bin 0 -> 4106 bytes
.../variants/t480/gma-mainboard.ads | 19 ++
.../sklkbl_thinkpad/variants/t480/gpio.c | 203 ++++++++++++++++++
.../sklkbl_thinkpad/variants/t480/hda_verb.c | 90 ++++++++
.../variants/t480/memory_init_params.c | 20 ++
.../variants/t480/overridetree.cb | 103 +++++++++
.../sklkbl_thinkpad/variants/t480s/data.vbt | Bin 0 -> 4106 bytes
.../variants/t480s/gma-mainboard.ads | 19 ++
.../sklkbl_thinkpad/variants/t480s/gpio.c | 199 +++++++++++++++++
.../sklkbl_thinkpad/variants/t480s/hda_verb.c | 90 ++++++++
.../variants/t480s/memory_init_params.c | 44 ++++
.../variants/t480s/overridetree.cb | 103 +++++++++
.../variants/t480s/spd/spd_0.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_1.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_10.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_11.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_12.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_13.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_14.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_15.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_16.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_17.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_18.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_19.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_2.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_20.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_3.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_4.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_5.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_6.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_7.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_8.bin | Bin 0 -> 512 bytes
.../variants/t480s/spd/spd_9.bin | Bin 0 -> 512 bytes
49 files changed, 1583 insertions(+), 6 deletions(-)
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ec.h
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_12.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_13.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_20.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_9.bin
diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
index dc41ef14ce..bba98d9dea 100644
--- a/src/device/pci_rom.c
+++ b/src/device/pci_rom.c
@@ -396,14 +396,16 @@ void pci_rom_ssdt(const struct device *device)
rom = cbrom;
}
+#if 0
const char *scope = acpi_device_path(device);
if (!scope) {
printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device));
return;
}
+#endif
/* write _ROM method */
- acpigen_write_scope(scope);
+ acpigen_write_scope("\\_SB.PCI0.RP01.PEGP");
acpigen_write_rom((void *)rom, rom->size * 512);
acpigen_pop_len(); /* pop scope */
}
diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
index bc54d3b422..8f4a8e1986 100644
--- a/src/ec/lenovo/h8/acpi/ec.asl
+++ b/src/ec/lenovo/h8/acpi/ec.asl
@@ -331,7 +331,7 @@ Device(EC)
#include "sleepbutton.asl"
#include "lid.asl"
#include "beep.asl"
-#include "thermal.asl"
+//#include "thermal.asl"
#include "systemstatus.asl"
#include "thinkpad.asl"
}
diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c
index 16fc8dce39..be71a24ced 100644
--- a/src/ec/lenovo/h8/bluetooth.c
+++ b/src/ec/lenovo/h8/bluetooth.c
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <southbridge/intel/common/gpio.h>
+// #include <southbridge/intel/common/gpio.h>
#include <console/console.h>
#include <device/device.h>
#include <ec/acpi/ec.h>
@@ -28,16 +28,18 @@ bool h8_has_bdc(const struct device *dev)
{
struct ec_lenovo_h8_config *conf = dev->chip_info;
- if (!conf->has_bdc_detection) {
+ if (1 || !conf->has_bdc_detection) {
printk(BIOS_INFO, "H8: BDC detection not implemented. "
"Assuming BDC installed\n");
return true;
}
+#if 0
if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
printk(BIOS_INFO, "H8: BDC installed\n");
return true;
}
+#endif
printk(BIOS_INFO, "H8: BDC not installed\n");
return false;
diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c
index 685886fcce..5cdcf77406 100644
--- a/src/ec/lenovo/h8/wwan.c
+++ b/src/ec/lenovo/h8/wwan.c
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
-#include <southbridge/intel/common/gpio.h>
+// #include <southbridge/intel/common/gpio.h>
#include <console/console.h>
#include <device/device.h>
#include <ec/acpi/ec.h>
@@ -26,16 +26,18 @@ bool h8_has_wwan(const struct device *dev)
{
struct ec_lenovo_h8_config *conf = dev->chip_info;
- if (!conf->has_wwan_detection) {
+ if (1 || !conf->has_wwan_detection) {
printk(BIOS_INFO, "H8: WWAN detection not implemented. "
"Assuming WWAN installed\n");
return true;
}
+#if 0
if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
printk(BIOS_INFO, "H8: WWAN installed\n");
return true;
}
+#endif
printk(BIOS_INFO, "H8: WWAN not installed\n");
return false;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
new file mode 100644
index 0000000000..4998672943
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+ bool
+ select BOARD_ROMSIZE_KB_16384
+ select EC_LENOVO_H8
+ select EC_LENOVO_PMH7
+ select H8_HAS_BAT_THRESHOLDS_IMPL
+ select H8_HAS_LEDLOGO
+ select H8_HAS_PRIMARY_FN_KEYS
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_GMA_HAVE_VBT
+ select INTEL_INT15
+ select MAINBOARD_HAS_LIBGFXINIT
+ select MAINBOARD_HAS_TPM2
+ select MAINBOARD_USES_IFD_GBE_REGION
+ select MEMORY_MAPPED_TPM
+ select SOC_INTEL_COMMON_BLOCK_HDA_VERB
+ select SOC_INTEL_KABYLAKE
+ select SPD_READ_BY_WORD
+ select SYSTEM_TYPE_LAPTOP
+
+config BOARD_LENOVO_T480
+ bool
+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+
+config BOARD_LENOVO_T480S
+ bool
+ select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+
+if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
+
+config MAINBOARD_DIR
+ default "lenovo/sklkbl_thinkpad"
+
+config VARIANT_DIR
+ default "t480" if BOARD_LENOVO_T480
+ default "t480s" if BOARD_LENOVO_T480S
+
+config OVERRIDE_DEVICETREE
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+config MAINBOARD_PART_NUMBER
+ default "T480" if BOARD_LENOVO_T480
+ default "T480s" if BOARD_LENOVO_T480S
+
+config CBFS_SIZE
+ default 0x900000
+
+config DIMM_MAX
+ default 2
+
+config DIMM_SPD_SIZE
+ default 512 # DDR4
+
+endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
new file mode 100644
index 0000000000..abc273f387
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config BOARD_LENOVO_T480
+ bool "ThinkPad T480"
+
+config BOARD_LENOVO_T480S
+ bool "ThinkPad T480s"
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
new file mode 100644
index 0000000000..c308239177
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk
@@ -0,0 +1,73 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c ec.c
+
+romstage-y += variants/$(VARIANT_DIR)/memory_init_params.c
+
+ramstage-y += ramstage.c ec.c
+ramstage-y += variants/$(VARIANT_DIR)/gpio.c variants/$(VARIANT_DIR)/hda_verb.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
+
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_0.bin
+spd_0.bin-file := variants/$(VARIANT_DIR)/spd/spd_0.bin
+spd_0.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_1.bin
+spd_1.bin-file := variants/$(VARIANT_DIR)/spd/spd_1.bin
+spd_1.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_2.bin
+spd_2.bin-file := variants/$(VARIANT_DIR)/spd/spd_2.bin
+spd_2.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_3.bin
+spd_3.bin-file := variants/$(VARIANT_DIR)/spd/spd_3.bin
+spd_3.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_4.bin
+spd_4.bin-file := variants/$(VARIANT_DIR)/spd/spd_4.bin
+spd_4.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_5.bin
+spd_5.bin-file := variants/$(VARIANT_DIR)/spd/spd_5.bin
+spd_5.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_6.bin
+spd_6.bin-file := variants/$(VARIANT_DIR)/spd/spd_6.bin
+spd_6.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_7.bin
+spd_7.bin-file := variants/$(VARIANT_DIR)/spd/spd_7.bin
+spd_7.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_8.bin
+spd_8.bin-file := variants/$(VARIANT_DIR)/spd/spd_8.bin
+spd_8.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_9.bin
+spd_9.bin-file := variants/$(VARIANT_DIR)/spd/spd_9.bin
+spd_9.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_10.bin
+spd_10.bin-file := variants/$(VARIANT_DIR)/spd/spd_10.bin
+spd_10.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_11.bin
+spd_11.bin-file := variants/$(VARIANT_DIR)/spd/spd_11.bin
+spd_11.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_12.bin
+spd_12.bin-file := variants/$(VARIANT_DIR)/spd/spd_12.bin
+spd_12.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_13.bin
+spd_13.bin-file := variants/$(VARIANT_DIR)/spd/spd_13.bin
+spd_13.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_14.bin
+spd_14.bin-file := variants/$(VARIANT_DIR)/spd/spd_14.bin
+spd_14.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_15.bin
+spd_15.bin-file := variants/$(VARIANT_DIR)/spd/spd_15.bin
+spd_15.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_16.bin
+spd_16.bin-file := variants/$(VARIANT_DIR)/spd/spd_16.bin
+spd_16.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_17.bin
+spd_17.bin-file := variants/$(VARIANT_DIR)/spd/spd_17.bin
+spd_17.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_18.bin
+spd_18.bin-file := variants/$(VARIANT_DIR)/spd/spd_18.bin
+spd_18.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_19.bin
+spd_19.bin-file := variants/$(VARIANT_DIR)/spd/spd_19.bin
+spd_19.bin-type := raw
+cbfs-files-$(CONFIG_BOARD_LENOVO_T480S) += spd_20.bin
+spd_20.bin-file := variants/$(VARIANT_DIR)/spd/spd_20.bin
+spd_20.bin-type := raw
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
new file mode 100644
index 0000000000..3a949a2fca
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/ec.asl
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
+#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
+#define THINKPAD_EC_GPE 22
+
+Name(\TCRT, 100)
+Name(\TPSV, 90)
+Name(\FLVL, 0)
+
+#include <ec/lenovo/h8/acpi/ec.asl>
+#include <ec/lenovo/h8/acpi/thinkpad_bat_thresholds_b0.asl>
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
new file mode 100644
index 0000000000..55b1db5b11
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
new file mode 100644
index 0000000000..fb660dbdfa
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/bootblock.c
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <bootblock_common.h>
+#include <device/pci.h>
+#include <soc/pci_devs.h>
+#include "ec.h"
+
+static void configure_uart(uint16_t port, uint16_t iobase, uint8_t irqno)
+{
+ microchip_pnp_enter_conf_state(port);
+
+ // Select LPC I/F LDN
+ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF);
+ // Write UART BAR
+ pnp_write_le32(port, LPCIF_BAR_UART, (uint32_t) iobase << 16 | 0x8707);
+ // Set SIRQ4 to UART
+ pnp_write(port, LPCIF_SIRQ(irqno), LDN_UART);
+
+ // Configure UART LDN
+ pnp_write(port, PNP_LDN_SELECT, LDN_UART);
+ pnp_write(port, UART_ACTIVATE, 0x01);
+ pnp_write(port, UART_CONFIG_SELECT, 0x00);
+
+ microchip_pnp_exit_conf_state(port);
+
+#ifdef CONFIG_BOARD_LENOVO_T480
+ // Supply debug unlock key
+ debug_write_key(DEBUG_RW_KEY_IDX, debug_rw_key);
+
+ // Use debug writes to set UART_TX and UART_RX GPIOs
+ debug_write_dword(0xf0c400 + 0x110, 0x00001000);
+ debug_write_dword(0xf0c400 + 0x114, 0x00001000);
+#endif
+}
+
+
+#define UART_PORT 0x3f8
+#define UART_IRQ 4
+
+void bootblock_mainboard_early_init(void)
+{
+ // Tell EC via BIOS Debug Port 1 that the world isn't on fire
+
+ // Let the EC know that BIOS code is running
+ outb(0x11, 0x86);
+ outb(0x6e, 0x86);
+
+ // Enable accesses to EC1 interface
+ ec0_write(0, ec0_read(0) | 0x20);
+
+ // Reset LEDs to power on state
+ // (Without this warm reboot leaves LEDs off)
+ ec0_write(0x0c, 0x80);
+ ec0_write(0x0c, 0x07);
+ ec0_write(0x0c, 0x8a);
+
+ // Setup debug UART
+ configure_uart(EC_CFG_PORT, UART_PORT, UART_IRQ);
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
new file mode 100644
index 0000000000..c07d4d53ca
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/devicetree.cb
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+ # IGD Displays
+ register "gfx" = "GMA_STATIC_DISPLAYS(0)"
+
+ register "panel_cfg" = "{
+ .up_delay_ms = 200,
+ .down_delay_ms = 50,
+ .cycle_delay_ms = 600,
+ .backlight_on_delay_ms = 1,
+ .backlight_off_delay_ms = 200,
+ .backlight_pwm_hz = 200,
+ }"
+
+ # Power
+ register "PmConfigSlpS3MinAssert" = "2" # 50ms
+ register "PmConfigSlpS4MinAssert" = "1" # 1s
+ register "PmConfigSlpSusMinAssert" = "3" # 500ms
+ register "PmConfigSlpAMinAssert" = "3" # 2s
+
+ device domain 0 on
+ device ref igpu on end
+ device ref sa_thermal on end
+ device ref thermal on end
+ device ref south_xhci on end
+ device ref lpc_espi on
+ register "serirq_mode" = "SERIRQ_CONTINUOUS"
+
+ register "gen1_dec" = "0x007c1601"
+ register "gen2_dec" = "0x000c15e1"
+
+ chip ec/lenovo/pmh7
+ register "backlight_enable" = "true"
+ register "dock_event_enable" = "true"
+ device pnp ff.1 on end # dummy
+ end
+
+ chip ec/lenovo/h8
+ register "beepmask0" = "0x00"
+ register "beepmask1" = "0x86"
+ register "config0" = "0xa6"
+ register "config1" = "0x0d"
+ register "config2" = "0xa8"
+ register "config3" = "0xc4"
+ register "has_keyboard_backlight" = "1"
+ register "event2_enable" = "0xff"
+ register "event3_enable" = "0xff"
+ register "event4_enable" = "0xd0"
+ register "event5_enable" = "0x3c"
+ register "event7_enable" = "0x01"
+ register "event8_enable" = "0x7b"
+ register "event9_enable" = "0xff"
+ register "eventc_enable" = "0xff"
+ register "eventd_enable" = "0xff"
+ register "evente_enable" = "0x9d"
+ device pnp ff.2 on # dummy
+ io 0x60 = 0x62
+ io 0x62 = 0x66
+ io 0x64 = 0x1600
+ io 0x66 = 0x1604
+ end
+ end
+
+ chip drivers/pc80/tpm
+ device pnp 0c31.0 on end
+ end
+ end
+ device ref hda on end
+ end
+end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
new file mode 100644
index 0000000000..aa4d4de2a6
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/dsdt.asl
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725
+)
+{
+ #include <acpi/dsdt_top.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Device (\_SB.PCI0)
+ {
+ #include <soc/intel/skylake/acpi/systemagent.asl>
+ #include <soc/intel/skylake/acpi/pch.asl>
+ #include <drivers/intel/gma/acpi/default_brightness_levels.asl>
+ }
+
+ Scope (\_SB.PCI0.RP01)
+ {
+ Device (PEGP)
+ {
+ Name (_ADR, Zero)
+ }
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.c b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c
new file mode 100644
index 0000000000..adb6a60324
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.c
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include "ec.h"
+
+#define MICROCHIP_CONFIGURATION_ENTRY_KEY 0x55
+#define MICROCHIP_CONFIGURATION_EXIT_KEY 0xaa
+
+void microchip_pnp_enter_conf_state(uint16_t port)
+{
+ outb(MICROCHIP_CONFIGURATION_ENTRY_KEY, port);
+}
+
+void microchip_pnp_exit_conf_state(uint16_t port)
+{
+ outb(MICROCHIP_CONFIGURATION_EXIT_KEY, port);
+}
+
+uint8_t pnp_read(uint16_t port, uint8_t index)
+{
+ outb(index, port);
+ return inb(port + 1);
+}
+
+uint32_t pnp_read_le32(uint16_t port, uint8_t index)
+{
+ return (uint32_t) pnp_read(port, index) |
+ (uint32_t) pnp_read(port, index + 1) << 8 |
+ (uint32_t) pnp_read(port, index + 2) << 16 |
+ (uint32_t) pnp_read(port, index + 3) << 24;
+}
+
+void pnp_write(uint16_t port, uint8_t index, uint8_t value)
+{
+ outb(index, port);
+ outb(value, port + 1);
+}
+
+void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value)
+{
+ pnp_write(port, index, value & 0xff);
+ pnp_write(port, index + 1, value >> 8 & 0xff);
+ pnp_write(port, index + 2, value >> 16 & 0xff);
+ pnp_write(port, index + 3, value >> 24 & 0xff);
+}
+
+static void ecN_clear_out_queue(uint16_t cmd_port, uint16_t data_port)
+{
+ while (inb(cmd_port) & EC_OBF)
+ inb(data_port);
+}
+
+static void ecN_wait_to_send(uint16_t cmd_port, uint16_t data_port)
+{
+ while (inb(cmd_port) & EC_IBF)
+ ;
+}
+
+static void ecN_wait_to_recv(uint16_t cmd_port, uint16_t data_port)
+{
+ while (!(inb(cmd_port) & EC_OBF))
+ ;
+}
+
+uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr)
+{
+ ecN_clear_out_queue(cmd_port, data_port);
+ ecN_wait_to_send(cmd_port, data_port);
+ outb(EC_READ, cmd_port);
+ ecN_wait_to_send(cmd_port, data_port);
+ outb(addr, data_port);
+ ecN_wait_to_recv(cmd_port, data_port);
+ return inb(data_port);
+}
+
+void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val)
+{
+ ecN_clear_out_queue(cmd_port, data_port);
+ ecN_wait_to_send(cmd_port, data_port);
+ outb(EC_WRITE, cmd_port);
+ ecN_wait_to_send(cmd_port, data_port);
+ outb(addr, data_port);
+ ecN_wait_to_send(cmd_port, data_port);
+ outb(val, data_port);
+}
+
+uint8_t eeprom_read(uint16_t addr)
+{
+ ecN_clear_out_queue(EC2_CMD, EC2_DATA);
+ ecN_wait_to_send(EC2_CMD, EC2_DATA);
+ outl(1, EC2_CMD);
+ ecN_wait_to_send(EC2_CMD, EC2_DATA);
+ outl(addr, EC2_DATA);
+ ecN_wait_to_recv(EC2_CMD, EC2_DATA);
+ return inl(EC2_DATA);
+}
+
+void eeprom_write(uint16_t addr, uint8_t val)
+{
+ ecN_clear_out_queue(EC2_CMD, EC2_DATA);
+ ecN_wait_to_send(EC2_CMD, EC2_DATA);
+ outl(2, EC2_CMD);
+ ecN_wait_to_send(EC2_CMD, EC2_DATA);
+ outl((uint32_t) addr | (uint32_t) val << 16, EC2_DATA);
+ ecN_wait_to_recv(EC2_CMD, EC2_DATA);
+ inl(EC2_DATA);
+}
+
+uint16_t debug_loaded_keys(void)
+{
+ return (uint16_t) ec0_read(0x87) << 8 | (uint16_t) ec0_read(0x86);
+}
+
+static void debug_cmd(uint8_t cmd)
+{
+ ec0_write(EC_DEBUG_CMD, cmd);
+ while (ec0_read(EC_DEBUG_CMD) & 0x80)
+ ;
+}
+
+void debug_read_key(uint8_t i, uint8_t *key)
+{
+ debug_cmd(0x80 | (i & 0xf));
+ for (int j = 0; j < 8; ++j)
+ key[j] = ec0_read(0x3e + j);
+}
+
+void debug_write_key(uint8_t i, const uint8_t *key)
+{
+ for (int j = 0; j < 8; ++j)
+ ec0_write(0x3e + j, key[j]);
+ debug_cmd(0xc0 | (i & 0xf));
+}
+
+uint32_t debug_read_dword(uint32_t addr)
+{
+ ecN_clear_out_queue(EC3_CMD, EC3_DATA);
+ ecN_wait_to_send(EC3_CMD, EC3_DATA);
+ outl(addr << 8 | 0xE2, EC3_DATA);
+ ecN_wait_to_recv(EC3_CMD, EC3_DATA);
+ return inl(EC3_DATA);
+}
+
+void debug_write_dword(uint32_t addr, uint32_t val)
+{
+ ecN_clear_out_queue(EC3_CMD, EC3_DATA);
+ ecN_wait_to_send(EC3_CMD, EC3_DATA);
+ outl(addr << 8 | 0xEA, EC3_DATA);
+ ecN_wait_to_send(EC3_CMD, EC3_DATA);
+ outl(val, EC3_DATA);
+}
+
+const uint8_t debug_rw_key[8] = { 0x7a, 0x41, 0xb1, 0x49, 0xfe, 0x21, 0x01, 0xcf };
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ec.h b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h
new file mode 100644
index 0000000000..d2963c8962
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ec.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef SKLKBL_THINKPAD_EC_H
+#define SKLKBL_THINKPAD_EC_H
+
+// EC configuration base address
+#define EC_CFG_PORT 0x4e
+
+// Chip global registers
+#define PNP_LDN_SELECT 0x07
+# define LDN_UART 0x07
+# define LDN_LPCIF 0x0c
+#define EC_DEVICE_ID 0x20
+#define EC_DEVICE_REV 0x21
+
+// LPC I/F registers
+#define LPCIF_SIRQ(i) (0x40 + (i))
+
+#define LPCIF_BAR_CFG 0x60
+#define LPCIF_BAR_MAILBOX 0x64
+#define LPCIF_BAR_8042 0x68
+#define LPCIF_BAR_ACPI_EC0 0x6c
+#define LPCIF_BAR_ACPI_EC1 0x70
+#define LPCIF_BAR_ACPI_EC2 0x74
+#define LPCIF_BAR_ACPI_EC3 0x78
+#define LPCIF_BAR_ACPI_PM0 0x7c
+#define LPCIF_BAR_UART 0x80
+#define LPCIF_BAR_FAST_KYBD 0x84
+#define LPCIF_BAR_EMBED_FLASH 0x88
+#define LPCIF_BAR_GP_SPI 0x8c
+#define LPCIF_BAR_EMI 0x90
+#define LPCIF_BAR_PMH7 0x94
+#define LPCIF_BAR_PORT80_DBG0 0x98
+#define LPCIF_BAR_PORT80_DBG1 0x9c
+#define LPCIF_BAR_RTC 0xa0
+
+// UART registers
+#define UART_ACTIVATE 0x30
+#define UART_CONFIG_SELECT 0xf0
+
+void microchip_pnp_enter_conf_state(uint16_t port);
+void microchip_pnp_exit_conf_state(uint16_t port);
+uint8_t pnp_read(uint16_t port, uint8_t index);
+uint32_t pnp_read_le32(uint16_t port, uint8_t index);
+void pnp_write(uint16_t port, uint8_t index, uint8_t value);
+void pnp_write_le32(uint16_t port, uint8_t index, uint32_t value);
+
+#define EC0_CMD 0x0066
+#define EC0_DATA 0x0062
+#define EC1_CMD 0x1604
+#define EC1_DATA 0x1600
+#define EC2_CMD 0x1634
+#define EC2_DATA 0x1630
+#define EC3_CMD 0x161c
+#define EC3_DATA 0x1618
+
+#define EC_OBF (1 << 0)
+#define EC_IBF (1 << 1)
+
+#define EC_READ 0x80
+#define EC_WRITE 0x81
+
+uint8_t ecN_read(uint16_t cmd_port, uint16_t data_port, uint8_t addr);
+
+void ecN_write(uint16_t cmd_port, uint16_t data_port, uint8_t addr, uint8_t val);
+
+// EC0 and EC1 mostly are useful with the READ/WRITE commands
+#define ec0_read(addr) ecN_read(EC0_CMD, EC0_DATA, addr)
+#define ec0_write(addr, val) ecN_write(EC0_CMD, EC0_DATA, addr, val)
+#define ec1_read(addr) ecN_read(EC1_CMD, EC1_DATA, addr)
+#define ec1_write(addr, val) ecN_write(EC1_CMD, EC1_DATA, addr, val)
+
+// Read from the emulated EEPROM
+uint8_t eeprom_read(uint16_t addr);
+
+// Write to the emulated EEPROM
+void eeprom_write(uint16_t addr, uint8_t val);
+
+// Read loaded debug key mask
+uint16_t debug_loaded_keys(void);
+
+// The following location (via either EC0 or EC1) can be used to interact with the debug interface
+#define EC_DEBUG_CMD 0x3d
+
+void debug_read_key(uint8_t i, uint8_t *key);
+
+void debug_write_key(uint8_t i, const uint8_t *key);
+
+uint32_t debug_read_dword(uint32_t addr);
+
+void debug_write_dword(uint32_t addr, uint32_t val);
+
+// RW unlock key index
+#define DEBUG_RW_KEY_IDX 1
+
+// RW unlock key for EC version N24HT37W
+extern const uint8_t debug_rw_key[8];
+
+#endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
new file mode 100644
index 0000000000..d89ed712d4
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/gpio.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef GPIO_H
+#define GPIO_H
+
+void variant_config_gpios(void);
+
+#endif
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
new file mode 100644
index 0000000000..44c8578852
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/ramstage.c
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <option.h>
+#include <soc/ramstage.h>
+#include "ec.h"
+#include "gpio.h"
+
+#define GPIO_GPU_RST GPP_E22 // active low
+#define GPIO_1R8VIDEO_AON_ON GPP_E23
+
+#define GPIO_DGFX_PWRGD GPP_F3
+
+#define GPIO_DISCRETE_PRESENCE GPP_D9 // active low
+#define GPIO_DGFX_VRAM_ID0 GPP_D11
+#define GPIO_DGFX_VRAM_ID1 GPP_D12
+
+void mainboard_silicon_init_params(FSP_SIL_UPD *params)
+{
+ static const char * const dgfx_vram_id_str[] = { "1GB", "2GB", "4GB", "N/A" };
+
+ int dgfx_vram_id;
+
+ // Setup GPIOs
+ variant_config_gpios();
+
+ // Detect and enable dGPU
+ if (gpio_get(GPIO_DISCRETE_PRESENCE) == 0) { // active low
+ dgfx_vram_id = gpio_get(GPIO_DGFX_VRAM_ID0) | gpio_get(GPIO_DGFX_VRAM_ID1) << 1;
+ printk(BIOS_DEBUG, "Discrete GPU present with %s VRAM\n", dgfx_vram_id_str[dgfx_vram_id]);
+
+ // NOTE: i pulled this GPU enable sequence from thin air
+ // it sometimes works but is buggy and the GPU disappears in some cases so disabling it by default.
+ // also unrelated to this enable sequence the nouveau driver only works on 6.8-6.9 kernels
+ if (get_uint_option("dgpu_enable", 0)) {
+ printk(BIOS_DEBUG, "Enabling discrete GPU\n");
+ gpio_set(GPIO_1R8VIDEO_AON_ON, 1); // Enable GPU power rail
+ while (!gpio_get(GPIO_DGFX_PWRGD)) // Wait for power good signal from GPU
+ ;
+ gpio_set(GPIO_GPU_RST, 1); // Release GPU from reset
+ } else {
+ printk(BIOS_DEBUG, "Discrete GPU will remain disabled\n");
+ }
+
+ } else {
+ printk(BIOS_DEBUG, "Discrete GPU not present\n");
+ }
+}
+
+static void dump_ec_cfg(uint16_t port)
+{
+ microchip_pnp_enter_conf_state(port);
+
+ // Device info
+ printk(BIOS_DEBUG, "Device id %02x\n", pnp_read(port, EC_DEVICE_ID));
+ printk(BIOS_DEBUG, "Device rev %02x\n", pnp_read(port, EC_DEVICE_REV));
+
+ // Switch to LPCIF LDN
+ pnp_write(port, PNP_LDN_SELECT, LDN_LPCIF);
+
+ // Dump SIRQs
+ for (int i = 0; i <= 15; i += 1)
+ printk(BIOS_DEBUG, "SIRQ%d = %02x\n", i, pnp_read(port, LPCIF_SIRQ(i)));
+
+ // Dump BARs
+ printk(BIOS_DEBUG, "BAR CFG = %08x\n", pnp_read_le32(port, LPCIF_BAR_CFG));
+ printk(BIOS_DEBUG, "BAR MAILBOX = %08x\n", pnp_read_le32(port, LPCIF_BAR_MAILBOX));
+ printk(BIOS_DEBUG, "BAR 8042 = %08x\n", pnp_read_le32(port, LPCIF_BAR_8042));
+ printk(BIOS_DEBUG, "BAR ACPI_EC0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC0));
+ printk(BIOS_DEBUG, "BAR ACPI_EC1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC1));
+ printk(BIOS_DEBUG, "BAR ACPI_EC2 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC2));
+ printk(BIOS_DEBUG, "BAR ACPI_EC3 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_EC3));
+ printk(BIOS_DEBUG, "BAR ACPI_PM0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_ACPI_PM0));
+ printk(BIOS_DEBUG, "BAR UART = %08x\n", pnp_read_le32(port, LPCIF_BAR_UART));
+ printk(BIOS_DEBUG, "BAR FAST_KYBD = %08x\n", pnp_read_le32(port, LPCIF_BAR_FAST_KYBD));
+ printk(BIOS_DEBUG, "BAR EMBED_FLASH = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMBED_FLASH));
+ printk(BIOS_DEBUG, "BAR GP_SPI = %08x\n", pnp_read_le32(port, LPCIF_BAR_GP_SPI));
+ printk(BIOS_DEBUG, "BAR EMI = %08x\n", pnp_read_le32(port, LPCIF_BAR_EMI));
+ printk(BIOS_DEBUG, "BAR PMH7 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PMH7));
+ printk(BIOS_DEBUG, "BAR PORT80_DBG0 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG0));
+ printk(BIOS_DEBUG, "BAR PORT80_DBG1 = %08x\n", pnp_read_le32(port, LPCIF_BAR_PORT80_DBG1));
+ printk(BIOS_DEBUG, "BAR RTC = %08x\n", pnp_read_le32(port, LPCIF_BAR_RTC));
+
+ microchip_pnp_exit_conf_state(port);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ if (CONFIG(VGA_ROM_RUN))
+ install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
+ GMA_INT15_PANEL_FIT_DEFAULT,
+ GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
+}
+
+static void mainboard_init(void *chip_info)
+{
+ dump_ec_cfg(EC_CFG_PORT);
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+ .init = mainboard_init,
+};
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..4db4202961d0be67b75f52b28f2111d5655595c3
GIT binary patch
literal 4106
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zDF)LeX(GlTYoZ2xkUp4bc(Fbi;|s>bV0gipVB&+pHzmFpc`=IXxii}qiqH*)7}PU+
z?woV)x!<09?wNbfhQa6n_IK}3M!Gw&OgS)sY2Q$LJ4F+z{-JneATkt9refXr6+8sr
zR{e1eASVcGl#mf_O&p%I^1;3af=xDeN0ZnydT=;zHOH-q=O;(UFda)^<j^52Z;c<A
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zTqQzcH(berra`9K(R~0OJ_eeA<Ovbd&vdN3&y}qtJ`q3y6wpP2V}*{Dbi8b357>=>
z&R-)LYP^U3@%6h}+0)7m-mEOhOM92<j^WbYrTU_kNXz~GCDNT`I|IC3AsFzURKM6k
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z3yTO|pc0N&G3cozl21Q6c)l0vjm~0uFL)%2_T5RYR1$~dO~u)4px!jFycZNnchPVA
z!0+Vc_afL{m>rv2PY8{Cma`W{yG~JNJu?;L!#fSLmwRW{8R@gD7Z5~{xvZGpN)U`j
z^I~=;XVmtVzgSv@Na@HC?lC8A1l2+CU<IqV7J%6_t~L}S#%I}a5R3FZk`D#n4m*-O
z$?u%iuC_w$3p=)&nXQX^AwrdnK*hRu`Mqc`AzOgztfsBxvm77j5G7KQo#~<Ufx}jQ
z?|~8PU!d?s-JLd{0Ph}c6J*Zsxd^=dPINEGPS4+NOQoUG&E#4_TUNoTPI5CrmHR%r
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literal 0
HcmV?d00001
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads
new file mode 100644
index 0000000000..fcfbd75a92
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (eDP,
+ DP1,
+ DP2,
+ HDMI1,
+ HDMI2,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
new file mode 100644
index 0000000000..f7c29e1f39
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../gpio.h"
+
+/* FIXME: There are multiple GPIOs here that should be locked to prevent "TPM GPIO fail" style
+ * attacks. Unfortunately SKL/KBL GPIO locking *does not* work currently. */
+
+static const struct pad_config gpio_table[] = {
+
+ /* ------- GPIO Community 0 ------- */
+
+ /* ------- GPIO Group GPP_A ------- */
+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */
+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */
+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */
+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */
+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */
+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */
+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */
+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */
+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */
+ PAD_CFG_NF(GPP_A9, NATIVE, DEEP, NF1), /* LPCCLK_EC_24M */
+ PAD_CFG_NF(GPP_A10, NATIVE, DEEP, NF1), /* LPCCLK_DEBUG_24M */
+ PAD_NC(GPP_A11, NONE),
+ PAD_NC(GPP_A12, NONE),
+ PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */
+ PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */
+ PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSWARN */
+ PAD_NC(GPP_A16, NONE),
+ PAD_NC(GPP_A17, NONE),
+ PAD_NC(GPP_A18, NONE),
+ PAD_NC(GPP_A19, NONE),
+ PAD_NC(GPP_A20, NONE),
+ PAD_NC(GPP_A21, NONE),
+ PAD_NC(GPP_A22, NONE),
+ PAD_NC(GPP_A23, NONE),
+
+ /* ------- GPIO Group GPP_B ------- */
+ PAD_NC(GPP_B0, NONE),
+ PAD_NC(GPP_B1, NONE),
+ PAD_NC(GPP_B2, NONE),
+ PAD_NC(GPP_B3, NONE),
+ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 */
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 */
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE10 */
+ PAD_NC(GPP_B11, NONE),
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */
+ PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */
+ PAD_CFG_GPO(GPP_B15, 1, DEEP), /* NFC_DLREQ */
+ PAD_NC(GPP_B16, NONE),
+ PAD_NC(GPP_B17, NONE),
+ PAD_NC(GPP_B18, NONE),
+ PAD_NC(GPP_B19, NONE),
+ PAD_NC(GPP_B20, NONE),
+ PAD_NC(GPP_B21, NONE),
+ PAD_NC(GPP_B22, NONE),
+ PAD_NC(GPP_B23, NONE),
+
+ /* ------- GPIO Community 1 ------- */
+
+ /* ------- GPIO Group GPP_C ------- */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
+ PAD_NC(GPP_C2, NONE),
+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */
+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
+ PAD_NC(GPP_C5, NONE),
+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */
+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */
+ PAD_NC(GPP_C8, NONE),
+ PAD_NC(GPP_C9, NONE),
+ PAD_NC(GPP_C10, NONE),
+ PAD_NC(GPP_C11, NONE),
+ PAD_NC(GPP_C12, NONE),
+ PAD_NC(GPP_C13, NONE),
+ PAD_NC(GPP_C14, NONE),
+ PAD_NC(GPP_C15, NONE),
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */
+ PAD_NC(GPP_C18, NONE),
+ PAD_NC(GPP_C19, NONE),
+ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
+ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
+
+ /* ------- GPIO Group GPP_D ------- */
+ PAD_NC(GPP_D0, NONE),
+ PAD_NC(GPP_D1, NONE),
+ PAD_NC(GPP_D2, NONE),
+ PAD_NC(GPP_D3, NONE),
+ PAD_NC(GPP_D4, NONE),
+ PAD_NC(GPP_D5, NONE),
+ PAD_NC(GPP_D6, NONE),
+ PAD_NC(GPP_D7, NONE),
+ PAD_NC(GPP_D8, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */
+ PAD_NC(GPP_D10, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */
+ PAD_NC(GPP_D13, NONE),
+ PAD_NC(GPP_D14, NONE),
+ PAD_NC(GPP_D15, NONE),
+ PAD_NC(GPP_D16, NONE),
+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY1 */
+ PAD_NC(GPP_D18, NONE),
+ PAD_NC(GPP_D19, NONE),
+ PAD_NC(GPP_D20, NONE),
+ PAD_NC(GPP_D21, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */
+ PAD_NC(GPP_D23, NONE),
+
+ /* ------- GPIO Group GPP_E ------- */
+ PAD_NC(GPP_E0, NONE),
+ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -WWAN_SATA_DTCT (always HIGH) */
+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -PE_DTCT */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */
+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */
+ PAD_NC(GPP_E5, NONE),
+ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */
+ PAD_NC(GPP_E7, NONE),
+ PAD_NC(GPP_E8, NONE),
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 (AON port) */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 (regular port) */
+ PAD_NC(GPP_E11, NONE),
+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */
+ PAD_NC(GPP_E15, NONE),
+ PAD_NC(GPP_E16, NONE),
+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
+ PAD_NC(GPP_E18, NONE),
+ PAD_NC(GPP_E19, NONE),
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */
+ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */
+ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */
+
+ /* ------- GPIO Community 2 ------- */
+
+ /* -------- GPIO Group GPD -------- */
+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */
+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */
+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */
+ PAD_NC(GPD7, NONE),
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */
+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */
+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
+
+ /* ------- GPIO Community 3 ------- */
+
+ /* ------- GPIO Group GPP_F ------- */
+ PAD_NC(GPP_F0, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */
+ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, ACPI), /* DGFX_PWRGD */
+ PAD_CFG_GPO(GPP_F4, 1, DEEP), /* -WWAN_RESET */
+ PAD_NC(GPP_F5, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */
+ PAD_NC(GPP_F16, NONE),
+ PAD_NC(GPP_F17, NONE),
+ PAD_NC(GPP_F18, NONE),
+ PAD_NC(GPP_F19, NONE),
+ PAD_NC(GPP_F20, NONE),
+ PAD_NC(GPP_F21, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -INTRUDER_PCH */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */
+
+ /* ------- GPIO Group GPP_G ------- */
+ PAD_NC(GPP_G0, NONE),
+ PAD_NC(GPP_G1, NONE),
+ PAD_NC(GPP_G2, NONE),
+ PAD_NC(GPP_G3, NONE),
+ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
+ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
+ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
+ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
+};
+
+void variant_config_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
new file mode 100644
index 0000000000..3a951ce0da
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/hda_verb.c
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257
+ 0x17aa225d, // Subsystem ID
+ 11,
+ AZALIA_SUBVENDOR(0, 0x17aa225d),
+
+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+ AZALIA_INTEGRATED,
+ AZALIA_INTERNAL,
+ AZALIA_MIC_IN,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_NO_JACK_PRESENCE_DETECT,
+ 2, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+ AZALIA_INTEGRATED,
+ AZALIA_INTERNAL,
+ AZALIA_SPEAKER,
+ AZALIA_OTHER_ANALOG,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_NO_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+ AZALIA_MIC_IN,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_BLACK,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 3, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+ AZALIA_HP_OUT,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_BLACK,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 15
+ )),
+
+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
+ 0x80860101, // Subsystem ID
+ 4,
+ AZALIA_SUBVENDOR(2, 0x80860101),
+
+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 2, 0
+ )),
+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 3, 0
+ )),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
new file mode 100644
index 0000000000..5252a402f9
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/memory_init_params.c
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/romstage.h>
+#include <spd_bin.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */
+ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */
+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
+
+ /* Get SPD for memory slots */
+ struct spd_block blk = { .addr_map = { 0x50, 0x51, } };
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)blk.spd_array[0];
+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
new file mode 100644
index 0000000000..bf66bd3a69
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/overridetree.cb
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+ device domain 0 on
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC1), // USB-A
+ [1] = USB2_PORT_MID(OC0), // USB-A (always on)
+ [2] = USB2_PORT_MID(OC_SKIP), // JSC-1 (smartcard slot)
+ [3] = USB2_PORT_MID(OC_SKIP), // USB-C (charging port)
+ [4] = USB2_PORT_MID(OC_SKIP), // JCAM1 (IR camera)
+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN1 (M.2 WWAN USB)
+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN1 (M.2 WLAN USB)
+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM1 (webcam)
+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR1 (fingerprint reader)
+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD1 (touch panel)
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC1), // USB-A
+ [1] = USB3_PORT_DEFAULT(OC0), // USB-A (always on)
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // RTS5344S (SD card reader)
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C (charging port)
+ }"
+ end
+
+ device ref sata on
+ # SATA_2 - JHDD1 SATA SSD
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[2]" = "1"
+ end
+
+ # PCIe controller 1 - 1x4
+ # PCIE 1-4 - RP1 - dGPU - CLKOUT0 - CLKREQ0
+ #
+ # PCIe controller 2 - 2x1+1x2 (lane reversal)
+ # PCIE 5 - GBE - GBE - CLKOUT1 - CLKREQ1 (clobbers RP8)
+ # PCIE 6 - RP7 - WLAN - CLKOUT2 - CLKREQ2
+ # PCIE 7-8 - RP5 - WWAN - CLKOUT3 - CLKREQ3
+ #
+ # PCIe controller 3 - 2x2
+ # PCIE 9-10 - RP9 - TB3 - CLKOUT4 - CLKREQ4
+ # PCIE 11-12 - RP11 - SSD - CLKOUT5 - CLKREQ5
+
+ # dGPU - x4
+ device ref pcie_rp1 on
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "0"
+ register "PcieRpClkSrcNumber[0]" = "0"
+ register "PcieRpAdvancedErrorReporting[0]" = "1"
+ register "PcieRpLtrEnable[0]" = "1"
+ end
+
+ # Ethernet (clobbers RP8)
+ device ref gbe on
+ register "LanClkReqSupported" = "1"
+ register "LanClkReqNumber" = "1"
+ register "EnableLanLtr" = "1"
+ register "EnableLanK1Off" = "1"
+ end
+
+ # M.2 WLAN - x1
+ device ref pcie_rp7 on
+ register "PcieRpEnable[6]" = "1"
+ register "PcieRpClkReqSupport[6]" = "1"
+ register "PcieRpClkReqNumber[6]" = "2"
+ register "PcieRpClkSrcNumber[6]" = "2"
+ register "PcieRpAdvancedErrorReporting[6]" = "1"
+ register "PcieRpLtrEnable[6]" = "1"
+ end
+
+ # M.2 WWAN - x2
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ register "PcieRpClkReqNumber[4]" = "3"
+ register "PcieRpClkSrcNumber[4]" = "3"
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ register "PcieRpLtrEnable[4]" = "1"
+ end
+
+ # TB3 (Alpine Ridge LP) - x2
+ device ref pcie_rp9 on
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "4"
+ register "PcieRpClkSrcNumber[8]" = "4"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieRpHotPlug[8]" = "1"
+ end
+
+ # M.2 2280 caddy - x2
+ device ref pcie_rp11 on
+ register "PcieRpEnable[10]" = "1"
+ register "PcieRpClkReqSupport[10]" = "1"
+ register "PcieRpClkReqNumber[10]" = "5"
+ register "PcieRpClkSrcNumber[10]" = "5"
+ register "PcieRpAdvancedErrorReporting[10]" = "1"
+ register "PcieRpLtrEnable[10]" = "1"
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..47732e37d5b2bad4e674fd10eafa605d26f97840
GIT binary patch
literal 4106
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z&9^i2&Hiq_`R2ZF8ipf7IM{nI5$^585@kULrrx0OPKv~ngNI__q41$dA{p()ui+v1
zw(9rm09lUPAP4nOTm0CRnF|aw5^SQSH<G}<u_Gfnvn6IuK0h@!j;UxI!$*&rIdkIh
zl$piB;eBDWa1|CgK9bAg{^O%Z%!ziiz{neeJDb~fBI?1GV5p^44?a$ETl=n1d+;%Z
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literal 0
HcmV?d00001
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
new file mode 100644
index 0000000000..fcfbd75a92
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gma-mainboard.ads
@@ -0,0 +1,19 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (eDP,
+ DP1,
+ DP2,
+ HDMI1,
+ HDMI2,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
new file mode 100644
index 0000000000..a98dd2bc4e
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
@@ -0,0 +1,199 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/gpio.h>
+#include "../../gpio.h"
+
+static const struct pad_config gpio_table[] = {
+ /* ------- GPIO Community 0 ------- */
+
+ /* ------- GPIO Group GPP_A ------- */
+ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */
+ PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */
+ PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */
+ PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */
+ PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */
+ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */
+ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */
+ PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */
+ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */
+ PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */
+ PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */
+ PAD_NC(GPP_A11, NONE),
+ PAD_NC(GPP_A12, NONE),
+ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* -SUSWARN */
+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1), /* -SUS_STAT */
+ PAD_CFG_NF(GPP_A15, UP_20K, DEEP, NF1), /* -SUSWARN */
+ PAD_NC(GPP_A16, NONE),
+ PAD_NC(GPP_A17, NONE),
+ PAD_NC(GPP_A18, NONE),
+ PAD_NC(GPP_A19, NONE),
+ PAD_NC(GPP_A20, NONE),
+ PAD_NC(GPP_A21, NONE),
+ PAD_NC(GPP_A22, NONE),
+ PAD_NC(GPP_A23, NONE),
+
+ /* ------- GPIO Group GPP_B ------- */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+ PAD_NC(GPP_B2, NONE),
+ PAD_NC(GPP_B3, NONE),
+ PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (dGPU) */
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (WWAN) */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE4 (GBE) */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WLAN) */
+ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), /* -CLKREQ_PCIE6 (TB3) */
+ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE8 (SSD) */
+ PAD_NC(GPP_B11, NONE),
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */
+ PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), /* PCH_SPKR */
+ PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */
+ PAD_NC(GPP_B16, NONE),
+ PAD_NC(GPP_B17, NONE),
+ PAD_NC(GPP_B18, NONE),
+ PAD_NC(GPP_B19, NONE),
+ PAD_NC(GPP_B20, NONE),
+ PAD_NC(GPP_B21, NONE),
+ PAD_NC(GPP_B22, NONE),
+ PAD_NC(GPP_B23, NONE),
+
+ /* ------- GPIO Community 1 ------- */
+
+ /* ------- GPIO Group GPP_C ------- */
+ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
+ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
+ PAD_CFG_GPO(GPP_C2, 1, DEEP),
+ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */
+ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
+ PAD_NC(GPP_C5, NONE),
+ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */
+ PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */
+ PAD_NC(GPP_C8, NONE),
+ PAD_NC(GPP_C9, NONE),
+ PAD_NC(GPP_C10, NONE),
+ PAD_NC(GPP_C11, NONE),
+ PAD_NC(GPP_C12, NONE),
+ PAD_NC(GPP_C13, NONE),
+ PAD_NC(GPP_C14, NONE),
+ PAD_NC(GPP_C15, NONE),
+ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */
+ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */
+ PAD_NC(GPP_C18, NONE),
+ PAD_NC(GPP_C19, NONE),
+ PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
+ PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
+ PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
+ PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
+
+ /* ------- GPIO Group GPP_D ------- */
+ PAD_NC(GPP_D0, NONE),
+ PAD_NC(GPP_D1, NONE),
+ PAD_NC(GPP_D2, NONE),
+ PAD_NC(GPP_D3, NONE),
+ PAD_NC(GPP_D4, NONE),
+ PAD_NC(GPP_D5, NONE),
+ PAD_NC(GPP_D6, NONE),
+ PAD_NC(GPP_D7, NONE),
+ PAD_NC(GPP_D8, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D9, UP_20K, DEEP, OFF, ACPI), /* -DISCRETE_PRESENCE */
+ PAD_NC(GPP_D10, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D11, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_D12, UP_20K, DEEP, OFF, ACPI), /* DGFX_VRAM_ID1 */
+ PAD_NC(GPP_D13, NONE),
+ PAD_NC(GPP_D14, NONE),
+ PAD_NC(GPP_D15, NONE),
+ PAD_NC(GPP_D16, NONE),
+ PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */
+ PAD_NC(GPP_D18, NONE),
+ PAD_NC(GPP_D19, NONE),
+ PAD_NC(GPP_D20, NONE),
+ PAD_NC(GPP_D21, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */
+ PAD_NC(GPP_D23, NONE),
+
+ /* ------- GPIO Group GPP_E ------- */
+ PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */
+ PAD_NC(GPP_E1, NONE),
+ PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1), /* -SATA2_DTCT */
+ PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */
+ PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */
+ PAD_NC(GPP_E5, NONE),
+ PAD_CFG_NF(GPP_E6, NONE, RSMRST, NF1), /* SATA2_DEVSLP */
+ PAD_NC(GPP_E7, NONE),
+ PAD_NC(GPP_E8, NONE),
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */
+ PAD_NC(GPP_E11, NONE),
+ PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */
+ PAD_NC(GPP_E15, NONE),
+ PAD_NC(GPP_E16, NONE),
+ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
+ PAD_NC(GPP_E18, NONE),
+ PAD_CFG_GPO(GPP_E19, 0, DEEP),
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */
+ PAD_CFG_TERM_GPO(GPP_E22, 0, UP_20K, RSMRST), /* -GPU_RST */
+ PAD_CFG_TERM_GPO(GPP_E23, 0, UP_20K, RSMRST), /* 1R8VIDEO_AON_ON */
+
+ /* ------- GPIO Community 2 ------- */
+
+ /* -------- GPIO Group GPD -------- */
+ PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */
+ PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */
+ PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */
+ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */
+ PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */
+ PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */
+ PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */
+ PAD_NC(GPD7, NONE),
+ PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */
+ PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */
+ PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */
+ PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
+
+ /* ------- GPIO Community 3 ------- */
+
+ /* ------- GPIO Group GPP_F ------- */
+ PAD_CFG_GPO(GPP_F0, 0, DEEP),
+ PAD_CFG_GPI_TRIG_OWN(GPP_F1, NONE, DEEP, OFF, ACPI), /* GC6_FB_EN */
+ PAD_CFG_GPO(GPP_F2, 1, DEEP), /* -GPU_EVENT */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, PLTRST, OFF, ACPI), /* DGFX_PWRGD */
+ PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */
+ PAD_NC(GPP_F5, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, DEEP, OFF, ACPI), /* -MIC_HW_EN (R37 to GND) */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, DEEP, OFF, ACPI), /* -INT_MIC_DTCT */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG1 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG2 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, DEEP, OFF, ACPI), /* WWAN_CFG3 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, DEEP, OFF, ACPI), /* PLANARID0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, DEEP, OFF, ACPI), /* PLANARID1 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, DEEP, OFF, ACPI), /* PLANARID2 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, DEEP, OFF, ACPI), /* PLANARID3 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */
+ PAD_NC(GPP_F21, NONE),
+ PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, DEEP, OFF, ACPI), /* -TAMPER_SW_DTCT */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, DEEP, OFF, ACPI), /* -SC_DTCT */
+
+ /* ------- GPIO Group GPP_G ------- */
+ PAD_NC(GPP_G0, NONE),
+ PAD_NC(GPP_G1, NONE),
+ PAD_NC(GPP_G2, NONE),
+ PAD_NC(GPP_G3, NONE),
+ PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
+ PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
+ PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
+ PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
+};
+
+void variant_config_gpios(void)
+{
+ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
new file mode 100644
index 0000000000..b1d96c5a76
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/hda_verb.c
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ 0x10ec0257, // Vendor/Device ID: Realtek ALC257
+ 0x17aa2258, // Subsystem ID
+ 11,
+ AZALIA_SUBVENDOR(0, 0x17aa2258),
+
+ AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
+ AZALIA_INTEGRATED,
+ AZALIA_INTERNAL,
+ AZALIA_MIC_IN,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_NO_JACK_PRESENCE_DETECT,
+ 2, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
+ AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
+ AZALIA_INTEGRATED,
+ AZALIA_INTERNAL,
+ AZALIA_SPEAKER,
+ AZALIA_OTHER_ANALOG,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_NO_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+ AZALIA_MIC_IN,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_BLACK,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 3, 0
+ )),
+ AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
+ AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
+ AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
+ AZALIA_HP_OUT,
+ AZALIA_STEREO_MONO_1_8,
+ AZALIA_BLACK,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 15
+ )),
+
+ 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
+ 0x80860101, // Subsystem ID
+ 4,
+ AZALIA_SUBVENDOR(2, 0x80860101),
+
+ AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+ AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+ AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
+ AZALIA_JACK,
+ AZALIA_DIGITAL_DISPLAY,
+ AZALIA_DIGITAL_OTHER_OUT,
+ AZALIA_OTHER_DIGITAL,
+ AZALIA_COLOR_UNKNOWN,
+ AZALIA_JACK_PRESENCE_DETECT,
+ 1, 0
+ )),
+};
+
+const u32 pc_beep_verbs[] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
new file mode 100644
index 0000000000..001e934b3a
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <cbfs.h>
+#include <gpio.h>
+#include <soc/gpio.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <stdio.h>
+
+static const struct pad_config memory_id_gpio_table[] = {
+ PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */
+ PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */
+};
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ int spd_idx;
+ char spd_name[20];
+ size_t spd_size;
+
+ FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
+ mem_cfg->DqPinsInterleaved = true; /* DDR_DQ in interleave mode */
+ mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */
+ mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
+
+ /* Get SPD for soldered RAM SPD (CH A) */
+ gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table));
+
+ spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 |
+ gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4;
+ printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx);
+ snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx);
+ mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map(spd_name, &spd_size);
+
+ /* Get SPD for memory slot (CH B) */
+ struct spd_block blk = { .addr_map = { [1] = 0x51, } };
+ get_spd_smbus(&blk);
+ dump_spd_info(&blk);
+
+ mem_cfg->MemorySpdPtr10 = (uintptr_t)blk.spd_array[1];
+}
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
new file mode 100644
index 0000000000..d4afca20c4
--- /dev/null
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/overridetree.cb
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+chip soc/intel/skylake
+ device domain 0 on
+ device ref south_xhci on
+ register "usb2_ports" = "{
+ [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on)
+ [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A)
+ [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot)
+ [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB-C)
+ [4] = USB2_PORT_MID(OC_SKIP), // JCAM (IR camera)
+ [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB)
+ [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB)
+ [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam)
+ [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader)
+ [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel)
+ }"
+ register "usb3_ports" = "{
+ [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on)
+ [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A)
+ [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader)
+ [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSBC (USB-C)
+ }"
+ end
+
+ device ref sata on
+ # SATA_2 - Main M.2 SATA SSD
+ register "SataPortsEnable[2]" = "1"
+ register "SataPortsDevSlp[2]" = "1"
+ end
+
+ # PCIe controller 1 - 1x2+2x1
+ # PCIE 1-2 - RP1 - dGPU - CLKOUT0 - CLKREQ0
+ # PCIE 4 - RP4 - WWAN - CLKOUT1 - CLKREQ1
+ #
+ # PCIe controller 2 - 2x1+1x2 (lane reversal)
+ # PCIE 5 - GBE - GBE - CLKOUT2 - CLKREQ2 (clobbers RP8)
+ # PCIE 6 - RP7 - WLAN - CLKOUT3 - CLKREQ3
+ # PCIE 7-8 - RP5 - TB3 - CLKOUT4 - CLKREQ4
+ #
+ # PCIe controller 3 - 1x4 (lane reversal)
+ # PCIE 9-12 - RP9 - SSD - CLKOUT5 - CLKREQ5
+
+ # dGPU - x2
+ device ref pcie_rp1 on
+ register "PcieRpEnable[0]" = "1"
+ register "PcieRpClkReqSupport[0]" = "1"
+ register "PcieRpClkReqNumber[0]" = "0"
+ register "PcieRpClkSrcNumber[0]" = "0"
+ register "PcieRpAdvancedErrorReporting[0]" = "1"
+ register "PcieRpLtrEnable[0]" = "1"
+ end
+
+ # M.2 WWAN - x1
+ device ref pcie_rp4 on
+ register "PcieRpEnable[3]" = "1"
+ register "PcieRpClkReqSupport[3]" = "1"
+ register "PcieRpClkReqNumber[3]" = "1"
+ register "PcieRpClkSrcNumber[3]" = "1"
+ register "PcieRpAdvancedErrorReporting[3]" = "1"
+ register "PcieRpLtrEnable[3]" = "1"
+ end
+
+ # Ethernet (clobbers RP8)
+ device ref gbe on
+ register "LanClkReqSupported" = "1"
+ register "LanClkReqNumber" = "2"
+ register "EnableLanLtr" = "1"
+ register "EnableLanK1Off" = "1"
+ end
+
+ # M.2 WLAN - x1
+ device ref pcie_rp7 on
+ register "PcieRpEnable[6]" = "1"
+ register "PcieRpClkReqSupport[6]" = "1"
+ register "PcieRpClkReqNumber[6]" = "3"
+ register "PcieRpClkSrcNumber[6]" = "3"
+ register "PcieRpAdvancedErrorReporting[6]" = "1"
+ register "PcieRpLtrEnable[6]" = "1"
+ end
+
+ # TB3 (Alpine Ridge LP) - x2
+ device ref pcie_rp5 on
+ register "PcieRpEnable[4]" = "1"
+ register "PcieRpClkReqSupport[4]" = "1"
+ register "PcieRpClkReqNumber[4]" = "4"
+ register "PcieRpClkSrcNumber[4]" = "4"
+ register "PcieRpAdvancedErrorReporting[4]" = "1"
+ register "PcieRpLtrEnable[4]" = "1"
+ register "PcieRpHotPlug[4]" = "1"
+ end
+
+ # M.2 2280 SSD - x2
+ device ref pcie_rp9 on
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpClkReqSupport[8]" = "1"
+ register "PcieRpClkReqNumber[8]" = "5"
+ register "PcieRpClkSrcNumber[8]" = "5"
+ register "PcieRpAdvancedErrorReporting[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ end
+ end
+end
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_0.bin
new file mode 100644
index 0000000000000000000000000000000000000000..86f39ddb55ea9fb58d5e5699637636ef597c734e
GIT binary patch
literal 512
zcmY!u;9+)EWZ+<6U|?oq29gXMJYRrxPEL*>N67~+1r7#Qh7a1t+8`-(puhlu3{YAD
YT>%dM8_BI;nL`dsaHtp+rc($20I8n}l>h($
literal 0
HcmV?d00001
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_1.bin
new file mode 100644
index 0000000000000000000000000000000000000000..df0f6e58b79286a4aeb690c5027adf7a1f5f668b
GIT binary patch
literal 512
zcmY!u;9+i6oWQ}rz`)GN3?vyic)kGXoSYm%j*<^t3LFfq3@hZcwLwzoK!E`Q8KATR
Yx&j>hH(SqvWezd%<4`dwOs5b40B_I==>Px#
literal 0
HcmV?d00001
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_10.bin
new file mode 100644
index 0000000000000000000000000000000000000000..24f0d8992bc5244c62488da9633e4885f52f3e22
GIT binary patch
literal 512
zcmY!u<Y9JIWZ+;(U|?oqW&i?q-XHu740(BZf(&^dxD+@TSQ$QOn`kgpFo@WI<Pkv3
zjN25185j^Oge*SRoUI_)=hwI&^9wTJQ%GaE+Z>cy&~OfFg0G3Wp`)phiHWn5fv$6q
PvjPw>z-1}5hGzN!nb#F$
literal 0
HcmV?d00001
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_11.bin
new file mode 100644
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_14.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_15.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_16.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_17.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_18.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_19.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_2.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_3.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_4.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_5.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_6.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_7.bin
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/spd/spd_8.bin
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--
2.39.5
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