mirror of
https://codeberg.org/libreboot/lbmk.git
synced 2026-07-16 03:25:25 +02:00
Leah Rowe
dbe24b039d
Several patches are now merged upstream and no longer needed in lbmk, such as the HP EliteBook 8560w patch, and related patches. Some patches were changed, for example the Dell Latitude ivb/snb laptops are now variants in coreboot, instead of being individual ports; now they re-use the same base code. This this, the corresponding files under config/submodules have changed, for things like 3rdparty submodules e.g. libgfxinit, and tarballs e.g. crossgcc. This is long overdue, and will enable more boards to be added. This newer revision will be used in the next release, and some follow-up patches will merge these trees into default: * coreboot/haswell * coreboot/dell Signed-off-by: Leah Rowe <leah@libreboot.org>
436 lines
14 KiB
Diff
436 lines
14 KiB
Diff
From 5d8a651a71d19918130f58c637700539dd320789 Mon Sep 17 00:00:00 2001
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From: Nicholas Chin <nic.c3.14@gmail.com>
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Date: Sun, 26 Nov 2023 17:08:52 -0700
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Subject: [PATCH 20/39] mb/dell: Add Latitude E6420 (Sandy Bridge)
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Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was
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not tested. I do not physically have this system; someone with physical
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access to one sent me the output of autoport which I then modified to
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produce this port. I was also sent the VBT binary, which was obtained
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from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the
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vendor firmware.
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This was originally tested and found to be working as a standalone board
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port in Libreboot, but this variant based port in upstream coreboot has
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not been tested.
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This can be internally flashed by sending a command to the EC, which
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causes the EC to pull the FDO pin low and the firmware to skip setting
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up any chipset based write protections [1]. The EC is the SMSC MEC5055,
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which seems to be compatible with the existing MEC5035 code.
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[1] https://gitlab.com/nic3-14159/dell-flash-unlock
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Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
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Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
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---
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src/mainboard/dell/snb_ivb_latitude/Kconfig | 13 +-
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.../dell/snb_ivb_latitude/Kconfig.name | 3 +
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.../snb_ivb_latitude/variants/e6420/data.vbt | Bin 0 -> 6144 bytes
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.../variants/e6420/early_init.c | 14 ++
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.../snb_ivb_latitude/variants/e6420/gpio.c | 191 ++++++++++++++++++
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.../variants/e6420/hda_verb.c | 32 +++
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.../variants/e6420/overridetree.cb | 35 ++++
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7 files changed, 287 insertions(+), 1 deletion(-)
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
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create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
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diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
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index 183a67bec3..d2786970ee 100644
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--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
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+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
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@@ -17,6 +17,12 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
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select SYSTEM_TYPE_LAPTOP
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select USE_NATIVE_RAMINIT
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+config BOARD_DELL_LATITUDE_E6420
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+ select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
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+ select BOARD_ROMSIZE_KB_10240
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+ select MAINBOARD_USES_IFD_GBE_REGION
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+ select SOUTHBRIDGE_INTEL_BD82X6X
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+
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config BOARD_DELL_LATITUDE_E5530
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select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
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select BOARD_ROMSIZE_KB_12288
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@@ -43,6 +49,7 @@ config MAINBOARD_DIR
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default "dell/snb_ivb_latitude"
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config MAINBOARD_PART_NUMBER
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+ default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
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default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
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default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
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default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
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@@ -54,11 +61,15 @@ config USBDEBUG_HCD_INDEX
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default 2
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config VARIANT_DIR
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+ default "e6420" if BOARD_DELL_LATITUDE_E6420
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default "e5530" if BOARD_DELL_LATITUDE_E5530
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default "e6430" if BOARD_DELL_LATITUDE_E6430
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default "e6530" if BOARD_DELL_LATITUDE_E6530
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config VGA_BIOS_ID
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- default "8086,0166"
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+ default "8086,0166" if BOARD_DELL_LATITUDE_E5530
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+ default "8086,0126" if BOARD_DELL_LATITUDE_E6420
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+ default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
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+ || BOARD_DELL_LATITUDE_E6530
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endif
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diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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index c15ef4028f..257d428a70 100644
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--- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
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@@ -1,5 +1,8 @@
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## SPDX-License-Identifier: GPL-2.0-only
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+config BOARD_DELL_LATITUDE_E6420
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+ bool "Latitude E6420"
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+
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config BOARD_DELL_LATITUDE_E5530
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bool "Latitude E5530"
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt
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new file mode 100644
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index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd
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GIT binary patch
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literal 6144
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zcmeHKeQZ-z6hE);wSBvNZ|mO1=*HLC2BQN8uVX6{N9eY)75ORymb$R8!YYuAZEgeE
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zKk|S@Fen*n41W-viAF;r%)~^EkpLz-B{2q##)LmGAtoY;7*Qhv_1yPbw$TC$2}G0K
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z=6Ao&x#ym9?z!i_&TOh(kLzky2cN8MTpny#R<;VU4Rkn?rBIz(YL~BBw<%b&zGhSH
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z$~AQ>@D0d=Xx6RE0BwSxspWdrW9y<FZGD@&x3_JL;p$p!;!BVdcKLkht0=-%(Jj&T
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z_GkyztZ%>#t7^)^(T-R<7W?O6ZTI%A+j=`<Jw3Q%dk6N!da<_?7oyiU3)^<~_TiSk
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zE$y+=RK3PGQ`gzmXYPRBx>C|f*UP9{h|4>ANrAe~?ymV*)83AaT#FuTjP=C2cg5P~
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zt4w78r$t#300cWY_k)mevmAmFI3&oBfytoAAPQiYK$XEIgHwV@5-gJ-Q-*p8yfTDj
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zaDz=1Y!X1B3`OpQ&Ik}bM|0xHn0gYNZw0rT=7AXS2in-q8K^?)0|el+Z6geW7i7MM
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zv~!|>HqL-|Fk}EYOa@)R<X)VQ7c}d8R1b@RTn5rq(90|QRg0?wwZZz(6Dz}w>zg9Y
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z8;!mD_V*XSjT33~$`o`s>zEGBq8AQ`HaH?y!Fh2QiX1v@aCo4LaENf&DZ_cE2A2qb
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z5@cC}X)=S^1RvpXLWs~v*hqMau$!=t@B-mg!XV)|;eEm>!Z6`H;R4|&!d1d`f|S7^
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zli+B98*!TfPE&6~NVM5j3v{N3OTjpnm_L@BPh(}esd(J!gj?~iJP?n|OZZOiTqlql
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zg<NWR@g&-*W-E%A7|*1Z_`sVO$K&iAP+VIj9{<1hT%SXsK}IBk8!daftR`6-)EUiS
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zvv*HR(#-ZwhA~7wcmxbe4%E?Y7P0y{1q|nqR1L29UR8v@#No^g5MH)7!>{%-$T|cR
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zZx5|xm>Fl>;@$m};P{0WC>O~<Nl1`*PLgPN_hP2a^h+L$ls&SYrkDYr+&l*%%S?^Q
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ziPSdtHE<LNEnr7cs=ihL-C>-p>*$9CpHRLgN|POkqD^UP4nw|4nf0bc8MOBk<;%js
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zfpCAWNzqSPlz@X%j9CGrwZDKUl@K{g6pzqiIIARDQ)#@^RW&0pmNG;XZ?!SlHB?L#
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zKRAMgq(R;aQd%@Gy38-LS@ix)fR**(P3B9wI=Uk^&cWmmwB<vf21<0#LBA!;qtAh(
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zYe5g_T{+gw^mi8QzPPraBoH~8oCz%r=$nVi1A)`Y8IKqIdqm6MihqxtpFaTggaPxu
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zQP07nf#&kPkPp}Cmk$F1g7q7QK;kz~80i&oDN}~wYbPUI6AtG5H+$T!@f5FzUhp21
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z^XiPT3rb%B@sA9g!n88R7BOsLS|?+D3}0v3dyIX|@JFWo&e%<c#V)PV#g@7-=F*;V
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zvAr&Q+ogTvVxPM3XP5Smi`f;Nt7uCU)}Y`HMcbpW=M_AuXlE35PQl+4O{7m66&I@7
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zGL@}Sai^*sP}va`KTx$VRQ8REf2*1+lTFH0=UkNx+eN|1rVyipl)Du=h=@%w+iQZG
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zT6@-PdW^oyFb44AG`HMZWEnP{&OQ+jC`N4emoS)x;EPN}uaSFOf-Mn8JRRO<WJc
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zn6%=L94~PR)%Ua_HTZcfTXD<p{%8p|<N<;Efw$Zb4$}{m8@7c((~<7^thaau&@Wx#
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zVGNL)lmH@{o=h*{muXGc!;nXrVgpp3;1V1stMj=4AtxyzX+?SoB~zN}!*r?9Qvs1P
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zmV_(CTmt0sY&6=F=_M>E34GYvuh1uQF+BUdWyQC5SaEM1QvKlHBMs13C}n{0SwRxW
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ziekMa&kvRFruRcKCevGy5)TxUBDlur@E{TtQ^NQ>nO+Cgl)&Ga(PxqVW?e3TLH-UY
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zdL3T{z^xdd`$(STFUb8R*cKa}r>n{Wk+MXRH~o-hN}#9OF*>T#>rfhiRs(Wc-R^9@
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z%F=<}dn(E}ADc03zJ>JvZe;_8f+WFLL4%qNYs`_aa`a$Pl5H;iO^Wt*cP3W(d=(g}
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zZ%nKT1$|r-tAv8($u2-BI2Uiz#%OT&!Q3b~Ru2P2j;Gem!@wfPsTR%J>W{8z)oq^J
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k^Qm&?O@bFkw4CTocwoW<6CRlGz=Q`TJTT#bN9KWl0rH4|j{pDw
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literal 0
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HcmV?d00001
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
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new file mode 100644
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index 0000000000..ff83db095b
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--- /dev/null
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+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
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@@ -0,0 +1,14 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <bootblock_common.h>
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+#include <device/pci_ops.h>
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+#include <ec/dell/mec5035/mec5035.h>
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+#include <southbridge/intel/bd82x6x/pch.h>
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+
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+void bootblock_mainboard_early_init(void)
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+{
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+ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
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+ | KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
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+ | COMB_LPC_EN | COMA_LPC_EN);
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+ mec5035_early_init();
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+}
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diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
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new file mode 100644
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index 0000000000..943c743f48
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--- /dev/null
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+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
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@@ -0,0 +1,191 @@
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+/* SPDX-License-Identifier: GPL-2.0-only */
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+
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+#include <southbridge/intel/common/gpio.h>
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
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+ .gpio0 = GPIO_MODE_GPIO,
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+ .gpio1 = GPIO_MODE_NATIVE,
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+ .gpio2 = GPIO_MODE_GPIO,
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+ .gpio3 = GPIO_MODE_NATIVE,
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+ .gpio4 = GPIO_MODE_GPIO,
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+ .gpio5 = GPIO_MODE_NATIVE,
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+ .gpio6 = GPIO_MODE_GPIO,
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+ .gpio7 = GPIO_MODE_GPIO,
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+ .gpio8 = GPIO_MODE_GPIO,
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+ .gpio9 = GPIO_MODE_NATIVE,
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+ .gpio10 = GPIO_MODE_NATIVE,
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+ .gpio11 = GPIO_MODE_NATIVE,
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+ .gpio12 = GPIO_MODE_NATIVE,
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+ .gpio13 = GPIO_MODE_GPIO,
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+ .gpio14 = GPIO_MODE_GPIO,
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+ .gpio15 = GPIO_MODE_GPIO,
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+ .gpio16 = GPIO_MODE_GPIO,
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+ .gpio17 = GPIO_MODE_GPIO,
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+ .gpio18 = GPIO_MODE_NATIVE,
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+ .gpio19 = GPIO_MODE_GPIO,
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+ .gpio20 = GPIO_MODE_NATIVE,
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+ .gpio21 = GPIO_MODE_GPIO,
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+ .gpio22 = GPIO_MODE_GPIO,
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+ .gpio23 = GPIO_MODE_NATIVE,
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+ .gpio24 = GPIO_MODE_GPIO,
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+ .gpio25 = GPIO_MODE_NATIVE,
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+ .gpio26 = GPIO_MODE_NATIVE,
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+ .gpio27 = GPIO_MODE_GPIO,
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+ .gpio28 = GPIO_MODE_GPIO,
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+ .gpio29 = GPIO_MODE_GPIO,
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+ .gpio30 = GPIO_MODE_GPIO,
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+ .gpio31 = GPIO_MODE_GPIO,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
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+ .gpio0 = GPIO_DIR_INPUT,
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+ .gpio2 = GPIO_DIR_INPUT,
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+ .gpio4 = GPIO_DIR_INPUT,
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+ .gpio6 = GPIO_DIR_INPUT,
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+ .gpio7 = GPIO_DIR_INPUT,
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+ .gpio8 = GPIO_DIR_INPUT,
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+ .gpio13 = GPIO_DIR_INPUT,
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+ .gpio14 = GPIO_DIR_INPUT,
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+ .gpio15 = GPIO_DIR_INPUT,
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+ .gpio16 = GPIO_DIR_INPUT,
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+ .gpio17 = GPIO_DIR_INPUT,
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+ .gpio19 = GPIO_DIR_INPUT,
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+ .gpio21 = GPIO_DIR_INPUT,
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+ .gpio22 = GPIO_DIR_INPUT,
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+ .gpio24 = GPIO_DIR_INPUT,
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+ .gpio27 = GPIO_DIR_INPUT,
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+ .gpio28 = GPIO_DIR_INPUT,
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+ .gpio29 = GPIO_DIR_INPUT,
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+ .gpio30 = GPIO_DIR_OUTPUT,
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+ .gpio31 = GPIO_DIR_INPUT,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_level = {
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+ .gpio30 = GPIO_LEVEL_HIGH,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
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+ .gpio0 = GPIO_INVERT,
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+ .gpio8 = GPIO_INVERT,
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+ .gpio14 = GPIO_INVERT,
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+};
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+
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+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
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+ .gpio32 = GPIO_MODE_NATIVE,
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+ .gpio33 = GPIO_MODE_GPIO,
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+ .gpio34 = GPIO_MODE_GPIO,
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+ .gpio35 = GPIO_MODE_GPIO,
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+ .gpio36 = GPIO_MODE_GPIO,
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+ .gpio37 = GPIO_MODE_GPIO,
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+ .gpio38 = GPIO_MODE_GPIO,
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+ .gpio39 = GPIO_MODE_GPIO,
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+ .gpio40 = GPIO_MODE_NATIVE,
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+ .gpio41 = GPIO_MODE_NATIVE,
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+ .gpio42 = GPIO_MODE_NATIVE,
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+ .gpio43 = GPIO_MODE_NATIVE,
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|
+ .gpio44 = GPIO_MODE_NATIVE,
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+ .gpio45 = GPIO_MODE_GPIO,
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+ .gpio46 = GPIO_MODE_NATIVE,
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+ .gpio47 = GPIO_MODE_NATIVE,
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+ .gpio48 = GPIO_MODE_GPIO,
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+ .gpio49 = GPIO_MODE_GPIO,
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|
+ .gpio50 = GPIO_MODE_NATIVE,
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+ .gpio51 = GPIO_MODE_GPIO,
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+ .gpio52 = GPIO_MODE_GPIO,
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|
+ .gpio53 = GPIO_MODE_NATIVE,
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|
+ .gpio54 = GPIO_MODE_GPIO,
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|
+ .gpio55 = GPIO_MODE_NATIVE,
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|
+ .gpio56 = GPIO_MODE_NATIVE,
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|
+ .gpio57 = GPIO_MODE_GPIO,
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|
+ .gpio58 = GPIO_MODE_NATIVE,
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|
+ .gpio59 = GPIO_MODE_NATIVE,
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+ .gpio60 = GPIO_MODE_GPIO,
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+ .gpio61 = GPIO_MODE_NATIVE,
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+ .gpio62 = GPIO_MODE_NATIVE,
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+ .gpio63 = GPIO_MODE_NATIVE,
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
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+ .gpio33 = GPIO_DIR_INPUT,
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+ .gpio34 = GPIO_DIR_OUTPUT,
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|
+ .gpio35 = GPIO_DIR_INPUT,
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|
+ .gpio36 = GPIO_DIR_INPUT,
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|
+ .gpio37 = GPIO_DIR_INPUT,
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|
+ .gpio38 = GPIO_DIR_INPUT,
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|
+ .gpio39 = GPIO_DIR_INPUT,
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|
+ .gpio45 = GPIO_DIR_OUTPUT,
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|
+ .gpio48 = GPIO_DIR_INPUT,
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+ .gpio49 = GPIO_DIR_OUTPUT,
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+ .gpio51 = GPIO_DIR_INPUT,
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|
+ .gpio52 = GPIO_DIR_INPUT,
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+ .gpio54 = GPIO_DIR_INPUT,
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+ .gpio57 = GPIO_DIR_INPUT,
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+ .gpio60 = GPIO_DIR_OUTPUT,
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_level = {
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+ .gpio34 = GPIO_LEVEL_HIGH,
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+ .gpio45 = GPIO_LEVEL_LOW,
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|
+ .gpio49 = GPIO_LEVEL_LOW,
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|
+ .gpio60 = GPIO_LEVEL_HIGH,
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+};
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+
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+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
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+};
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+
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+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
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+ .gpio64 = GPIO_MODE_NATIVE,
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|
+ .gpio65 = GPIO_MODE_NATIVE,
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|
+ .gpio66 = GPIO_MODE_NATIVE,
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|
+ .gpio67 = GPIO_MODE_NATIVE,
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+ .gpio68 = GPIO_MODE_GPIO,
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+ .gpio69 = GPIO_MODE_GPIO,
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+ .gpio70 = GPIO_MODE_GPIO,
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+ .gpio71 = GPIO_MODE_GPIO,
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+ .gpio72 = GPIO_MODE_NATIVE,
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+ .gpio73 = GPIO_MODE_NATIVE,
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+ .gpio74 = GPIO_MODE_NATIVE,
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|
+ .gpio75 = GPIO_MODE_NATIVE,
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
|
+ .gpio68 = GPIO_DIR_INPUT,
|
|
+ .gpio69 = GPIO_DIR_INPUT,
|
|
+ .gpio70 = GPIO_DIR_INPUT,
|
|
+ .gpio71 = GPIO_DIR_INPUT,
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_level = {
|
|
+};
|
|
+
|
|
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
|
|
+};
|
|
+
|
|
+const struct pch_gpio_map mainboard_gpio_map = {
|
|
+ .set1 = {
|
|
+ .mode = &pch_gpio_set1_mode,
|
|
+ .direction = &pch_gpio_set1_direction,
|
|
+ .level = &pch_gpio_set1_level,
|
|
+ .blink = &pch_gpio_set1_blink,
|
|
+ .invert = &pch_gpio_set1_invert,
|
|
+ .reset = &pch_gpio_set1_reset,
|
|
+ },
|
|
+ .set2 = {
|
|
+ .mode = &pch_gpio_set2_mode,
|
|
+ .direction = &pch_gpio_set2_direction,
|
|
+ .level = &pch_gpio_set2_level,
|
|
+ .reset = &pch_gpio_set2_reset,
|
|
+ },
|
|
+ .set3 = {
|
|
+ .mode = &pch_gpio_set3_mode,
|
|
+ .direction = &pch_gpio_set3_direction,
|
|
+ .level = &pch_gpio_set3_level,
|
|
+ .reset = &pch_gpio_set3_reset,
|
|
+ },
|
|
+};
|
|
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
|
|
new file mode 100644
|
|
index 0000000000..ede8445aaf
|
|
--- /dev/null
|
|
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
|
|
@@ -0,0 +1,32 @@
|
|
+/* SPDX-License-Identifier: GPL-2.0-only */
|
|
+
|
|
+#include <device/azalia_device.h>
|
|
+
|
|
+const u32 cim_verb_data[] = {
|
|
+ 0x111d76e7, /* Codec Vendor / Device ID: IDT */
|
|
+ 0x10280493, /* Subsystem ID */
|
|
+ 11, /* Number of 4 dword sets */
|
|
+ AZALIA_SUBVENDOR(0, 0x10280493),
|
|
+ AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
|
|
+ AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
|
|
+ AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
|
|
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
|
|
+ AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
|
|
+ AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
|
|
+ AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
|
|
+ AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
|
|
+ AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
|
|
+ AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
|
|
+
|
|
+ 0x80862805, /* Codec Vendor / Device ID: Intel */
|
|
+ 0x80860101, /* Subsystem ID */
|
|
+ 4, /* Number of 4 dword sets */
|
|
+ AZALIA_SUBVENDOR(3, 0x80860101),
|
|
+ AZALIA_PIN_CFG(3, 0x05, 0x18560010),
|
|
+ AZALIA_PIN_CFG(3, 0x06, 0x18560020),
|
|
+ AZALIA_PIN_CFG(3, 0x07, 0x18560030),
|
|
+};
|
|
+
|
|
+const u32 pc_beep_verbs[0] = {};
|
|
+
|
|
+AZALIA_ARRAY_SIZES;
|
|
diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
|
|
new file mode 100644
|
|
index 0000000000..3012a3177f
|
|
--- /dev/null
|
|
+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
|
|
@@ -0,0 +1,35 @@
|
|
+## SPDX-License-Identifier: GPL-2.0-or-later
|
|
+
|
|
+chip northbridge/intel/sandybridge
|
|
+ device domain 0 on
|
|
+ subsystemid 0x1028 0x0493 inherit
|
|
+
|
|
+ device ref igd on
|
|
+ register "gpu_cpu_backlight" = "0x0000054f"
|
|
+ register "gpu_pch_backlight" = "0x13121312"
|
|
+ end
|
|
+
|
|
+ chip southbridge/intel/bd82x6x
|
|
+ register "usb_port_config" = "{
|
|
+ { 1, 1, 0 },
|
|
+ { 1, 1, 0 },
|
|
+ { 1, 1, 1 },
|
|
+ { 1, 1, 1 },
|
|
+ { 1, 0, 2 },
|
|
+ { 1, 1, 2 },
|
|
+ { 1, 1, 3 },
|
|
+ { 1, 1, 3 },
|
|
+ { 1, 1, 5 },
|
|
+ { 1, 1, 5 },
|
|
+ { 1, 1, 7 },
|
|
+ { 1, 1, 6 },
|
|
+ { 1, 0, 6 },
|
|
+ { 1, 0, 7 },
|
|
+ }"
|
|
+
|
|
+ device ref sata1 on
|
|
+ register "sata_port_map" = "0x3b"
|
|
+ end
|
|
+ end
|
|
+ end
|
|
+end
|
|
--
|
|
2.39.2
|
|
|