mirror of
https://codeberg.org/libreboot/lbmk.git
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Leah Rowe
b95a411a36
Patchset 20 from: https://review.coreboot.org/c/coreboot/+/83274/18..20 Updated to that. A bunch of changes I made locally have been copied here, thus removed from lbmk. The previous setup in lbmk was to have only the DIMM slot work, on the ThinkPad T480S, without setting up SPD for the onboard RAM> Mate Kukri reverse engineered the scheme by which the SPDs are chosen at boot, based on the wiring of the board. This should just about match the way Lenovo did it in their firmware. Signed-off-by: Leah Rowe <leah@libreboot.org>
31 lines
993 B
Diff
31 lines
993 B
Diff
From b3049cfd11aa0f3c124ed8f87e98a200201ecbdc Mon Sep 17 00:00:00 2001
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From: Mate Kukri <km@mkukri.xyz>
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Date: Fri, 22 Nov 2024 21:26:48 +0000
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Subject: [PATCH 3/8] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
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bootblock
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Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173
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Signed-off-by: Mate Kukri <km@mkukri.xyz>
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---
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src/soc/intel/skylake/bootblock/pch.c | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
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index df00bb85a9..beaece960b 100644
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--- a/src/soc/intel/skylake/bootblock/pch.c
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+++ b/src/soc/intel/skylake/bootblock/pch.c
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@@ -100,8 +100,8 @@ static void soc_config_pwrmbase(void)
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void pch_early_iorange_init(void)
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{
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- uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
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- LPC_IOE_EC_62_66;
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+ uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F |
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+ LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66;
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const config_t *config = config_of_soc();
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--
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2.39.5
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