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Leah Rowe
2edd583aee
Courtesy of Kat Inskip who ported this board. Headphone output doesn't work at the moment, due to incorrect verb. Intel VBT is also wrong. Both are taken from another board. This will be amended later with the correct verb and VBT. Signed-off-by: Leah Rowe <leah@libreboot.org>
48 lines
1.9 KiB
Diff
48 lines
1.9 KiB
Diff
From 71ec1f7a6480e72b77a567f8cc0c2673a5e7905f Mon Sep 17 00:00:00 2001
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From: Leah Rowe <info@minifree.org>
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Date: Wed, 11 Dec 2024 01:06:01 +0000
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Subject: [PATCH 28/48] dell/3050micro: disable nvme hotplug
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in my testing, when running my 3050micro for a few days,
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the nvme would sometimes randomly rename.
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e.g. nvme0n1 renamed to nvme0n2
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this might cause crashes in linux, if booting only from the
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nvme. in my case, i was booting from mdraid (sata+nvme) and
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every few days, the nvme would rename at least once, causing
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my RAID to become unsynced. since i'm using RAID1, this was
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OK and I could simply re-sync the array, but this is quite
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precarious indeed. if you're using raid0, that will potentially
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corrupt your RAID array indefinitely.
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this same issue manifested on the T480/T480 thinkpads, and
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S3 resume would break because of that, when booting from nvme,
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because the nvme would be "unplugged" and appear to linux as a
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new device (the one that you booted from).
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the fix there was to disable hotplugging on that pci-e slot
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for the nvme, so apply the same fix here for 3050 micro
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Signed-off-by: Leah Rowe <leah@libreboot.org>
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---
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.../dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb | 2 +-
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1 file changed, 1 insertion(+), 1 deletion(-)
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diff --git a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
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index c5f1749b2c..ff48a8121a 100644
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--- a/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
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+++ b/src/mainboard/dell/sklkbl_desktops/variants/optiplex_3050/overridetree.cb
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@@ -46,7 +46,7 @@ chip soc/intel/skylake
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register "PcieRpAdvancedErrorReporting[20]" = "1"
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register "PcieRpLtrEnable[20]" = "true"
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register "PcieRpClkSrcNumber[20]" = "3"
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- register "PcieRpHotPlug[20]" = "1"
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+ register "PcieRpHotPlug[20]" = "0"
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end
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end
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--
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2.47.3
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