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afccecbde01ce657bc7a65c2f69f9b4fbd958739
lbmk/config/coreboot/default/patches/0020-mb-dell-gm45_latitudes-Add-E4300-variant.patch
T
Leah Rowe c716341c13 cb/kabylake: don't hardcode power_on_after_fail 
I realised that the Dell OptiPlex 3050 Micro has NVRAM available.
Use that backend, and hardcode power_on_after_fail to Disable,
which is already done in cmos.default.

The Lenovo ThinkPad T480 currently has no option table in coreboot,
besides the CBFS one. For this, the CBFS option table has been
enabled, and the build system has been modified to insert
a relevant config for power_on_after_fail.

Nicholas Chin informs me that Kabylake generally has legacy NVRAM,
so enabling it for the T480/T480s should work, but we'll need
to use it in the future anyway; better to just use CBFS now.

I *could* use the CBFS backend on 3050micro as well.

Signed-off-by: Leah Rowe <leah@libreboot.org>
2025-10-06 04:03:36 +01:00

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Raw Blame History

From 75620139fe2bd6898d51dd7bd02e1031369feeec Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Thu, 26 Sep 2024 19:51:25 -0600
Subject: [PATCH 20/40] mb/dell/gm45_latitudes: Add E4300 variant
Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
---
src/mainboard/dell/gm45_latitude/Kconfig | 5 +
src/mainboard/dell/gm45_latitude/Kconfig.name | 3 +
.../gm45_latitude/variants/e4300/data.vbt | Bin 0 -> 3881 bytes
.../variants/e4300/gma-mainboard.ads | 17 +++
.../dell/gm45_latitude/variants/e4300/gpio.c | 138 ++++++++++++++++++
.../gm45_latitude/variants/e4300/hda_verb.c | 37 +++++
.../variants/e4300/overridetree.cb | 10 ++
7 files changed, 210 insertions(+)
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
index 4b026be2ba..9f0f56e304 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig
+++ b/src/mainboard/dell/gm45_latitude/Kconfig
@@ -20,6 +20,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
config BOARD_DELL_E6400
select BOARD_DELL_GM45_LATITUDE_COMMON
+config BOARD_DELL_E4300
+ select BOARD_DELL_GM45_LATITUDE_COMMON
+
if BOARD_DELL_GM45_LATITUDE_COMMON
config INTEL_GMA_DPLL_REF_FREQ
default 100000000
@@ -29,12 +32,14 @@ config MAINBOARD_DIR
config MAINBOARD_PART_NUMBER
default "Latitude E6400" if BOARD_DELL_E6400
+ default "Latitude E4300" if BOARD_DELL_E4300
config OVERRIDE_DEVICETREE
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config VARIANT_DIR
default "e6400" if BOARD_DELL_E6400
+ default "e4300" if BOARD_DELL_E4300
config USBDEBUG_HCD_INDEX
default 1
diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
index aefe777109..4dc95f46be 100644
--- a/src/mainboard/dell/gm45_latitude/Kconfig.name
+++ b/src/mainboard/dell/gm45_latitude/Kconfig.name
@@ -1,4 +1,7 @@
## SPDX-License-Identifier: GPL-2.0-only
+config BOARD_DELL_E4300
+ bool "Latitude E4300"
+
config BOARD_DELL_E6400
bool "Latitude E6400"
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
new file mode 100644
index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3
GIT binary patch
literal 3881
zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+
zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5a<biIGGii6#d8gP4#QmGpeGyBx))(i;53
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zN=hgb2&njUcPLB!=P$(o-$={^mxQGIHvtVGBS4IU%YyNVhd3krw*m^es@B12UftTZ
zHsf}zTi<zK_vS6VeYx!qdQTpH>PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC
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literal 0
HcmV?d00001
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
new file mode 100644
index 0000000000..89b81b3d69
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+ ports : constant Port_List :=
+ (DP2, -- dock DP
+ Analog, -- mainboard VGA
+ LVDS,
+ others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
new file mode 100644
index 0000000000..b50f8da0b5
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+ .gpio0 = GPIO_MODE_NATIVE,
+ .gpio1 = GPIO_MODE_GPIO,
+ .gpio2 = GPIO_MODE_GPIO,
+ .gpio3 = GPIO_MODE_GPIO,
+ .gpio4 = GPIO_MODE_GPIO,
+ .gpio5 = GPIO_MODE_GPIO,
+ .gpio6 = GPIO_MODE_GPIO,
+ .gpio7 = GPIO_MODE_GPIO,
+ .gpio8 = GPIO_MODE_GPIO,
+ .gpio9 = GPIO_MODE_NATIVE,
+ .gpio10 = GPIO_MODE_NATIVE,
+ .gpio11 = GPIO_MODE_NATIVE,
+ .gpio12 = GPIO_MODE_NATIVE,
+ .gpio13 = GPIO_MODE_GPIO,
+ .gpio14 = GPIO_MODE_GPIO,
+ .gpio15 = GPIO_MODE_NATIVE,
+ .gpio16 = GPIO_MODE_NATIVE,
+ .gpio17 = GPIO_MODE_GPIO,
+ .gpio18 = GPIO_MODE_GPIO,
+ .gpio19 = GPIO_MODE_GPIO,
+ .gpio20 = GPIO_MODE_GPIO,
+ .gpio21 = GPIO_MODE_GPIO,
+ .gpio22 = GPIO_MODE_GPIO,
+ .gpio23 = GPIO_MODE_NATIVE,
+ .gpio24 = GPIO_MODE_GPIO,
+ .gpio25 = GPIO_MODE_NATIVE,
+ .gpio26 = GPIO_MODE_NATIVE,
+ .gpio27 = GPIO_MODE_GPIO,
+ .gpio28 = GPIO_MODE_GPIO,
+ .gpio29 = GPIO_MODE_NATIVE,
+ .gpio30 = GPIO_MODE_NATIVE,
+ .gpio31 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+ .gpio1 = GPIO_DIR_INPUT,
+ .gpio2 = GPIO_DIR_INPUT,
+ .gpio3 = GPIO_DIR_INPUT,
+ .gpio4 = GPIO_DIR_INPUT,
+ .gpio5 = GPIO_DIR_INPUT,
+ .gpio6 = GPIO_DIR_INPUT,
+ .gpio7 = GPIO_DIR_INPUT,
+ .gpio8 = GPIO_DIR_INPUT,
+ .gpio13 = GPIO_DIR_INPUT,
+ .gpio14 = GPIO_DIR_INPUT,
+ .gpio17 = GPIO_DIR_INPUT,
+ .gpio18 = GPIO_DIR_INPUT,
+ .gpio19 = GPIO_DIR_INPUT,
+ .gpio20 = GPIO_DIR_INPUT,
+ .gpio21 = GPIO_DIR_INPUT,
+ .gpio22 = GPIO_DIR_INPUT,
+ .gpio24 = GPIO_DIR_INPUT,
+ .gpio27 = GPIO_DIR_INPUT,
+ .gpio28 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+ .gpio1 = GPIO_INVERT,
+ .gpio7 = GPIO_INVERT,
+ .gpio8 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+ .gpio32 = GPIO_MODE_NATIVE,
+ .gpio33 = GPIO_MODE_GPIO,
+ .gpio34 = GPIO_MODE_GPIO,
+ .gpio35 = GPIO_MODE_NATIVE,
+ .gpio36 = GPIO_MODE_GPIO,
+ .gpio37 = GPIO_MODE_GPIO,
+ .gpio38 = GPIO_MODE_GPIO,
+ .gpio39 = GPIO_MODE_GPIO,
+ .gpio40 = GPIO_MODE_NATIVE,
+ .gpio41 = GPIO_MODE_NATIVE,
+ .gpio42 = GPIO_MODE_NATIVE,
+ .gpio43 = GPIO_MODE_NATIVE,
+ .gpio44 = GPIO_MODE_NATIVE,
+ .gpio45 = GPIO_MODE_NATIVE,
+ .gpio46 = GPIO_MODE_NATIVE,
+ .gpio47 = GPIO_MODE_NATIVE,
+ .gpio48 = GPIO_MODE_GPIO,
+ .gpio49 = GPIO_MODE_GPIO,
+ .gpio50 = GPIO_MODE_NATIVE,
+ .gpio51 = GPIO_MODE_NATIVE,
+ .gpio52 = GPIO_MODE_GPIO,
+ .gpio53 = GPIO_MODE_GPIO,
+ .gpio54 = GPIO_MODE_NATIVE,
+ .gpio55 = GPIO_MODE_NATIVE,
+ .gpio56 = GPIO_MODE_GPIO,
+ .gpio57 = GPIO_MODE_GPIO,
+ .gpio58 = GPIO_MODE_NATIVE,
+ .gpio59 = GPIO_MODE_NATIVE,
+ .gpio60 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+ .gpio33 = GPIO_DIR_INPUT,
+ .gpio34 = GPIO_DIR_INPUT,
+ .gpio36 = GPIO_DIR_INPUT,
+ .gpio37 = GPIO_DIR_INPUT,
+ .gpio38 = GPIO_DIR_INPUT,
+ .gpio39 = GPIO_DIR_INPUT,
+ .gpio48 = GPIO_DIR_INPUT,
+ .gpio49 = GPIO_DIR_INPUT,
+ .gpio52 = GPIO_DIR_INPUT,
+ .gpio53 = GPIO_DIR_INPUT,
+ .gpio56 = GPIO_DIR_INPUT,
+ .gpio57 = GPIO_DIR_INPUT,
+ .gpio60 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+ .set1 = {
+ .mode = &pch_gpio_set1_mode,
+ .direction = &pch_gpio_set1_direction,
+ .level = &pch_gpio_set1_level,
+ .blink = &pch_gpio_set1_blink,
+ .invert = &pch_gpio_set1_invert,
+ },
+ .set2 = {
+ .mode = &pch_gpio_set2_mode,
+ .direction = &pch_gpio_set2_direction,
+ .level = &pch_gpio_set2_level,
+ },
+};
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
new file mode 100644
index 0000000000..a9948a93dd
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+ /* coreboot specific header */
+ 0x111d76b2, /* IDT 92HD71B7X */
+ 0x1028024d, /* Subsystem ID */
+ 13, /* Number of entries */
+
+ /* Pin Widget Verb Table */
+
+ AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
+ AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
+ AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
+ AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
+ AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
+ AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
+ AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
+ AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
+ AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
+ AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
+ AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
+ AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
+ AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
+};
+
+const u32 pc_beep_verbs[] = {
+ 0x00170500, /* power up codec */
+ 0x00d70500, /* power up speakers */
+ 0x00d70102, /* select mixer (input 0x2) for speakers */
+ 0x00d70740, /* enable speakers output */
+ 0x02770720, /* enable beep input */
+ 0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
+ 0x00d37000, /* unmute speakers */
+};
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
new file mode 100644
index 0000000000..20dfa245fb
--- /dev/null
+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/gm45
+ device domain 0 on
+ subsystemid 0x1028 0x024d inherit
+ chip southbridge/intel/i82801ix
+ device pci 1c.2 off end # PCIe Port #3
+ end
+ end
+end
--
2.47.3
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