mirror of
https://codeberg.org/libreboot/lbmk.git
synced 2026-07-23 07:19:24 +02:00
Leah Rowe
aa0e4205d6
i noticed that the enablement patch came first, before the actual driver. while this functioned overall, it was obviously flawed in terms of the resulting git history. the person who sent the patch previously had 0046- on both patch names, which meant that alphabetical sorting caused the enablement patch to be applied before the driver patch. furthermore: it seems that the submitted had manually re-applied the same Kconfig changes in the enablement patch, adding their own name - since Kconfig is not copyrightable anyway, in this specific example, or otherwise trivial, it's probably fine, but the original author on the gerrit patch is actually Matt DeVillier: https://review.coreboot.org/c/coreboot/+/88490 I have therefore simply re-based by checking out Matt's patch, on patchset 1. However, patchset 1 of Matt's patch uses patch set 16 of: https://review.coreboot.org/c/coreboot/+/75286 HustlerOne's lbmk merge uses patchset 18: https://review.coreboot.org/c/coreboot/+/75286/18 The differences between the two can be observed, thus: https://review.coreboot.org/c/coreboot/+/75286/16..18 It should be clarified that these patches are not upstreamed yet, but under heavy review on gerrit. However, testing has revealed that the patch is mostly stable. Signed-off-by: Leah Rowe <leah@libreboot.org>
124 lines
5.7 KiB
Diff
124 lines
5.7 KiB
Diff
From 5249bfd28ffcdab2d54c3c111ec6d3dc567ad090 Mon Sep 17 00:00:00 2001
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From: Matt DeVillier <matt.devillier@gmail.com>
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Date: Fri, 18 Jul 2025 14:24:05 -0500
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Subject: [PATCH 2/2] mb/lenovo/t480(s): Enable TBT support
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Select the discrete TBT controller driver, and configure the necessary
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GPIOs for the Alpine Ridge TBT controller to be fully functional.
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Update the documentation w/r/t TBT functionality.
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TEST=build/boot Lenovo T480, boot Linux, verify all TBT-related PCI
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devices populated, lower USB-C port works for USB data and PCIe.
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Change-Id: Ie5586fa72ed6819b9d1c37373c21605d39bad7b4
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Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
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---
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Documentation/mainboard/lenovo/t480.md | 5 ++---
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src/mainboard/lenovo/sklkbl_thinkpad/Kconfig | 2 ++
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src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c | 8 ++++----
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.../lenovo/sklkbl_thinkpad/variants/t480s/gpio.c | 8 ++++----
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4 files changed, 12 insertions(+), 11 deletions(-)
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diff --git a/Documentation/mainboard/lenovo/t480.md b/Documentation/mainboard/lenovo/t480.md
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index 9ebce8ff7d..4c3408c4aa 100644
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--- a/Documentation/mainboard/lenovo/t480.md
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+++ b/Documentation/mainboard/lenovo/t480.md
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@@ -162,8 +162,6 @@ binaries if only flashing the `bios` region.
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## Known Issues
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-- Alpine Ridge Thunderbolt 3 controller does not work
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- - Lower (right) USB-C port only works for charging/DP alt mode, not USB/PCIe data
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- Some Fn+F{1-12} keys aren't handled correctly
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- Nvidia dGPU is finicky
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- Needs option ROM
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@@ -175,6 +173,7 @@ binaries if only flashing the `bios` region.
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## Verified Working
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+- Alpine Ridge Thunderbolt 3 controller
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- Integrated graphics init with libgfxinit
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- video output: internal (eDP), miniDP
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- ACPI support
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@@ -196,4 +195,4 @@ binaries if only flashing the `bios` region.
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[from Lenovo's site]: https://pcsupport.lenovo.com/gb/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480s-type-20l7-20l8/solutions/ht508988-critical-intel-thunderbolt-software-and-firmware-updates-thinkpad
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[how to externally flash the TB3 firmware]: https://libreboot.org/docs/install/t480.html#thunderbolt-issue-read-this-before-flashing
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[Dell firmware updater]: https://web.archive.org/web/20241110222323/https://dl.dell.com/FOLDER04573471M/1/Inspiron_5468_1.3.0.exe
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-[Dell_PFS_Extract.py]: https://github.com/vuquangtrong/Dell-PFS-BIOS-Assembler/blob/master/Dell_PFS_Extract.py
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\ No newline at end of file
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+[Dell_PFS_Extract.py]: https://github.com/vuquangtrong/Dell-PFS-BIOS-Assembler/blob/master/Dell_PFS_Extract.py
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
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index 6036ceb06d..e6fb950d66 100644
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--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
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+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
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@@ -26,12 +26,14 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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config BOARD_LENOVO_T480
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bool
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select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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+ select DRIVERS_INTEL_DTBT
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select MEC1653_HAS_DEBUG_UNLOCK
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select VARIANT_HAS_DGPU
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config BOARD_LENOVO_T480S
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bool
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select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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+ select DRIVERS_INTEL_DTBT
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select VARIANT_HAS_DGPU
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if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
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index f337843fd9..ffd2841e49 100644
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--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
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+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480/gpio.c
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@@ -86,7 +86,7 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_C18, NONE),
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PAD_NC(GPP_C19, NONE),
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PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
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- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
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+ PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */
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PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
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PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
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@@ -191,9 +191,9 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_G1, NONE),
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PAD_NC(GPP_G2, NONE),
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PAD_NC(GPP_G3, NONE),
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- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
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- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
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- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
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+ PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */
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+ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */
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+ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */
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PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
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};
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diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
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index 4f1c57390d..c24c1abb07 100644
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--- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
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+++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/gpio.c
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@@ -82,7 +82,7 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_C18, NONE),
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PAD_NC(GPP_C19, NONE),
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PAD_CFG_GPO(GPP_C20, 0, DEEP), /* EPRIVACY_ON */
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- PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
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+ PAD_CFG_GPO(GPP_C21, 1, PLTRST), /* TBT_FORCE_PWR */
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PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
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PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
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@@ -187,9 +187,9 @@ static const struct pad_config gpio_table[] = {
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PAD_NC(GPP_G1, NONE),
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PAD_NC(GPP_G2, NONE),
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PAD_NC(GPP_G3, NONE),
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- PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
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- PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
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- PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
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+ PAD_CFG_GPO(GPP_G4, 1, PLTRST), /* TBT_RTD3_PWR_EN */
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+ PAD_CFG_GPO(GPP_G5, 1, PLTRST), /* TBT_FORCE_USB_PWR */
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+ PAD_CFG_GPO(GPP_G6, 1, PLTRST), /* -TBT_PERST */
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PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
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};
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--
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2.47.3
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