mirror of
https://codeberg.org/libreboot/lbmk.git
synced 2026-07-15 17:58:46 +02:00
Leah Rowe
4a6dc5553f
Base revision changed to: commit b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a Author: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Date: Fri Jan 5 16:48:17 2024 +0800 mb/google/dedede/var/metaknight:Add fw_config probe for multi codec and amplifier Of note: Several out-of-tree ports have been adjusted to use the new SPD config style, where it is defined in devicetree. I manually updated the E6530 patch myself, based on the update that Nicholas did on E6430 (Nicholas will later update the E6530 patch himself, and I'll re-merge the patch). Several upstream patches now exist in this revision, that we were able to remove from lbmk. The heap size patch was reverted upstream, as we did, but see: https://review.coreboot.org/c/coreboot/+/80023 https://review.coreboot.org/c/coreboot/+/79525 Although we still disable the TSEG Stage Cache, ivy/sandy/haswell should be reliable on S3 now (leaving TSEG Stage Cache disabled, for now, anyway). Also included in upstream now: commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94 Author: Bill Xie <persmule@hardenedlinux.org> Date: Sat Oct 7 01:32:51 2023 +0800 drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume Further patches from upstream: commit 432e92688eca0e85cbaebca3232f65936b305a98 Author: Bill Xie <persmule@hardenedlinux.org> Date: Fri Nov 3 12:34:01 2023 +0800 drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum This should fix S3 on GM45 thinkpads. Signed-off-by: Leah Rowe <leah@libreboot.org>
69 lines
2.2 KiB
Diff
69 lines
2.2 KiB
Diff
From 50a52cea2b43e6e407b456c082e908c7d29e090b Mon Sep 17 00:00:00 2001
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From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
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Date: Wed, 27 Oct 2021 13:36:01 +0200
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Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
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---
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src/mainboard/apple/macbook21/Kconfig | 1 +
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src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++
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src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++
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3 files changed, 20 insertions(+)
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diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
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index 5f5ffde588..27377b737c 100644
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--- a/src/mainboard/apple/macbook21/Kconfig
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+++ b/src/mainboard/apple/macbook21/Kconfig
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@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
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select HAVE_ACPI_TABLES
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select HAVE_ACPI_RESUME
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select I945_LVDS
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+ select DRIVERS_I2C_CK505
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config MAINBOARD_DIR
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default "apple/macbook21"
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diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c
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index 13d06f0839..88b8669c61 100644
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--- a/src/mainboard/apple/macbook21/cstates.c
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+++ b/src/mainboard/apple/macbook21/cstates.c
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@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = {
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.addrh = 0,
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}
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},
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+ {
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+ .ctype = 3,
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+ .latency = 17,
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+ .power = 250,
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+ .resource = {
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+ .space_id = ACPI_ADDRESS_SPACE_FIXED,
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+ .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL,
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+ .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT,
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+ .access_size = ACPI_ACCESS_SIZE_UNDEFINED,
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+ .addrl = 0x20,
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+ .addrh = 0,
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+ }
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+ },
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};
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int get_cst_entries(const acpi_cstate_t **entries)
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diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
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index fd86e939b9..263fbabcd1 100644
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--- a/src/mainboard/apple/macbook21/devicetree.cb
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+++ b/src/mainboard/apple/macbook21/devicetree.cb
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@@ -100,7 +100,13 @@ chip northbridge/intel/i945
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end
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device pci 1f.3 on # SMBUS
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subsystemid 0x8086 0x7270
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+ chip drivers/i2c/ck505
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+ register "mask" = "{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }"
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+ register "regs" = "{ 0x77, 0x77, 0x2d, 0x00, 0x21, 0x10, 0x3b, 0x06, 0x07, 0x0f, 0xf0, 0x01, 0x1e, 0x7f, 0x80, 0x80, 0x10, 0x08, 0x04, 0x01 }"
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+ device i2c 69 on end
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+ end
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end
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+
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end
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end
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end
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--
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2.39.2
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