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Leah Rowe
99a88ebfa2
Use patchset 15 instead of 14:
config/coreboot/default/patches/0061-WIP-OptiPlex-3050-Micro-port.patch
Rebase the verb patch; patchset 15 modified the Makefile:
config/coreboot/default/patches/0064-dell-optiplex_3050-add-hda_verb.c.patch
We were using patchset 14 for the 3050 micro:
https://review.coreboot.org/c/coreboot/+/82053/14
Now we use patchset 15:
https://review.coreboot.org/c/coreboot/+/82053/15
Without this patch, the fans are always on a low setting, on
the Dell OptiPlex 3050 Micro, even under stress conditions. With
this patch, the fans change speed according to CPU temperature.
I had to rebase my verb patch, because Mate modified the Makefile
to add his sch5555 handler, on the same line where I add hda_verb.
Mate tells me he will merge my verb and vbt patches into a further
patchset later on. For now, I've simply rebased these patches on
top of Mate's newer work; I've told him he can use them in his port.
I'm probably going to now issue a new revision ROM image for
Libreboot 20241008, so that users can get this fix sooner.
Signed-off-by: Leah Rowe <leah@libreboot.org>
56 lines
2.0 KiB
Diff
56 lines
2.0 KiB
Diff
From b24c5caf5a8f63555d3b71e7a786c822a4c262cc Mon Sep 17 00:00:00 2001
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From: Leah Rowe <info@minifree.org>
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Date: Sat, 4 May 2024 02:00:53 +0100
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Subject: [PATCH 39/65] nb/haswell: lock policy regs when disabling IOMMU
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Angel Pons told me I should do it. See comments here:
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https://review.coreboot.org/c/coreboot/+/81016
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I see no harm in complying with the request. I'll merge
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this into the main patch at a later date and try to
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get this upstreamed.
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Just a reminder: on Optiplex 9020 variants, Xorg locks up
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under Linux when tested with a graphics card; disabling
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IOMMU works around the issue. Intel graphics work just fine
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with IOMMU turned on. Libreboot disables IOMMU by default,
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on the 9020, so that users can install graphics cards easily.
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Signed-off-by: Leah Rowe <info@minifree.org>
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---
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src/northbridge/intel/haswell/early_init.c | 15 +++++++--------
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1 file changed, 7 insertions(+), 8 deletions(-)
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diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
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index 1a7e0b1076..e9506ee830 100644
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--- a/src/northbridge/intel/haswell/early_init.c
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+++ b/src/northbridge/intel/haswell/early_init.c
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@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void)
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const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
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u8 enable_iommu = get_uint_option("iommu", 1);
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- if (!enable_iommu)
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- return;
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-
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if (capid0_a & VTD_DISABLE)
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return;
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- /* Setup BARs: zeroize top 32 bits; set enable bit */
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- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
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- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
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- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
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- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
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+ if (enable_iommu) {
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+ /* Setup BARs: zeroize top 32 bits; set enable bit */
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+ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
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+ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
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+ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
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+ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
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+ }
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/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
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u32 reg32;
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--
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2.39.5
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