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Leah Rowe
4a6dc5553f
Base revision changed to: commit b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a Author: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Date: Fri Jan 5 16:48:17 2024 +0800 mb/google/dedede/var/metaknight:Add fw_config probe for multi codec and amplifier Of note: Several out-of-tree ports have been adjusted to use the new SPD config style, where it is defined in devicetree. I manually updated the E6530 patch myself, based on the update that Nicholas did on E6430 (Nicholas will later update the E6530 patch himself, and I'll re-merge the patch). Several upstream patches now exist in this revision, that we were able to remove from lbmk. The heap size patch was reverted upstream, as we did, but see: https://review.coreboot.org/c/coreboot/+/80023 https://review.coreboot.org/c/coreboot/+/79525 Although we still disable the TSEG Stage Cache, ivy/sandy/haswell should be reliable on S3 now (leaving TSEG Stage Cache disabled, for now, anyway). Also included in upstream now: commit 29030d0f3dad2ec6b86000dfe2c8e951ae80bf94 Author: Bill Xie <persmule@hardenedlinux.org> Date: Sat Oct 7 01:32:51 2023 +0800 drivers/pc80/rtc/option.c: Stop resetting CMOS during s3 resume Further patches from upstream: commit 432e92688eca0e85cbaebca3232f65936b305a98 Author: Bill Xie <persmule@hardenedlinux.org> Date: Fri Nov 3 12:34:01 2023 +0800 drivers/pc80/rtc/option.c: Reset only CMOS range covered by checksum This should fix S3 on GM45 thinkpads. Signed-off-by: Leah Rowe <leah@libreboot.org>
48 lines
1.7 KiB
Diff
48 lines
1.7 KiB
Diff
From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001
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From: Leah Rowe <leah@libreboot.org>
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Date: Wed, 1 Dec 2021 02:53:00 +0000
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Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert
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"cpu/intel/model_1067x: enable PECI"
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This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
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Enabling PECI without microcode updates loaded causes the CPUID feature set
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to become corrupted. And one consequence is broken SpeedStep. At least, that's
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my understanding looking at Intel Errata. This revert is not a fix, because
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upstream is correct (upstream assumes microcode updates). We will simply
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maintain this revert patch in Libreboot, from now on.
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---
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src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
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1 file changed, 9 deletions(-)
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diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
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index 315e7c36fc..1423fd72bc 100644
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--- a/src/cpu/intel/model_1067x/model_1067x_init.c
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+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
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@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
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wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
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}
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-#define IA32_PECI_CTL 0x5a0
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-
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static void configure_misc(const int eist, const int tm2, const int emttm)
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{
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msr_t msr;
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@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
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msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
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wrmsr(IA32_MISC_ENABLE, msr);
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}
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-
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- /* Enable PECI
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- WARNING: due to Erratum AW67 described in Intel document #318733
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- the microcode must be updated before this MSR is written to. */
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- msr = rdmsr(IA32_PECI_CTL);
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- msr.lo |= 1;
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- wrmsr(IA32_PECI_CTL, msr);
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}
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#define PIC_SENS_CFG 0x1aa
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--
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2.39.2
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