include/rom.sh: use ccache when building coreboot

ccache now required, in build dependencies

Signed-off-by: Leah Rowe <leah@libreboot.org>

.gitignore

@@ -24,8 +24,6 @@
 /push
 /version
 /versiondate
-/.version
-/.versiondate
 /vendorfiles/
 *me.bin
 *sch5545ec.bin
@@ -36,11 +34,3 @@
 /todo.txt
 /lock
 /hash/
-/dump/
-/qrun*.sh
-*.tar.*
-/m
-/f
-/r
-/e
-/xbmkpath/

README.md

@@ -1,57 +1,123 @@
 Libreboot
 =========
 
-Documentation: [libreboot.org](https://libreboot.org)\
+Find libreboot documentation at <https://libreboot.org/>
-Support: [\#libreboot](https://web.libera.chat/#libreboot) on
-  [Libera](https://libera.chat/) IRC
 
-Libreboot provides 
+The `libreboot` project provides
-[libre](https://libreboot.org/freedom-status.html)
+[libre](https://libreboot.org/freedom-status.html) *boot
-boot firmware on
+firmware* that initializes the hardware (e.g. memory controller, CPU,
-[supported motherboards](https://libreboot.org/docs/install/#which-systems-are-supported-by-libreboot). It replaces proprietary vendor BIOS/UEFI implementations, by
+peripherals) on specific Intel/AMD x86 and ARM targets, which
-* Using coreboot to initialize the hardware (e.g. memory controller, CPU, etc.) while
+then starts a bootloader for your operating system. Linux/BSD are
-  minimizing unwanted functionality (e.g. backdoors such as the Intel Management Engine)
+well-supported. It replaces proprietary BIOS/UEFI firmware. Help is available
-* ... which runs a payload such as SeaBIOS, GRUB, or U-Boot
+via [\#libreboot IRC](https://web.libera.chat/#libreboot)
-* ... which loads your operating system's boot loader (BSD and Linux-based
+on [Libera](https://libera.chat/) IRC.
-  [systems](systems) are supported).
 
-Why use Libreboot, and what is coreboot?
+Why use Libreboot?
-----------------------------------------
+==================
 
-A lot of users who use libre operating systems still use proprietary boot
+Why should you use *libreboot*?
-firmware, which often contain backdoors and bugs, hampering
+----------------------------
-[user freedom](https://writefreesoftware.org) and
-[right to repair](https://www.eff.org/issues/right-to-repair).
 
-[coreboot](https://coreboot.org) provides libre boot firmware by initializing
+Libreboot gives you freedoms that you otherwise can't get with most other
-the hardware then running a payload. However, coreboot is notoriously difficult
+boot firmware. It's extremely powerful and configurable for many use cases.
-to configure and install for most non-technical users, requiring detailed
-technical knowledge of hardware.
 
-Libreboot solves this by being **a coreboot distribution** (in the same way
+You have rights. The right to privacy, freedom of thought, freedom of speech
-that Alpine Linux is a Linux distribution). It provides a fully automated build
+and the right to read. In this context, Libreboot gives you these rights.
-system that downloads and compiles pre-configured ROM images for supported
+Your freedom matters.
-motherboards, so end-users could easily fetch images to flash onto their
+[Right to repair](https://vid.puffyan.us/watch?v=Npd_xDuNi9k) matters.
-devices.
+Many people use proprietary (non-libre)
+boot firmware, even if they use [a libre OS](https://www.openbsd.org/).
+Proprietary firmware often contains backdoors (more info on the FAQ), and it
+and can be buggy. The libreboot project was founded in December 2013,
+with the express purpose of making coreboot firmware accessible for
+non-technical users.
 
-Libreboot also produces documentation aimed at non-technical users and
+The `libreboot` project uses [coreboot](https://www.coreboot.org/) for [hardware
-excellent user support via IRC.
+initialisation](https://doc.coreboot.org/getting_started/architecture.html).
+Coreboot is notoriously difficult to install for most non-technical users; it
+handles only basic initialization and jumps to a separate
+[payload](https://doc.coreboot.org/payloads.html) program (e.g.
+[GRUB](https://www.gnu.org/software/grub/),
+[Tianocore](https://www.tianocore.org/)), which must also be configured.
+*The libreboot software solves this problem*; it is a *coreboot distribution* with
+an automated build system (named *lbmk*) that builds complete *ROM images*, for
+more robust installation. Documentation is provided.
 
-Contribute
+How does Libreboot differ from coreboot?
-----------
+========================================
+
+In the same way that *Debian* is a GNU+Linux distribution, `libreboot` is
+a *coreboot distribution*. If you want to build a ROM image from scratch, you
+otherwise have to perform expert-level configuration of coreboot, GRUB and
+whatever other software you need, to prepare the ROM image. With *libreboot*,
+you can literally download from Git or a source archive, and run `make`, and it
+will build entire ROM images. An automated build system, named `lbmk`
+(Libreboot MaKe), builds these ROM images automatically, without any user input
+or intervention required. Configuration has already been performed in advance.
+
+If you were to build regular coreboot, without using libreboot's automated
+build system, it would require a lot more intervention and decent technical
+knowledge to produce a working configuration.
+
+Regular binary releases of `libreboot` provide these
+ROM images pre-compiled, and you can simply install them, with no special
+knowledge or skill except the ability to follow installation instructions
+and run commands BSD/Linux.
+
+Project goals
+=============
+
+-   *Support as much hardware as possible!* Libreboot aims to eventually
+    have *maintainers* for every board supported by coreboot, at every
+    point in time.
+-   *Make coreboot easy to use*. Coreboot is notoriously difficult
+    to install, due to an overall lack of user-focused documentation
+    and support. Most people will simply give up before attempting to
+    install coreboot. Libreboot's automated build system and user-friendly
+    installation instructions solves this problem.
+
+Libreboot attempts to bridge this divide by providing a build system
+automating much of the coreboot image creation and customization.
+Secondly, the project produces documentation aimed at non-technical users.
+Thirdly, the project attempts to provide excellent user support via IRC.
+
+Libreboot already comes with a payload (GRUB), flashprog and other
+needed parts. Everything is fully integrated, in a way where most of
+the complicated steps that are otherwise required, are instead done
+for the user in advance.
+
+You can download ROM images for your libreboot system and install
+them without having to build anything from source. If, however, you are
+interested in building your own image, the build system makes it relatively
+easy to do so.
+
+Not a coreboot fork!
+--------------------
+
+Libreboot is not a fork of coreboot. Every so often, the project
+re-bases on the latest version of coreboot, with the number of custom
+patches in use minimized. Tested, *stable* (static) releases are then provided
+in Libreboot, based on specific coreboot revisions.
+
+How to help
+===========
 
 You can check bugs listed on
 the [bug tracker](https://codeberg.org/libreboot/lbmk/issues).
 
-You may use Codeberg pull requests to send patches with bug fixes or other
+If you spot a bug and have a fix, the website has instructions for how to send
-improvements. This repository hosts the code for the main build system.
+patches, and you can also report it. Also, this entire website is
-The website lives in [a separate repository](https://codeberg.org/libreboot/lbwww).
+written in Markdown and hosted in a [separate
+repository](https://codeberg.org/libreboot/lbwww) where you can send patches.
 
-Development is also done on the IRC channel.
+Any and all development discussion and user support are all done on the IRC
+channel. More information is on <https://libreboot.org/contact.html>.
 
-License for this README
+LICENSE FOR THIS README
------------------------
+=======================
 
-It's just a README file. It is released under
+It's just a README file. This README file is released under the terms of the
-[Creative Commons Zero, version 1.0](https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt).
+Creative Commons Zero license, version 1.0 of the license, which you can
+read here:
 
+<https://creativecommons.org/publicdomain/zero/1.0/legalcode.txt>

build

@@ -0,0 +1,45 @@
+#!/usr/bin/env sh
+# SPDX-License-Identifier: GPL-3.0-or-later
+# Copyright (c) 2014-2015,2020-2024 Leah Rowe <leah@libreboot.org>
+# Copyright (c) 2015 Patrick "P. J." McDermott <pj@pehjota.net>
+# Copyright (c) 2015-2016 Klemens Nanni <contact@autoboot.org>
+# Copyright (c) 2022 Caleb La Grange <thonkpeasant@protonmail.com>
+
+set -u -e
+
+if [ "./${0##*/}" != "${0}" ] || [ ! -f "build" ] || [ -L "build" ]; then
+	printf "You must run this in the proper work directory.\n" 1>&2
+	exit 1
+fi
+
+. "include/lib.sh"
+. "include/vendor.sh"
+. "include/mrc.sh"
+
+err="fail"
+
+main()
+{
+	[ $# -lt 1 ] && $err "bad command"
+	spath="script/$1"; shift 1
+
+	[ "${spath#script/}" = "download" ] && vendor_download $@ && return 0
+	[ -f "$spath" ] || $err "bad command"
+	"$spath" $@ || $err "excmd: $spath $(echo "$@")"; set -u -e
+}
+
+fail()
+{
+	tmp_cleanup || printf "WARNING: can't rm tmpfiles: %s\n" "$TMPDIR" 1>&2
+	err_ "${1}"
+}
+
+tmp_cleanup()
+{
+	[ "$xbmk_parent" = "y" ] || return 0
+	[ "$TMPDIR" = "/tmp" ] || rm -Rf "$TMPDIR" || return 1
+	rm -f lock || return 1
+}
+
+main $@
+tmp_cleanup || err_ "can't rm TMPDIR upon non-zero exit: $TMPDIR"

config/coreboot/coreboot413/patches/0002-Fix-cbfstool-build-error-on-GCC-15-host-compiler.patch

@@ -1,33 +0,0 @@
-From 06e8d7a9db4efe1dc2b7e5865b801a5518b38fbd Mon Sep 17 00:00:00 2001
-From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
-Date: Tue, 29 Apr 2025 17:31:13 +0300
-Subject: [PATCH 1/1] Fix cbfstool build error on GCC 15 host compiler
-
-GCC 15 now considers the unterminated-string-initialization warning as
-part of -Werror by default. Coreboot compiles host utilities with the
-system compiler, which results in getting this error in some files.
-
-Mark a hexadecimal translation table in cbfstool code as "nonstring" to
-avoid the warning-turned-error.
-
-Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
----
- util/cbfstool/common.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
-index 539d0baccf..f6fe647503 100644
---- a/util/cbfstool/common.c
-+++ b/util/cbfstool/common.c
-@@ -188,7 +188,7 @@ uint64_t intfiletype(const char *name)
- 
- char *bintohex(uint8_t *data, size_t len)
- {
--	static const char translate[16] = "0123456789abcdef";
-+	static const char translate[16] __attribute__((__nonstring__)) = "0123456789abcdef";
- 
- 	char *result = malloc(len * 2 + 1);
- 	if (result == NULL)
--- 
-2.39.5
-

config/coreboot/coreboot413/target.cfg

@@ -1,4 +1,2 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
 tree="coreboot413"
 rev="5c186c6777c9438ff4681929c9c25c98dee28bef"

config/coreboot/d510mo/config/libgfxinit_txtmode

@@ -6,19 +6,19 @@
 #
 # General setup
 #
+CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
 # CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
@@ -37,6 +37,7 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_TSEG_STAGE_CACHE is not set
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
 
 #
 # Software Bill Of Materials (SBOM)
@@ -54,11 +55,10 @@ CONFIG_NO_STAGE_CACHE=y
 #
 # CONFIG_VENDOR_51NB is not set
 # CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
 # CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
 # CONFIG_VENDOR_BIOSTAR is not set
@@ -67,30 +67,23 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_IBM is not set
 CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_INVENTEC is not set
 # CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
 # CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
 # CONFIG_VENDOR_PACKARDBELL is not set
@@ -100,7 +93,6 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_PRODRIVE is not set
 # CONFIG_VENDOR_PROTECTLI is not set
 # CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
 # CONFIG_VENDOR_RAZER is not set
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
@@ -111,9 +103,7 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
 # CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
 CONFIG_BOARD_SPECIFIC_OPTIONS=y
 CONFIG_MAINBOARD_PART_NUMBER="D510MO"
 CONFIG_MAINBOARD_VERSION="1.0"
@@ -129,26 +119,22 @@ CONFIG_MAX_CPUS=4
 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_POST_DEVICE=y
 CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_DEVICETREE="devicetree.cb"
 # CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=256
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_DCACHE_RAM_BASE=0xfefc0000
 CONFIG_DCACHE_RAM_SIZE=0x8000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -164,6 +150,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_ADLRVP_P is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -171,9 +159,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
 # CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
-# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
 # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
-# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
 # CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
 
 #
@@ -192,7 +178,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_DQ67SW is not set
 # CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
 # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
-# CONFIG_BOARD_INTEL_FROST_CREEK is not set
 # CONFIG_BOARD_INTEL_GLKRVP is not set
 # CONFIG_BOARD_INTEL_HARCUVAR is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -208,11 +193,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
-
-#
-# Ptlrvp
-#
-# CONFIG_BOARD_INTEL_PTLRVP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
 # CONFIG_BOARD_INTEL_STRAGO is not set
@@ -220,19 +200,17 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
 CONFIG_PCIEXP_HOTPLUG_BUSES=32
 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+# CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -272,7 +250,6 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -281,13 +258,13 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
 CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
@@ -316,8 +293,6 @@ CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
 CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_CPU_PT_ROM_MAP_GB=4
 CONFIG_SMM_TSEG=y
 CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
 CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -372,8 +347,6 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y
 #
 # Embedded Controllers
 #
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-# CONFIG_GOOGLE_PVMFW_CBMEM is not set
 CONFIG_ARCH_X86=y
 CONFIG_ARCH_BOOTBLOCK_X86_32=y
 CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -397,10 +370,6 @@ CONFIG_HAVE_CF9_RESET=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
 # end of Chipset
 
 #
@@ -417,7 +386,6 @@ CONFIG_NO_EARLY_GFX_INIT=y
 # Display
 #
 CONFIG_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
 # end of Display
 
 CONFIG_PCI=y
@@ -451,7 +419,6 @@ CONFIG_USE_DDR2=y
 #
 CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
 # CONFIG_ELOG is not set
-# CONFIG_DRIVERS_OPTION_CFR is not set
 # CONFIG_SMMSTORE is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -469,7 +436,6 @@ CONFIG_SPI_FLASH_ISSI=y
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -491,8 +457,6 @@ CONFIG_DRIVERS_MC146818=y
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -545,6 +509,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -619,6 +584,7 @@ CONFIG_PAYLOAD_NONE=y
 #
 # General Debug Settings
 #
+# CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
@@ -632,13 +598,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y
 # end of Debugging
 
 CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

config/coreboot/d510mo/target.cfg

@@ -1,8 +1,6 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
 tree="default"
 xarch="i386-elf"
 payload_seabios="y"
 payload_memtest="y"
-release="n"
+
 build_depend="seabios/default memtest86plus"

config/coreboot/d510mo_16mb/config/libgfxinit_txtmode

@@ -6,19 +6,19 @@
 #
 # General setup
 #
+CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
 # CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
@@ -37,6 +37,7 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_TSEG_STAGE_CACHE is not set
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
 
 #
 # Software Bill Of Materials (SBOM)
@@ -54,11 +55,10 @@ CONFIG_NO_STAGE_CACHE=y
 #
 # CONFIG_VENDOR_51NB is not set
 # CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
 # CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
 # CONFIG_VENDOR_BIOSTAR is not set
@@ -67,30 +67,23 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_IBM is not set
 CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_INVENTEC is not set
 # CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
 # CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
 # CONFIG_VENDOR_PACKARDBELL is not set
@@ -100,7 +93,6 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_PRODRIVE is not set
 # CONFIG_VENDOR_PROTECTLI is not set
 # CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
 # CONFIG_VENDOR_RAZER is not set
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
@@ -111,9 +103,7 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
 # CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
 CONFIG_BOARD_SPECIFIC_OPTIONS=y
 CONFIG_MAINBOARD_PART_NUMBER="D510MO"
 CONFIG_MAINBOARD_VERSION="1.0"
@@ -129,26 +119,22 @@ CONFIG_MAX_CPUS=4
 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_POST_DEVICE=y
 CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_DEVICETREE="devicetree.cb"
 # CONFIG_VBOOT is not set
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=256
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_DCACHE_RAM_BASE=0xfefc0000
 CONFIG_DCACHE_RAM_SIZE=0x8000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -164,6 +150,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_ADLRVP_P is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -171,9 +159,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
 # CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
-# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
 # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
-# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
 # CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
 
 #
@@ -192,7 +178,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_DQ67SW is not set
 # CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
 # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
-# CONFIG_BOARD_INTEL_FROST_CREEK is not set
 # CONFIG_BOARD_INTEL_GLKRVP is not set
 # CONFIG_BOARD_INTEL_HARCUVAR is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -208,11 +193,6 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
-
-#
-# Ptlrvp
-#
-# CONFIG_BOARD_INTEL_PTLRVP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
 # CONFIG_BOARD_INTEL_STRAGO is not set
@@ -220,19 +200,17 @@ CONFIG_BOARD_INTEL_D510MO=y
 # CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
 CONFIG_PCIEXP_HOTPLUG_BUSES=32
 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+# CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -272,7 +250,6 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -281,13 +258,13 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
 CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
@@ -316,8 +293,6 @@ CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
 CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_CPU_PT_ROM_MAP_GB=4
 CONFIG_SMM_TSEG=y
 CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
 CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -372,8 +347,6 @@ CONFIG_SUPERIO_WINBOND_W83627THG=y
 #
 # Embedded Controllers
 #
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-# CONFIG_GOOGLE_PVMFW_CBMEM is not set
 CONFIG_ARCH_X86=y
 CONFIG_ARCH_BOOTBLOCK_X86_32=y
 CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -397,10 +370,6 @@ CONFIG_HAVE_CF9_RESET=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
 # end of Chipset
 
 #
@@ -417,7 +386,6 @@ CONFIG_NO_EARLY_GFX_INIT=y
 # Display
 #
 CONFIG_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
 # end of Display
 
 CONFIG_PCI=y
@@ -451,7 +419,6 @@ CONFIG_USE_DDR2=y
 #
 CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
 # CONFIG_ELOG is not set
-# CONFIG_DRIVERS_OPTION_CFR is not set
 # CONFIG_SMMSTORE is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -469,7 +436,6 @@ CONFIG_SPI_FLASH_ISSI=y
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -491,8 +457,6 @@ CONFIG_DRIVERS_MC146818=y
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -545,6 +509,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -619,6 +584,7 @@ CONFIG_PAYLOAD_NONE=y
 #
 # General Debug Settings
 #
+# CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
@@ -632,13 +598,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y
 # end of Debugging
 
 CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

config/coreboot/d510mo_16mb/target.cfg

@@ -1,8 +1,6 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
 tree="default"
 xarch="i386-elf"
 payload_seabios="y"
 payload_grub="y"
 payload_memtest="y"
-release="n"
+

config/coreboot/d945gclf_512kb/config/libgfxinit_txtmode

@@ -6,19 +6,19 @@
 #
 # General setup
 #
+CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
 # CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
@@ -37,6 +37,7 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
 CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
 
 #
 # Software Bill Of Materials (SBOM)
@@ -54,11 +55,10 @@ CONFIG_TSEG_STAGE_CACHE=y
 #
 # CONFIG_VENDOR_51NB is not set
 # CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
 # CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
 # CONFIG_VENDOR_BIOSTAR is not set
@@ -67,30 +67,23 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_IBM is not set
 CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_INVENTEC is not set
 # CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
 # CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
 # CONFIG_VENDOR_PACKARDBELL is not set
@@ -100,7 +93,6 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_PRODRIVE is not set
 # CONFIG_VENDOR_PROTECTLI is not set
 # CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
 # CONFIG_VENDOR_RAZER is not set
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
@@ -111,9 +103,7 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
 # CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
 CONFIG_BOARD_SPECIFIC_OPTIONS=y
 CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
 CONFIG_MAINBOARD_VERSION="1.0"
@@ -129,27 +119,23 @@ CONFIG_MAX_CPUS=4
 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_POST_DEVICE=y
 CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_DEVICETREE="devicetree.cb"
 # CONFIG_VBOOT is not set
 CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_DCACHE_RAM_BASE=0xfefc0000
 CONFIG_DCACHE_RAM_SIZE=0x8000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -165,6 +151,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_ADLRVP_P is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -172,9 +160,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
 # CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
-# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
 # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
-# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
 # CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
 
 #
@@ -193,7 +179,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_DQ67SW is not set
 # CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
 # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
-# CONFIG_BOARD_INTEL_FROST_CREEK is not set
 # CONFIG_BOARD_INTEL_GLKRVP is not set
 # CONFIG_BOARD_INTEL_HARCUVAR is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -209,11 +194,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
-
-#
-# Ptlrvp
-#
-# CONFIG_BOARD_INTEL_PTLRVP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
 # CONFIG_BOARD_INTEL_STRAGO is not set
@@ -221,17 +201,15 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
-CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+# CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
-CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_512=y
@@ -271,7 +249,6 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -280,13 +257,13 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
 CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
@@ -315,8 +292,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
 CONFIG_SETUP_XIP_CACHE=y
 CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_CPU_PT_ROM_MAP_GB=4
 CONFIG_SMM_TSEG=y
 CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
 CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -371,8 +346,6 @@ CONFIG_SUPERIO_SMSC_LPC47M15X=y
 #
 # Embedded Controllers
 #
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-# CONFIG_GOOGLE_PVMFW_CBMEM is not set
 CONFIG_ARCH_X86=y
 CONFIG_ARCH_BOOTBLOCK_X86_32=y
 CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -396,10 +369,6 @@ CONFIG_HAVE_CF9_RESET=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
 # end of Chipset
 
 #
@@ -416,7 +385,6 @@ CONFIG_NO_EARLY_GFX_INIT=y
 # Display
 #
 CONFIG_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
 # end of Display
 
 CONFIG_PCI=y
@@ -446,7 +414,6 @@ CONFIG_USE_DDR2=y
 #
 CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
 # CONFIG_ELOG is not set
-# CONFIG_DRIVERS_OPTION_CFR is not set
 # CONFIG_SMMSTORE is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -464,7 +431,6 @@ CONFIG_SPI_FLASH_ISSI=y
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -485,8 +451,6 @@ CONFIG_DRIVERS_MC146818=y
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -539,6 +503,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -617,6 +582,7 @@ CONFIG_PAYLOAD_NONE=y
 #
 # General Debug Settings
 #
+# CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
@@ -631,13 +597,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y
 # end of Debugging
 
 CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

config/coreboot/d945gclf_512kb/target.cfg

@@ -1,7 +1,5 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
 tree="default"
 xarch="i386-elf"
 payload_seabios="y"
-release="n"
+
 build_depend="seabios/default"

config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode

@@ -6,19 +6,19 @@
 #
 # General setup
 #
+CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
 # CONFIG_COMPILER_LLVM_CLANG is not set
+CONFIG_ARCH_SUPPORTS_CLANG=y
 # CONFIG_ANY_TOOLCHAIN is not set
 # CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
 # CONFIG_IWYU is not set
 # CONFIG_FMD_GENPARSER is not set
 # CONFIG_UTIL_GENPARSER is not set
 # CONFIG_OPTION_BACKEND_NONE is not set
 CONFIG_USE_OPTION_TABLE=y
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
 CONFIG_STATIC_OPTION_TABLE=y
 CONFIG_COMPRESS_RAMSTAGE_LZMA=y
 # CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
@@ -37,6 +37,7 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
 CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
 
 #
 # Software Bill Of Materials (SBOM)
@@ -54,11 +55,10 @@ CONFIG_TSEG_STAGE_CACHE=y
 #
 # CONFIG_VENDOR_51NB is not set
 # CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
 # CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
 # CONFIG_VENDOR_ASROCK is not set
 # CONFIG_VENDOR_ASUS is not set
 # CONFIG_VENDOR_BIOSTAR is not set
@@ -67,30 +67,23 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
 # CONFIG_VENDOR_HP is not set
 # CONFIG_VENDOR_IBASE is not set
 # CONFIG_VENDOR_IBM is not set
 CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_INVENTEC is not set
 # CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
 # CONFIG_VENDOR_LENOVO is not set
 # CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
 # CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
 # CONFIG_VENDOR_OCP is not set
 # CONFIG_VENDOR_OPENCELLULAR is not set
 # CONFIG_VENDOR_PACKARDBELL is not set
@@ -100,7 +93,6 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_PRODRIVE is not set
 # CONFIG_VENDOR_PROTECTLI is not set
 # CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
 # CONFIG_VENDOR_RAZER is not set
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
@@ -111,9 +103,7 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_SUPERMICRO is not set
 # CONFIG_VENDOR_SYSTEM76 is not set
 # CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
 # CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
 CONFIG_BOARD_SPECIFIC_OPTIONS=y
 CONFIG_MAINBOARD_PART_NUMBER="D945GCLF"
 CONFIG_MAINBOARD_VERSION="1.0"
@@ -129,27 +119,23 @@ CONFIG_MAX_CPUS=4
 # CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
 CONFIG_POST_DEVICE=y
 CONFIG_POST_IO=y
-CONFIG_OVERRIDE_DEVICETREE=""
 CONFIG_DEVICETREE="devicetree.cb"
 # CONFIG_VBOOT is not set
 CONFIG_IRQ_SLOT_COUNT=18
+CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
+CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
+CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
+CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
+CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
+CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
+# CONFIG_CONSOLE_POST is not set
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 CONFIG_DCACHE_RAM_BASE=0xfefc0000
 CONFIG_DCACHE_RAM_SIZE=0x8000
 CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
@@ -165,6 +151,8 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_ADLRVP_P is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -172,9 +160,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
 # CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
-# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
 # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
-# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
 # CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
 
 #
@@ -193,7 +179,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_DQ67SW is not set
 # CONFIG_BOARD_INTEL_ELKHARTLAKE_CRB is not set
 # CONFIG_BOARD_INTEL_EMERALDLAKE2 is not set
-# CONFIG_BOARD_INTEL_FROST_CREEK is not set
 # CONFIG_BOARD_INTEL_GLKRVP is not set
 # CONFIG_BOARD_INTEL_HARCUVAR is not set
 # CONFIG_BOARD_INTEL_JASPERLAKE_RVP is not set
@@ -209,11 +194,6 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_MTLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP4ES_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_MTLRVP_P_MCHP is not set
-
-#
-# Ptlrvp
-#
-# CONFIG_BOARD_INTEL_PTLRVP is not set
 # CONFIG_BOARD_INTEL_SKLSDLBRK is not set
 # CONFIG_BOARD_INTEL_SHADOWMOUNTAIN is not set
 # CONFIG_BOARD_INTEL_STRAGO is not set
@@ -221,17 +201,15 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_TGLRVP_UP4 is not set
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
-CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+# CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
-CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -271,7 +249,6 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -280,13 +257,13 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
 CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
 # CONFIG_PCIEXP_COMMON_CLOCK is not set
 CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
 CONFIG_FIXED_SMBUS_IO_BASE=0x400
 CONFIG_CBFS_CACHE_ALIGN=8
 CONFIG_INTEL_HAS_TOP_SWAP=y
@@ -315,8 +292,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
 CONFIG_SETUP_XIP_CACHE=y
 CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_CPU_PT_ROM_MAP_GB=4
 CONFIG_SMM_TSEG=y
 CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
 CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -371,8 +346,6 @@ CONFIG_SUPERIO_SMSC_LPC47M15X=y
 #
 # Embedded Controllers
 #
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-# CONFIG_GOOGLE_PVMFW_CBMEM is not set
 CONFIG_ARCH_X86=y
 CONFIG_ARCH_BOOTBLOCK_X86_32=y
 CONFIG_ARCH_VERSTAGE_X86_32=y
@@ -396,10 +369,6 @@ CONFIG_HAVE_CF9_RESET=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
 # end of Chipset
 
 #
@@ -416,7 +385,6 @@ CONFIG_NO_EARLY_GFX_INIT=y
 # Display
 #
 CONFIG_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
 # end of Display
 
 CONFIG_PCI=y
@@ -446,7 +414,6 @@ CONFIG_USE_DDR2=y
 #
 CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
 # CONFIG_ELOG is not set
-# CONFIG_DRIVERS_OPTION_CFR is not set
 # CONFIG_SMMSTORE is not set
 CONFIG_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
@@ -464,7 +431,6 @@ CONFIG_SPI_FLASH_ISSI=y
 CONFIG_HAVE_USBDEBUG=y
 # CONFIG_USBDEBUG is not set
 # CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
 # CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
 # CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
@@ -485,8 +451,6 @@ CONFIG_DRIVERS_MC146818=y
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -539,6 +503,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console
@@ -617,6 +582,7 @@ CONFIG_PAYLOAD_NONE=y
 #
 # General Debug Settings
 #
+# CONFIG_FATAL_ASSERTS is not set
 # CONFIG_DEBUG_CBFS is not set
 CONFIG_HAVE_DEBUG_RAM_SETUP=y
 # CONFIG_DEBUG_RAM_SETUP is not set
@@ -631,13 +597,6 @@ CONFIG_HAVE_DEBUG_SMBUS=y
 # end of Debugging
 
 CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
 CONFIG_WARNINGS_ARE_ERRORS=y
 CONFIG_MAX_REBOOT_CNT=3
 CONFIG_RELOCATABLE_MODULES=y

config/coreboot/d945gclf_8mb/target.cfg

@@ -1,8 +1,6 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
 tree="default"
 xarch="i386-elf"
 payload_seabios="y"
 payload_grub="y"
-release="n"
+
 build_depend="seabios/default grub/default"

config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch

@@ -0,0 +1,23 @@
+From 1195c954a3b6822e5e843067251c0c80c9520eab Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@retroboot.org>
+Date: Fri, 19 Mar 2021 05:54:58 +0000
+Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of
+ 8MiB
+
+---
+ src/mainboard/apple/macbook21/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
+index cf1bc4566e..dc0df3b6d6 100644
+--- a/src/mainboard/apple/macbook21/cmos.default
++++ b/src/mainboard/apple/macbook21/cmos.default
+@@ -5,4 +5,4 @@ boot_devices=''
+ boot_default=0x40
+ cmos_defaults_loaded=Yes
+ lpt=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+

config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch

@@ -1,7 +1,7 @@
-From bd959c38f6ee21db1ff8f4fbb0675e38bfbe1147 Mon Sep 17 00:00:00 2001
+From 50a52cea2b43e6e407b456c082e908c7d29e090b Mon Sep 17 00:00:00 2001
 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
 Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 01/37] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
 
 ---
  src/mainboard/apple/macbook21/Kconfig       |  1 +
@@ -10,10 +10,10 @@ Subject: [PATCH 01/37] add c3 and clockgen to apple/macbook21
  3 files changed, 20 insertions(+)
 
 diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
-index 330d8efae2..cf10343554 100644
+index 5f5ffde588..27377b737c 100644
 --- a/src/mainboard/apple/macbook21/Kconfig
 +++ b/src/mainboard/apple/macbook21/Kconfig
-@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
+@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
  	select HAVE_ACPI_TABLES
  	select HAVE_ACPI_RESUME
  	select I945_LVDS
@@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644
  	end
  end
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch

@@ -0,0 +1,23 @@
+From ca4cd66f411247395a323e5ea1abf09e83057827 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Sun, 3 Jan 2021 03:34:01 +0000
+Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default
+ (previously it was 8MiB)
+
+---
+ src/mainboard/lenovo/x60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
+index 5c3576d1f3..88170a1aab 100644
+--- a/src/mainboard/lenovo/x60/cmos.default
++++ b/src/mainboard/lenovo/x60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+

config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch

@@ -0,0 +1,22 @@
+From eca0f4a3a4d6907e92b948547a362ca0ac3fc382 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Mon, 22 Feb 2021 22:16:59 +0000
+Subject: [PATCH 04/30] lenovo/t60: make 64MiB VRAM the default in cmos.default
+
+---
+ src/mainboard/lenovo/t60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
+index af865f16da..7f03157df7 100644
+--- a/src/mainboard/lenovo/t60/cmos.default
++++ b/src/mainboard/lenovo/t60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+

config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch

@@ -0,0 +1,23 @@
+From 2eae87815675aebd472b6042777fe51279be4550 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:10:33 +0100
+Subject: [PATCH 05/30] lenovo/t400: set VRAM to 256MiB VRAM by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/lenovo/t400/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
+index a326e315b1..b907a3e2df 100644
+--- a/src/mainboard/lenovo/t400/cmos.default
++++ b/src/mainboard/lenovo/t400/cmos.default
+@@ -13,4 +13,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ hybrid_graphics_mode=Integrated Only
+-gfx_uma_size=32M
++gfx_uma_size=256M
+-- 
+2.39.2
+

config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch

@@ -0,0 +1,23 @@
+From f6b4913a5eca619b745d5ccea9af022a54fb185b Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:11:59 +0100
+Subject: [PATCH 06/30] lenovo/x200: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/lenovo/x200/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
+index bb4323836e..458b3f19c5 100644
+--- a/src/mainboard/lenovo/x200/cmos.default
++++ b/src/mainboard/lenovo/x200/cmos.default
+@@ -12,4 +12,4 @@ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=256M
+-- 
+2.39.2
+

config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch

@@ -0,0 +1,23 @@
+From a3a0969075163be413f968b03671aa5d8662672a Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:18:26 +0100
+Subject: [PATCH 07/30] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+index 8372032119..bedad54d2a 100644
+--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
++++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+-gfx_uma_size=64M
++gfx_uma_size=256M
+-- 
+2.39.2
+

config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch

@@ -0,0 +1,23 @@
+From 223ac17617b3a0c08925abbbe42d0d003e144a28 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:21:39 +0100
+Subject: [PATCH 08/30] acer/g43t-am3: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/acer/g43t-am3/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
+index 706f5dd551..e8b45ea22c 100644
+--- a/src/mainboard/acer/g43t-am3/cmos.default
++++ b/src/mainboard/acer/g43t-am3/cmos.default
+@@ -3,4 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=64M
++gfx_uma_size=256M
+-- 
+2.39.2
+

config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch

@@ -1,7 +1,7 @@
-From e5eab4c8043b89a325b4a28bf7da456d68475144 Mon Sep 17 00:00:00 2001
+From 80ebbfef42454ea0911e5fc3858103d905987ed8 Mon Sep 17 00:00:00 2001
 From: persmule <persmule@gmail.com>
 Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 02/37] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 09/30] lenovo/t400: Enable all SATA ports
 
 There are 2 SATA ports on the chassis of t400(s), but at least one dock for
 t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -30,5 +30,5 @@ index 259c3e1b21..3d007533a4 100644
  			register "sata_traffic_monitor"		= "0"
  
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch

@@ -0,0 +1,22 @@
+From 318a97c284f8d5030100476a32516ddc9e51603d Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 20 Dec 2021 01:29:31 +0000
+Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
+ default
+
+---
+ src/mainboard/lenovo/x230/cmos.default | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
+index 7314066c2b..2e315d4521 100644
+--- a/src/mainboard/lenovo/x230/cmos.default
++++ b/src/mainboard/lenovo/x230/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ usb_always_on=Disable
+ f1_to_f12_as_primary=Enable
+ me_state=Normal
++gfx_uma_size=224M
+-- 
+2.39.2
+

config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch

@@ -1,7 +1,7 @@
-From fd398cc10600cccce3dd4931651a5294ffebde9a Mon Sep 17 00:00:00 2001
+From 47afbe8b94edd1ff58c1daf0bda020e6afac35f4 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 03/37] lenovo/x230: set me_state=Disabled in cmos.default
+Subject: [PATCH 11/30] lenovo/x230: set me_state=Disabled in cmos.default
 
 I only recently found out about this. It's possible to use me_cleaner to
 do the same thing, but some people might just flash coreboot and not do
@@ -23,15 +23,16 @@ Date:   Thu Nov 21 21:47:31 2019 +0300
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
-index 732e214b32..8454f0eac0 100644
+index 2e315d4521..3585cbd58b 100644
 --- a/src/mainboard/lenovo/x230/cmos.default
 +++ b/src/mainboard/lenovo/x230/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,5 +15,5 @@ trackpoint=Enable
  backlight=Both
  usb_always_on=Disable
  f1_to_f12_as_primary=Enable
 -me_state=Normal
 +me_state=Disabled
+ gfx_uma_size=224M
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch

@@ -1,7 +1,7 @@
-From 74230d8123cb7c31afd084658720084b1a5ac5d9 Mon Sep 17 00:00:00 2001
+From 531ef34ece796f38cb8a13a54856e46e79842e29 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 04/37] set me_state=Disabled on all cmos.default files!
+Subject: [PATCH 12/30] set me_state=Disabled on all cmos.default files!
 
 yeah. why the hell isn't this the default
 
@@ -20,105 +20,103 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
  10 files changed, 10 insertions(+), 10 deletions(-)
 
 diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
-index be08e0a342..b8970efa46 100644
+index 681c40e78b..57cdcf9162 100644
 --- a/src/mainboard/lenovo/l520/cmos.default
 +++ b/src/mainboard/lenovo/l520/cmos.default
-@@ -16,4 +16,4 @@ sticky_fn=Disable
+@@ -14,4 +14,4 @@ sticky_fn=Disable
  trackpoint=Enable
  backlight=Both
  usb_always_on=Disable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
-index 6fd26c5fe3..27a62d07b3 100644
+index 8244071b8a..c011867916 100644
 --- a/src/mainboard/lenovo/t420/cmos.default
 +++ b/src/mainboard/lenovo/t420/cmos.default
-@@ -16,4 +16,4 @@ sticky_fn=Disable
+@@ -14,4 +14,4 @@ sticky_fn=Disable
  trackpoint=Enable
  hybrid_graphics_mode=Integrated Only
  usb_always_on=Disable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
-index 6fd26c5fe3..27a62d07b3 100644
+index 8244071b8a..c011867916 100644
 --- a/src/mainboard/lenovo/t420s/cmos.default
 +++ b/src/mainboard/lenovo/t420s/cmos.default
-@@ -16,4 +16,4 @@ sticky_fn=Disable
+@@ -14,4 +14,4 @@ sticky_fn=Disable
  trackpoint=Enable
  hybrid_graphics_mode=Integrated Only
  usb_always_on=Disable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
-index c896eadec1..6d1e172056 100644
+index 26795fe5cf..55e1e6c04e 100644
 --- a/src/mainboard/lenovo/t430/cmos.default
 +++ b/src/mainboard/lenovo/t430/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,4 +15,4 @@ trackpoint=Enable
  backlight=Both
  usb_always_on=Disable
  hybrid_graphics_mode=Integrated Only
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
-index 286fb0ae8c..5a05c73721 100644
+index 52dbf70377..b16800ca9e 100644
 --- a/src/mainboard/lenovo/t430s/cmos.default
 +++ b/src/mainboard/lenovo/t430s/cmos.default
-@@ -18,4 +18,4 @@ backlight=Both
+@@ -16,4 +16,4 @@ backlight=Both
  enable_dual_graphics=Disable
  usb_always_on=Disable
  f1_to_f12_as_primary=Enable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
-index 4857f92f67..ab1be1a678 100644
+index cf79b391e2..b66f7034dc 100644
 --- a/src/mainboard/lenovo/t520/cmos.default
 +++ b/src/mainboard/lenovo/t520/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,4 +15,4 @@ trackpoint=Enable
  backlight=Both
  hybrid_graphics_mode=Integrated Only
  usb_always_on=Disable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
-index 4857f92f67..ab1be1a678 100644
+index cf79b391e2..b66f7034dc 100644
 --- a/src/mainboard/lenovo/t530/cmos.default
 +++ b/src/mainboard/lenovo/t530/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,4 +15,4 @@ trackpoint=Enable
  backlight=Both
  hybrid_graphics_mode=Integrated Only
  usb_always_on=Disable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
-index ef706c1303..b318ab9772 100644
+index 6d1d57a795..52f303dfdb 100644
 --- a/src/mainboard/lenovo/x220/cmos.default
 +++ b/src/mainboard/lenovo/x220/cmos.default
-@@ -15,4 +15,4 @@ usb_always_on=Disable
+@@ -13,4 +13,4 @@ usb_always_on=Disable
  fn_ctrl_swap=Disable
  sticky_fn=Disable
  trackpoint=Enable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
-index d61046df6b..8c793fd1c3 100644
+index 62715bc6ba..129b5fd121 100644
 --- a/src/mainboard/protectli/vault_cml/cmos.default
 +++ b/src/mainboard/protectli/vault_cml/cmos.default
-@@ -2,4 +2,4 @@
+@@ -1,3 +1,3 @@
- 
  boot_option=Fallback
  debug_level=Debug
 -me_state=Enable
 +me_state=Disabled
 diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
-index d61046df6b..8c793fd1c3 100644
+index 62715bc6ba..129b5fd121 100644
 --- a/src/mainboard/system76/tgl-u/cmos.default
 +++ b/src/mainboard/system76/tgl-u/cmos.default
-@@ -2,4 +2,4 @@
+@@ -1,3 +1,3 @@
- 
  boot_option=Fallback
  debug_level=Debug
 -me_state=Enable
 +me_state=Disabled
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch

@@ -0,0 +1,203 @@
+From 158b79e6057e071d039619f617c112d31fb13f64 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 19 Feb 2023 18:21:43 +0000
+Subject: [PATCH 15/30] util/ifdtool: add --nuke flag (all 0xFF on region)
+
+When this option is used, the region's contents are overwritten
+with all ones (0xFF).
+
+Example:
+
+./ifdtool --nuke gbe coreboot.rom
+./ifdtool --nuke bios coreboot.com
+./ifdtool --nuke me coreboot.com
+
+Rebased since the last revision update in lbmk.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
+ 1 file changed, 81 insertions(+), 31 deletions(-)
+
+diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
+index 191b3216de..38132b4a28 100644
+--- a/util/ifdtool/ifdtool.c
++++ b/util/ifdtool/ifdtool.c
+@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
+ 	       "                                         tgl    - Tiger Lake\n"
+ 	       "                                         wbg    - Wellsburg\n"
+ 	       "   -S | --setpchstrap                    Write a PCH strap\n"
++	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
+ 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
+ 	       "   -v | --version:                       print the version\n"
+ 	       "   -h | --help:                          print this help\n\n"
+@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
+ 	       "\n");
+ }
+ 
++static int
++get_region_type_string(const char *region_type_string)
++{
++       if (!strcasecmp("Descriptor", region_type_string))
++               return 0;
++       else if (!strcasecmp("BIOS", region_type_string))
++               return 1;
++       else if (!strcasecmp("ME", region_type_string))
++               return 2;
++       else if (!strcasecmp("GbE", region_type_string))
++               return 3;
++       else if (!strcasecmp("Platform Data", region_type_string))
++               return 4;
++       else if (!strcasecmp("Device Exp1", region_type_string))
++               return 5;
++       else if (!strcasecmp("Secondary BIOS", region_type_string))
++               return 6;
++       else if (!strcasecmp("Reserved", region_type_string))
++               return 7;
++       else if (!strcasecmp("EC", region_type_string))
++               return 8;
++       else if (!strcasecmp("Device Exp2", region_type_string))
++               return 9;
++       else if (!strcasecmp("IE", region_type_string))
++               return 10;
++       else if (!strcasecmp("10GbE_0", region_type_string))
++               return 11;
++       else if (!strcasecmp("10GbE_1", region_type_string))
++               return 12;
++       else if (!strcasecmp("PTT", region_type_string))
++               return 15;
++       return -1;
++}
++
++static void
++nuke(const char *filename, char *image, int size, int region_type)
++{
++       int i;
++       struct region region;
++       const struct frba *frba = find_frba(image, size);
++       if (!frba)
++               exit(EXIT_FAILURE);
++
++       region = get_region(frba, region_type);
++       if (region.size > 0) {
++               for (i = region.base; i <= region.limit; i++) {
++                       if ((i + 1) > (size))
++                               break;
++                       image[i] = 0xFF;
++               }
++               write_image(filename, image, size);
++       }
++}
++
+ int main(int argc, char *argv[])
+ {
+ 	int opt, option_index = 0;
+@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
+ 	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
+ 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
+ 	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
++	int mode_nuke = 0;
+ 	int mode_gpr0_disable = 0;
+ 	char *region_type_string = NULL, *region_fname = NULL;
+ 	const char *layout_fname = NULL;
+@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
+ 		{"validate", 0, NULL, 't'},
+ 		{"setpchstrap", 1, NULL, 'S'},
+ 		{"newvalue", 1, NULL, 'V'},
++		{"nuke", 1, NULL, 'N'},
+ 		{0, 0, 0, 0}
+ 	};
+ 
+@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
+ 			region_fname++;
+ 			// Descriptor, BIOS, ME, GbE, Platform
+ 			// valid type?
+-			if (!strcasecmp("Descriptor", region_type_string))
+-				region_type = 0;
+-			else if (!strcasecmp("BIOS", region_type_string))
+-				region_type = 1;
+-			else if (!strcasecmp("ME", region_type_string))
+-				region_type = 2;
+-			else if (!strcasecmp("GbE", region_type_string))
+-				region_type = 3;
+-			else if (!strcasecmp("Platform Data", region_type_string))
+-				region_type = 4;
+-			else if (!strcasecmp("Device Exp1", region_type_string))
+-				region_type = 5;
+-			else if (!strcasecmp("Secondary BIOS", region_type_string))
+-				region_type = 6;
+-			else if (!strcasecmp("Reserved", region_type_string))
+-				region_type = 7;
+-			else if (!strcasecmp("EC", region_type_string))
+-				region_type = 8;
+-			else if (!strcasecmp("Device Exp2", region_type_string))
+-				region_type = 9;
+-			else if (!strcasecmp("IE", region_type_string))
+-				region_type = 10;
+-			else if (!strcasecmp("10GbE_0", region_type_string))
+-				region_type = 11;
+-			else if (!strcasecmp("10GbE_1", region_type_string))
+-				region_type = 12;
+-			else if (!strcasecmp("PTT", region_type_string))
+-				region_type = 15;
+-			if (region_type == -1) {
++                       if ((region_type =
++                           get_region_type_string(region_type_string)) == -1) {
+ 				fprintf(stderr, "No such region type: '%s'\n\n",
+ 					region_type_string);
+ 				fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
+ 		case 't':
+ 			mode_validate = 1;
+ 			break;
++               case 'N':
++                       region_type_string = strdup(optarg);
++                       if (!region_type_string) {
++                               fprintf(stderr, "No region specified\n");
++                               print_usage(argv[0]);
++                               exit(EXIT_FAILURE);
++                       }
++                       if ((region_type =
++                           get_region_type_string(region_type_string)) == -1) {
++                               fprintf(stderr, "No such region type: '%s'\n\n",
++                                       region_type_string);
++                               print_usage(argv[0]);
++                               exit(EXIT_FAILURE);
++                       }
++                       mode_nuke = 1;
++                       break;
+ 		case 'v':
+ 			print_version();
+ 			exit(EXIT_SUCCESS);
+@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
+ 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ 			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
+ 			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
+-			mode_gpr0_disable) > 1) {
++			mode_gpr0_disable + mode_nuke) > 1) {
+ 		fprintf(stderr, "You may not specify more than one mode.\n\n");
+ 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ 		exit(EXIT_FAILURE);
+@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
+ 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ 			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
+ 			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
+-			mode_validate + mode_gpr0_disable) == 0) {
++			mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
+ 		fprintf(stderr, "You need to specify a mode.\n\n");
+ 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ 		exit(EXIT_FAILURE);
+@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
+ 		write_image(new_filename, image, size);
+ 	}
+ 
++       if (mode_nuke) {
++               nuke(new_filename, image, size, region_type);
++       }
++
+ 	if (mode_altmedisable) {
+ 		struct fpsba *fpsba = find_fpsba(image, size);
+ 		struct fmsba *fmsba = find_fmsba(image, size);
+-- 
+2.39.2
+

config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch

@@ -0,0 +1,47 @@
+From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Wed, 1 Dec 2021 02:53:00 +0000
+Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert
+ "cpu/intel/model_1067x: enable PECI"
+
+This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
+
+Enabling PECI without microcode updates loaded causes the CPUID feature set
+to become corrupted. And one consequence is broken SpeedStep. At least, that's
+my understanding looking at Intel Errata. This revert is not a fix, because
+upstream is correct (upstream assumes microcode updates). We will simply
+maintain this revert patch in Libreboot, from now on.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 315e7c36fc..1423fd72bc 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
+ 	wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
+ }
+ 
+-#define IA32_PECI_CTL		0x5a0
+-
+ static void configure_misc(const int eist, const int tm2, const int emttm)
+ {
+ 	msr_t msr;
+@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
+ 		msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
+ 		wrmsr(IA32_MISC_ENABLE, msr);
+ 	}
+-
+-	/* Enable PECI
+-	   WARNING: due to Erratum AW67 described in Intel document #318733
+-	   the microcode must be updated before this MSR is written to. */
+-	msr = rdmsr(IA32_PECI_CTL);
+-	msr.lo |= 1;
+-	wrmsr(IA32_PECI_CTL, msr);
+ }
+ 
+ #define PIC_SENS_CFG	0x1aa
+-- 
+2.39.2
+

config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch

@@ -0,0 +1,173 @@
+From 8a94f38398b8fa554fa4ae53ecb88a372df634fd Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 17 Apr 2023 15:49:57 +0100
+Subject: [PATCH 17/30] GM45-type CPUs: don't enable alternative SMRR
+
+This reverts the changes in coreboot revision:
+df7aecd92643d207feaf7fd840f8835097346644
+
+While this fix is *technically correct*, the one in
+coreboot, it breaks rebooting as tested on several
+GM45 ThinkPads e.g. X200, T400, when microcode
+updates are not applied.
+
+Since November 2022, Libreboot includes microcode
+updates by default, but it tells users how to remove
+it from the ROM (with cbfstool) if they wish.
+
+Well, with Libreboot 20221214, 20230319 and 20230413,
+mitigations present in Libreboot 20220710 (which did
+not have microcode updates) do not exist.
+
+This patch, along with the other patch to remove PECI
+support (which breaks speedstep when microcode updates
+are not applied) have now been re-added to Libreboot.
+
+It is still best to use microcode updates by default.
+These patches in coreboot are not critically urgent,
+and you can use the machines with or without them,
+regardless of ucode.
+
+I'll probably re-write this and the other patch at
+some point, applying the change conditionally upon
+whether or not microcode is applied.
+
+Pragmatism is a good thing. I recommend it.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c |  4 +++
+ src/cpu/intel/model_1067x/mp_init.c          | 26 --------------------
+ src/cpu/intel/model_106cx/model_106cx_init.c |  4 +++
+ src/cpu/intel/model_6ex/model_6ex_init.c     |  4 +++
+ src/cpu/intel/model_6fx/model_6fx_init.c     |  4 +++
+ 5 files changed, 16 insertions(+), 26 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 1423fd72bc..d1f98ca43a 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -8,6 +8,7 @@
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
+ #include <cpu/intel/smm_reloc.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define MSR_BBL_CR_CTL3		0x11e
+ 
+@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states(quad);
+ 
+diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
+index bc53214310..72f40f6762 100644
+--- a/src/cpu/intel/model_1067x/mp_init.c
++++ b/src/cpu/intel/model_1067x/mp_init.c
+@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
+ 	smm_initialize();
+ }
+ 
+-#define SMRR_SUPPORTED (1 << 11)
+-
+ static void per_cpu_smm_trigger(void)
+ {
+-	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+-	if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
+-		set_feature_ctrl_vmx();
+-		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
+-		/* We don't care if the lock is already setting
+-		   as our smm relocation handler is able to handle
+-		   setups where SMRR is not enabled here. */
+-		if (ia32_ft_ctrl.lo & (1 << 0)) {
+-			/* IA32_FEATURE_CONTROL locked. If we set it again we
+-			   get an illegal instruction. */
+-			printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
+-			printk(BIOS_DEBUG, "SMRR status: %senabled\n",
+-			       ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
+-		} else {
+-			if (!CONFIG(SET_IA32_FC_LOCK_BIT))
+-				printk(BIOS_INFO,
+-				       "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
+-			ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
+-			wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
+-		}
+-	} else {
+-		set_vmx_and_lock();
+-	}
+-
+ 	/* Relocate the SMM handler. */
+ 	smm_relocate();
+ }
+diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
+index 05f5f327cc..0450c2ad83 100644
+--- a/src/cpu/intel/model_106cx/model_106cx_init.c
++++ b/src/cpu/intel/model_106cx/model_106cx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
+index 5bd1c32815..f3bb08cde3 100644
+--- a/src/cpu/intel/model_6ex/model_6ex_init.c
++++ b/src/cpu/intel/model_6ex/model_6ex_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
+index 535fb8fae7..f7b05facd2 100644
+--- a/src/cpu/intel/model_6fx/model_6fx_init.c
++++ b/src/cpu/intel/model_6fx/model_6fx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+-- 
+2.39.2
+

config/coreboot/default/patches/0017-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch

@@ -1,240 +0,0 @@
-From 6acc310c1d695d47c148296da9da189de21d58be Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 6 Aug 2024 00:50:24 +0100
-Subject: [PATCH 17/37] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
-
-We add this patch:
-
-commit commit_id_here
-Author: Angel Pons <th3fanbus@gmail.com>
-Date:   Mon May 10 22:40:59 2021 +0200
-
-    nb/intel/gm45: Make DDR2 raminit work
-
-This patch was original applied, in lbmk, only on coreboot/dell,
-separately from coreboot/default, which was wasteful because it
-meant having an entire coreboot tree just for a single board. We
-did this, because the DDR2 RCOMP fix happened to break DDR3 init
-on other boards.
-
-What *this* new patch does on top of Angel's patch, is make sure
-that their changes only apply to DDR2, while DDR3 behaviour remains
-unchanged. This means that the Dell Latitude E6400 can be supported
-in the main coreboot tree, within lbmk.
-
-Essentially, this patch restores the old behaviour, prior to applying
-Angel's patch, only when DDR3 memory is used.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/northbridge/intel/gm45/raminit.c          | 161 +++++++++---------
- .../intel/gm45/raminit_rcomp_calibration.c    |   9 +-
- 2 files changed, 88 insertions(+), 82 deletions(-)
-
-diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
-index df8f46fbbc..433db3a68c 100644
---- a/src/northbridge/intel/gm45/raminit.c
-+++ b/src/northbridge/intel/gm45/raminit.c
-@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
- 				reg = (reg & ~(0xf << 10)) | (2 << 10);
- 			else
- 				reg = (reg & ~(0xf << 10)) | (3 << 10);
--			reg = (reg & ~(0x7 <<  5)) | (2 << 5);
-+			if (spd_type == DDR2)
-+				reg = (reg & ~(0x7 <<  5)) | (2 << 5);
-+			else
-+				reg = (reg & ~(0x7 <<  5)) | (3 << 5);
- 		} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
- 			reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
- 			reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
-@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
- 		raminit_write_training(timings->mem_clock, dimms, s3resume);
- 	}
- 
--	/*
--	 * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
--	 * after receiver enable calibration, otherwise raminit sometimes
--	 * completes with non-working memory.
--	 */
--	mchbar_write32(0x0530, 0x06060005);
--	mchbar_write32(0x0680, 0x06060606);
--	mchbar_write32(0x0684, 0x08070606);
--	mchbar_write32(0x0688, 0x0e0e0c0a);
--	mchbar_write32(0x068c, 0x0e0e0e0e);
--	mchbar_write32(0x0698, 0x06060606);
--	mchbar_write32(0x069c, 0x08070606);
--	mchbar_write32(0x06a0, 0x0c0c0b0a);
--	mchbar_write32(0x06a4, 0x0c0c0c0c);
--
--	mchbar_write32(0x06c0, 0x02020202);
--	mchbar_write32(0x06c4, 0x03020202);
--	mchbar_write32(0x06c8, 0x04040403);
--	mchbar_write32(0x06cc, 0x04040404);
--	mchbar_write32(0x06d8, 0x02020202);
--	mchbar_write32(0x06dc, 0x03020202);
--	mchbar_write32(0x06e0, 0x04040403);
--	mchbar_write32(0x06e4, 0x04040404);
--
--	mchbar_write32(0x0700, 0x02020202);
--	mchbar_write32(0x0704, 0x03020202);
--	mchbar_write32(0x0708, 0x04040403);
--	mchbar_write32(0x070c, 0x04040404);
--	mchbar_write32(0x0718, 0x02020202);
--	mchbar_write32(0x071c, 0x03020202);
--	mchbar_write32(0x0720, 0x04040403);
--	mchbar_write32(0x0724, 0x04040404);
--
--	mchbar_write32(0x0740, 0x02020202);
--	mchbar_write32(0x0744, 0x03020202);
--	mchbar_write32(0x0748, 0x04040403);
--	mchbar_write32(0x074c, 0x04040404);
--	mchbar_write32(0x0758, 0x02020202);
--	mchbar_write32(0x075c, 0x03020202);
--	mchbar_write32(0x0760, 0x04040403);
--	mchbar_write32(0x0764, 0x04040404);
--
--	mchbar_write32(0x0780, 0x06060606);
--	mchbar_write32(0x0784, 0x09070606);
--	mchbar_write32(0x0788, 0x0e0e0c0b);
--	mchbar_write32(0x078c, 0x0e0e0e0e);
--	mchbar_write32(0x0798, 0x06060606);
--	mchbar_write32(0x079c, 0x09070606);
--	mchbar_write32(0x07a0, 0x0d0d0c0b);
--	mchbar_write32(0x07a4, 0x0d0d0d0d);
--
--	mchbar_write32(0x07c0, 0x06060606);
--	mchbar_write32(0x07c4, 0x09070606);
--	mchbar_write32(0x07c8, 0x0e0e0c0b);
--	mchbar_write32(0x07cc, 0x0e0e0e0e);
--	mchbar_write32(0x07d8, 0x06060606);
--	mchbar_write32(0x07dc, 0x09070606);
--	mchbar_write32(0x07e0, 0x0d0d0c0b);
--	mchbar_write32(0x07e4, 0x0d0d0d0d);
--
--	mchbar_write32(0x0840, 0x06060606);
--	mchbar_write32(0x0844, 0x08070606);
--	mchbar_write32(0x0848, 0x0e0e0c0a);
--	mchbar_write32(0x084c, 0x0e0e0e0e);
--	mchbar_write32(0x0858, 0x06060606);
--	mchbar_write32(0x085c, 0x08070606);
--	mchbar_write32(0x0860, 0x0c0c0b0a);
--	mchbar_write32(0x0864, 0x0c0c0c0c);
--
--	mchbar_write32(0x0880, 0x02020202);
--	mchbar_write32(0x0884, 0x03020202);
--	mchbar_write32(0x0888, 0x04040403);
--	mchbar_write32(0x088c, 0x04040404);
--	mchbar_write32(0x0898, 0x02020202);
--	mchbar_write32(0x089c, 0x03020202);
--	mchbar_write32(0x08a0, 0x04040403);
--	mchbar_write32(0x08a4, 0x04040404);
-+	if (sysinfo->spd_type == DDR2) {
-+		/*
-+		 * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
-+		 * after receiver enable calibration, otherwise raminit sometimes
-+		 * completes with non-working memory.
-+		 */
-+		mchbar_write32(0x0530, 0x06060005);
-+		mchbar_write32(0x0680, 0x06060606);
-+		mchbar_write32(0x0684, 0x08070606);
-+		mchbar_write32(0x0688, 0x0e0e0c0a);
-+		mchbar_write32(0x068c, 0x0e0e0e0e);
-+		mchbar_write32(0x0698, 0x06060606);
-+		mchbar_write32(0x069c, 0x08070606);
-+		mchbar_write32(0x06a0, 0x0c0c0b0a);
-+		mchbar_write32(0x06a4, 0x0c0c0c0c);
-+
-+		mchbar_write32(0x06c0, 0x02020202);
-+		mchbar_write32(0x06c4, 0x03020202);
-+		mchbar_write32(0x06c8, 0x04040403);
-+		mchbar_write32(0x06cc, 0x04040404);
-+		mchbar_write32(0x06d8, 0x02020202);
-+		mchbar_write32(0x06dc, 0x03020202);
-+		mchbar_write32(0x06e0, 0x04040403);
-+		mchbar_write32(0x06e4, 0x04040404);
-+
-+		mchbar_write32(0x0700, 0x02020202);
-+		mchbar_write32(0x0704, 0x03020202);
-+		mchbar_write32(0x0708, 0x04040403);
-+		mchbar_write32(0x070c, 0x04040404);
-+		mchbar_write32(0x0718, 0x02020202);
-+		mchbar_write32(0x071c, 0x03020202);
-+		mchbar_write32(0x0720, 0x04040403);
-+		mchbar_write32(0x0724, 0x04040404);
-+
-+		mchbar_write32(0x0740, 0x02020202);
-+		mchbar_write32(0x0744, 0x03020202);
-+		mchbar_write32(0x0748, 0x04040403);
-+		mchbar_write32(0x074c, 0x04040404);
-+		mchbar_write32(0x0758, 0x02020202);
-+		mchbar_write32(0x075c, 0x03020202);
-+		mchbar_write32(0x0760, 0x04040403);
-+		mchbar_write32(0x0764, 0x04040404);
-+
-+		mchbar_write32(0x0780, 0x06060606);
-+		mchbar_write32(0x0784, 0x09070606);
-+		mchbar_write32(0x0788, 0x0e0e0c0b);
-+		mchbar_write32(0x078c, 0x0e0e0e0e);
-+		mchbar_write32(0x0798, 0x06060606);
-+		mchbar_write32(0x079c, 0x09070606);
-+		mchbar_write32(0x07a0, 0x0d0d0c0b);
-+		mchbar_write32(0x07a4, 0x0d0d0d0d);
-+
-+		mchbar_write32(0x07c0, 0x06060606);
-+		mchbar_write32(0x07c4, 0x09070606);
-+		mchbar_write32(0x07c8, 0x0e0e0c0b);
-+		mchbar_write32(0x07cc, 0x0e0e0e0e);
-+		mchbar_write32(0x07d8, 0x06060606);
-+		mchbar_write32(0x07dc, 0x09070606);
-+		mchbar_write32(0x07e0, 0x0d0d0c0b);
-+		mchbar_write32(0x07e4, 0x0d0d0d0d);
-+
-+		mchbar_write32(0x0840, 0x06060606);
-+		mchbar_write32(0x0844, 0x08070606);
-+		mchbar_write32(0x0848, 0x0e0e0c0a);
-+		mchbar_write32(0x084c, 0x0e0e0e0e);
-+		mchbar_write32(0x0858, 0x06060606);
-+		mchbar_write32(0x085c, 0x08070606);
-+		mchbar_write32(0x0860, 0x0c0c0b0a);
-+		mchbar_write32(0x0864, 0x0c0c0c0c);
-+
-+		mchbar_write32(0x0880, 0x02020202);
-+		mchbar_write32(0x0884, 0x03020202);
-+		mchbar_write32(0x0888, 0x04040403);
-+		mchbar_write32(0x088c, 0x04040404);
-+		mchbar_write32(0x0898, 0x02020202);
-+		mchbar_write32(0x089c, 0x03020202);
-+		mchbar_write32(0x08a0, 0x04040403);
-+		mchbar_write32(0x08a4, 0x04040404);
-+	}
- 
- 	igd_compute_ggc(sysinfo);
- 
-diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-index b74765fd9c..5d4505e063 100644
---- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
- 		reg = mchbar_read32(0x518);
- 		lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
- 		lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
--		if (i == 1) {
-+		if ((i == 1) && (ddr_type == DDR2)) {
- 			magic_comp[0] = (reg >> 8) & 0x3f;
- 			magic_comp[1] = (reg >> 0) & 0x3f;
- 		}
-@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
- 		}
- 		mchbar += 0x0040;
- 	}
--
--	mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
--	mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
-+	if (ddr_type == DDR2) {
-+		mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
-+		mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
-+	}
- }
--- 
-2.39.5
-

config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch

@@ -1,7 +1,7 @@
-From 18069af7c0c6beedfadb615cca9127e82a0d8007 Mon Sep 17 00:00:00 2001
+From 2b899f40ce5d728faa7c1da23c3348435b7ac9cb Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 06/37] mb/dell/e6400: Enable 01.0 device in devicetree for
+Subject: [PATCH 18/30] mb/dell/e6400: Enable 01.0 device in devicetree for
  dGPU models
 
 Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
@@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644
  		device pci 02.1 on end # Display
  		device pci 03.0 on end # ME
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -1,7 +1,7 @@
-From 9563c107a4b40e66b610d7205a21590c7c181c78 Mon Sep 17 00:00:00 2001
+From 2ccd3e71730004c3ffbed178087cb778c170079e Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 07/37] Remove warning for coreboot images built without a
+Subject: [PATCH 19/30] Remove warning for coreboot images built without a
  payload
 
 I added this in upstream to prevent people from accidentally flashing
@@ -13,10 +13,10 @@ up. This has caused confusion and concern so just patch it out.
  1 file changed, 1 insertion(+), 12 deletions(-)
 
 diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
-index 5f988dac1b..516133880f 100644
+index a2336aa876..4f1692a873 100644
 --- a/payloads/Makefile.mk
 +++ b/payloads/Makefile.mk
-@@ -50,16 +50,5 @@ distclean-payloads:
+@@ -49,16 +49,5 @@ distclean-payloads:
  print-repo-info-payloads:
  	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
  
@@ -35,5 +35,5 @@ index 5f988dac1b..516133880f 100644
 -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
 +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0019-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch

@@ -1,52 +0,0 @@
-From a683dffd774dbbe25cc77c0f7d3853232c17c2bf Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Mon, 12 Aug 2024 02:15:24 +0100
-Subject: [PATCH 19/37] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
-
-set it to 96MHz. fixes the following build error when
-building for x4x boards e.g. gigabyte ga-g41m-es2l:
-
-hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config"
-make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1
-
-this error was introduced when merging coreboot/dell
-into coreboot/default in lbmk. nicholas chin's fix in lbmk
-was as follows:
-
-commit 8629873a6043067affc137be275b7aa69cb1f10c
-Author: Nicholas Chin <nic.c3.14@gmail.com>
-Date:   Mon May 20 10:46:25 2024 -0600
-
-    Fix E6400 display issue with 1440 x 900 panel
-
-this currently corresponds to the patch in lbmk,
-as of 12 august 2024:
-
-0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
-
-The assumption prior to Nicholas's fix was 96MHz, so set
-it accordingly on x4x northbridge.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/northbridge/intel/x4x/Kconfig | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
-index 097e11126c..6430319f6a 100644
---- a/src/northbridge/intel/x4x/Kconfig
-+++ b/src/northbridge/intel/x4x/Kconfig
-@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
- 
- if NORTHBRIDGE_INTEL_X4X
- 
-+config INTEL_GMA_DPLL_REF_FREQ
-+	int
-+	default 96000000
-+
- config CBFS_SIZE
- 	default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
- 
--- 
-2.39.5
-

config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch

@@ -0,0 +1,826 @@
+From a49df0307455d6d8b7a9efb9f4639b72be1b64d4 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sat, 19 Aug 2023 16:19:10 -0600
+Subject: [PATCH 20/30] mb/dell: Add Latitude E6430 (Ivy Bridge)
+
+Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. This
+is based on the autoport output with some manual tweaks. The flash is
+8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. It
+can also be internally flashed by sending a command to the EC, which
+causes the EC to pull the FDO pin low and the firmware to skip setting
+up any chipset based write protections [1]. The EC is the SMSC MEC5055,
+which seems to be compatible with the existing MEC5035 code.
+
+Working:
+- Libgfxinit
+- USB EHCI debug (left side usb port is HCD index 2, middle port on the
+  right side is HCD index 1)
+- Keyboard
+- Touchpad/trackpoint
+- ExpressCard
+- Audio
+- Ethernet
+- SD card reader
+- mPCIe WiFi
+- SeaBIOS 1.16.2
+- edk2 (MrChromebox' fork, uefipayload_202306)
+- Internal flashing using dell-flash-unlock
+
+Not working:
+- S3 suspend: Possibly EC related
+- Physical wireless switch - this triggers an SMI handler in the vendor
+  firmware which sends commands to the EC to enable/disable wireless
+  devices
+- Battery reporting - needs ACPI code for the EC
+- Brightness hotkeys - probably EC related
+
+Unknown/untested:
+- Dock
+- eSATA
+- TPM
+- dGPU on non-UMA model
+- Bluetooth module (not included on my system)
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6430/Kconfig           |  44 +++++
+ src/mainboard/dell/e6430/Kconfig.name      |   2 +
+ src/mainboard/dell/e6430/Makefile.inc      |   6 +
+ src/mainboard/dell/e6430/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e6430/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e6430/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e6430/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e6430/board_info.txt    |   6 +
+ src/mainboard/dell/e6430/cmos.default      |   9 +
+ src/mainboard/dell/e6430/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e6430/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e6430/devicetree.cb     |  70 ++++++++
+ src/mainboard/dell/e6430/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e6430/early_init.c      |  32 ++++
+ src/mainboard/dell/e6430/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e6430/gpio.c            | 192 +++++++++++++++++++++
+ src/mainboard/dell/e6430/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e6430/mainboard.c       |  21 +++
+ 18 files changed, 593 insertions(+)
+ create mode 100644 src/mainboard/dell/e6430/Kconfig
+ create mode 100644 src/mainboard/dell/e6430/Kconfig.name
+ create mode 100644 src/mainboard/dell/e6430/Makefile.inc
+ create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e6430/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e6430/board_info.txt
+ create mode 100644 src/mainboard/dell/e6430/cmos.default
+ create mode 100644 src/mainboard/dell/e6430/cmos.layout
+ create mode 100644 src/mainboard/dell/e6430/data.vbt
+ create mode 100644 src/mainboard/dell/e6430/devicetree.cb
+ create mode 100644 src/mainboard/dell/e6430/dsdt.asl
+ create mode 100644 src/mainboard/dell/e6430/early_init.c
+ create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e6430/gpio.c
+ create mode 100644 src/mainboard/dell/e6430/hda_verb.c
+ create mode 100644 src/mainboard/dell/e6430/mainboard.c
+
+diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
+new file mode 100644
+index 0000000000..e4c799803e
+--- /dev/null
++++ b/src/mainboard/dell/e6430/Kconfig
+@@ -0,0 +1,44 @@
++if BOARD_DELL_LATITUDE_E6430
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_12288
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_C216
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e6430"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E6430"
++
++config PS2K_EISAID
++	default "PNP0303"
++
++config PS2M_EISAID
++	default "PNP0F13"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0166"
++
++endif
+diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
+new file mode 100644
+index 0000000000..f866b03585
+--- /dev/null
++++ b/src/mainboard/dell/e6430/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E6430
++	bool "Latitude E6430"
+diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e6430/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt
+new file mode 100644
+index 0000000000..4601a4aaba
+--- /dev/null
++++ b/src/mainboard/dell/e6430/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2012
+diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
+new file mode 100644
+index 0000000000..2a5b30f2b7
+--- /dev/null
++++ b/src/mainboard/dell/e6430/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Normal
+diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e6430/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d
+GIT binary patch
+literal 6144
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+zcDa=Dn9^Q5?6k6+@y4UvvL3SDxKs*_^RS1n^H*!{fYZz^rPBX<FZ?DhF0v6`u90ic
+zA-5^lMeh7u!RIful;@oGY=u>mV(=eO(Cd-pvqPqVBRYz~7nA{nO7|Kv{w^;?LXb8F
+zZpK}KE=2zd4)ya^Le2qLGkt7<&s%Z6*Z`k>QW26OPC!Y8WP|wUI8Rlea-W3+oBO=P
+z7W#bDD=HM*SuTlWaHmLu%9{LBg+7xrp>y^-%p_)+nfZB&dFmKmF?B(+QtAm&-^!?J
+zr{Qq~n%$Y;KvfME{x@gVUB~vz&MBs@*k&z6fZ?Ic-b`*fKea1&Fkj=~!ZaqDU=O0r
+zYCPKK+S_PdhGTnR+18<YSJL`a_aBz`G`HE=V`WMDYTMfPLXT~qEK3^O(Kj!<{?_~E
+z{ct?ZJ!#R&H|_;QGyr;2JDTu4Urkt)#LW}e65l@e>g0GR_nHOE`gieuP-A>69j*W0
+z><PPSE2YwgK714^F4A&KOda3ou4=7C($dQbCP^XH=U4QVf8#_di>h~9>kwTD6>nL4
+zBSLUr+fHA!LgjQi9)hfgsV8iv!rHDd&4tY)VQn!?C&K1ZSo<JM{|K9!t~KbiT{nky
+zZA_;>>gEHwc1)*Nb@P2)`%EVorfFy!3`!X0sG<GVpasKx*wBs}^oC)6VrYLeNR61y
+z5$%!)?TnbWM6~@8x-Vir9?_nP(0dVcIij74P%LV0jB1@x<FeCA(YGuW>p0XopwxoS
+z0g?6TPW!DC<JKR&l%Knmp5z$x;*#X7@7xT>ql9>N1GN_$T-UVr&HErC5juykd~Sxy
+zq!PK|<^jJ^DuQ9)7p<sFLXlH${*3wEJ(L;FsEd;DgJ^{x0*)Wd^<xJzFfF2O*!)Bc
+zXtuum#xVj7H8Tulu*qs$*N1J-3WmV*15LsWQhjX<ZR^LFq0OSkUSwZ$8NS&h7|>t`
+z7FKz(x)t4R_RHf7I)6EA!d)M`R($wttvJgMee=p9zrFL_EL#DYA0wUzD?Ryj%h>lB
+ztg|e-5!;@t?uT+rR=1)e9yp?8gwNW88`Zyt!8rx=+B{i(4~DY`_-WO>sGeD;nsGcs
+z7h1ZN6srJX#Uke;d$JhpccQxNhw2Qz?Zw91`@8IHm-n!7{19~*_}LvecV2YZ7%!rJ
+zJQk}HtK2>CvB*WQ@u9a$Eq*zF2M=FM=@c`>dwDQ;<8EgZ-}dvt6=k(8Kqfa=nDJJ{
+z`Qth}G~%sFr{ZEKZb_%aySrD?sV%fJw`vFfda&ho1a>X)H^I}D_0A<|*{8kwEBU8>
+qS<b6g={WLAp3+&R^8(yo-t$_!=7BX2ta)I~18W{w^T5By1OEis_@J`@
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
+new file mode 100644
+index 0000000000..054b01c5ac
+--- /dev/null
++++ b/src/mainboard/dell/e6430/devicetree.cb
+@@ -0,0 +1,70 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00001312"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x0534 inherit
++
++		device ref host_bridge on end
++		device ref peg10 off end
++		device ref igd on end
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x005c0921"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x33"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++			register "superspeed_capable_ports" = "0x0000000f"
++			register "xhci_overcurrent_mapping" = "0x00000c03"
++			register "xhci_switchable_ports" = "0x0000000f"
++
++			device ref xhci		on end
++			device ref mei1		on end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	on end
++			device ref gbe		on end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end # WWAN Slot
++			device ref pcie_rp2	on end # SLAN Slot
++			device ref pcie_rp3	on end # ExpressCard
++			device ref pcie_rp4	on end # E-Module (optical bay)
++			device ref pcie_rp5	on end # Extra Half Mini PCIe slot
++			device ref pcie_rp6	on end # SD/MMC Card Reader
++			device ref pcie_rp7	off end
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1	on end
++			device ref smbus	on end
++			device ref sata2	off end
++			device ref thermal	off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e6430/dsdt.asl b/src/mainboard/dell/e6430/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e6430/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
+new file mode 100644
+index 0000000000..d882c3d78b
+--- /dev/null
++++ b/src/mainboard/dell/e6430/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 0, 2 },
++	{ 1, 1, 2 },
++	{ 1, 1, 3 },
++	{ 1, 1, 3 },
++	{ 1, 1, 4 },
++	{ 1, 1, 4 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 2, 6 },
++	{ 1, 2, 6 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
+new file mode 100644
+index 0000000000..1310830c8e
+--- /dev/null
++++ b/src/mainboard/dell/e6430/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, --mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c
+new file mode 100644
+index 0000000000..777570765a
+--- /dev/null
++++ b/src/mainboard/dell/e6430/gpio.c
+@@ -0,0 +1,192 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_GPIO,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_NATIVE,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio1 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_OUTPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio28 = GPIO_LEVEL_LOW,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++	.gpio30 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio13 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_NATIVE,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_INPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_NATIVE,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c
+new file mode 100644
+index 0000000000..56ada95c58
+--- /dev/null
++++ b/src/mainboard/dell/e6430/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76df,	/* Codec Vendor / Device ID: IDT */
++	0x10280534,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x10280534),
++	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862806,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e6430/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.39.2
+

config/coreboot/default/patches/0020-mb-dell-Convert-E6400-into-a-variant.patch

@@ -1,243 +0,0 @@
-From a48ba23bb4a24730fa49b5a10b56c9de873dea8a Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Thu, 26 Sep 2024 19:48:26 -0600
-Subject: [PATCH 20/37] mb/dell: Convert E6400 into a variant
-
-All the GM45 Dell Latitudes should be nearly identical, so convert the
-E6400 port into a variant so that future ports for the other systems can
-share code with each other.
-
-Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/e6400/Makefile.mk          |  10 --------
- .../dell/{e6400 => gm45_latitude}/Kconfig     |  22 +++++++++++++-----
- .../{e6400 => gm45_latitude}/Kconfig.name     |   0
- src/mainboard/dell/gm45_latitude/Makefile.mk  |  11 +++++++++
- .../dell/{e6400 => gm45_latitude}/acpi/ec.asl |   0
- .../acpi/ich9_pci_irqs.asl                    |   0
- .../{e6400 => gm45_latitude}/acpi/superio.asl |   0
- .../dell/{e6400 => gm45_latitude}/blc.c       |   0
- .../{e6400 => gm45_latitude}/board_info.txt   |   0
- .../dell/{e6400 => gm45_latitude}/bootblock.c |   0
- .../{e6400 => gm45_latitude}/cmos.default     |   0
- .../dell/{e6400 => gm45_latitude}/cmos.layout |   0
- .../dell/{e6400 => gm45_latitude}/cstates.c   |   0
- .../{e6400 => gm45_latitude}/devicetree.cb    |   1 -
- .../dell/{e6400 => gm45_latitude}/dsdt.asl    |   0
- .../dell/{e6400 => gm45_latitude}/mainboard.c |   0
- .../dell/{e6400 => gm45_latitude}/romstage.c  |   0
- .../variants}/e6400/data.vbt                  | Bin
- .../variants}/e6400/gma-mainboard.ads         |   0
- .../{ => gm45_latitude/variants}/e6400/gpio.c |   0
- .../variants}/e6400/hda_verb.c                |   0
- .../variants/e6400/overridetree.cb            |   7 ++++++
- 22 files changed, 34 insertions(+), 17 deletions(-)
- delete mode 100644 src/mainboard/dell/e6400/Makefile.mk
- rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig (64%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig.name (100%)
- create mode 100644 src/mainboard/dell/gm45_latitude/Makefile.mk
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ec.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ich9_pci_irqs.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/superio.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/blc.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/board_info.txt (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/bootblock.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.default (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.layout (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cstates.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/devicetree.cb (98%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/dsdt.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/mainboard.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/romstage.c (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/data.vbt (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gma-mainboard.ads (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gpio.c (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/hda_verb.c (100%)
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-
-diff --git a/src/mainboard/dell/e6400/Makefile.mk b/src/mainboard/dell/e6400/Makefile.mk
-deleted file mode 100644
-index ca3a82db48..0000000000
---- a/src/mainboard/dell/e6400/Makefile.mk
-+++ /dev/null
-@@ -1,10 +0,0 @@
--## SPDX-License-Identifier: GPL-2.0-only
--
--bootblock-y += bootblock.c
--
--romstage-y += gpio.c
--
--ramstage-y += cstates.c
--ramstage-y += blc.c
--
--ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
-similarity index 64%
-rename from src/mainboard/dell/e6400/Kconfig
-rename to src/mainboard/dell/gm45_latitude/Kconfig
-index 6fe1b1c456..ba76fb6e8c 100644
---- a/src/mainboard/dell/e6400/Kconfig
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig
-@@ -1,9 +1,7 @@
- ## SPDX-License-Identifier: GPL-2.0-only
- 
--if BOARD_DELL_E6400
--
--config BOARD_SPECIFIC_OPTIONS
--	def_bool y
-+config BOARD_DELL_GM45_LATITUDE_COMMON
-+	def_bool n
- 	select SYSTEM_TYPE_LAPTOP
- 	select CPU_INTEL_SOCKET_P
- 	select NORTHBRIDGE_INTEL_GM45
-@@ -19,19 +17,31 @@ config BOARD_SPECIFIC_OPTIONS
- 	select INTEL_GMA_HAVE_VBT
- 	select EC_DELL_MEC5035
- 
-+
-+config BOARD_DELL_E6400
-+	select BOARD_DELL_GM45_LATITUDE_COMMON
-+
-+if BOARD_DELL_GM45_LATITUDE_COMMON
-+
- config INTEL_GMA_DPLL_REF_FREQ
- 	default 100000000
- 
- config MAINBOARD_DIR
--	default "dell/e6400"
-+	default "dell/gm45_latitude"
- 
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E6400" if BOARD_DELL_E6400
- 
-+config OVERRIDE_DEVICETREE
-+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-+
-+config VARIANT_DIR
-+	default "e6400" if BOARD_DELL_E6400
-+
- config USBDEBUG_HCD_INDEX
- 	default 1
- 
- config CBFS_SIZE
- 	default 0x1A0000
- 
--endif # BOARD_DELL_E6400
-+endif # BOARD_DELL_GM45_LATITUDE_COMMON
-diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
-similarity index 100%
-rename from src/mainboard/dell/e6400/Kconfig.name
-rename to src/mainboard/dell/gm45_latitude/Kconfig.name
-diff --git a/src/mainboard/dell/gm45_latitude/Makefile.mk b/src/mainboard/dell/gm45_latitude/Makefile.mk
-new file mode 100644
-index 0000000000..5295d5be22
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/Makefile.mk
-@@ -0,0 +1,11 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+bootblock-y += bootblock.c
-+
-+romstage-y += variants/$(VARIANT_DIR)/gpio.c
-+
-+ramstage-y += cstates.c
-+ramstage-y += blc.c
-+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
-+
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/gm45_latitude/acpi/ec.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/ec.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/ec.asl
-diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
-diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/gm45_latitude/acpi/superio.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/superio.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/superio.asl
-diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/gm45_latitude/blc.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/blc.c
-rename to src/mainboard/dell/gm45_latitude/blc.c
-diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/gm45_latitude/board_info.txt
-similarity index 100%
-rename from src/mainboard/dell/e6400/board_info.txt
-rename to src/mainboard/dell/gm45_latitude/board_info.txt
-diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/gm45_latitude/bootblock.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/bootblock.c
-rename to src/mainboard/dell/gm45_latitude/bootblock.c
-diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/gm45_latitude/cmos.default
-similarity index 100%
-rename from src/mainboard/dell/e6400/cmos.default
-rename to src/mainboard/dell/gm45_latitude/cmos.default
-diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/gm45_latitude/cmos.layout
-similarity index 100%
-rename from src/mainboard/dell/e6400/cmos.layout
-rename to src/mainboard/dell/gm45_latitude/cmos.layout
-diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/gm45_latitude/cstates.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/cstates.c
-rename to src/mainboard/dell/gm45_latitude/cstates.c
-diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
-similarity index 98%
-rename from src/mainboard/dell/e6400/devicetree.cb
-rename to src/mainboard/dell/gm45_latitude/devicetree.cb
-index e9f3915d17..76dae87153 100644
---- a/src/mainboard/dell/e6400/devicetree.cb
-+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
-@@ -15,7 +15,6 @@ chip northbridge/intel/gm45
- 	register "pci_mmio_size" = "2048"
- 
- 	device domain 0 on
--		subsystemid 0x1028 0x0233 inherit
- 		ops gm45_pci_domain_ops
- 
- 		device pci 00.0 on end # host bridge
-diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/gm45_latitude/dsdt.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/dsdt.asl
-rename to src/mainboard/dell/gm45_latitude/dsdt.asl
-diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/gm45_latitude/mainboard.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/mainboard.c
-rename to src/mainboard/dell/gm45_latitude/mainboard.c
-diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/gm45_latitude/romstage.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/romstage.c
-rename to src/mainboard/dell/gm45_latitude/romstage.c
-diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
-similarity index 100%
-rename from src/mainboard/dell/e6400/data.vbt
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
-diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
-similarity index 100%
-rename from src/mainboard/dell/e6400/gma-mainboard.ads
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/gpio.c
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
-diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/hda_verb.c
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-new file mode 100644
-index 0000000000..acc34a2252
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-@@ -0,0 +1,7 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/gm45
-+	device domain 0 on
-+		subsystemid 0x1028 0x0233 inherit
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch

@@ -1,7 +1,7 @@
-From 7f650a19d30fe6157b150c5248d6086007323d72 Mon Sep 17 00:00:00 2001
+From 70262a5f4bf801814d68f8778ea89b5cd8ef8f9a Mon Sep 17 00:00:00 2001
 From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
 Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH 08/37] HACK: Disable coreboot related BL31 features
+Subject: [PATCH 21/30] HACK: Disable coreboot related BL31 features
 
 I don't know why, but removing this BL31 make argument lets gru-kevin
 power off properly when shut down from Linux. Needs investigation.
@@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation.
  1 file changed, 3 deletions(-)
 
 diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
-index f54c6d22fc..b075abfd42 100644
+index 538d254ace..18e451d63c 100644
 --- a/src/arch/arm64/Makefile.mk
 +++ b/src/arch/arm64/Makefile.mk
-@@ -162,9 +162,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
+@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
  # Always enable crash reporting, even on a release build
  BL31_MAKEARGS += CRASH_REPORTING=1
  
@@ -24,5 +24,5 @@ index f54c6d22fc..b075abfd42 100644
  BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
  
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0021-mb-dell-gm45_latitudes-Add-E4300-variant.patch

@@ -1,332 +0,0 @@
-From b87e6774f0407ea48610c83ea54ab6a4b4a78a24 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Thu, 26 Sep 2024 19:51:25 -0600
-Subject: [PATCH 21/37] mb/dell/gm45_latitudes: Add E4300 variant
-
-Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/gm45_latitude/Kconfig      |   5 +
- src/mainboard/dell/gm45_latitude/Kconfig.name |   3 +
- .../gm45_latitude/variants/e4300/data.vbt     | Bin 0 -> 3881 bytes
- .../variants/e4300/gma-mainboard.ads          |  17 +++
- .../dell/gm45_latitude/variants/e4300/gpio.c  | 138 ++++++++++++++++++
- .../gm45_latitude/variants/e4300/hda_verb.c   |  37 +++++
- .../variants/e4300/overridetree.cb            |  10 ++
- 7 files changed, 210 insertions(+)
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-
-diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
-index ba76fb6e8c..144f9bcdf0 100644
---- a/src/mainboard/dell/gm45_latitude/Kconfig
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig
-@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
- config BOARD_DELL_E6400
- 	select BOARD_DELL_GM45_LATITUDE_COMMON
- 
-+config BOARD_DELL_E4300
-+	select BOARD_DELL_GM45_LATITUDE_COMMON
-+
- if BOARD_DELL_GM45_LATITUDE_COMMON
- 
- config INTEL_GMA_DPLL_REF_FREQ
-@@ -31,12 +34,14 @@ config MAINBOARD_DIR
- 
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E6400" if BOARD_DELL_E6400
-+	default "Latitude E4300" if BOARD_DELL_E4300
- 
- config OVERRIDE_DEVICETREE
- 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
- 
- config VARIANT_DIR
- 	default "e6400" if BOARD_DELL_E6400
-+	default "e4300" if BOARD_DELL_E4300
- 
- config USBDEBUG_HCD_INDEX
- 	default 1
-diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
-index aefe777109..4dc95f46be 100644
---- a/src/mainboard/dell/gm45_latitude/Kconfig.name
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig.name
-@@ -1,4 +1,7 @@
- ## SPDX-License-Identifier: GPL-2.0-only
- 
-+config BOARD_DELL_E4300
-+	bool "Latitude E4300"
-+
- config BOARD_DELL_E6400
- 	bool "Latitude E6400"
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3
-GIT binary patch
-literal 3881
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-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
-new file mode 100644
-index 0000000000..89b81b3d69
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
-@@ -0,0 +1,17 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (DP2, -- dock DP
-+      Analog, -- mainboard VGA
-+      LVDS,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
-new file mode 100644
-index 0000000000..b50f8da0b5
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
-@@ -0,0 +1,138 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0  = GPIO_MODE_NATIVE,
-+	.gpio1  = GPIO_MODE_GPIO,
-+	.gpio2  = GPIO_MODE_GPIO,
-+	.gpio3  = GPIO_MODE_GPIO,
-+	.gpio4  = GPIO_MODE_GPIO,
-+	.gpio5  = GPIO_MODE_GPIO,
-+	.gpio6  = GPIO_MODE_GPIO,
-+	.gpio7  = GPIO_MODE_GPIO,
-+	.gpio8  = GPIO_MODE_GPIO,
-+	.gpio9  = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_NATIVE,
-+	.gpio16 = GPIO_MODE_NATIVE,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_GPIO,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_GPIO,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_NATIVE,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio1  = GPIO_DIR_INPUT,
-+	.gpio2  = GPIO_DIR_INPUT,
-+	.gpio3  = GPIO_DIR_INPUT,
-+	.gpio4  = GPIO_DIR_INPUT,
-+	.gpio5  = GPIO_DIR_INPUT,
-+	.gpio6  = GPIO_DIR_INPUT,
-+	.gpio7  = GPIO_DIR_INPUT,
-+	.gpio8  = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio18 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio20 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio1  = GPIO_INVERT,
-+	.gpio7  = GPIO_INVERT,
-+	.gpio8  = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_NATIVE,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_NATIVE,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_GPIO,
-+	.gpio54 = GPIO_MODE_NATIVE,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio53 = GPIO_DIR_INPUT,
-+	.gpio56 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode      = &pch_gpio_set1_mode,
-+		.direction = &pch_gpio_set1_direction,
-+		.level     = &pch_gpio_set1_level,
-+		.blink     = &pch_gpio_set1_blink,
-+		.invert    = &pch_gpio_set1_invert,
-+	},
-+	.set2 = {
-+		.mode      = &pch_gpio_set2_mode,
-+		.direction = &pch_gpio_set2_direction,
-+		.level     = &pch_gpio_set2_level,
-+	},
-+};
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
-new file mode 100644
-index 0000000000..a9948a93dd
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
-@@ -0,0 +1,37 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	/* coreboot specific header */
-+	0x111d76b2, /* IDT 92HD71B7X */
-+	0x1028024d, /* Subsystem ID */
-+	13,	    /* Number of entries */
-+
-+	/* Pin Widget Verb Table */
-+
-+	AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
-+	AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
-+	AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
-+	AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
-+	AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
-+	AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
-+};
-+
-+const u32 pc_beep_verbs[] = {
-+	0x00170500, /* power up codec */
-+	0x00d70500, /* power up speakers */
-+	0x00d70102, /* select mixer (input 0x2) for speakers */
-+	0x00d70740, /* enable speakers output */
-+	0x02770720, /* enable beep input */
-+	0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
-+	0x00d37000, /* unmute speakers */
-+};
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-new file mode 100644
-index 0000000000..20dfa245fb
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-@@ -0,0 +1,10 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/gm45
-+	device domain 0 on
-+		subsystemid 0x1028 0x024d inherit
-+		chip southbridge/intel/i82801ix
-+			device pci 1c.2 off end # PCIe Port #3
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch

@@ -0,0 +1,39 @@
+From 536a1dd349f590cbefccac7e7364cafcdaec9600 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 22 Oct 2023 15:02:25 +0100
+Subject: [PATCH 22/30] don't use github for the acpica download
+
+i have the tarball from a previous download, and i placed
+it on libreboot rsync, which then got mirrored to princeton.
+
+today, github's ssl cert was b0rking the hell out and i really
+really wanted to finish a build, and didn't want to wait for
+github to fix their httpd.
+
+so i'm now hosting this specific acpica tarball on rsync.
+
+this patch makes that URL be used, instead of the github one.
+
+that's the 2nd time i've had to patch coreboot's acpica download!
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 23a5caf2bb..36565a906c 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+ GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+ BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
++IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+ CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/default/patches/0022-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch

@@ -1,70 +0,0 @@
-From 0bc9ca409793836dcdb386db97b7a9464d92a973 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 3 May 2024 16:31:12 -0600
-Subject: [PATCH 22/37] mb/dell: Add S3 SMI handler for Dell Latitudes
-
-Integrate the previously added mec5035_smi_sleep() function into
-mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
-The E6400 does not require the EC command to sucessfully suspend and
-resume from S3, though sending it does enable the breathing effect on
-the power LED while in S3. Without it, all LEDs turn off during S3.
-
-Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/e7240/smihandler.c            | 9 +++++++++
- src/mainboard/dell/gm45_latitude/smihandler.c    | 9 +++++++++
- src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
- 3 files changed, 27 insertions(+)
- create mode 100644 src/mainboard/dell/e7240/smihandler.c
- create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
-
-diff --git a/src/mainboard/dell/e7240/smihandler.c b/src/mainboard/dell/e7240/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
---- /dev/null
-+++ b/src/mainboard/dell/e7240/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_smi_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_smi_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_smi_sleep(slp_typ);
-+}
--- 
-2.39.5
-

config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch

@@ -0,0 +1,142 @@
+From ad812d008d570c1655bff13a9026f39a9efdcbc9 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Tue, 31 Oct 2023 18:24:39 +0000
+Subject: [PATCH 23/30] crank up vram allocation on more intel boards
+
+these were added to libreboot, and it's a policy of
+libreboot to max out the vram settings. this was
+overlooked, in prior revisions and releases.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/dell/e6400/cmos.default                | 2 +-
+ src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
+ src/mainboard/hp/compaq_8200_elite_sff/cmos.default  | 2 +-
+ src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
+ src/mainboard/hp/snb_ivb_laptops/cmos.default        | 1 +
+ src/mainboard/lenovo/t420/cmos.default               | 1 +
+ src/mainboard/lenovo/t420s/cmos.default              | 1 +
+ src/mainboard/lenovo/t430/cmos.default               | 1 +
+ src/mainboard/lenovo/t520/cmos.default               | 1 +
+ src/mainboard/lenovo/t530/cmos.default               | 1 +
+ src/mainboard/lenovo/x201/cmos.default               | 1 +
+ src/mainboard/lenovo/x220/cmos.default               | 1 +
+ 12 files changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
+index eeb6f47364..25dfa38cb5 100644
+--- a/src/mainboard/dell/e6400/cmos.default
++++ b/src/mainboard/dell/e6400/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Disable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=256M
+diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
+index ccc7e64625..7c97b84baf 100644
+--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
++++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
+@@ -3,5 +3,5 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=128M
++gfx_uma_size=224M
+ fan_full_speed=Disable
+diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+index 6d27a79c66..4517ffc7c2 100644
+--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
++++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+@@ -3,5 +3,5 @@ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=224M
+ psu_fan_lvl=3
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+index 6f3cec735e..9fc4db2990 100644
+--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+@@ -3,4 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=224M
+diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
+index ad822d5043..89418a4cfc 100644
+--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
++++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
+@@ -3,3 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
+index c011867916..83f590d39d 100644
+--- a/src/mainboard/lenovo/t420/cmos.default
++++ b/src/mainboard/lenovo/t420/cmos.default
+@@ -15,3 +15,4 @@ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
+index c011867916..83f590d39d 100644
+--- a/src/mainboard/lenovo/t420s/cmos.default
++++ b/src/mainboard/lenovo/t420s/cmos.default
+@@ -15,3 +15,4 @@ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
+index 55e1e6c04e..a72108f47e 100644
+--- a/src/mainboard/lenovo/t430/cmos.default
++++ b/src/mainboard/lenovo/t430/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ usb_always_on=Disable
+ hybrid_graphics_mode=Integrated Only
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
+index b66f7034dc..a73ea6e9ee 100644
+--- a/src/mainboard/lenovo/t520/cmos.default
++++ b/src/mainboard/lenovo/t520/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
+index b66f7034dc..a73ea6e9ee 100644
+--- a/src/mainboard/lenovo/t530/cmos.default
++++ b/src/mainboard/lenovo/t530/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
+index 2cf484fd5a..46294d91ca 100644
+--- a/src/mainboard/lenovo/x201/cmos.default
++++ b/src/mainboard/lenovo/x201/cmos.default
+@@ -15,3 +15,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ usb_always_on=Disable
++gfx_uma_size=128M
+diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
+index 52f303dfdb..92a2026542 100644
+--- a/src/mainboard/lenovo/x220/cmos.default
++++ b/src/mainboard/lenovo/x220/cmos.default
+@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable
+ sticky_fn=Disable
+ trackpoint=Enable
+ me_state=Disabled
++gfx_uma_size=224M
+-- 
+2.39.2
+

config/coreboot/default/patches/0023-ec-dell-mec5035-Route-power-button-event-to-host.patch

@@ -1,92 +0,0 @@
-From d91dc168d6b8eca5e78aef9e48571d6edb156d45 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Tue, 18 Jun 2024 21:31:08 -0600
-Subject: [PATCH 23/37] ec/dell/mec5035: Route power button event to host
-
-If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
-power button results in the EC powering off the system without letting
-the OS cleanly shutting itself down. This command and argument tells the
-EC to route power button events to the host so that it can determine
-what to do.
-
-The EC command was identified from the ec/google/wilco code, which is
-used for Dell's Latitude Chromebooks. According to the EC_GOOGLE_WILCO
-Kconfig help text, those ECs run a modified version of Dell's typical
-Latitude EC firmware, so it is likely that the two firmware
-implementations use similar commands. Examining LPC traffic between the
-host and the EC on the Latitude E6400 did reveal that the same command
-was being sent by the vendor firmware to the EC, but this does not
-confirm that it has the same meaning as the command from the Wilco code.
-Sending the command using inb/outb calls in a userspace C program while
-running coreboot without this patch did allow subsequent power button
-events to be handled by the host, confirming that the command was indeed
-the same.
-
-Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/mec5035.c | 8 ++++++++
- src/ec/dell/mec5035/mec5035.h | 7 +++++++
- 2 files changed, 15 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 85c2ab0140..bdae929a27 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
- 	ec_command(CMD_RADIO_CTRL);
- }
- 
-+void mec5035_power_button_route(enum ec_power_button_route target)
-+{
-+	u8 buf = (u8)target;
-+	write_mailbox_regs(&buf, 2, 1);
-+	ec_command(CMD_POWER_BUTTON_TO_HOST);
-+}
-+
- void mec5035_change_wake(u8 source, enum ec_wake_change change)
- {
- 	u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
-@@ -121,6 +128,7 @@ static void mec5035_init(struct device *dev)
- 	/* Unconditionally use this argument for now as this setting
- 	   is probably the most sensible default out of the 3 choices. */
- 	mec5035_mouse_touchpad(TP_PS2_MOUSE);
-+	mec5035_power_button_route(HOST);
- 
- 	pc_keyboard_init(NO_AUX_DEVICE);
- 
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index 8d4fded28b..51422598c4 100644
---- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -11,6 +11,7 @@
- enum mec5035_cmd {
- 	CMD_MOUSE_TP = 0x1a,
- 	CMD_RADIO_CTRL = 0x2b,
-+	CMD_POWER_BUTTON_TO_HOST = 0x3e,
- 	CMD_ACPI_WAKEUP_CHANGE = 0x4a,
- 	CMD_SLEEP_ENABLE = 0x64,
- 	CMD_CPU_OK = 0xc2,
-@@ -36,6 +37,11 @@ enum ec_radio_state {
- 	RADIO_ON
- };
- 
-+enum ec_power_button_route {
-+	EC = 0,
-+	HOST
-+};
-+
- #define ACPI_WAKEUP_NUM_ARGS 4
- enum ec_wake_change {
- 	WAKE_OFF = 0,
-@@ -55,6 +61,7 @@ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
- void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
-+void mec5035_power_button_route(enum ec_power_button_route target);
- void mec5035_change_wake(u8 source, enum ec_wake_change change);
- void mec5035_sleep_enable(void);
- 
--- 
-2.39.5
-

config/coreboot/default/patches/0024-Disable-compression-on-refcode-insertion.patch

@@ -1,31 +0,0 @@
-From b6bd33b0430f72c2fce16a3b1e41927ef540923b Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 31 Dec 2024 14:42:24 +0000
-Subject: [PATCH 24/37] Disable compression on refcode insertion
-
-Compression is not reliably reproducible. In an lbmk release
-context, this means we cannot rely on vendorfile insertion.
-
-Therefore, use uncompressed refcode.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- Makefile.mk | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/Makefile.mk b/Makefile.mk
-index 3969bfbd05..15346569f8 100644
---- a/Makefile.mk
-+++ b/Makefile.mk
-@@ -1392,7 +1392,7 @@ endif
- cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
- $(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
- $(CONFIG_CBFS_PREFIX)/refcode-type := stage
--$(CONFIG_CBFS_PREFIX)/refcode-compression := $(CBFS_COMPRESS_FLAG)
-+$(CONFIG_CBFS_PREFIX)/refcode-compression := none
- 
- cbfs-files-$(CONFIG_SEABIOS_VGA_COREBOOT) += vgaroms/seavgabios.bin
- vgaroms/seavgabios.bin-file := $(CONFIG_PAYLOAD_VGABIOS_FILE)
--- 
-2.39.5
-

config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch

@@ -1,7 +1,7 @@
-From 3f6f65ed6a435fe49534c8a0b5cb98c3eac71150 Mon Sep 17 00:00:00 2001
+From a9ab864aee1be7a03926443ddc94e4c5012719ba Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 11:41:41 +0000
-Subject: [PATCH 09/37] dell/e6430: use ME Soft Temporary Disable
+Subject: [PATCH 24/30] dell/e6430: use ME Soft Temporary Disable
 
 i overlooked this. it's set on other boards.
 
@@ -12,13 +12,13 @@ disablement, to absolutely ensure Intel ME is not alive
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
- src/mainboard/dell/snb_ivb_latitude/cmos.default | 2 +-
+ src/mainboard/dell/e6430/cmos.default | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default
+diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
 index 2a5b30f2b7..279415dfd1 100644
---- a/src/mainboard/dell/snb_ivb_latitude/cmos.default
+--- a/src/mainboard/dell/e6430/cmos.default
-+++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default
++++ b/src/mainboard/dell/e6430/cmos.default
 @@ -6,4 +6,4 @@ bluetooth=Enable
  wwan=Enable
  wlan=Enable
@@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644
 -me_state=Normal
 +me_state=Disabled
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0025-nb-intel-Disable-stack-overflow-debug-options.patch

@@ -1,187 +0,0 @@
-From fc4c65f3bb807b9fc766745a70f92729b0b8d99e Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 21 Apr 2025 02:58:47 +0100
-Subject: [PATCH 25/37] nb/intel/*: Disable stack overflow debug options
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/northbridge/intel/e7505/Kconfig       |  9 +++++++++
- src/northbridge/intel/gm45/Kconfig        |  9 +++++++++
- src/northbridge/intel/haswell/Kconfig     |  9 +++++++++
- src/northbridge/intel/i440bx/Kconfig      | 13 +++++++++++++
- src/northbridge/intel/i945/Kconfig        |  9 +++++++++
- src/northbridge/intel/ironlake/Kconfig    |  9 +++++++++
- src/northbridge/intel/pineview/Kconfig    |  9 +++++++++
- src/northbridge/intel/sandybridge/Kconfig |  9 +++++++++
- src/northbridge/intel/x4x/Kconfig         |  9 +++++++++
- 9 files changed, 85 insertions(+)
-
-diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig
-index 039a7396f8..ddcb986f10 100644
---- a/src/northbridge/intel/e7505/Kconfig
-+++ b/src/northbridge/intel/e7505/Kconfig
-@@ -7,3 +7,12 @@ config NORTHBRIDGE_INTEL_E7505
- 	select NO_CBFS_MCACHE
- 	select SMM_TSEG
- 	select NEED_SMALL_2MB_PAGE_TABLES
-+
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
-index fc5df8b11a..95e3644b73 100644
---- a/src/northbridge/intel/gm45/Kconfig
-+++ b/src/northbridge/intel/gm45/Kconfig
-@@ -58,4 +58,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- 	default 0xfed19000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
-index 6191cb6ccf..0f5b5c7241 100644
---- a/src/northbridge/intel/haswell/Kconfig
-+++ b/src/northbridge/intel/haswell/Kconfig
-@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL
- 
- if NORTHBRIDGE_INTEL_HASWELL
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- config USE_NATIVE_RAMINIT
- 	bool "[NOT COMPLETE] Use native raminit"
- 	default n
-diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig
-index dbb2d7436b..5e9418b6a9 100644
---- a/src/northbridge/intel/i440bx/Kconfig
-+++ b/src/northbridge/intel/i440bx/Kconfig
-@@ -19,3 +19,16 @@ config SDRAMPWR_4DIMM
- 	  If your board has 4 DIMM slots, you must use select this option, in
- 	  your Kconfig file of the board. On boards with 3 DIMM slots,
- 	  do _not_ select this option.
-+
-+if NORTHBRIDGE_INTEL_I440BX
-+
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
-+endif
-diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig
-index 32eff1a611..9479d75c07 100644
---- a/src/northbridge/intel/i945/Kconfig
-+++ b/src/northbridge/intel/i945/Kconfig
-@@ -89,4 +89,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- 	default 0xfed19000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-diff --git a/src/northbridge/intel/ironlake/Kconfig b/src/northbridge/intel/ironlake/Kconfig
-index 2bafebf92e..16b81705bb 100644
---- a/src/northbridge/intel/ironlake/Kconfig
-+++ b/src/northbridge/intel/ironlake/Kconfig
-@@ -63,4 +63,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- 	default 0xfed19000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig
-index 59cfcd5e0a..a3ad8d3425 100644
---- a/src/northbridge/intel/pineview/Kconfig
-+++ b/src/northbridge/intel/pineview/Kconfig
-@@ -42,4 +42,13 @@ config FIXED_EPBAR_MMIO_BASE
- config DOMAIN_RESOURCE_32BIT_LIMIT
- 	default 0xfec00000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig
-index 973eed8bbd..6387cf926d 100644
---- a/src/northbridge/intel/sandybridge/Kconfig
-+++ b/src/northbridge/intel/sandybridge/Kconfig
-@@ -208,4 +208,13 @@ config IGD_DEFAULT_UMA_INDEX
- 	default 2 if IGD_DEFAULT_UMA_SIZE_96MB
- 	default 3 if IGD_DEFAULT_UMA_SIZE_128MB
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
-diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
-index 6430319f6a..1803ef5733 100644
---- a/src/northbridge/intel/x4x/Kconfig
-+++ b/src/northbridge/intel/x4x/Kconfig
-@@ -53,4 +53,13 @@ config FIXED_DMIBAR_MMIO_BASE
- config FIXED_EPBAR_MMIO_BASE
- 	default 0xfed19000
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+      bool
-+      default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+      bool
-+      default n
-+
- endif
--- 
-2.39.5
-

config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch

@@ -0,0 +1,36 @@
+From 936a8f113772c93d7501e7133159ab4e23436222 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 5 Nov 2023 22:57:08 +0000
+Subject: [PATCH 25/30] use mirrorservice.org for gcc downloads
+
+the gnu.org 302 redirect often fails
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 36565a906c..4d4ca06113 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
+ # to the jenkins build as well, or the builder won't download it.
+ 
+ # GCC toolchain archive locations
+-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
+-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
+ IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch

@@ -0,0 +1,792 @@
+From 973783a989cdcb7b77029e369156c81eefe8cc67 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sat, 19 Aug 2023 16:19:10 -0600
+Subject: [PATCH 26/30] mb/dell: Add Latitude E6530 (Ivy Bridge)
+
+Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested.  This
+is based on the autoport output with some manual tweaks. The flash is
+8MiB + 4MiB. It can be internally flashed by sending a command to the
+EC, which causes the EC to pull the FDO pin low and the firmware to skip
+setting up any chipset based write protections. [1] The EC is the SMSC
+MEC5055, which seems to be compatible with the existing MEC5035 code.
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6530/Kconfig           |  37 ++++
+ src/mainboard/dell/e6530/Kconfig.name      |   2 +
+ src/mainboard/dell/e6530/Makefile.inc      |   6 +
+ src/mainboard/dell/e6530/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e6530/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e6530/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e6530/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e6530/board_info.txt    |   6 +
+ src/mainboard/dell/e6530/cmos.default      |   9 +
+ src/mainboard/dell/e6530/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e6530/data.vbt          | Bin 0 -> 4280 bytes
+ src/mainboard/dell/e6530/devicetree.cb     |  68 ++++++++
+ src/mainboard/dell/e6530/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e6530/early_init.c      |  38 ++++
+ src/mainboard/dell/e6530/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e6530/gpio.c            | 192 +++++++++++++++++++++
+ src/mainboard/dell/e6530/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e6530/mainboard.c       |  21 +++
+ 18 files changed, 590 insertions(+)
+ create mode 100644 src/mainboard/dell/e6530/Kconfig
+ create mode 100644 src/mainboard/dell/e6530/Kconfig.name
+ create mode 100644 src/mainboard/dell/e6530/Makefile.inc
+ create mode 100644 src/mainboard/dell/e6530/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e6530/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e6530/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e6530/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e6530/board_info.txt
+ create mode 100644 src/mainboard/dell/e6530/cmos.default
+ create mode 100644 src/mainboard/dell/e6530/cmos.layout
+ create mode 100644 src/mainboard/dell/e6530/data.vbt
+ create mode 100644 src/mainboard/dell/e6530/devicetree.cb
+ create mode 100644 src/mainboard/dell/e6530/dsdt.asl
+ create mode 100644 src/mainboard/dell/e6530/early_init.c
+ create mode 100644 src/mainboard/dell/e6530/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e6530/gpio.c
+ create mode 100644 src/mainboard/dell/e6530/hda_verb.c
+ create mode 100644 src/mainboard/dell/e6530/mainboard.c
+
+diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
+new file mode 100644
+index 0000000000..582adddbd4
+--- /dev/null
++++ b/src/mainboard/dell/e6530/Kconfig
+@@ -0,0 +1,37 @@
++if BOARD_DELL_LATITUDE_E6530
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_12288
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_C216
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config MAINBOARD_DIR
++	default "dell/e6530"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E6530"
++
++config VGA_BIOS_ID
++	default "8086,0166"
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config USBDEBUG_HCD_INDEX
++	default 2
++endif
+diff --git a/src/mainboard/dell/e6530/Kconfig.name b/src/mainboard/dell/e6530/Kconfig.name
+new file mode 100644
+index 0000000000..01ed76d107
+--- /dev/null
++++ b/src/mainboard/dell/e6530/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E6530
++	bool "Latitude E6530"
+diff --git a/src/mainboard/dell/e6530/Makefile.inc b/src/mainboard/dell/e6530/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e6530/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6530/acpi/ec.asl b/src/mainboard/dell/e6530/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6530/acpi/platform.asl b/src/mainboard/dell/e6530/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e6530/acpi/superio.asl b/src/mainboard/dell/e6530/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e6530/acpi_tables.c b/src/mainboard/dell/e6530/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e6530/board_info.txt b/src/mainboard/dell/e6530/board_info.txt
+new file mode 100644
+index 0000000000..4601a4aaba
+--- /dev/null
++++ b/src/mainboard/dell/e6530/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2012
+diff --git a/src/mainboard/dell/e6530/cmos.default b/src/mainboard/dell/e6530/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e6530/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
+new file mode 100644
+index 0000000000..e85ea4c661
+--- /dev/null
++++ b/src/mainboard/dell/e6530/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++415	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e6530/data.vbt b/src/mainboard/dell/e6530/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
+GIT binary patch
+literal 4280
+zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV
+zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU
+zIJ+cPr4+cc-@WIad+wQY&YW{+c1J!nPPgn&^^N3Hy*D37jg0=7CSl@*=mXr>x75gi
+zTMlK0$A=H4Mh~QKqCa92jz_;d3rtFqp(o-4gCnzxrJ2}Rw@^!haWp<ahv&+aDb5_3
+zE0-vq=pkms7Ves!pD#^PA#PF^_wjBTO=oC(ayR{asyKURiBdh3?x76Ll#Z5WXklvl
+z@M5XFK#OxUXqrdzedca+l4WK~_tG8Hv&HgsX`$Za3pnYy`CpW$@0?nsSh|}MrfK#j
+z%y^t^lPNt{p5INwGcz<MWEN<wv`{J^Eluv$Rb2&6%ZgV5Bp(6~Lz2Eoz~@C!!B)bs
+z1x-OrK~}*8L07Po(5+xZL6I<}phTEf5QRsVJYHa{f^AXPFaoSsnJ0feXUdB=CJ>Fv
+zr&_=Q6YubieL}zoiJ0a+c+(bGwFN5g1pz;^rGP1sM+lHB@UAPM2&F=RB&yv@$caXF
+ze~Io&3CQe=cMHr!e{yiokd?~p&F&k`jg99Ex7}WO=$8*Kx8wXv4eSa_CJqKVkyRr&
+zCdcqs*@M5!gD84e@fW{|5B#mDGTH;JFw`h^stQcTjf@V3pNe8&f$=NG?-+klRGea*
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+zfbB~~a>piTMAVDNyHR<{<v-=}gXhE(15|emxueb8Kv%5>0{F7}8pool{7_h6u?7yg
+zlyNm>-Eq_&WjW{0$9ZHq6x?~W8l2#1g0CyrtN#R-nbWG(?>iNG1zRiZgj;Lm_%rVe
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+z^!Fn27&z6hSPR+*;D*&lm-)OE=ZgjK*(X&XdBq7RDUd7>|Lou?UMNg6lVCB;TPz{Z
+zN4-~p*Rr=uq8OYdlAy38{}dt5%2}aUax{}zWzDRgmsn2|!)=Bp)U35;Ld3H+Ye=*_
+z4S&0{5*TVI!OU-SWz$XUwrrnb%9?NHau^uhn>&;%&X#8O7mt)SIJr8D$u?NS=rUW6
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+zoNu>t*Q}|siS8#MYavR6j7&(~AEL#OaV(^+gy>YrSPiLfgy{2-p=xT2Mtd}4R8#XB
+z-LDysYw8J&{-GJKYwEiif07x7u5QsOr5oeA`ZJxDb>p|XdQzvCb>nSaeP1UfY_x~f
+z9bwuRHf|5Ahr{&iu<>+QeI`t=g^e>|^=z1;5o23K?TP5uo%2>aXQWCKr#dH;Qr0*j
+z3LecKKarw5`Xblzd$&H4oP%y&l3egyUc<=<Azs)*u}X^*n$F~s2O<-paSF?q*HB+n
+zqBfj5;J|x@hM`M(QD20jrkwi8`y3l;8qO;#l8A#CMI8Kg9E{ERsT>TGXaGC^5Cz)J
+z4?eb?Kub*nWYdmhV-4?j<o}k#pt-{wK;b3U(B^+`s7-`HYOZOxv<+RG^LulAxKL|9
+z3NH#9{Lg*7U1&gy<zHSG$;LMHby+V=ENlGFVLKjt%kkph7kP1M8|vebT=K5)*E>JW
+zjd{Tu*o*CE*QO)}{_J>haU5zn+1QJ^eBg|d5n5-%|DwS@1+<Mtvat=iZ3BF??pZXh
+zth4PnnWL*s%}k43fbe34>yaZ_2@Kj<UGt)`2G5>K>)nIBR-xB@+1PQ2*c$lV?Z13o
+zbX%CHpm`!1Z4$d28~9k{rfu-0w@xg6{q!u2{)Dm_))4RK$?#7P*t7V+g_9d<V!MD`
+zaj`t-?uy6zsjzp<-IdM6g(XhQX2iF<+p?Kmw6?a+f^VMex*PuetNfqf+4_FpD%8TW
+eZvUbDHC^NLu5~gtzg|!EqSkX2ep9pg!tpEeo1jDh
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
+new file mode 100644
+index 0000000000..96eed178c5
+--- /dev/null
++++ b/src/mainboard/dell/e6530/devicetree.cb
+@@ -0,0 +1,68 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00000251"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x0535 inherit
++
++		device ref host_bridge on end # Host bridge
++		device ref peg10 off end # PEG
++		device ref igd on end # iGPU
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x005c0921"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x007c0901"
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x33"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++			register "superspeed_capable_ports" = "0x0000000f"
++			register "xhci_overcurrent_mapping" = "0x00000c03"
++			register "xhci_switchable_ports" = "0x0000000f"
++
++			device ref xhci		on end # USB 3.0 Controller
++			device ref mei1		off end # Management Engine Interface 1
++			device ref mei2		off end # Management Engine Interface 2
++			device ref me_ide_r	off end # Management Engine IDE-R
++			device ref me_kt	on end # Management Engine KT
++			device ref gbe		on end # Intel Gigabit Ethernet
++			device ref ehci2	on end # USB2 EHCI #2
++			device ref hda		on end # High Definition Audio
++			device ref pcie_rp1	on end # PCIe Port #1
++			device ref pcie_rp2	on end # PCIe Port #2
++			device ref pcie_rp3	on end # PCIe Port #3
++			device ref pcie_rp4	on end # PCIe Port #4
++			device ref pcie_rp5	off end # PCIe Port #5
++			device ref pcie_rp6	on end # PCIe Port #6
++			device ref pcie_rp7	off end # PCIe Port #7
++			device ref pcie_rp8	off end # PCIe Port #8
++			device ref ehci1	on end # USB2 EHCI #1
++			device ref pci_bridge	off end # PCI bridge
++			device ref lpc		on # LPC bridge
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1	on end # SATA Controller 1
++			device ref smbus	on end # SMBus
++			device ref sata2	off end # SATA Controller 2
++			device ref thermal	off end # Thermal
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e6530/dsdt.asl b/src/mainboard/dell/e6530/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e6530/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
+new file mode 100644
+index 0000000000..d57f48e7f1
+--- /dev/null
++++ b/src/mainboard/dell/e6530/early_init.c
+@@ -0,0 +1,38 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <northbridge/intel/sandybridge/raminit_native.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 1, 2 },
++	{ 1, 1, 2 },
++	{ 1, 0, 3 },
++	{ 1, 1, 3 },
++	{ 1, 1, 4 },
++	{ 1, 1, 4 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 2, 6 },
++	{ 1, 2, 6 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
++	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
++	mec5035_early_init();
++}
++
++void mainboard_get_spd(spd_raw_data *spd, bool id_only)
++{
++	read_spd(&spd[0], 0x50, id_only);
++	read_spd(&spd[2], 0x52, id_only);
++}
+diff --git a/src/mainboard/dell/e6530/gma-mainboard.ads b/src/mainboard/dell/e6530/gma-mainboard.ads
+new file mode 100644
+index 0000000000..1310830c8e
+--- /dev/null
++++ b/src/mainboard/dell/e6530/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, --mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e6530/gpio.c b/src/mainboard/dell/e6530/gpio.c
+new file mode 100644
+index 0000000000..777570765a
+--- /dev/null
++++ b/src/mainboard/dell/e6530/gpio.c
+@@ -0,0 +1,192 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_GPIO,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_NATIVE,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio1 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_OUTPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio28 = GPIO_LEVEL_LOW,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++	.gpio30 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio13 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_NATIVE,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_INPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_NATIVE,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e6530/hda_verb.c b/src/mainboard/dell/e6530/hda_verb.c
+new file mode 100644
+index 0000000000..9de7e34311
+--- /dev/null
++++ b/src/mainboard/dell/e6530/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76df,	/* Codec Vendor / Device ID: IDT */
++	0x10280535,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x10280535),
++	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862806,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e6530/mainboard.c b/src/mainboard/dell/e6530/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e6530/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.39.2
+

config/coreboot/default/patches/0026-soc-intel-skylake-configure-usb-acpi.patch

@@ -1,94 +0,0 @@
-From 14002b2575d73d3edbc72584502a463e6802cba6 Mon Sep 17 00:00:00 2001
-From: Felix Singer <felixsinger@posteo.net>
-Date: Wed, 26 Jun 2024 04:24:31 +0200
-Subject: [PATCH 26/37] soc/intel/skylake: configure usb acpi
-
-Change-Id: I53fc73046e4b107064fa8c3c617ba6d9b807b71d
-Signed-off-by: Felix Singer <felixsinger@posteo.net>
----
- src/soc/intel/skylake/Kconfig    |  1 +
- src/soc/intel/skylake/chipset.cb | 56 +++++++++++++++++++++++++++++++-
- 2 files changed, 56 insertions(+), 1 deletion(-)
-
-diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index 4ad33496b2..9191ed0ff8 100644
---- a/src/soc/intel/skylake/Kconfig
-+++ b/src/soc/intel/skylake/Kconfig
-@@ -10,6 +10,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
- 	select CPU_INTEL_COMMON
- 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
- 	select CPU_SUPPORTS_PM_TIMER_EMULATION
-+	select DRIVERS_USB_ACPI
- 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
- 	select FSP_COMPRESS_FSP_S_LZ4
- 	select FSP_M_XIP
-diff --git a/src/soc/intel/skylake/chipset.cb b/src/soc/intel/skylake/chipset.cb
-index 6538a1475b..dfb81d496e 100644
---- a/src/soc/intel/skylake/chipset.cb
-+++ b/src/soc/intel/skylake/chipset.cb
-@@ -13,7 +13,61 @@ chip soc/intel/skylake
- 		device pci 07.0 alias chap         off                     end
- 		device pci 08.0 alias gmm          off                     end # Gaussian Mixture Model
- 		device pci 13.0 alias ish          off                     end # SensorHub
--		device pci 14.0 alias south_xhci   off ops usb_xhci_ops    end
-+		device pci 14.0 alias south_xhci   off ops usb_xhci_ops
-+			chip drivers/usb/acpi
-+				register "type" = "UPC_TYPE_HUB"
-+				device usb 0.0 alias xhci_root_hub off
-+					chip drivers/usb/acpi
-+						device usb 2.0 alias usb2_port1 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 2.1 alias usb2_port2 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 2.2 alias usb2_port3 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 2.3 alias usb2_port4 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 2.4 alias usb2_port5 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 2.5 alias usb2_port6 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 2.6 alias usb2_port7 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 2.7 alias usb2_port8 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 2.8 alias usb2_port9 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 2.9 alias usb2_port10 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 3.0 alias usb3_port1 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 3.1 alias usb3_port2 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 3.2 alias usb3_port3 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 3.3 alias usb3_port4 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 3.4 alias usb3_port5 off end
-+					end
-+					chip drivers/usb/acpi
-+						device usb 3.5 alias usb3_port6 off end
-+					end
-+				end
-+			end
-+		end
- 		device pci 14.1 alias south_xdci   off ops usb_xdci_ops    end
- 		device pci 14.2 alias thermal      off                     end
- 		device pci 14.3 alias cio          off                     end
--- 
-2.39.5
-

config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch

@@ -0,0 +1,145 @@
+From 88652afd52b0a8e0fc8bb1656e59d8ae4796d847 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Thu, 25 Jan 2024 14:30:03 +0000
+Subject: [PATCH 27/30] rebase dell/e6530 to newer coreboot code
+
+i diffed nicholas's current e6430 patch, versus the old one,
+prior to this revision update in lbmk, also cross referencing
+the original e6430 and e6530 patches, diffing them, and the
+result in this patch. most notably, spd data is now defined in
+the devicetree, instead of early_init.c as per:
+
+commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da
+Author: Keith Hui <buurin@gmail.com>
+Date:   Sat Jul 22 12:49:05 2023 -0400
+    mb/*: Update SPD mapping for sandybridge boards
+
+This should work fine. Will test after this builds.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/mainboard/dell/e6530/Kconfig       | 15 +++++++++++----
+ src/mainboard/dell/e6530/cmos.layout   |  2 +-
+ src/mainboard/dell/e6530/devicetree.cb |  8 +++++---
+ src/mainboard/dell/e6530/early_init.c  | 12 +++---------
+ 4 files changed, 20 insertions(+), 17 deletions(-)
+
+diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
+index 582adddbd4..a104566890 100644
+--- a/src/mainboard/dell/e6530/Kconfig
++++ b/src/mainboard/dell/e6530/Kconfig
+@@ -20,18 +20,25 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select SYSTEM_TYPE_LAPTOP
+ 	select USE_NATIVE_RAMINIT
+ 
++config DRAM_RESET_GATE_GPIO
++	default 60
++
+ config MAINBOARD_DIR
+ 	default "dell/e6530"
+ 
+ config MAINBOARD_PART_NUMBER
+ 	default "Latitude E6530"
+ 
+-config VGA_BIOS_ID
+-	default "8086,0166"
++config PS2K_EISAID
++	default "PNP0303"
+ 
+-config DRAM_RESET_GATE_GPIO
+-	default 60
++config PS2M_EISAID
++	default "PNP0F13"
+ 
+ config USBDEBUG_HCD_INDEX
+ 	default 2
++
++config VGA_BIOS_ID
++	default "8086,0166"
++
+ endif
+diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
+index e85ea4c661..1aa7e77bce 100644
+--- a/src/mainboard/dell/e6530/cmos.layout
++++ b/src/mainboard/dell/e6530/cmos.layout
+@@ -25,7 +25,7 @@ entries
+ # coreboot config options: EC
+ 412	1	e	1	bluetooth
+ 413	1	e	1	wwan
+-415	1	e	1	wlan
++414	1	e	1	wlan
+ 
+ # coreboot config options: ME
+ 424	1	e	14	me_state
+diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
+index 96eed178c5..37135bcf0f 100644
+--- a/src/mainboard/dell/e6530/devicetree.cb
++++ b/src/mainboard/dell/e6530/devicetree.cb
+@@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 	register "gpu_panel_power_up_delay" = "400"
+ 	register "gpu_pch_backlight" = "0x13121312"
+ 
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
+ 	device domain 0x0 on
+ 		subsystemid 0x1028 0x0535 inherit
+ 
+@@ -24,7 +26,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 			register "gen1_dec" = "0x007c0681"
+ 			register "gen2_dec" = "0x005c0921"
+ 			register "gen3_dec" = "0x003c07e1"
+-			register "gen4_dec" = "0x007c0901"
++			register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
+ 			register "gpi0_routing" = "2"
+ 			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ 			register "pcie_port_coalesce" = "1"
+@@ -37,7 +39,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 			register "xhci_switchable_ports" = "0x0000000f"
+ 
+ 			device ref xhci		on end # USB 3.0 Controller
+-			device ref mei1		off end # Management Engine Interface 1
++			device ref mei1		on end # Management Engine Interface 1
+ 			device ref mei2		off end # Management Engine Interface 2
+ 			device ref me_ide_r	off end # Management Engine IDE-R
+ 			device ref me_kt	on end # Management Engine KT
+@@ -48,7 +50,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 			device ref pcie_rp2	on end # PCIe Port #2
+ 			device ref pcie_rp3	on end # PCIe Port #3
+ 			device ref pcie_rp4	on end # PCIe Port #4
+-			device ref pcie_rp5	off end # PCIe Port #5
++			device ref pcie_rp5	on end # PCIe Port #5
+ 			device ref pcie_rp6	on end # PCIe Port #6
+ 			device ref pcie_rp7	off end # PCIe Port #7
+ 			device ref pcie_rp8	off end # PCIe Port #8
+diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
+index d57f48e7f1..2b40f6963f 100644
+--- a/src/mainboard/dell/e6530/early_init.c
++++ b/src/mainboard/dell/e6530/early_init.c
+@@ -4,7 +4,6 @@
+ #include <bootblock_common.h>
+ #include <device/pci_ops.h>
+ #include <ec/dell/mec5035/mec5035.h>
+-#include <northbridge/intel/sandybridge/raminit_native.h>
+ #include <southbridge/intel/bd82x6x/pch.h>
+ 
+ const struct southbridge_usb_port mainboard_usb_ports[] = {
+@@ -26,13 +25,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
+ 
+ void bootblock_mainboard_early_init(void)
+ {
+-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
+-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
+ 	mec5035_early_init();
+ }
+-
+-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+-{
+-	read_spd(&spd[0], 0x50, id_only);
+-	read_spd(&spd[2], 0x52, id_only);
+-}
+-- 
+2.39.2
+

config/coreboot/default/patches/0027-soc-intel-skylake-Enable-4E-4F-PNP-I-O-ports-in-boot.patch

@@ -1,30 +0,0 @@
-From 3bb65b7f2a02ecb93e15ae037da38ad8f812747b Mon Sep 17 00:00:00 2001
-From: Mate Kukri <km@mkukri.xyz>
-Date: Fri, 22 Nov 2024 21:26:48 +0000
-Subject: [PATCH 27/37] soc/intel/skylake: Enable 4E/4F PNP I/O ports in
- bootblock
-
-Change-Id: I57c9d8a9513a268e2ca6a0abd1306cd038598173
-Signed-off-by: Mate Kukri <km@mkukri.xyz>
----
- src/soc/intel/skylake/bootblock/pch.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c
-index df00bb85a9..beaece960b 100644
---- a/src/soc/intel/skylake/bootblock/pch.c
-+++ b/src/soc/intel/skylake/bootblock/pch.c
-@@ -100,8 +100,8 @@ static void soc_config_pwrmbase(void)
- 
- void pch_early_iorange_init(void)
- {
--	uint16_t io_enables = LPC_IOE_SUPERIO_2E_2F | LPC_IOE_KBC_60_64 |
--			LPC_IOE_EC_62_66;
-+	uint16_t io_enables = LPC_IOE_EC_4E_4F | LPC_IOE_SUPERIO_2E_2F |
-+			LPC_IOE_KBC_60_64 | LPC_IOE_EC_62_66;
- 
- 	const config_t *config = config_of_soc();
- 
--- 
-2.39.5
-

config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch

@@ -0,0 +1,54 @@
+From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Thu, 25 Jan 2024 14:37:30 +0000
+Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree
+
+we neuter anyway. disabling it in devicetree will prevent linux
+from ever trying to use it or load a driver for it, and thus
+might prevent benign error messages from appearing in dmesg.
+
+this change was suggested by nicholas when asked on irc.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/mainboard/dell/e6430/devicetree.cb | 4 ++--
+ src/mainboard/dell/e6530/devicetree.cb | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
+index 054b01c5ac..2b8574c984 100644
+--- a/src/mainboard/dell/e6430/devicetree.cb
++++ b/src/mainboard/dell/e6430/devicetree.cb
+@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 			register "xhci_switchable_ports" = "0x0000000f"
+ 
+ 			device ref xhci		on end
+-			device ref mei1		on end
++			device ref mei1		off end
+ 			device ref mei2		off end
+ 			device ref me_ide_r	off end
+-			device ref me_kt	on end
++			device ref me_kt	off end
+ 			device ref gbe		on end
+ 			device ref ehci2	on end
+ 			device ref hda		on end
+diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
+index 37135bcf0f..010200bb6d 100644
+--- a/src/mainboard/dell/e6530/devicetree.cb
++++ b/src/mainboard/dell/e6530/devicetree.cb
+@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 			register "xhci_switchable_ports" = "0x0000000f"
+ 
+ 			device ref xhci		on end # USB 3.0 Controller
+-			device ref mei1		on end # Management Engine Interface 1
++			device ref mei1		off end # Management Engine Interface 1
+ 			device ref mei2		off end # Management Engine Interface 2
+ 			device ref me_ide_r	off end # Management Engine IDE-R
+-			device ref me_kt	on end # Management Engine KT
++			device ref me_kt	off end # Management Engine KT
+ 			device ref gbe		on end # Intel Gigabit Ethernet
+ 			device ref ehci2	on end # USB2 EHCI #2
+ 			device ref hda		on end # High Definition Audio
+-- 
+2.39.2
+

config/coreboot/default/patches/0029-mb-dell-Add-Optiplex-780-MT-x4x-ICH10.patch

@@ -1,708 +0,0 @@
-From 75cc0ea09234064318046624845b0afc5afb0ce5 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Mon, 30 Sep 2024 20:44:38 -0400
-Subject: [PATCH 29/37] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
-
-Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/optiplex_780/Kconfig       |  40 ++++
- src/mainboard/dell/optiplex_780/Kconfig.name  |   4 +
- src/mainboard/dell/optiplex_780/Makefile.mk   |  10 +
- src/mainboard/dell/optiplex_780/acpi/ec.asl   |   5 +
- .../dell/optiplex_780/acpi/ich10_pci_irqs.asl |  32 ++++
- .../dell/optiplex_780/acpi/superio.asl        |  18 ++
- .../dell/optiplex_780/board_info.txt          |   6 +
- src/mainboard/dell/optiplex_780/cmos.default  |   8 +
- src/mainboard/dell/optiplex_780/cmos.layout   |  72 ++++++++
- src/mainboard/dell/optiplex_780/cstates.c     |   8 +
- src/mainboard/dell/optiplex_780/devicetree.cb |  63 +++++++
- src/mainboard/dell/optiplex_780/dsdt.asl      |  26 +++
- .../dell/optiplex_780/gma-mainboard.ads       |  16 ++
- .../optiplex_780/variants/780_mt/data.vbt     | Bin 0 -> 1917 bytes
- .../optiplex_780/variants/780_mt/early_init.c |  12 ++
- .../dell/optiplex_780/variants/780_mt/gpio.c  | 174 ++++++++++++++++++
- .../optiplex_780/variants/780_mt/hda_verb.c   |  26 +++
- .../variants/780_mt/overridetree.cb           |  10 +
- 18 files changed, 530 insertions(+)
- create mode 100644 src/mainboard/dell/optiplex_780/Kconfig
- create mode 100644 src/mainboard/dell/optiplex_780/Kconfig.name
- create mode 100644 src/mainboard/dell/optiplex_780/Makefile.mk
- create mode 100644 src/mainboard/dell/optiplex_780/acpi/ec.asl
- create mode 100644 src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
- create mode 100644 src/mainboard/dell/optiplex_780/acpi/superio.asl
- create mode 100644 src/mainboard/dell/optiplex_780/board_info.txt
- create mode 100644 src/mainboard/dell/optiplex_780/cmos.default
- create mode 100644 src/mainboard/dell/optiplex_780/cmos.layout
- create mode 100644 src/mainboard/dell/optiplex_780/cstates.c
- create mode 100644 src/mainboard/dell/optiplex_780/devicetree.cb
- create mode 100644 src/mainboard/dell/optiplex_780/dsdt.asl
- create mode 100644 src/mainboard/dell/optiplex_780/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
-
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
-new file mode 100644
-index 0000000000..2d06c75c9a
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/Kconfig
-@@ -0,0 +1,40 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+config BOARD_DELL_OPTIPLEX_780_COMMON
-+	def_bool n
-+	select BOARD_ROMSIZE_KB_8192
-+	select CPU_INTEL_SOCKET_LGA775
-+	select DRIVERS_I2C_CK505
-+	select HAVE_ACPI_RESUME
-+	select HAVE_ACPI_TABLES
-+	select HAVE_CMOS_DEFAULT
-+	select HAVE_OPTION_TABLE
-+	select INTEL_GMA_HAVE_VBT
-+	select MAINBOARD_HAS_LIBGFXINIT
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select NORTHBRIDGE_INTEL_X4X
-+	select PCIEXP_ASPM
-+	select PCIEXP_CLK_PM
-+	select SOUTHBRIDGE_INTEL_I82801JX
-+
-+config BOARD_DELL_OPTIPLEX_780_MT
-+	select BOARD_DELL_OPTIPLEX_780_COMMON
-+
-+if BOARD_DELL_OPTIPLEX_780_COMMON
-+
-+config VGA_BIOS_ID
-+	default "8086,2e22"
-+
-+config MAINBOARD_DIR
-+	default "dell/optiplex_780"
-+
-+config MAINBOARD_PART_NUMBER
-+	default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
-+
-+config OVERRIDE_DEVICETREE
-+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-+
-+config VARIANT_DIR
-+	default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
-+
-+endif # BOARD_DELL_OPTIPLEX_780_COMMON
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
-new file mode 100644
-index 0000000000..db7f2e8fe3
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
-@@ -0,0 +1,4 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+config BOARD_DELL_OPTIPLEX_780_MT
-+	bool "OptiPlex 780 MT"
-diff --git a/src/mainboard/dell/optiplex_780/Makefile.mk b/src/mainboard/dell/optiplex_780/Makefile.mk
-new file mode 100644
-index 0000000000..d462995d75
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/Makefile.mk
-@@ -0,0 +1,10 @@
-+# SPDX-License-Identifier: GPL-2.0-only
-+
-+ramstage-y += cstates.c
-+romstage-y += variants/$(VARIANT_DIR)/gpio.c
-+
-+bootblock-y += variants/$(VARIANT_DIR)/early_init.c
-+romstage-y += variants/$(VARIANT_DIR)/early_init.c
-+
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
-diff --git a/src/mainboard/dell/optiplex_780/acpi/ec.asl b/src/mainboard/dell/optiplex_780/acpi/ec.asl
-new file mode 100644
-index 0000000000..479296cb76
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/acpi/ec.asl
-@@ -0,0 +1,5 @@
-+/* SPDX-License-Identifier: CC-PDDC */
-+
-+/* Please update the license if adding licensable material. */
-+
-+/* dummy */
-diff --git a/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
-new file mode 100644
-index 0000000000..b7588dcc41
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/acpi/ich10_pci_irqs.asl
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+/* This is board specific information:
-+ * IRQ routing for the 0:1e.0 PCI bridge of the ICH10
-+ */
-+
-+If (PICM) {
-+	Return (Package() {
-+		/* PCI slot */
-+		Package() { 0x0001ffff, 0, 0, 0x14},
-+		Package() { 0x0001ffff, 1, 0, 0x15},
-+		Package() { 0x0001ffff, 2, 0, 0x16},
-+		Package() { 0x0001ffff, 3, 0, 0x17},
-+
-+		Package() { 0x0002ffff, 0, 0, 0x15},
-+		Package() { 0x0002ffff, 1, 0, 0x16},
-+		Package() { 0x0002ffff, 2, 0, 0x17},
-+		Package() { 0x0002ffff, 3, 0, 0x14},
-+	})
-+} Else {
-+	Return (Package() {
-+		Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKE, 0},
-+		Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKF, 0},
-+		Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKG, 0},
-+		Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKH, 0},
-+
-+		Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKF, 0},
-+		Package() { 0x0002ffff, 1, \_SB.PCI0.LPCB.LNKG, 0},
-+		Package() { 0x0002ffff, 2, \_SB.PCI0.LPCB.LNKH, 0},
-+		Package() { 0x0002ffff, 3, \_SB.PCI0.LPCB.LNKE, 0},
-+	})
-+}
-diff --git a/src/mainboard/dell/optiplex_780/acpi/superio.asl b/src/mainboard/dell/optiplex_780/acpi/superio.asl
-new file mode 100644
-index 0000000000..9f3900b86c
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/acpi/superio.asl
-@@ -0,0 +1,18 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#undef SUPERIO_DEV
-+#undef SUPERIO_PNP_BASE
-+#undef IT8720F_SHOW_SP1
-+#undef IT8720F_SHOW_SP2
-+#undef IT8720F_SHOW_EC
-+#undef IT8720F_SHOW_KBCK
-+#undef IT8720F_SHOW_KBCM
-+#undef IT8720F_SHOW_GPIO
-+#undef IT8720F_SHOW_CIR
-+#define SUPERIO_DEV		SIO0
-+#define SUPERIO_PNP_BASE	0x2e
-+#define IT8720F_SHOW_EC		1
-+#define IT8720F_SHOW_KBCK	1
-+#define IT8720F_SHOW_KBCM	1
-+#define IT8720F_SHOW_GPIO	1
-+#include <superio/ite/it8720f/acpi/superio.asl>
-diff --git a/src/mainboard/dell/optiplex_780/board_info.txt b/src/mainboard/dell/optiplex_780/board_info.txt
-new file mode 100644
-index 0000000000..aaf657b583
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/board_info.txt
-@@ -0,0 +1,6 @@
-+Category: desktop
-+Board URL: https://www.acer.com/ac/en/GB/content/support-product/1137?b=1
-+ROM package: SOIC-8
-+ROM protocol: SPI
-+ROM socketed: n
-+Flashrom support: y
-diff --git a/src/mainboard/dell/optiplex_780/cmos.default b/src/mainboard/dell/optiplex_780/cmos.default
-new file mode 100644
-index 0000000000..23f0e55f3e
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/cmos.default
-@@ -0,0 +1,8 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+boot_option=Fallback
-+debug_level=Debug
-+power_on_after_fail=Disable
-+nmi=Enable
-+sata_mode=AHCI
-+gfx_uma_size=64M
-diff --git a/src/mainboard/dell/optiplex_780/cmos.layout b/src/mainboard/dell/optiplex_780/cmos.layout
-new file mode 100644
-index 0000000000..9f5012adb4
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/cmos.layout
-@@ -0,0 +1,72 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+# -----------------------------------------------------------------
-+entries
-+
-+# -----------------------------------------------------------------
-+0	120	r	0	reserved_memory
-+
-+# -----------------------------------------------------------------
-+# RTC_BOOT_BYTE (coreboot hardcoded)
-+384	1	e	4	boot_option
-+388	4	h	0	reboot_counter
-+
-+# -----------------------------------------------------------------
-+# coreboot config options: console
-+395	4	e	6	debug_level
-+
-+# coreboot config options: southbridge
-+408	1	e	10	sata_mode
-+409	2	e	7	power_on_after_fail
-+411	1	e	1	nmi
-+
-+# coreboot config options: cpu
-+
-+# coreboot config options: northbridge
-+432	4	e	11	gfx_uma_size
-+
-+# coreboot config options: check sums
-+984	16	h	0	check_sum
-+
-+# -----------------------------------------------------------------
-+
-+enumerations
-+
-+#ID	value	text
-+1	0	Disable
-+1	1	Enable
-+2	0	Enable
-+2	1	Disable
-+4	0	Fallback
-+4	1	Normal
-+6	0	Emergency
-+6	1	Alert
-+6	2	Critical
-+6	3	Error
-+6	4	Warning
-+6	5	Notice
-+6	6	Info
-+6	7	Debug
-+6	8	Spew
-+7	0	Disable
-+7	1	Enable
-+7	2	Keep
-+10	0	AHCI
-+10	1	Compatible
-+11	1	4M
-+11	2	8M
-+11	3	16M
-+11	4	32M
-+11	5	48M
-+11	6	64M
-+11	7	128M
-+11	8	256M
-+11	9	96M
-+11	10	160M
-+11	11	224M
-+11	12	352M
-+
-+# -----------------------------------------------------------------
-+checksums
-+
-+checksum 392 983 984
-diff --git a/src/mainboard/dell/optiplex_780/cstates.c b/src/mainboard/dell/optiplex_780/cstates.c
-new file mode 100644
-index 0000000000..4adf0edc63
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/cstates.c
-@@ -0,0 +1,8 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpigen.h>
-+
-+int get_cst_entries(const acpi_cstate_t **entries)
-+{
-+	return 0;
-+}
-diff --git a/src/mainboard/dell/optiplex_780/devicetree.cb b/src/mainboard/dell/optiplex_780/devicetree.cb
-new file mode 100644
-index 0000000000..95e3bd517c
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/devicetree.cb
-@@ -0,0 +1,63 @@
-+# SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/x4x
-+	device cpu_cluster 0 on ops x4x_cpu_bus_ops end		# APIC cluster
-+	device domain 0 on
-+		ops x4x_pci_domain_ops		# PCI domain
-+		subsystemid 0x8086 0x0028 inherit
-+		device pci 0.0 on  end		# Host Bridge
-+		device pci 1.0 on  end		# PCIe x16 2.0 slot
-+		device pci 2.0 on  end		# Integrated graphics controller
-+		device pci 2.1 on  end		# Integrated graphics controller 2
-+		device pci 3.0 off end		# ME
-+		device pci 3.1 off end		# ME
-+		chip southbridge/intel/i82801jx	# ICH10
-+			register "gpe0_en" = "0x40"
-+
-+			# Set AHCI mode.
-+			register "sata_port_map"	= "0x3f"
-+			register "sata_clock_request"	= "1"
-+
-+			# Enable PCIe ports 0,1 as slots.
-+			register "pcie_slot_implemented" = "0x3"
-+
-+			device pci 19.0 on  end		# GBE
-+			device pci 1a.0 on  end		# USB
-+			device pci 1a.1 on  end		# USB
-+			device pci 1a.2 on  end		# USB
-+			device pci 1a.7 on  end		# USB
-+			device pci 1b.0 on  end		# Audio
-+			device pci 1c.0 off end		# PCIe 1
-+			device pci 1c.1 off end		# PCIe 2
-+			device pci 1c.2 off end		# PCIe 3
-+			device pci 1c.3 off end		# PCIe 4
-+			device pci 1c.4 off end		# PCIe 5
-+			device pci 1c.5 off end		# PCIe 6
-+			device pci 1d.0 on  end		# USB
-+			device pci 1d.1 on  end		# USB
-+			device pci 1d.2 on  end		# USB
-+			device pci 1d.7 on  end		# USB
-+			device pci 1e.0 on  end		# PCI bridge
-+			device pci 1f.0 on  end		# LPC bridge
-+			device pci 1f.2 on  end		# SATA (IDE: port 0-3, AHCI/RAID: 0-5)
-+			device pci 1f.3 on		# SMBus
-+				chip drivers/i2c/ck505	# IDT CV194
-+					register "mask" = "{ 0xff, 0xff, 0xff, 0xff,
-+							     0xff, 0xff, 0xff, 0xff,
-+							     0xff, 0xff, 0xff, 0xff,
-+							     0xff, 0xff, 0xff, 0xff,
-+							     0xff, 0xff, 0xff }"
-+					register "regs" = "{ 0x15, 0x82, 0xff, 0xff,
-+							     0xff, 0x00, 0x00, 0x95,
-+							     0x00, 0x65, 0x7d, 0x56,
-+							     0x13, 0xc0, 0x00, 0x07,
-+							     0x01, 0x0a, 0x64 }"
-+					device i2c 69 on end
-+				end
-+			end
-+			device pci 1f.4 off end
-+			device pci 1f.5 off end		# SATA 2 (for port 4-5 in IDE mode)
-+			device pci 1f.6 off end		# Thermal Subsystem
-+		end
-+	end
-+end
-diff --git a/src/mainboard/dell/optiplex_780/dsdt.asl b/src/mainboard/dell/optiplex_780/dsdt.asl
-new file mode 100644
-index 0000000000..9ad70469de
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/dsdt.asl
-@@ -0,0 +1,26 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi.h>
-+DefinitionBlock(
-+	"dsdt.aml",
-+	"DSDT",
-+	ACPI_DSDT_REV_2,
-+	OEM_ID,
-+	ACPI_TABLE_CREATOR,
-+	0x20090811	// OEM revision
-+)
-+{
-+	#include <acpi/dsdt_top.asl>
-+
-+	OSYS = 2002
-+	// global NVS and variables
-+	#include <southbridge/intel/common/acpi/platform.asl>
-+
-+	Device (\_SB.PCI0)
-+	{
-+		#include <northbridge/intel/x4x/acpi/x4x.asl>
-+		#include <southbridge/intel/i82801jx/acpi/ich10.asl>
-+	}
-+
-+	#include <southbridge/intel/common/acpi/sleepstates.asl>
-+}
-diff --git a/src/mainboard/dell/optiplex_780/gma-mainboard.ads b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
-new file mode 100644
-index 0000000000..bc81cf4a40
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/gma-mainboard.ads
-@@ -0,0 +1,16 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (DP2,
-+      Analog,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_mt/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..fefda9d6f226b88ab67c5b044de30a707df22fbf
-GIT binary patch
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-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
-new file mode 100644
-index 0000000000..e2fa05cd8f
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/early_init.c
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <northbridge/intel/x4x/x4x.h>
-+
-+void mb_get_spd_map(u8 spd_map[4])
-+{
-+	// BTX form factor
-+	spd_map[0] = 0x53;
-+	spd_map[1] = 0x52;
-+	spd_map[2] = 0x51;
-+	spd_map[3] = 0x50;
-+}
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
-new file mode 100644
-index 0000000000..9993f17c55
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/gpio.c
-@@ -0,0 +1,174 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0  = GPIO_MODE_NATIVE,
-+	.gpio1  = GPIO_MODE_NATIVE,
-+	.gpio2  = GPIO_MODE_GPIO,
-+	.gpio3  = GPIO_MODE_GPIO,
-+	.gpio4  = GPIO_MODE_GPIO,
-+	.gpio5  = GPIO_MODE_GPIO,
-+	.gpio6  = GPIO_MODE_GPIO,
-+	.gpio7  = GPIO_MODE_NATIVE,
-+	.gpio8  = GPIO_MODE_NATIVE,
-+	.gpio9  = GPIO_MODE_GPIO,
-+	.gpio10 = GPIO_MODE_GPIO,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_NATIVE,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_NATIVE,
-+	.gpio18 = GPIO_MODE_GPIO,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_GPIO,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio2  = GPIO_DIR_INPUT,
-+	.gpio3  = GPIO_DIR_INPUT,
-+	.gpio4  = GPIO_DIR_INPUT,
-+	.gpio5  = GPIO_DIR_INPUT,
-+	.gpio6  = GPIO_DIR_INPUT,
-+	.gpio9  = GPIO_DIR_OUTPUT,
-+	.gpio10 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio18 = GPIO_DIR_OUTPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio20 = GPIO_DIR_OUTPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_INPUT,
-+	.gpio31 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio9  = GPIO_LEVEL_HIGH,
-+	.gpio18 = GPIO_LEVEL_HIGH,
-+	.gpio20 = GPIO_LEVEL_HIGH,
-+	.gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio13 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_GPIO,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_NATIVE,
-+	.gpio52 = GPIO_MODE_NATIVE,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio32 = GPIO_DIR_INPUT,
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_INPUT,
-+	.gpio35 = GPIO_DIR_OUTPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio56 = GPIO_DIR_OUTPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio35 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_HIGH,
-+	.gpio56 = GPIO_LEVEL_HIGH,
-+	.gpio60 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_NATIVE,
-+	.gpio69 = GPIO_MODE_NATIVE,
-+	.gpio70 = GPIO_MODE_NATIVE,
-+	.gpio71 = GPIO_MODE_NATIVE,
-+	.gpio72 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio72 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode      = &pch_gpio_set1_mode,
-+		.direction = &pch_gpio_set1_direction,
-+		.level     = &pch_gpio_set1_level,
-+		.blink     = &pch_gpio_set1_blink,
-+		.invert    = &pch_gpio_set1_invert,
-+	},
-+	.set2 = {
-+		.mode      = &pch_gpio_set2_mode,
-+		.direction = &pch_gpio_set2_direction,
-+		.level     = &pch_gpio_set2_level,
-+	},
-+	.set3 = {
-+		.mode      = &pch_gpio_set3_mode,
-+		.direction = &pch_gpio_set3_direction,
-+		.level     = &pch_gpio_set3_level,
-+	},
-+};
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
-new file mode 100644
-index 0000000000..4158bcf899
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/hda_verb.c
-@@ -0,0 +1,26 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	/* coreboot specific header */
-+	0x11d4194a, /* Analog Devices AD1984A */
-+	0xbfd40000, /*  Subsystem ID */
-+	10,         /* Number of entries */
-+
-+	/* Pin Widget Verb Table */
-+	AZALIA_PIN_CFG(0, 0x11, 0x032140f0),
-+	AZALIA_PIN_CFG(0, 0x12, 0x21214010),
-+	AZALIA_PIN_CFG(0, 0x13, 0x901701f0),
-+	AZALIA_PIN_CFG(0, 0x14, 0x03a190f0),
-+	AZALIA_PIN_CFG(0, 0x15, 0xb7a70121),
-+	AZALIA_PIN_CFG(0, 0x16, 0x9933012e),
-+	AZALIA_PIN_CFG(0, 0x17, 0x97a601f0),
-+	AZALIA_PIN_CFG(0, 0x1a, 0x90f301f0),
-+	AZALIA_PIN_CFG(0, 0x1b, 0x014510f0),
-+	AZALIA_PIN_CFG(0, 0x1c, 0x21a19020),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
-new file mode 100644
-index 0000000000..555b1c1f5c
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_mt/overridetree.cb
-@@ -0,0 +1,10 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/x4x
-+	device domain 0 on
-+		chip southbridge/intel/i82801jx
-+			device pci 1c.0 on  end		# PCIe 1
-+			device pci 1c.1 on  end		# PCIe 2
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0030-mb-dell-optiplex_780-Add-USFF-variant.patch

@@ -1,326 +0,0 @@
-From 6725ec0bb976c61cbe87e61bf0e8b02e38d14de9 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Wed, 30 Oct 2024 20:55:25 -0600
-Subject: [PATCH 30/37] mb/dell/optiplex_780: Add USFF variant
-
-Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/optiplex_780/Kconfig       |   5 +
- src/mainboard/dell/optiplex_780/Kconfig.name  |   3 +
- .../optiplex_780/variants/780_usff/data.vbt   | Bin 0 -> 1917 bytes
- .../variants/780_usff/early_init.c            |   9 +
- .../optiplex_780/variants/780_usff/gpio.c     | 166 ++++++++++++++++++
- .../optiplex_780/variants/780_usff/hda_verb.c |  26 +++
- .../variants/780_usff/overridetree.cb         |  10 ++
- 7 files changed, 219 insertions(+)
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
- create mode 100644 src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
-
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig b/src/mainboard/dell/optiplex_780/Kconfig
-index 2d06c75c9a..fc649e35d5 100644
---- a/src/mainboard/dell/optiplex_780/Kconfig
-+++ b/src/mainboard/dell/optiplex_780/Kconfig
-@@ -20,6 +20,9 @@ config BOARD_DELL_OPTIPLEX_780_COMMON
- config BOARD_DELL_OPTIPLEX_780_MT
- 	select BOARD_DELL_OPTIPLEX_780_COMMON
- 
-+config BOARD_DELL_OPTIPLEX_780_USFF
-+	select BOARD_DELL_OPTIPLEX_780_COMMON
-+
- if BOARD_DELL_OPTIPLEX_780_COMMON
- 
- config VGA_BIOS_ID
-@@ -30,11 +33,13 @@ config MAINBOARD_DIR
- 
- config MAINBOARD_PART_NUMBER
- 	default "OptiPlex 780 MT" if BOARD_DELL_OPTIPLEX_780_MT
-+	default "OptiPlex 780 USFF" if BOARD_DELL_OPTIPLEX_780_USFF
- 
- config OVERRIDE_DEVICETREE
- 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
- 
- config VARIANT_DIR
- 	default "780_mt" if BOARD_DELL_OPTIPLEX_780_MT
-+	default "780_usff" if BOARD_DELL_OPTIPLEX_780_USFF
- 
- endif # BOARD_DELL_OPTIPLEX_780_COMMON
-diff --git a/src/mainboard/dell/optiplex_780/Kconfig.name b/src/mainboard/dell/optiplex_780/Kconfig.name
-index db7f2e8fe3..bc84c82a79 100644
---- a/src/mainboard/dell/optiplex_780/Kconfig.name
-+++ b/src/mainboard/dell/optiplex_780/Kconfig.name
-@@ -2,3 +2,6 @@
- 
- config BOARD_DELL_OPTIPLEX_780_MT
- 	bool "OptiPlex 780 MT"
-+
-+config BOARD_DELL_OPTIPLEX_780_USFF
-+	bool "OptiPlex 780 USFF"
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt b/src/mainboard/dell/optiplex_780/variants/780_usff/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..dbd764f285ed18f7ee9c54bc777560138bd9b5f7
-GIT binary patch
-literal 1917
-zcmd6nO>7%Q6vzLwGv3{}j$^l`v7@w1q*9sEq+2(b3K>`@c5#TSx@i<uQKf!)+gO;|
-zveT#>P+W+B10OwbsGtX=N(gc4jSGjKDkP+yIUo^nsel8$^ny^9H?td8Ra=EiCEn=G
-z@6DV4?!2AdojnUv^Rirgvs$heXUkGs9S+{Jc2WPhP0buTak^BTFP@&N9-E$(UtuSX
-zS{r`=b+EX|Ig`2a*^5oDdG>8jE-1BBxs`*jgrf_sj_fP;%L|PwURRcCFBMCroNRQv
-zmp$2TUhc}qJMB(u#jDG@x6(N85thC4%Z=8hiN}lj&zb2~``u3C;?lCrPQOTnInFqB
-zhvdwqWv?lxTb=fVEH;~RPHDPw&g*&|s$pU<Iv53Rb6YTgMPOY8;~P1Yglh^6Fgt1^
-zCTz|SVPcSpZ44F@&oNPUMO@&BE3y(57YP_Y!4SZhE?GXYa7k+b0(X|s7u3GDRf^1#
-zOd2ZCCPO|I&sHEt;p8UshhHtYQ>7!7x2m<d`Gu2<r+Qc4|6pwd8&zFboH_W7XE7uU
-zWW-@Cim&mdY2!O{JANR)OTJG2z>LBtAF!g>K`zPnkx!DpPHuk6{_zc*0qi7)Aet$T
-z1ks@8hWS#+6cI5)j1oD86{5PX8Zu2(^OC6M`<pE+J?KFZ=&_JVP1YL=#z<-Q*24K4
-zn+$YxrHNJJc`k?_8N=Kres26_#E8GLn2{jfW5P%ge`kL(Btkt=>xo)V)Ow=U6P12c
-z=U0uNC9T9v{)-|#h(mSX*hSA8)ZeocL7l4J&!{RSO{6~oTtyn535j!RQh#GA*wTF8
-zvasRbO~d!?*FbM3K`W?lHx=v*(jiARIhWyh4^io|;n?@1H>uqJy>0sjV-Dt)_=%bE
-zgNO3D@uE5m+7aqi?Y8b+inye%Z=HUmgBtaZ3Lc%OLt+bo+)5BjVwT<{mxT`nde$vb
-zV99s{>`r76L#Hr6XW6r|<iq#4Jr?XsxKyeJKEj7;e4SZ^1B12u&iV_9M0*Kem@fmn
-z1C>>HT47I`**Q#Vu0QW!^VP-9S{xXzpq_zS#9k-;aXz?b+S!Ne$Kkk6dq<Gj{q2D(
-z>&Hj-x+kx1W-4#E&beDT*S)=&NoSE?<-w!G@~aW()0ZN4O&=Q+nZa)p%Vd$k-_$a=
-T#w3FFBiyj<XAh$hb(enud`r7S
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
-new file mode 100644
-index 0000000000..2a55fc3a6e
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/early_init.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <northbridge/intel/x4x/x4x.h>
-+
-+void mb_get_spd_map(u8 spd_map[4])
-+{
-+	spd_map[0] = 0x50;
-+	spd_map[2] = 0x52;
-+}
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
-new file mode 100644
-index 0000000000..389f4077d7
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/gpio.c
-@@ -0,0 +1,166 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0  = GPIO_MODE_NATIVE,
-+	.gpio1  = GPIO_MODE_NATIVE,
-+	.gpio2  = GPIO_MODE_GPIO,
-+	.gpio3  = GPIO_MODE_GPIO,
-+	.gpio4  = GPIO_MODE_GPIO,
-+	.gpio5  = GPIO_MODE_GPIO,
-+	.gpio6  = GPIO_MODE_GPIO,
-+	.gpio7  = GPIO_MODE_NATIVE,
-+	.gpio8  = GPIO_MODE_NATIVE,
-+	.gpio9  = GPIO_MODE_GPIO,
-+	.gpio10 = GPIO_MODE_GPIO,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_NATIVE,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_NATIVE,
-+	.gpio18 = GPIO_MODE_GPIO,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_GPIO,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio2  = GPIO_DIR_INPUT,
-+	.gpio3  = GPIO_DIR_INPUT,
-+	.gpio4  = GPIO_DIR_INPUT,
-+	.gpio5  = GPIO_DIR_INPUT,
-+	.gpio6  = GPIO_DIR_INPUT,
-+	.gpio9  = GPIO_DIR_OUTPUT,
-+	.gpio10 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio18 = GPIO_DIR_OUTPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio20 = GPIO_DIR_OUTPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_INPUT,
-+	.gpio31 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio9  = GPIO_LEVEL_HIGH,
-+	.gpio18 = GPIO_LEVEL_HIGH,
-+	.gpio20 = GPIO_LEVEL_HIGH,
-+	.gpio28 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio13 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_GPIO,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_NATIVE,
-+	.gpio52 = GPIO_MODE_NATIVE,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio32 = GPIO_DIR_INPUT,
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_INPUT,
-+	.gpio35 = GPIO_DIR_OUTPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio56 = GPIO_DIR_OUTPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio35 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_HIGH,
-+	.gpio56 = GPIO_LEVEL_HIGH,
-+	.gpio60 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio72 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio72 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode      = &pch_gpio_set1_mode,
-+		.direction = &pch_gpio_set1_direction,
-+		.level     = &pch_gpio_set1_level,
-+		.blink     = &pch_gpio_set1_blink,
-+		.invert    = &pch_gpio_set1_invert,
-+	},
-+	.set2 = {
-+		.mode      = &pch_gpio_set2_mode,
-+		.direction = &pch_gpio_set2_direction,
-+		.level     = &pch_gpio_set2_level,
-+	},
-+	.set3 = {
-+		.mode      = &pch_gpio_set3_mode,
-+		.direction = &pch_gpio_set3_direction,
-+		.level     = &pch_gpio_set3_level,
-+	},
-+};
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
-new file mode 100644
-index 0000000000..c94e06b156
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/hda_verb.c
-@@ -0,0 +1,26 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	/* coreboot specific header */
-+	0x11d4194a, /* Analog Devices AD1984A */
-+	0x10280420, /*  Subsystem ID */
-+	10,         /* Number of entries */
-+
-+	/* Pin Widget Verb Table */
-+	AZALIA_PIN_CFG(0, 0x11, 0x02214040),
-+	AZALIA_PIN_CFG(0, 0x12, 0x01014010),
-+	AZALIA_PIN_CFG(0, 0x13, 0x991301f0),
-+	AZALIA_PIN_CFG(0, 0x14, 0x02a19020),
-+	AZALIA_PIN_CFG(0, 0x15, 0x01813030),
-+	AZALIA_PIN_CFG(0, 0x16, 0x413301f0),
-+	AZALIA_PIN_CFG(0, 0x17, 0x41a601f0),
-+	AZALIA_PIN_CFG(0, 0x1a, 0x41f301f0),
-+	AZALIA_PIN_CFG(0, 0x1b, 0x414501f0),
-+	AZALIA_PIN_CFG(0, 0x1c, 0x413301f0),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
-new file mode 100644
-index 0000000000..555b1c1f5c
---- /dev/null
-+++ b/src/mainboard/dell/optiplex_780/variants/780_usff/overridetree.cb
-@@ -0,0 +1,10 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/x4x
-+	device domain 0 on
-+		chip southbridge/intel/i82801jx
-+			device pci 1c.0 on  end		# PCIe 1
-+			device pci 1c.1 on  end		# PCIe 2
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0030-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch

@@ -1,7 +1,7 @@
-From b4d48233a8d829d7285501f662d999aad898be21 Mon Sep 17 00:00:00 2001
+From 4e0b62e6f0977cf922b1947955538ddca63bb954 Mon Sep 17 00:00:00 2001
 From: Riku Viitanen <riku.viitanen@protonmail.com>
 Date: Sat, 23 Dec 2023 19:02:10 +0200
-Subject: [PATCH 10/37] mb/hp: Add Compaq Elite 8300 CMT port
+Subject: [PATCH 30/30] mb/hp: Add Compaq Elite 8300 CMT port
 
 Based on autoport and Z220 SuperIO code.
 
@@ -32,7 +32,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
 ---
  .../hp/compaq_elite_8300_cmt/Kconfig          |  39 ++++
  .../hp/compaq_elite_8300_cmt/Kconfig.name     |   2 +
- .../hp/compaq_elite_8300_cmt/Makefile.mk      |   7 +
+ .../hp/compaq_elite_8300_cmt/Makefile.inc     |   7 +
  .../hp/compaq_elite_8300_cmt/acpi/ec.asl      |   1 +
  .../compaq_elite_8300_cmt/acpi/platform.asl   |  10 +
  .../hp/compaq_elite_8300_cmt/acpi/superio.asl |  29 +++
@@ -41,17 +41,17 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
  .../hp/compaq_elite_8300_cmt/cmos.default     |   7 +
  .../hp/compaq_elite_8300_cmt/cmos.layout      |  74 +++++++
  .../hp/compaq_elite_8300_cmt/data.vbt         | Bin 0 -> 3902 bytes
- .../hp/compaq_elite_8300_cmt/devicetree.cb    | 177 ++++++++++++++++
+ .../hp/compaq_elite_8300_cmt/devicetree.cb    | 161 +++++++++++++++
  .../hp/compaq_elite_8300_cmt/dsdt.asl         |  26 +++
- .../hp/compaq_elite_8300_cmt/early_init.c     |  14 ++
+ .../hp/compaq_elite_8300_cmt/early_init.c     |  31 +++
  .../compaq_elite_8300_cmt/gma-mainboard.ads   |  17 ++
  src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++
  .../hp/compaq_elite_8300_cmt/hda_verb.c       |  33 +++
  .../hp/compaq_elite_8300_cmt/mainboard.c      |  16 ++
- 18 files changed, 660 insertions(+)
+ 18 files changed, 661 insertions(+)
  create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
  create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
  create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
  create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
  create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
@@ -121,11 +121,11 @@ index 0000000000..bd399b1e76
 @@ -0,0 +1,2 @@
 +config BOARD_HP_COMPAQ_ELITE_8300_CMT
 +	bool "Compaq Elite 8300 CMT"
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
+diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
 new file mode 100644
 index 0000000000..fb492d3583
 --- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
++++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
 @@ -0,0 +1,7 @@
 +## SPDX-License-Identifier: GPL-2.0-only
 +
@@ -353,10 +353,10 @@ HcmV?d00001
 
 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
 new file mode 100644
-index 0000000000..3d21739b72
+index 0000000000..f4efabd792
 --- /dev/null
 +++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-@@ -0,0 +1,177 @@
+@@ -0,0 +1,161 @@
 +# SPDX-License-Identifier: GPL-2.0-only
 +
 +chip northbridge/intel/sandybridge
@@ -386,22 +386,6 @@ index 0000000000..3d21739b72
 +			register "superspeed_capable_ports" = "0x0000000f"
 +			register "xhci_overcurrent_mapping" = "0x00000c03"
 +			register "xhci_switchable_ports" = "0x0000000f"
-+			register "usb_port_config" = "{
-+				{ 1, 0, 0 },
-+				{ 1, 0, 0 },
-+				{ 1, 0, 1 },
-+				{ 1, 0, 1 },
-+				{ 1, 0, 2 },
-+				{ 1, 0, 2 },
-+				{ 1, 0, 3 },
-+				{ 1, 0, 3 },
-+				{ 1, 0, 4 },
-+				{ 1, 0, 4 },
-+				{ 1, 0, 6 },
-+				{ 1, 0, 5 },
-+				{ 1, 0, 5 },
-+				{ 1, 0, 6 }
-+			}"
 +
 +			device ref xhci on   end # USB 3.0 Controller
 +			device ref mei1 off  end # Management Engine Interface 1
@@ -421,7 +405,7 @@ index 0000000000..3d21739b72
 +			device ref pcie_rp3 on end
 +			device ref pcie_rp4 on end
 +			device ref pcie_rp5 on end
-+			device ref pcie_rp6 on end
++			device ref pcie_rp5 on end
 +			device ref pcie_rp7 on end
 +			device ref pcie_rp8 on end
 +
@@ -568,10 +552,10 @@ index 0000000000..e8e2b3a3e5
 +}
 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
 new file mode 100644
-index 0000000000..8d10c6317c
+index 0000000000..99b7891c70
 --- /dev/null
 +++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
-@@ -0,0 +1,14 @@
+@@ -0,0 +1,31 @@
 +/* SPDX-License-Identifier: GPL-2.0-only */
 +
 +#include <bootblock_common.h>
@@ -581,6 +565,23 @@ index 0000000000..8d10c6317c
 +
 +#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
 +
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 0, 0 },
++	{ 1, 0, 0 },
++	{ 1, 0, 1 },
++	{ 1, 0, 1 },
++	{ 1, 0, 2 },
++	{ 1, 0, 2 },
++	{ 1, 0, 3 },
++	{ 1, 0, 3 },
++	{ 1, 0, 4 },
++	{ 1, 0, 4 },
++	{ 1, 0, 6 },
++	{ 1, 0, 5 },
++	{ 1, 0, 5 },
++	{ 1, 0, 6 },
++};
++
 +void bootblock_mainboard_early_init(void)
 +{
 +	if (CONFIG(CONSOLE_SERIAL))
@@ -868,5 +869,5 @@ index 0000000000..8dbd95ef96
 +	.enable_dev = mainboard_enable,
 +};
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0031-dell-3050micro-disable-nvme-hotplug.patch

@@ -1,49 +0,0 @@
-From 4ffaddc37d30d39f25faeaef73046a6e2ce525e8 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Wed, 11 Dec 2024 01:06:01 +0000
-Subject: [PATCH 31/37] dell/3050micro: disable nvme hotplug
-
-in my testing, when running my 3050micro for a few days,
-the nvme would sometimes randomly rename.
-
-e.g. nvme0n1 renamed to nvme0n2
-
-this might cause crashes in linux, if booting only from the
-nvme. in my case, i was booting from mdraid (sata+nvme) and
-every few days, the nvme would rename at least once, causing
-my RAID to become unsynced. since i'm using RAID1, this was
-OK and I could simply re-sync the array, but this is quite
-precarious indeed. if you're using raid0, that will potentially
-corrupt your RAID array indefinitely.
-
-this same issue manifested on the T480/T480 thinkpads, and
-S3 resume would break because of that, when booting from nvme,
-because the nvme would be "unplugged" and appear to linux as a
-new device (the one that you booted from).
-
-the fix there was to disable hotplugging on that pci-e slot
-for the nvme, so apply the same fix here for 3050 micro
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/mainboard/dell/optiplex_3050/devicetree.cb | 4 +++-
- 1 file changed, 3 insertions(+), 1 deletion(-)
-
-diff --git a/src/mainboard/dell/optiplex_3050/devicetree.cb b/src/mainboard/dell/optiplex_3050/devicetree.cb
-index da11085ab6..2a97306c5d 100644
---- a/src/mainboard/dell/optiplex_3050/devicetree.cb
-+++ b/src/mainboard/dell/optiplex_3050/devicetree.cb
-@@ -45,7 +45,9 @@ chip soc/intel/skylake
- 			register "PcieRpAdvancedErrorReporting[20]"     = "1"
- 			register "PcieRpLtrEnable[20]"                  = "true"
- 			register "PcieRpClkSrcNumber[20]"               = "3"
--			register "PcieRpHotPlug[20]"                    = "1"
-+# disable hotplug on nvme to prevent renaming e.g. nvme0n1 rename to nvme0n2,
-+# which could cause crashes in linux if booting from nvme
-+			register "PcieRpHotPlug[20]"                    = "0"
- 		end
- 
- 		# Realtek LAN
--- 
-2.39.5
-

config/coreboot/default/patches/0031-mb-dell-Add-OptiPlex-7020-9020-port_cb55232_31.patch

@@ -0,0 +1,923 @@
+From 38a713eb071dd9c1b7d5092ce686537e5d9266f5 Mon Sep 17 00:00:00 2001
+From: Mate Kukri <kukri.mate@gmail.com>
+Date: Mon, 4 Dec 2023 21:34:18 +0000
+Subject: [PATCH 1/1] mb/dell: Add OptiPlex 7020/9020 port
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The OptiPlex 7020 and 9020 use physically identical motherboards.
+
+Each model comes in the following form factors:
+- 7020: SFF, MT
+- 9020: USFF (not currently supported), SFF, MT
+
+(7020 SFF) Boots Linux and Windows 10:
+- Tested with an i3-4160 and i5-4460
+- DRAM init works using the MRC (4G, 4G+4G)
+- iGPU init works using libgfxinit (VGA, 2x DP)
+- PCIe 16x: tested, ok
+- PCIe 4x: tested, ok
+- All USB2 and USB3 ports work
+- SMSC SCH5555 Super I/O: serial works, PS/2 untested
+- Audio: back and front output works, internal speaker works,
+         mic inputs untested
+- Ethernet: tested, works
+
+(9020 MT)
+- Tested by Michael Büchler (thanks for the overridetree)
+
+Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a
+Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
+---
+ src/mainboard/dell/optiplex_9020/Kconfig      |  34 +++
+ src/mainboard/dell/optiplex_9020/Kconfig.name |  11 +
+ src/mainboard/dell/optiplex_9020/Makefile.inc |   5 +
+ src/mainboard/dell/optiplex_9020/acpi/ec.asl  |   3 +
+ .../dell/optiplex_9020/acpi/platform.asl      |  11 +
+ .../dell/optiplex_9020/acpi/superio.asl       |   3 +
+ .../dell/optiplex_9020/board_info.txt         |   8 +
+ src/mainboard/dell/optiplex_9020/bootblock.c  | 116 ++++++++++
+ src/mainboard/dell/optiplex_9020/cmos.default |   4 +
+ src/mainboard/dell/optiplex_9020/cmos.layout  |  58 +++++
+ src/mainboard/dell/optiplex_9020/data.vbt     | Bin 0 -> 4409 bytes
+ .../dell/optiplex_9020/devicetree.cb          |  80 +++++++
+ src/mainboard/dell/optiplex_9020/dsdt.asl     |  25 ++
+ .../dell/optiplex_9020/gma-mainboard.ads      |  18 ++
+ src/mainboard/dell/optiplex_9020/gpio.c       | 217 ++++++++++++++++++
+ src/mainboard/dell/optiplex_9020/hda_verb.c   |  27 +++
+ src/mainboard/dell/optiplex_9020/mainboard.c  |  15 ++
+ .../dell/optiplex_9020/overridetree_mt.cb     |  10 +
+ src/mainboard/dell/optiplex_9020/romstage.c   |  53 +++++
+ 19 files changed, 698 insertions(+)
+ create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig
+ create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig.name
+ create mode 100644 src/mainboard/dell/optiplex_9020/Makefile.inc
+ create mode 100644 src/mainboard/dell/optiplex_9020/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/optiplex_9020/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/optiplex_9020/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/optiplex_9020/board_info.txt
+ create mode 100644 src/mainboard/dell/optiplex_9020/bootblock.c
+ create mode 100644 src/mainboard/dell/optiplex_9020/cmos.default
+ create mode 100644 src/mainboard/dell/optiplex_9020/cmos.layout
+ create mode 100644 src/mainboard/dell/optiplex_9020/data.vbt
+ create mode 100644 src/mainboard/dell/optiplex_9020/devicetree.cb
+ create mode 100644 src/mainboard/dell/optiplex_9020/dsdt.asl
+ create mode 100644 src/mainboard/dell/optiplex_9020/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/optiplex_9020/gpio.c
+ create mode 100644 src/mainboard/dell/optiplex_9020/hda_verb.c
+ create mode 100644 src/mainboard/dell/optiplex_9020/mainboard.c
+ create mode 100644 src/mainboard/dell/optiplex_9020/overridetree_mt.cb
+ create mode 100644 src/mainboard/dell/optiplex_9020/romstage.c
+
+diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
+new file mode 100644
+index 0000000000..774a72f161
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/Kconfig
+@@ -0,0 +1,34 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++if BOARD_DELL_OPTIPLEX_9020_SFF || BOARD_DELL_OPTIPLEX_9020_MT
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_12288
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_OPTION_TABLE
++	select HAVE_CMOS_DEFAULT
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select NORTHBRIDGE_INTEL_HASWELL
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_LYNXPOINT
++	select SUPERIO_SMSC_SCH555x
++
++config CBFS_SIZE
++	default 0x600000
++
++config MAINBOARD_DIR
++	default "dell/optiplex_9020"
++
++config MAINBOARD_PART_NUMBER
++	default "OptiPlex 7020/9020 SFF" if BOARD_DELL_OPTIPLEX_9020_SFF
++	default "OptiPlex 7020/9020 MT" if BOARD_DELL_OPTIPLEX_9020_MT
++
++config OVERRIDE_DEVICETREE
++	default "overridetree_mt.cb" if BOARD_DELL_OPTIPLEX_9020_MT
++
++endif
+diff --git a/src/mainboard/dell/optiplex_9020/Kconfig.name b/src/mainboard/dell/optiplex_9020/Kconfig.name
+new file mode 100644
+index 0000000000..c25c330a44
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/Kconfig.name
+@@ -0,0 +1,11 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++config BOARD_DELL_OPTIPLEX_9020_SFF
++	bool "OptiPlex 7020/9020 SFF"
++	help
++	  The 7020 SFF and 9020 SFF mainboards are physically identical.
++
++config BOARD_DELL_OPTIPLEX_9020_MT
++	bool "OptiPlex 7020/9020 MT"
++	help
++	  The 7020 MT and 9020 MT mainboards are physically identical.
+diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc
+new file mode 100644
+index 0000000000..6ca2f2afaa
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/Makefile.inc
+@@ -0,0 +1,5 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
++bootblock-y += bootblock.c
+diff --git a/src/mainboard/dell/optiplex_9020/acpi/ec.asl b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
+new file mode 100644
+index 0000000000..16990d45f4
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: CC-PDDC */
++
++/* Please update the license if adding licensable material. */
+diff --git a/src/mainboard/dell/optiplex_9020/acpi/platform.asl b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
+new file mode 100644
+index 0000000000..cda7682e3e
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
+@@ -0,0 +1,11 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	Return(Package() { 0, 0 })
++}
++
++Method(_PTS, 1)
++{
++
++}
+diff --git a/src/mainboard/dell/optiplex_9020/acpi/superio.asl b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
+new file mode 100644
+index 0000000000..16990d45f4
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: CC-PDDC */
++
++/* Please update the license if adding licensable material. */
+diff --git a/src/mainboard/dell/optiplex_9020/board_info.txt b/src/mainboard/dell/optiplex_9020/board_info.txt
+new file mode 100644
+index 0000000000..e30cf9c41f
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/board_info.txt
+@@ -0,0 +1,8 @@
++Vendor name: Dell Inc.
++Board name: OptiPlex 7020/9020
++Release year: 2014
++Category: desktop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
+diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
+new file mode 100644
+index 0000000000..2837cf9cf1
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/bootblock.c
+@@ -0,0 +1,116 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <arch/io.h>
++#include <device/pnp_ops.h>
++#include <superio/smsc/sch555x/sch555x.h>
++#include <southbridge/intel/lynxpoint/pch.h>
++
++static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
++{
++	// Clear EC-to-Host mailbox
++	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
++	outb(tmp, SCH555x_EMI_IOBASE + 1);
++
++	// Send address and value to the EC
++	sch555x_emi_write16(0, (addr1 * 2) | 0x101);
++	sch555x_emi_write32(4, val | (addr2 << 16));
++
++	// Wait for acknowledgement message from EC
++	outb(1, SCH555x_EMI_IOBASE);
++	size_t timeout = 0;
++	do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
++}
++
++struct ec_init_entry {
++	uint16_t addr;
++	uint8_t val;
++};
++
++static void ec_init(void)
++{
++	/*
++	 * Tables from CORE_PEI
++	 */
++
++	static const struct ec_init_entry init_table1[] = {
++		{0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10},
++		{0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10},
++		{0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12},
++		{0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12},
++		{0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10},
++		{0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11},
++	};
++
++	for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i)
++		ec_write(2, init_table1[i].addr, init_table1[i].val);
++
++	static const struct ec_init_entry init_table2[] = {
++		{0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f},
++		{0x0083, 0xbb}, {0x0085, 0xd9}, {0x0086, 0x2c}, {0x008a, 0x34},
++		{0x008b, 0x60}, {0x0090, 0x5e}, {0x0091, 0x5e}, {0x0092, 0x86},
++		{0x0096, 0xa4}, {0x0097, 0xa4}, {0x0098, 0xa4}, {0x009b, 0xa4},
++		{0x00a0, 0x0a}, {0x00a1, 0x0a}, {0x00ae, 0x7c}, {0x00af, 0x7c},
++		{0x00b0, 0x9e}, {0x00b3, 0x7c}, {0x00b6, 0x08}, {0x00b7, 0x08},
++		{0x00ea, 0x64}, {0x00ef, 0xff}, {0x00f8, 0x15}, {0x00f9, 0x00},
++		{0x00f0, 0x30}, {0x00fd, 0x01}, {0x01a1, 0x00}, {0x01a2, 0x00},
++		{0x01b1, 0x08}, {0x01be, 0x90}, {0x0280, 0x24}, {0x0281, 0x13},
++		{0x0282, 0x03}, {0x0283, 0x0a}, {0x0284, 0x80}, {0x0285, 0x03},
++		{0x0288, 0x80}, {0x0289, 0x0c}, {0x028a, 0x03}, {0x028b, 0x0a},
++		{0x028c, 0x80}, {0x028d, 0x03}, {0x0040, 0x01},
++	};
++
++	for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i)
++		ec_write(1, init_table2[i].addr, init_table2[i].val);
++
++	/*
++	 * Table from PeiHwmInit
++	 */
++
++	static const struct ec_init_entry hwm_init_table[] = {
++		{0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f},
++		{0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33},
++		{0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff},
++		{0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00},
++		{0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00},
++		{0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80},
++		{0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02},
++		{0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04},
++		{0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50},
++		{0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50},
++		{0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c},
++		{0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd},
++		{0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e},
++		{0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00},
++		{0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff},
++		{0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00},
++		{0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c},
++		{0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02},
++		{0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03},
++	};
++
++	for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i)
++		ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val);
++}
++
++#define SCH555x_IOBASE	0x2e
++#define GLOBAL_DEV	PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL)
++#define SERIAL_DEV	PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1)
++
++void mainboard_config_superio(void)
++{
++	// Super I/O early init will map Runtime and EMI registers
++	sch555x_early_init(GLOBAL_DEV);
++
++	// Changes LED color among a few other things (extracted from Dell's FW)
++	outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS);
++	outb(0x00, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN);
++	outb(0x18, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN1);
++	outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
++	outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
++
++	// Magic EC init
++	ec_init();
++
++	// Magic EC init is needed for UART1 initialization to work
++	sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
++}
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
+new file mode 100644
+index 0000000000..b159660aa8
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/cmos.default
+@@ -0,0 +1,4 @@
++boot_option=Fallback
++debug_level=Debug
++nmi=Disable
++power_on_after_fail=Disable
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
+new file mode 100644
+index 0000000000..c9ba76c78f
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/cmos.layout
+@@ -0,0 +1,58 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	3	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	4	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	5	power_on_after_fail
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++
++2	0	Enable
++2	1	Disable
++
++3	0	Fallback
++3	1	Normal
++
++4	0	Emergency
++4	1	Alert
++4	2	Critical
++4	3	Error
++4	4	Warning
++4	5	Notice
++4	6	Info
++4	7	Debug
++4	8	Spew
++
++5	0	Disable
++5	1	Enable
++5	2	Keep
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 415 984
+diff --git a/src/mainboard/dell/optiplex_9020/data.vbt b/src/mainboard/dell/optiplex_9020/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..1779f3b8d1018ba0aae480103b145bd7b6dd6187
+GIT binary patch
+literal 4409
+zcmdT{T}&KR6h8B_yR)-1!!lr9XiE<T5h_au1f&hdSy<_UtKG6lH%+yR*`>u$pi5g@
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+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
+new file mode 100644
+index 0000000000..c0b17a15ff
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
+@@ -0,0 +1,80 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++chip northbridge/intel/haswell
++	# This mainboard has VGA
++	register "gpu_ddi_e_connected" = "1"
++
++	chip cpu/intel/haswell
++		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
++	end
++
++	device domain 0 on
++		ops haswell_pci_domain_ops
++
++		subsystemid 0x1028 0x05a5 inherit
++
++		device pci 00.0 on  end					# Host bridge
++		device pci 01.0 on  end					# PCIe graphics
++		device pci 02.0 on  end					# VGA controller
++		device pci 03.0 on  end					# Mini-HD audio
++
++		chip southbridge/intel/lynxpoint
++			register "gen1_dec" = "0x007c0a01"
++			register "gen2_dec" = "0x007c0901"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x001c0901"
++			register "sata_port_map" = "0x33"
++
++			device pci 14.0 on  end				# xHCI controller
++			device pci 16.0 on  end				# Management Engine interface 1
++			device pci 16.1 off end				# Management Engine interface 2
++			device pci 16.2 off end				# Management Engine IDE-R
++			device pci 16.3 on  end				# Management Engine KT
++			device pci 19.0 on      			# Intel Gigabit Ethernet
++				subsystemid 0x1028 0x05a4
++			end
++			device pci 1a.0 on  end				# EHCI controller #2
++			device pci 1b.0 on  end				# HD audio controller
++			device pci 1c.0 off end
++			device pci 1c.1 off end
++			device pci 1c.2 off end
++			device pci 1c.3 off end
++			device pci 1c.4 on  end				# PCIe 4x slot
++			device pci 1c.5 off end
++			device pci 1c.6 off end
++			device pci 1c.7 off end
++			device pci 1d.0 on  end				# EHCI controller #1
++			device pci 1f.0 on				# LPC bridge
++				chip superio/smsc/sch555x
++					device pnp 2e.0 on		# EMI
++						io 0x60 = 0xa00
++					end
++					device pnp 2e.1 on		# 8042
++						io 0x60 = 0x60
++						irq 0x0f = 0
++						irq 0x70 = 1
++						irq 0x72 = 12
++					end
++					device pnp 2e.7 on		# UART1
++						io 0x60 = 0x3f8
++						irq 0x0f = 2
++						irq 0x70 = 4
++					end
++					device pnp 2e.8 off end 	# UART2
++					device pnp 2e.c on		# LPC interface
++						io 0x60 = 0x2e
++					end
++					device pnp 2e.a on		# Runtime registers
++						io 0x60 = 0xa40
++					end
++					device pnp 2e.b  off end	# Floppy Controller
++					device pnp 2e.11 off end	# Parallel Port
++				end
++			end
++			device pci 1f.2 on  end				# SATA controller 1
++			device pci 1f.3 on  end				# SMBus
++			device pci 1f.5 off end				# SATA controller 2
++			device pci 1f.6 off end				# Thermal
++		end
++	end
++end
+diff --git a/src/mainboard/dell/optiplex_9020/dsdt.asl b/src/mainboard/dell/optiplex_9020/dsdt.asl
+new file mode 100644
+index 0000000000..7ec1e9775a
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/dsdt.asl
+@@ -0,0 +1,25 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi.h>
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20181031	/* OEM Revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++	#include <cpu/intel/common/acpi/cpu.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
++		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
+new file mode 100644
+index 0000000000..173f2f1d0d
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
+@@ -0,0 +1,18 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (DP1,
++      DP2,
++      DP3,
++      Analog,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/optiplex_9020/gpio.c b/src/mainboard/dell/optiplex_9020/gpio.c
+new file mode 100644
+index 0000000000..48b7707e2c
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/gpio.c
+@@ -0,0 +1,217 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_GPIO,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_GPIO,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_GPIO,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_NATIVE,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_NATIVE,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_NATIVE,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_GPIO,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_GPIO,
++	.gpio26 = GPIO_MODE_GPIO,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_NATIVE,
++	.gpio30 = GPIO_MODE_NATIVE,
++	.gpio31 = GPIO_MODE_GPIO,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio1 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio5 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio11 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_OUTPUT,
++	.gpio15 = GPIO_DIR_OUTPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_OUTPUT,
++	.gpio23 = GPIO_DIR_OUTPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio25 = GPIO_DIR_OUTPUT,
++	.gpio26 = GPIO_DIR_OUTPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_OUTPUT,
++	.gpio31 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio13 = GPIO_LEVEL_LOW,
++	.gpio15 = GPIO_LEVEL_HIGH,
++	.gpio22 = GPIO_LEVEL_HIGH,
++	.gpio23 = GPIO_LEVEL_HIGH,
++	.gpio25 = GPIO_LEVEL_HIGH,
++	.gpio26 = GPIO_LEVEL_HIGH,
++	.gpio28 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++	.gpio18 = GPIO_BLINK,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio8 = GPIO_INVERT,
++	.gpio9 = GPIO_INVERT,
++	.gpio11 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++	.gpio26 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_GPIO,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_NATIVE,
++	.gpio37 = GPIO_MODE_NATIVE,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_GPIO,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_GPIO,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_GPIO,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_GPIO,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_GPIO,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio32 = GPIO_DIR_INPUT,
++	.gpio33 = GPIO_DIR_OUTPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio44 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio46 = GPIO_DIR_INPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_INPUT,
++	.gpio50 = GPIO_DIR_OUTPUT,
++	.gpio51 = GPIO_DIR_OUTPUT,
++	.gpio52 = GPIO_DIR_OUTPUT,
++	.gpio53 = GPIO_DIR_OUTPUT,
++	.gpio54 = GPIO_DIR_OUTPUT,
++	.gpio55 = GPIO_DIR_OUTPUT,
++	.gpio57 = GPIO_DIR_OUTPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio33 = GPIO_LEVEL_HIGH,
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio50 = GPIO_LEVEL_HIGH,
++	.gpio51 = GPIO_LEVEL_HIGH,
++	.gpio52 = GPIO_LEVEL_HIGH,
++	.gpio53 = GPIO_LEVEL_HIGH,
++	.gpio54 = GPIO_LEVEL_HIGH,
++	.gpio55 = GPIO_LEVEL_HIGH,
++	.gpio57 = GPIO_LEVEL_HIGH,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_GPIO,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_GPIO,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_NATIVE,
++	.gpio71 = GPIO_MODE_NATIVE,
++	.gpio72 = GPIO_MODE_GPIO,
++	.gpio73 = GPIO_MODE_GPIO,
++	.gpio74 = GPIO_MODE_GPIO,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio64 = GPIO_DIR_OUTPUT,
++	.gpio66 = GPIO_DIR_OUTPUT,
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio72 = GPIO_DIR_OUTPUT,
++	.gpio73 = GPIO_DIR_INPUT,
++	.gpio74 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++	.gpio64 = GPIO_LEVEL_HIGH,
++	.gpio66 = GPIO_LEVEL_HIGH,
++	.gpio72 = GPIO_LEVEL_HIGH,
++	.gpio74 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 =	{
++		.mode = &pch_gpio_set1_mode,
++		.direction = &pch_gpio_set1_direction,
++		.level = &pch_gpio_set1_level,
++		.blink = &pch_gpio_set1_blink,
++		.invert = &pch_gpio_set1_invert,
++		.reset = &pch_gpio_set1_reset,
++	},
++	.set2 =	{
++		.mode = &pch_gpio_set2_mode,
++		.direction = &pch_gpio_set2_direction,
++		.level = &pch_gpio_set2_level,
++		.reset = &pch_gpio_set2_reset,
++	},
++	.set3 =	{
++		.mode = &pch_gpio_set3_mode,
++		.direction = &pch_gpio_set3_direction,
++		.level = &pch_gpio_set3_level,
++		.reset = &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/optiplex_9020/hda_verb.c b/src/mainboard/dell/optiplex_9020/hda_verb.c
+new file mode 100644
+index 0000000000..df43ade3e6
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/hda_verb.c
+@@ -0,0 +1,27 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <stdint.h>
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x10ec0280, /* Realtek ALC3220 */
++	0x102805a5, /* Subsystem ID */
++	13,	 /* Number of entries */
++	AZALIA_SUBVENDOR(0, 0x102805a5),
++	AZALIA_PIN_CFG(0, 0x12, 0x4008c000),
++	AZALIA_PIN_CFG(0, 0x13, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x15, 0x0221401f),
++	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x18, 0x01a13040),
++	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x1a, 0x02a19030),
++	AZALIA_PIN_CFG(0, 0x1b, 0x01014020),
++	AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
++	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
++};
++
++const u32 pc_beep_verbs[] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
+new file mode 100644
+index 0000000000..c834fea5d3
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/mainboard.c
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++
++static void mainboard_enable(struct device *dev)
++{
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
+new file mode 100644
+index 0000000000..90205c2d68
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
+@@ -0,0 +1,10 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++chip northbridge/intel/haswell
++	device domain 0 on
++		chip southbridge/intel/lynxpoint
++			device pci 1c.1 on  end	# PCI (via XIO2001 bridge)
++			device pci 1c.2 on  end	# PCIe 1x slot
++		end
++	end
++end
+diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c
+new file mode 100644
+index 0000000000..2b9cdaa5fd
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/romstage.c
+@@ -0,0 +1,53 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <northbridge/intel/haswell/haswell.h>
++#include <northbridge/intel/haswell/raminit.h>
++#include <southbridge/intel/lynxpoint/pch.h>
++
++void mainboard_config_rcba(void)
++{
++	RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQC, PIRQD, PIRQA);
++	RCBA16(D29IR) = DIR_ROUTE(PIRQC, PIRQA, PIRQD, PIRQH);
++	RCBA16(D28IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
++	RCBA16(D27IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQG);
++	RCBA16(D26IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQF, PIRQA);
++	RCBA16(D25IR) = DIR_ROUTE(PIRQH, PIRQG, PIRQF, PIRQE);
++	RCBA16(D22IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQA);
++	RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
++}
++
++void mb_get_spd_map(struct spd_info *spdi)
++{
++	spdi->addresses[0] = 0x50;
++	spdi->addresses[1] = 0x51;
++	spdi->addresses[2] = 0x52;
++	spdi->addresses[3] = 0x53;
++}
++
++const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
++	/* Length, Enable, OCn#, Location */
++	{0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
++	{0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
++	{0x0040, 1, 1, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 2, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 3, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 3, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 0, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 0, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 4, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 4, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 5, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 5, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 6, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 7, USB_PORT_BACK_PANEL},
++};
++
++const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
++	/* Enable, OCn# */
++	{1, 6},
++	{1, 7},
++	{0, USB_OC_PIN_SKIP},
++	{0, USB_OC_PIN_SKIP},
++	{1, 1},
++	{1, 2},
++};
+-- 
+2.39.2
+

config/coreboot/default/patches/0032-lenovo-Add-Kconfig-option-CONFIG_LENOVO_TBFW_BIN.patch

@@ -1,78 +0,0 @@
-From 5d8930edfa1d9537ba80e24c0cf8f0c9e4e9ec72 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Wed, 18 Dec 2024 02:06:18 +0000
-Subject: [PATCH 32/37] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
-
-This is used by lbmk to know where a tb.bin file goes,
-when extracting and padding TBT.bin from Lenovo ThunderBolt
-firmware updates on T480/T480s and other machines, grabbing
-Lenovo update files.
-
-Not used in any builds, so it's not relevant for ./mk inject
-
-However, the ThunderBolt firmware is now auto-downloaded on
-T480/T480s. This is not inserted, because it doesn't go in
-the main flash, but the resulting ROM image can be flashed
-on the TB controller's separate flash chip.
-
-Locations are as follows:
-
-vendorfiles/t480s/tb.bin
-vendorfiles/t480/tb.bin
-
-This can be used for other affected ThinkPads when they're
-added to Libreboot, but note that Lenovo provides different
-TB firmware files for each machine.
-
-Since I assume it's the same TB controller on all of those
-machines, I have to wonder: what difference is there between
-the various TBT.bin files provided by Lenovo, and how do they
-differ in terms of actual flashed configuration?
-
-We simply flash the padded TBT.bin when updating the firmware,
-flashing externally. That's what this patch is for, so that
-lbmk can auto-download them.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/mainboard/lenovo/Kconfig | 26 ++++++++++++++++++++++++++
- 1 file changed, 26 insertions(+)
-
-diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
-index 2ffbaab85f..512b326381 100644
---- a/src/mainboard/lenovo/Kconfig
-+++ b/src/mainboard/lenovo/Kconfig
-@@ -18,4 +18,30 @@ config MAINBOARD_FAMILY
- 	string
- 	default MAINBOARD_PART_NUMBER
- 
-+config LENOVO_TBFW_BIN
-+	string "Lenovo ThunderBolt firmware bin file"
-+	default ""
-+	help
-+	  ThunderBolt firmware for certain ThinkPad models e.g. T480.
-+	  Not used in the actual build. Libreboot's build system uses this
-+	  along with config/vendor/*/pkg.cfg entries defining a URL to the
-+	  Lenovo download link and hash. The resulting file when processed by
-+	  lbmk can be flashed to the ThunderBolt firmware's 25XX NOR device.
-+	  Earlier versions of this firmware had debug commands enabled that
-+	  sent logs to said flash IC, and it would quickly fill up, bricking
-+	  the ThunderBolt controller. With these updates, flashed externally,
-+	  you can fix the issue if present or otherwise prevent it. The benefit
-+	  here is that you then don't need to use Windows or a boot disk. You
-+	  can flash the TB firmware while flashing Libreboot firmware. Easy!
-+	  Look for these variables in lbmk:
-+	  TBFW_url TBFW_url_bkup TBFW_hash and look at how it handles that and
-+	  CONFIG_LENOVO_TBFW_BIN, in lbmk's include/vendor.sh file.
-+	  The path set by CONFIG_LENOVO_TBFW_BIN is used by lbmk when extracting
-+	  the firmware, putting it at that desired location. In this way, lbmk
-+	  can auto-download such firmware. E.g. ./mk -d coreboot t480_fsp_16mb
-+	  and it appears at vendorfiles/t480/tb.bin fully padded and everything!
-+
-+	  Just leave this blank if you don't care about this option. It's not
-+	  useful for every ThinkPad, only certain models.
-+
- endif # VENDOR_LENOVO
--- 
-2.39.5
-

config/coreboot/default/patches/0032-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch

@@ -0,0 +1,774 @@
+From 41002e64c92e90903fa591c4a8a1cc0108833743 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sun, 26 Nov 2023 17:08:52 -0700
+Subject: [PATCH] mb/dell: Add Latitude E6420 (Sandy Bridge)
+
+Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6420/Kconfig           |  38 ++++
+ src/mainboard/dell/e6420/Kconfig.name      |   2 +
+ src/mainboard/dell/e6420/Makefile.inc      |   6 +
+ src/mainboard/dell/e6420/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e6420/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e6420/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e6420/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e6420/board_info.txt    |   6 +
+ src/mainboard/dell/e6420/cmos.default      |   9 +
+ src/mainboard/dell/e6420/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e6420/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e6420/devicetree.cb     |  66 +++++++
+ src/mainboard/dell/e6420/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e6420/early_init.c      |  32 ++++
+ src/mainboard/dell/e6420/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e6420/gpio.c            | 191 +++++++++++++++++++++
+ src/mainboard/dell/e6420/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e6420/mainboard.c       |  21 +++
+ 18 files changed, 582 insertions(+)
+ create mode 100644 src/mainboard/dell/e6420/Kconfig
+ create mode 100644 src/mainboard/dell/e6420/Kconfig.name
+ create mode 100644 src/mainboard/dell/e6420/Makefile.inc
+ create mode 100644 src/mainboard/dell/e6420/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e6420/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e6420/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e6420/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e6420/board_info.txt
+ create mode 100644 src/mainboard/dell/e6420/cmos.default
+ create mode 100644 src/mainboard/dell/e6420/cmos.layout
+ create mode 100644 src/mainboard/dell/e6420/data.vbt
+ create mode 100644 src/mainboard/dell/e6420/devicetree.cb
+ create mode 100644 src/mainboard/dell/e6420/dsdt.asl
+ create mode 100644 src/mainboard/dell/e6420/early_init.c
+ create mode 100644 src/mainboard/dell/e6420/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e6420/gpio.c
+ create mode 100644 src/mainboard/dell/e6420/hda_verb.c
+ create mode 100644 src/mainboard/dell/e6420/mainboard.c
+
+diff --git a/src/mainboard/dell/e6420/Kconfig b/src/mainboard/dell/e6420/Kconfig
+new file mode 100644
+index 0000000000..cff62bf70c
+--- /dev/null
++++ b/src/mainboard/dell/e6420/Kconfig
+@@ -0,0 +1,38 @@
++if BOARD_DELL_LATITUDE_E6420
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_10240
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_BD82X6X
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e6420"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E6420"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0126"
++
++endif # BOARD_DELL_LATITUDE_E6420
+diff --git a/src/mainboard/dell/e6420/Kconfig.name b/src/mainboard/dell/e6420/Kconfig.name
+new file mode 100644
+index 0000000000..1722891e7b
+--- /dev/null
++++ b/src/mainboard/dell/e6420/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E6420
++	bool "Latitude E6420"
+diff --git a/src/mainboard/dell/e6420/Makefile.inc b/src/mainboard/dell/e6420/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e6420/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6420/acpi/ec.asl b/src/mainboard/dell/e6420/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e6420/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6420/acpi/platform.asl b/src/mainboard/dell/e6420/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e6420/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e6420/acpi/superio.asl b/src/mainboard/dell/e6420/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e6420/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e6420/acpi_tables.c b/src/mainboard/dell/e6420/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e6420/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e6420/board_info.txt b/src/mainboard/dell/e6420/board_info.txt
+new file mode 100644
+index 0000000000..34d5ad9e0b
+--- /dev/null
++++ b/src/mainboard/dell/e6420/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2011
+diff --git a/src/mainboard/dell/e6420/cmos.default b/src/mainboard/dell/e6420/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e6420/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e6420/cmos.layout b/src/mainboard/dell/e6420/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e6420/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e6420/data.vbt b/src/mainboard/dell/e6420/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd
+GIT binary patch
+literal 6144
+zcmeHKeQZ-z6hE);wSBvNZ|mO1=*HLC2BQN8uVX6{N9eY)75ORymb$R8!YYuAZEgeE
+zKk|S@Fen*n41W-viAF;r%)~^EkpLz-B{2q##)LmGAtoY;7*Qhv_1yPbw$TC$2}G0K
+z=6Ao&x#ym9?z!i_&TOh(kLzky2cN8MTpny#R<;VU4Rkn?rBIz(YL~BBw<%b&zGhSH
+z$~AQ>@D0d=Xx6RE0BwSxspWdrW9y<FZGD@&x3_JL;p$p!;!BVdcKLkht0=-%(Jj&T
+z_GkyztZ%>#t7^)^(T-R<7W?O6ZTI%A+j=`<Jw3Q%dk6N!da<_?7oyiU3)^<~_TiSk
+zE$y+=RK3PGQ`gzmXYPRBx>C|f*UP9{h|4>ANrAe~?ymV*)83AaT#FuTjP=C2cg5P~
+zt4w78r$t#300cWY_k)mevmAmFI3&oBfytoAAPQiYK$XEIgHwV@5-gJ-Q-*p8yfTDj
+zaDz=1Y!X1B3`OpQ&Ik}bM|0xHn0gYNZw0rT=7AXS2in-q8K^?)0|el+Z6geW7i7MM
+zv~!|>HqL-|Fk}EYOa@)R<X)VQ7c}d8R1b@RTn5rq(90|QRg0?wwZZz(6Dz}w>zg9Y
+z8;!mD_V*XSjT33~$`o`s>zEGBq8AQ`HaH?y!Fh2QiX1v@aCo4LaENf&DZ_cE2A2qb
+z5@cC}X)=S^1RvpXLWs~v*hqMau$!=t@B-mg!XV)|;eEm>!Z6`H;R4|&!d1d`f|S7^
+zli+B98*!TfPE&6~NVM5j3v{N3OTjpnm_L@BPh(}esd(J!gj?~iJP?n|OZZOiTqlql
+zg<NWR@g&-*W-E%A7|*1Z_`sVO$K&iAP+VIj9{<1hT%SXsK}IBk8!daftR`6-)EUiS
+zvv*HR(#-ZwhA~7wcmxbe4%E?Y7P0y{1q|nqR1L29UR8v@#No^g5MH)7!>{%-$T|cR
+zZx5|xm>Fl>;@$m};P{0WC>O~<Nl1`*PLgPN_hP2a^h+L$ls&SYrkDYr+&l*%%S?^Q
+ziPSdtHE<LNEnr7cs=ihL-C>-p>*$9CpHRLgN|POkqD^UP4nw|4nf0bc8MOBk<;%js
+zfpCAWNzqSPlz@X%j9CGrwZDKUl@K{g6pzqiIIARDQ)#@^RW&0pmNG;XZ?!SlHB?L#
+zKRAMgq(R;aQd%@Gy38-LS@ix)fR**(P3B9wI=Uk^&cWmmwB<vf21<0#LBA!;qtAh(
+zYe5g_T{+gw^mi8QzPPraBoH~8oCz%r=$nVi1A)`Y8IKqIdqm6MihqxtpFaTggaPxu
+zQP07nf#&kPkPp}Cmk$F1g7q7QK;kz~80i&oDN}~wYbPUI6AtG5H+$T!@f5FzUhp21
+z^XiPT3rb%B@sA9g!n88R7BOsLS|?+D3}0v3dyIX|@JFWo&e%<c#V)PV#g@7-=F*;V
+zvAr&Q+ogTvVxPM3XP5Smi`f;Nt7uCU)}Y`HMcbpW=M_AuXlE35PQl+4O{7m66&I@7
+zGL@}Sai^*sP}va`KTx$VRQ8REf2*1+lTFH0=UkNx+eN|1rVyipl)Du=h=@%w+iQZG
+zT6@-PdW^oyFb44AG`HMZWEnP{&OQ+jC`N4emoS)x;EPN}uaSFOf-Mn8JRRO&LTWJc
+zn6%=L94~PR)%Ua_HTZcfTXD<p{%8p|<N<;Efw$Zb4$}{m8@7c((~<7^thaau&@Wx#
+zVGNL)lmH@{o=h*{muXGc!;nXrVgpp3;1V1stMj=4AtxyzX+?SoB~zN}!*r?9Qvs1P
+zmV_(CTmt0sY&6=F=_M>E34GYvuh1uQF+BUdWyQC5SaEM1QvKlHBMs13C}n{0SwRxW
+ziekMa&kvRFruRcKCevGy5)TxUBDlur@E{TtQ^NQ>nO+Cgl)&Ga(PxqVW?e3TLH-UY
+zdL3T{z^xdd`$(STFUb8R*cKa}r>n{Wk+MXRH~o-hN}#9OF*>T#>rfhiRs(Wc-R^9@
+z%F=<}dn(E}ADc03zJ>JvZe;_8f+WFLL4%qNYs`_aa`a$Pl5H;iO^Wt*cP3W(d=(g}
+zZ%nKT1$|r-tAv8($u2-BI2Uiz#%OT&!Q3b~Ru2P2j;Gem!@wfPsTR%J>W{8z)oq^J
+k^Qm&?O@bFkw4CTocwoW<6CRlGz=Q`TJTT#bN9KWl0rH4|j{pDw
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e6420/devicetree.cb b/src/mainboard/dell/e6420/devicetree.cb
+new file mode 100644
+index 0000000000..f9259f7175
+--- /dev/null
++++ b/src/mainboard/dell/e6420/devicetree.cb
+@@ -0,0 +1,66 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x0000054f"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x0493 inherit
++
++		device ref host_bridge on end # Host bridge
++		device ref peg10 on end # PEG
++		device ref igd on end # iGPU
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x007c0901"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x001c0901"
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x3b"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++
++			device ref mei1		off end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	off end
++			device ref gbe		on end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end
++			device ref pcie_rp2	on end
++			device ref pcie_rp3	on end
++			device ref pcie_rp4	on end
++			device ref pcie_rp5	off end
++			device ref pcie_rp6	on end
++			device ref pcie_rp7	off end
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1 on end
++			device ref smbus on end
++			device ref sata2 off end
++			device ref thermal off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e6420/dsdt.asl b/src/mainboard/dell/e6420/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e6420/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e6420/early_init.c b/src/mainboard/dell/e6420/early_init.c
+new file mode 100644
+index 0000000000..0682441ed6
+--- /dev/null
++++ b/src/mainboard/dell/e6420/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 0, 2 },
++	{ 1, 1, 2 },
++	{ 1, 1, 3 },
++	{ 1, 1, 3 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 1, 7 },
++	{ 1, 1, 6 },
++	{ 1, 0, 6 },
++	{ 1, 0, 7 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e6420/gma-mainboard.ads b/src/mainboard/dell/e6420/gma-mainboard.ads
+new file mode 100644
+index 0000000000..2a16f44360
+--- /dev/null
++++ b/src/mainboard/dell/e6420/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, -- mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e6420/gpio.c b/src/mainboard/dell/e6420/gpio.c
+new file mode 100644
+index 0000000000..943c743f48
+--- /dev/null
++++ b/src/mainboard/dell/e6420/gpio.c
+@@ -0,0 +1,191 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_NATIVE,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_NATIVE,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_GPIO,
++	.gpio31 = GPIO_MODE_GPIO,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_INPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++	.gpio30 = GPIO_DIR_OUTPUT,
++	.gpio31 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio30 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_NATIVE,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_OUTPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio49 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_NATIVE,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e6420/hda_verb.c b/src/mainboard/dell/e6420/hda_verb.c
+new file mode 100644
+index 0000000000..b3803b7c65
+--- /dev/null
++++ b/src/mainboard/dell/e6420/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
++	0x10280493,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x10280493),
++	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862805,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e6420/mainboard.c b/src/mainboard/dell/e6420/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e6420/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.43.0
+

config/coreboot/default/patches/0033-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch

@@ -0,0 +1,773 @@
+From 5e8bff81220d4d0f663feed443e4594b76e442bf Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Wed, 31 Jan 2024 22:07:25 -0700
+Subject: [PATCH] mb/dell: Add Latitude E6520 (Sandy Bridge)
+
+Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6520/Kconfig           |  38 +++++
+ src/mainboard/dell/e6520/Kconfig.name      |   2 +
+ src/mainboard/dell/e6520/Makefile.inc      |   6 +
+ src/mainboard/dell/e6520/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e6520/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e6520/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e6520/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e6520/board_info.txt    |   6 +
+ src/mainboard/dell/e6520/cmos.default      |   9 +
+ src/mainboard/dell/e6520/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e6520/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e6520/devicetree.cb     |  66 +++++++
+ src/mainboard/dell/e6520/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e6520/early_init.c      |  32 ++++
+ src/mainboard/dell/e6520/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e6520/gpio.c            | 190 +++++++++++++++++++++
+ src/mainboard/dell/e6520/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e6520/mainboard.c       |  21 +++
+ 18 files changed, 581 insertions(+)
+ create mode 100644 src/mainboard/dell/e6520/Kconfig
+ create mode 100644 src/mainboard/dell/e6520/Kconfig.name
+ create mode 100644 src/mainboard/dell/e6520/Makefile.inc
+ create mode 100644 src/mainboard/dell/e6520/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e6520/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e6520/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e6520/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e6520/board_info.txt
+ create mode 100644 src/mainboard/dell/e6520/cmos.default
+ create mode 100644 src/mainboard/dell/e6520/cmos.layout
+ create mode 100644 src/mainboard/dell/e6520/data.vbt
+ create mode 100644 src/mainboard/dell/e6520/devicetree.cb
+ create mode 100644 src/mainboard/dell/e6520/dsdt.asl
+ create mode 100644 src/mainboard/dell/e6520/early_init.c
+ create mode 100644 src/mainboard/dell/e6520/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e6520/gpio.c
+ create mode 100644 src/mainboard/dell/e6520/hda_verb.c
+ create mode 100644 src/mainboard/dell/e6520/mainboard.c
+
+diff --git a/src/mainboard/dell/e6520/Kconfig b/src/mainboard/dell/e6520/Kconfig
+new file mode 100644
+index 0000000000..db9f25b4ac
+--- /dev/null
++++ b/src/mainboard/dell/e6520/Kconfig
+@@ -0,0 +1,38 @@
++if BOARD_DELL_LATITUDE_E6520
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_10240
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_BD82X6X
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e6520"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E6520"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0116"
++
++endif # BOARD_DELL_LATITUDE_E6520
+diff --git a/src/mainboard/dell/e6520/Kconfig.name b/src/mainboard/dell/e6520/Kconfig.name
+new file mode 100644
+index 0000000000..25968e80e5
+--- /dev/null
++++ b/src/mainboard/dell/e6520/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E6520
++	bool "Latitude E6520"
+diff --git a/src/mainboard/dell/e6520/Makefile.inc b/src/mainboard/dell/e6520/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e6520/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6520/acpi/ec.asl b/src/mainboard/dell/e6520/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e6520/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6520/acpi/platform.asl b/src/mainboard/dell/e6520/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e6520/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e6520/acpi/superio.asl b/src/mainboard/dell/e6520/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e6520/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e6520/acpi_tables.c b/src/mainboard/dell/e6520/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e6520/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e6520/board_info.txt b/src/mainboard/dell/e6520/board_info.txt
+new file mode 100644
+index 0000000000..34d5ad9e0b
+--- /dev/null
++++ b/src/mainboard/dell/e6520/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2011
+diff --git a/src/mainboard/dell/e6520/cmos.default b/src/mainboard/dell/e6520/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e6520/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e6520/cmos.layout b/src/mainboard/dell/e6520/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e6520/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e6520/data.vbt b/src/mainboard/dell/e6520/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
+GIT binary patch
+literal 6144
+zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN)
+z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y
+z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+
+z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7
+zcXx+--0R}IwzW3-+`f2k?^Av5V7MpRO-q(9rn_R1@Xlz2Ztdy`$Gf6^w6~|bKi!!7
+z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ
+z)4V8f0Gt`D`+>9Fr~tnJ76EJ`5D_F1cn-`0$RgN9unI6kfYkzIiO?W`ON4+34lv1_
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+O?SW|zOncy=dEg(6JAK&z
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e6520/devicetree.cb b/src/mainboard/dell/e6520/devicetree.cb
+new file mode 100644
+index 0000000000..cfba8ef4e7
+--- /dev/null
++++ b/src/mainboard/dell/e6520/devicetree.cb
+@@ -0,0 +1,66 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00001312"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x0494 inherit
++
++		device ref host_bridge on end # Host bridge
++		device ref peg10 on end # PEG
++		device ref igd on end # iGPU
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x007c0901"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x001c0901"
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x3b"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++
++			device ref mei1		off end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	off end
++			device ref gbe		on end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end
++			device ref pcie_rp2	on end
++			device ref pcie_rp3	on end
++			device ref pcie_rp4	on end
++			device ref pcie_rp5	off end
++			device ref pcie_rp6	on end
++			device ref pcie_rp7	off end
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1 on end
++			device ref smbus on end
++			device ref sata2 off end
++			device ref thermal off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e6520/dsdt.asl b/src/mainboard/dell/e6520/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e6520/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e6520/early_init.c b/src/mainboard/dell/e6520/early_init.c
+new file mode 100644
+index 0000000000..2a37091df6
+--- /dev/null
++++ b/src/mainboard/dell/e6520/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 0, 2 },
++	{ 1, 1, 2 },
++	{ 1, 0, 3 },
++	{ 1, 0, 3 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 1, 7 },
++	{ 1, 1, 6 },
++	{ 1, 0, 6 },
++	{ 1, 0, 7 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e6520/gma-mainboard.ads b/src/mainboard/dell/e6520/gma-mainboard.ads
+new file mode 100644
+index 0000000000..2a16f44360
+--- /dev/null
++++ b/src/mainboard/dell/e6520/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, -- mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e6520/gpio.c b/src/mainboard/dell/e6520/gpio.c
+new file mode 100644
+index 0000000000..61f01816c4
+--- /dev/null
++++ b/src/mainboard/dell/e6520/gpio.c
+@@ -0,0 +1,190 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_NATIVE,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_NATIVE,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_GPIO,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_INPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++	.gpio30 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio30 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_NATIVE,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_OUTPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio49 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_NATIVE,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e6520/hda_verb.c b/src/mainboard/dell/e6520/hda_verb.c
+new file mode 100644
+index 0000000000..d33eb3b4c5
+--- /dev/null
++++ b/src/mainboard/dell/e6520/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
++	0x10280494,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x10280494),
++	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862805,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e6520/mainboard.c b/src/mainboard/dell/e6520/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e6520/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.43.0
+

config/coreboot/default/patches/0033-soc-intel-skylake-Don-t-compress-FSP-S.patch

@@ -1,36 +0,0 @@
-From 49cee334bc7fe9a78b9355b5256a37984bac385a Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Thu, 26 Dec 2024 19:45:20 +0000
-Subject: [PATCH 33/37] soc/intel/skylake: Don't compress FSP-S
-
-Build systems like lbmk need to reproducibly insert
-certain vendor files on release images.
-
-Compression isn't always reproducible, and making it
-so costs a lot more time than simply disabling compression.
-
-With this change, the FSP-S module will now be inserted
-without compression, which means that there will now be
-about 40KB of extra space used in the flash.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/soc/intel/skylake/Kconfig | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index 9191ed0ff8..d51ffaef7b 100644
---- a/src/soc/intel/skylake/Kconfig
-+++ b/src/soc/intel/skylake/Kconfig
-@@ -12,7 +12,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
- 	select CPU_SUPPORTS_PM_TIMER_EMULATION
- 	select DRIVERS_USB_ACPI
- 	select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
--	select FSP_COMPRESS_FSP_S_LZ4
-+#	select FSP_COMPRESS_FSP_S_LZ4
- 	select FSP_M_XIP
- 	select GENERIC_GPIO_LIB
- 	select HAVE_FSP_GOP
--- 
-2.39.5
-

config/coreboot/default/patches/0034-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch

@@ -0,0 +1,780 @@
+From 86911e57c556389eed386bc23d5e87dd520afec9 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Wed, 31 Jan 2024 22:57:07 -0700
+Subject: [PATCH] mb/dell: Add Latitude E5530 (Ivy Bridge)
+
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e5530/Kconfig           |  37 ++++
+ src/mainboard/dell/e5530/Kconfig.name      |   2 +
+ src/mainboard/dell/e5530/Makefile.inc      |   6 +
+ src/mainboard/dell/e5530/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e5530/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e5530/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e5530/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e5530/board_info.txt    |   6 +
+ src/mainboard/dell/e5530/cmos.default      |   9 +
+ src/mainboard/dell/e5530/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e5530/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e5530/devicetree.cb     |  70 ++++++++
+ src/mainboard/dell/e5530/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e5530/early_init.c      |  32 ++++
+ src/mainboard/dell/e5530/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e5530/gpio.c            | 194 +++++++++++++++++++++
+ src/mainboard/dell/e5530/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e5530/mainboard.c       |  21 +++
+ 18 files changed, 588 insertions(+)
+ create mode 100644 src/mainboard/dell/e5530/Kconfig
+ create mode 100644 src/mainboard/dell/e5530/Kconfig.name
+ create mode 100644 src/mainboard/dell/e5530/Makefile.inc
+ create mode 100644 src/mainboard/dell/e5530/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e5530/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e5530/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e5530/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e5530/board_info.txt
+ create mode 100644 src/mainboard/dell/e5530/cmos.default
+ create mode 100644 src/mainboard/dell/e5530/cmos.layout
+ create mode 100644 src/mainboard/dell/e5530/data.vbt
+ create mode 100644 src/mainboard/dell/e5530/devicetree.cb
+ create mode 100644 src/mainboard/dell/e5530/dsdt.asl
+ create mode 100644 src/mainboard/dell/e5530/early_init.c
+ create mode 100644 src/mainboard/dell/e5530/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e5530/gpio.c
+ create mode 100644 src/mainboard/dell/e5530/hda_verb.c
+ create mode 100644 src/mainboard/dell/e5530/mainboard.c
+
+diff --git a/src/mainboard/dell/e5530/Kconfig b/src/mainboard/dell/e5530/Kconfig
+new file mode 100644
+index 0000000000..3faae4ee50
+--- /dev/null
++++ b/src/mainboard/dell/e5530/Kconfig
+@@ -0,0 +1,37 @@
++if BOARD_DELL_LATITUDE_E5530
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_12288
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_C216
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e5530"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E5530"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0166"
++
++endif # BOARD_DELL_LATITUDE_E5530
+diff --git a/src/mainboard/dell/e5530/Kconfig.name b/src/mainboard/dell/e5530/Kconfig.name
+new file mode 100644
+index 0000000000..775963204a
+--- /dev/null
++++ b/src/mainboard/dell/e5530/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E5530
++	bool "Latitude E5530"
+diff --git a/src/mainboard/dell/e5530/Makefile.inc b/src/mainboard/dell/e5530/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e5530/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e5530/acpi/ec.asl b/src/mainboard/dell/e5530/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e5530/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e5530/acpi/platform.asl b/src/mainboard/dell/e5530/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e5530/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e5530/acpi/superio.asl b/src/mainboard/dell/e5530/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e5530/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e5530/acpi_tables.c b/src/mainboard/dell/e5530/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e5530/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e5530/board_info.txt b/src/mainboard/dell/e5530/board_info.txt
+new file mode 100644
+index 0000000000..4601a4aaba
+--- /dev/null
++++ b/src/mainboard/dell/e5530/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2012
+diff --git a/src/mainboard/dell/e5530/cmos.default b/src/mainboard/dell/e5530/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e5530/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e5530/cmos.layout b/src/mainboard/dell/e5530/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e5530/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e5530/data.vbt b/src/mainboard/dell/e5530/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3
+GIT binary patch
+literal 6144
+zcmeHKU2Gdg5dO}0w$JA~+qs02q)iz56C9e5vuQ#oL0l3O+%|395Q2peO{y4(2uX0t
+zuMja1N)bPb1cE+5)fYsCK!89MFQAGChyWpk5PuR<K|G+sLmxmOR4}u5=Rg`mj70g7
+zvgdDic6N4dW^QKhynd)>kS^cR)3#-(r*-?zo-O^C(kLvv8XM<+Y3tdt^YY!P?!oTe
+zJ^ed-x6w0Lh5fN#jsv5TWE#mtd*_yky}9xDK(kOwLt+C7_AQAd#iwr=o0`gvQZ`{x
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+Jz~2*rUjdP?m;3+#
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e5530/devicetree.cb b/src/mainboard/dell/e5530/devicetree.cb
+new file mode 100644
+index 0000000000..2af748cf27
+--- /dev/null
++++ b/src/mainboard/dell/e5530/devicetree.cb
+@@ -0,0 +1,70 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00000000"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x03d003d0"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x053d inherit
++
++		device ref host_bridge on end
++		device ref peg10 off end
++		device ref igd on end
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x005c0921"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x33"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++			register "superspeed_capable_ports" = "0x0000000f"
++			register "xhci_overcurrent_mapping" = "0x00000c03"
++			register "xhci_switchable_ports" = "0x0000000f"
++
++			device ref xhci		on end
++			device ref mei1		off end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	off end
++			device ref gbe		off end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end # WWAN Slot
++			device ref pcie_rp2	on end # SLAN Slot
++			device ref pcie_rp3	on end # ExpressCard
++			device ref pcie_rp4	off end
++			device ref pcie_rp5	on end # Extra Half Mini PCIe slot
++			device ref pcie_rp6	on end # SD/MMC Card Reader
++			device ref pcie_rp7	on end # BCM5761 Ethernet
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1	on end
++			device ref smbus	on end
++			device ref sata2	off end
++			device ref thermal	off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e5530/dsdt.asl b/src/mainboard/dell/e5530/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e5530/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e5530/early_init.c b/src/mainboard/dell/e5530/early_init.c
+new file mode 100644
+index 0000000000..00fd5f6795
+--- /dev/null
++++ b/src/mainboard/dell/e5530/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 1, 2 },
++	{ 1, 1, 2 },
++	{ 1, 1, 3 },
++	{ 1, 0, 3 },
++	{ 1, 2, 4 },
++	{ 1, 1, 4 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 0, 6 },
++	{ 1, 1, 6 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e5530/gma-mainboard.ads b/src/mainboard/dell/e5530/gma-mainboard.ads
+new file mode 100644
+index 0000000000..1310830c8e
+--- /dev/null
++++ b/src/mainboard/dell/e5530/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, --mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e5530/gpio.c b/src/mainboard/dell/e5530/gpio.c
+new file mode 100644
+index 0000000000..0599f13921
+--- /dev/null
++++ b/src/mainboard/dell/e5530/gpio.c
+@@ -0,0 +1,194 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_GPIO,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_GPIO,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_NATIVE,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio1 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio12 = GPIO_DIR_OUTPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_OUTPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio12 = GPIO_LEVEL_HIGH,
++	.gpio28 = GPIO_LEVEL_LOW,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++	.gpio30 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio13 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_GPIO,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_INPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_INPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_INPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio53 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_GPIO,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++	.gpio74 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e5530/hda_verb.c b/src/mainboard/dell/e5530/hda_verb.c
+new file mode 100644
+index 0000000000..4c7c36ee05
+--- /dev/null
++++ b/src/mainboard/dell/e5530/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76df,	/* Codec Vendor / Device ID: IDT */
++	0x1028053d,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x1028053d),
++	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0),
++
++	0x80862806,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e5530/mainboard.c b/src/mainboard/dell/e5530/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e5530/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.43.0
+

config/coreboot/default/patches/0034-soc-intel-pmc-Hardcoded-poweroff-after-power-fail.patch

@@ -1,82 +0,0 @@
-From 09740dc9d43a8dc24b7416b70476796515af6581 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 31 Dec 2024 01:40:42 +0000
-Subject: [PATCH 34/37] soc/intel/pmc: Hardcoded poweroff after power fail
-
-Coreboot can set the power state for power on after previous
-power failure, based on the option table. On the ThinkPad T480,
-we have no nvram and, due to coreboot's design, we therefore
-have no option table, so the default setting is enabled.
-
-In my testing, this seems to be that the system will turn on
-after a power failure. If your ThinkPad was previously in a state
-where it wouldn't turn on when plugging in the power, it'd be fine.
-
-If your battery ran out later on, this would be triggered and
-your ThinkPad would permanently turn on, when plugging in a charger,
-and there is currently no way to configure this behaviour.
-
-We currently only use the common SoC PMC code on the ThinkPad
-T480, T480s and the Dell OptiPlex 3050 Micro, at the time of
-this patch, and it is desirable that the system be set to power
-off after power fail anyway.
-
-In some cases, you might want the opposite, for example if you're
-running a server. This will be documented on the website, for that
-reason.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/soc/intel/common/block/pmc/pmclib.c | 36 +++----------------------
- 1 file changed, 4 insertions(+), 32 deletions(-)
-
-diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
-index 64b9bb997c..7823775bcb 100644
---- a/src/soc/intel/common/block/pmc/pmclib.c
-+++ b/src/soc/intel/common/block/pmc/pmclib.c
-@@ -776,38 +776,10 @@ void pmc_clear_pmcon_sts(void)
- 
- void pmc_set_power_failure_state(const bool target_on)
- {
--	const unsigned int state = get_uint_option("power_on_after_fail",
--					 CONFIG_MAINBOARD_POWER_FAILURE_STATE);
--
--	/*
--	 * On the shutdown path (target_on == false), we only need to
--	 * update the register for MAINBOARD_POWER_STATE_PREVIOUS. For
--	 * all other cases, we don't write the register to avoid clob-
--	 * bering the value set on the boot path. This is necessary,
--	 * for instance, when we can't access the option backend in SMM.
--	 */
--
--	switch (state) {
--	case MAINBOARD_POWER_STATE_OFF:
--		if (!target_on)
--			break;
--		printk(BIOS_INFO, "Set power off after power failure.\n");
--		pmc_soc_set_afterg3_en(false);
--		break;
--	case MAINBOARD_POWER_STATE_ON:
--		if (!target_on)
--			break;
--		printk(BIOS_INFO, "Set power on after power failure.\n");
--		pmc_soc_set_afterg3_en(true);
--		break;
--	case MAINBOARD_POWER_STATE_PREVIOUS:
--		printk(BIOS_INFO, "Keep power state after power failure.\n");
--		pmc_soc_set_afterg3_en(target_on);
--		break;
--	default:
--		printk(BIOS_WARNING, "Unknown power-failure state: %d\n", state);
--		break;
--	}
-+	if (!target_on)
-+		return;
-+	printk(BIOS_INFO, "Set power off after power failure.\n");
-+	pmc_soc_set_afterg3_en(false);
- }
- 
- /* This function returns the highest assertion duration of the SLP_Sx assertion widths */
--- 
-2.39.5
-

config/coreboot/default/patches/0035-hp8560w-Add-MXM-System-Infomation-Structure.patch

@@ -0,0 +1,41 @@
+From b2cf0657a2058118baf6f4ec96e356de3c9e493e Mon Sep 17 00:00:00 2001
+From: Riku Viitanen <riku.viitanen@protonmail.com>
+Date: Sun, 11 Feb 2024 19:02:20 +0200
+Subject: [PATCH] hp8560w: Add MXM System Infomation Structure
+
+Change-Id: I45b421f2d7baf8ca8dedbd3b1ab1e38392b6219b
+Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
+---
+ src/mainboard/hp/snb_ivb_laptops/Makefile.mk      |   6 ++++++
+ .../hp/snb_ivb_laptops/variants/8560w/mxm-30-sis  | Bin 0 -> 129 bytes
+ 2 files changed, 6 insertions(+)
+ create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
+
+diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
+index c007bb68cd..7950abbc4e 100644
+--- a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
++++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
+@@ -9,3 +9,9 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb
+ 
+ # FIXME: Other variants with same size onboard RAM may exist.
+ SPD_SOURCES = hynix_4g
++
++ifeq ($(CONFIG_BOARD_HP_8560W),y)
++cbfs-files-y += mxm-30-sis
++mxm-30-sis-file := variants/$(VARIANT_DIR)/mxm-30-sis
++mxm-30-sis-type := raw
++endif
+diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
+new file mode 100644
+index 0000000000000000000000000000000000000000..7e4e245a50d8d5d36ddb22e3b1aed3fa87a2f57d
+GIT binary patch
+literal 129
+zcmeZ`@Qr6?sAMn@-0}aX9Rou`%?mKiz;Fq|&xF!hw;=rNM_^h3Dy{$(SAdE$zF=lx
+o@?l{RW{6;7W}LwIl$Vj2apDSgHUS2PJFE;0Kxqas5d=FN0HAs+0RR91
+
+literal 0
+HcmV?d00001
+
+-- 
+2.43.1
+

config/coreboot/default/patches/0035-mb-dell-Add-Latitude-E5520-Sandybridge.patch

@@ -0,0 +1,775 @@
+From 7c7ce2087e1ff5f0eedb65793254163d01be3056 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Wed, 7 Feb 2024 10:23:38 -0700
+Subject: [PATCH] mb/dell: Add Latitude E5520 (Sandybridge)
+
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e5520/Kconfig           |  37 ++++
+ src/mainboard/dell/e5520/Kconfig.name      |   2 +
+ src/mainboard/dell/e5520/Makefile.inc      |   5 +
+ src/mainboard/dell/e5520/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e5520/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e5520/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e5520/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e5520/board_info.txt    |   6 +
+ src/mainboard/dell/e5520/cmos.default      |   9 +
+ src/mainboard/dell/e5520/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e5520/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e5520/devicetree.cb     |  66 +++++++
+ src/mainboard/dell/e5520/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e5520/early_init.c      |  32 ++++
+ src/mainboard/dell/e5520/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e5520/gpio.c            | 195 +++++++++++++++++++++
+ src/mainboard/dell/e5520/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e5520/mainboard.c       |  21 +++
+ 18 files changed, 584 insertions(+)
+ create mode 100644 src/mainboard/dell/e5520/Kconfig
+ create mode 100644 src/mainboard/dell/e5520/Kconfig.name
+ create mode 100644 src/mainboard/dell/e5520/Makefile.inc
+ create mode 100644 src/mainboard/dell/e5520/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e5520/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e5520/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e5520/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e5520/board_info.txt
+ create mode 100644 src/mainboard/dell/e5520/cmos.default
+ create mode 100644 src/mainboard/dell/e5520/cmos.layout
+ create mode 100644 src/mainboard/dell/e5520/data.vbt
+ create mode 100644 src/mainboard/dell/e5520/devicetree.cb
+ create mode 100644 src/mainboard/dell/e5520/dsdt.asl
+ create mode 100644 src/mainboard/dell/e5520/early_init.c
+ create mode 100644 src/mainboard/dell/e5520/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e5520/gpio.c
+ create mode 100644 src/mainboard/dell/e5520/hda_verb.c
+ create mode 100644 src/mainboard/dell/e5520/mainboard.c
+
+diff --git a/src/mainboard/dell/e5520/Kconfig b/src/mainboard/dell/e5520/Kconfig
+new file mode 100644
+index 0000000000..213c54cf5c
+--- /dev/null
++++ b/src/mainboard/dell/e5520/Kconfig
+@@ -0,0 +1,37 @@
++if BOARD_DELL_LATITUDE_E5520
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_6144
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_BD82X6X
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e5520"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E5520"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0126"
++
++endif # BOARD_DELL_LATITUDE_E5520
+diff --git a/src/mainboard/dell/e5520/Kconfig.name b/src/mainboard/dell/e5520/Kconfig.name
+new file mode 100644
+index 0000000000..c88913e8b3
+--- /dev/null
++++ b/src/mainboard/dell/e5520/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E5520
++	bool "Latitude E5520"
+diff --git a/src/mainboard/dell/e5520/Makefile.inc b/src/mainboard/dell/e5520/Makefile.inc
+new file mode 100644
+index 0000000000..18391d8b18
+--- /dev/null
++++ b/src/mainboard/dell/e5520/Makefile.inc
+@@ -0,0 +1,5 @@
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e5520/acpi/ec.asl b/src/mainboard/dell/e5520/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e5520/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e5520/acpi/platform.asl b/src/mainboard/dell/e5520/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e5520/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e5520/acpi/superio.asl b/src/mainboard/dell/e5520/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e5520/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e5520/acpi_tables.c b/src/mainboard/dell/e5520/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e5520/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e5520/board_info.txt b/src/mainboard/dell/e5520/board_info.txt
+new file mode 100644
+index 0000000000..34d5ad9e0b
+--- /dev/null
++++ b/src/mainboard/dell/e5520/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2011
+diff --git a/src/mainboard/dell/e5520/cmos.default b/src/mainboard/dell/e5520/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e5520/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e5520/cmos.layout b/src/mainboard/dell/e5520/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e5520/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e5520/data.vbt b/src/mainboard/dell/e5520/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729
+GIT binary patch
+literal 6144
+zcmeHKZ){Ul6hE);wSBvNZ|mL$bmQOM2BTvXUI!}^N9ejTij1vnu+)Wx6<c9(Y_%K6
+zzOV-@f<ehpWB5RHBpMBgG7}RuMuM2=l*E{6G$wq&gqTQ3#E2RZsOP@dvW*rP7>Fjj
+z&F`Lj?>YC}bI(2Z+}C+6zKyiGrosQXuW7A+&1%<rN+Y1ck(}dLrx)Ma#^x>lnvFGE
+zeD#gB>*#Tq4&j^|7Xcz1r^pp*)g#T}u1Me3ct>Pgls5Qi3!6e2W0%`a-Ic|3efWuR
+zXJ@#}wJyGMTXTcY<%@TBKh@(3hP$Gjv}E}rx-%9D_eLXhYe!c&-VyDg-Cdo1>Biji
+zNNsnlFW#|jdoOj?mZ43m>cVO%UE9@*E7x|%V~c4`XD4l9GCi~@+7pfMibfX8L?!^I
+zc~Rg1I5SxH1DAEZ0{jA41jrJBh#-l;b6^%g7QrThRe)&%tQH_!ggOD7A_PRRgGuI0
+z0zi=n#rCB66d-sO$M~^6wgeb$2fH1|0R`v}xUiWCU`4SF;Dyh&j|mK&6WJWJ&Pq9I
+zVgmFQfh+)vE}(KWwHA|Oh3fSkss|;2E(2i}s1?gRRV%8!K7U={vHD=s#+Fd)W^M1j
+z{R4$??VSvEWpgT=vCM&1-U$bI6CB~IV3Z$$Vv7o!EDnev4j~R(MHsazZ~^fLLKGF4
+zEfQFOa3dZ?1Q1P#&4?!vyAk^k&m&$z3?WV+-b0*1j37o4=MX<3E+eiYge(Ht2umAW
+zOPDmU>UL{flI9u|@JtVvfp#o8ek?VfVV9YP5(%pnZX~{PKq4WoWGmV8t$=Ri@{zLQ
+zNYYt4<$0Ry&qIoG;7s-t333)Nu8opN{NG!)&!I@eO(cVx8vBVEBvotJ7%yNl$7iQ_
+zI=xk30+V$ff`F6<wRoF(TK%j9nsr#H23umU%)_7jNOl%*FPU567qbg;4gtp711nj2
+z#+kHw`v4|5cA+`UMIvAl;slnH1nl0v=xH<al>1}ljxDE1dcda^&!do|r^eJkI?aC-
+zEQMSfm?<w*Unzumkj_w5>VYL6W4=aCiy4rk%xq~5LV?bi|GL2$G7li<%c7yd;6T34
+zQBN5huZ3~6`ChGkpb$Bg5ITb#2iK-qs|1`=sl6Dhn(Lj&8Agt?S{sTDmmtRj7Jm_1
+zFnt{w&FdFkWS3bl>OeL?eO+*i{)9G!cSI-InGt|U0eEYmRCOHm7|I;#LO8ksRIeJ#
+zGe+jTwPg4C4TYuN(9zULV3k+hI$YuPo=%N8oZ#u_4S!3Xelt6N0BmuC`hCNeg+&97
+z6*!>)uHvr%2004GZv?!_-y&|TRmil=9D%Q`1aXBsnD^gov3*UZI34&1_vn(B=T4kZ
+z_A>ClXVIBNaS^hd&^DrU6VgZMYeadMkdFxcktn|ra-Gl;n^I{bt86rCQ=YMry*B!$
+zP5ID9KDE)GZOY#^VwPyRq^y+48j0?ZlzxdkC()CV@`*&wO7vGr;qjA3rb}gIwM-gi
+zx>HsT$mEDj-<OpyWb%zn|B@A3Hkp<!FT5;hrt_SZiy?*wDaIu{h>%Ir=@rh7)SR;b
+zAEWQGv_X1)wq0y5Ha0c~&psIsln<Hiu3;#Lf;%*eI<@?p8cfMJV(IYi8q$NA#iS8`
+z_~|4t4b^wtMSAeFST^F8-Tm<zu8D&j^8=&I4;I}Im>aeSK~X8*^Z9SE44_`P#KIUL
+zf6^N2f>5HCPWM3N+f0MyWOV^kz~!-wVc4MRXOY>4Jsxd1RyBKEMzNf{RKhesKFdbq
+zJ(*d<l2Y#n?E?~iBA39P?~Pr2d#}5=#Sfl-VGzGUF$4U2KcqCIVlwkC(&7PQk_X!a
+z8}3Jgq-&U*Co|h1>l)ZQGyW_x->i#;FvQ*=Nv&nG0N5@D@jjv_Q}K}6MP?1A6`JGe
+zDwj9pN+x;T4>`I9e5x(uqdK#OGB31ikk@Xv=dxLb4fx(;ktX@rOb~M~?dYQQYiPia
+z8r;jUQ?sd2@3||-cb2Eb%JFYfxHsONoaJ^eqoKN{<g9?-%`7oWz+aJS0tEc!^d@hD
+z1-I{%hr!Y?0uVZpUbl__37xn@jkD6Z>3SATgBQlEoN7&ZV9Eni9+>jLln16fFy(=V
+H=7E0zE^L4Z
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e5520/devicetree.cb b/src/mainboard/dell/e5520/devicetree.cb
+new file mode 100644
+index 0000000000..bef96ac14c
+--- /dev/null
++++ b/src/mainboard/dell/e5520/devicetree.cb
+@@ -0,0 +1,66 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00000218"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x049a inherit
++
++		device ref host_bridge on end # Host bridge
++		device ref peg10 on end # PEG
++		device ref igd on end # iGPU
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x007c0901"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x001c0901"
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x3b"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++
++			device ref mei1		off end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	off end
++			device ref gbe		off end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end
++			device ref pcie_rp2	on end
++			device ref pcie_rp3	on end
++			device ref pcie_rp4	off end
++			device ref pcie_rp5	on end
++			device ref pcie_rp6	on end
++			device ref pcie_rp7	on end
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1 on end
++			device ref smbus on end
++			device ref sata2 off end
++			device ref thermal off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e5520/dsdt.asl b/src/mainboard/dell/e5520/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e5520/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e5520/early_init.c b/src/mainboard/dell/e5520/early_init.c
+new file mode 100644
+index 0000000000..7297921546
+--- /dev/null
++++ b/src/mainboard/dell/e5520/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 1, 2 },
++	{ 1, 1, 2 },
++	{ 1, 1, 3 },
++	{ 1, 1, 3 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 1, 7 },
++	{ 1, 1, 6 },
++	{ 1, 1, 6 },
++	{ 1, 1, 7 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e5520/gma-mainboard.ads b/src/mainboard/dell/e5520/gma-mainboard.ads
+new file mode 100644
+index 0000000000..2a16f44360
+--- /dev/null
++++ b/src/mainboard/dell/e5520/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, -- mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e5520/gpio.c b/src/mainboard/dell/e5520/gpio.c
+new file mode 100644
+index 0000000000..f76b93d9f0
+--- /dev/null
++++ b/src/mainboard/dell/e5520/gpio.c
+@@ -0,0 +1,195 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_NATIVE,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_GPIO,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_NATIVE,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_GPIO,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio12 = GPIO_DIR_OUTPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_INPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++	.gpio30 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio12 = GPIO_LEVEL_HIGH,
++	.gpio30 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_NATIVE,
++	.gpio46 = GPIO_MODE_GPIO,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_NATIVE,
++	.gpio50 = GPIO_MODE_GPIO,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_GPIO,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_GPIO,
++	.gpio56 = GPIO_MODE_GPIO,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_OUTPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio46 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio50 = GPIO_DIR_OUTPUT,
++	.gpio51 = GPIO_DIR_OUTPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio53 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio55 = GPIO_DIR_OUTPUT,
++	.gpio56 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_LOW,
++	.gpio37 = GPIO_LEVEL_LOW,
++	.gpio46 = GPIO_LEVEL_HIGH,
++	.gpio50 = GPIO_LEVEL_HIGH,
++	.gpio51 = GPIO_LEVEL_LOW,
++	.gpio55 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_NATIVE,
++	.gpio69 = GPIO_MODE_NATIVE,
++	.gpio70 = GPIO_MODE_NATIVE,
++	.gpio71 = GPIO_MODE_NATIVE,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_GPIO,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio74 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e5520/hda_verb.c b/src/mainboard/dell/e5520/hda_verb.c
+new file mode 100644
+index 0000000000..e2efee3646
+--- /dev/null
++++ b/src/mainboard/dell/e5520/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
++	0x1028049a,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x1028049a),
++	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862805,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e5520/mainboard.c b/src/mainboard/dell/e5520/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e5520/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.43.0
+

config/coreboot/default/patches/0035-src-intel-skylake-Disable-stack-overflow-debug-optio.patch

@@ -1,61 +0,0 @@
-From 18f4e970ebda43dd538f74398aea463a67040dd3 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 6 Jan 2025 01:36:23 +0000
-Subject: [PATCH 35/37] src/intel/skylake: Disable stack overflow debug options
-
-The option was appearing in T480/3050micro configs of lbmk,
-after updating on the coreboot/next uprev for 20241206 rev8:
-
-CONFIG_DEBUG_STACK_OVERFLOW_BREAKPOINTS=y
-
-I did some digging. See coreboot commit:
-
-commit 51cc2bacb6b07279b97e9934d079060475481fb6
-Author: Subrata Banik <subratabanik@google.com>
-Date:   Fri Dec 13 13:07:28 2024 +0530
-
-    soc/intel/pantherlake: Disable stack overflow debug options
-
-Well now:
-
-I'm disabling this behaviour on Skylake, for the same
-behaviour, because I want as few behaviour changes in general,
-as possible, for the rev8 release.
-
-According to Subrata's patch, which was for Pantherlake,
-without this change, stack corruption can occur on verstage
-and romstage early on. Please look at that coreboot patch,
-referenced above, for clarity.
-
-I see no harm in disabling this option for Skylake, since
-the behaviour that it otherwise enables was not present
-before.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/soc/intel/skylake/Kconfig | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
-index d51ffaef7b..42af82a5d8 100644
---- a/src/soc/intel/skylake/Kconfig
-+++ b/src/soc/intel/skylake/Kconfig
-@@ -129,6 +129,15 @@ config DCACHE_RAM_SIZE
- 	  The size of the cache-as-ram region required during bootblock
- 	  and/or romstage.
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+	bool
-+	default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+	bool
-+	default n
-+
- config DCACHE_BSP_STACK_SIZE
- 	hex
- 	default 0x20400 if FSP_USES_CB_STACK
--- 
-2.39.5
-

config/coreboot/default/patches/0036-nb-intel-haswell-make-IOMMU-a-runtime-option.patch

@@ -0,0 +1,292 @@
+From 7c755b4502ea007f2216ea76f2ed734452def883 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Sat, 2 Mar 2024 22:51:09 +0000
+Subject: [PATCH 1/2] nb/intel/haswell: make IOMMU a runtime option
+
+When I tested graphics cards on a coreboot port for Dell
+OptiPlex 9020 SFF, I could not use a graphics card unless
+I set iommu=off on the Linux cmdline.
+
+Coreboot's current behaviour is to check whether the CPU
+has vt-d support and, if it does, initialise the IOMMU.
+
+This patch maintains the current behaviour by default, but
+allows the user to turn *off* the IOMMU, even if vt-d is
+supported by the host CPU.
+
+If iommu=Disable is specified, the check will not be
+performed, and the IOMMU will be left disabled. This option
+has been added to all current Haswell boards, though it is
+recommended to leave the IOMMU turned on in most setups.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/mainboard/asrock/b85m_pro4/cmos.default    | 1 +
+ src/mainboard/asrock/b85m_pro4/cmos.layout     | 3 +++
+ src/mainboard/asrock/h81m-hds/cmos.default     | 1 +
+ src/mainboard/asrock/h81m-hds/cmos.layout      | 6 ++++++
+ src/mainboard/dell/optiplex_9020/cmos.default  | 1 +
+ src/mainboard/dell/optiplex_9020/cmos.layout   | 6 ++++++
+ src/mainboard/google/beltino/cmos.layout       | 5 +++++
+ src/mainboard/google/slippy/cmos.layout        | 5 +++++
+ src/mainboard/intel/baskingridge/cmos.layout   | 4 ++++
+ src/mainboard/lenovo/haswell/cmos.default      | 1 +
+ src/mainboard/lenovo/haswell/cmos.layout       | 3 +++
+ src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
+ src/mainboard/supermicro/x10slm-f/cmos.layout  | 6 ++++++
+ src/northbridge/intel/haswell/early_init.c     | 5 +++++
+ 14 files changed, 48 insertions(+)
+
+diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default
+index c51001c03c..1c5c17f841 100644
+--- a/src/mainboard/asrock/b85m_pro4/cmos.default
++++ b/src/mainboard/asrock/b85m_pro4/cmos.default
+@@ -2,3 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ nmi=Enable
+ power_on_after_fail=Disable
++iommu=Enable
+diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout
+index efdc333fc2..c9883ea71d 100644
+--- a/src/mainboard/asrock/b85m_pro4/cmos.layout
++++ b/src/mainboard/asrock/b85m_pro4/cmos.layout
+@@ -11,6 +11,7 @@
+ 	395	4	e	4	debug_level
+ 	408	1	e	1	nmi
+ 	409	2	e	5	power_on_after_fail
++	412	1	e	6	iommu
+ 	984	16	h	0	check_sum
+ # -----------------------------------------------------------------
+ 
+@@ -38,6 +39,8 @@
+ 	5	0	Disable
+ 	5	1	Enable
+ 	5	2	Keep
++	6	0	Disable
++	6	1	Enable
+ # -----------------------------------------------------------------
+ 
+ # -----------------------------------------------------------------
+diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default
+index c51001c03c..1c5c17f841 100644
+--- a/src/mainboard/asrock/h81m-hds/cmos.default
++++ b/src/mainboard/asrock/h81m-hds/cmos.default
+@@ -2,3 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ nmi=Enable
+ power_on_after_fail=Disable
++iommu=Enable
+diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout
+index c9ba76c78f..95ee3d36fb 100644
+--- a/src/mainboard/asrock/h81m-hds/cmos.layout
++++ b/src/mainboard/asrock/h81m-hds/cmos.layout
+@@ -21,6 +21,9 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	5	power_on_after_fail
+ 
++# enable or disable iommu
++412	1	e	6	iommu
++
+ # coreboot config options: check sums
+ 984	16	h	0	check_sum
+ 
+@@ -52,6 +55,9 @@ enumerations
+ 5	1	Enable
+ 5	2	Keep
+ 
++6	0	Disable
++6	1	Enable
++
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
+index b159660aa8..8253570f19 100644
+--- a/src/mainboard/dell/optiplex_9020/cmos.default
++++ b/src/mainboard/dell/optiplex_9020/cmos.default
+@@ -2,3 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ nmi=Disable
+ power_on_after_fail=Disable
++iommu=Enable
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
+index c9ba76c78f..72ff9c4bee 100644
+--- a/src/mainboard/dell/optiplex_9020/cmos.layout
++++ b/src/mainboard/dell/optiplex_9020/cmos.layout
+@@ -21,6 +21,9 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	5	power_on_after_fail
+ 
++# turn iommu on or off
++412	1	e	6	iommu
++
+ # coreboot config options: check sums
+ 984	16	h	0	check_sum
+ 
+@@ -52,6 +55,9 @@ enumerations
+ 5	1	Enable
+ 5	2	Keep
+ 
++6	0	Disable
++6	1	Enable
++
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout
+index 78d44c1415..c143979ae1 100644
+--- a/src/mainboard/google/beltino/cmos.layout
++++ b/src/mainboard/google/beltino/cmos.layout
+@@ -19,6 +19,9 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	7	power_on_after_fail
+ 
++# enable or disable iommu
++412	1	e	8	iommu
++
+ # coreboot config options: bootloader
+ #Used by ChromeOS:
+ 416	128	r	0	vbnv
+@@ -47,6 +50,8 @@ enumerations
+ 7	0	Disable
+ 7	1	Enable
+ 7	2	Keep
++8	0	Disable
++8	1	Enable
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout
+index 78d44c1415..c143979ae1 100644
+--- a/src/mainboard/google/slippy/cmos.layout
++++ b/src/mainboard/google/slippy/cmos.layout
+@@ -19,6 +19,9 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	7	power_on_after_fail
+ 
++# enable or disable iommu
++412	1	e	8	iommu
++
+ # coreboot config options: bootloader
+ #Used by ChromeOS:
+ 416	128	r	0	vbnv
+@@ -47,6 +50,8 @@ enumerations
+ 7	0	Disable
+ 7	1	Enable
+ 7	2	Keep
++8	0	Disable
++8	1	Enable
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout
+index 78d44c1415..f2c602f541 100644
+--- a/src/mainboard/intel/baskingridge/cmos.layout
++++ b/src/mainboard/intel/baskingridge/cmos.layout
+@@ -19,6 +19,8 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	7	power_on_after_fail
+ 
++412	1	e	8	iommu
++
+ # coreboot config options: bootloader
+ #Used by ChromeOS:
+ 416	128	r	0	vbnv
+@@ -47,6 +49,8 @@ enumerations
+ 7	0	Disable
+ 7	1	Enable
+ 7	2	Keep
++8	0	Disable
++8	1	Enable
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default
+index bb8626d48b..051658d757 100644
+--- a/src/mainboard/lenovo/haswell/cmos.default
++++ b/src/mainboard/lenovo/haswell/cmos.default
+@@ -12,3 +12,4 @@ trackpoint=Enable
+ backlight=Keyboard
+ enable_dual_graphics=Disable
+ usb_always_on=Disable
++iommu=Enable
+diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout
+index 27915d3ab7..59df76b64c 100644
+--- a/src/mainboard/lenovo/haswell/cmos.layout
++++ b/src/mainboard/lenovo/haswell/cmos.layout
+@@ -23,6 +23,7 @@ entries
+ 
+ # coreboot config options: EC
+ 411	1	e	8	first_battery
++413	1	e	14	iommu
+ 415	1	e	1	wlan
+ 416	1	e	1	trackpoint
+ 417	1	e	1	fn_ctrl_swap
+@@ -72,6 +73,8 @@ enumerations
+ 13	0	Disable
+ 13	1	AC and battery
+ 13	2	AC only
++14	0	Disable
++14	1	Enable
+ 
+ # -----------------------------------------------------------------
+ checksums
+diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default
+index f4047147f7..eea2c36b88 100644
+--- a/src/mainboard/supermicro/x10slm-f/cmos.default
++++ b/src/mainboard/supermicro/x10slm-f/cmos.default
+@@ -3,3 +3,4 @@ debug_level=Debug
+ nmi=Enable
+ power_on_after_fail=Keep
+ hide_ast2400=Disable
++iommu=Enable
+diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout
+index 38ba87aa45..24d39e97ee 100644
+--- a/src/mainboard/supermicro/x10slm-f/cmos.layout
++++ b/src/mainboard/supermicro/x10slm-f/cmos.layout
+@@ -21,6 +21,9 @@ entries
+ 408	1	e	1	nmi
+ 409	2	e	5	power_on_after_fail
+ 
++# enable or disable iommu
++412	1	e	6	iommu
++
+ # coreboot config options: mainboard
+ 416	1	e	1	hide_ast2400
+ 
+@@ -55,6 +58,9 @@ enumerations
+ 5	1	Enable
+ 5	2	Keep
+ 
++6	0	Disable
++6	1	Enable
++
+ # -----------------------------------------------------------------
+ checksums
+ 
+diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
+index e47deb5da6..1a7e0b1076 100644
+--- a/src/northbridge/intel/haswell/early_init.c
++++ b/src/northbridge/intel/haswell/early_init.c
+@@ -5,6 +5,7 @@
+ #include <device/mmio.h>
+ #include <device/pci_def.h>
+ #include <device/pci_ops.h>
++#include <option.h>
+ 
+ #include "haswell.h"
+ 
+@@ -157,6 +158,10 @@ static void haswell_setup_misc(void)
+ static void haswell_setup_iommu(void)
+ {
+ 	const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
++	u8 enable_iommu = get_uint_option("iommu", 1);
++
++	if (!enable_iommu)
++		return;
+ 
+ 	if (capid0_a & VTD_DISABLE)
+ 		return;
+-- 
+2.39.2
+

config/coreboot/default/patches/0036-src-intel-x4x-Disable-stack-overflow-debug.patch

@@ -1,33 +0,0 @@
-From 8dcd86c34d92b9b17bcfe4c7c61793042dc97268 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 6 Jan 2025 01:53:53 +0000
-Subject: [PATCH 36/37] src/intel/x4x: Disable stack overflow debug
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/northbridge/intel/x4x/Kconfig | 9 +++++++++
- 1 file changed, 9 insertions(+)
-
-diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
-index 1803ef5733..7129aabf72 100644
---- a/src/northbridge/intel/x4x/Kconfig
-+++ b/src/northbridge/intel/x4x/Kconfig
-@@ -32,6 +32,15 @@ config ECAM_MMCONF_BUS_NUMBER
- 	int
- 	default 256
- 
-+# Override DEBUG Kconfig to avoid false alarm about stack overflow.
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS
-+	bool
-+	default n
-+
-+config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES
-+	bool
-+	default n
-+
- # This number must be equal or lower than what's reported in ACPI PCI _CRS
- config DOMAIN_RESOURCE_32BIT_LIMIT
- 	default 0xfec00000
--- 
-2.39.5
-

config/coreboot/default/patches/0037-Conditional-TBFW-setting-for-T480-T480S.patch

@@ -1,37 +0,0 @@
-From 9b547c2029611793f895117a807fa2d2c22a5332 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Mon, 21 Apr 2025 05:14:45 +0100
-Subject: [PATCH 37/37] Conditional TBFW setting for T480/T480S
-
-Otherwise, other boards will define it, which
-might trigger the vendor download script, and
-lead to a non-zero exit.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/mainboard/lenovo/Kconfig | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig
-index 512b326381..3d3490b35d 100644
---- a/src/mainboard/lenovo/Kconfig
-+++ b/src/mainboard/lenovo/Kconfig
-@@ -18,6 +18,8 @@ config MAINBOARD_FAMILY
- 	string
- 	default MAINBOARD_PART_NUMBER
- 
-+if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S
-+
- config LENOVO_TBFW_BIN
- 	string "Lenovo ThunderBolt firmware bin file"
- 	default ""
-@@ -44,4 +46,6 @@ config LENOVO_TBFW_BIN
- 	  Just leave this blank if you don't care about this option. It's not
- 	  useful for every ThinkPad, only certain models.
- 
-+endif # BOARD LENOVO_T480 || BOARD_LENOVO_T480S
-+
- endif # VENDOR_LENOVO
--- 
-2.39.5
-

config/coreboot/default/patches/0037-dell-optiplex_9020-Disable-IOMMU-by-default.patch

@@ -1,7 +1,7 @@
-From 4b0536ce7cd55eedc52d13497bea59d91e8924d8 Mon Sep 17 00:00:00 2001
+From 61041d49b94236400e836b8ea518d3a064b95c4e Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 2 Mar 2024 23:00:09 +0000
-Subject: [PATCH 12/37] dell/optiplex_9020: Disable IOMMU by default
+Subject: [PATCH 2/2] dell/optiplex_9020: Disable IOMMU by default
 
 Needed to make graphics cards work. Turning it on is
 recommended if only using iGPU, otherwise leave it off
@@ -15,15 +15,15 @@ Signed-off-by: Leah Rowe <info@minifree.org>
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
-index 8000eea8c0..0700f971ee 100644
+index 8253570f19..7bccc80e51 100644
 --- a/src/mainboard/dell/optiplex_9020/cmos.default
 +++ b/src/mainboard/dell/optiplex_9020/cmos.default
-@@ -4,4 +4,4 @@ debug_level=Debug
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
  nmi=Disable
  power_on_after_fail=Disable
- fan_full_speed=Disable
 -iommu=Enable
 +iommu=Disable
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0038-do-not-break-building-other-thinkpads-with-the-hacks.patch

@@ -1,153 +0,0 @@
-From 49204919e885dca2be45ffbaf2f5af62109ec3a7 Mon Sep 17 00:00:00 2001
-From: gaspar-ilom <gasparilom@riseup.net>
-Date: Thu, 6 Mar 2025 23:00:00 +0000
-Subject: [PATCH 1/1] do not break building other thinkpads with the hacks for
- the t480/s made Mate Kukri
-
-still not fixing things properly but at least it should now be possible to build older thinkpads without regressions.
-prior, some code was just commented or unreachable. now we make this explicit with preprocessor directives.
-heads should build all boards on this coreboot version from the same coreboot tree.
-
-Signed-off-by: gaspar-ilom <gasparilom@riseup.net>
----
- src/device/pci_rom.c         |  9 ++++++---
- src/ec/lenovo/h8/acpi/ec.asl |  4 +++-
- src/ec/lenovo/h8/bluetooth.c | 14 ++++++++++----
- src/ec/lenovo/h8/wwan.c      | 14 ++++++++++----
- 4 files changed, 29 insertions(+), 12 deletions(-)
-
-diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c
-index bba98d9dea..db3dbbe2ce 100644
---- a/src/device/pci_rom.c
-+++ b/src/device/pci_rom.c
-@@ -396,16 +396,19 @@ void pci_rom_ssdt(const struct device *device)
- 		rom = cbrom;
- 	}
- 
--#if 0
-+
-+	#if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+	const char *scope = "\\_SB.PCI0.RP01.PEGP";
-+	#else
- 	const char *scope = acpi_device_path(device);
-+	#endif
- 	if (!scope) {
- 		printk(BIOS_ERR, "%s: Missing ACPI scope\n", dev_path(device));
- 		return;
- 	}
--#endif
- 
- 	/* write _ROM method */
--	acpigen_write_scope("\\_SB.PCI0.RP01.PEGP");
-+	acpigen_write_scope(scope);
- 	acpigen_write_rom((void *)rom, rom->size * 512);
- 	acpigen_pop_len(); /* pop scope */
- }
-diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl
-index 8f4a8e1986..f80c15106c 100644
---- a/src/ec/lenovo/h8/acpi/ec.asl
-+++ b/src/ec/lenovo/h8/acpi/ec.asl
-@@ -331,7 +331,9 @@ Device(EC)
- #include "sleepbutton.asl"
- #include "lid.asl"
- #include "beep.asl"
--//#include "thermal.asl"
-+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+#include "thermal.asl"
-+#endif
- #include "systemstatus.asl"
- #include "thinkpad.asl"
- }
-diff --git a/src/ec/lenovo/h8/bluetooth.c b/src/ec/lenovo/h8/bluetooth.c
-index be71a24ced..e60b6c088c 100644
---- a/src/ec/lenovo/h8/bluetooth.c
-+++ b/src/ec/lenovo/h8/bluetooth.c
-@@ -1,6 +1,8 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
- 
--// #include <southbridge/intel/common/gpio.h>
-+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+#include <southbridge/intel/common/gpio.h>
-+#endif
- #include <console/console.h>
- #include <device/device.h>
- #include <ec/acpi/ec.h>
-@@ -26,23 +28,27 @@ void h8_bluetooth_enable(int on)
-  */
- bool h8_has_bdc(const struct device *dev)
- {
-+	#if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+	printk(BIOS_INFO, "H8: BDC detection not implemented. "
-+			  "Assuming BDC installed\n");
-+	return true;
-+	#else
- 	struct ec_lenovo_h8_config *conf = dev->chip_info;
- 
--	if (1 || !conf->has_bdc_detection) {
-+	if (!conf->has_bdc_detection) {
- 		printk(BIOS_INFO, "H8: BDC detection not implemented. "
- 				  "Assuming BDC installed\n");
- 		return true;
- 	}
- 
--#if 0
- 	if (get_gpio(conf->bdc_gpio_num) == conf->bdc_gpio_lvl) {
- 		printk(BIOS_INFO, "H8: BDC installed\n");
- 		return true;
- 	}
--#endif
- 
- 	printk(BIOS_INFO, "H8: BDC not installed\n");
- 	return false;
-+	#endif
- }
- 
- /*
-diff --git a/src/ec/lenovo/h8/wwan.c b/src/ec/lenovo/h8/wwan.c
-index 5cdcf77406..b4f5787e01 100644
---- a/src/ec/lenovo/h8/wwan.c
-+++ b/src/ec/lenovo/h8/wwan.c
-@@ -1,6 +1,8 @@
- /* SPDX-License-Identifier: GPL-2.0-only */
- 
--// #include <southbridge/intel/common/gpio.h>
-+#if !CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+#include <southbridge/intel/common/gpio.h>
-+#endif
- #include <console/console.h>
- #include <device/device.h>
- #include <ec/acpi/ec.h>
-@@ -24,23 +26,27 @@ void h8_wwan_enable(int on)
-  */
- bool h8_has_wwan(const struct device *dev)
- {
-+	#if CONFIG(BOARD_LENOVO_SKLKBL_THINKPAD_COMMON)
-+	printk(BIOS_INFO, "H8: WWAN detection not implemented. "
-+			  "Assuming WWAN installed\n");
-+	return true;
-+	#else
- 	struct ec_lenovo_h8_config *conf = dev->chip_info;
- 
--	if (1 || !conf->has_wwan_detection) {
-+	if (!conf->has_wwan_detection) {
- 		printk(BIOS_INFO, "H8: WWAN detection not implemented. "
- 				  "Assuming WWAN installed\n");
- 		return true;
- 	}
- 
--#if 0
- 	if (get_gpio(conf->wwan_gpio_num) == conf->wwan_gpio_lvl) {
- 		printk(BIOS_INFO, "H8: WWAN installed\n");
- 		return true;
- 	}
--#endif
- 
- 	printk(BIOS_INFO, "H8: WWAN not installed\n");
- 	return false;
-+	#endif
- }
- 
- /*
--- 
-2.39.5
-

config/coreboot/default/patches/0038-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch

@@ -0,0 +1,774 @@
+From 7dd58c8b301404a8bafee25a1e97a8a5d614b3d6 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Mon, 4 Mar 2024 18:05:43 -0700
+Subject: [PATCH] mb/dell: Add Latitude E5420 (Sandy Bridge)
+
+---
+ src/mainboard/dell/e5420/Kconfig           |  37 ++++
+ src/mainboard/dell/e5420/Kconfig.name      |   2 +
+ src/mainboard/dell/e5420/Makefile.mk       |   5 +
+ src/mainboard/dell/e5420/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e5420/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e5420/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e5420/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e5420/board_info.txt    |   6 +
+ src/mainboard/dell/e5420/cmos.default      |   9 +
+ src/mainboard/dell/e5420/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e5420/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e5420/devicetree.cb     |  66 +++++++
+ src/mainboard/dell/e5420/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e5420/early_init.c      |  32 ++++
+ src/mainboard/dell/e5420/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e5420/gpio.c            | 195 +++++++++++++++++++++
+ src/mainboard/dell/e5420/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e5420/mainboard.c       |  21 +++
+ 18 files changed, 584 insertions(+)
+ create mode 100644 src/mainboard/dell/e5420/Kconfig
+ create mode 100644 src/mainboard/dell/e5420/Kconfig.name
+ create mode 100644 src/mainboard/dell/e5420/Makefile.mk
+ create mode 100644 src/mainboard/dell/e5420/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e5420/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e5420/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e5420/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e5420/board_info.txt
+ create mode 100644 src/mainboard/dell/e5420/cmos.default
+ create mode 100644 src/mainboard/dell/e5420/cmos.layout
+ create mode 100755 src/mainboard/dell/e5420/data.vbt
+ create mode 100644 src/mainboard/dell/e5420/devicetree.cb
+ create mode 100644 src/mainboard/dell/e5420/dsdt.asl
+ create mode 100644 src/mainboard/dell/e5420/early_init.c
+ create mode 100644 src/mainboard/dell/e5420/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e5420/gpio.c
+ create mode 100644 src/mainboard/dell/e5420/hda_verb.c
+ create mode 100644 src/mainboard/dell/e5420/mainboard.c
+
+diff --git a/src/mainboard/dell/e5420/Kconfig b/src/mainboard/dell/e5420/Kconfig
+new file mode 100644
+index 0000000000..f4385045ae
+--- /dev/null
++++ b/src/mainboard/dell/e5420/Kconfig
+@@ -0,0 +1,37 @@
++if BOARD_DELL_LATITUDE_E5420
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_6144
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_BD82X6X
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e5420"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E5420"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0116"
++
++endif # BOARD_DELL_LATITUDE_E5420
+diff --git a/src/mainboard/dell/e5420/Kconfig.name b/src/mainboard/dell/e5420/Kconfig.name
+new file mode 100644
+index 0000000000..eb495fb705
+--- /dev/null
++++ b/src/mainboard/dell/e5420/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E5420
++	bool "Latitude E5420"
+diff --git a/src/mainboard/dell/e5420/Makefile.mk b/src/mainboard/dell/e5420/Makefile.mk
+new file mode 100644
+index 0000000000..18391d8b18
+--- /dev/null
++++ b/src/mainboard/dell/e5420/Makefile.mk
+@@ -0,0 +1,5 @@
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e5420/acpi/ec.asl b/src/mainboard/dell/e5420/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e5420/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e5420/acpi/platform.asl b/src/mainboard/dell/e5420/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e5420/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e5420/acpi/superio.asl b/src/mainboard/dell/e5420/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e5420/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e5420/acpi_tables.c b/src/mainboard/dell/e5420/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e5420/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e5420/board_info.txt b/src/mainboard/dell/e5420/board_info.txt
+new file mode 100644
+index 0000000000..34d5ad9e0b
+--- /dev/null
++++ b/src/mainboard/dell/e5420/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2011
+diff --git a/src/mainboard/dell/e5420/cmos.default b/src/mainboard/dell/e5420/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e5420/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e5420/cmos.layout b/src/mainboard/dell/e5420/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e5420/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e5420/data.vbt b/src/mainboard/dell/e5420/data.vbt
+new file mode 100755
+index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57
+GIT binary patch
+literal 6144
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+zk9)u(7?cb(hChhTM57@QFfmbMB!G!dNsO6BW5OSp5EGF^jHnTTdhUBI+h`e+1ft1q
+z^SfW?+;h)4_uO+|XEfEV$91)<gOArWE)OnSTD}Ug6?8a~vz+SmQn!4~y3N7b^|hPp
+zR<5aEfv-b8M00Lk251!oO|8(YA6XaeXzkt-Z)@Ee!_{@z#Fro^?DqN4SGjRIu8KYp
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+z31FHG)7?qk5g>e?=ER{f^&}W<0k@mxff(?6+Stw+s6y%k1mM$cLk#^FWWI*9bE1GY
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+X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e5420/devicetree.cb b/src/mainboard/dell/e5420/devicetree.cb
+new file mode 100644
+index 0000000000..f26413557d
+--- /dev/null
++++ b/src/mainboard/dell/e5420/devicetree.cb
+@@ -0,0 +1,66 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00000c31"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x049b inherit
++
++		device ref host_bridge on end # Host bridge
++		device ref peg10 on end # PEG
++		device ref igd on end # iGPU
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x007c0901"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x001c0901"
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x3b"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++
++			device ref mei1		off end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	off end
++			device ref gbe		off end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end
++			device ref pcie_rp2	on end
++			device ref pcie_rp3	on end
++			device ref pcie_rp4	off end
++			device ref pcie_rp5	on end
++			device ref pcie_rp6	on end
++			device ref pcie_rp7	on end
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1 on end
++			device ref smbus on end
++			device ref sata2 off end
++			device ref thermal off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e5420/dsdt.asl b/src/mainboard/dell/e5420/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e5420/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e5420/early_init.c b/src/mainboard/dell/e5420/early_init.c
+new file mode 100644
+index 0000000000..7297921546
+--- /dev/null
++++ b/src/mainboard/dell/e5420/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 1, 2 },
++	{ 1, 1, 2 },
++	{ 1, 1, 3 },
++	{ 1, 1, 3 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 1, 7 },
++	{ 1, 1, 6 },
++	{ 1, 1, 6 },
++	{ 1, 1, 7 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e5420/gma-mainboard.ads b/src/mainboard/dell/e5420/gma-mainboard.ads
+new file mode 100644
+index 0000000000..2a16f44360
+--- /dev/null
++++ b/src/mainboard/dell/e5420/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, -- mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e5420/gpio.c b/src/mainboard/dell/e5420/gpio.c
+new file mode 100644
+index 0000000000..f76b93d9f0
+--- /dev/null
++++ b/src/mainboard/dell/e5420/gpio.c
+@@ -0,0 +1,195 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_NATIVE,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_GPIO,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_NATIVE,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_GPIO,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio12 = GPIO_DIR_OUTPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_INPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++	.gpio30 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio12 = GPIO_LEVEL_HIGH,
++	.gpio30 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_NATIVE,
++	.gpio46 = GPIO_MODE_GPIO,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_NATIVE,
++	.gpio50 = GPIO_MODE_GPIO,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_GPIO,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_GPIO,
++	.gpio56 = GPIO_MODE_GPIO,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_OUTPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio46 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio50 = GPIO_DIR_OUTPUT,
++	.gpio51 = GPIO_DIR_OUTPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio53 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio55 = GPIO_DIR_OUTPUT,
++	.gpio56 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_LOW,
++	.gpio37 = GPIO_LEVEL_LOW,
++	.gpio46 = GPIO_LEVEL_HIGH,
++	.gpio50 = GPIO_LEVEL_HIGH,
++	.gpio51 = GPIO_LEVEL_LOW,
++	.gpio55 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_NATIVE,
++	.gpio69 = GPIO_MODE_NATIVE,
++	.gpio70 = GPIO_MODE_NATIVE,
++	.gpio71 = GPIO_MODE_NATIVE,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_GPIO,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio74 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e5420/hda_verb.c b/src/mainboard/dell/e5420/hda_verb.c
+new file mode 100644
+index 0000000000..70e7c2e79a
+--- /dev/null
++++ b/src/mainboard/dell/e5420/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
++	0x1028049b,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x1028049b),
++	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0xd5a30130),
++
++	0x80862805,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e5420/mainboard.c b/src/mainboard/dell/e5420/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e5420/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.44.0
+

config/coreboot/default/patches/0039-fix-sata-ports-on-dell-9020-sff-and-mt.patch

@@ -0,0 +1,66 @@
+From 4889f08306f1530211dcc6f6a4e999c6cc72f3ac Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Sat, 30 Mar 2024 05:57:54 +0000
+Subject: [PATCH 1/1] fix sata ports on dell 9020 sff and mt
+
+mate kukri has a patch under review on coreboot that sets
+sata port map to 0x7 on sff and 0xf on mt.
+
+see: intel 8 series pch datasheet, section 13.1.35
+
+basically, the 6 least significant bits enable the sata
+slots; 1 for enable and 0 for disable. there can be up
+to 6 ports. least significant bit is port 0, then next
+is port 1, and so on.
+
+coreboot currently enables ports 0, 1, 4 and 5, making this
+value 0x33 (converted to binary: 00110011). sff has ports
+0, 1 and 2 wired, so mate changed that to 0x7 (00000111).
+
+on mt, the blue ports are ports 0 and 1, but the two white
+ports don't work, but coreboot enables 4 and 5; it is
+likely that the blue ports are in fact 0 and 1, and the
+white ports are 2 and 3, but we've not tested this!
+
+it could be that the blue ports are ports 4 and 5, and
+the white ports are 2 and 3! we have not yet determined
+this, but mate set it to 0xf, meaning ports 0 1 2 and 3
+are enabled, in his patch under review. the chance that
+it's 2, 3, 4 and 5 on the board is unlikely, but it is
+theoretically possible and has not been confirmed.
+
+therefore, for now, i will set the value to 0x3f, which
+in binary is 00111111, thus enabling all 6 slots. the two
+that aren't physically wired don't really matter. enabling
+ports (from the pch) that electrically aren't there and
+then powering on is electrically equivalent to those ports
+being actually being wired, but with no devices plugged
+into them. therefore, 0x3f is an effective shotgun fix.
+
+i'll remove this patch and use mate's fix when the latter
+has been tested on MT; it has already been tested on SFF.
+
+this patch fixes the 3rd sata slot on 9020 sff, and the 3rd
+and 4th sata slots on 9020 MT
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/mainboard/dell/optiplex_9020/devicetree.cb | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
+index c0b17a15ff..7bfa6736a6 100644
+--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
+@@ -23,7 +23,7 @@ chip northbridge/intel/haswell
+ 			register "gen2_dec" = "0x007c0901"
+ 			register "gen3_dec" = "0x003c07e1"
+ 			register "gen4_dec" = "0x001c0901"
+-			register "sata_port_map" = "0x33"
++			register "sata_port_map" = "0x3f"
+ 
+ 			device pci 14.0 on  end				# xHCI controller
+ 			device pci 16.0 on  end				# Management Engine interface 1
+-- 
+2.39.2
+

config/coreboot/default/patches/0039-hp-8300cmt-remove-xhci_overcurrent_mapping.patch

@@ -1,42 +0,0 @@
-From b313c1d4bae17fc6eb3a8217c503187d1cd5453d Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Tue, 22 Apr 2025 10:21:59 +0100
-Subject: [PATCH 1/1] hp/8300cmt: remove xhci_overcurrent_mapping
-
-No longer needed, as per the following commit:
-
-commit a3d1e6c4806e6c0e2e744be3a03fce12f21778d1
-Author: Keith Hui <buurin@gmail.com>
-Date:   Tue Dec 31 18:19:31 2024 -0500
-
-    sb/intel/bd82x6x: Apply EHCI mapping to xhci_overcurrent_mapping
-
-Removing this from the devicetree also allows the
-board to compile, otherwise an error is thrown:
-
-build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:10: error: 'const struct southbridge_intel_bd82x6x_config' has no member named 'xhci_overcurrent_mapping'
-  147 |         .xhci_overcurrent_mapping = 0x00000c03,
-      |          ^~~~~~~~~~~~~~~~~~~~~~~~
-build/mainboard/hp/compaq_elite_8300_cmt/static.c:147:37: error: excess elements in struct initializer [-Werror]
-  147 |         .xhci_overcurrent_mapping = 0x00000c03,
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb | 1 -
- 1 file changed, 1 deletion(-)
-
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-index 3d21739b72..3a0b6d5c59 100644
---- a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-@@ -25,7 +25,6 @@ chip northbridge/intel/sandybridge
- 			register "spi_lvscc" = "0x2005"
- 			register "spi_uvscc" = "0x2005"
- 			register "superspeed_capable_ports" = "0x0000000f"
--			register "xhci_overcurrent_mapping" = "0x00000c03"
- 			register "xhci_switchable_ports" = "0x0000000f"
- 			register "usb_port_config" = "{
- 				{ 1, 0, 0 },
--- 
-2.39.5
-

config/coreboot/default/patches/0040-Fix-build-with-GCC-15-as-host-compiler.patch

@@ -1,62 +0,0 @@
-From 281151d85240bd8a60545b6415e0f44ce6a2af33 Mon Sep 17 00:00:00 2001
-From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
-Date: Tue, 29 Apr 2025 17:31:13 +0300
-Subject: [PATCH] WIP: Fix build with GCC 15 as host compiler
-
-GCC 15 now considers the unterminated-string-initialization warning as
-part of -Werror by default. Coreboot compiles host utilities with the
-system compiler, which results in getting this error in some files.
-
-Mark a hexadecimal translation table in cbfstool code as "nonstring" to
-avoid the warning-turned-error.
-
-The bios log prefixes are non-null-terminated as well, but I couldn't
-figure out how to mark them as non-strings. Temporarily disable the
-warning with a pragma to avoid the error. That pragma causes an error on
-GCC 14, so disable pragma warnings along with it to avoid that as well.
-
-Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
----
- src/commonlib/include/commonlib/loglevel.h | 4 ++++
- util/cbfstool/common.c                     | 2 +-
- 2 files changed, 5 insertions(+), 1 deletion(-)
-
-diff --git a/src/commonlib/include/commonlib/loglevel.h b/src/commonlib/include/commonlib/loglevel.h
-index 79fbcfc6d92b..31438c945ff5 100644
---- a/src/commonlib/include/commonlib/loglevel.h
-+++ b/src/commonlib/include/commonlib/loglevel.h
-@@ -163,6 +163,9 @@
-  * When printing logs, lines should be printed with the following prefixes in
-  * front of them according to the BIOS_LOG_PREFIX_PATTERN printf() pattern.
-  */
-+#pragma GCC diagnostic push
-+#pragma GCC diagnostic ignored "-Wpragmas"
-+#pragma GCC diagnostic ignored "-Wunterminated-string-initialization"
- #define BIOS_LOG_PREFIX_PATTERN "[%.5s]  "
- #define BIOS_LOG_PREFIX_MAX_LEVEL BIOS_SPEW
- static const char bios_log_prefix[BIOS_LOG_PREFIX_MAX_LEVEL + 1][5] = {
-@@ -177,6 +180,7 @@ static const char bios_log_prefix[BIOS_LOG_PREFIX_MAX_LEVEL + 1][5] = {
- 	[BIOS_DEBUG]   = "DEBUG",
- 	[BIOS_SPEW]    = "SPEW ",
- };
-+#pragma GCC diagnostic pop
- 
- /*
-  * When printing to terminals supporting ANSI escape sequences, the following
-diff --git a/util/cbfstool/common.c b/util/cbfstool/common.c
-index 7154bc9d5425..cb08c9e8ec11 100644
---- a/util/cbfstool/common.c
-+++ b/util/cbfstool/common.c
-@@ -192,7 +192,7 @@ uint64_t intfiletype(const char *name)
- 
- char *bintohex(uint8_t *data, size_t len)
- {
--	static const char translate[16] = "0123456789abcdef";
-+	static const char translate[16] __attribute__((__nonstring__)) = "0123456789abcdef";
- 
- 	char *result = malloc(len * 2 + 1);
- 	if (result == NULL)
-
--- 
-2.49.0
-

config/coreboot/default/patches/0040-nb-haswell-Disable-iGPU-when-dGPU-is-used.patch

@@ -0,0 +1,54 @@
+From c6ce9c635e6576c86c546177c3d770dec2f3c9ae Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Fri, 23 Feb 2024 13:33:31 +0000
+Subject: [PATCH 1/1] nb/haswell: Disable iGPU when dGPU is used
+
+This is usually is handled by Haswell mrc.bin, disabling VGA
+decode on the iGPU when a dGPU is installed. However, Broadwell
+mrc.bin does not, so the iGPU and dGPU are both enabled.
+
+This patch disables legacy VGA cycles for iGPU, under such
+conditions. It has been tested on Broadwell mrc.bin when
+using a graphics card on Dell OptiPlex 9020 SFF (currently
+under review at this time of writing, submitted by Mate
+Kukri).
+
+This patch has also been tested when Haswell mrc.bin is used,
+and there are seemingly no breaking changes caused by it.
+
+Change-Id: I1df0a3aa42f8475b7741007bf3e28c2e089d916b
+Signed-off-by: Leah Rowe <info@minifree.org>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/80717
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+Reviewed-by: Nico Huber <nico.h@gmx.de>
+---
+ src/northbridge/intel/haswell/gma.c | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
+index 6e6948b70f..48a0ba54c7 100644
+--- a/src/northbridge/intel/haswell/gma.c
++++ b/src/northbridge/intel/haswell/gma.c
+@@ -461,12 +461,19 @@ static void gma_generate_ssdt(const struct device *dev)
+ 	drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
+ }
+ 
++static void gma_func0_disable(struct device *dev)
++{
++	/* Disable VGA decode */
++	pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
++}
++
+ static struct device_operations gma_func0_ops = {
+ 	.read_resources		= pci_dev_read_resources,
+ 	.set_resources		= pci_dev_set_resources,
+ 	.enable_resources	= pci_dev_enable_resources,
+ 	.init			= gma_func0_init,
+ 	.acpi_fill_ssdt		= gma_generate_ssdt,
++	.vga_disable            = gma_func0_disable,
+ 	.ops_pci		= &pci_dev_ops_pci,
+ };
+ 
+-- 
+2.39.2
+

config/coreboot/default/patches/0041-crossgcc-gmp-Add-upstream-fix-for-GCC-15.patch

@@ -1,71 +0,0 @@
-From ee3925486f3567b9fe45cb98a88b9acc64991127 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Tue, 29 Apr 2025 21:15:22 +0100
-Subject: [PATCH 1/1] crossgcc/gmp: Add upstream fix for GCC 15
-
-See:
-https://gmplib.org/list-archives/gmp-devel/2025-January/006279.html
-
-by default, upstream GCC-15 now defaults to -std=c23, instead
-of -std=c17, which can cause some build issues.
-
-GMP has this patch on their mailing list for GCC-15 (see link).
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- .../gmp-6.3.0_acinclude-m4-fix-std-c23.patch  | 43 +++++++++++++++++++
- 1 file changed, 43 insertions(+)
- create mode 100644 util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23.patch
-
-diff --git a/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23.patch b/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23.patch
-new file mode 100644
-index 0000000000..b884b62df7
---- /dev/null
-+++ b/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23.patch
-@@ -0,0 +1,43 @@
-+From b1b61bc8ab19659f0fb8c0f87edcd79ae1bfef7e Mon Sep 17 00:00:00 2001
-+From: Rudi Heitbaum <rudi@heitbaum.com>
-+Date: Wed, 22 Jan 2025 02:34:09 +0100
-+Subject: [PATCH 1/1] acinclude.m4: fix -std=c23 build failure
-+
-+Add prototype to configure test function as c23 removes unprototyped
-+functions.
-+
-+gcc-15 switched to -std=c23 by default:
-+
-+    https://gcc.gnu.org/git/?p=gcc.git;a=commitdiff;h=55e3bd376b2214e200fa76d12b67ff259b06c212
-+
-+As a result `configure` fails with:
-+    conftest.c: In function 'f':
-+    conftest.c:12:48: error: too many arguments to function 'g'; expected 0, have 6
-+       12 | for(i=0;i<1;i++){if(e(got,got,9,d[i].n)==0)h();g(i,d[i].src,d[i].n,got,d[i].want,9);if(d[i].n)h();}}
-+          |                                                ^ ~
-+    conftest.c:7:6: note: declared here
-+        7 | void g(){}
-+          |      ^
-+
-+Link: https://gmplib.org/list-archives/gmp-bugs/2024-November/005550.html
-+Signed-off-by: Rudi Heitbaum <rudi@heitbaum.com>
-+---
-+ acinclude.m4 | 2 +-
-+ 1 file changed, 1 insertion(+), 1 deletion(-)
-+
-+diff --git a/acinclude.m4 b/acinclude.m4
-+index 9cf9483..1eed843 100644
-+--- a/acinclude.m4
-++++ b/acinclude.m4
-+@@ -609,7 +609,7 @@ GMP_PROG_CC_WORKS_PART([$1], [long long reliability test 1],
-+ 
-+ #if defined (__GNUC__) && ! defined (__cplusplus)
-+ typedef unsigned long long t1;typedef t1*t2;
-+-void g(){}
-++void g(int,const t1 *,t1,t1 *,const t1 *,int){}
-+ void h(){}
-+ static __inline__ t1 e(t2 rp,t2 up,int n,t1 v0)
-+ {t1 c,x,r;int i;if(v0){c=1;for(i=1;i<n;i++){x=up[i];r=x+1;rp[i]=r;}}return c;}
-+-- 
-+2.39.5
-+
--- 
-2.39.5
-

config/coreboot/default/patches/0041-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch

@@ -1,7 +1,7 @@
-From c8329f84b2d06581dcbeecedc38b7c4715a9cba7 Mon Sep 17 00:00:00 2001
+From 0801b3ba8a0ce0109e30d27f405c912d5d705e9c Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 6 Apr 2024 01:22:47 +0100
-Subject: [PATCH 13/37] nb/haswell: Fully disable iGPU when dGPU is used
+Subject: [PATCH 1/1] nb/haswell: Fully disable iGPU when dGPU is used
 
 My earlier patch disabled decode *and* disabled the iGPU itself, but
 a subsequent revision disabled only VGA decode. Upon revisiting, I
@@ -33,10 +33,10 @@ Signed-off-by: Leah Rowe <info@minifree.org>
  1 file changed, 3 insertions(+)
 
 diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
-index f7fad3183d..1b188e92e1 100644
+index 48a0ba54c7..f0b848852d 100644
 --- a/src/northbridge/intel/haswell/gma.c
 +++ b/src/northbridge/intel/haswell/gma.c
-@@ -466,6 +466,9 @@ static void gma_func0_disable(struct device *dev)
+@@ -465,6 +465,9 @@ static void gma_func0_disable(struct device *dev)
  {
  	/* Disable VGA decode */
  	pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
@@ -47,5 +47,5 @@ index f7fad3183d..1b188e92e1 100644
  
  static struct device_operations gma_func0_ops = {
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0042-further-gcc-15-fix-for-compiling-gmp.patch

@@ -1,54 +0,0 @@
-From 983835d1470dde4559d9ee58c60e65c0bb3873c2 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <leah@libreboot.org>
-Date: Tue, 29 Apr 2025 23:13:42 +0100
-Subject: [PATCH 1/1] further gcc-15 fix for compiling gmp
-
-same as the previous fix, but we needed to apply
-the exact same change to the configure file, in
-the appropriate place.
-
-Signed-off-by: Leah Rowe <leah@libreboot.org>
----
- ...6.3.0_acinclude-m4-fix-std-c23-extra.patch | 30 +++++++++++++++++++
- 1 file changed, 30 insertions(+)
- create mode 100644 util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23-extra.patch
-
-diff --git a/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23-extra.patch b/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23-extra.patch
-new file mode 100644
-index 0000000000..bee0159abf
---- /dev/null
-+++ b/util/crossgcc/patches/gmp-6.3.0_acinclude-m4-fix-std-c23-extra.patch
-@@ -0,0 +1,30 @@
-+From f1da82325f91ccf8f3a251c0f94388acf091c1fe Mon Sep 17 00:00:00 2001
-+From: Leah Rowe <leah@libreboot.org>
-+Date: Tue, 29 Apr 2025 23:11:25 +0100
-+Subject: [PATCH 1/1] further gcc-15 -std=23 mitigation
-+
-+the same fix as in the previous revision, also needs
-+to be applied here. this make the coreboot build process
-+pass, when compiling gmp.
-+
-+Signed-off-by: Leah Rowe <leah@libreboot.org>
-+---
-+ configure | 2 +-
-+ 1 file changed, 1 insertion(+), 1 deletion(-)
-+
-+diff --git a/configure b/configure
-+index 7910aa0..bd4342d 100755
-+--- a/configure
-++++ b/configure
-+@@ -6568,7 +6568,7 @@ if test "$gmp_prog_cc_works" = yes; then
-+ 
-+ #if defined (__GNUC__) && ! defined (__cplusplus)
-+ typedef unsigned long long t1;typedef t1*t2;
-+-void g(){}
-++void g(int,const t1 *,t1,t1 *,const t1 *,int){}
-+ void h(){}
-+ static __inline__ t1 e(t2 rp,t2 up,int n,t1 v0)
-+ {t1 c,x,r;int i;if(v0){c=1;for(i=1;i<n;i++){x=up[i];r=x+1;rp[i]=r;}}return c;}
-+-- 
-+2.39.5
-+
--- 
-2.39.5
-

config/coreboot/default/patches/0042-mb-dell-optiplex_9020-Implement-late-HWM-initializat.patch

@@ -0,0 +1,602 @@
+From c58e0fea2a4e591e5ecd8a1f376c3b3af0fbb306 Mon Sep 17 00:00:00 2001
+From: Mate Kukri <kukri.mate@gmail.com>
+Date: Thu, 18 Apr 2024 20:28:45 +0100
+Subject: [PATCH 1/1] mb/dell/optiplex_9020: Implement late HWM initialization
+
+There are 4 different chassis types specified by vendor firmware, each
+with a slightly different HWM configuration.
+
+The chassis type to use is determined at runtime by reading a set of
+4 PCH GPIOs: 70, 38, 17, and 1.
+
+Additionally vendor firmware also provides an option to run the fans at
+full speed. This is substituted with a coreboot nvram option in this
+implementation.
+
+This was tested to make fan control work on my OptiPlex 7020 SFF.
+
+NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
+however the OptiPlex 9020's SCH5555 does not use externally
+programmed EC firmware.
+
+Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
+Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
+---
+ src/mainboard/dell/optiplex_9020/Makefile.inc |   3 +-
+ src/mainboard/dell/optiplex_9020/bootblock.c  |  25 +-
+ src/mainboard/dell/optiplex_9020/cmos.default |   1 +
+ src/mainboard/dell/optiplex_9020/cmos.layout  |   5 +-
+ src/mainboard/dell/optiplex_9020/mainboard.c  | 387 ++++++++++++++++++
+ src/mainboard/dell/optiplex_9020/sch5555_ec.c |  54 +++
+ src/mainboard/dell/optiplex_9020/sch5555_ec.h |  10 +
+ 7 files changed, 463 insertions(+), 22 deletions(-)
+ create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.c
+ create mode 100644 src/mainboard/dell/optiplex_9020/sch5555_ec.h
+
+diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc
+index 6ca2f2afaa..08e2e53577 100644
+--- a/src/mainboard/dell/optiplex_9020/Makefile.inc
++++ b/src/mainboard/dell/optiplex_9020/Makefile.inc
+@@ -2,4 +2,5 @@
+ 
+ romstage-y += gpio.c
+ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+-bootblock-y += bootblock.c
++ramstage-y += sch5555_ec.c
++bootblock-y += bootblock.c sch5555_ec.c
+diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
+index 2837cf9cf1..e5e759273e 100644
+--- a/src/mainboard/dell/optiplex_9020/bootblock.c
++++ b/src/mainboard/dell/optiplex_9020/bootblock.c
+@@ -4,29 +4,14 @@
+ #include <device/pnp_ops.h>
+ #include <superio/smsc/sch555x/sch555x.h>
+ #include <southbridge/intel/lynxpoint/pch.h>
+-
+-static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
+-{
+-	// Clear EC-to-Host mailbox
+-	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
+-	outb(tmp, SCH555x_EMI_IOBASE + 1);
+-
+-	// Send address and value to the EC
+-	sch555x_emi_write16(0, (addr1 * 2) | 0x101);
+-	sch555x_emi_write32(4, val | (addr2 << 16));
+-
+-	// Wait for acknowledgement message from EC
+-	outb(1, SCH555x_EMI_IOBASE);
+-	size_t timeout = 0;
+-	do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
+-}
++#include "sch5555_ec.h"
+ 
+ struct ec_init_entry {
+ 	uint16_t addr;
+ 	uint8_t val;
+ };
+ 
+-static void ec_init(void)
++static void bootblock_ec_init(void)
+ {
+ 	/*
+ 	 * Tables from CORE_PEI
+@@ -108,9 +93,9 @@ void mainboard_config_superio(void)
+ 	outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
+ 	outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
+ 
+-	// Magic EC init
+-	ec_init();
++	// Perform bootblock EC initialization
++	bootblock_ec_init();
+ 
+-	// Magic EC init is needed for UART1 initialization to work
++	// Bootblock EC initialization is required for UART1 to work
+ 	sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ }
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
+index 7bccc80e51..1909abcb9f 100644
+--- a/src/mainboard/dell/optiplex_9020/cmos.default
++++ b/src/mainboard/dell/optiplex_9020/cmos.default
+@@ -3,3 +3,4 @@ debug_level=Debug
+ nmi=Disable
+ power_on_after_fail=Disable
+ iommu=Disable
++fan_full_speed=Disable
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
+index 72ff9c4bee..4a1496a878 100644
+--- a/src/mainboard/dell/optiplex_9020/cmos.layout
++++ b/src/mainboard/dell/optiplex_9020/cmos.layout
+@@ -22,7 +22,10 @@ entries
+ 409	2	e	5	power_on_after_fail
+ 
+ # turn iommu on or off
+-412	1	e	6	iommu
++411	1	e	6	iommu
++
++# coreboot config options: EC
++412	1	e	1	fan_full_speed
+ 
+ # coreboot config options: check sums
+ 984	16	h	0	check_sum
+diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
+index c834fea5d3..0b7829c736 100644
+--- a/src/mainboard/dell/optiplex_9020/mainboard.c
++++ b/src/mainboard/dell/optiplex_9020/mainboard.c
+@@ -1,7 +1,12 @@
+ /* SPDX-License-Identifier: GPL-2.0-only */
+ 
++#include <bootstate.h>
++#include <cpu/x86/msr.h>
+ #include <device/device.h>
+ #include <drivers/intel/gma/int15.h>
++#include <option.h>
++#include <southbridge/intel/common/gpio.h>
++#include "sch5555_ec.h"
+ 
+ static void mainboard_enable(struct device *dev)
+ {
+@@ -13,3 +18,385 @@ static void mainboard_enable(struct device *dev)
+ struct chip_operations mainboard_ops = {
+ 	.enable_dev = mainboard_enable,
+ };
++
++#define HWM_TAB_ADD_TEMP_TARGET	1
++#define HWM_TAB_PKG_POWER_ANY	0xffff
++#define CHASSIS_TYPE_UNKNOWN	0xff
++
++struct hwm_tab_entry {
++	uint16_t addr;
++	uint8_t val;
++	uint8_t flags;
++	uint16_t pkg_power;
++};
++
++struct hwm_tab_entry HWM_TAB3[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x00, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0x8a, 0, 0x0010 },
++	{ 0x086, 0x4c, 0, 0x0010 },
++	{ 0x08a, 0x66, 0, 0x0010 },
++	{ 0x08b, 0x5b, 0, 0x0010 },
++	{ 0x090, 0x65, 0, 0xffff },
++	{ 0x091, 0x70, 0, 0xffff },
++	{ 0x092, 0x86, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0xa4, 0, 0xffff },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x0e, 0, 0xffff },
++	{ 0x0a1, 0x0e, 0, 0xffff },
++	{ 0x0ae, 0x7c, 0, 0xffff },
++	{ 0x0af, 0x86, 0, 0xffff },
++	{ 0x0b0, 0x9a, 0, 0xffff },
++	{ 0x0b3, 0x9a, 0, 0xffff },
++	{ 0x0b6, 0x08, 0, 0xffff },
++	{ 0x0b7, 0x08, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0x0020 },
++	{ 0x0ea, 0x5c, 0, 0x0010 },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x0fd, 0x01, 0, 0xffff },
++	{ 0x1a1, 0x00, 0, 0xffff },
++	{ 0x1a2, 0x00, 0, 0xffff },
++	{ 0x1b1, 0x08, 0, 0xffff },
++	{ 0x1be, 0x99, 0, 0xffff },
++	{ 0x280, 0xa0, 0, 0x0010 },
++	{ 0x281, 0x0f, 0, 0x0010 },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x288, 0x68, 0, 0x0010 },
++	{ 0x289, 0x10, 0, 0x0010 },
++	{ 0x28a, 0x03, 0, 0xffff },
++	{ 0x28b, 0x0a, 0, 0xffff },
++	{ 0x28c, 0x80, 0, 0xffff },
++	{ 0x28d, 0x03, 0, 0xffff },
++};
++
++struct hwm_tab_entry HWM_TAB4[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x00, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0x99, 0, 0x0020 },
++	{ 0x085, 0xad, 0, 0x0010 },
++	{ 0x086, 0x1c, 0, 0xffff },
++	{ 0x08a, 0x39, 0, 0x0020 },
++	{ 0x08a, 0x41, 0, 0x0010 },
++	{ 0x08b, 0x76, 0, 0x0020 },
++	{ 0x08b, 0x8b, 0, 0x0010 },
++	{ 0x090, 0x5e, 0, 0xffff },
++	{ 0x091, 0x5e, 0, 0xffff },
++	{ 0x092, 0x86, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0xa4, 0, 0xffff },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x0a, 0, 0xffff },
++	{ 0x0a1, 0x0a, 0, 0xffff },
++	{ 0x0ae, 0x7c, 0, 0xffff },
++	{ 0x0af, 0x7c, 0, 0xffff },
++	{ 0x0b0, 0x9a, 0, 0xffff },
++	{ 0x0b3, 0x7c, 0, 0xffff },
++	{ 0x0b6, 0x08, 0, 0xffff },
++	{ 0x0b7, 0x08, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0x0020 },
++	{ 0x0ea, 0x5c, 0, 0x0010 },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x0fd, 0x01, 0, 0xffff },
++	{ 0x1a1, 0x00, 0, 0xffff },
++	{ 0x1a2, 0x00, 0, 0xffff },
++	{ 0x1b1, 0x08, 0, 0xffff },
++	{ 0x1be, 0x90, 0, 0xffff },
++	{ 0x280, 0x94, 0, 0x0020 },
++	{ 0x281, 0x11, 0, 0x0020 },
++	{ 0x280, 0x94, 0, 0x0010 },
++	{ 0x281, 0x11, 0, 0x0010 },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x288, 0x28, 0, 0x0020 },
++	{ 0x289, 0x0a, 0, 0x0020 },
++	{ 0x288, 0x28, 0, 0x0010 },
++	{ 0x289, 0x0a, 0, 0x0010 },
++	{ 0x28a, 0x03, 0, 0xffff },
++	{ 0x28b, 0x0a, 0, 0xffff },
++	{ 0x28c, 0x80, 0, 0xffff },
++	{ 0x28d, 0x03, 0, 0xffff },
++};
++
++struct hwm_tab_entry HWM_TAB5[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x00, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0x66, 0, 0x0020 },
++	{ 0x085, 0x5d, 0, 0x0010 },
++	{ 0x086, 0x1c, 0, 0xffff },
++	{ 0x08a, 0x39, 0, 0x0020 },
++	{ 0x08a, 0x41, 0, 0x0010 },
++	{ 0x08b, 0x76, 0, 0x0020 },
++	{ 0x08b, 0x80, 0, 0x0010 },
++	{ 0x090, 0x5d, 0, 0x0020 },
++	{ 0x090, 0x5e, 0, 0x0010 },
++	{ 0x091, 0x5e, 0, 0xffff },
++	{ 0x092, 0x86, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0xa3, 0, 0x0020 },
++	{ 0x098, 0xa4, 0, 0x0010 },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x08, 0, 0xffff },
++	{ 0x0a1, 0x0a, 0, 0xffff },
++	{ 0x0ae, 0x7c, 0, 0xffff },
++	{ 0x0af, 0x7c, 0, 0xffff },
++	{ 0x0b0, 0x9a, 0, 0xffff },
++	{ 0x0b3, 0x7c, 0, 0xffff },
++	{ 0x0b6, 0x08, 0, 0xffff },
++	{ 0x0b7, 0x08, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0x0020 },
++	{ 0x0ea, 0x5c, 0, 0x0010 },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x0fd, 0x01, 0, 0xffff },
++	{ 0x1a1, 0x00, 0, 0xffff },
++	{ 0x1a2, 0x00, 0, 0xffff },
++	{ 0x1b1, 0x08, 0, 0xffff },
++	{ 0x1be, 0x98, 0, 0x0020 },
++	{ 0x1be, 0x90, 0, 0x0010 },
++	{ 0x280, 0x94, 0, 0x0020 },
++	{ 0x281, 0x11, 0, 0x0020 },
++	{ 0x280, 0x94, 0, 0x0010 },
++	{ 0x281, 0x11, 0, 0x0010 },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x288, 0x28, 0, 0x0020 },
++	{ 0x289, 0x0a, 0, 0x0020 },
++	{ 0x288, 0x28, 0, 0x0010 },
++	{ 0x289, 0x0a, 0, 0x0010 },
++	{ 0x28a, 0x03, 0, 0xffff },
++	{ 0x28b, 0x0a, 0, 0xffff },
++	{ 0x28c, 0x80, 0, 0xffff },
++	{ 0x28d, 0x03, 0, 0xffff },
++};
++
++struct hwm_tab_entry HWM_TAB6[] = {
++	{ 0x005, 0x33, 0, 0xffff },
++	{ 0x018, 0x2f, 0, 0xffff },
++	{ 0x019, 0x2f, 0, 0xffff },
++	{ 0x01a, 0x2f, 0, 0xffff },
++	{ 0x080, 0x00, 0, 0xffff },
++	{ 0x081, 0x00, 0, 0xffff },
++	{ 0x083, 0xbb, 0, 0xffff },
++	{ 0x085, 0x98, 0, 0xffff },
++	{ 0x086, 0x3c, 0, 0xffff },
++	{ 0x08a, 0x39, 0, 0x0020 },
++	{ 0x08a, 0x3d, 0, 0x0010 },
++	{ 0x08b, 0x44, 0, 0x0020 },
++	{ 0x08b, 0x51, 0, 0x0010 },
++	{ 0x090, 0x61, 0, 0xffff },
++	{ 0x091, 0x6d, 0, 0xffff },
++	{ 0x092, 0x86, 0, 0xffff },
++	{ 0x096, 0xa4, 0, 0xffff },
++	{ 0x097, 0xa4, 0, 0xffff },
++	{ 0x098, 0x9f, 0, 0x0020 },
++	{ 0x098, 0xa4, 0, 0x0010 },
++	{ 0x09b, 0xa4, 0, 0xffff },
++	{ 0x0a0, 0x0e, 0, 0xffff },
++	{ 0x0a1, 0x0e, 0, 0xffff },
++	{ 0x0ae, 0x7c, 0, 0xffff },
++	{ 0x0af, 0x7c, 0, 0xffff },
++	{ 0x0b0, 0x9b, 0, 0x0020 },
++	{ 0x0b0, 0x98, 0, 0x0010 },
++	{ 0x0b3, 0x9a, 0, 0xffff },
++	{ 0x0b6, 0x08, 0, 0xffff },
++	{ 0x0b7, 0x08, 0, 0xffff },
++	{ 0x0ea, 0x64, 0, 0x0020 },
++	{ 0x0ea, 0x5c, 0, 0x0010 },
++	{ 0x0ef, 0xff, 0, 0xffff },
++	{ 0x0f8, 0x15, 0, 0xffff },
++	{ 0x0f9, 0x00, 0, 0xffff },
++	{ 0x0f0, 0x30, 0, 0xffff },
++	{ 0x0fd, 0x01, 0, 0xffff },
++	{ 0x1a1, 0x00, 0, 0xffff },
++	{ 0x1a2, 0x00, 0, 0xffff },
++	{ 0x1b1, 0x08, 0, 0xffff },
++	{ 0x1be, 0x9a, 0, 0x0020 },
++	{ 0x1be, 0x96, 0, 0x0010 },
++	{ 0x280, 0x94, 0, 0x0020 },
++	{ 0x281, 0x11, 0, 0x0020 },
++	{ 0x280, 0x94, 0, 0x0010 },
++	{ 0x281, 0x11, 0, 0x0010 },
++	{ 0x282, 0x03, 0, 0xffff },
++	{ 0x283, 0x0a, 0, 0xffff },
++	{ 0x284, 0x80, 0, 0xffff },
++	{ 0x285, 0x03, 0, 0xffff },
++	{ 0x288, 0x94, 0, 0x0020 },
++	{ 0x289, 0x11, 0, 0x0020 },
++	{ 0x288, 0x94, 0, 0x0010 },
++	{ 0x289, 0x11, 0, 0x0010 },
++	{ 0x28a, 0x03, 0, 0xffff },
++	{ 0x28b, 0x0a, 0, 0xffff },
++	{ 0x28c, 0x80, 0, 0xffff },
++	{ 0x28d, 0x03, 0, 0xffff },
++};
++
++static uint8_t get_chassis_type(void)
++{
++	uint8_t gpio_chassis_type;
++
++	// Read chassis type from GPIO
++	gpio_chassis_type = get_gpio(70) << 3 | get_gpio(38) << 2 |
++			    get_gpio(17) << 1 | get_gpio(1);
++
++	printk(BIOS_DEBUG, "GPIO chassis type = %#x\n", gpio_chassis_type);
++
++	// Turn it into internal chassis index
++	switch (gpio_chassis_type) {
++	case 0x08:
++	case 0x0a:
++		return 4;
++	case 0x0b:
++		return 3;
++	case 0x0c:
++		return 5;
++	case 0x0d: // SFF
++	case 0x0e:
++	case 0x0f:
++		return 6;
++	default:
++		return CHASSIS_TYPE_UNKNOWN;
++	}
++
++}
++
++static uint8_t get_temp_target(void)
++{
++	uint8_t val = rdmsr(0x1a2).lo >> 8 & 0xff;
++	if (!val)
++		val = 20;
++	return 0x95 - val;
++}
++
++static uint16_t get_pkg_power(void)
++{
++	uint8_t rapl_power_unit = rdmsr(0x606).lo & 0xf;
++	if (rapl_power_unit)
++		rapl_power_unit = 2 << (rapl_power_unit - 1);
++	uint16_t pkg_power_info = rdmsr(0x614).lo & 0x7fff;
++	if (pkg_power_info / rapl_power_unit > 0x41)
++		return 32;
++	else
++		return 16;
++}
++
++static void apply_hwm_tab(struct hwm_tab_entry *arr, size_t size)
++{
++	uint8_t temp_target = get_temp_target();
++	uint16_t pkg_power = get_pkg_power();
++
++	printk(BIOS_DEBUG, "Temp target = %#x\n", temp_target);
++	printk(BIOS_DEBUG, "Package power = %#x\n", pkg_power);
++
++	for (size_t i = 0; i < size; ++i) {
++		// Skip entry if it doesn't apply for this package power
++		if (arr[i].pkg_power != pkg_power &&
++		    arr[i].pkg_power != HWM_TAB_PKG_POWER_ANY)
++			continue;
++
++		uint8_t val = arr[i].val;
++
++		// Add temp target to value if requested (current tables never do)
++		if (arr[i].flags & HWM_TAB_ADD_TEMP_TARGET)
++			val += temp_target;
++
++		// Perform write
++		ec_write(1, arr[i].addr, val);
++
++	}
++}
++
++static void sch5555_ec_hwm_init(void *arg)
++{
++	uint8_t chassis_type, saved_2fc;
++
++	printk(BIOS_DEBUG, "OptiPlex 9020 late HWM init\n");
++
++	saved_2fc = ec_read(1, 0x2fc);
++	ec_write(1, 0x2fc, 0xa0);
++	ec_write(1, 0x2fd, 0x32);
++
++	chassis_type = get_chassis_type();
++
++	if (chassis_type != CHASSIS_TYPE_UNKNOWN) {
++		printk(BIOS_DEBUG, "Chassis type = %#x\n", chassis_type);
++	} else {
++		printk(BIOS_DEBUG, "WARNING: Unknown chassis type\n");
++	}
++
++	// Apply HWM table based on chassis type
++	switch (chassis_type) {
++	case 3:
++		apply_hwm_tab(HWM_TAB3, ARRAY_SIZE(HWM_TAB3));
++		break;
++	case 4:
++		apply_hwm_tab(HWM_TAB4, ARRAY_SIZE(HWM_TAB4));
++		break;
++	case 5:
++		apply_hwm_tab(HWM_TAB5, ARRAY_SIZE(HWM_TAB5));
++		break;
++	case 6:
++		apply_hwm_tab(HWM_TAB6, ARRAY_SIZE(HWM_TAB6));
++		break;
++	}
++
++	// NOTE: vendor firmware applies these when "max core address" > 2
++	// i think this is always the case
++	ec_write(1, 0x9e, 0x30);
++	ec_write(1, 0xeb, ec_read(1, 0xea));
++
++	ec_write(1, 0x2fc, saved_2fc);
++
++	// Apply full speed fan config if requested or if the chassis type is unknown
++	if (chassis_type == CHASSIS_TYPE_UNKNOWN || get_uint_option("fan_full_speed", 0)) {
++		printk(BIOS_DEBUG, "Setting full fan speed\n");
++		ec_write(1, 0x80, 0x60 | ec_read(1, 0x80));
++		ec_write(1, 0x81, 0x60 | ec_read(1, 0x81));
++	}
++
++	ec_read(1, 0xb8);
++
++	if ((chassis_type == 4 || chassis_type == 5) && ec_read(1, 0x26) == 0) {
++		ec_write(1, 0xa0, ec_read(1, 0xa0) & 0xfb);
++		ec_write(1, 0xa1, ec_read(1, 0xa1) & 0xfb);
++		ec_write(1, 0xa2, ec_read(1, 0xa2) & 0xfb);
++		ec_write(1, 0x8a, 0x99);
++		ec_write(1, 0x8b, 0x47);
++		ec_write(1, 0x8c, 0x91);
++	}
++}
++
++BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5555_ec_hwm_init, NULL);
+diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.c b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
+new file mode 100644
+index 0000000000..a1067ac063
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.c
+@@ -0,0 +1,54 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <arch/io.h>
++#include <device/pnp_ops.h>
++#include <superio/smsc/sch555x/sch555x.h>
++#include "sch5555_ec.h"
++
++uint8_t ec_read(uint8_t addr1, uint16_t addr2)
++{
++	// clear ec-to-host mailbox
++	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
++	outb(tmp, SCH555x_EMI_IOBASE + 1);
++
++	// send address
++	outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
++	outw((addr1 * 2) | 0x100, SCH555x_EMI_IOBASE + 4);
++
++	outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
++	outl(addr2 << 16, SCH555x_EMI_IOBASE + 4);
++
++	// send message to ec
++	outb(1, SCH555x_EMI_IOBASE);
++
++	// wait for ack
++	for (size_t retry = 0; retry < 0xfff; ++retry)
++		if (inb(SCH555x_EMI_IOBASE + 1) & 1)
++			break;
++
++	// read result
++	outw(4 | 0x8000, SCH555x_EMI_IOBASE + 2);
++	return inb(SCH555x_EMI_IOBASE + 4);
++}
++
++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
++{
++	// clear ec-to-host mailbox
++	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
++	outb(tmp, SCH555x_EMI_IOBASE + 1);
++
++	// send address and value
++	outw(0 | 0x8001, SCH555x_EMI_IOBASE + 2);
++	outw((addr1 * 2) | 0x101, SCH555x_EMI_IOBASE + 4);
++
++	outw(4 | 0x8002, SCH555x_EMI_IOBASE + 2);
++	outl(val | (addr2 << 16), SCH555x_EMI_IOBASE + 4);
++
++	// send message to ec
++	outb(1, SCH555x_EMI_IOBASE);
++
++	// wait for ack
++	for (size_t retry = 0; retry < 0xfff; ++retry)
++		if (inb(SCH555x_EMI_IOBASE + 1) & 1)
++			break;
++}
+diff --git a/src/mainboard/dell/optiplex_9020/sch5555_ec.h b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
+new file mode 100644
+index 0000000000..7e399e8e74
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/sch5555_ec.h
+@@ -0,0 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#ifndef __SCH5555_EC_H__
++#define __SCH5555_EC_H__
++
++uint8_t ec_read(uint8_t addr1, uint16_t addr2);
++
++void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val);
++
++#endif
+-- 
+2.39.2
+

config/coreboot/default/patches/0043-mb-dell-optiplex_9020-Add-support-for-TPM1.2-device.patch

@@ -0,0 +1,49 @@
+From cd3c553a313a26494e5dc31ff8323c3a919f190a Mon Sep 17 00:00:00 2001
+From: Mate Kukri <kukri.mate@gmail.com>
+Date: Wed, 10 Apr 2024 20:31:35 +0100
+Subject: [PATCH 1/1] mb/dell/optiplex_9020: Add support for TPM1.2 device
+
+These machines come with a TPM1.2 device by default. It is somewhat
+obsolete these days, but there is no harm in enabling it.
+
+Change-Id: Iec05321862aed58695c256b00494e5953219786d
+Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
+Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827
+Reviewed-by: Angel Pons <th3fanbus@gmail.com>
+Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
+---
+ src/mainboard/dell/optiplex_9020/Kconfig       | 2 ++
+ src/mainboard/dell/optiplex_9020/devicetree.cb | 3 +++
+ 2 files changed, 5 insertions(+)
+
+diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
+index 774a72f161..296938aa8d 100644
+--- a/src/mainboard/dell/optiplex_9020/Kconfig
++++ b/src/mainboard/dell/optiplex_9020/Kconfig
+@@ -12,7 +12,9 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select INTEL_GMA_HAVE_VBT
+ 	select INTEL_INT15
+ 	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_HAS_TPM1
+ 	select MAINBOARD_USES_IFD_GBE_REGION
++	select MEMORY_MAPPED_TPM
+ 	select NORTHBRIDGE_INTEL_HASWELL
+ 	select SERIRQ_CONTINUOUS_MODE
+ 	select SOUTHBRIDGE_INTEL_LYNXPOINT
+diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
+index 7bfa6736a6..e5cbd64127 100644
+--- a/src/mainboard/dell/optiplex_9020/devicetree.cb
++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
+@@ -70,6 +70,9 @@ chip northbridge/intel/haswell
+ 					device pnp 2e.b  off end	# Floppy Controller
+ 					device pnp 2e.11 off end	# Parallel Port
+ 				end
++				chip drivers/pc80/tpm
++					device pnp 0c31.0 on end
++				end
+ 			end
+ 			device pci 1f.2 on  end				# SATA controller 1
+ 			device pci 1f.3 on  end				# SMBus
+-- 
+2.39.2
+

config/coreboot/default/patches/0044-hp-8560w-turn-on-wifi.patch

@@ -0,0 +1,47 @@
+From 4ccef4fffd98071c339cb4135e2d8c805e554378 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Fri, 3 May 2024 17:45:52 +0100
+Subject: [PATCH 1/1] hp/8560w: turn on wifi
+
+according to angel pons, this gpio is WLAN_TRN_OFF#
+and setting it high will make wifi work. testing with
+this change as suggested by angel. see:
+
+https://review.coreboot.org/c/coreboot/+/39398/4/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c#158
+
+if it makes it into a libreboot release, you can assume
+the fix works. right now we have this problem:
+
+https://codeberg.org/libreboot/lbmk/issues/201
+
+Riku reported:
+
+[  333.890080] atkbd serio0: Unknown key pressed (translated set 2, code 0xf8 on isa0060/serio0).
+[  333.890102] atkbd serio0: Use 'setkeycodes e078 <keycode>' to make it known.
+[  334.104069] atkbd serio0: Unknown key released (translated set 2, code 0xf8 on isa0060/serio0).
+[  334.104090] atkbd serio0: Use 'setkeycodes e078 <keycode>' to make it known.
+
+The wifi stays to hardblocked in rfkill. When the wireless button
+is pressed, nothing changes except for these lines in dmesg.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
+index 560d668d6f..10cd11ce48 100644
+--- a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
++++ b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/gpio.c
+@@ -155,7 +155,7 @@ static const struct pch_gpio_set2 pch_gpio_set2_level = {
+ 	.gpio37 = GPIO_LEVEL_LOW,
+ 	.gpio49 = GPIO_LEVEL_LOW,
+ 	.gpio53 = GPIO_LEVEL_HIGH,
+-	.gpio57 = GPIO_LEVEL_LOW,
++	.gpio57 = GPIO_LEVEL_HIGH,
+ 	.gpio60 = GPIO_LEVEL_HIGH,
+ 	.gpio61 = GPIO_LEVEL_HIGH,
+ };
+-- 
+2.39.2
+

config/coreboot/default/patches/0045-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch

@@ -1,37 +1,16 @@
-From 73dbf291631fdbae2d8e8a761c147523c8d9e65c Mon Sep 17 00:00:00 2001
+From a8c4f7004ea1c9b8268a87dd0b700c250ec4747d Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 3 May 2024 11:03:32 -0600
-Subject: [PATCH 14/37] ec/dell/mec5035: Add S3 suspend SMI handler
+Subject: [PATCH] ec/dell/mec5035: Add S3 suspend SMI handler
-
-This is necessary for S3 resume to work on SNB and newer Dell Latitude
-laptops. If a command isn't sent, the EC cuts power to the DIMMs,
-preventing the system from resuming. These commands were found using an
-FPGA to log all LPC bus transactions between the host and the EC and
-then narrowing down which ones were actually necessary.
-
-Interestingly, the command IDs appear to be identical to those in
-ec/google/wilco, the EC used on Dell Latitude Chromebooks, and that EC
-implements a similar S3 SMI handler as the one implemented in this
-commit. The Wilco EC Kconfig does suggest that its firmware is a
-modified version of Dell's usual Latitude EC firmware, so the
-similarities seem to be intentional.
-
-These similarities also identified a command to enable or disable wake
-sources like the power button and lid switch, and this was added to the
-SMI handler to disable lid wake as the system does not yet resume
-properly from a like wake with coreboot.
-
-Tested on the Latitude E6430 (Ivy Bridge) and the Precision M6800
-(Haswell, not yet pushed).
 
 Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
 ---
  src/ec/dell/mec5035/Makefile.mk  |  1 +
  src/ec/dell/mec5035/mec5035.c    | 14 ++++++++++++++
- src/ec/dell/mec5035/mec5035.h    | 22 ++++++++++++++++++++++
+ src/ec/dell/mec5035/mec5035.h    | 19 +++++++++++++++++++
  src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++
- 4 files changed, 54 insertions(+)
+ 4 files changed, 51 insertions(+)
  create mode 100644 src/ec/dell/mec5035/smihandler.c
 
 diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk
@@ -46,35 +25,35 @@ index 4ebdd811f9..be557e4599 100644
  
  endif
 diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index dffbb7960c..85c2ab0140 100644
+index 68b6b2f7fb..33bf046634 100644
 --- a/src/ec/dell/mec5035/mec5035.c
 +++ b/src/ec/dell/mec5035/mec5035.c
 @@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
  	ec_command(CMD_RADIO_CTRL);
  }
  
-+void mec5035_change_wake(u8 source, enum ec_wake_change change)
-+{
-+	u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
-+	write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS);
-+	ec_command(CMD_ACPI_WAKEUP_CHANGE);
-+}
-+
 +void mec5035_sleep_enable(void)
 +{
 +	u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
 +	write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
 +	ec_command(CMD_SLEEP_ENABLE);
 +}
++
++void mec5035_change_wake(u8 source, enum ec_wake_change change)
++{
++	u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
++	write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS);
++	ec_command(CMD_ACPI_WAKEUP_CHANGE);
++}
 +
  void mec5035_early_init(void)
  {
  	/* If this isn't sent the EC shuts down the system after about 15
 diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index 32f791cb01..8d4fded28b 100644
+index fa15a9d621..069616fbc5 100644
 --- a/src/ec/dell/mec5035/mec5035.h
 +++ b/src/ec/dell/mec5035/mec5035.h
-@@ -4,12 +4,15 @@
+@@ -4,6 +4,7 @@
  #define _EC_DELL_MEC5035_H_
  
  #include <stdint.h>
@@ -82,46 +61,37 @@ index 32f791cb01..8d4fded28b 100644
  
  #define NUM_REGISTERS	32
  
- enum mec5035_cmd {
+@@ -29,9 +30,27 @@ enum ec_radio_state {
- 	CMD_MOUSE_TP = 0x1a,
- 	CMD_RADIO_CTRL = 0x2b,
-+	CMD_ACPI_WAKEUP_CHANGE = 0x4a,
-+	CMD_SLEEP_ENABLE = 0x64,
- 	CMD_CPU_OK = 0xc2,
- };
- 
-@@ -33,9 +36,28 @@ enum ec_radio_state {
  	RADIO_ON
  };
  
++#define CMD_ACPI_WAKEUP_CHANGE 0x4a
 +#define ACPI_WAKEUP_NUM_ARGS 4
 +enum ec_wake_change {
 +	WAKE_OFF = 0,
 +	WAKE_ON
 +};
-+
-+/* Copied from ec/google/wilco/commands.h. Not sure if these all apply */
 +enum ec_acpi_wake_events {
 +	EC_ACPI_WAKE_PWRB = BIT(0),     /* Wake up by power button */
 +	EC_ACPI_WAKE_LID = BIT(1),      /* Wake up by lid switch */
 +	EC_ACPI_WAKE_RTC = BIT(5),      /* Wake up by RTC */
 +};
 +
++#define CMD_SLEEP_ENABLE 0x64
 +#define SLEEP_EN_NUM_ARGS 2
 +
- u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
+ u8 mec5035_mouse_touchpad(u8 setting);
  void mec5035_cpu_ok(void);
  void mec5035_early_init(void);
  void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
++void mec5035_sleep(int slp_type);
 +void mec5035_change_wake(u8 source, enum ec_wake_change change);
 +void mec5035_sleep_enable(void);
-+
-+void mec5035_smi_sleep(int slp_type);
  
  #endif /* _EC_DELL_MEC5035_H_ */
 diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c
 new file mode 100644
-index 0000000000..958733bf97
+index 0000000000..1db834773d
 --- /dev/null
 +++ b/src/ec/dell/mec5035/smihandler.c
 @@ -0,0 +1,17 @@
@@ -132,7 +102,7 @@ index 0000000000..958733bf97
 +#include <ec/acpi/ec.h>
 +#include "mec5035.h"
 +
-+void mec5035_smi_sleep(int slp_type)
++void mec5035_sleep(int slp_type)
 +{
 +	switch (slp_type) {
 +	case ACPI_S3:
@@ -143,5 +113,5 @@ index 0000000000..958733bf97
 +	}
 +}
 -- 
-2.39.5
+2.44.0
 

config/coreboot/default/patches/0046-mb-dell-Add-S3-SMI-handler-for-SNB-IVB-Latitudes.patch

@@ -0,0 +1,133 @@
+From 9ff35368733c5e5a852ebd6295f262710553913b Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 3 May 2024 16:31:12 -0600
+Subject: [PATCH] mb/dell/: Add S3 SMI handler for SNB/IVB Latitudes
+
+This should fix S3 suspend on these systems
+
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e5420/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e5520/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e5530/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e6420/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e6430/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e6520/smihandler.c | 9 +++++++++
+ src/mainboard/dell/e6530/smihandler.c | 9 +++++++++
+ 7 files changed, 63 insertions(+)
+ create mode 100644 src/mainboard/dell/e5420/smihandler.c
+ create mode 100644 src/mainboard/dell/e5520/smihandler.c
+ create mode 100644 src/mainboard/dell/e5530/smihandler.c
+ create mode 100644 src/mainboard/dell/e6420/smihandler.c
+ create mode 100644 src/mainboard/dell/e6430/smihandler.c
+ create mode 100644 src/mainboard/dell/e6520/smihandler.c
+ create mode 100644 src/mainboard/dell/e6530/smihandler.c
+
+diff --git a/src/mainboard/dell/e5420/smihandler.c b/src/mainboard/dell/e5420/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e5420/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e5520/smihandler.c b/src/mainboard/dell/e5520/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e5520/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e5530/smihandler.c b/src/mainboard/dell/e5530/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e5530/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e6420/smihandler.c b/src/mainboard/dell/e6420/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e6420/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e6430/smihandler.c b/src/mainboard/dell/e6430/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e6430/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e6520/smihandler.c b/src/mainboard/dell/e6520/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e6520/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+diff --git a/src/mainboard/dell/e6530/smihandler.c b/src/mainboard/dell/e6530/smihandler.c
+new file mode 100644
+index 0000000000..334d7b1a5f
+--- /dev/null
++++ b/src/mainboard/dell/e6530/smihandler.c
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <cpu/x86/smm.h>
++#include <ec/dell/mec5035/mec5035.h>
++
++void mainboard_smi_sleep(u8 slp_typ)
++{
++	mec5035_sleep(slp_typ);
++}
+-- 
+2.44.0
+

config/coreboot/default/patches/0047-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch

@@ -1,7 +1,7 @@
-From a507fe609a2e99c95218ec430916eaf4c3cb61d9 Mon Sep 17 00:00:00 2001
+From fa4f05e39744eb4c4606f940b8acc7fd053b11d4 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <info@minifree.org>
 Date: Sat, 4 May 2024 02:00:53 +0100
-Subject: [PATCH 15/37] nb/haswell: lock policy regs when disabling IOMMU
+Subject: [PATCH 1/1] nb/haswell: lock policy regs when disabling IOMMU
 
 Angel Pons told me I should do it. See comments here:
 https://review.coreboot.org/c/coreboot/+/81016
@@ -51,5 +51,5 @@ index 1a7e0b1076..e9506ee830 100644
  	/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
  	u32 reg32;
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/target.cfg

@@ -1,4 +1,2 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
 tree="default"
-rev="c247f62749b967143e58c33aa0e5e234711a628f"
+rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"

config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch

@@ -0,0 +1,203 @@
+From 4fbd327df271d613d4a56a36eafd88d9d642ec6b Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 19 Feb 2023 18:21:43 +0000
+Subject: [PATCH 1/9] util/ifdtool: add --nuke flag (all 0xFF on region)
+
+When this option is used, the region's contents are overwritten
+with all ones (0xFF).
+
+Example:
+
+./ifdtool --nuke gbe coreboot.rom
+./ifdtool --nuke bios coreboot.com
+./ifdtool --nuke me coreboot.com
+
+Rebased since the last revision update in lbmk.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
+ 1 file changed, 81 insertions(+), 31 deletions(-)
+
+diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
+index 191b3216de..38132b4a28 100644
+--- a/util/ifdtool/ifdtool.c
++++ b/util/ifdtool/ifdtool.c
+@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
+ 	       "                                         tgl    - Tiger Lake\n"
+ 	       "                                         wbg    - Wellsburg\n"
+ 	       "   -S | --setpchstrap                    Write a PCH strap\n"
++	       "   -N | --nuke <region>                  Overwrite the specified region with 0xFF (all ones)\n"
+ 	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
+ 	       "   -v | --version:                       print the version\n"
+ 	       "   -h | --help:                          print this help\n\n"
+@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
+ 	       "\n");
+ }
+ 
++static int
++get_region_type_string(const char *region_type_string)
++{
++       if (!strcasecmp("Descriptor", region_type_string))
++               return 0;
++       else if (!strcasecmp("BIOS", region_type_string))
++               return 1;
++       else if (!strcasecmp("ME", region_type_string))
++               return 2;
++       else if (!strcasecmp("GbE", region_type_string))
++               return 3;
++       else if (!strcasecmp("Platform Data", region_type_string))
++               return 4;
++       else if (!strcasecmp("Device Exp1", region_type_string))
++               return 5;
++       else if (!strcasecmp("Secondary BIOS", region_type_string))
++               return 6;
++       else if (!strcasecmp("Reserved", region_type_string))
++               return 7;
++       else if (!strcasecmp("EC", region_type_string))
++               return 8;
++       else if (!strcasecmp("Device Exp2", region_type_string))
++               return 9;
++       else if (!strcasecmp("IE", region_type_string))
++               return 10;
++       else if (!strcasecmp("10GbE_0", region_type_string))
++               return 11;
++       else if (!strcasecmp("10GbE_1", region_type_string))
++               return 12;
++       else if (!strcasecmp("PTT", region_type_string))
++               return 15;
++       return -1;
++}
++
++static void
++nuke(const char *filename, char *image, int size, int region_type)
++{
++       int i;
++       struct region region;
++       const struct frba *frba = find_frba(image, size);
++       if (!frba)
++               exit(EXIT_FAILURE);
++
++       region = get_region(frba, region_type);
++       if (region.size > 0) {
++               for (i = region.base; i <= region.limit; i++) {
++                       if ((i + 1) > (size))
++                               break;
++                       image[i] = 0xFF;
++               }
++               write_image(filename, image, size);
++       }
++}
++
+ int main(int argc, char *argv[])
+ {
+ 	int opt, option_index = 0;
+@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
+ 	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
+ 	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
+ 	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
++	int mode_nuke = 0;
+ 	int mode_gpr0_disable = 0;
+ 	char *region_type_string = NULL, *region_fname = NULL;
+ 	const char *layout_fname = NULL;
+@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
+ 		{"validate", 0, NULL, 't'},
+ 		{"setpchstrap", 1, NULL, 'S'},
+ 		{"newvalue", 1, NULL, 'V'},
++		{"nuke", 1, NULL, 'N'},
+ 		{0, 0, 0, 0}
+ 	};
+ 
+@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
+ 			region_fname++;
+ 			// Descriptor, BIOS, ME, GbE, Platform
+ 			// valid type?
+-			if (!strcasecmp("Descriptor", region_type_string))
+-				region_type = 0;
+-			else if (!strcasecmp("BIOS", region_type_string))
+-				region_type = 1;
+-			else if (!strcasecmp("ME", region_type_string))
+-				region_type = 2;
+-			else if (!strcasecmp("GbE", region_type_string))
+-				region_type = 3;
+-			else if (!strcasecmp("Platform Data", region_type_string))
+-				region_type = 4;
+-			else if (!strcasecmp("Device Exp1", region_type_string))
+-				region_type = 5;
+-			else if (!strcasecmp("Secondary BIOS", region_type_string))
+-				region_type = 6;
+-			else if (!strcasecmp("Reserved", region_type_string))
+-				region_type = 7;
+-			else if (!strcasecmp("EC", region_type_string))
+-				region_type = 8;
+-			else if (!strcasecmp("Device Exp2", region_type_string))
+-				region_type = 9;
+-			else if (!strcasecmp("IE", region_type_string))
+-				region_type = 10;
+-			else if (!strcasecmp("10GbE_0", region_type_string))
+-				region_type = 11;
+-			else if (!strcasecmp("10GbE_1", region_type_string))
+-				region_type = 12;
+-			else if (!strcasecmp("PTT", region_type_string))
+-				region_type = 15;
+-			if (region_type == -1) {
++                       if ((region_type =
++                           get_region_type_string(region_type_string)) == -1) {
+ 				fprintf(stderr, "No such region type: '%s'\n\n",
+ 					region_type_string);
+ 				fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
+ 		case 't':
+ 			mode_validate = 1;
+ 			break;
++               case 'N':
++                       region_type_string = strdup(optarg);
++                       if (!region_type_string) {
++                               fprintf(stderr, "No region specified\n");
++                               print_usage(argv[0]);
++                               exit(EXIT_FAILURE);
++                       }
++                       if ((region_type =
++                           get_region_type_string(region_type_string)) == -1) {
++                               fprintf(stderr, "No such region type: '%s'\n\n",
++                                       region_type_string);
++                               print_usage(argv[0]);
++                               exit(EXIT_FAILURE);
++                       }
++                       mode_nuke = 1;
++                       break;
+ 		case 'v':
+ 			print_version();
+ 			exit(EXIT_SUCCESS);
+@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
+ 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ 			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
+ 			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
+-			mode_gpr0_disable) > 1) {
++			mode_gpr0_disable + mode_nuke) > 1) {
+ 		fprintf(stderr, "You may not specify more than one mode.\n\n");
+ 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ 		exit(EXIT_FAILURE);
+@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
+ 	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
+ 			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
+ 			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
+-			mode_validate + mode_gpr0_disable) == 0) {
++			mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
+ 		fprintf(stderr, "You need to specify a mode.\n\n");
+ 		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
+ 		exit(EXIT_FAILURE);
+@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
+ 		write_image(new_filename, image, size);
+ 	}
+ 
++       if (mode_nuke) {
++               nuke(new_filename, image, size, region_type);
++       }
++
+ 	if (mode_altmedisable) {
+ 		struct fpsba *fpsba = find_fpsba(image, size);
+ 		struct fmsba *fmsba = find_fmsba(image, size);
+-- 
+2.39.2
+

config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch

@@ -0,0 +1,47 @@
+From 362e86f89b3980699e7e794df9b98018397fe2d8 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Wed, 1 Dec 2021 02:53:00 +0000
+Subject: [PATCH 2/9] fix speedstep on x200/t400: Revert
+ "cpu/intel/model_1067x: enable PECI"
+
+This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
+
+Enabling PECI without microcode updates loaded causes the CPUID feature set
+to become corrupted. And one consequence is broken SpeedStep. At least, that's
+my understanding looking at Intel Errata. This revert is not a fix, because
+upstream is correct (upstream assumes microcode updates). We will simply
+maintain this revert patch in Libreboot, from now on.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 315e7c36fc..1423fd72bc 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
+ 	wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
+ }
+ 
+-#define IA32_PECI_CTL		0x5a0
+-
+ static void configure_misc(const int eist, const int tm2, const int emttm)
+ {
+ 	msr_t msr;
+@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
+ 		msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
+ 		wrmsr(IA32_MISC_ENABLE, msr);
+ 	}
+-
+-	/* Enable PECI
+-	   WARNING: due to Erratum AW67 described in Intel document #318733
+-	   the microcode must be updated before this MSR is written to. */
+-	msr = rdmsr(IA32_PECI_CTL);
+-	msr.lo |= 1;
+-	wrmsr(IA32_PECI_CTL, msr);
+ }
+ 
+ #define PIC_SENS_CFG	0x1aa
+-- 
+2.39.2
+

config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch

@@ -0,0 +1,173 @@
+From 883455573f07551eaf2b12ab80bedcd2b4904a17 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 17 Apr 2023 15:49:57 +0100
+Subject: [PATCH 3/9] GM45-type CPUs: don't enable alternative SMRR
+
+This reverts the changes in coreboot revision:
+df7aecd92643d207feaf7fd840f8835097346644
+
+While this fix is *technically correct*, the one in
+coreboot, it breaks rebooting as tested on several
+GM45 ThinkPads e.g. X200, T400, when microcode
+updates are not applied.
+
+Since November 2022, Libreboot includes microcode
+updates by default, but it tells users how to remove
+it from the ROM (with cbfstool) if they wish.
+
+Well, with Libreboot 20221214, 20230319 and 20230413,
+mitigations present in Libreboot 20220710 (which did
+not have microcode updates) do not exist.
+
+This patch, along with the other patch to remove PECI
+support (which breaks speedstep when microcode updates
+are not applied) have now been re-added to Libreboot.
+
+It is still best to use microcode updates by default.
+These patches in coreboot are not critically urgent,
+and you can use the machines with or without them,
+regardless of ucode.
+
+I'll probably re-write this and the other patch at
+some point, applying the change conditionally upon
+whether or not microcode is applied.
+
+Pragmatism is a good thing. I recommend it.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c |  4 +++
+ src/cpu/intel/model_1067x/mp_init.c          | 26 --------------------
+ src/cpu/intel/model_106cx/model_106cx_init.c |  4 +++
+ src/cpu/intel/model_6ex/model_6ex_init.c     |  4 +++
+ src/cpu/intel/model_6fx/model_6fx_init.c     |  4 +++
+ 5 files changed, 16 insertions(+), 26 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 1423fd72bc..d1f98ca43a 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -8,6 +8,7 @@
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
+ #include <cpu/intel/smm_reloc.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define MSR_BBL_CR_CTL3		0x11e
+ 
+@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states(quad);
+ 
+diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
+index bc53214310..72f40f6762 100644
+--- a/src/cpu/intel/model_1067x/mp_init.c
++++ b/src/cpu/intel/model_1067x/mp_init.c
+@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
+ 	smm_initialize();
+ }
+ 
+-#define SMRR_SUPPORTED (1 << 11)
+-
+ static void per_cpu_smm_trigger(void)
+ {
+-	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+-	if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
+-		set_feature_ctrl_vmx();
+-		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
+-		/* We don't care if the lock is already setting
+-		   as our smm relocation handler is able to handle
+-		   setups where SMRR is not enabled here. */
+-		if (ia32_ft_ctrl.lo & (1 << 0)) {
+-			/* IA32_FEATURE_CONTROL locked. If we set it again we
+-			   get an illegal instruction. */
+-			printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
+-			printk(BIOS_DEBUG, "SMRR status: %senabled\n",
+-			       ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
+-		} else {
+-			if (!CONFIG(SET_IA32_FC_LOCK_BIT))
+-				printk(BIOS_INFO,
+-				       "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
+-			ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
+-			wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
+-		}
+-	} else {
+-		set_vmx_and_lock();
+-	}
+-
+ 	/* Relocate the SMM handler. */
+ 	smm_relocate();
+ }
+diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
+index 05f5f327cc..0450c2ad83 100644
+--- a/src/cpu/intel/model_106cx/model_106cx_init.c
++++ b/src/cpu/intel/model_106cx/model_106cx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
+index 5bd1c32815..f3bb08cde3 100644
+--- a/src/cpu/intel/model_6ex/model_6ex_init.c
++++ b/src/cpu/intel/model_6ex/model_6ex_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
+index 535fb8fae7..f7b05facd2 100644
+--- a/src/cpu/intel/model_6fx/model_6fx_init.c
++++ b/src/cpu/intel/model_6fx/model_6fx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+-- 
+2.39.2
+

config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch

@@ -0,0 +1,28 @@
+From 458fe39e9cd2536cfa8671427e6f557396143339 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sat, 6 May 2023 15:53:41 -0600
+Subject: [PATCH 4/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
+ models
+
+Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6400/devicetree.cb | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
+index bb954cbd7b..e9f3915d17 100644
+--- a/src/mainboard/dell/e6400/devicetree.cb
++++ b/src/mainboard/dell/e6400/devicetree.cb
+@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
+ 		ops gm45_pci_domain_ops
+ 
+ 		device pci 00.0 on end # host bridge
+-		device pci 01.0 off end
++		device pci 01.0 on end
+ 		device pci 02.0 on end # VGA
+ 		device pci 02.1 on end # Display
+ 		device pci 03.0 on end # ME
+-- 
+2.39.2
+

config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -0,0 +1,39 @@
+From de4eeaf6d44cb05c60c0b0d54b43cdb88686b998 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Fri, 12 May 2023 19:55:15 -0600
+Subject: [PATCH 5/9] Remove warning for coreboot images built without a
+ payload
+
+I added this in upstream to prevent people from accidentally flashing
+roms without a payload resulting in a no boot situation, but in
+libreboot lbmk handles the payload and thus this warning always comes
+up. This has caused confusion and concern so just patch it out.
+---
+ payloads/Makefile.mk | 13 +------------
+ 1 file changed, 1 insertion(+), 12 deletions(-)
+
+diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
+index a2336aa876..4f1692a873 100644
+--- a/payloads/Makefile.mk
++++ b/payloads/Makefile.mk
+@@ -49,16 +49,5 @@ distclean-payloads:
+ print-repo-info-payloads:
+ 	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
+ 
+-ifeq ($(CONFIG_PAYLOAD_NONE),y)
+-show_notices:: warn_no_payload
+-endif
+-
+-warn_no_payload:
+-	printf "\n\t** WARNING **\n"
+-	printf "coreboot has been built without a payload. Writing\n"
+-	printf "a coreboot image without a payload to your board's\n"
+-	printf "flash chip will result in a non-booting system. You\n"
+-	printf "can use cbfstool to add a payload to the image.\n\n"
+-
+ .PHONY: force-payload coreinfo nvramcui
+-.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
++.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
+-- 
+2.39.2
+

config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch

@@ -0,0 +1,39 @@
+From 261454e47783b973b088e9dbea47bda02758dcb4 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 22 Oct 2023 15:02:25 +0100
+Subject: [PATCH 6/9] don't use github for the acpica download
+
+i have the tarball from a previous download, and i placed
+it on libreboot rsync, which then got mirrored to princeton.
+
+today, github's ssl cert was b0rking the hell out and i really
+really wanted to finish a build, and didn't want to wait for
+github to fix their httpd.
+
+so i'm now hosting this specific acpica tarball on rsync.
+
+this patch makes that URL be used, instead of the github one.
+
+that's the 2nd time i've had to patch coreboot's acpica download!
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 23a5caf2bb..36565a906c 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+ GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+ BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
++IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+ CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch

@@ -0,0 +1,36 @@
+From 622daa7c46de01530de60a7be32c8b9e48b356fd Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 5 Nov 2023 22:57:08 +0000
+Subject: [PATCH 7/9] use mirrorservice.org for gcc downloads
+
+the gnu.org 302 redirect often fails
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 36565a906c..4d4ca06113 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
+ # to the jenkins build as well, or the builder won't download it.
+ 
+ # GCC toolchain archive locations
+-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
+-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
+ IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch

@@ -1,7 +1,7 @@
-From 9e0a6aa376db81f9409eda92b6783a8262c1fedb Mon Sep 17 00:00:00 2001
+From f26df5dff7be4b0c9d8dced1cf6ed07472a174c7 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH 16/37] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH 8/9] nb/intel/gm45: Make DDR2 raminit work
 
 List of changes:
  - Update some timing and ODT values
@@ -20,10 +20,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  3 files changed, 106 insertions(+), 13 deletions(-)
 
 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
-index 5d9ac56606..338260ea7a 100644
+index d929533d92..997f8a0e5a 100644
 --- a/src/northbridge/intel/gm45/gm45.h
 +++ b/src/northbridge/intel/gm45/gm45.h
-@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
+@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
  int raminit_read_vco_index(void);
  u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
  
@@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644
 +	mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
  }
 -- 
-2.39.5
+2.39.2
 

config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch

@@ -0,0 +1,23 @@
+From f318da0563ecb2386ac368e04bad88a8aacbc83d Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Wed, 1 Nov 2023 16:33:11 +0000
+Subject: [PATCH 9/9] dell/e6400: crank up vram to 256MB (max)
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/dell/e6400/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
+index eeb6f47364..25dfa38cb5 100644
+--- a/src/mainboard/dell/e6400/cmos.default
++++ b/src/mainboard/dell/e6400/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Disable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=256M
+-- 
+2.39.2
+

config/coreboot/dell/patches/0010-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch

@@ -1,7 +1,7 @@
-From 7461210ecc7c8e41f3f941bd5ce7943e5f66c711 Mon Sep 17 00:00:00 2001
+From 6f4968919cf4e801caacf8392492457b79efa9c6 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Mon, 20 May 2024 10:24:16 -0600
-Subject: [PATCH 18/37] mb/dell/e6400: Use 100 MHz reference clock for display
+Subject: [PATCH] mb/dell/e6400: Use 100 MHz reference clock for display
 
 The E6400 uses a 100 MHz reference clock for spread spectrum support on
 LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
@@ -19,10 +19,10 @@ Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
  2 files changed, 7 insertions(+)
 
 diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
-index 417d95fd5d..6fe1b1c456 100644
+index 034de4be2b..4cb16af697 100644
 --- a/src/mainboard/dell/e6400/Kconfig
 +++ b/src/mainboard/dell/e6400/Kconfig
-@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS
+@@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS
  	select INTEL_GMA_HAVE_VBT
  	select EC_DELL_MEC5035
  
@@ -33,10 +33,10 @@ index 417d95fd5d..6fe1b1c456 100644
  	default "dell/e6400"
  
 diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
-index fef0d735b3..fc5df8b11a 100644
+index 2a266b9771..2432c9d78e 100644
 --- a/src/northbridge/intel/gm45/Kconfig
 +++ b/src/northbridge/intel/gm45/Kconfig
-@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
+@@ -13,6 +13,10 @@ config NORTHBRIDGE_INTEL_GM45
  
  if NORTHBRIDGE_INTEL_GM45
  
@@ -48,5 +48,5 @@ index fef0d735b3..fc5df8b11a 100644
  	select VBOOT_STARTS_IN_BOOTBLOCK
  
 -- 
-2.39.5
+2.45.1
 

config/coreboot/dell/target.cfg

@@ -0,0 +1,4 @@
+tree="dell"
+tree_depend="default"
+xtree="default"
+rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"

config/coreboot/dell3050micro_vfsp_16mb/config/libgfxinit_corebootfb

@@ -1,825 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-CONFIG_OPTION_BACKEND_NONE=y
-# CONFIG_USE_OPTION_TABLE is not set
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_3050"
-CONFIG_VGA_BIOS_ID="8086,0406"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=512
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0xEEE000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
-CONFIG_MAX_CPUS=16
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_OVERRIDE_DEVICETREE=""
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-CONFIG_PCIEXP_L1_SUB_STATE=y
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-CONFIG_USE_PM_ACPI_TIMER=y
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-# CONFIG_BOARD_DELL_E4300 is not set
-# CONFIG_BOARD_DELL_E6400 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_3050=y
-# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_DCACHE_RAM_BASE=0xfef00000
-CONFIG_DCACHE_RAM_SIZE=0x40000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
-CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
-CONFIG_USE_LEGACY_8254_TIMER=y
-# CONFIG_DEBUG_SMI is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
-CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
-CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
-CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
-CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x200000
-CONFIG_SMM_MODULE_STACK_SIZE=0x800
-CONFIG_ACPI_BERT_SIZE=0x0
-CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IFD_CHIPSET="sklkbl"
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_MAX_ROOT_PORTS=24
-CONFIG_PCR_BASE_ADDRESS=0xfd000000
-CONFIG_CPU_BCLK_MHZ=100
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
-CONFIG_CPU_XTAL_HZ=24000000
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
-CONFIG_SOC_INTEL_I2C_DEV_MAX=6
-# CONFIG_ENABLE_SATA_TEST_MODE is not set
-CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
-CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
-CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
-CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
-CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_FSP_PUBLISH_MBP_HOB=y
-CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
-CONFIG_MAX_HECI_DEVICES=5
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HAVE_PAM0_REGISTER=y
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
-CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
-CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
-CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
-CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
-CONFIG_SOC_INTEL_KABYLAKE=y
-CONFIG_SKYLAKE_SOC_PCH_H=y
-CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
-CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
-CONFIG_FSP_T_LOCATION=0xfffe0000
-CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
-CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_SOC_INTEL_COMMON=y
-
-#
-# Intel SoC Common Code for IP blocks
-#
-CONFIG_SOC_INTEL_COMMON_BLOCK=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
-CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
-# CONFIG_USE_COREBOOT_MP_INIT is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
-CONFIG_INTEL_CAR_NEM_ENHANCED=y
-# CONFIG_USE_INTEL_FSP_MP_INIT is not set
-CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
-CONFIG_HAVE_HYPERTHREADING=y
-# CONFIG_FSP_HYPERTHREADING is not set
-# CONFIG_INTEL_KEYLOCKER is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
-CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
-CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
-CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
-CONFIG_SOC_INTEL_CSE_RW_FILE=""
-CONFIG_SOC_INTEL_CSE_RW_VERSION=""
-CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
-CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
-CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
-CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
-CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
-CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
-CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
-# CONFIG_SOC_INTEL_DISABLE_IGD is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
-CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
-# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
-CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
-CONFIG_SA_ENABLE_DPR=y
-CONFIG_HAVE_CAPID_A_REGISTER=y
-CONFIG_HAVE_BDSM_BGSM_REGISTER=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
-
-#
-# Intel SoC Common PCH Code
-#
-CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
-CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
-CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
-CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
-CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
-CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
-
-#
-# Intel SoC Common coreboot stages and non-IP blocks
-#
-CONFIG_SOC_INTEL_COMMON_BASECODE=y
-CONFIG_SOC_INTEL_COMMON_RESET=y
-CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
-CONFIG_PAVP=y
-# CONFIG_MMA is not set
-CONFIG_SOC_INTEL_COMMON_NHLT=y
-# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_PARALLEL_MP_AP_WORK=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_CPU_PT_ROM_MAP_GB=512
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-
-#
-# Southbridge
-#
-# CONFIG_PCIEXP_HOTPLUG is not set
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_SMSC_SCH555x=y
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-# CONFIG_GOOGLE_PVMFW_CBMEM is not set
-CONFIG_UDK_BASE=y
-CONFIG_UDK_2017_BINDING=y
-CONFIG_UDK_2013_VERSION=2013
-CONFIG_UDK_2017_VERSION=2017
-CONFIG_UDK_202005_VERSION=202005
-CONFIG_UDK_202111_VERSION=202111
-CONFIG_UDK_202302_VERSION=202302
-CONFIG_UDK_202305_VERSION=202305
-CONFIG_UDK_VERSION=2017
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_HAVE_FSP_GOP=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_RUN_FSP_GOP is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y
-# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set
-# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set
-# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
-# CONFIG_DRIVERS_EFI_FW_INFO is not set
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-CONFIG_MRC_SETTINGS_PROTECT=y
-# CONFIG_DRIVERS_OPTION_CFR is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_DESIGNWARE=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-# CONFIG_FSP_USE_REPO is not set
-# CONFIG_DISPLAY_HOBS is not set
-# CONFIG_DISPLAY_UPD_DATA is not set
-CONFIG_PLATFORM_USES_FSP2_0=y
-CONFIG_PLATFORM_USES_FSP2_X86_32=y
-CONFIG_HAVE_INTEL_FSP_REPO=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_FSP_S_CBFS="fsps.bin"
-CONFIG_FSP_M_CBFS="fspm.bin"
-# CONFIG_FSP_FULL_FD is not set
-CONFIG_FSP_T_RESERVED_SIZE=0x0
-CONFIG_FSP_M_XIP=y
-CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
-CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
-CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
-CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
-# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
-# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Skylake"
-CONFIG_GFX_GMA_PCH="Sunrise_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-CONFIG_USE_PC_CMOS_ALTCENTURY=y
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_USB_ACPI=y
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
-# end of Memory initialization
-
-# CONFIG_STM is not set
-# CONFIG_INTEL_CBNT_SUPPORT is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_CUSTOM_MADT=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_ACPI_LPIT=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_ACPI_S1_NOT_SUPPORTED=y
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_ACPI_NHLT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
-# CONFIG_DISPLAY_FSP_HEADER is not set
-# CONFIG_VERIFY_HOBS is not set
-# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
-CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
-# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-CONFIG_HAVE_DEBUG_GPIO=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_GENERIC_GPIO_LIB=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/dell3050micro_vfsp_16mb/config/libgfxinit_txtmode

@@ -1,818 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-CONFIG_OPTION_BACKEND_NONE=y
-# CONFIG_USE_OPTION_TABLE is not set
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_3050"
-CONFIG_VGA_BIOS_ID="8086,0406"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=512
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0xEEE000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_MAX_CPUS=16
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_OVERRIDE_DEVICETREE=""
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-CONFIG_PCIEXP_L1_SUB_STATE=y
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-CONFIG_USE_PM_ACPI_TIMER=y
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-# CONFIG_BOARD_DELL_E4300 is not set
-# CONFIG_BOARD_DELL_E6400 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_3050=y
-# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_DCACHE_RAM_BASE=0xfef00000
-CONFIG_DCACHE_RAM_SIZE=0x40000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
-CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
-CONFIG_USE_LEGACY_8254_TIMER=y
-# CONFIG_DEBUG_SMI is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
-CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
-CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
-CONFIG_FSP_M_FILE="../../../vendorfiles/kabylake/Fsp_M.fd"
-CONFIG_FSP_S_FILE="../../../vendorfiles/kabylake/Fsp_S.fd"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x200000
-CONFIG_SMM_MODULE_STACK_SIZE=0x800
-CONFIG_ACPI_BERT_SIZE=0x0
-CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IFD_CHIPSET="sklkbl"
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_MAX_ROOT_PORTS=24
-CONFIG_PCR_BASE_ADDRESS=0xfd000000
-CONFIG_CPU_BCLK_MHZ=100
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
-CONFIG_CPU_XTAL_HZ=24000000
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
-CONFIG_SOC_INTEL_I2C_DEV_MAX=6
-# CONFIG_ENABLE_SATA_TEST_MODE is not set
-CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
-CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
-CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
-CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
-CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_FSP_PUBLISH_MBP_HOB=y
-CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
-CONFIG_MAX_HECI_DEVICES=5
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HAVE_PAM0_REGISTER=y
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
-CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
-CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
-CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
-CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
-CONFIG_SOC_INTEL_KABYLAKE=y
-CONFIG_SKYLAKE_SOC_PCH_H=y
-CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
-CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
-CONFIG_FSP_T_LOCATION=0xfffe0000
-CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
-CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_SOC_INTEL_COMMON=y
-
-#
-# Intel SoC Common Code for IP blocks
-#
-CONFIG_SOC_INTEL_COMMON_BLOCK=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
-CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
-# CONFIG_USE_COREBOOT_MP_INIT is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
-CONFIG_INTEL_CAR_NEM_ENHANCED=y
-# CONFIG_USE_INTEL_FSP_MP_INIT is not set
-CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
-CONFIG_HAVE_HYPERTHREADING=y
-# CONFIG_FSP_HYPERTHREADING is not set
-# CONFIG_INTEL_KEYLOCKER is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
-CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
-CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
-CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
-CONFIG_SOC_INTEL_CSE_RW_FILE=""
-CONFIG_SOC_INTEL_CSE_RW_VERSION=""
-CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
-CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
-CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
-CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
-CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
-CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
-CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
-# CONFIG_SOC_INTEL_DISABLE_IGD is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
-CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
-# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
-CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
-CONFIG_SA_ENABLE_DPR=y
-CONFIG_HAVE_CAPID_A_REGISTER=y
-CONFIG_HAVE_BDSM_BGSM_REGISTER=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
-
-#
-# Intel SoC Common PCH Code
-#
-CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
-CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
-CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
-CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
-CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
-CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
-
-#
-# Intel SoC Common coreboot stages and non-IP blocks
-#
-CONFIG_SOC_INTEL_COMMON_BASECODE=y
-CONFIG_SOC_INTEL_COMMON_RESET=y
-CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
-CONFIG_PAVP=y
-# CONFIG_MMA is not set
-CONFIG_SOC_INTEL_COMMON_NHLT=y
-# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_PARALLEL_MP_AP_WORK=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_CPU_PT_ROM_MAP_GB=512
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-
-#
-# Southbridge
-#
-# CONFIG_PCIEXP_HOTPLUG is not set
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_SMSC_SCH555x=y
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-# CONFIG_GOOGLE_PVMFW_CBMEM is not set
-CONFIG_UDK_BASE=y
-CONFIG_UDK_2017_BINDING=y
-CONFIG_UDK_2013_VERSION=2013
-CONFIG_UDK_2017_VERSION=2017
-CONFIG_UDK_202005_VERSION=202005
-CONFIG_UDK_202111_VERSION=202111
-CONFIG_UDK_202302_VERSION=202302
-CONFIG_UDK_202305_VERSION=202305
-CONFIG_UDK_VERSION=2017
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_HAVE_FSP_GOP=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_RUN_FSP_GOP is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
-# CONFIG_DRIVERS_EFI_FW_INFO is not set
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-CONFIG_MRC_SETTINGS_PROTECT=y
-# CONFIG_DRIVERS_OPTION_CFR is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_DESIGNWARE=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-# CONFIG_FSP_USE_REPO is not set
-# CONFIG_DISPLAY_HOBS is not set
-# CONFIG_DISPLAY_UPD_DATA is not set
-CONFIG_PLATFORM_USES_FSP2_0=y
-CONFIG_PLATFORM_USES_FSP2_X86_32=y
-CONFIG_HAVE_INTEL_FSP_REPO=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_FSP_S_CBFS="fsps.bin"
-CONFIG_FSP_M_CBFS="fspm.bin"
-# CONFIG_FSP_FULL_FD is not set
-CONFIG_FSP_T_RESERVED_SIZE=0x0
-CONFIG_FSP_M_XIP=y
-CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
-CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
-CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
-CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
-# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
-# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Skylake"
-CONFIG_GFX_GMA_PCH="Sunrise_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-CONFIG_USE_PC_CMOS_ALTCENTURY=y
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_USB_ACPI=y
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
-# end of Memory initialization
-
-# CONFIG_STM is not set
-# CONFIG_INTEL_CBNT_SUPPORT is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_CUSTOM_MADT=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_ACPI_LPIT=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_ACPI_S1_NOT_SUPPORTED=y
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_ACPI_NHLT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
-# CONFIG_DISPLAY_FSP_HEADER is not set
-# CONFIG_VERIFY_HOBS is not set
-# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
-CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
-# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-CONFIG_HAVE_DEBUG_GPIO=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_GENERIC_GPIO_LIB=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/dell3050micro_vfsp_16mb/target.cfg

@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-3.0-or-later
-
-tree="default"
-xarch="i386-elf"
-payload_seabios="y"
-payload_grub="y"
-payload_memtest="y"
-grub_scan_disk="nvme ahci"
-grubtree="xhci"
-vcfg="3050micro"
-build_depend="seabios/default grub/xhci memtest86plus u-boot/amd64coreboot"
-IFD_platform="sklkbl"
-payload_uboot_amd64="y"

config/coreboot/dell7010sff_12mb/config/libgfxinit_txtmode

@@ -1,703 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-CONFIG_NO_STAGE_CACHE=y
-# CONFIG_TSEG_STAGE_CACHE is not set
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MITAC_COMPUTING is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_NOVACUSTOM is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 9010"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/snb_ivb_workstations"
-CONFIG_VGA_BIOS_ID="8086,0106"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0xBE5000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_MAX_CPUS=8
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_VARIANT_DIR="optiplex_9010_sff"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-CONFIG_DEVICETREE="variants/baseboard/devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-CONFIG_PCIEXP_L1_SUB_STATE=y
-# CONFIG_PCIEXP_CLK_PM is not set
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_DRAM_RESET_GATE_GPIO=60
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=64
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_USBDEBUG_HCD_INDEX=2
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="Precision T1650"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-CONFIG_TPM_PIRQ=0x0
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-# CONFIG_BOARD_DELL_E4300 is not set
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_9010=y
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_BOARD_DELL_SNB_IVB_WORKSTATIONS=y
-CONFIG_INCLUDE_SMSC_SCH5545_EC_FW=y
-CONFIG_SMSC_SCH5545_EC_FW_FILE="../../../vendorfiles/t1650/sch5545ec.bin"
-CONFIG_DCACHE_RAM_BASE=0xfefe0000
-CONFIG_DCACHE_RAM_SIZE=0x20000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x10000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/t1650/12_ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/t1650/me.bin"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/t1650/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-# CONFIG_TPM_MEASURED_BOOT is not set
-CONFIG_BOARD_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_12288=y
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=12288
-CONFIG_ROM_SIZE=0x00c00000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="northbridge/intel/sandybridge/chipset.cb"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_X86_64_SUPPORT is not set
-CONFIG_SERIRQ_CONTINUOUS_MODE=y
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xf0000000
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0x48254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-# CONFIG_ALWAYS_ALLOW_ABOVE_4G_ALLOCATION is not set
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_206AX=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_CPU_PT_ROM_MAP_GB=4
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_USE_NATIVE_RAMINIT=y
-CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
-# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_MAX_DIMMS is not set
-# CONFIG_NATIVE_RAMINIT_IGNORE_XMP_REQUESTED_VOLTAGE is not set
-# CONFIG_RAMINIT_ALWAYS_ALLOW_DLL_OFF is not set
-CONFIG_RAMINIT_ENABLE_ECC=y
-CONFIG_IGD_DEFAULT_UMA_SIZE_32MB=y
-# CONFIG_IGD_DEFAULT_UMA_SIZE_64MB is not set
-# CONFIG_IGD_DEFAULT_UMA_SIZE_96MB is not set
-# CONFIG_IGD_DEFAULT_UMA_SIZE_128MB is not set
-CONFIG_IGD_DEFAULT_UMA_INDEX=0
-
-#
-# Southbridge
-#
-CONFIG_SOUTHBRIDGE_INTEL_BD82X6X_COMMON=y
-CONFIG_SOUTHBRIDGE_INTEL_C216=y
-# CONFIG_HIDE_MEI_ON_ERROR is not set
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_ME=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_HAVE_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_INTEL_CHIPSET_LOCKDOWN=y
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_SMSC_SCH5545=y
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-# CONFIG_GOOGLE_PVMFW_CBMEM is not set
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x04000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-# CONFIG_DRIVERS_OPTION_CFR is not set
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_TPM_INIT_RAMSTAGE=y
-# CONFIG_TPM_PPI is not set
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_EMULATION_QEMU_FW_CFG is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_INT15=y
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Ironlake"
-CONFIG_GFX_GMA_PCH="Cougar_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_MEMORY_MAPPED_TPM=y
-CONFIG_TPM_TIS_BASE_ADDRESS=0xfed40000
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_TPM1=y
-# CONFIG_TPM2 is not set
-CONFIG_TPM=y
-CONFIG_MAINBOARD_HAS_TPM1=y
-# CONFIG_TPM_DEACTIVATE is not set
-# CONFIG_DEBUG_TPM is not set
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
-# end of Memory initialization
-
-# CONFIG_INTEL_TXT is not set
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xf0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-
-#
-# Boot Logo Configuration
-#
-# CONFIG_BMP_LOGO is not set
-# end of Boot Logo Configuration
-
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y