haswell: disable igpu when dgpu is used

normally, haswell mrc.bin handles this, if hide-peg-from-mrc
is disabled, broadwell mrc allows use of both gpus - so i had
to disable it in coreboot, using the normal method in gma.c

Signed-off-by: Leah Rowe <leah@libreboot.org>

.gitignore

@@ -1,9 +1,8 @@
 *~
 *.o
-/cache/
 /lbmk.err.log
-/repo/
 /docs/
+/cbutils/
 /pciroms/
 /util/dell-flash-unlock/dell_flash_unlock
 /TODO
@@ -30,9 +29,3 @@
 /mrc/
 /util/nvmutil/nvm
 /src/
-/CHANGELOG
-/todo.txt
-/lock
-/hash/
-/dump/
-/qrun*.sh

README.md

@@ -94,7 +94,7 @@ easy to do so.
 Not a coreboot fork!
 --------------------
 
-Libreboot is *not a fork of coreboot*. Every so often, the project
+Libreboot is not a fork of coreboot. Every so often, the project
 re-bases on the latest version of coreboot, with the number of custom
 patches in use minimized. Tested, *stable* (static) releases are then provided
 in Libreboot, based on specific coreboot revisions.
@@ -111,7 +111,7 @@ written in Markdown and hosted in a [separate
 repository](https://codeberg.org/libreboot/lbwww) where you can send patches.
 
 Any and all development discussion and user support are all done on the IRC
-channel. More information is on <https://libreboot.org/contact.html>.
+channel. More information is on https://libreboot.org/contact.html.
 
 LICENSE FOR THIS README
 =======================

build

@@ -1,132 +1,150 @@
 #!/usr/bin/env sh
 # SPDX-License-Identifier: GPL-3.0-or-later
-# Copyright (c) 2014-2015,2020-2024 Leah Rowe <leah@libreboot.org>
+# SPDX-FileCopyrightText: 2014,2015,2020,2021,2023 Leah Rowe <leah@libreboot.org>
-# Copyright (c) 2015 Patrick "P. J." McDermott <pj@pehjota.net>
+# SPDX-FileCopyrightText: 2015 Patrick "P. J." McDermott <pj@pehjota.net>
-# Copyright (c) 2015-2016 Klemens Nanni <contact@autoboot.org>
+# SPDX-FileCopyrightText: 2015, 2016 Klemens Nanni <contact@autoboot.org>
-# Copyright (c) 2022 Caleb La Grange <thonkpeasant@protonmail.com>
+# SPDX-FileCopyrightText: 2022, Caleb La Grange <thonkpeasant@protonmail.com>
 
 set -u -e
 
-if [ "./${0##*/}" != "${0}" ] || [ ! -f "build" ] || [ -L "build" ]; then
+export LC_COLLATE=C
-	printf "You must run this in the proper work directory.\n" 1>&2
+export LC_ALL=C
-	exit 1
+
+. "include/err.sh"
+. "include/option.sh"
+
+eval "$(setvars "" option aur_notice tmpdir)"
+
+tmpdir_was_set="y"
+set | grep TMPDIR 1>/dev/null 2>/dev/null || tmpdir_was_set="n"
+if [ "${tmpdir_was_set}" = "y" ]; then
+	[ "${TMPDIR%_*}" = "/tmp/lbmk" ] || tmpdir_was_set="n"
+fi
+if [ "${tmpdir_was_set}" = "n" ]; then
+	export TMPDIR="/tmp"
+	tmpdir="$(mktemp -d -t lbmk_XXXXXXXX)"
+	export TMPDIR="${tmpdir}"
+else
+	export TMPDIR="${TMPDIR}"
+	tmpdir="${TMPDIR}"
 fi
 
-. "include/lib.sh"
+linkpath="${0}"
-. "include/vendor.sh"
+linkname="${linkpath##*/}"
-. "include/mrc.sh"
+buildpath="./script/${linkname}"
-
-eval `setvars "" vdir src_dirname srcdir mode xp ser`
-err="fail"
 
 main()
 {
-	[ $# -lt 1 ] && $err "bad command"
+	xx_ id -u 1>/dev/null 2>/dev/null
-	spath="script/$1"; shcmd="shift 1"
+	[ $# -lt 1 ] && fail "Too few arguments. Try: ${0} help"
-	[ "${1#-*}" != "$1" ] && spath="script/trees" && shcmd=":"
 
-	for g in "which git" "git config --global user.name" \
+	[ "$1" = "dependencies" ] && xx_ install_packages $@ && lbmk_exit 0
-	    "git config --global user.email" "git_init"; do
+
-		eval "$g 1>/dev/null 2>/dev/null || $err \"Unconfigured: $g\""
+	for cmd in initcmd check_git check_project git_init excmd; do
+		eval "${cmd} \$@"
 	done
-
+	lbmk_exit 0
-	case "${spath#script/}" in
-	version) printf "%s\nWebsite: %s\n" "$relname" "$projectsite" ;;
-	release) shift 1; mkrelease $@ ;;
-	inject) shift 1; vendor_inject $@ ;;
-	download) shift 1; vendor_download $@ ;;
-	roms)
-		[ $# -gt 1 ] && [ "$2" = "serprog" ] && \
-		    mk -b stm32-vserprog pico-serprog && return 0
-		shift 1; x_ ./mk -b coreboot $@ ;;
-	*)
-		[ -f "$spath" ] || $err "bad command"
-		$shcmd; "$spath" $@ || $err "excmd: $spath $(echo "$@")" ;;
-	esac
-	set -u -e # some commands disable them. turn them on!
 }
 
+initcmd()
+{
+	[ "$(id -u)" != "0" ] || fail "this command as root is not permitted"
+
+	check_project
+
+	case "${1}" in
+	help) usage ${0} ;;
+	list) items "${buildpath}" ;;
+	version) mkversion ;;
+	*)
+		option="${1}"
+		return 0 ;;
+	esac
+	lbmk_exit 0
+}
+
+install_packages()
+{
+	if [ $# -lt 2 ]; then
+		printf "You must specify a distro, namely:\n" 1>&2
+		printf "Look at files under config/dependencies/\n" 1>&2
+		printf "Example: ./build dependencies debian\n" 1>&2
+		fail "install_packages: target not specified"
+	fi
+
+	[ -f "config/dependencies/${2}" ] || fail "Unsupported target"
+
+	. "config/dependencies/${2}"
+
+	xx_ ${pkg_add} ${pkglist}
+	[ -z "${aur_notice}" ] && return 0
+	printf "You must install AUR packages: %s\n" "$aur_notice" 1>&2
+}
+
+# release archives contain .gitignore, but not .git.
+# lbmk can be run from lbmk.git, or an archive.
 git_init()
 {
-	[ -L ".git" ] && return 1
+	[ -L ".git" ] && fail "Reference .git is a symlink"
 	[ -e ".git" ] && return 0
-	eval `setvars "$(date -Rud @$versiondate)" cdate _nogit`
+	eval "$(setvars "$(date -Rd @${versiondate})" cdate _nogit)"
 
-	git init || return 1
+	git init || fail "${PWD}: cannot initialise Git repository"
-	git add -A . || return 1
+	git add -A . || fail "${PWD}: cannot add files to Git repository"
-	git commit -m "$projectname $version" --date "$cdate" \
+	git commit -m "${projectname} ${version}" --date "${cdate}" \
-	    --author="xbmk <xbmk@example.com>" || return 1
+	    --author="lbmk <lbmk@libreboot.org>" || \
-	git tag -a "$version" -m "$projectname $version" || return 1
+	    fail "$PWD: can't commit ${projectname}/${version}, date $cdate"
+	git tag -a "${version}" -m "${projectname} ${version}" || \
+	    fail "${PWD}: cannot git-tag ${projectname}/${version}"
 }
 
-mkrelease()
+excmd()
 {
-	export XBMK_RELEASE="y"
+	lbmkcmd="${buildpath}/${option}"
-
+	[ -f "${lbmkcmd}" ] || fail "Invalid command. Run: ${linkpath} help"
-	vdir="release"
+	shift 1; "$lbmkcmd" $@ || fail "excmd: ${lbmkcmd} ${@}"
-	while getopts d:m: option; do
-		[ -z "$OPTARG" ] && $err "empty argument not allowed"
-		case "$option" in
-		d) vdir="$OPTARG" ;;
-		m) mode="$OPTARG" ;;
-		*) $err "invalid option '-$option'" ;;
-		esac
-	done
-
-	vdir="$vdir/$version"
-	src_dirname="${relname}_src"
-	srcdir="$vdir/$src_dirname"
-
-	[ -e "$vdir" ] && $err "already exists: \"$vdir\""
-	mkdir -p "$vdir" || $err "mkvdir: !mkdir -p \"$vdir\""
-	git clone . "$srcdir" || $err "mkdir: !gitclone \"$srcdir\""
-	touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
-
-	build_release
-
-	printf "\n\nDONE! Check release files under %s\n" "$vdir"
 }
 
-build_release()
+usage()
 {
-	(
+	progname=${0}
-	cd "$srcdir" || $err "$vdir: !cd \"$srcdir\""
+	cat <<- EOF
-	./mk -f; x_ rm -Rf tmp; rmgit .
+	$(mkversion)
-	x_ mv src/docs docs
-	) || $err "can't create release files"
 
-	git log --graph --pretty=format:'%Cred%h%Creset %s %Creset' \
+	USAGE:	${progname} <OPTION>
-	    --abbrev-commit > "$srcdir/CHANGELOG" || $err "!gitlog $srcdir"
-	rm -f "$srcdir/lock" || $err "can't remove lock file in $srcdir"
 
-	(
+	possible values for 'OPTION':
-	cd "${srcdir%/*}" || $err "$vdir: mktarball \"$srcdir\""
+	$(items "${buildpath}")
-	mktarball "${srcdir##*/}" "${srcdir##*/}.tar.xz" || $err "$vdir: mksrc"
-	) || $err "can't create src tarball"
-	[ "$mode" = "src" ] && return 0
 
-	touch "$srcdir/lock" || $err "can't make lock file in $srcdir/"
+	To know what ${projectname} version you're on, type:
-	(
+	${progname} version
-	cd "$srcdir" || $err "$vdir: 2 !cd \"$srcdir\""
-	mk -b coreboot pico-serprog stm32-vserprog pcsx-redux
-	x_ mv bin ../roms
-	) || $err "can't build rom images"
 
-	rm -Rf "$srcdir" || $err "!rm -Rf $srcdir"
+	Refer to ${projectname} documentation for more info.
+	EOF
+}
+
+mkversion()
+{
+	printf "revision: %s %s\n" "$projectname" "$version"
+	printf "revision date: %s\n" "$(date -Rud @${versiondate})"
+}
+
+lbmk_exit()
+{
+	tmp_cleanup || err "lbmk_exit: can't rm tmpdir upon exit $1: $tmpdir"
+	exit $1
 }
 
 fail()
 {
-	tmp_cleanup || printf "WARNING: can't rm tmpfiles: %s\n" "$TMPDIR" 1>&2
+	tmp_cleanup || printf "WARNING: can't rm tmpdir: %s\n" "$tmpdir" 1>&2
-	err_ "${1}"
+	err "${1}"
 }
 
 tmp_cleanup()
 {
-	[ "$xbmk_parent" = "y" ] || return 0
+	[ "${tmpdir_was_set}" = "n" ] || return 0
-	[ "$TMPDIR" = "/tmp" ] || rm -Rf "$TMPDIR" || return 1
+	rm -Rf "${tmpdir}" || return 1
-	rm -f lock || return 1
 }
 
 main $@
-tmp_cleanup || err_ "can't rm TMPDIR upon non-zero exit: $TMPDIR"

config/coreboot/build.list

@@ -0,0 +1 @@
+build/coreboot.rom

config/coreboot/d510mo/config/libgfxinit_txtmode

@@ -6,6 +6,7 @@
 #
 # General setup
 #
+CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -36,6 +37,7 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_TSEG_STAGE_CACHE is not set
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
 
 #
 # Software Bill Of Materials (SBOM)
@@ -53,8 +55,8 @@ CONFIG_NO_STAGE_CACHE=y
 #
 # CONFIG_VENDOR_51NB is not set
 # CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
 # CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
@@ -65,13 +67,11 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
@@ -93,7 +93,6 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_PRODRIVE is not set
 # CONFIG_VENDOR_PROTECTLI is not set
 # CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
 # CONFIG_VENDOR_RAZER is not set
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
@@ -124,17 +123,15 @@ CONFIG_DEVICETREE="devicetree.cb"
 # CONFIG_VBOOT is not set
 CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=256
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -147,13 +144,14 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_ADLRVP_P is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -161,9 +159,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
 # CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
-# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
 # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
-# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
 # CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
 
 #
@@ -208,16 +204,13 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
 CONFIG_PCIEXP_HOTPLUG_BUSES=32
 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+# CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -257,7 +250,6 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -266,6 +258,7 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@@ -300,7 +293,6 @@ CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
 CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
 CONFIG_SMM_TSEG=y
 CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
 CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -378,7 +370,6 @@ CONFIG_HAVE_CF9_RESET=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
 # end of Chipset
 
 #
@@ -466,8 +457,6 @@ CONFIG_DRIVERS_MC146818=y
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -520,6 +509,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console

config/coreboot/d510mo/target.cfg

@@ -1,6 +1,6 @@
 tree="default"
 xarch="i386-elf"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
 payload_memtest="y"
-release="n"
-build_depend="seabios/default memtest86plus"

config/coreboot/d510mo_16mb/config/libgfxinit_txtmode

@@ -6,6 +6,7 @@
 #
 # General setup
 #
+CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -36,6 +37,7 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_TSEG_STAGE_CACHE is not set
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
 
 #
 # Software Bill Of Materials (SBOM)
@@ -53,8 +55,8 @@ CONFIG_NO_STAGE_CACHE=y
 #
 # CONFIG_VENDOR_51NB is not set
 # CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
 # CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
@@ -65,13 +67,11 @@ CONFIG_NO_STAGE_CACHE=y
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
@@ -93,7 +93,6 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_PRODRIVE is not set
 # CONFIG_VENDOR_PROTECTLI is not set
 # CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
 # CONFIG_VENDOR_RAZER is not set
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
@@ -124,17 +123,15 @@ CONFIG_DEVICETREE="devicetree.cb"
 # CONFIG_VBOOT is not set
 CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=256
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -147,13 +144,14 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_ADLRVP_P is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -161,9 +159,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
 # CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
-# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
 # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
-# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
 # CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
 
 #
@@ -208,16 +204,13 @@ CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D510MO"
 CONFIG_PCIEXP_HOTPLUG_BUSES=32
 CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
 CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+# CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_1024=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -257,7 +250,6 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x80000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -266,6 +258,7 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@@ -300,7 +293,6 @@ CONFIG_UDELAY_TSC=y
 CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
 CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
 CONFIG_SMM_TSEG=y
 CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
 CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -378,7 +370,6 @@ CONFIG_HAVE_CF9_RESET=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
 # end of Chipset
 
 #
@@ -466,8 +457,6 @@ CONFIG_DRIVERS_MC146818=y
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -520,6 +509,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console

config/coreboot/d510mo_16mb/target.cfg

@@ -1,6 +1,5 @@
 tree="default"
 xarch="i386-elf"
 payload_seabios="y"
-payload_grub="y"
+payload_seabios_withgrub="y"
 payload_memtest="y"
-release="n"

config/coreboot/d945gclf_512kb/config/libgfxinit_txtmode

@@ -6,6 +6,7 @@
 #
 # General setup
 #
+CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -36,6 +37,7 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
 CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
 
 #
 # Software Bill Of Materials (SBOM)
@@ -53,8 +55,8 @@ CONFIG_TSEG_STAGE_CACHE=y
 #
 # CONFIG_VENDOR_51NB is not set
 # CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
 # CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
@@ -65,13 +67,11 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
@@ -93,7 +93,6 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_PRODRIVE is not set
 # CONFIG_VENDOR_PROTECTLI is not set
 # CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
 # CONFIG_VENDOR_RAZER is not set
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
@@ -125,17 +124,15 @@ CONFIG_DEVICETREE="devicetree.cb"
 CONFIG_IRQ_SLOT_COUNT=18
 CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -148,13 +145,14 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_ADLRVP_P is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -162,9 +160,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
 # CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
-# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
 # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
-# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
 # CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
 
 #
@@ -206,17 +202,14 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+# CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
-CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 CONFIG_COREBOOT_ROMSIZE_KB_512=y
@@ -256,7 +249,6 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -265,6 +257,7 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@@ -299,7 +292,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
 CONFIG_SETUP_XIP_CACHE=y
 CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
 CONFIG_SMM_TSEG=y
 CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
 CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -377,7 +369,6 @@ CONFIG_HAVE_CF9_RESET=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
 # end of Chipset
 
 #
@@ -460,8 +451,6 @@ CONFIG_DRIVERS_MC146818=y
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -514,6 +503,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console

config/coreboot/d945gclf_512kb/target.cfg

@@ -1,5 +1,6 @@
 tree="default"
 xarch="i386-elf"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
-release="n"
+payload_memtest="n"
-build_depend="seabios/default"

config/coreboot/d945gclf_8mb/config/libgfxinit_txtmode

@@ -6,6 +6,7 @@
 #
 # General setup
 #
+CONFIG_COREBOOT_BUILD=y
 CONFIG_LOCALVERSION=""
 CONFIG_CBFS_PREFIX="fallback"
 CONFIG_COMPILER_GCC=y
@@ -36,6 +37,7 @@ CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
 CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_UPDATE_IMAGE is not set
 # CONFIG_BOOTSPLASH_IMAGE is not set
+# CONFIG_FW_CONFIG is not set
 
 #
 # Software Bill Of Materials (SBOM)
@@ -53,8 +55,8 @@ CONFIG_TSEG_STAGE_CACHE=y
 #
 # CONFIG_VENDOR_51NB is not set
 # CONFIG_VENDOR_ACER is not set
+# CONFIG_VENDOR_ADLINK is not set
 # CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
 # CONFIG_VENDOR_AOPEN is not set
 # CONFIG_VENDOR_APPLE is not set
 # CONFIG_VENDOR_ASROCK is not set
@@ -65,13 +67,11 @@ CONFIG_TSEG_STAGE_CACHE=y
 # CONFIG_VENDOR_CAVIUM is not set
 # CONFIG_VENDOR_CLEVO is not set
 # CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
 # CONFIG_VENDOR_DELL is not set
 # CONFIG_VENDOR_EMULATION is not set
 # CONFIG_VENDOR_EXAMPLE is not set
 # CONFIG_VENDOR_FACEBOOK is not set
 # CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
 # CONFIG_VENDOR_GETAC is not set
 # CONFIG_VENDOR_GIGABYTE is not set
 # CONFIG_VENDOR_GOOGLE is not set
@@ -93,7 +93,6 @@ CONFIG_VENDOR_INTEL=y
 # CONFIG_VENDOR_PRODRIVE is not set
 # CONFIG_VENDOR_PROTECTLI is not set
 # CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
 # CONFIG_VENDOR_RAZER is not set
 # CONFIG_VENDOR_RODA is not set
 # CONFIG_VENDOR_SAMSUNG is not set
@@ -125,17 +124,15 @@ CONFIG_DEVICETREE="devicetree.cb"
 CONFIG_IRQ_SLOT_COUNT=18
 CONFIG_OVERRIDE_DEVICETREE=""
 # CONFIG_VGA_BIOS is not set
-# CONFIG_PCIEXP_ASPM is not set
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-# CONFIG_PCIEXP_CLK_PM is not set
 CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Intel"
 CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
 CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
 CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
 CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
 CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
 # CONFIG_CONSOLE_POST is not set
+CONFIG_PS2K_EISAID="PNP0303"
+CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xf0000000
 CONFIG_ECAM_MMCONF_BUS_NUMBER=64
 CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
@@ -148,13 +145,14 @@ CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
 CONFIG_SPI_FLASH_WINBOND=y
 # CONFIG_DRIVERS_INTEL_WIFI is not set
 CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
 CONFIG_CARDBUS_PLUGIN_SUPPORT=y
 CONFIG_SPI_FLASH_GIGADEVICE=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_ADLRVP_P is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_P_MCHP is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M is not set
+# CONFIG_BOARD_INTEL_ADLRVP_M_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N is not set
 # CONFIG_BOARD_INTEL_ADLRVP_N_EXT_EC is not set
 # CONFIG_BOARD_INTEL_ADLRVP_RPL is not set
@@ -162,9 +160,7 @@ CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP1 is not set
 # CONFIG_BOARD_INTEL_APOLLOLAKE_RVP2 is not set
 # CONFIG_BOARD_INTEL_ARCHERCITY_CRB is not set
-# CONFIG_BOARD_INTEL_AVENUECITY_CRB is not set
 # CONFIG_BOARD_INTEL_BASKING_RIDGE is not set
-# CONFIG_BOARD_INTEL_BEECHNUTCITY_CRB is not set
 # CONFIG_BOARD_INTEL_CEDARISLAND_CRB is not set
 
 #
@@ -206,17 +202,14 @@ CONFIG_BOARD_INTEL_D945GCLF=y
 # CONFIG_BOARD_INTEL_WTM2 is not set
 # CONFIG_DEBUG_SMI is not set
 CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="D945GCLF"
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
 CONFIG_D3COLD_SUPPORT=y
+# CONFIG_PCIEXP_ASPM is not set
+# CONFIG_PCIEXP_L1_SUB_STATE is not set
+# CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
 CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
-CONFIG_HEAP_SIZE=0x100000
 CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
 CONFIG_BOARD_ROMSIZE_KB_512=y
 # CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
 # CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
@@ -256,7 +249,6 @@ CONFIG_VERSTAGE_ADDR=0x2000000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"
 CONFIG_STACK_SIZE=0x2000
@@ -265,6 +257,7 @@ CONFIG_INTEL_GMA_BCLV_WIDTH=16
 CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
 CONFIG_INTEL_GMA_BCLM_WIDTH=16
 CONFIG_BOOTBLOCK_IN_CBFS=y
+CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfe000000
 CONFIG_HPET_MIN_TICKS=0x80
 CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
 CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
@@ -299,7 +292,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
 CONFIG_TSC_SYNC_MFENCE=y
 CONFIG_SETUP_XIP_CACHE=y
 CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
 CONFIG_SMM_TSEG=y
 CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
 CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
@@ -377,7 +369,6 @@ CONFIG_HAVE_CF9_RESET=y
 CONFIG_DEBUG_HW_BREAKPOINTS=y
 CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
 # CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
 # end of Chipset
 
 #
@@ -460,8 +451,6 @@ CONFIG_DRIVERS_MC146818=y
 CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
 CONFIG_VGA=y
 # CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
 # end of Generic Drivers
 
 #
@@ -514,6 +503,7 @@ CONFIG_HAVE_ACPI_TABLES=y
 CONFIG_BOOT_DEVICE_SPI_FLASH=y
 CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
 CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
+CONFIG_HEAP_SIZE=0x100000
 
 #
 # Console

config/coreboot/d945gclf_8mb/target.cfg

@@ -1,6 +1,6 @@
 tree="default"
 xarch="i386-elf"
+payload_grub="n"
+payload_grub_withseabios="n"
 payload_seabios="y"
-payload_grub="y"
+payload_memtest="n"
-release="n"
-build_depend="seabios/default grub/default"

config/coreboot/default/patches/0001-apple-macbook21-Set-default-VRAM-to-64MiB-instead-of.patch

@@ -0,0 +1,23 @@
+From 1195c954a3b6822e5e843067251c0c80c9520eab Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@retroboot.org>
+Date: Fri, 19 Mar 2021 05:54:58 +0000
+Subject: [PATCH 01/30] apple/macbook21: Set default VRAM to 64MiB instead of
+ 8MiB
+
+---
+ src/mainboard/apple/macbook21/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default
+index cf1bc4566e..dc0df3b6d6 100644
+--- a/src/mainboard/apple/macbook21/cmos.default
++++ b/src/mainboard/apple/macbook21/cmos.default
+@@ -5,4 +5,4 @@ boot_devices=''
+ boot_default=0x40
+ cmos_defaults_loaded=Yes
+ lpt=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+

config/coreboot/default/patches/0002-add-c3-and-clockgen-to-apple-macbook21.patch

@@ -1,7 +1,7 @@
-From f625e31ee3abb867e775ab0cb724550825699c36 Mon Sep 17 00:00:00 2001
+From 50a52cea2b43e6e407b456c082e908c7d29e090b Mon Sep 17 00:00:00 2001
 From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
 Date: Wed, 27 Oct 2021 13:36:01 +0200
-Subject: [PATCH 01/51] add c3 and clockgen to apple/macbook21
+Subject: [PATCH 02/30] add c3 and clockgen to apple/macbook21
 
 ---
  src/mainboard/apple/macbook21/Kconfig       |  1 +
@@ -10,10 +10,10 @@ Subject: [PATCH 01/51] add c3 and clockgen to apple/macbook21
  3 files changed, 20 insertions(+)
 
 diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
-index 330d8efae2..cf10343554 100644
+index 5f5ffde588..27377b737c 100644
 --- a/src/mainboard/apple/macbook21/Kconfig
 +++ b/src/mainboard/apple/macbook21/Kconfig
-@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
+@@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS
  	select HAVE_ACPI_TABLES
  	select HAVE_ACPI_RESUME
  	select I945_LVDS
@@ -64,5 +64,5 @@ index fd86e939b9..263fbabcd1 100644
  	end
  end
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0003-lenovo-x60-64MiB-Video-RAM-changed-to-default-previo.patch

@@ -0,0 +1,23 @@
+From ca4cd66f411247395a323e5ea1abf09e83057827 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Sun, 3 Jan 2021 03:34:01 +0000
+Subject: [PATCH 03/30] lenovo/x60: 64MiB Video RAM changed to default
+ (previously it was 8MiB)
+
+---
+ src/mainboard/lenovo/x60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default
+index 5c3576d1f3..88170a1aab 100644
+--- a/src/mainboard/lenovo/x60/cmos.default
++++ b/src/mainboard/lenovo/x60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+

config/coreboot/default/patches/0004-lenovo-t60-make-64MiB-VRAM-the-default-in-cmos.defau.patch

@@ -0,0 +1,22 @@
+From eca0f4a3a4d6907e92b948547a362ca0ac3fc382 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@osboot.org>
+Date: Mon, 22 Feb 2021 22:16:59 +0000
+Subject: [PATCH 04/30] lenovo/t60: make 64MiB VRAM the default in cmos.default
+
+---
+ src/mainboard/lenovo/t60/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default
+index af865f16da..7f03157df7 100644
+--- a/src/mainboard/lenovo/t60/cmos.default
++++ b/src/mainboard/lenovo/t60/cmos.default
+@@ -15,4 +15,4 @@ trackpoint=Enable
+ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+-gfx_uma_size=8M
++gfx_uma_size=64M
+-- 
+2.39.2
+

config/coreboot/default/patches/0005-lenovo-t400-set-VRAM-to-256MiB-VRAM-by-default.patch

@@ -0,0 +1,23 @@
+From 2eae87815675aebd472b6042777fe51279be4550 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:10:33 +0100
+Subject: [PATCH 05/30] lenovo/t400: set VRAM to 256MiB VRAM by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/lenovo/t400/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default
+index a326e315b1..b907a3e2df 100644
+--- a/src/mainboard/lenovo/t400/cmos.default
++++ b/src/mainboard/lenovo/t400/cmos.default
+@@ -13,4 +13,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ hybrid_graphics_mode=Integrated Only
+-gfx_uma_size=32M
++gfx_uma_size=256M
+-- 
+2.39.2
+

config/coreboot/default/patches/0006-lenovo-x200-set-VRAM-to-256MiB-by-default.patch

@@ -0,0 +1,23 @@
+From f6b4913a5eca619b745d5ccea9af022a54fb185b Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:11:59 +0100
+Subject: [PATCH 06/30] lenovo/x200: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/lenovo/x200/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x200/cmos.default b/src/mainboard/lenovo/x200/cmos.default
+index bb4323836e..458b3f19c5 100644
+--- a/src/mainboard/lenovo/x200/cmos.default
++++ b/src/mainboard/lenovo/x200/cmos.default
+@@ -12,4 +12,4 @@ sticky_fn=Disable
+ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=256M
+-- 
+2.39.2
+

config/coreboot/default/patches/0007-gigabyte-ga-g41m-es2l-set-VRAM-to-256MiB-by-default.patch

@@ -0,0 +1,23 @@
+From a3a0969075163be413f968b03671aa5d8662672a Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:18:26 +0100
+Subject: [PATCH 07/30] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/gigabyte/ga-g41m-es2l/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+index 8372032119..bedad54d2a 100644
+--- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
++++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+-gfx_uma_size=64M
++gfx_uma_size=256M
+-- 
+2.39.2
+

config/coreboot/default/patches/0008-acer-g43t-am3-set-VRAM-to-256MiB-by-default.patch

@@ -0,0 +1,23 @@
+From 223ac17617b3a0c08925abbbe42d0d003e144a28 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Fri, 14 May 2021 13:21:39 +0100
+Subject: [PATCH 08/30] acer/g43t-am3: set VRAM to 256MiB by default
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/acer/g43t-am3/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/acer/g43t-am3/cmos.default b/src/mainboard/acer/g43t-am3/cmos.default
+index 706f5dd551..e8b45ea22c 100644
+--- a/src/mainboard/acer/g43t-am3/cmos.default
++++ b/src/mainboard/acer/g43t-am3/cmos.default
+@@ -3,4 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=64M
++gfx_uma_size=256M
+-- 
+2.39.2
+

config/coreboot/default/patches/0008-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch

@@ -1,430 +0,0 @@
-From 40545928c415c27d3a30748e4bfdee7f9d8f82f9 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sat, 19 Aug 2023 16:19:10 -0600
-Subject: [PATCH 08/51] mb/dell: Add Latitude E6530 (Ivy Bridge)
-
-Mainboard is QALA0/LA-7761P (UMA). The version with a Nvidia dGPU was
-not tested. I do not physically have this system; someone with physical
-access to one sent me the output of autoport which I then modified to
-produce this port.
-
-I was also sent the vbios obtained using intel_bios_dumper while running
-version A22 of the vendor firmware, which I then processed using
-`intelvbttool --inoprom vbios.bin --outvbt data.vbt` to obtain data.vbt.
-
-This was originally tested and found to be working as a standalone board
-port in Libreboot, though this variant based port in upstream coreboot
-has not been tested.
-
-This can be internally flashed by sending a command to the EC, which
-causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections [1]. The EC is the SMSC MEC5055,
-which seems to be compatible with the existing MEC5035 code.
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: I9fcd73416018574f8934962f92c8222d0101cb71
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |   8 +
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e6530/data.vbt  | Bin 0 -> 4280 bytes
- .../variants/e6530/early_init.c               |  14 ++
- .../snb_ivb_latitude/variants/e6530/gpio.c    | 192 ++++++++++++++++++
- .../variants/e6530/hda_verb.c                 |  32 +++
- .../variants/e6530/overridetree.cb            |  37 ++++
- 7 files changed, 286 insertions(+)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index be9ac37845..03377275f0 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -23,6 +23,12 @@ config BOARD_DELL_LATITUDE_E6430
- 	select MAINBOARD_USES_IFD_GBE_REGION
- 	select SOUTHBRIDGE_INTEL_C216
- 
-+config BOARD_DELL_LATITUDE_E6530
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_12288
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select SOUTHBRIDGE_INTEL_C216
-+
- if BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 
- config DRAM_RESET_GATE_GPIO
-@@ -33,6 +39,7 @@ config MAINBOARD_DIR
- 
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
-+	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
- 
- config OVERRIDE_DEVICETREE
- 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-@@ -42,6 +49,7 @@ config USBDEBUG_HCD_INDEX
- 
- config VARIANT_DIR
- 	default "e6430" if BOARD_DELL_LATITUDE_E6430
-+	default "e6530" if BOARD_DELL_LATITUDE_E6530
- 
- config VGA_BIOS_ID
- 	default "8086,0166"
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index 183252630a..d89185d670 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -2,3 +2,6 @@
- 
- config BOARD_DELL_LATITUDE_E6430
- 	bool "Latitude E6430"
-+
-+config BOARD_DELL_LATITUDE_E6530
-+	bool "Latitude E6530"
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
-GIT binary patch
-literal 4280
-zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV
-zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU
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-eZvUbDHC^NLu5~gtzg|!EqSkX2ep9pg!tpEeo1jDh
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c
-new file mode 100644
-index 0000000000..ff83db095b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/early_init.c
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c
-new file mode 100644
-index 0000000000..777570765a
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/gpio.c
-@@ -0,0 +1,192 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_GPIO,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio1 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+	.gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio13 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c
-new file mode 100644
-index 0000000000..3ebccff81d
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76df,	/* Codec Vendor / Device ID: IDT */
-+	0x10280535,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x10280535),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862806,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb
-new file mode 100644
-index 0000000000..8b9c82fba4
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6530/overridetree.cb
-@@ -0,0 +1,37 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x0535 inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x00000251"
-+			register "gpu_pch_backlight" = "0x13121312"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "usb_port_config" = "{
-+				{ 1, 1, 0 },
-+				{ 1, 1, 0 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 2 },
-+				{ 1, 0, 3 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 4 },
-+				{ 1, 1, 4 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 5 },
-+				{ 1, 2, 6 },
-+				{ 1, 2, 6 },
-+			}"
-+
-+			device ref xhci on
-+				register "superspeed_capable_ports" = "0x0000000f"
-+				register "xhci_overcurrent_mapping" = "0x00000c03"
-+				register "xhci_switchable_ports" = "0x0000000f"
-+			end
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0009-lenovo-t400-Enable-all-SATA-ports.patch

@@ -1,7 +1,7 @@
-From 8821f229d4fe48153ec7a45e0e04c3b2a3cd8c7c Mon Sep 17 00:00:00 2001
+From 80ebbfef42454ea0911e5fc3858103d905987ed8 Mon Sep 17 00:00:00 2001
 From: persmule <persmule@gmail.com>
 Date: Sun, 31 Oct 2021 23:33:26 +0000
-Subject: [PATCH 02/51] lenovo/t400: Enable all SATA ports
+Subject: [PATCH 09/30] lenovo/t400: Enable all SATA ports
 
 There are 2 SATA ports on the chassis of t400(s), but at least one dock for
 t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -30,5 +30,5 @@ index 259c3e1b21..3d007533a4 100644
  			register "sata_traffic_monitor"		= "0"
  
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0009-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch

@@ -1,430 +0,0 @@
-From 423e2e28618b08a4107aea0a2fbc1096f5a8be02 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Wed, 31 Jan 2024 22:57:07 -0700
-Subject: [PATCH 09/51] mb/dell: Add Latitude E5530 (Ivy Bridge)
-
-Mainboard is QXW10/LA-7902P (UMA). I do not physically have this board;
-someone with physical access to one sent me the output of autoport which
-I then modified to produce this port. I was also sent the VBT binary,
-which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
-version A21 of the vendor firmware.
-
-This was originally tested and found to be working as a standalone board
-port in Libreboot, but this variant based port in upstream coreboot has
-not been tested.
-
-This can be internally flashed by sending a command to the EC, which
-causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections [1]. The EC is the SMSC MEC5055,
-which seems to be compatible with the existing MEC5035 code.
-
-Change-Id: Idaf6618df70aa19d8e60b2263088737712dec5f0
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |   7 +
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e5530/data.vbt  | Bin 0 -> 6144 bytes
- .../variants/e5530/early_init.c               |  14 ++
- .../snb_ivb_latitude/variants/e5530/gpio.c    | 194 ++++++++++++++++++
- .../variants/e5530/hda_verb.c                 |  32 +++
- .../variants/e5530/overridetree.cb            |  39 ++++
- 7 files changed, 289 insertions(+)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index 03377275f0..183a67bec3 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select SYSTEM_TYPE_LAPTOP
- 	select USE_NATIVE_RAMINIT
- 
-+config BOARD_DELL_LATITUDE_E5530
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_12288
-+	select SOUTHBRIDGE_INTEL_C216
-+
- config BOARD_DELL_LATITUDE_E6430
- 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select BOARD_ROMSIZE_KB_12288
-@@ -38,6 +43,7 @@ config MAINBOARD_DIR
- 	default "dell/snb_ivb_latitude"
- 
- config MAINBOARD_PART_NUMBER
-+	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
- 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
- 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
- 
-@@ -48,6 +54,7 @@ config USBDEBUG_HCD_INDEX
- 	default 2
- 
- config VARIANT_DIR
-+	default "e5530" if BOARD_DELL_LATITUDE_E5530
- 	default "e6430" if BOARD_DELL_LATITUDE_E6430
- 	default "e6530" if BOARD_DELL_LATITUDE_E6530
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index d89185d670..c15ef4028f 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -1,5 +1,8 @@
- ## SPDX-License-Identifier: GPL-2.0-only
- 
-+config BOARD_DELL_LATITUDE_E5530
-+	bool "Latitude E5530"
-+
- config BOARD_DELL_LATITUDE_E6430
- 	bool "Latitude E6430"
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3
-GIT binary patch
-literal 6144
-zcmeHKU2Gdg5dO}0w$JA~+qs02q)iz56C9e5vuQ#oL0l3O+%|395Q2peO{y4(2uX0t
-zuMja1N)bPb1cE+5)fYsCK!89MFQAGChyWpk5PuR<K|G+sLmxmOR4}u5=Rg`mj70g7
-zvgdDic6N4dW^QKhynd)>kS^cR)3#-(r*-?zo-O^C(kLvv8XM<+Y3tdt^YY!P?!oTe
-zJ^ed-x6w0Lh5fN#jsv5TWE#mtd*_yky}9xDK(kOwLt+C7_AQAd#iwr=o0`gvQZ`{x
-z6ZeT`x^^;8+a~jSa^o~PF@8J6N5;o#dhCwebaM;!_oisw1#O9K={qQM<@Oeu$lXeN
-z#wJGcW4Y<2)-A{Bot(NoKX%>qdnw-AOi9bKT9Z~HL5|7PJDHz4kGlEx143q+26EH6
-z{4KfB^9;?<fTOaiNPy%=@LovL&q<^d1Qdi+Xex9SvIM^ZLq%9cP{A1rE>#dw(WfA;
-zBCR3@pCS1a;A|CZW1h7H*l#mW{%y{bf)9ofiz!EHzyiac@{RpMzz>O-<~{hx5tw%b
-z3ZJWD4_g-`iF`tUJb}+Vfe;XI1T2Y4_Y!iVk<<T4ce(^PWKh<?N^a`t+}vgNr25iZ
-z`!fTBL)ojYF5G?3y|eW=`9>MLB9et&!A7LDDE7&5ye#|hn%s#IWgagDEPNHHMUhb-
-ztc9t?uz{bD#kh#kpsE;AO-wWHV?4olPStRPag^~k<737bjBgm<GlC%vRgBe)4U9I%
-zg^XUtcE**A5ylOSn;A2V2N;hso?--U#>t|ufS}_`LGs2bcSKCVBh4s0>G7ZR_@NWx
-zkph}GhP}~YR?roT!61GqzQ?gBsuv3jY}UXbmr|alv^VxUqbz5<`5=!hhpaa*7DK~4
-zP4ad6dhH!>nYpc4{J&G-w{UiWo$zXnTz{tAq0|?c_`QJ7pKmCwIpe7Uix$P?9}v*1
-z(aVR6OkMkQ6oM}*UC@j78!~>7=OZCVYXeu|u0SiI4}w$uw6&0P09LF%Hp}O&IA3gl
-z4@ap0NfAe+q(ZVm{Bwe*Do~kbCc$Q!x7b3Sk9tLgVmsR<Q4H=9Nl;mmf2xpY<*d*-
-z`yI_BR#`La=Oxxt#qgS`3pER^nh^CZ%*qlq2N9@uSAtz-C7AhduB_U|{>#oOrY`tq
-z%|?L!zRd2-$V6^@$H<Mj3MXf#F<J+^8%<X2{tnmQTI*aK*ageBrm9^|<Ked3j_s;%
-zva<(Dob)BOwdcj8Z67UhYUAjbk==Of9W#D7k!DJobLx$$fXD_wuZyD&Kk-$EIY~S`
-zan1ANbFUW8hZ0pUw5)y??*}!;chdgq|0X5;s;m`@YdY{zs4z#z8e;13T6b4tC7gy$
-zTwszEQhk0!U$`3=Qi)ZbY^*|bAyvF>@ml^iaX;uzoVB3JA(|h9tcNKXHdA43N0|18
-z&3$2QE=)(l=6qQDAWT1oO-<KoblR+&{kk@!)1A8ch^`&b>2=+FU)Mg<35IDJ+8Tp;
-z40F)Xt}$rVFdsLxLk7KRn4cKhmj<a3vp%A&kI>eLd38j)HbM_Y%!3i_aD?8An8za8
-z@d(AD=Gv&%5;e{}p%i?_q(T*^IwzEx*Eu1wKHV9=lVUvjqv!B@cWER!2fe%`IqO?q
-z!=Wf4kzGUaLX8`m#*P^uL?%M#6qc9Qu(YT|ZMb#7UzCc_(DkQYEG<G&Q*QkX`CS`I
-z8cwQnl8A#CMH~W79L&{2*Jof_MD5t{bPTAszWUa20yPzD=*wW8)wHSu?avDhffu^!
-zL>Q#%k_O0@^DN5S@MXi$D;acJ>#cTV-(U@Offv4ACp4hO4$Ll!WO)s3P4=t9vpWBC
-zSckhlcD?xUuX=Gx96Dx{IsQ23r&;o1*+^Cp2RA3nd$A-RIHP2Q7uitC>c67FIR*5}
-zB3a%B!?6K=TJ$W+SJv@*9Lms{mTvWmU4Zanj_Z*lSqOGISzYp?yawOqLhVhRt#-E6
-zd)YW~h&meh-5prIE}Cr&7f?MMi&cqTt_^%Fa?>k(=`9jVoIf@}{g+WX#TpWuc+!2v
-zPG^>A|NZ2GlGsKdGqN{7>Fr7+Hc_^3z}uBhC4?nzOQ*!QyVugGjkK_~$bvtfY`h79
-z9rOI3;Mt}9)_G{zXTAPw`8T@6=Ut0r9R5;0#Zy|#8F;v4^UAmqft3iXL|`QXD-l?U
-Jz~2*rUjdP?m;3+#
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c
-new file mode 100644
-index 0000000000..ff83db095b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/early_init.c
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c
-new file mode 100644
-index 0000000000..0599f13921
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/gpio.c
-@@ -0,0 +1,194 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_GPIO,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_GPIO,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio1 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio12 = GPIO_DIR_OUTPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio12 = GPIO_LEVEL_HIGH,
-+	.gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+	.gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio13 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_GPIO,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_INPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio53 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_GPIO,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+	.gpio74 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c
-new file mode 100644
-index 0000000000..3e89a6d75f
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76df,	/* Codec Vendor / Device ID: IDT */
-+	0x1028053d,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x1028053d),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0),
-+
-+	0x80862806,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb
-new file mode 100644
-index 0000000000..85c448d010
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5530/overridetree.cb
-@@ -0,0 +1,39 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x053d inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x00000000"
-+			register "gpu_pch_backlight" = "0x03d003d0"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "usb_port_config" = "{
-+				{ 1, 1, 0 },
-+				{ 1, 1, 0 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 3 },
-+				{ 1, 0, 3 },
-+				{ 1, 2, 4 },
-+				{ 1, 1, 4 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 5 },
-+				{ 1, 0, 6 },
-+				{ 1, 1, 6 },
-+			}"
-+
-+			device ref xhci on
-+				register "superspeed_capable_ports" = "0x0000000f"
-+				register "xhci_overcurrent_mapping" = "0x00000c03"
-+				register "xhci_switchable_ports" = "0x0000000f"
-+			end
-+			device ref gbe off end
-+			device ref pcie_rp7 on end # BCM5761 Ethernet
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0010-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch

@@ -0,0 +1,22 @@
+From 318a97c284f8d5030100476a32516ddc9e51603d Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 20 Dec 2021 01:29:31 +0000
+Subject: [PATCH 10/30] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
+ default
+
+---
+ src/mainboard/lenovo/x230/cmos.default | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
+index 7314066c2b..2e315d4521 100644
+--- a/src/mainboard/lenovo/x230/cmos.default
++++ b/src/mainboard/lenovo/x230/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ usb_always_on=Disable
+ f1_to_f12_as_primary=Enable
+ me_state=Normal
++gfx_uma_size=224M
+-- 
+2.39.2
+

config/coreboot/default/patches/0010-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch

@@ -1,435 +0,0 @@
-From 200668a694f1c534a94a0bc8996416e246fe91b0 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Sun, 26 Nov 2023 17:08:52 -0700
-Subject: [PATCH 10/51] mb/dell: Add Latitude E6420 (Sandy Bridge)
-
-Mainboard is PAL50/LA-6591P (UMA). The version with an Nvidia dGPU was
-not tested. I do not physically have this system; someone with physical
-access to one sent me the output of autoport which I then modified to
-produce this port. I was also sent the VBT binary, which was obtained
-from `/sys/kernel/debug/dri/0/i915_vbt` while running version A25 of the
-vendor firmware.
-
-This was originally tested and found to be working as a standalone board
-port in Libreboot, but this variant based port in upstream coreboot has
-not been tested.
-
-This can be internally flashed by sending a command to the EC, which
-causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections [1]. The EC is the SMSC MEC5055,
-which seems to be compatible with the existing MEC5035 code.
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |  13 +-
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e6420/data.vbt  | Bin 0 -> 6144 bytes
- .../variants/e6420/early_init.c               |  14 ++
- .../snb_ivb_latitude/variants/e6420/gpio.c    | 191 ++++++++++++++++++
- .../variants/e6420/hda_verb.c                 |  32 +++
- .../variants/e6420/overridetree.cb            |  35 ++++
- 7 files changed, 287 insertions(+), 1 deletion(-)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index 183a67bec3..d2786970ee 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -17,6 +17,12 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select SYSTEM_TYPE_LAPTOP
- 	select USE_NATIVE_RAMINIT
- 
-+config BOARD_DELL_LATITUDE_E6420
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_10240
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+
- config BOARD_DELL_LATITUDE_E5530
- 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select BOARD_ROMSIZE_KB_12288
-@@ -43,6 +49,7 @@ config MAINBOARD_DIR
- 	default "dell/snb_ivb_latitude"
- 
- config MAINBOARD_PART_NUMBER
-+	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
- 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
- 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
- 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
-@@ -54,11 +61,15 @@ config USBDEBUG_HCD_INDEX
- 	default 2
- 
- config VARIANT_DIR
-+	default "e6420" if BOARD_DELL_LATITUDE_E6420
- 	default "e5530" if BOARD_DELL_LATITUDE_E5530
- 	default "e6430" if BOARD_DELL_LATITUDE_E6430
- 	default "e6530" if BOARD_DELL_LATITUDE_E6530
- 
- config VGA_BIOS_ID
--	default "8086,0166"
-+	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
-+	default "8086,0126" if BOARD_DELL_LATITUDE_E6420
-+	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
-+		|| BOARD_DELL_LATITUDE_E6530
- 
- endif
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index c15ef4028f..257d428a70 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -1,5 +1,8 @@
- ## SPDX-License-Identifier: GPL-2.0-only
- 
-+config BOARD_DELL_LATITUDE_E6420
-+	bool "Latitude E6420"
-+
- config BOARD_DELL_LATITUDE_E5530
- 	bool "Latitude E5530"
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd
-GIT binary patch
-literal 6144
-zcmeHKeQZ-z6hE);wSBvNZ|mO1=*HLC2BQN8uVX6{N9eY)75ORymb$R8!YYuAZEgeE
-zKk|S@Fen*n41W-viAF;r%)~^EkpLz-B{2q##)LmGAtoY;7*Qhv_1yPbw$TC$2}G0K
-z=6Ao&x#ym9?z!i_&TOh(kLzky2cN8MTpny#R<;VU4Rkn?rBIz(YL~BBw<%b&zGhSH
-z$~AQ>@D0d=Xx6RE0BwSxspWdrW9y<FZGD@&x3_JL;p$p!;!BVdcKLkht0=-%(Jj&T
-z_GkyztZ%>#t7^)^(T-R<7W?O6ZTI%A+j=`<Jw3Q%dk6N!da<_?7oyiU3)^<~_TiSk
-zE$y+=RK3PGQ`gzmXYPRBx>C|f*UP9{h|4>ANrAe~?ymV*)83AaT#FuTjP=C2cg5P~
-zt4w78r$t#300cWY_k)mevmAmFI3&oBfytoAAPQiYK$XEIgHwV@5-gJ-Q-*p8yfTDj
-zaDz=1Y!X1B3`OpQ&Ik}bM|0xHn0gYNZw0rT=7AXS2in-q8K^?)0|el+Z6geW7i7MM
-zv~!|>HqL-|Fk}EYOa@)R<X)VQ7c}d8R1b@RTn5rq(90|QRg0?wwZZz(6Dz}w>zg9Y
-z8;!mD_V*XSjT33~$`o`s>zEGBq8AQ`HaH?y!Fh2QiX1v@aCo4LaENf&DZ_cE2A2qb
-z5@cC}X)=S^1RvpXLWs~v*hqMau$!=t@B-mg!XV)|;eEm>!Z6`H;R4|&!d1d`f|S7^
-zli+B98*!TfPE&6~NVM5j3v{N3OTjpnm_L@BPh(}esd(J!gj?~iJP?n|OZZOiTqlql
-zg<NWR@g&-*W-E%A7|*1Z_`sVO$K&iAP+VIj9{<1hT%SXsK}IBk8!daftR`6-)EUiS
-zvv*HR(#-ZwhA~7wcmxbe4%E?Y7P0y{1q|nqR1L29UR8v@#No^g5MH)7!>{%-$T|cR
-zZx5|xm>Fl>;@$m};P{0WC>O~<Nl1`*PLgPN_hP2a^h+L$ls&SYrkDYr+&l*%%S?^Q
-ziPSdtHE<LNEnr7cs=ihL-C>-p>*$9CpHRLgN|POkqD^UP4nw|4nf0bc8MOBk<;%js
-zfpCAWNzqSPlz@X%j9CGrwZDKUl@K{g6pzqiIIARDQ)#@^RW&0pmNG;XZ?!SlHB?L#
-zKRAMgq(R;aQd%@Gy38-LS@ix)fR**(P3B9wI=Uk^&cWmmwB<vf21<0#LBA!;qtAh(
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-zQP07nf#&kPkPp}Cmk$F1g7q7QK;kz~80i&oDN}~wYbPUI6AtG5H+$T!@f5FzUhp21
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-zvAr&Q+ogTvVxPM3XP5Smi`f;Nt7uCU)}Y`HMcbpW=M_AuXlE35PQl+4O{7m66&I@7
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-zT6@-PdW^oyFb44AG`HMZWEnP{&OQ+jC`N4emoS)x;EPN}uaSFOf-Mn8JRRO&LTWJc
-zn6%=L94~PR)%Ua_HTZcfTXD<p{%8p|<N<;Efw$Zb4$}{m8@7c((~<7^thaau&@Wx#
-zVGNL)lmH@{o=h*{muXGc!;nXrVgpp3;1V1stMj=4AtxyzX+?SoB~zN}!*r?9Qvs1P
-zmV_(CTmt0sY&6=F=_M>E34GYvuh1uQF+BUdWyQC5SaEM1QvKlHBMs13C}n{0SwRxW
-ziekMa&kvRFruRcKCevGy5)TxUBDlur@E{TtQ^NQ>nO+Cgl)&Ga(PxqVW?e3TLH-UY
-zdL3T{z^xdd`$(STFUb8R*cKa}r>n{Wk+MXRH~o-hN}#9OF*>T#>rfhiRs(Wc-R^9@
-z%F=<}dn(E}ADc03zJ>JvZe;_8f+WFLL4%qNYs`_aa`a$Pl5H;iO^Wt*cP3W(d=(g}
-zZ%nKT1$|r-tAv8($u2-BI2Uiz#%OT&!Q3b~Ru2P2j;Gem!@wfPsTR%J>W{8z)oq^J
-k^Qm&?O@bFkw4CTocwoW<6CRlGz=Q`TJTT#bN9KWl0rH4|j{pDw
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
-new file mode 100644
-index 0000000000..ff83db095b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/early_init.c
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
-new file mode 100644
-index 0000000000..943c743f48
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/gpio.c
-@@ -0,0 +1,191 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_NATIVE,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_NATIVE,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+	.gpio31 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
-new file mode 100644
-index 0000000000..ede8445aaf
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x10280493,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x10280493),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
-new file mode 100644
-index 0000000000..3012a3177f
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6420/overridetree.cb
-@@ -0,0 +1,35 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x0493 inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x0000054f"
-+			register "gpu_pch_backlight" = "0x13121312"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "usb_port_config" = "{
-+				{ 1, 1, 0 },
-+				{ 1, 1, 0 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 1 },
-+				{ 1, 0, 2 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 7 },
-+				{ 1, 1, 6 },
-+				{ 1, 0, 6 },
-+				{ 1, 0, 7 },
-+			}"
-+
-+			device ref sata1 on
-+				register "sata_port_map" = "0x3b"
-+			end
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0011-lenovo-x230-set-me_state-Disabled-in-cmos.default.patch

@@ -1,7 +1,7 @@
-From 0298639b6e80c8950fbb4484180b7195883ab8c1 Mon Sep 17 00:00:00 2001
+From 47afbe8b94edd1ff58c1daf0bda020e6afac35f4 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Mon, 3 Jan 2022 19:06:22 +0000
-Subject: [PATCH 03/51] lenovo/x230: set me_state=Disabled in cmos.default
+Subject: [PATCH 11/30] lenovo/x230: set me_state=Disabled in cmos.default
 
 I only recently found out about this. It's possible to use me_cleaner to
 do the same thing, but some people might just flash coreboot and not do
@@ -23,15 +23,16 @@ Date:   Thu Nov 21 21:47:31 2019 +0300
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
-index 732e214b32..8454f0eac0 100644
+index 2e315d4521..3585cbd58b 100644
 --- a/src/mainboard/lenovo/x230/cmos.default
 +++ b/src/mainboard/lenovo/x230/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,5 +15,5 @@ trackpoint=Enable
  backlight=Both
  usb_always_on=Disable
  f1_to_f12_as_primary=Enable
 -me_state=Normal
 +me_state=Disabled
+ gfx_uma_size=224M
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0011-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch

@@ -1,449 +0,0 @@
-From 53abe363f2fa038080a976f2d3a2c63ee8da9022 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Wed, 31 Jan 2024 22:07:25 -0700
-Subject: [PATCH 11/51] mb/dell: Add Latitude E6520 (Sandy Bridge)
-
-Mainboard is PAL60/LA-6562P (UMA). The version with an Nvidia dGPU was
-not tested. I do not physically have this system; someone with physical
-access to one sent me the output of autoport which I then modified to
-produce this port. I was also sent the VBT binary, which was obtained
-from `/sys/kernel/debug/dri/0/i915_vbt` while running version A08 of the
-vendor firmware.
-
-This was originally tested and found to be working as a standalone board
-port in Libreboot, but this variant based port in upstream coreboot has
-not been tested.
-
-This can be internally flashed by sending a command to the EC, which
-causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections [1]. The EC is the SMSC MEC5055,
-which seems to be compatible with the existing MEC5035 code.
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |   9 +
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e6520/data.vbt  | Bin 0 -> 6144 bytes
- .../variants/e6520/early_init.c               |  31 +++
- .../snb_ivb_latitude/variants/e6520/gpio.c    | 190 ++++++++++++++++++
- .../variants/e6520/hda_verb.c                 |  32 +++
- .../variants/e6520/overridetree.cb            |  35 ++++
- 7 files changed, 300 insertions(+)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index d2786970ee..72bdc96c0a 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -23,6 +23,12 @@ config BOARD_DELL_LATITUDE_E6420
- 	select MAINBOARD_USES_IFD_GBE_REGION
- 	select SOUTHBRIDGE_INTEL_BD82X6X
- 
-+config BOARD_DELL_LATITUDE_E6520
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_10240
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+
- config BOARD_DELL_LATITUDE_E5530
- 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select BOARD_ROMSIZE_KB_12288
-@@ -50,6 +56,7 @@ config MAINBOARD_DIR
- 
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
-+	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
- 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
- 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
- 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
-@@ -62,11 +69,13 @@ config USBDEBUG_HCD_INDEX
- 
- config VARIANT_DIR
- 	default "e6420" if BOARD_DELL_LATITUDE_E6420
-+	default "e6520" if BOARD_DELL_LATITUDE_E6520
- 	default "e5530" if BOARD_DELL_LATITUDE_E5530
- 	default "e6430" if BOARD_DELL_LATITUDE_E6430
- 	default "e6530" if BOARD_DELL_LATITUDE_E6530
- 
- config VGA_BIOS_ID
-+	default "8086,0116" if BOARD_DELL_LATITUDE_E6520
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
- 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index 257d428a70..c7665ac263 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -3,6 +3,9 @@
- config BOARD_DELL_LATITUDE_E6420
- 	bool "Latitude E6420"
- 
-+config BOARD_DELL_LATITUDE_E6520
-+	bool "Latitude E6520"
-+
- config BOARD_DELL_LATITUDE_E5530
- 	bool "Latitude E5530"
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
-GIT binary patch
-literal 6144
-zcmeHKZ){Ul6hE);wSB#PZ|mL$bQ^!}HW(eF@H)0JafGfbqsZ9G21{L7Sg{or$5uN)
-z_QgG55e!O(8p8*oBhhF`l$n^QF%rN;rzFNqqcPzFCd5QSB1Y7RKt1=pmTk1aFo9^Y
-z+x+gi_nvdlJ@?#m&wZWW=G#bH>ze$J`&!oe*Q|E0r!)d89LYY8b$aowZEoG-uiIF+
-z#n;$ezm6V<nGnvtc?lrGaf)1_);!W0?uqnojdw-1MQM|dwy`OcF?M@A)KgVV*N2}7
-zcXx+--0R}IwzW3-+`f2k?^Av5V7MpRO-q(9rn_R1@Xlz2Ztdy`$Gf6^w6~|bKi!!7
-z9;xq*^~bxmZQn^<^<`+2s=BdSM%VW2#FguN<FO^QuDhGIFquBu677q|cSj>jWFixQ
-z)4V8f0Gt`D`+>9Fr~tnJ76EJ`5D_F1cn-`0$RgN9unI6kfYkzIiO?W`ON4+34lv1_
-zNdPDkq1cf$p8^EW;TS*O$CdzNo#1fbIG_Oi0T(ti0jwyt0le_p_HlvX^CFvr)>$b>
-zO-z8^CSU`w=mIK7Q)@9fR;XUzrFu{T=rRyygIZBpU9+Or>+?4R9%~G?Y-|g)Z`Sti
-z+do(U*Wb-xR~DzjS<75#=Us4sH^C9U2FCbND7L7u$>M|<;t=AnRfI9C0v8c~AVg7t
-zIU<3D2oK^>L;%r(*o=4*u?Mja@dDyi#4zFn;(f#^#3*76aUSs#;tJv#La-6YLRdQB
-zdcvfERkvH?k~GJlfM<HR476j(@nfm+47<!Ult@^ua5M3h6A}q=C0ognX9aX4mxq)U
-zXOhm=DbLene?C%_16Q)2NRV@Yacz`D;{V>Ve-1?&ZXy}n)YwnVAgNlz#zX;=IX)-F
-z)9LL3lbEdY5Co)LsK?vP)7s}G(5xduE!Y!#Wgh<IN3(3ey=-oWU(9aEJ_HzV53Jbq
-zj5B5RjzLUt>_T&xi$uUA#0e}X3D~`J(bHz;DgTa@GrpW6=>eZwJeNYYo*GjF=``;(
-zuoQ3|V5YoKd$j=KK{`uSX*DeU1oJg=+RT6)rLe6%2>Ci^!5ao=*gS}wFN=nUf`fTF
-zM?Gb5ycWjM7I?MJ!2;w|LFg=UoLq-ytr2iemG)AsW}bI4X9PK}T5UKsQi7anu=tD6
-zf|={kXkNeQBD>6bQ3taC8XJOJ^e40_ydyfr&a41L^1)jNrK<B_wV}+ZE`p;QK=rDz
-zTw`SJ+e`Oc*icaF4INF51Xg*~ts@m)@9ETt(*@N7yy0)Ddce%i9{^k2kbd8=Wns~P
-zWBD$~himxDharxF@f!ti^0$~9Zxt{tg`@Dbl_0Ki2Xp_MEw-<z6qgep;XYmR%Dl-F
-z%3cBfcN;Avikpz-gmw_6mymu!Unk0YgnUfsk3{*6kQ;=S*p(_fS!JhDyYh^k?6uRk
-z?8--W@~NHvY*+ra6SG9iC1s^V)<|@Rqzp*pd5NBslrs`JC(&Oeg~v}CnJ$x+)iP<8
-z=`LA0Ad@39{XkZ}kjXbP{YzHtS!70*yy%LcnJ#cz4u%*Wq!^d*AVMZdr&l=#Qgik~
-ze2l)cX+!kF9EaFhY;0^Uo_#VNC?7K2Tf=ZR1y5);b!mCGG?<cc#M0rtHKYeKi%BE?
-z@Y6|P8fx#li}c`Uv24UGyZaM0To;Ep<_AWZA1t~bFgI)uf}&Eq=L_Cs89=>wnT0Vx
-z-jp>o1ffJNommZ4?=TIPlePIw0hgQ706f*tBC`#pg>9&zRHe>J2%RxBTrOc6Adh9E
-ziJr`?VQH!N!_GkoKaoq|+3$^Ae0#sUxXlmM1Huq~g<=Ls?ILv+nQcH%PQedGOlH=Q
-z77rMcJlH4Mkc#U2(IDv>rsm1aHpsdL_RdT^i_ACcQUMIJcSus}*(?CIiy^#^=t=g1
-z+*^Zbh30&^#_bKclSy9pL$<B~pK8m*sLpIdnHM@W$nA7Ea@Z`x27K?aNK<@lCW(2L
-zb@kB3H8kKy4W3Hu)NN|kd!DL^o#iR9a{QYV-Wl&r&hmIFX{ezkIV<4zFiVUQ@K>ao
-z00DnFy~Uek!JRwhVX!of0)$Sa*X^S~LMQH0<E(UUx}L=|;Kgw(r(4q=nD)T52c|tR
-O?SW|zOncy=dEg(6JAK&z
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
-new file mode 100644
-index 0000000000..b6415a428b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/early_init.c
-@@ -0,0 +1,31 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+	{ 1, 1, 0 },
-+	{ 1, 1, 0 },
-+	{ 1, 1, 1 },
-+	{ 1, 1, 1 },
-+	{ 1, 0, 2 },
-+	{ 1, 1, 2 },
-+	{ 1, 0, 3 },
-+	{ 1, 0, 3 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 5 },
-+	{ 1, 1, 7 },
-+	{ 1, 1, 6 },
-+	{ 1, 0, 6 },
-+	{ 1, 0, 7 },
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
-new file mode 100644
-index 0000000000..61f01816c4
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/gpio.c
-@@ -0,0 +1,190 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_NATIVE,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_NATIVE,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
-new file mode 100644
-index 0000000000..ae376691e7
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x10280494,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x10280494),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
-new file mode 100644
-index 0000000000..f90f2dee1f
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6520/overridetree.cb
-@@ -0,0 +1,35 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x0494 inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x00001312"
-+			register "gpu_pch_backlight" = "0x13121312"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "usb_port_config" = "{
-+				{ 1, 1, 0 },
-+				{ 1, 1, 0 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 1 },
-+				{ 1, 0, 2 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 7 },
-+				{ 1, 1, 6 },
-+				{ 1, 0, 6 },
-+				{ 1, 0, 7 },
-+			}"
-+
-+			device ref sata1 on
-+				register "sata_port_map" = "0x3b"
-+			end
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0012-mb-dell-Add-Latitude-E5520-Sandy-Bridge.patch

@@ -1,442 +0,0 @@
-From 3f8eade6150f582129332f6347e9a685f8a7b500 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Wed, 7 Feb 2024 10:23:38 -0700
-Subject: [PATCH 12/51] mb/dell: Add Latitude E5520 (Sandy Bridge)
-
-Mainboard is Krug 15". I do not physically have this system; someone
-with physical access to one sent me the output of autoport which I then
-modified to produce this port. I was also sent the VBT binary, which was
-obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
-A14 of the vendor firmware.
-
-This was originally tested and found to be working as a standalone
-board port in Libreboot, but this variant based port in upstream
-coreboot has not been tested.
-
-This can be internally flashed by sending a command to the EC, which
-causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections [1]. The EC is the SMSC MEC5055,
-which seems to be compatible with the existing MEC5035 code.
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: Ic9bfc028d4b8ae01ccc019157bb53e7764671134
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |  10 +-
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e5520/data.vbt  | Bin 0 -> 6144 bytes
- .../variants/e5520/early_init.c               |  14 ++
- .../snb_ivb_latitude/variants/e5520/gpio.c    | 195 ++++++++++++++++++
- .../variants/e5520/hda_verb.c                 |  32 +++
- .../variants/e5520/overridetree.cb            |  39 ++++
- 7 files changed, 292 insertions(+), 1 deletion(-)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index 72bdc96c0a..4e94a7ef80 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select SYSTEM_TYPE_LAPTOP
- 	select USE_NATIVE_RAMINIT
- 
-+config BOARD_DELL_LATITUDE_E5520
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_6144
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+
- config BOARD_DELL_LATITUDE_E6420
- 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select BOARD_ROMSIZE_KB_10240
-@@ -55,6 +60,7 @@ config MAINBOARD_DIR
- 	default "dell/snb_ivb_latitude"
- 
- config MAINBOARD_PART_NUMBER
-+	default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
- 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
- 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
- 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
-@@ -68,6 +74,7 @@ config USBDEBUG_HCD_INDEX
- 	default 2
- 
- config VARIANT_DIR
-+	default "e5520" if BOARD_DELL_LATITUDE_E5520
- 	default "e6420" if BOARD_DELL_LATITUDE_E6420
- 	default "e6520" if BOARD_DELL_LATITUDE_E6520
- 	default "e5530" if BOARD_DELL_LATITUDE_E5530
-@@ -77,7 +84,8 @@ config VARIANT_DIR
- config VGA_BIOS_ID
- 	default "8086,0116" if BOARD_DELL_LATITUDE_E6520
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
--	default "8086,0126" if BOARD_DELL_LATITUDE_E6420
-+	default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
-+		|| BOARD_DELL_LATITUDE_E5520
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
- 		|| BOARD_DELL_LATITUDE_E6530
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index c7665ac263..7976691f21 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -1,5 +1,8 @@
- ## SPDX-License-Identifier: GPL-2.0-only
- 
-+config BOARD_DELL_LATITUDE_E5520
-+	bool "Latitude E5520"
-+
- config BOARD_DELL_LATITUDE_E6420
- 	bool "Latitude E6420"
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729
-GIT binary patch
-literal 6144
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-zf6^N2f>5HCPWM3N+f0MyWOV^kz~!-wVc4MRXOY>4Jsxd1RyBKEMzNf{RKhesKFdbq
-zJ(*d<l2Y#n?E?~iBA39P?~Pr2d#}5=#Sfl-VGzGUF$4U2KcqCIVlwkC(&7PQk_X!a
-z8}3Jgq-&U*Co|h1>l)ZQGyW_x->i#;FvQ*=Nv&nG0N5@D@jjv_Q}K}6MP?1A6`JGe
-zDwj9pN+x;T4>`I9e5x(uqdK#OGB31ikk@Xv=dxLb4fx(;ktX@rOb~M~?dYQQYiPia
-z8r;jUQ?sd2@3||-cb2Eb%JFYfxHsONoaJ^eqoKN{<g9?-%`7oWz+aJS0tEc!^d@hD
-z1-I{%hr!Y?0uVZpUbl__37xn@jkD6Z>3SATgBQlEoN7&ZV9Eni9+>jLln16fFy(=V
-H=7E0zE^L4Z
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c
-new file mode 100644
-index 0000000000..ff83db095b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/early_init.c
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c
-new file mode 100644
-index 0000000000..f76b93d9f0
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/gpio.c
-@@ -0,0 +1,195 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_NATIVE,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_GPIO,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_NATIVE,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio12 = GPIO_DIR_OUTPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio12 = GPIO_LEVEL_HIGH,
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_GPIO,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_NATIVE,
-+	.gpio50 = GPIO_MODE_GPIO,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_GPIO,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_GPIO,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_OUTPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio46 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio50 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_OUTPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio53 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio55 = GPIO_DIR_OUTPUT,
-+	.gpio56 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_LOW,
-+	.gpio37 = GPIO_LEVEL_LOW,
-+	.gpio46 = GPIO_LEVEL_HIGH,
-+	.gpio50 = GPIO_LEVEL_HIGH,
-+	.gpio51 = GPIO_LEVEL_LOW,
-+	.gpio55 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_NATIVE,
-+	.gpio69 = GPIO_MODE_NATIVE,
-+	.gpio70 = GPIO_MODE_NATIVE,
-+	.gpio71 = GPIO_MODE_NATIVE,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_GPIO,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio74 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c
-new file mode 100644
-index 0000000000..1373975352
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x1028049a,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x1028049a),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb
-new file mode 100644
-index 0000000000..479d1b696e
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5520/overridetree.cb
-@@ -0,0 +1,39 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x049a inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x00000218"
-+			register "gpu_pch_backlight" = "0x13121312"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
-+			register "usb_port_config" = "{
-+				{ 1, 1, 0 },
-+				{ 1, 1, 0 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 7 },
-+				{ 1, 1, 6 },
-+				{ 1, 1, 6 },
-+				{ 1, 1, 7 },
-+			}"
-+
-+			device ref gbe off end
-+			device ref pcie_rp4 off end
-+			device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet
-+			device ref sata1 on
-+				register "sata_port_map" = "0x3b"
-+			end
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0012-set-me_state-Disabled-on-all-cmos.default-files.patch

@@ -1,7 +1,7 @@
-From c697c90ace86edfe724c86bd6a680cf0ae0e4b58 Mon Sep 17 00:00:00 2001
+From 531ef34ece796f38cb8a13a54856e46e79842e29 Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Wed, 2 Mar 2022 21:50:01 +0000
-Subject: [PATCH 04/51] set me_state=Disabled on all cmos.default files!
+Subject: [PATCH 12/30] set me_state=Disabled on all cmos.default files!
 
 yeah. why the hell isn't this the default
 
@@ -20,105 +20,103 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
  10 files changed, 10 insertions(+), 10 deletions(-)
 
 diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
-index be08e0a342..b8970efa46 100644
+index 681c40e78b..57cdcf9162 100644
 --- a/src/mainboard/lenovo/l520/cmos.default
 +++ b/src/mainboard/lenovo/l520/cmos.default
-@@ -16,4 +16,4 @@ sticky_fn=Disable
+@@ -14,4 +14,4 @@ sticky_fn=Disable
  trackpoint=Enable
  backlight=Both
  usb_always_on=Disable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
-index 6fd26c5fe3..27a62d07b3 100644
+index 8244071b8a..c011867916 100644
 --- a/src/mainboard/lenovo/t420/cmos.default
 +++ b/src/mainboard/lenovo/t420/cmos.default
-@@ -16,4 +16,4 @@ sticky_fn=Disable
+@@ -14,4 +14,4 @@ sticky_fn=Disable
  trackpoint=Enable
  hybrid_graphics_mode=Integrated Only
  usb_always_on=Disable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
-index 6fd26c5fe3..27a62d07b3 100644
+index 8244071b8a..c011867916 100644
 --- a/src/mainboard/lenovo/t420s/cmos.default
 +++ b/src/mainboard/lenovo/t420s/cmos.default
-@@ -16,4 +16,4 @@ sticky_fn=Disable
+@@ -14,4 +14,4 @@ sticky_fn=Disable
  trackpoint=Enable
  hybrid_graphics_mode=Integrated Only
  usb_always_on=Disable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
-index c896eadec1..6d1e172056 100644
+index 26795fe5cf..55e1e6c04e 100644
 --- a/src/mainboard/lenovo/t430/cmos.default
 +++ b/src/mainboard/lenovo/t430/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,4 +15,4 @@ trackpoint=Enable
  backlight=Both
  usb_always_on=Disable
  hybrid_graphics_mode=Integrated Only
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
-index 286fb0ae8c..5a05c73721 100644
+index 52dbf70377..b16800ca9e 100644
 --- a/src/mainboard/lenovo/t430s/cmos.default
 +++ b/src/mainboard/lenovo/t430s/cmos.default
-@@ -18,4 +18,4 @@ backlight=Both
+@@ -16,4 +16,4 @@ backlight=Both
  enable_dual_graphics=Disable
  usb_always_on=Disable
  f1_to_f12_as_primary=Enable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
-index 4857f92f67..ab1be1a678 100644
+index cf79b391e2..b66f7034dc 100644
 --- a/src/mainboard/lenovo/t520/cmos.default
 +++ b/src/mainboard/lenovo/t520/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,4 +15,4 @@ trackpoint=Enable
  backlight=Both
  hybrid_graphics_mode=Integrated Only
  usb_always_on=Disable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
-index 4857f92f67..ab1be1a678 100644
+index cf79b391e2..b66f7034dc 100644
 --- a/src/mainboard/lenovo/t530/cmos.default
 +++ b/src/mainboard/lenovo/t530/cmos.default
-@@ -17,4 +17,4 @@ trackpoint=Enable
+@@ -15,4 +15,4 @@ trackpoint=Enable
  backlight=Both
  hybrid_graphics_mode=Integrated Only
  usb_always_on=Disable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
-index ef706c1303..b318ab9772 100644
+index 6d1d57a795..52f303dfdb 100644
 --- a/src/mainboard/lenovo/x220/cmos.default
 +++ b/src/mainboard/lenovo/x220/cmos.default
-@@ -15,4 +15,4 @@ usb_always_on=Disable
+@@ -13,4 +13,4 @@ usb_always_on=Disable
  fn_ctrl_swap=Disable
  sticky_fn=Disable
  trackpoint=Enable
 -me_state=Normal
 +me_state=Disabled
 diff --git a/src/mainboard/protectli/vault_cml/cmos.default b/src/mainboard/protectli/vault_cml/cmos.default
-index d61046df6b..8c793fd1c3 100644
+index 62715bc6ba..129b5fd121 100644
 --- a/src/mainboard/protectli/vault_cml/cmos.default
 +++ b/src/mainboard/protectli/vault_cml/cmos.default
-@@ -2,4 +2,4 @@
+@@ -1,3 +1,3 @@
- 
  boot_option=Fallback
  debug_level=Debug
 -me_state=Enable
 +me_state=Disabled
 diff --git a/src/mainboard/system76/tgl-u/cmos.default b/src/mainboard/system76/tgl-u/cmos.default
-index d61046df6b..8c793fd1c3 100644
+index 62715bc6ba..129b5fd121 100644
 --- a/src/mainboard/system76/tgl-u/cmos.default
 +++ b/src/mainboard/system76/tgl-u/cmos.default
-@@ -2,4 +2,4 @@
+@@ -1,3 +1,3 @@
- 
  boot_option=Fallback
  debug_level=Debug
 -me_state=Enable
 +me_state=Disabled
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0013-lenovo-x230-introduce-FHD-variant.patch

@@ -0,0 +1,198 @@
+From 7b9003f98c7c685b2fe56781f3b0916018037b72 Mon Sep 17 00:00:00 2001
+From: Alexander Couzens <lynxis@fe80.eu>
+Date: Sat, 19 Mar 2022 13:42:33 +0000
+Subject: [PATCH 13/30] lenovo/x230: introduce FHD variant
+
+There is a modification for the x230 which uses the 2nd DP from the dock
+as the integrated panel's connection, which allows using a custom eDP
+panel instead of the stock LVDS display.
+
+There are several adapter boards present on the market and all of them
+uses the same method of enabling the custom eDP panel.
+
+To make this work with coreboot, the internal LVDS connector should be
+disabled in libgfxinit. The VBT has been modified as well, which allows
+brightness controls to work out of the box.
+
+The modifications done to the VBT are:
+- Remove the LVDS port entry.
+- Move the DP-3 (which is the 2nd DP on the dock) entry to the first
+  position on the list.
+- Set the DP-3 as internally connected.
+
+This has been reported to work with the following panels:
+- LP125WF2-SPB4 (1920*1080, 12.5")
+- LQ125T1JW02 (2560*1440, 12.5")
+- LQ133M1JW21 (1920*1080, 13.3")
+- LTN133HL10-201 (1920*1080, 13.3")
+- B133HAN04.6 (1920*1080, 13.3")
+- B133QAN02.0 (2560*1600, 13.3")
+
+Other eDP panels not on this list should work as well.
+
+Change-Id: I0355d39a61956792e69bccd5274cfc2749d72bf0
+Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
+Signed-off-by: Felix Singer <felixsinger@posteo.net>
+---
+ src/mainboard/lenovo/x230/Kconfig             |  15 ++++++++-----
+ src/mainboard/lenovo/x230/Kconfig.name        |   3 +++
+ src/mainboard/lenovo/x230/Makefile.mk         |   5 +++++
+ .../lenovo/x230/variants/x230_edp/data.vbt    | Bin 0 -> 4281 bytes
+ .../x230/variants/x230_edp/gma-mainboard.ads  |  21 ++++++++++++++++++
+ 5 files changed, 38 insertions(+), 6 deletions(-)
+ create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
+ create mode 100644 src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
+
+diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
+index 279095629b..acfd0ed561 100644
+--- a/src/mainboard/lenovo/x230/Kconfig
++++ b/src/mainboard/lenovo/x230/Kconfig
+@@ -1,4 +1,4 @@
+-if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S
++if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
+ 
+ config BOARD_SPECIFIC_OPTIONS
+ 	def_bool y
+@@ -11,7 +11,7 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select H8_HAS_BAT_THRESHOLDS_IMPL
+ 	select H8_HAS_PRIMARY_FN_KEYS if BOARD_LENOVO_X230S
+ 	select NO_UART_ON_SUPERIO
+-	select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
++	select BOARD_ROMSIZE_KB_12288 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
+ 	select BOARD_ROMSIZE_KB_16384 if BOARD_LENOVO_X230S
+ 	select HAVE_ACPI_TABLES
+ 	select HAVE_OPTION_TABLE
+@@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select INTEL_INT15
+ 	select DRIVERS_RICOH_RCE822
+ 	select MEMORY_MAPPED_TPM
+-	select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
++	select MAINBOARD_HAS_TPM1 if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
+ 	select MAINBOARD_HAS_LIBGFXINIT
+ 	select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
+ 	select INTEL_GMA_HAVE_VBT
+@@ -47,17 +47,20 @@ config MAINBOARD_DIR
+ 	default "lenovo/x230"
+ 
+ config VARIANT_DIR
+-	default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T
++	default "x230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230T || BOARD_LENOVO_X230_EDP
+ 	default "x230s" if BOARD_LENOVO_X230S
+ 
+ config MAINBOARD_PART_NUMBER
+-	default "ThinkPad X230" if BOARD_LENOVO_X230
++	default "ThinkPad X230" if BOARD_LENOVO_X230 || BOARD_LENOVO_X230_EDP
+ 	default "ThinkPad X230t" if BOARD_LENOVO_X230T
+ 	default "ThinkPad X230s" if BOARD_LENOVO_X230S
+ 
+ config OVERRIDE_DEVICETREE
+ 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+ 
++config INTEL_GMA_VBT_FILE
++	default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
++
+ config USBDEBUG_HCD_INDEX
+ 	int
+ 	default 2
+@@ -79,4 +82,4 @@ config PS2M_EISAID
+ config THINKPADEC_HKEY_EISAID
+ 	default "LEN0068"
+ 
+-endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ||  BOARD_LENOVO_X230S
++endif # BOARD_LENOVO_X230 || BOARD_LENOVO_X230T ||  BOARD_LENOVO_X230S || BOARD_LENOVO_X230_EDP
+diff --git a/src/mainboard/lenovo/x230/Kconfig.name b/src/mainboard/lenovo/x230/Kconfig.name
+index 1a01436879..e7290a12dd 100644
+--- a/src/mainboard/lenovo/x230/Kconfig.name
++++ b/src/mainboard/lenovo/x230/Kconfig.name
+@@ -6,3 +6,6 @@ config BOARD_LENOVO_X230T
+ 
+ config BOARD_LENOVO_X230S
+ 	bool "ThinkPad X230s"
++
++config BOARD_LENOVO_X230_EDP
++	bool "ThinkPad X230 eDP Mod (2K/FHD)"
+diff --git a/src/mainboard/lenovo/x230/Makefile.mk b/src/mainboard/lenovo/x230/Makefile.mk
+index 8e801f145d..6e6f9f90b9 100644
+--- a/src/mainboard/lenovo/x230/Makefile.mk
++++ b/src/mainboard/lenovo/x230/Makefile.mk
+@@ -5,4 +5,9 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
+ romstage-y += variants/$(VARIANT_DIR)/early_init.c
+ romstage-y += variants/$(VARIANT_DIR)/gpio.c
+ ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
++
++ifeq ($(CONFIG_BOARD_LENOVO_X230_EDP),y)
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x230_edp/gma-mainboard.ads
++else
+ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
++endif
+diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt b/src/mainboard/lenovo/x230/variants/x230_edp/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
+GIT binary patch
+literal 4281
+zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^
+zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
+zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
+zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
+zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
+zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
+z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
+zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
+z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
+z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
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+zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
+z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}(
+z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg
+zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW>
+zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn
+zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L
+zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy;
+z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY
+zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
+zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
+zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
+z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
+zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
+zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
+zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
+z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
+zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
+zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH
+z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
+zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
+p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
+new file mode 100644
+index 0000000000..f7cf0bc264
+--- /dev/null
++++ b/src/mainboard/lenovo/x230/variants/x230_edp/gma-mainboard.ads
+@@ -0,0 +1,21 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (DP1,
++      DP2,
++      DP3,
++      HDMI1,
++      HDMI2,
++      HDMI3,
++      Analog,
++      others => Disabled);
++
++end GMA.Mainboard;
+-- 
+2.39.2
+

config/coreboot/default/patches/0013-mb-dell-Add-Latitude-E5420-Sandy-Bridge.patch

@@ -1,442 +0,0 @@
-From bbcd6a7f09ee99f3b26b0931f1dcd70970242ee8 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Mon, 4 Mar 2024 18:05:43 -0700
-Subject: [PATCH 13/51] mb/dell: Add Latitude E5420 (Sandy Bridge)
-
-Mainboard is Krug 14". I do not physically have this system; someone
-with physical access to one sent me the output of autoport which I then
-modified to produce this port. I was also sent the VBT binary, which was
-obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running version
-A02 of the vendor firmware.
-
-This was originally tested and found to be working as a standalone board
-port in Libreboot, but this variant based port in upstream coreboot has
-not been tested.
-
-This can be internally flashed by sending a command to the EC, which
-causes the EC to pull the FDO pin low and the firmware to skip setting
-up any chipset based write protections [1]. The EC is the SMSC MEC5055,
-which seems to be compatible with the existing MEC5035 code.
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: I0283653156083768e1fd451bcf539b4e028589f4
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |  10 +-
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e5420/data.vbt  | Bin 0 -> 6144 bytes
- .../variants/e5420/early_init.c               |  14 ++
- .../snb_ivb_latitude/variants/e5420/gpio.c    | 195 ++++++++++++++++++
- .../variants/e5420/hda_verb.c                 |  32 +++
- .../variants/e5420/overridetree.cb            |  39 ++++
- 7 files changed, 292 insertions(+), 1 deletion(-)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index 4e94a7ef80..e6a21ffb99 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -17,6 +17,11 @@ config BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select SYSTEM_TYPE_LAPTOP
- 	select USE_NATIVE_RAMINIT
- 
-+config BOARD_DELL_LATITUDE_E5420
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_6144
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+
- config BOARD_DELL_LATITUDE_E5520
- 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select BOARD_ROMSIZE_KB_6144
-@@ -60,6 +65,7 @@ config MAINBOARD_DIR
- 	default "dell/snb_ivb_latitude"
- 
- config MAINBOARD_PART_NUMBER
-+	default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
- 	default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
- 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
- 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
-@@ -74,6 +80,7 @@ config USBDEBUG_HCD_INDEX
- 	default 2
- 
- config VARIANT_DIR
-+	default "e5420" if BOARD_DELL_LATITUDE_E5420
- 	default "e5520" if BOARD_DELL_LATITUDE_E5520
- 	default "e6420" if BOARD_DELL_LATITUDE_E6420
- 	default "e6520" if BOARD_DELL_LATITUDE_E6520
-@@ -82,7 +89,8 @@ config VARIANT_DIR
- 	default "e6530" if BOARD_DELL_LATITUDE_E6530
- 
- config VGA_BIOS_ID
--	default "8086,0116" if BOARD_DELL_LATITUDE_E6520
-+	default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \
-+		|| BOARD_DELL_LATITUDE_E5420
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
- 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
- 		|| BOARD_DELL_LATITUDE_E5520
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index 7976691f21..a3fa2b1837 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -1,5 +1,8 @@
- ## SPDX-License-Identifier: GPL-2.0-only
- 
-+config BOARD_DELL_LATITUDE_E5420
-+	bool "Latitude E5420"
-+
- config BOARD_DELL_LATITUDE_E5520
- 	bool "Latitude E5520"
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..98b82fe6110fd295b5749041ec7f8c084ace5f57
-GIT binary patch
-literal 6144
-zcmeHKeQZ-z6hE);wSBvNZ!2$ObQ^;MgV6zl*Rhp}BXnCCMZU^_r7jRwT!kfLo8?3H
-zk9)u(7?cb(hChhTM57@QFfmbMB!G!dNsO6BW5OSp5EGF^jHnTTdhUBI+h`e+1ft1q
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-z6@7Fc$&>sAxwiz{BE$1kb$K9Co=ozlA973y^i(^BM|EZ$$^y`0KyHiMJ%O*XbfEX1
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-X1LGbT_rSOZ#yv3ZfpHH!G!Og(1Xg~J
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c
-new file mode 100644
-index 0000000000..ff83db095b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/early_init.c
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c
-new file mode 100644
-index 0000000000..f76b93d9f0
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/gpio.c
-@@ -0,0 +1,195 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_NATIVE,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_GPIO,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_NATIVE,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio12 = GPIO_DIR_OUTPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio12 = GPIO_LEVEL_HIGH,
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_GPIO,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_NATIVE,
-+	.gpio50 = GPIO_MODE_GPIO,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_GPIO,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_GPIO,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_OUTPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio46 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio50 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_OUTPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio53 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio55 = GPIO_DIR_OUTPUT,
-+	.gpio56 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_LOW,
-+	.gpio37 = GPIO_LEVEL_LOW,
-+	.gpio46 = GPIO_LEVEL_HIGH,
-+	.gpio50 = GPIO_LEVEL_HIGH,
-+	.gpio51 = GPIO_LEVEL_LOW,
-+	.gpio55 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_NATIVE,
-+	.gpio69 = GPIO_MODE_NATIVE,
-+	.gpio70 = GPIO_MODE_NATIVE,
-+	.gpio71 = GPIO_MODE_NATIVE,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_GPIO,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio74 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c
-new file mode 100644
-index 0000000000..0bc6c35a63
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x1028049b,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x1028049b),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0xd5a30130),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb
-new file mode 100644
-index 0000000000..3f55bfd49d
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e5420/overridetree.cb
-@@ -0,0 +1,39 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x049b inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x00000c31"
-+			register "gpu_pch_backlight" = "0x13121312"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
-+			register "usb_port_config" = "{
-+				{ 1, 1, 0 },
-+				{ 1, 1, 0 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 7 },
-+				{ 1, 1, 6 },
-+				{ 1, 1, 6 },
-+				{ 1, 1, 7 },
-+			}"
-+
-+			device ref gbe off end
-+			device ref pcie_rp4 off end
-+			device ref pcie_rp7 on end # Broadcom BCM5761 Gigabit Ethernet
-+			device ref sata1 on
-+				register "sata_port_map" = "0x3b"
-+			end
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0014-lenovo-x230-fix-the-data.vbt-path-for-the-EDP-varian.patch

@@ -0,0 +1,25 @@
+From 9959fe252cceca7005b63e3313f7f95114f1f93c Mon Sep 17 00:00:00 2001
+From: Alexei Sorokin <sor.alexei@meowr.ru>
+Date: Sun, 27 Nov 2022 18:36:26 +0300
+Subject: [PATCH 14/30] lenovo/x230: fix the data.vbt path for the EDP variant
+
+---
+ src/mainboard/lenovo/x230/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig
+index acfd0ed561..34108c3c04 100644
+--- a/src/mainboard/lenovo/x230/Kconfig
++++ b/src/mainboard/lenovo/x230/Kconfig
+@@ -59,7 +59,7 @@ config OVERRIDE_DEVICETREE
+ 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+ 
+ config INTEL_GMA_VBT_FILE
+-	default "variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
++       default "src/mainboard/\$(MAINBOARDDIR)/variants/x230_edp/data.vbt" if BOARD_LENOVO_X230_EDP
+ 
+ config USBDEBUG_HCD_INDEX
+ 	int
+-- 
+2.39.2
+

config/coreboot/default/patches/0014-mb-dell-Add-Latitude-E6320-Sandy-Bridge.patch

@@ -1,435 +0,0 @@
-From cd6e699649459fa5ff2623018ccf3585eb3d3821 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Wed, 7 Feb 2024 15:23:46 -0700
-Subject: [PATCH 14/51] mb/dell: Add Latitude E6320 (Sandy Bridge)
-
-Mainboard is PAL70/LA-6611P. I do not physically have this system;
-someone with physical access to one sent me the output of autoport which
-I then modified to produce this port. I was also sent the VBT binary,
-which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
-version A22 of the vendor firmware. This port has not been tested.
-
-The EC is the SMSC MEC5055, which seems to be compatible with the
-existing MEC5035 code. As with the other Dell systems with this EC, this
-board is assumed to be internally flashable using an EC command that
-tells it to pull the FDO pin low on the next boot, which also tells the
-vendor firmware to disable all write protections to the flash [1].
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: I5905f8c6a8dbad56e03bdeedc2179600d0c4ba46
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |  11 +-
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e6320/data.vbt  | Bin 0 -> 6144 bytes
- .../variants/e6320/early_init.c               |  17 ++
- .../snb_ivb_latitude/variants/e6320/gpio.c    | 190 ++++++++++++++++++
- .../variants/e6320/hda_verb.c                 |  32 +++
- .../variants/e6320/overridetree.cb            |  35 ++++
- 7 files changed, 287 insertions(+), 1 deletion(-)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index e6a21ffb99..84ffe1d33a 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520
- 	select BOARD_ROMSIZE_KB_6144
- 	select SOUTHBRIDGE_INTEL_BD82X6X
- 
-+config BOARD_DELL_LATITUDE_E6320
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_10240
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+
- config BOARD_DELL_LATITUDE_E6420
- 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select BOARD_ROMSIZE_KB_10240
-@@ -67,6 +73,7 @@ config MAINBOARD_DIR
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
- 	default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
-+	default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320
- 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
- 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
- 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
-@@ -82,6 +89,7 @@ config USBDEBUG_HCD_INDEX
- config VARIANT_DIR
- 	default "e5420" if BOARD_DELL_LATITUDE_E5420
- 	default "e5520" if BOARD_DELL_LATITUDE_E5520
-+	default "e6320" if BOARD_DELL_LATITUDE_E6320
- 	default "e6420" if BOARD_DELL_LATITUDE_E6420
- 	default "e6520" if BOARD_DELL_LATITUDE_E6520
- 	default "e5530" if BOARD_DELL_LATITUDE_E5530
-@@ -93,7 +101,8 @@ config VGA_BIOS_ID
- 		|| BOARD_DELL_LATITUDE_E5420
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
- 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
--		|| BOARD_DELL_LATITUDE_E5520
-+		|| BOARD_DELL_LATITUDE_E5520 \
-+		|| BOARD_DELL_LATITUDE_E6320
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
- 		|| BOARD_DELL_LATITUDE_E6530
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index a3fa2b1837..ef6a1329a9 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420
- config BOARD_DELL_LATITUDE_E5520
- 	bool "Latitude E5520"
- 
-+config BOARD_DELL_LATITUDE_E6320
-+	bool "Latitude E6320"
-+
- config BOARD_DELL_LATITUDE_E6420
- 	bool "Latitude E6420"
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..471a9e29da639dd496f3ecebd5d0754a9045c00b
-GIT binary patch
-literal 6144
-zcmeHKeP|p-6#wn*-rZ(yH@R-odPzTgZEU>S#_pv}j2iKhT+^%8_DtJw21|4GP8*0x
-zyw;EYW49Xozz<Rt@ek1mic(N32r8oZ0U9lcR8a)~s33wLV8yCftLK~DJJWb)8w-j;
-z=J?H<nfK<+n>TOX?48xuwV5_`Zb)3w)w?dSc1`nTL|NF_SMw&<<)v%g#!cH2otrzi
-zb*<mneJMSLdC1iK_7#v-6w7R}+t1&W8P4wBo*&F!lcNn?)F-EqWZV#oQEb%`x-4^5
-zW@sogOik1`n9Wc#r82|0A!=-0LD!FFGrMwG+CDg($q(js(#Y`8?s79ubEJD@ba#I6
-znjO0++P#czvh8NBR?)iQUA%txNPhHO>Kq!PUMaJadUHE-`5SWCb4_6i;5Aj(6hQGK
-zcq^2uUt5sS5YSMiL+CJcs0#cVOdTN|K@D>?tkF=dqenwjM^Z-^K2z~&z+xRs!o^Jx
-zkUGd?>QtXw8V(I09OiMb0DZy>`=tO^#BCssw{}bkOnj=#Ic!~!6!J*{`jbEv5O4)-
-zg-UBlIa$c9Pg4C;0_-wq3t+dbZfn1wBi@zhNnWx()w{Vb-G8OC_m*478gTrX3U*a1
-zHr@y<Lcbct?Wzy^)OH+FC$S`8V@n`{QN~@2dxJU-1ucBe_>rOO78dFPXES1q3mHj9
-zFXKwa)r^}Mw=nKzJjj?}>}NdBc$G29IK=pr@de`u;}}D$5~yYbw&Hlf=OF0X?I=Y$
-z$D`mgy>}U$hl}G6m&PmXveHnY5DenC!g~=E3i?HIrEpyk>_(-IsVtEqUEoqxrDFdq
-zrYwhOv0o^NgW$OKN}=$7Z-w5*Vuv?T3~uuFGwP92?Qr8n0iQp=u*7rep9Q8dW#?ZI
-zFly1ww^^l*+YC6t16l_{g}tVVpVZ0fDk%5+`|+*688vr-<Lw_SRc^+avHI{BCpdYb
-z70yLEI0-45%t;z||GKzov+|VFW6hab&NAG9FD+h6sBu$cX`r0eJ%T`kvK4+(wT`0=
-z$fxKG+om?Ge1-EhbNc*Xjy1opKZSaiv-EL~GvOa&&bx~z##3W;F2{b=<HQ4!<1CFk
-z17i)$X+`=C=0udOPOx3$IjzopqwQzLr*jT4C)(jmj2>uYP8$M=#caX6OWA1Ez395U
-z%x<yAs)6-Ascr5<x*>CIZibyRlE~I0-ianVaz~q|EMlL7hc1U5w?}Kekws6fyy@`e
-z4NdX%L#2`A#c_N4ftGmuwbDo=incwf=WnBJk6)fYz%6Cmy>HwK$Y|iP`Y7sgjDPhQ
-zR|wv367k}1g)-G@kXq(X;{Bjt998b9{cpD9zGhOQ5%$4OSMtc2(<dx@0O}7_G+$WF
-zLYyaPtFT6d*e&Q$VLd0r%Yr@=*7rjEDyT7JwT8sSA<BiU8$)7mh@K2tFNMULA^I|8
-z{Sp#>gO(fCMTS^w(6xrO#}IcK^sHgMZis^heP>uIf6|z=%Cy#)Vxvjdo7U~7*k{rU
-zruB{~J}~KL(+X9Kxz*-5M>NNGSaIfXi19({d4mrk?K50@R0%Wn*PP9d(MMIzI2~RX
-z)(4h&8(YL@UyKJ*)4o${n5ZGd(hDf+)cv8sSBxWen|f*u<-sgt(u+U-bkd}Tj+5@9
-zJosfSdvPo8zGnluemJg=E7A{=N<Rc#KYYEg?^p`+_?~aU(kEmFus{DshA~iA(onLY
-zvIfpBJt;KWP4n8&`n1##c($WnDo|=?rlHBz&}36&HPWwp8op_i8c-**(TSd{Y{SZ?
-z_=^K$27e+q;^vRNU3~a=cd;V{%O=iuo*&xwXyg19${Ap0yO@a|N-<e^7iIClF{vUn
-z&4$y_V7MA)=E=%7n63u!J9FY$RK8hXHDE%%Lx$ZgX902-<9r|4lkx>QwFch>PUO1w
-z=6JffnB-kQ)VLb>sSZdDrI@U2!?HLA9Mlek!*k>;&jx<)xfnBiY^I6DRt*l*`n8ly
-zu!h)b?sRV1==Nf*Cw9&&i7n^9Nts>wk>adaY&E5OdW*A?iI}v+E6GGlsR<+#%jpl^
-zGz<Q^vpj>qhDjj3zr60Bgh=l{NzJp$x#fCR%*8!ZR?fC&JuvHmSr5#5VAcb(9+>sO
-IzvhA80TAzedH?_b
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
-new file mode 100644
-index 0000000000..b0c4638858
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/early_init.c
-@@ -0,0 +1,17 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+const struct southbridge_usb_port mainboard_usb_ports[] = {
-+};
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
-new file mode 100644
-index 0000000000..61f01816c4
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/gpio.c
-@@ -0,0 +1,190 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_NATIVE,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_NATIVE,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
-new file mode 100644
-index 0000000000..2e3f7fa697
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x10280492,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x10280492),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
-new file mode 100644
-index 0000000000..3bfe6b57ed
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6320/overridetree.cb
-@@ -0,0 +1,35 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x0492 inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x00000622"
-+			register "gpu_pch_backlight" = "0x13121312"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "usb_port_config" = "{
-+				{ 1, 1, 0 },
-+				{ 1, 0, 0 },
-+				{ 1, 1, 1 },
-+				{ 1, 0, 1 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 3 },
-+				{ 1, 0, 5 },
-+				{ 1, 0, 5 },
-+				{ 1, 1, 7 },
-+				{ 1, 1, 6 },
-+				{ 1, 0, 6 },
-+				{ 1, 0, 7 },
-+			}"
-+
-+			device ref sata1 on
-+				register "sata_port_map" = "0x3b"
-+			end
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0015-mb-dell-Add-Latitude-E6220-Sandy-Bridge.patch

@@ -1,438 +0,0 @@
-From a32431d5f7574ffa6391221c7740f1739203eaa7 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 8 Mar 2024 09:27:36 -0700
-Subject: [PATCH 15/51] mb/dell: Add Latitude E6220 (Sandy Bridge)
-
-Mainboard is codenamed Vida. I do not physically have this system;
-someone with physical access to one sent me the output of autoport which
-I then modified to produce this port. The VBT was obtained using
-intelvbttool while running version A14 (latest available version) of the
-vendor firmware.
-
-Tested and found to boot as part of a libreboot build based on upstream
-coreboot commit b7341da191 with additional patches, though these do not
-appear to affect SNB/IVB. The base E6430 patch was tested against
-coreboot main.
-
-The EC is the SMSC MEC5055, which seems to be compatible with the
-existing MEC5035 code. As with the other Dell systems with this EC, this
-board is assumed to be internally flashable using an EC command that
-tells it to pull the FDO pin low on the next boot, which also tells the
-vendor firmware to disable all write protections to the flash [1].
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: I570023b0837521b75aac6d5652c74030c06b8a4c
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |   9 +
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e6220/data.vbt  | Bin 0 -> 3985 bytes
- .../variants/e6220/early_init.c               |  14 ++
- .../snb_ivb_latitude/variants/e6220/gpio.c    | 192 ++++++++++++++++++
- .../variants/e6220/hda_verb.c                 |  32 +++
- .../variants/e6220/overridetree.cb            |  37 ++++
- 7 files changed, 287 insertions(+)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index 84ffe1d33a..baa83baa41 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -27,6 +27,12 @@ config BOARD_DELL_LATITUDE_E5520
- 	select BOARD_ROMSIZE_KB_6144
- 	select SOUTHBRIDGE_INTEL_BD82X6X
- 
-+config BOARD_DELL_LATITUDE_E6220
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_10240
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select SOUTHBRIDGE_INTEL_BD82X6X
-+
- config BOARD_DELL_LATITUDE_E6320
- 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select BOARD_ROMSIZE_KB_10240
-@@ -73,6 +79,7 @@ config MAINBOARD_DIR
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E5420" if BOARD_DELL_LATITUDE_E5420
- 	default "Latitude E5520" if BOARD_DELL_LATITUDE_E5520
-+	default "Latitude E6220" if BOARD_DELL_LATITUDE_E6220
- 	default "Latitude E6320" if BOARD_DELL_LATITUDE_E6320
- 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
- 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
-@@ -89,6 +96,7 @@ config USBDEBUG_HCD_INDEX
- config VARIANT_DIR
- 	default "e5420" if BOARD_DELL_LATITUDE_E5420
- 	default "e5520" if BOARD_DELL_LATITUDE_E5520
-+	default "e6220" if BOARD_DELL_LATITUDE_E6220
- 	default "e6320" if BOARD_DELL_LATITUDE_E6320
- 	default "e6420" if BOARD_DELL_LATITUDE_E6420
- 	default "e6520" if BOARD_DELL_LATITUDE_E6520
-@@ -102,6 +110,7 @@ config VGA_BIOS_ID
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
- 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
- 		|| BOARD_DELL_LATITUDE_E5520 \
-+		|| BOARD_DELL_LATITUDE_E6220 \
- 		|| BOARD_DELL_LATITUDE_E6320
- 	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
- 		|| BOARD_DELL_LATITUDE_E6530
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index ef6a1329a9..349ee7f79e 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -6,6 +6,9 @@ config BOARD_DELL_LATITUDE_E5420
- config BOARD_DELL_LATITUDE_E5520
- 	bool "Latitude E5520"
- 
-+config BOARD_DELL_LATITUDE_E6220
-+	bool "Latitude E6220"
-+
- config BOARD_DELL_LATITUDE_E6320
- 	bool "Latitude E6320"
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..548075a74500b5d159108089ee29cff802d07db7
-GIT binary patch
-literal 3985
-zcmdT{eP|p-6#wn*-rZ(yH@R-odPzTgZQ6LXjonL|7&YQ0xu#d`$C=h}21|4GP8*0x
-zyjE@hv0Dv(P?c0g{G(_DMJZ@22r8oZ0U9lcR8a)~s33wOSg|T<^?b8?XBzL?#)6`A
-z{N~Nfd-LYan>TOv7WZ{+rcIq264!S1u1&02-MpSC3mf}u-r~BvbgkXEX=|c$bLZBs
-zbsM{{q9-s1nVR3f2C|A`nJsqvC7UwC+1=angV`H%w4sao<P?&OTVpYbtz1OwGuLN^
-zhBCv{M16zV3^h|KGn^Zu#@6L@%V;*UGnb`pgTtBpU~UJE3=i!tH{%>fx<^KL=Lc`x
-zzLTQeOW7vdZsuwwtsUOU>vxajM=zqzp&{y(GCQa@w<DLoHJ81}6s7=PS9MJR6hDG@
-zLaF+#1qlrS4OKdX4nv2kz^}p75z-OVFk8cF4b?h&G(>eIb%fzF6`uwy)UhaB+ynus
-zBRr-~^|__t=m5fD9tR81r@XLV3UEc-2I6>o`;@@MXS$rj)&)r+pA?|K2vh+9SHM=N
-zw3d{Uh1~iK)juV`E`v4?cFU@^_DehBU5TFLmFrTyoBPuJ*ExIdxO1!lC!eceSG8i}
-z&A<Zmt5Mvo`mkSZ$5C|>ivl*T2}Cf;*vEJvsN-nR!WWDm8M<y^zAkV9BgVLlk!18T
-zu4CN5*u}VmaUbIm#suRa;|0cRj7i2(#%GK#8OIsFFtjRxYDQoSP8NI)g09_;Qlzsy
-z3O>^Zmcltu96wMRudvHXLxn;xh~EqEM^Gr}m&=vHbwRKjl{%)fM2d8tOI4MM{l!dK
-z4$)%2P!LDJaqX2t;s4$Wy@Q1gZ=x97<n3qFBc<Bm#;F26e|~<6=hD9lOk>K<zaU`L
-zqML8CN*#9@aDs=m4ulGOO%*?>lhsvF9`g6&TYocZ_JQN=A1hUE#+kAD@E9jJd7%}~
-zMLIYMDVoel8h1}$+_YJF%DJ&-O)X~`ZoroouO-yDsj)OrPU{{+ph4LJKdD;Bi3a3T
-zbe?Tf8&<r^`I<R>elW+H+t;5$y~|nhq{o@?k1^-Hg%jhcu{xJyzvgk`0m*Te#GQe$
-z2IjOP{U&oF$`&WsuJN2!=fTnT^W)PwhnW-Ya3)3%H!`OUfy6?#V9r%+wCY}TU0!Cl
-z*kjeex}MZl_aWVoxhXfp&Ur~>>k;onlO4II%~KY!FT|r)!;agdwcf~rXIAVwc6CEj
-zJpE{CBzZ;L-gdYp9)G<w5{aU1kLvl`XxrnL=MQj88F%j+w*oR6c&t8(di=t_dW<Us
-z?>C8f@wZ%=YBfkLb0_gZP%us?_tgG3TXJ7BDbWb~V23Mt{QT(?mOc#ihbo#YtY#rD
-z7PLiJBSP#J^tiB|7vdE`p9|}IA$}9o7_wSJ;))RELe^~|u{T6dhpd-F;;j&U6|#N}
-z3BN(h4C``3tTE^&!`fqrdks2dSZ^5Oh(X^Omdc+rCapBB)uz~J(k-TSw<-3U^rC6K
-zYl;s|`q{KX)nazFdEs%*@f}l~SsY?~kb2(WgGl=fm!43<O#L+%@MH9Gl`~Gq=7;rx
-zMc&31@YxsRfz-6`>>4I&2(k1$iaK?FYVZ}~h~1{1T|;>=%b4`yk3XF>siEVHyC@HS
-z8OvVW%DeB`K&~H7>f?&^gQU_A0oM<l8+N5oZ4)iV>;p0b*k61j!x*S5X(-unS`9rZ
-zG}=vb+R*x})DSq-Q7;uJwKLPuG`Ej6G}#nch4dSqhHo0B2Gq%HbgCyS+pwZ3{?fph
-z!Jo*Dxcw7v7a#rIU2IRmVn4KE$x~88+a7J4zd|_!%xo9z$+P;Q6qA*AQ5FvzlPW^f
-zY&aJUhO1#_o~&$x>1qJKGpC+K<(u_&1197<WZ2zu79e*q&i9c$DPNGYYw%s_L~d?x
-zj;EW8N#6BCjjMs5>VVWxipk10ERAEpLG3^|JWI~<Y~c5vi!sB;W|~-R<=`-_TSLhN
-zYlyAlPUkfn-CnHq)Xv2vv1R->DYG*_Qk)fwt)g^KZ*f*K5tEj9C7Ea`HGyPe8U4wd
-nX2Iz@%Q6UTm;}-X%j^D0i1fiT)I6)4TdrsMY}`L(<y7krryzQ}
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c
-new file mode 100644
-index 0000000000..ff83db095b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/early_init.c
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
-new file mode 100644
-index 0000000000..2306e4cf0a
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/gpio.c
-@@ -0,0 +1,192 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_GPIO,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_NATIVE,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_GPIO,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio1 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+	.gpio30 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio30 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio1 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_OUTPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio49 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
-new file mode 100644
-index 0000000000..0c69f0bd0e
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
-+	0x102804a9,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x102804a9),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862805,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
-new file mode 100644
-index 0000000000..9faf27e27b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6220/overridetree.cb
-@@ -0,0 +1,37 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x04a9 inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x0000046a"
-+			register "gpu_pch_backlight" = "0x13121312"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
-+			register "usb_port_config" = "{
-+				{ 1, 1, 0 },
-+				{ 1, 0, 0 },
-+				{ 1, 1, 1 },
-+				{ 1, 0, 1 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 3 },
-+				{ 1, 1, 3 },
-+				{ 1, 0, 5 },
-+				{ 1, 0, 5 },
-+				{ 1, 1, 7 },
-+				{ 1, 1, 6 },
-+				{ 1, 0, 6 },
-+				{ 1, 0, 7 },
-+			}"
-+
-+			device ref pcie_rp4 off end
-+			device ref sata1 on
-+				register "sata_port_map" = "0x3b"
-+			end
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0015-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch

@@ -1,7 +1,7 @@
-From d2f579b82921c2c35e4cf756db0ca476fbadfac1 Mon Sep 17 00:00:00 2001
+From 158b79e6057e071d039619f617c112d31fb13f64 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
+From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 05/51] util/ifdtool: add --nuke flag (all 0xFF on region)
+Subject: [PATCH 15/30] util/ifdtool: add --nuke flag (all 0xFF on region)
 
 When this option is used, the region's contents are overwritten
 with all ones (0xFF).
@@ -16,14 +16,14 @@ Rebased since the last revision update in lbmk.
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
- util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
+ util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
- 1 file changed, 83 insertions(+), 31 deletions(-)
+ 1 file changed, 81 insertions(+), 31 deletions(-)
 
 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index 32b2081d93..1473cf058b 100644
+index 191b3216de..38132b4a28 100644
 --- a/util/ifdtool/ifdtool.c
 +++ b/util/ifdtool/ifdtool.c
-@@ -2204,6 +2204,7 @@ static void print_usage(const char *name)
+@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
  	       "                                         tgl    - Tiger Lake\n"
  	       "                                         wbg    - Wellsburg\n"
  	       "   -S | --setpchstrap                    Write a PCH strap\n"
@@ -31,7 +31,7 @@ index 32b2081d93..1473cf058b 100644
  	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
  	       "   -v | --version:                       print the version\n"
  	       "   -h | --help:                          print this help\n\n"
-@@ -2212,6 +2213,60 @@ static void print_usage(const char *name)
+@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
  	       "\n");
  }
  
@@ -92,15 +92,15 @@ index 32b2081d93..1473cf058b 100644
  int main(int argc, char *argv[])
  {
  	int opt, option_index = 0;
-@@ -2219,6 +2274,7 @@ int main(int argc, char *argv[])
+@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
  	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
  	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
  	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
 +	int mode_nuke = 0;
- 	int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
+ 	int mode_gpr0_disable = 0;
  	char *region_type_string = NULL, *region_fname = NULL;
  	const char *layout_fname = NULL;
-@@ -2254,6 +2310,7 @@ int main(int argc, char *argv[])
+@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
  		{"validate", 0, NULL, 't'},
  		{"setpchstrap", 1, NULL, 'S'},
  		{"newvalue", 1, NULL, 'V'},
@@ -108,7 +108,7 @@ index 32b2081d93..1473cf058b 100644
  		{0, 0, 0, 0}
  	};
  
-@@ -2303,35 +2360,8 @@ int main(int argc, char *argv[])
+@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
  			region_fname++;
  			// Descriptor, BIOS, ME, GbE, Platform
  			// valid type?
@@ -141,12 +141,12 @@ index 32b2081d93..1473cf058b 100644
 -			else if (!strcasecmp("PTT", region_type_string))
 -				region_type = 15;
 -			if (region_type == -1) {
-+			if ((region_type =
++                       if ((region_type =
-+			    get_region_type_string(region_type_string)) == -1) {
++                           get_region_type_string(region_type_string)) == -1) {
  				fprintf(stderr, "No such region type: '%s'\n\n",
  					region_type_string);
  				fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
-@@ -2508,6 +2538,22 @@ int main(int argc, char *argv[])
+@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
  		case 't':
  			mode_validate = 1;
  			break;
@@ -169,37 +169,35 @@ index 32b2081d93..1473cf058b 100644
  		case 'v':
  			print_version();
  			exit(EXIT_SUCCESS);
-@@ -2524,7 +2570,8 @@ int main(int argc, char *argv[])
+@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
  	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
  			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
  			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
--			(mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
+-			mode_gpr0_disable) > 1) {
-+			(mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
++			mode_gpr0_disable + mode_nuke) > 1) {
-+			mode_nuke) > 1) {
  		fprintf(stderr, "You may not specify more than one mode.\n\n");
  		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
  		exit(EXIT_FAILURE);
-@@ -2533,7 +2580,8 @@ int main(int argc, char *argv[])
+@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
  	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
  			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
  			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
--			mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
+-			mode_validate + mode_gpr0_disable) == 0) {
-+			mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
++			mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
-+			mode_nuke) == 0) {
  		fprintf(stderr, "You need to specify a mode.\n\n");
  		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
  		exit(EXIT_FAILURE);
-@@ -2646,6 +2694,10 @@ int main(int argc, char *argv[])
+@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
  		write_image(new_filename, image, size);
  	}
  
-+	if (mode_nuke) {
++       if (mode_nuke) {
-+		nuke(new_filename, image, size, region_type);
++               nuke(new_filename, image, size, region_type);
-+	}
++       }
 +
  	if (mode_altmedisable) {
  		struct fpsba *fpsba = find_fpsba(image, size);
  		struct fmsba *fmsba = find_fmsba(image, size);
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0016-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch

@@ -0,0 +1,47 @@
+From bb83e857a2e7b6ecb7cb476ba65019b14e68dc34 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Wed, 1 Dec 2021 02:53:00 +0000
+Subject: [PATCH 16/30] fix speedstep on x200/t400: Revert
+ "cpu/intel/model_1067x: enable PECI"
+
+This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
+
+Enabling PECI without microcode updates loaded causes the CPUID feature set
+to become corrupted. And one consequence is broken SpeedStep. At least, that's
+my understanding looking at Intel Errata. This revert is not a fix, because
+upstream is correct (upstream assumes microcode updates). We will simply
+maintain this revert patch in Libreboot, from now on.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 315e7c36fc..1423fd72bc 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
+ 	wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
+ }
+ 
+-#define IA32_PECI_CTL		0x5a0
+-
+ static void configure_misc(const int eist, const int tm2, const int emttm)
+ {
+ 	msr_t msr;
+@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
+ 		msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
+ 		wrmsr(IA32_MISC_ENABLE, msr);
+ 	}
+-
+-	/* Enable PECI
+-	   WARNING: due to Erratum AW67 described in Intel document #318733
+-	   the microcode must be updated before this MSR is written to. */
+-	msr = rdmsr(IA32_PECI_CTL);
+-	msr.lo |= 1;
+-	wrmsr(IA32_PECI_CTL, msr);
+ }
+ 
+ #define PIC_SENS_CFG	0x1aa
+-- 
+2.39.2
+

config/coreboot/default/patches/0016-mb-dell-Add-Latitude-E6330-Ivy-Bridge.patch

@@ -1,436 +0,0 @@
-From 0889cc6b6f62cba616feff5ae8558be31f298069 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 8 Mar 2024 09:33:03 -0700
-Subject: [PATCH 16/51] mb/dell: Add Latitude E6330 (Ivy Bridge)
-
-Mainboard is QAL70/LA-7741P. I do not physically have this system;
-someone with physical access to one sent me the output of autoport which
-I then modified to produce this port. I was also sent the VBT binary,
-which was obtained from `/sys/kernel/debug/dri/0/i915_vbt` while running
-version A21 of the vendor firmware. This port has not been tested.
-
-The EC is the SMSC MEC5055, which seems to be compatible with the
-existing MEC5035 code. As with the other Dell systems with this EC, this
-board is assumed to be internally flashable using an EC command that
-tells it to pull the FDO pin low on the next boot, which also tells the
-vendor firmware to disable all write protections to the flash [1].
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Change-Id: I827826e9ff8a9a534c50250458b399104478e06c
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |  11 +-
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e6330/data.vbt  | Bin 0 -> 6144 bytes
- .../variants/e6330/early_init.c               |  14 ++
- .../snb_ivb_latitude/variants/e6330/gpio.c    | 192 ++++++++++++++++++
- .../variants/e6330/hda_verb.c                 |  32 +++
- .../variants/e6330/overridetree.cb            |  37 ++++
- 7 files changed, 288 insertions(+), 1 deletion(-)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index baa83baa41..49bf225fe2 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530
- 	select BOARD_ROMSIZE_KB_12288
- 	select SOUTHBRIDGE_INTEL_C216
- 
-+config BOARD_DELL_LATITUDE_E6330
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_12288
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select SOUTHBRIDGE_INTEL_C216
-+
- config BOARD_DELL_LATITUDE_E6430
- 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select BOARD_ROMSIZE_KB_12288
-@@ -84,6 +90,7 @@ config MAINBOARD_PART_NUMBER
- 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
- 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
- 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
-+	default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330
- 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
- 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
- 
-@@ -101,13 +108,15 @@ config VARIANT_DIR
- 	default "e6420" if BOARD_DELL_LATITUDE_E6420
- 	default "e6520" if BOARD_DELL_LATITUDE_E6520
- 	default "e5530" if BOARD_DELL_LATITUDE_E5530
-+	default "e6330" if BOARD_DELL_LATITUDE_E6330
- 	default "e6430" if BOARD_DELL_LATITUDE_E6430
- 	default "e6530" if BOARD_DELL_LATITUDE_E6530
- 
- config VGA_BIOS_ID
- 	default "8086,0116" if BOARD_DELL_LATITUDE_E6520 \
- 		|| BOARD_DELL_LATITUDE_E5420
--	default "8086,0166" if BOARD_DELL_LATITUDE_E5530
-+	default "8086,0166" if BOARD_DELL_LATITUDE_E5530 \
-+		|| BOARD_DELL_LATITUDE_E6330
- 	default "8086,0126" if BOARD_DELL_LATITUDE_E6420 \
- 		|| BOARD_DELL_LATITUDE_E5520 \
- 		|| BOARD_DELL_LATITUDE_E6220 \
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index 349ee7f79e..d6fc8eb224 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520
- config BOARD_DELL_LATITUDE_E5530
- 	bool "Latitude E5530"
- 
-+config BOARD_DELL_LATITUDE_E6330
-+	bool "Latitude E6330"
-+
- config BOARD_DELL_LATITUDE_E6430
- 	bool "Latitude E6430"
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..18856746656058651c571ecbb3708e0543b19d62
-GIT binary patch
-literal 6144
-zcmeHKU2GiH75-*tc6WAmW_LYygMSkDB*E^Q*zv5f7dLg)@$NQV2a{}!yImnfyvQ4D
-z;n-$v0!RpNi<_o@ktI-@2a590stC0zRi%iRR%stvi&hAs3R<K}X~hFddB_6@s8W`5
-zXJ!q~E{TOme<a`8@BW;7?l<?GIp@yo&H2<M-FZ0GKbBAR-Ekx}HvVOrhK1*2?{QsU
-zQe#K%JeC=q96gpAKa#$keu^D99ee*0FfB=@F_0J<9-Ch-&BZ5r1T6`{$;1%Fm+qfk
-zTr5pfAz@KB*NGlFzEGx2aqh%IxkQOuX*`{wy~+KQo+-}XSE7aaxko77OBtFgoh;4K
-z(#-7f<x+WxmKSK)vQFgtt^L+?s+Z<V57E7|^TqOPX{mn0n<VLl#Yf7s_suL*Jl#VB
-zmSyz~ScwEVTc-3vd2v6D&dt$;&{?91(o(5>vNXNl&<qW@AghW5NPYw#ha~-b0Dc7_
-z6}t(eHgpwn6<HNi1Vcp^p-07-iXve~MTs!0A_ku!`4nKciajxJYXsOYuuT4N%smA!
-zPazgl&bNRSrvAz|_6r3+B;r1=!7D;RUUw8Ke+vNt7E3`(BA-woPvJFBK^3Gzfh4Nk
-zOX!J0PJNB)Mk&Z_i?S2ez+iItz=)m79LydX&rM9`3wPaJ`T92=Uv0;g-!<4*M6z%+
-z*omwb#VI+CU&%iFS{_DGS;sE}7G4juqRMCww!+k6=+abJj4v>Dsr*z_6HAP5GJeST
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-z*H2<VyY>2;juB|7F+k?y(_2~3@STqQ@f^sqD2c8g3x>ciM%siMq~;pKwfE57kw2K@
-z!-ZN0QTVOP@aA5@fEGKjy2+D`t?2KzpPyRQ`JcmHJoc(<#h<UT;@W$t_d{|;S>vyF
-zewtgef*II~y;k>*B!+(8*blXsY-~kcJa9zG2yfcMCt+|-0ex$pY`h1<*#rEv=~*<+
-ztV``Um!q33-Aap9fUshX^N~GS2@X3^U9+MwgYQ74^?~6&yU^#oY#cvC9R_}P2d<wN
-zJvOE)Xr7A2n#3x14}2_g(YN^0+oYDbb#|V{ze3pzGb9FiF#6Ra&L}bT(ZOvswS7RY
-zxLjWFRwWXHR5&={t;%K+Vkd6NX2iF<SF)LXv@y472OmG!_W%Ni*ZDuev-S0%b!dfW
-wz4{IL!+uT9t2XI4@_L@?Ri*bc_<n8A+wHaowmq=zfo%_LdtloGpN<DU00~N<ApigX
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
-new file mode 100644
-index 0000000000..ff83db095b
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/early_init.c
-@@ -0,0 +1,14 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
-+			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
-+			| COMB_LPC_EN | COMA_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
-new file mode 100644
-index 0000000000..777570765a
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/gpio.c
-@@ -0,0 +1,192 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_GPIO,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio1 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+	.gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio13 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
-new file mode 100644
-index 0000000000..804733b172
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76df,	/* Codec Vendor / Device ID: IDT */
-+	0x10280533,	/* Subsystem ID */
-+	11,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x10280533),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862806,	/* Codec Vendor / Device ID: Intel */
-+	0x80860101,	/* Subsystem ID */
-+	4,		/* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
-new file mode 100644
-index 0000000000..4125159367
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6330/overridetree.cb
-@@ -0,0 +1,37 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x0533 inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x00001312"
-+			register "gpu_pch_backlight" = "0x13121312"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "usb_port_config" = "{
-+				{ 1, 2, 0 },
-+				{ 1, 0, 0 },
-+				{ 1, 0, 1 },
-+				{ 1, 1, 1 },
-+				{ 1, 1, 2 },
-+				{ 1, 1, 2 },
-+				{ 1, 2, 3 },
-+				{ 1, 2, 3 },
-+				{ 1, 2, 4 },
-+				{ 1, 1, 4 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 5 },
-+				{ 1, 2, 6 },
-+				{ 1, 0, 6 },
-+			}"
-+
-+			device ref xhci on
-+				register "superspeed_capable_ports" = "0x0000000f"
-+				register "xhci_overcurrent_mapping" = "0x00000c03"
-+				register "xhci_switchable_ports" = "0x0000000f"
-+			end
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0017-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch

@@ -0,0 +1,173 @@
+From 8a94f38398b8fa554fa4ae53ecb88a372df634fd Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 17 Apr 2023 15:49:57 +0100
+Subject: [PATCH 17/30] GM45-type CPUs: don't enable alternative SMRR
+
+This reverts the changes in coreboot revision:
+df7aecd92643d207feaf7fd840f8835097346644
+
+While this fix is *technically correct*, the one in
+coreboot, it breaks rebooting as tested on several
+GM45 ThinkPads e.g. X200, T400, when microcode
+updates are not applied.
+
+Since November 2022, Libreboot includes microcode
+updates by default, but it tells users how to remove
+it from the ROM (with cbfstool) if they wish.
+
+Well, with Libreboot 20221214, 20230319 and 20230413,
+mitigations present in Libreboot 20220710 (which did
+not have microcode updates) do not exist.
+
+This patch, along with the other patch to remove PECI
+support (which breaks speedstep when microcode updates
+are not applied) have now been re-added to Libreboot.
+
+It is still best to use microcode updates by default.
+These patches in coreboot are not critically urgent,
+and you can use the machines with or without them,
+regardless of ucode.
+
+I'll probably re-write this and the other patch at
+some point, applying the change conditionally upon
+whether or not microcode is applied.
+
+Pragmatism is a good thing. I recommend it.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c |  4 +++
+ src/cpu/intel/model_1067x/mp_init.c          | 26 --------------------
+ src/cpu/intel/model_106cx/model_106cx_init.c |  4 +++
+ src/cpu/intel/model_6ex/model_6ex_init.c     |  4 +++
+ src/cpu/intel/model_6fx/model_6fx_init.c     |  4 +++
+ 5 files changed, 16 insertions(+), 26 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 1423fd72bc..d1f98ca43a 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -8,6 +8,7 @@
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
+ #include <cpu/intel/smm_reloc.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define MSR_BBL_CR_CTL3		0x11e
+ 
+@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states(quad);
+ 
+diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
+index bc53214310..72f40f6762 100644
+--- a/src/cpu/intel/model_1067x/mp_init.c
++++ b/src/cpu/intel/model_1067x/mp_init.c
+@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
+ 	smm_initialize();
+ }
+ 
+-#define SMRR_SUPPORTED (1 << 11)
+-
+ static void per_cpu_smm_trigger(void)
+ {
+-	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+-	if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
+-		set_feature_ctrl_vmx();
+-		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
+-		/* We don't care if the lock is already setting
+-		   as our smm relocation handler is able to handle
+-		   setups where SMRR is not enabled here. */
+-		if (ia32_ft_ctrl.lo & (1 << 0)) {
+-			/* IA32_FEATURE_CONTROL locked. If we set it again we
+-			   get an illegal instruction. */
+-			printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
+-			printk(BIOS_DEBUG, "SMRR status: %senabled\n",
+-			       ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
+-		} else {
+-			if (!CONFIG(SET_IA32_FC_LOCK_BIT))
+-				printk(BIOS_INFO,
+-				       "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
+-			ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
+-			wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
+-		}
+-	} else {
+-		set_vmx_and_lock();
+-	}
+-
+ 	/* Relocate the SMM handler. */
+ 	smm_relocate();
+ }
+diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
+index 05f5f327cc..0450c2ad83 100644
+--- a/src/cpu/intel/model_106cx/model_106cx_init.c
++++ b/src/cpu/intel/model_106cx/model_106cx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
+index 5bd1c32815..f3bb08cde3 100644
+--- a/src/cpu/intel/model_6ex/model_6ex_init.c
++++ b/src/cpu/intel/model_6ex/model_6ex_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
+index 535fb8fae7..f7b05facd2 100644
+--- a/src/cpu/intel/model_6fx/model_6fx_init.c
++++ b/src/cpu/intel/model_6fx/model_6fx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+-- 
+2.39.2
+

config/coreboot/default/patches/0017-mb-dell-Add-Latitude-E6230-Ivy-Bridge.patch

@@ -1,440 +0,0 @@
-From 84d7f3201eb4492acd7d290a02d19c4850c85791 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Thu, 26 Oct 2017 21:26:43 +0800
-Subject: [PATCH 17/51] mb/dell: Add Latitude E6230 (Ivy Bridge)
-
-This was adapted from CB:22693 from Iru Cai, which was based on
-autoport. I do not physically have this system. Someone with physical
-access to an E6230 running version A11 of the vendor firmware sent me
-the VBT after running the command `intelvbttool --inlegacy --outvbt
-data.vbt`. This new version of the port has not yet been tested.
-
-The EC is the SMSC MEC5055, which seems to be compatible with the
-existing MEC5035 code. As with the other Dell systems with this EC, this
-board is assumed to be internally flashable using an EC command that
-tells it to pull the FDO pin low on the next boot, which also tells the
-vendor firmware to disable all write protections to the flash [1].
-
-[1] https://gitlab.com/nic3-14159/dell-flash-unlock
-
-Original-Change-Id: I8cdc01e902e670310628809416290045c2102340
-Change-Id: I32927beea7c29b96a851ab77ed15b0160f16d369
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/snb_ivb_latitude/Kconfig   |  11 +-
- .../dell/snb_ivb_latitude/Kconfig.name        |   3 +
- .../snb_ivb_latitude/variants/e6230/data.vbt  | Bin 0 -> 4280 bytes
- .../variants/e6230/early_init.c               |  12 ++
- .../snb_ivb_latitude/variants/e6230/gpio.c    | 193 ++++++++++++++++++
- .../variants/e6230/hda_verb.c                 |  32 +++
- .../variants/e6230/overridetree.cb            |  40 ++++
- 7 files changed, 290 insertions(+), 1 deletion(-)
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-index 49bf225fe2..f6e097930b 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig
-@@ -56,6 +56,12 @@ config BOARD_DELL_LATITUDE_E5530
- 	select BOARD_ROMSIZE_KB_12288
- 	select SOUTHBRIDGE_INTEL_C216
- 
-+config BOARD_DELL_LATITUDE_E6230
-+	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
-+	select BOARD_ROMSIZE_KB_12288
-+	select MAINBOARD_USES_IFD_GBE_REGION
-+	select SOUTHBRIDGE_INTEL_C216
-+
- config BOARD_DELL_LATITUDE_E6330
- 	select BOARD_DELL_SNB_IVB_LATITUDE_COMMON
- 	select BOARD_ROMSIZE_KB_12288
-@@ -90,6 +96,7 @@ config MAINBOARD_PART_NUMBER
- 	default "Latitude E6420" if BOARD_DELL_LATITUDE_E6420
- 	default "Latitude E6520" if BOARD_DELL_LATITUDE_E6520
- 	default "Latitude E5530" if BOARD_DELL_LATITUDE_E5530
-+	default "Latitude E6230" if BOARD_DELL_LATITUDE_E6230
- 	default "Latitude E6330" if BOARD_DELL_LATITUDE_E6330
- 	default "Latitude E6430" if BOARD_DELL_LATITUDE_E6430
- 	default "Latitude E6530" if BOARD_DELL_LATITUDE_E6530
-@@ -108,6 +115,7 @@ config VARIANT_DIR
- 	default "e6420" if BOARD_DELL_LATITUDE_E6420
- 	default "e6520" if BOARD_DELL_LATITUDE_E6520
- 	default "e5530" if BOARD_DELL_LATITUDE_E5530
-+	default "e6230" if BOARD_DELL_LATITUDE_E6230
- 	default "e6330" if BOARD_DELL_LATITUDE_E6330
- 	default "e6430" if BOARD_DELL_LATITUDE_E6430
- 	default "e6530" if BOARD_DELL_LATITUDE_E6530
-@@ -121,7 +129,8 @@ config VGA_BIOS_ID
- 		|| BOARD_DELL_LATITUDE_E5520 \
- 		|| BOARD_DELL_LATITUDE_E6220 \
- 		|| BOARD_DELL_LATITUDE_E6320
--	default "8086,0166" if BOARD_DELL_LATITUDE_E6430 \
-+	default "8086,0166" if BOARD_DELL_LATITUDE_E6230 \
-+		|| BOARD_DELL_LATITUDE_E6430 \
- 		|| BOARD_DELL_LATITUDE_E6530
- 
- endif
-diff --git a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-index d6fc8eb224..cb7bbd5cdb 100644
---- a/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-+++ b/src/mainboard/dell/snb_ivb_latitude/Kconfig.name
-@@ -21,6 +21,9 @@ config BOARD_DELL_LATITUDE_E6520
- config BOARD_DELL_LATITUDE_E5530
- 	bool "Latitude E5530"
- 
-+config BOARD_DELL_LATITUDE_E6230
-+	bool "Latitude E6230"
-+
- config BOARD_DELL_LATITUDE_E6330
- 	bool "Latitude E6330"
- 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..45ce8f435eea647a0bddaab3fd1e9282c87afc66
-GIT binary patch
-literal 4280
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-z`Kb3Q@LKkANhE_aMG_R&<ewt+nVbp5l*3G7mYJEKr<kXS;TA&^G;5`q5b>;y8g^P<
-zfWO_D2@EyVVBxnpv*}hgTeeRzWz9BoISh>M%^k`WXG=5ti$_Wu99)~lWE-qubeXNk
-zla9Tu=Jhyn5T<3$H#?Hfm-`+(d$7IBDx9cEvNv1i-LEDr>r7438bfkPcKod+mwd22
-z%{^(w&NuG)MKl0fTMTXZFJEm~k;KCj*D60g=j!2jsP)<fOUGaEZa`&xE*)?FZuW#-
-z8!Of7<|N(^R#xcjmZ&nZ%~{pC5y_T*PB2LdDjuI#Te}-4Qccvj+u4N3TBx|oVy*mP
-z<9xfFziy4n?sPv3Sqo7jWMo3>{tzvOjAJ2nB}At~#%f4?FGT+d8LFnXXtYN&Mm06B
-z(JwUPX-z$$(d(M=uBLvh@h6#K=;~&jQo1p&t3TCgSvQ{3)l)jXr5hjW>fd!z!bW>o
-z-4UjJVdJi_dN@o^hK(1(>dRqzCv2PztLMTLjTqY^YEMMJ{=B#1IV)9~IMg|yl(NPF
-zQSfMX`?(b5)))B!zjy0B$ua20CCLTPl^IS&2=T&Zid9-1*K{VAJP?rxjYC+zGDCe*
-ziQI7VfF17@3`3W-qCN>lPC5CL_c?p0F<ekqB;g0q3P1R5KNubPsT>TGXaGB3i~{ZE
-zr=QtIprytDnU7C*Wj%x0k)O{Y%nUnl%}K%F|J_iVaD&ubW4Qbtx;pZEb9}f^Yd;Ea
-zI1Ha{7Yt~z{LAY++1QG{F6*_4WsUziY{x?%I9B}i5-Tphhk8FGm%J<d_0CUoV^%N&
-zTe02j+LXk=ZyWoe7L$#wsEY@VC>f!3d-ysG_9>uk%#)4xpxb+ZkJdel#+h}l9j9`1
-zt*M!5u?i4YtZ+WECo6$LJF06|G-mMZskGiV*lQJf-ItB+hltI<?{5E<^P=0rL<P+g
-z(P)!c<?MlvMK0O~UwZ4*;x|ms(&&#Vn_-4{KM#g~a=;$N2QD7mSX0{t<cf>sId@e&
-z-cN<SWA3VKCN6g3lx#+PySpWu*+pw}>vr(fgI)K*zkikg6TDJi?^}ghc*U*%A%EGg
-Y$$8Z}9a~<{Q@y10T!W`-d%n2+Kj)*Kg#Z8m
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
-new file mode 100644
-index 0000000000..24c1b32467
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/early_init.c
-@@ -0,0 +1,12 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <bootblock_common.h>
-+#include <device/pci_ops.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+#include <southbridge/intel/bd82x6x/pch.h>
-+
-+void bootblock_mainboard_early_init(void)
-+{
-+	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN);
-+	mec5035_early_init();
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
-new file mode 100644
-index 0000000000..c07e4b1c56
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/gpio.c
-@@ -0,0 +1,193 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0 = GPIO_MODE_GPIO,
-+	.gpio1 = GPIO_MODE_GPIO,
-+	.gpio2 = GPIO_MODE_GPIO,
-+	.gpio3 = GPIO_MODE_GPIO,
-+	.gpio4 = GPIO_MODE_GPIO,
-+	.gpio5 = GPIO_MODE_NATIVE,
-+	.gpio6 = GPIO_MODE_GPIO,
-+	.gpio7 = GPIO_MODE_GPIO,
-+	.gpio8 = GPIO_MODE_GPIO,
-+	.gpio9 = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_GPIO,
-+	.gpio16 = GPIO_MODE_GPIO,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_NATIVE,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_NATIVE,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_GPIO,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio0 = GPIO_DIR_INPUT,
-+	.gpio1 = GPIO_DIR_INPUT,
-+	.gpio2 = GPIO_DIR_INPUT,
-+	.gpio3 = GPIO_DIR_INPUT,
-+	.gpio4 = GPIO_DIR_INPUT,
-+	.gpio6 = GPIO_DIR_INPUT,
-+	.gpio7 = GPIO_DIR_INPUT,
-+	.gpio8 = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio15 = GPIO_DIR_INPUT,
-+	.gpio16 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_OUTPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_OUTPUT,
-+	.gpio29 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+	.gpio17 = GPIO_LEVEL_HIGH,
-+	.gpio28 = GPIO_LEVEL_LOW,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_reset = {
-+	.gpio30 = GPIO_RESET_RSMRST,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio0 = GPIO_INVERT,
-+	.gpio8 = GPIO_INVERT,
-+	.gpio13 = GPIO_INVERT,
-+	.gpio14 = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_GPIO,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_GPIO,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_GPIO,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_NATIVE,
-+	.gpio54 = GPIO_MODE_GPIO,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_NATIVE,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+	.gpio61 = GPIO_MODE_NATIVE,
-+	.gpio62 = GPIO_MODE_NATIVE,
-+	.gpio63 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_OUTPUT,
-+	.gpio35 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio45 = GPIO_DIR_OUTPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio51 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio54 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_OUTPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+	.gpio34 = GPIO_LEVEL_HIGH,
-+	.gpio45 = GPIO_LEVEL_LOW,
-+	.gpio60 = GPIO_LEVEL_HIGH,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_reset = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
-+	.gpio64 = GPIO_MODE_NATIVE,
-+	.gpio65 = GPIO_MODE_NATIVE,
-+	.gpio66 = GPIO_MODE_NATIVE,
-+	.gpio67 = GPIO_MODE_NATIVE,
-+	.gpio68 = GPIO_MODE_GPIO,
-+	.gpio69 = GPIO_MODE_GPIO,
-+	.gpio70 = GPIO_MODE_GPIO,
-+	.gpio71 = GPIO_MODE_GPIO,
-+	.gpio72 = GPIO_MODE_NATIVE,
-+	.gpio73 = GPIO_MODE_NATIVE,
-+	.gpio74 = GPIO_MODE_NATIVE,
-+	.gpio75 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
-+	.gpio68 = GPIO_DIR_INPUT,
-+	.gpio69 = GPIO_DIR_INPUT,
-+	.gpio70 = GPIO_DIR_INPUT,
-+	.gpio71 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_level = {
-+};
-+
-+static const struct pch_gpio_set3 pch_gpio_set3_reset = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode		= &pch_gpio_set1_mode,
-+		.direction	= &pch_gpio_set1_direction,
-+		.level		= &pch_gpio_set1_level,
-+		.blink		= &pch_gpio_set1_blink,
-+		.invert		= &pch_gpio_set1_invert,
-+		.reset		= &pch_gpio_set1_reset,
-+	},
-+	.set2 = {
-+		.mode		= &pch_gpio_set2_mode,
-+		.direction	= &pch_gpio_set2_direction,
-+		.level		= &pch_gpio_set2_level,
-+		.reset		= &pch_gpio_set2_reset,
-+	},
-+	.set3 = {
-+		.mode		= &pch_gpio_set3_mode,
-+		.direction	= &pch_gpio_set3_direction,
-+		.level		= &pch_gpio_set3_level,
-+		.reset		= &pch_gpio_set3_reset,
-+	},
-+};
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
-new file mode 100644
-index 0000000000..f6876f9e09
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/hda_verb.c
-@@ -0,0 +1,32 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	0x111d76df, /* Codec Vendor / Device ID: IDT */
-+	0x10280532, /* Subsystem ID */
-+	11, /* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(0, 0x10280532),
-+	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
-+	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
-+	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
-+
-+	0x80862806, /* Codec Vendor / Device ID: Intel */
-+	0x80860101, /* Subsystem ID */
-+	4, /* Number of 4 dword sets */
-+	AZALIA_SUBVENDOR(3, 0x80860101),
-+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
-+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
-+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
-+};
-+
-+const u32 pc_beep_verbs[0] = {};
-+
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
-new file mode 100644
-index 0000000000..3a0fa720da
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/variants/e6230/overridetree.cb
-@@ -0,0 +1,40 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/sandybridge
-+	device domain 0 on
-+		subsystemid 0x1028 0x0532 inherit
-+
-+		device ref igd on
-+			register "gpu_cpu_backlight" = "0x000009e9"
-+			register "gpu_pch_backlight" = "0x13121312"
-+		end
-+
-+		chip southbridge/intel/bd82x6x
-+			register "usb_port_config" = "{
-+				{ 1, 1, 0 },
-+				{ 1, 1, 0 },
-+				{ 1, 0, 1 },
-+				{ 1, 2, 1 },
-+				{ 1, 0, 2 },
-+				{ 1, 0, 2 },
-+				{ 1, 0, 3 },
-+				{ 1, 1, 3 },
-+				{ 1, 2, 4 },
-+				{ 1, 1, 4 },
-+				{ 1, 1, 5 },
-+				{ 1, 1, 5 },
-+				{ 1, 2, 6 },
-+				{ 1, 0, 6 },
-+			}"
-+
-+			device ref xhci on
-+				register "superspeed_capable_ports" = "0x0000000f"
-+				register "xhci_overcurrent_mapping" = "0x00000c03"
-+				register "xhci_switchable_ports" = "0x0000000f"
-+			end
-+			device ref sata1 on
-+				register "sata_port_map" = "0x31"
-+			end
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0018-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch

@@ -1,7 +1,7 @@
-From a5bc59037dabd95b6595c5aaf38b83da2a91de54 Mon Sep 17 00:00:00 2001
+From 2b899f40ce5d728faa7c1da23c3348435b7ac9cb Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Sat, 6 May 2023 15:53:41 -0600
-Subject: [PATCH 06/51] mb/dell/e6400: Enable 01.0 device in devicetree for
+Subject: [PATCH 18/30] mb/dell/e6400: Enable 01.0 device in devicetree for
  dGPU models
 
 Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
@@ -24,5 +24,5 @@ index bb954cbd7b..e9f3915d17 100644
  		device pci 02.1 on end # Display
  		device pci 03.0 on end # ME
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0019-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -1,7 +1,7 @@
-From f883599a362f1383f3712b72516f76187d0a9cbe Mon Sep 17 00:00:00 2001
+From 2ccd3e71730004c3ffbed178087cb778c170079e Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 07/51] Remove warning for coreboot images built without a
+Subject: [PATCH 19/30] Remove warning for coreboot images built without a
  payload
 
 I added this in upstream to prevent people from accidentally flashing
@@ -13,10 +13,10 @@ up. This has caused confusion and concern so just patch it out.
  1 file changed, 1 insertion(+), 12 deletions(-)
 
 diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
-index 5f988dac1b..516133880f 100644
+index a2336aa876..4f1692a873 100644
 --- a/payloads/Makefile.mk
 +++ b/payloads/Makefile.mk
-@@ -50,16 +50,5 @@ distclean-payloads:
+@@ -49,16 +49,5 @@ distclean-payloads:
  print-repo-info-payloads:
  	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
  
@@ -35,5 +35,5 @@ index 5f988dac1b..516133880f 100644
 -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
 +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0020-mb-dell-Add-Latitude-E6430-Ivy-Bridge.patch

@@ -0,0 +1,826 @@
+From a49df0307455d6d8b7a9efb9f4639b72be1b64d4 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sat, 19 Aug 2023 16:19:10 -0600
+Subject: [PATCH 20/30] mb/dell: Add Latitude E6430 (Ivy Bridge)
+
+Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested. This
+is based on the autoport output with some manual tweaks. The flash is
+8MiB + 4MiB, and is fairly easily accessed by removing the keyboard. It
+can also be internally flashed by sending a command to the EC, which
+causes the EC to pull the FDO pin low and the firmware to skip setting
+up any chipset based write protections [1]. The EC is the SMSC MEC5055,
+which seems to be compatible with the existing MEC5035 code.
+
+Working:
+- Libgfxinit
+- USB EHCI debug (left side usb port is HCD index 2, middle port on the
+  right side is HCD index 1)
+- Keyboard
+- Touchpad/trackpoint
+- ExpressCard
+- Audio
+- Ethernet
+- SD card reader
+- mPCIe WiFi
+- SeaBIOS 1.16.2
+- edk2 (MrChromebox' fork, uefipayload_202306)
+- Internal flashing using dell-flash-unlock
+
+Not working:
+- S3 suspend: Possibly EC related
+- Physical wireless switch - this triggers an SMI handler in the vendor
+  firmware which sends commands to the EC to enable/disable wireless
+  devices
+- Battery reporting - needs ACPI code for the EC
+- Brightness hotkeys - probably EC related
+
+Unknown/untested:
+- Dock
+- eSATA
+- TPM
+- dGPU on non-UMA model
+- Bluetooth module (not included on my system)
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6430/Kconfig           |  44 +++++
+ src/mainboard/dell/e6430/Kconfig.name      |   2 +
+ src/mainboard/dell/e6430/Makefile.inc      |   6 +
+ src/mainboard/dell/e6430/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e6430/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e6430/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e6430/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e6430/board_info.txt    |   6 +
+ src/mainboard/dell/e6430/cmos.default      |   9 +
+ src/mainboard/dell/e6430/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e6430/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e6430/devicetree.cb     |  70 ++++++++
+ src/mainboard/dell/e6430/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e6430/early_init.c      |  32 ++++
+ src/mainboard/dell/e6430/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e6430/gpio.c            | 192 +++++++++++++++++++++
+ src/mainboard/dell/e6430/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e6430/mainboard.c       |  21 +++
+ 18 files changed, 593 insertions(+)
+ create mode 100644 src/mainboard/dell/e6430/Kconfig
+ create mode 100644 src/mainboard/dell/e6430/Kconfig.name
+ create mode 100644 src/mainboard/dell/e6430/Makefile.inc
+ create mode 100644 src/mainboard/dell/e6430/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e6430/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e6430/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e6430/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e6430/board_info.txt
+ create mode 100644 src/mainboard/dell/e6430/cmos.default
+ create mode 100644 src/mainboard/dell/e6430/cmos.layout
+ create mode 100644 src/mainboard/dell/e6430/data.vbt
+ create mode 100644 src/mainboard/dell/e6430/devicetree.cb
+ create mode 100644 src/mainboard/dell/e6430/dsdt.asl
+ create mode 100644 src/mainboard/dell/e6430/early_init.c
+ create mode 100644 src/mainboard/dell/e6430/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e6430/gpio.c
+ create mode 100644 src/mainboard/dell/e6430/hda_verb.c
+ create mode 100644 src/mainboard/dell/e6430/mainboard.c
+
+diff --git a/src/mainboard/dell/e6430/Kconfig b/src/mainboard/dell/e6430/Kconfig
+new file mode 100644
+index 0000000000..e4c799803e
+--- /dev/null
++++ b/src/mainboard/dell/e6430/Kconfig
+@@ -0,0 +1,44 @@
++if BOARD_DELL_LATITUDE_E6430
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_12288
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_C216
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e6430"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E6430"
++
++config PS2K_EISAID
++	default "PNP0303"
++
++config PS2M_EISAID
++	default "PNP0F13"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0166"
++
++endif
+diff --git a/src/mainboard/dell/e6430/Kconfig.name b/src/mainboard/dell/e6430/Kconfig.name
+new file mode 100644
+index 0000000000..f866b03585
+--- /dev/null
++++ b/src/mainboard/dell/e6430/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E6430
++	bool "Latitude E6430"
+diff --git a/src/mainboard/dell/e6430/Makefile.inc b/src/mainboard/dell/e6430/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e6430/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6430/acpi/ec.asl b/src/mainboard/dell/e6430/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6430/acpi/platform.asl b/src/mainboard/dell/e6430/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e6430/acpi/superio.asl b/src/mainboard/dell/e6430/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e6430/acpi_tables.c b/src/mainboard/dell/e6430/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e6430/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e6430/board_info.txt b/src/mainboard/dell/e6430/board_info.txt
+new file mode 100644
+index 0000000000..4601a4aaba
+--- /dev/null
++++ b/src/mainboard/dell/e6430/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2012
+diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
+new file mode 100644
+index 0000000000..2a5b30f2b7
+--- /dev/null
++++ b/src/mainboard/dell/e6430/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Normal
+diff --git a/src/mainboard/dell/e6430/cmos.layout b/src/mainboard/dell/e6430/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e6430/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e6430/data.vbt b/src/mainboard/dell/e6430/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..08952c26ab82933ebb5cc5b9c7e2265963a87b2d
+GIT binary patch
+literal 6144
+zcmeHKU2Gdw7XHRFw#VZc+nI!tq)j-qG$b@>#vu)%WW~fb!7ZV6LkJc^+qlG~(WXgp
+zLU)l?#Jhyj)dGqHf<6H13kV^8g;enZDm*~=5kd&@Cn1Fu52*0a2hgri!F%q^IFQ;)
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+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
+new file mode 100644
+index 0000000000..054b01c5ac
+--- /dev/null
++++ b/src/mainboard/dell/e6430/devicetree.cb
+@@ -0,0 +1,70 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00001312"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x0534 inherit
++
++		device ref host_bridge on end
++		device ref peg10 off end
++		device ref igd on end
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x005c0921"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x33"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++			register "superspeed_capable_ports" = "0x0000000f"
++			register "xhci_overcurrent_mapping" = "0x00000c03"
++			register "xhci_switchable_ports" = "0x0000000f"
++
++			device ref xhci		on end
++			device ref mei1		on end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	on end
++			device ref gbe		on end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end # WWAN Slot
++			device ref pcie_rp2	on end # SLAN Slot
++			device ref pcie_rp3	on end # ExpressCard
++			device ref pcie_rp4	on end # E-Module (optical bay)
++			device ref pcie_rp5	on end # Extra Half Mini PCIe slot
++			device ref pcie_rp6	on end # SD/MMC Card Reader
++			device ref pcie_rp7	off end
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1	on end
++			device ref smbus	on end
++			device ref sata2	off end
++			device ref thermal	off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e6430/dsdt.asl b/src/mainboard/dell/e6430/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e6430/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e6430/early_init.c b/src/mainboard/dell/e6430/early_init.c
+new file mode 100644
+index 0000000000..d882c3d78b
+--- /dev/null
++++ b/src/mainboard/dell/e6430/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 0, 2 },
++	{ 1, 1, 2 },
++	{ 1, 1, 3 },
++	{ 1, 1, 3 },
++	{ 1, 1, 4 },
++	{ 1, 1, 4 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 2, 6 },
++	{ 1, 2, 6 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e6430/gma-mainboard.ads b/src/mainboard/dell/e6430/gma-mainboard.ads
+new file mode 100644
+index 0000000000..1310830c8e
+--- /dev/null
++++ b/src/mainboard/dell/e6430/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, --mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e6430/gpio.c b/src/mainboard/dell/e6430/gpio.c
+new file mode 100644
+index 0000000000..777570765a
+--- /dev/null
++++ b/src/mainboard/dell/e6430/gpio.c
+@@ -0,0 +1,192 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_GPIO,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_NATIVE,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio1 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_OUTPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio28 = GPIO_LEVEL_LOW,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++	.gpio30 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio13 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_NATIVE,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_INPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_NATIVE,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e6430/hda_verb.c b/src/mainboard/dell/e6430/hda_verb.c
+new file mode 100644
+index 0000000000..56ada95c58
+--- /dev/null
++++ b/src/mainboard/dell/e6430/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76df,	/* Codec Vendor / Device ID: IDT */
++	0x10280534,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x10280534),
++	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862806,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e6430/mainboard.c b/src/mainboard/dell/e6430/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e6430/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.39.2
+

config/coreboot/default/patches/0021-HACK-Disable-coreboot-related-BL31-features.patch

@@ -1,7 +1,7 @@
-From ec27f5414c78d493ec7be4cd055ac877ce9ea178 Mon Sep 17 00:00:00 2001
+From 70262a5f4bf801814d68f8778ea89b5cd8ef8f9a Mon Sep 17 00:00:00 2001
 From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
 Date: Thu, 22 Jun 2023 16:44:27 +0300
-Subject: [PATCH 18/51] HACK: Disable coreboot related BL31 features
+Subject: [PATCH 21/30] HACK: Disable coreboot related BL31 features
 
 I don't know why, but removing this BL31 make argument lets gru-kevin
 power off properly when shut down from Linux. Needs investigation.
@@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation.
  1 file changed, 3 deletions(-)
 
 diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
-index cb43897efd..a9e5ff399a 100644
+index 538d254ace..18e451d63c 100644
 --- a/src/arch/arm64/Makefile.mk
 +++ b/src/arch/arm64/Makefile.mk
-@@ -173,9 +173,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
+@@ -159,9 +159,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
  # Always enable crash reporting, even on a release build
  BL31_MAKEARGS += CRASH_REPORTING=1
  
@@ -24,5 +24,5 @@ index cb43897efd..a9e5ff399a 100644
  BL31_MAKEARGS += BUILD_PLAT="$(BL31_BUILD)"
  
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0021-nb-intel-haswell-make-IOMMU-a-runtime-option.patch

@@ -1,292 +0,0 @@
-From 4c7577314f19e934d690c4cce3642fe693400c07 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Sat, 2 Mar 2024 22:51:09 +0000
-Subject: [PATCH 21/51] nb/intel/haswell: make IOMMU a runtime option
-
-When I tested graphics cards on a coreboot port for Dell
-OptiPlex 9020 SFF, I could not use a graphics card unless
-I set iommu=off on the Linux cmdline.
-
-Coreboot's current behaviour is to check whether the CPU
-has vt-d support and, if it does, initialise the IOMMU.
-
-This patch maintains the current behaviour by default, but
-allows the user to turn *off* the IOMMU, even if vt-d is
-supported by the host CPU.
-
-If iommu=Disable is specified, the check will not be
-performed, and the IOMMU will be left disabled. This option
-has been added to all current Haswell boards, though it is
-recommended to leave the IOMMU turned on in most setups.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/mainboard/asrock/b85m_pro4/cmos.default    | 1 +
- src/mainboard/asrock/b85m_pro4/cmos.layout     | 3 +++
- src/mainboard/asrock/h81m-hds/cmos.default     | 1 +
- src/mainboard/asrock/h81m-hds/cmos.layout      | 6 ++++++
- src/mainboard/dell/optiplex_9020/cmos.default  | 1 +
- src/mainboard/dell/optiplex_9020/cmos.layout   | 6 ++++++
- src/mainboard/google/beltino/cmos.layout       | 5 +++++
- src/mainboard/google/slippy/cmos.layout        | 5 +++++
- src/mainboard/intel/baskingridge/cmos.layout   | 4 ++++
- src/mainboard/lenovo/haswell/cmos.default      | 1 +
- src/mainboard/lenovo/haswell/cmos.layout       | 3 +++
- src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
- src/mainboard/supermicro/x10slm-f/cmos.layout  | 6 ++++++
- src/northbridge/intel/haswell/early_init.c     | 5 +++++
- 14 files changed, 48 insertions(+)
-
-diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default
-index 01bf20ad16..dfc8b80fb0 100644
---- a/src/mainboard/asrock/b85m_pro4/cmos.default
-+++ b/src/mainboard/asrock/b85m_pro4/cmos.default
-@@ -4,3 +4,4 @@ boot_option=Fallback
- debug_level=Debug
- nmi=Enable
- power_on_after_fail=Disable
-+iommu=Enable
-diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout
-index efdc333fc2..c9883ea71d 100644
---- a/src/mainboard/asrock/b85m_pro4/cmos.layout
-+++ b/src/mainboard/asrock/b85m_pro4/cmos.layout
-@@ -11,6 +11,7 @@
- 	395	4	e	4	debug_level
- 	408	1	e	1	nmi
- 	409	2	e	5	power_on_after_fail
-+	412	1	e	6	iommu
- 	984	16	h	0	check_sum
- # -----------------------------------------------------------------
- 
-@@ -38,6 +39,8 @@
- 	5	0	Disable
- 	5	1	Enable
- 	5	2	Keep
-+	6	0	Disable
-+	6	1	Enable
- # -----------------------------------------------------------------
- 
- # -----------------------------------------------------------------
-diff --git a/src/mainboard/asrock/h81m-hds/cmos.default b/src/mainboard/asrock/h81m-hds/cmos.default
-index 01bf20ad16..dfc8b80fb0 100644
---- a/src/mainboard/asrock/h81m-hds/cmos.default
-+++ b/src/mainboard/asrock/h81m-hds/cmos.default
-@@ -4,3 +4,4 @@ boot_option=Fallback
- debug_level=Debug
- nmi=Enable
- power_on_after_fail=Disable
-+iommu=Enable
-diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout
-index c9ba76c78f..95ee3d36fb 100644
---- a/src/mainboard/asrock/h81m-hds/cmos.layout
-+++ b/src/mainboard/asrock/h81m-hds/cmos.layout
-@@ -21,6 +21,9 @@ entries
- 408	1	e	1	nmi
- 409	2	e	5	power_on_after_fail
- 
-+# enable or disable iommu
-+412	1	e	6	iommu
-+
- # coreboot config options: check sums
- 984	16	h	0	check_sum
- 
-@@ -52,6 +55,9 @@ enumerations
- 5	1	Enable
- 5	2	Keep
- 
-+6	0	Disable
-+6	1	Enable
-+
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
-index 6c4a2a1be7..8000eea8c0 100644
---- a/src/mainboard/dell/optiplex_9020/cmos.default
-+++ b/src/mainboard/dell/optiplex_9020/cmos.default
-@@ -4,3 +4,4 @@ debug_level=Debug
- nmi=Disable
- power_on_after_fail=Disable
- fan_full_speed=Disable
-+iommu=Enable
-diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
-index d10ad95b23..4a1496a878 100644
---- a/src/mainboard/dell/optiplex_9020/cmos.layout
-+++ b/src/mainboard/dell/optiplex_9020/cmos.layout
-@@ -21,6 +21,9 @@ entries
- 408	1	e	1	nmi
- 409	2	e	5	power_on_after_fail
- 
-+# turn iommu on or off
-+411	1	e	6	iommu
-+
- # coreboot config options: EC
- 412	1	e	1	fan_full_speed
- 
-@@ -55,6 +58,9 @@ enumerations
- 5	1	Enable
- 5	2	Keep
- 
-+6	0	Disable
-+6	1	Enable
-+
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout
-index 78d44c1415..c143979ae1 100644
---- a/src/mainboard/google/beltino/cmos.layout
-+++ b/src/mainboard/google/beltino/cmos.layout
-@@ -19,6 +19,9 @@ entries
- 408	1	e	1	nmi
- 409	2	e	7	power_on_after_fail
- 
-+# enable or disable iommu
-+412	1	e	8	iommu
-+
- # coreboot config options: bootloader
- #Used by ChromeOS:
- 416	128	r	0	vbnv
-@@ -47,6 +50,8 @@ enumerations
- 7	0	Disable
- 7	1	Enable
- 7	2	Keep
-+8	0	Disable
-+8	1	Enable
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout
-index 78d44c1415..c143979ae1 100644
---- a/src/mainboard/google/slippy/cmos.layout
-+++ b/src/mainboard/google/slippy/cmos.layout
-@@ -19,6 +19,9 @@ entries
- 408	1	e	1	nmi
- 409	2	e	7	power_on_after_fail
- 
-+# enable or disable iommu
-+412	1	e	8	iommu
-+
- # coreboot config options: bootloader
- #Used by ChromeOS:
- 416	128	r	0	vbnv
-@@ -47,6 +50,8 @@ enumerations
- 7	0	Disable
- 7	1	Enable
- 7	2	Keep
-+8	0	Disable
-+8	1	Enable
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout
-index 78d44c1415..f2c602f541 100644
---- a/src/mainboard/intel/baskingridge/cmos.layout
-+++ b/src/mainboard/intel/baskingridge/cmos.layout
-@@ -19,6 +19,8 @@ entries
- 408	1	e	1	nmi
- 409	2	e	7	power_on_after_fail
- 
-+412	1	e	8	iommu
-+
- # coreboot config options: bootloader
- #Used by ChromeOS:
- 416	128	r	0	vbnv
-@@ -47,6 +49,8 @@ enumerations
- 7	0	Disable
- 7	1	Enable
- 7	2	Keep
-+8	0	Disable
-+8	1	Enable
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/mainboard/lenovo/haswell/cmos.default b/src/mainboard/lenovo/haswell/cmos.default
-index 08db97c5a9..cc6b363cd9 100644
---- a/src/mainboard/lenovo/haswell/cmos.default
-+++ b/src/mainboard/lenovo/haswell/cmos.default
-@@ -14,3 +14,4 @@ trackpoint=Enable
- backlight=Keyboard
- enable_dual_graphics=Disable
- usb_always_on=Disable
-+iommu=Enable
-diff --git a/src/mainboard/lenovo/haswell/cmos.layout b/src/mainboard/lenovo/haswell/cmos.layout
-index 27915d3ab7..59df76b64c 100644
---- a/src/mainboard/lenovo/haswell/cmos.layout
-+++ b/src/mainboard/lenovo/haswell/cmos.layout
-@@ -23,6 +23,7 @@ entries
- 
- # coreboot config options: EC
- 411	1	e	8	first_battery
-+413	1	e	14	iommu
- 415	1	e	1	wlan
- 416	1	e	1	trackpoint
- 417	1	e	1	fn_ctrl_swap
-@@ -72,6 +73,8 @@ enumerations
- 13	0	Disable
- 13	1	AC and battery
- 13	2	AC only
-+14	0	Disable
-+14	1	Enable
- 
- # -----------------------------------------------------------------
- checksums
-diff --git a/src/mainboard/supermicro/x10slm-f/cmos.default b/src/mainboard/supermicro/x10slm-f/cmos.default
-index 7ce38fb5d7..6049e7938a 100644
---- a/src/mainboard/supermicro/x10slm-f/cmos.default
-+++ b/src/mainboard/supermicro/x10slm-f/cmos.default
-@@ -5,3 +5,4 @@ debug_level=Debug
- nmi=Enable
- power_on_after_fail=Keep
- hide_ast2400=Disable
-+iommu=Enable
-diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout
-index 38ba87aa45..24d39e97ee 100644
---- a/src/mainboard/supermicro/x10slm-f/cmos.layout
-+++ b/src/mainboard/supermicro/x10slm-f/cmos.layout
-@@ -21,6 +21,9 @@ entries
- 408	1	e	1	nmi
- 409	2	e	5	power_on_after_fail
- 
-+# enable or disable iommu
-+412	1	e	6	iommu
-+
- # coreboot config options: mainboard
- 416	1	e	1	hide_ast2400
- 
-@@ -55,6 +58,9 @@ enumerations
- 5	1	Enable
- 5	2	Keep
- 
-+6	0	Disable
-+6	1	Enable
-+
- # -----------------------------------------------------------------
- checksums
- 
-diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
-index e47deb5da6..1a7e0b1076 100644
---- a/src/northbridge/intel/haswell/early_init.c
-+++ b/src/northbridge/intel/haswell/early_init.c
-@@ -5,6 +5,7 @@
- #include <device/mmio.h>
- #include <device/pci_def.h>
- #include <device/pci_ops.h>
-+#include <option.h>
- 
- #include "haswell.h"
- 
-@@ -157,6 +158,10 @@ static void haswell_setup_misc(void)
- static void haswell_setup_iommu(void)
- {
- 	const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
-+	u8 enable_iommu = get_uint_option("iommu", 1);
-+
-+	if (!enable_iommu)
-+		return;
- 
- 	if (capid0_a & VTD_DISABLE)
- 		return;
--- 
-2.39.5
-

config/coreboot/default/patches/0022-dell-optiplex_9020-Disable-IOMMU-by-default.patch

@@ -1,29 +0,0 @@
-From b5695d0f0dc44ed1eb1feac008e601040feda55d Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Sat, 2 Mar 2024 23:00:09 +0000
-Subject: [PATCH 22/51] dell/optiplex_9020: Disable IOMMU by default
-
-Needed to make graphics cards work. Turning it on is
-recommended if only using iGPU, otherwise leave it off
-by default. The IOMMU is extremely buggy when a graphics
-card is used. Leaving it off by default will ensure that
-the default ROM images in Libreboot will work on any setup.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/mainboard/dell/optiplex_9020/cmos.default | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
-index 8000eea8c0..0700f971ee 100644
---- a/src/mainboard/dell/optiplex_9020/cmos.default
-+++ b/src/mainboard/dell/optiplex_9020/cmos.default
-@@ -4,4 +4,4 @@ debug_level=Debug
- nmi=Disable
- power_on_after_fail=Disable
- fan_full_speed=Disable
--iommu=Enable
-+iommu=Disable
--- 
-2.39.5
-

config/coreboot/default/patches/0022-don-t-use-github-for-the-acpica-download.patch

@@ -0,0 +1,39 @@
+From 536a1dd349f590cbefccac7e7364cafcdaec9600 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 22 Oct 2023 15:02:25 +0100
+Subject: [PATCH 22/30] don't use github for the acpica download
+
+i have the tarball from a previous download, and i placed
+it on libreboot rsync, which then got mirrored to princeton.
+
+today, github's ssl cert was b0rking the hell out and i really
+really wanted to finish a build, and didn't want to wait for
+github to fix their httpd.
+
+so i'm now hosting this specific acpica tarball on rsync.
+
+this patch makes that URL be used, instead of the github one.
+
+that's the 2nd time i've had to patch coreboot's acpica download!
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 23a5caf2bb..36565a906c 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+ GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+ BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
++IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+ CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/default/patches/0023-crank-up-vram-allocation-on-more-intel-boards.patch

@@ -0,0 +1,142 @@
+From ad812d008d570c1655bff13a9026f39a9efdcbc9 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Tue, 31 Oct 2023 18:24:39 +0000
+Subject: [PATCH 23/30] crank up vram allocation on more intel boards
+
+these were added to libreboot, and it's a policy of
+libreboot to max out the vram settings. this was
+overlooked, in prior revisions and releases.
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/dell/e6400/cmos.default                | 2 +-
+ src/mainboard/dell/snb_ivb_workstations/cmos.default | 2 +-
+ src/mainboard/hp/compaq_8200_elite_sff/cmos.default  | 2 +-
+ src/mainboard/hp/compaq_elite_8300_usdt/cmos.default | 2 +-
+ src/mainboard/hp/snb_ivb_laptops/cmos.default        | 1 +
+ src/mainboard/lenovo/t420/cmos.default               | 1 +
+ src/mainboard/lenovo/t420s/cmos.default              | 1 +
+ src/mainboard/lenovo/t430/cmos.default               | 1 +
+ src/mainboard/lenovo/t520/cmos.default               | 1 +
+ src/mainboard/lenovo/t530/cmos.default               | 1 +
+ src/mainboard/lenovo/x201/cmos.default               | 1 +
+ src/mainboard/lenovo/x220/cmos.default               | 1 +
+ 12 files changed, 12 insertions(+), 4 deletions(-)
+
+diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
+index eeb6f47364..25dfa38cb5 100644
+--- a/src/mainboard/dell/e6400/cmos.default
++++ b/src/mainboard/dell/e6400/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Disable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=256M
+diff --git a/src/mainboard/dell/snb_ivb_workstations/cmos.default b/src/mainboard/dell/snb_ivb_workstations/cmos.default
+index ccc7e64625..7c97b84baf 100644
+--- a/src/mainboard/dell/snb_ivb_workstations/cmos.default
++++ b/src/mainboard/dell/snb_ivb_workstations/cmos.default
+@@ -3,5 +3,5 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=128M
++gfx_uma_size=224M
+ fan_full_speed=Disable
+diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+index 6d27a79c66..4517ffc7c2 100644
+--- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
++++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.default
+@@ -3,5 +3,5 @@ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=224M
+ psu_fan_lvl=3
+diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+index 6f3cec735e..9fc4db2990 100644
+--- a/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
++++ b/src/mainboard/hp/compaq_elite_8300_usdt/cmos.default
+@@ -3,4 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Enable
+ nmi=Enable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=224M
+diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.default b/src/mainboard/hp/snb_ivb_laptops/cmos.default
+index ad822d5043..89418a4cfc 100644
+--- a/src/mainboard/hp/snb_ivb_laptops/cmos.default
++++ b/src/mainboard/hp/snb_ivb_laptops/cmos.default
+@@ -3,3 +3,4 @@ debug_level=Debug
+ power_on_after_fail=Disable
+ nmi=Enable
+ sata_mode=AHCI
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
+index c011867916..83f590d39d 100644
+--- a/src/mainboard/lenovo/t420/cmos.default
++++ b/src/mainboard/lenovo/t420/cmos.default
+@@ -15,3 +15,4 @@ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
+index c011867916..83f590d39d 100644
+--- a/src/mainboard/lenovo/t420s/cmos.default
++++ b/src/mainboard/lenovo/t420s/cmos.default
+@@ -15,3 +15,4 @@ trackpoint=Enable
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
+index 55e1e6c04e..a72108f47e 100644
+--- a/src/mainboard/lenovo/t430/cmos.default
++++ b/src/mainboard/lenovo/t430/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ usb_always_on=Disable
+ hybrid_graphics_mode=Integrated Only
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
+index b66f7034dc..a73ea6e9ee 100644
+--- a/src/mainboard/lenovo/t520/cmos.default
++++ b/src/mainboard/lenovo/t520/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
+index b66f7034dc..a73ea6e9ee 100644
+--- a/src/mainboard/lenovo/t530/cmos.default
++++ b/src/mainboard/lenovo/t530/cmos.default
+@@ -16,3 +16,4 @@ backlight=Both
+ hybrid_graphics_mode=Integrated Only
+ usb_always_on=Disable
+ me_state=Disabled
++gfx_uma_size=224M
+diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default
+index 2cf484fd5a..46294d91ca 100644
+--- a/src/mainboard/lenovo/x201/cmos.default
++++ b/src/mainboard/lenovo/x201/cmos.default
+@@ -15,3 +15,4 @@ power_management_beeps=Enable
+ low_battery_beep=Enable
+ sata_mode=AHCI
+ usb_always_on=Disable
++gfx_uma_size=128M
+diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
+index 52f303dfdb..92a2026542 100644
+--- a/src/mainboard/lenovo/x220/cmos.default
++++ b/src/mainboard/lenovo/x220/cmos.default
+@@ -14,3 +14,4 @@ fn_ctrl_swap=Disable
+ sticky_fn=Disable
+ trackpoint=Enable
+ me_state=Disabled
++gfx_uma_size=224M
+-- 
+2.39.2
+

config/coreboot/default/patches/0023-nb-haswell-Fully-disable-iGPU-when-dGPU-is-used.patch

@@ -1,51 +0,0 @@
-From d86824305f11bc684f1e91e3826158b8c7d7e0ee Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Sat, 6 Apr 2024 01:22:47 +0100
-Subject: [PATCH 23/51] nb/haswell: Fully disable iGPU when dGPU is used
-
-My earlier patch disabled decode *and* disabled the iGPU itself, but
-a subsequent revision disabled only VGA decode. Upon revisiting, I
-found that, actually, yes, you also need to disable the iGPU entirely.
-
-Tested on Dell 9020 SFF using broadwell MRC, with both iGPU and dGPU.
-With this patch, the iGPU is completely disabled when you install a
-graphics card, but the iGPU is available to use when no graphics card
-is present.
-
-For more context, see:
-
-Author: Leah Rowe <info@minifree.org>
-Date:   Fri Feb 23 13:33:31 2024 +0000
-
-    nb/haswell: Disable iGPU when dGPU is used
-
-And look at the Gerrit comments:
-
-https://review.coreboot.org/c/coreboot/+/80717/
-
-So, my original submission on change 80717 was actually correct.
-This patch fixes the issue. I tested on iGPU and dGPU, with both
-broadwell and haswell mrc.bin.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/northbridge/intel/haswell/gma.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
-index f7fad3183d..1b188e92e1 100644
---- a/src/northbridge/intel/haswell/gma.c
-+++ b/src/northbridge/intel/haswell/gma.c
-@@ -466,6 +466,9 @@ static void gma_func0_disable(struct device *dev)
- {
- 	/* Disable VGA decode */
- 	pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
-+
-+	/* Required or else the graphics card doesn't work */
-+	dev->enabled = 0;
- }
- 
- static struct device_operations gma_func0_ops = {
--- 
-2.39.5
-

config/coreboot/default/patches/0024-dell-e6430-use-ME-Soft-Temporary-Disable.patch

@@ -1,7 +1,7 @@
-From a15b59616e00c43c05d7853080859d4aefe26c5d Mon Sep 17 00:00:00 2001
+From a9ab864aee1be7a03926443ddc94e4c5012719ba Mon Sep 17 00:00:00 2001
 From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 5 Nov 2023 11:41:41 +0000
-Subject: [PATCH 19/51] dell/e6430: use ME Soft Temporary Disable
+Subject: [PATCH 24/30] dell/e6430: use ME Soft Temporary Disable
 
 i overlooked this. it's set on other boards.
 
@@ -12,13 +12,13 @@ disablement, to absolutely ensure Intel ME is not alive
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
- src/mainboard/dell/snb_ivb_latitude/cmos.default | 2 +-
+ src/mainboard/dell/e6430/cmos.default | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
-diff --git a/src/mainboard/dell/snb_ivb_latitude/cmos.default b/src/mainboard/dell/snb_ivb_latitude/cmos.default
+diff --git a/src/mainboard/dell/e6430/cmos.default b/src/mainboard/dell/e6430/cmos.default
 index 2a5b30f2b7..279415dfd1 100644
---- a/src/mainboard/dell/snb_ivb_latitude/cmos.default
+--- a/src/mainboard/dell/e6430/cmos.default
-+++ b/src/mainboard/dell/snb_ivb_latitude/cmos.default
++++ b/src/mainboard/dell/e6430/cmos.default
 @@ -6,4 +6,4 @@ bluetooth=Enable
  wwan=Enable
  wlan=Enable
@@ -26,5 +26,5 @@ index 2a5b30f2b7..279415dfd1 100644
 -me_state=Normal
 +me_state=Disabled
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0024-ec-dell-mec5035-Replace-defines-with-enums.patch

@@ -1,91 +0,0 @@
-From a1566875789469ebd91e472301be4b359aac0a4c Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Tue, 28 May 2024 17:23:21 -0600
-Subject: [PATCH 24/51] ec/dell/mec5035: Replace defines with enums
-
-Instead of using defines for command IDs and argument values, use enums
-to provide more type safety. This also has the effect of moving the
-command IDs to a more central location instead of defines spread out
-throughout the header.
-
-Change-Id: I788531e8b70e79541213853f177326d217235ef2
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
-Reviewed-on: https://review.coreboot.org/c/coreboot/+/82998
-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
-Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
----
- src/ec/dell/mec5035/mec5035.c | 10 +++++-----
- src/ec/dell/mec5035/mec5035.h | 20 ++++++++++++--------
- 2 files changed, 17 insertions(+), 13 deletions(-)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 68b6b2f7fb..dffbb7960c 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -66,17 +66,17 @@ static enum cb_err write_mailbox_regs(const u8 *data, u8 start, u8 count)
- 	return CB_SUCCESS;
- }
- 
--static void ec_command(u8 cmd)
-+static void ec_command(enum mec5035_cmd cmd)
- {
- 	outb(0, MAILBOX_INDEX);
--	outb(cmd, MAILBOX_DATA);
-+	outb((u8)cmd, MAILBOX_DATA);
- 	wait_ec();
- }
- 
--u8 mec5035_mouse_touchpad(u8 setting)
-+u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting)
- {
--	u8 buf[15] = {0};
--	write_mailbox_regs(&setting, 2, 1);
-+	u8 buf[15] = {(u8)setting};
-+	write_mailbox_regs(buf, 2, 1);
- 	ec_command(CMD_MOUSE_TP);
- 	/* The vendor firmware reads 15 bytes starting at index 1, presumably
- 	   to get some sort of return code. Though I don't know for sure if
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index fa15a9d621..32f791cb01 100644
---- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -7,16 +7,20 @@
- 
- #define NUM_REGISTERS	32
- 
-+enum mec5035_cmd {
-+	CMD_MOUSE_TP = 0x1a,
-+	CMD_RADIO_CTRL = 0x2b,
-+	CMD_CPU_OK = 0xc2,
-+};
-+
- /* Touchpad (TP) and mouse related. The EC seems to
-    default to 0 which results in the TP not working. */
--#define CMD_MOUSE_TP	0x1a
--#define SERIAL_MOUSE	0 /* Disable TP, force use of a serial mouse */
--#define PS2_MOUSE	1 /* Disable TP when using a PS/2 mouse */
--#define TP_PS2_MOUSE	2 /* Leave TP enabled when using a PS/2 mouse */
--
--#define CMD_CPU_OK	0xc2
-+enum ec_mouse_setting {
-+	SERIAL_MOUSE = 0, /* Disable TP, force use of a serial mouse */
-+	PS2_MOUSE, /* Disable TP when using a PS/2 mouse */
-+	TP_PS2_MOUSE /* Leave TP enabled when using a PS/2 mouse */
-+};
- 
--#define CMD_RADIO_CTRL 0x2b
- #define RADIO_CTRL_NUM_ARGS 3
- enum ec_radio_dev {
- 	RADIO_WLAN = 0,
-@@ -29,7 +33,7 @@ enum ec_radio_state {
- 	RADIO_ON
- };
- 
--u8 mec5035_mouse_touchpad(u8 setting);
-+u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
- void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
--- 
-2.39.5
-

config/coreboot/default/patches/0025-ec-dell-mec5035-Add-S3-suspend-SMI-handler.patch

@@ -1,147 +0,0 @@
-From 2fdd5bbb2bbec76c3c2238c4cd471b9b63073942 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 3 May 2024 11:03:32 -0600
-Subject: [PATCH 25/51] ec/dell/mec5035: Add S3 suspend SMI handler
-
-This is necessary for S3 resume to work on SNB and newer Dell Latitude
-laptops. If a command isn't sent, the EC cuts power to the DIMMs,
-preventing the system from resuming. These commands were found using an
-FPGA to log all LPC bus transactions between the host and the EC and
-then narrowing down which ones were actually necessary.
-
-Interestingly, the command IDs appear to be identical to those in
-ec/google/wilco, the EC used on Dell Latitude Chromebooks, and that EC
-implements a similar S3 SMI handler as the one implemented in this
-commit. The Wilco EC Kconfig does suggest that its firmware is a
-modified version of Dell's usual Latitude EC firmware, so the
-similarities seem to be intentional.
-
-These similarities also identified a command to enable or disable wake
-sources like the power button and lid switch, and this was added to the
-SMI handler to disable lid wake as the system does not yet resume
-properly from a like wake with coreboot.
-
-Tested on the Latitude E6430 (Ivy Bridge) and the Precision M6800
-(Haswell, not yet pushed).
-
-Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/Makefile.mk  |  1 +
- src/ec/dell/mec5035/mec5035.c    | 14 ++++++++++++++
- src/ec/dell/mec5035/mec5035.h    | 22 ++++++++++++++++++++++
- src/ec/dell/mec5035/smihandler.c | 17 +++++++++++++++++
- 4 files changed, 54 insertions(+)
- create mode 100644 src/ec/dell/mec5035/smihandler.c
-
-diff --git a/src/ec/dell/mec5035/Makefile.mk b/src/ec/dell/mec5035/Makefile.mk
-index 4ebdd811f9..be557e4599 100644
---- a/src/ec/dell/mec5035/Makefile.mk
-+++ b/src/ec/dell/mec5035/Makefile.mk
-@@ -5,5 +5,6 @@ ifeq ($(CONFIG_EC_DELL_MEC5035),y)
- bootblock-y += mec5035.c
- romstage-y += mec5035.c
- ramstage-y += mec5035.c
-+smm-y += mec5035.c smihandler.c
- 
- endif
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index dffbb7960c..85c2ab0140 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -94,6 +94,20 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
- 	ec_command(CMD_RADIO_CTRL);
- }
- 
-+void mec5035_change_wake(u8 source, enum ec_wake_change change)
-+{
-+	u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
-+	write_mailbox_regs(buf, 2, ACPI_WAKEUP_NUM_ARGS);
-+	ec_command(CMD_ACPI_WAKEUP_CHANGE);
-+}
-+
-+void mec5035_sleep_enable(void)
-+{
-+	u8 buf[SLEEP_EN_NUM_ARGS] = {3, 0};
-+	write_mailbox_regs(buf, 2, SLEEP_EN_NUM_ARGS);
-+	ec_command(CMD_SLEEP_ENABLE);
-+}
-+
- void mec5035_early_init(void)
- {
- 	/* If this isn't sent the EC shuts down the system after about 15
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index 32f791cb01..8d4fded28b 100644
---- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -4,12 +4,15 @@
- #define _EC_DELL_MEC5035_H_
- 
- #include <stdint.h>
-+#include <types.h>
- 
- #define NUM_REGISTERS	32
- 
- enum mec5035_cmd {
- 	CMD_MOUSE_TP = 0x1a,
- 	CMD_RADIO_CTRL = 0x2b,
-+	CMD_ACPI_WAKEUP_CHANGE = 0x4a,
-+	CMD_SLEEP_ENABLE = 0x64,
- 	CMD_CPU_OK = 0xc2,
- };
- 
-@@ -33,9 +36,28 @@ enum ec_radio_state {
- 	RADIO_ON
- };
- 
-+#define ACPI_WAKEUP_NUM_ARGS 4
-+enum ec_wake_change {
-+	WAKE_OFF = 0,
-+	WAKE_ON
-+};
-+
-+/* Copied from ec/google/wilco/commands.h. Not sure if these all apply */
-+enum ec_acpi_wake_events {
-+	EC_ACPI_WAKE_PWRB = BIT(0),     /* Wake up by power button */
-+	EC_ACPI_WAKE_LID = BIT(1),      /* Wake up by lid switch */
-+	EC_ACPI_WAKE_RTC = BIT(5),      /* Wake up by RTC */
-+};
-+
-+#define SLEEP_EN_NUM_ARGS 2
-+
- u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
- void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
-+void mec5035_change_wake(u8 source, enum ec_wake_change change);
-+void mec5035_sleep_enable(void);
-+
-+void mec5035_smi_sleep(int slp_type);
- 
- #endif /* _EC_DELL_MEC5035_H_ */
-diff --git a/src/ec/dell/mec5035/smihandler.c b/src/ec/dell/mec5035/smihandler.c
-new file mode 100644
-index 0000000000..958733bf97
---- /dev/null
-+++ b/src/ec/dell/mec5035/smihandler.c
-@@ -0,0 +1,17 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <acpi/acpi.h>
-+#include <console/console.h>
-+#include <ec/acpi/ec.h>
-+#include "mec5035.h"
-+
-+void mec5035_smi_sleep(int slp_type)
-+{
-+	switch (slp_type) {
-+	case ACPI_S3:
-+		/* System does not yet resume properly if woken by lid */
-+		mec5035_change_wake(EC_ACPI_WAKE_LID, WAKE_OFF);
-+		mec5035_sleep_enable();
-+		break;
-+	}
-+}
--- 
-2.39.5
-

config/coreboot/default/patches/0025-use-mirrorservice.org-for-gcc-downloads.patch

@@ -0,0 +1,36 @@
+From 936a8f113772c93d7501e7133159ab4e23436222 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 5 Nov 2023 22:57:08 +0000
+Subject: [PATCH 25/30] use mirrorservice.org for gcc downloads
+
+the gnu.org 302 redirect often fails
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 36565a906c..4d4ca06113 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
+ # to the jenkins build as well, or the builder won't download it.
+ 
+ # GCC toolchain archive locations
+-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
+-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
+ IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/default/patches/0026-mb-dell-Add-Latitude-E6530-Ivy-Bridge.patch

@@ -0,0 +1,792 @@
+From 973783a989cdcb7b77029e369156c81eefe8cc67 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sat, 19 Aug 2023 16:19:10 -0600
+Subject: [PATCH 26/30] mb/dell: Add Latitude E6530 (Ivy Bridge)
+
+Mainboard is QALA0/LA-7761P (UMA). The dGPU model was not tested.  This
+is based on the autoport output with some manual tweaks. The flash is
+8MiB + 4MiB. It can be internally flashed by sending a command to the
+EC, which causes the EC to pull the FDO pin low and the firmware to skip
+setting up any chipset based write protections. [1] The EC is the SMSC
+MEC5055, which seems to be compatible with the existing MEC5035 code.
+
+[1] https://gitlab.com/nic3-14159/dell-flash-unlock
+
+Change-Id: I93c6622fc5da1d0d61a5b2c197ac7227d9525908
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6530/Kconfig           |  37 ++++
+ src/mainboard/dell/e6530/Kconfig.name      |   2 +
+ src/mainboard/dell/e6530/Makefile.inc      |   6 +
+ src/mainboard/dell/e6530/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e6530/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e6530/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e6530/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e6530/board_info.txt    |   6 +
+ src/mainboard/dell/e6530/cmos.default      |   9 +
+ src/mainboard/dell/e6530/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e6530/data.vbt          | Bin 0 -> 4280 bytes
+ src/mainboard/dell/e6530/devicetree.cb     |  68 ++++++++
+ src/mainboard/dell/e6530/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e6530/early_init.c      |  38 ++++
+ src/mainboard/dell/e6530/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e6530/gpio.c            | 192 +++++++++++++++++++++
+ src/mainboard/dell/e6530/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e6530/mainboard.c       |  21 +++
+ 18 files changed, 590 insertions(+)
+ create mode 100644 src/mainboard/dell/e6530/Kconfig
+ create mode 100644 src/mainboard/dell/e6530/Kconfig.name
+ create mode 100644 src/mainboard/dell/e6530/Makefile.inc
+ create mode 100644 src/mainboard/dell/e6530/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e6530/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e6530/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e6530/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e6530/board_info.txt
+ create mode 100644 src/mainboard/dell/e6530/cmos.default
+ create mode 100644 src/mainboard/dell/e6530/cmos.layout
+ create mode 100644 src/mainboard/dell/e6530/data.vbt
+ create mode 100644 src/mainboard/dell/e6530/devicetree.cb
+ create mode 100644 src/mainboard/dell/e6530/dsdt.asl
+ create mode 100644 src/mainboard/dell/e6530/early_init.c
+ create mode 100644 src/mainboard/dell/e6530/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e6530/gpio.c
+ create mode 100644 src/mainboard/dell/e6530/hda_verb.c
+ create mode 100644 src/mainboard/dell/e6530/mainboard.c
+
+diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
+new file mode 100644
+index 0000000000..582adddbd4
+--- /dev/null
++++ b/src/mainboard/dell/e6530/Kconfig
+@@ -0,0 +1,37 @@
++if BOARD_DELL_LATITUDE_E6530
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_12288
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_C216
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config MAINBOARD_DIR
++	default "dell/e6530"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E6530"
++
++config VGA_BIOS_ID
++	default "8086,0166"
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config USBDEBUG_HCD_INDEX
++	default 2
++endif
+diff --git a/src/mainboard/dell/e6530/Kconfig.name b/src/mainboard/dell/e6530/Kconfig.name
+new file mode 100644
+index 0000000000..01ed76d107
+--- /dev/null
++++ b/src/mainboard/dell/e6530/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E6530
++	bool "Latitude E6530"
+diff --git a/src/mainboard/dell/e6530/Makefile.inc b/src/mainboard/dell/e6530/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e6530/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6530/acpi/ec.asl b/src/mainboard/dell/e6530/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6530/acpi/platform.asl b/src/mainboard/dell/e6530/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e6530/acpi/superio.asl b/src/mainboard/dell/e6530/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e6530/acpi_tables.c b/src/mainboard/dell/e6530/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e6530/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e6530/board_info.txt b/src/mainboard/dell/e6530/board_info.txt
+new file mode 100644
+index 0000000000..4601a4aaba
+--- /dev/null
++++ b/src/mainboard/dell/e6530/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2012
+diff --git a/src/mainboard/dell/e6530/cmos.default b/src/mainboard/dell/e6530/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e6530/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
+new file mode 100644
+index 0000000000..e85ea4c661
+--- /dev/null
++++ b/src/mainboard/dell/e6530/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++415	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e6530/data.vbt b/src/mainboard/dell/e6530/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..af64a913d521fe240ce30e114e90fe75d3841bbc
+GIT binary patch
+literal 4280
+zcmdT{U2GiH75-*te`aTAcGqJQY$rA+e`ZbWcy_TDH@NC}cbl$*NjAn^RtPm->J7GV
+zY_m3jN`RN*h9FvG3Do9+qP$c^s1;PLB3@br9>Ag%La5?TLP`-2DDaR65U2_)=g!QU
+zIJ+cPr4+cc-@WIad+wQY&YW{+c1J!nPPgn&^^N3Hy*D37jg0=7CSl@*=mXr>x75gi
+zTMlK0$A=H4Mh~QKqCa92jz_;d3rtFqp(o-4gCnzxrJ2}Rw@^!haWp<ahv&+aDb5_3
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+zaj`t-?uy6zsjzp<-IdM6g(XhQX2iF<+p?Kmw6?a+f^VMex*PuetNfqf+4_FpD%8TW
+eZvUbDHC^NLu5~gtzg|!EqSkX2ep9pg!tpEeo1jDh
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
+new file mode 100644
+index 0000000000..96eed178c5
+--- /dev/null
++++ b/src/mainboard/dell/e6530/devicetree.cb
+@@ -0,0 +1,68 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00000251"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x0535 inherit
++
++		device ref host_bridge on end # Host bridge
++		device ref peg10 off end # PEG
++		device ref igd on end # iGPU
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x005c0921"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x007c0901"
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x33"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++			register "superspeed_capable_ports" = "0x0000000f"
++			register "xhci_overcurrent_mapping" = "0x00000c03"
++			register "xhci_switchable_ports" = "0x0000000f"
++
++			device ref xhci		on end # USB 3.0 Controller
++			device ref mei1		off end # Management Engine Interface 1
++			device ref mei2		off end # Management Engine Interface 2
++			device ref me_ide_r	off end # Management Engine IDE-R
++			device ref me_kt	on end # Management Engine KT
++			device ref gbe		on end # Intel Gigabit Ethernet
++			device ref ehci2	on end # USB2 EHCI #2
++			device ref hda		on end # High Definition Audio
++			device ref pcie_rp1	on end # PCIe Port #1
++			device ref pcie_rp2	on end # PCIe Port #2
++			device ref pcie_rp3	on end # PCIe Port #3
++			device ref pcie_rp4	on end # PCIe Port #4
++			device ref pcie_rp5	off end # PCIe Port #5
++			device ref pcie_rp6	on end # PCIe Port #6
++			device ref pcie_rp7	off end # PCIe Port #7
++			device ref pcie_rp8	off end # PCIe Port #8
++			device ref ehci1	on end # USB2 EHCI #1
++			device ref pci_bridge	off end # PCI bridge
++			device ref lpc		on # LPC bridge
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1	on end # SATA Controller 1
++			device ref smbus	on end # SMBus
++			device ref sata2	off end # SATA Controller 2
++			device ref thermal	off end # Thermal
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e6530/dsdt.asl b/src/mainboard/dell/e6530/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e6530/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
+new file mode 100644
+index 0000000000..d57f48e7f1
+--- /dev/null
++++ b/src/mainboard/dell/e6530/early_init.c
+@@ -0,0 +1,38 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <northbridge/intel/sandybridge/raminit_native.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 1, 2 },
++	{ 1, 1, 2 },
++	{ 1, 0, 3 },
++	{ 1, 1, 3 },
++	{ 1, 1, 4 },
++	{ 1, 1, 4 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 2, 6 },
++	{ 1, 2, 6 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
++	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
++	mec5035_early_init();
++}
++
++void mainboard_get_spd(spd_raw_data *spd, bool id_only)
++{
++	read_spd(&spd[0], 0x50, id_only);
++	read_spd(&spd[2], 0x52, id_only);
++}
+diff --git a/src/mainboard/dell/e6530/gma-mainboard.ads b/src/mainboard/dell/e6530/gma-mainboard.ads
+new file mode 100644
+index 0000000000..1310830c8e
+--- /dev/null
++++ b/src/mainboard/dell/e6530/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, --mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e6530/gpio.c b/src/mainboard/dell/e6530/gpio.c
+new file mode 100644
+index 0000000000..777570765a
+--- /dev/null
++++ b/src/mainboard/dell/e6530/gpio.c
+@@ -0,0 +1,192 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_GPIO,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_NATIVE,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio1 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_OUTPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio28 = GPIO_LEVEL_LOW,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++	.gpio30 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio13 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_NATIVE,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_INPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_NATIVE,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e6530/hda_verb.c b/src/mainboard/dell/e6530/hda_verb.c
+new file mode 100644
+index 0000000000..9de7e34311
+--- /dev/null
++++ b/src/mainboard/dell/e6530/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76df,	/* Codec Vendor / Device ID: IDT */
++	0x10280535,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x10280535),
++	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862806,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e6530/mainboard.c b/src/mainboard/dell/e6530/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e6530/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.39.2
+

config/coreboot/default/patches/0026-nb-haswell-lock-policy-regs-when-disabling-IOMMU.patch

@@ -1,55 +0,0 @@
-From ce7d65790b9b8656ebbaa0ca715adff6a9c25588 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Sat, 4 May 2024 02:00:53 +0100
-Subject: [PATCH 26/51] nb/haswell: lock policy regs when disabling IOMMU
-
-Angel Pons told me I should do it. See comments here:
-https://review.coreboot.org/c/coreboot/+/81016
-
-I see no harm in complying with the request. I'll merge
-this into the main patch at a later date and try to
-get this upstreamed.
-
-Just a reminder: on Optiplex 9020 variants, Xorg locks up
-under Linux when tested with a graphics card; disabling
-IOMMU works around the issue. Intel graphics work just fine
-with IOMMU turned on. Libreboot disables IOMMU by default,
-on the 9020, so that users can install graphics cards easily.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/northbridge/intel/haswell/early_init.c | 15 +++++++--------
- 1 file changed, 7 insertions(+), 8 deletions(-)
-
-diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
-index 1a7e0b1076..e9506ee830 100644
---- a/src/northbridge/intel/haswell/early_init.c
-+++ b/src/northbridge/intel/haswell/early_init.c
-@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void)
- 	const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
- 	u8 enable_iommu = get_uint_option("iommu", 1);
- 
--	if (!enable_iommu)
--		return;
--
- 	if (capid0_a & VTD_DISABLE)
- 		return;
- 
--	/* Setup BARs: zeroize top 32 bits; set enable bit */
--	mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
--	mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
--	mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
--	mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
-+	if (enable_iommu) {
-+		/* Setup BARs: zeroize top 32 bits; set enable bit */
-+		mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
-+		mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
-+		mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
-+		mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
-+	}
- 
- 	/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
- 	u32 reg32;
--- 
-2.39.5
-

config/coreboot/default/patches/0027-rebase-dell-e6530-to-newer-coreboot-code.patch

@@ -0,0 +1,145 @@
+From 88652afd52b0a8e0fc8bb1656e59d8ae4796d847 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Thu, 25 Jan 2024 14:30:03 +0000
+Subject: [PATCH 27/30] rebase dell/e6530 to newer coreboot code
+
+i diffed nicholas's current e6430 patch, versus the old one,
+prior to this revision update in lbmk, also cross referencing
+the original e6430 and e6530 patches, diffing them, and the
+result in this patch. most notably, spd data is now defined in
+the devicetree, instead of early_init.c as per:
+
+commit 45e4ab4a660cb7ce312f2d11a153f2d9ef4158da
+Author: Keith Hui <buurin@gmail.com>
+Date:   Sat Jul 22 12:49:05 2023 -0400
+    mb/*: Update SPD mapping for sandybridge boards
+
+This should work fine. Will test after this builds.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/mainboard/dell/e6530/Kconfig       | 15 +++++++++++----
+ src/mainboard/dell/e6530/cmos.layout   |  2 +-
+ src/mainboard/dell/e6530/devicetree.cb |  8 +++++---
+ src/mainboard/dell/e6530/early_init.c  | 12 +++---------
+ 4 files changed, 20 insertions(+), 17 deletions(-)
+
+diff --git a/src/mainboard/dell/e6530/Kconfig b/src/mainboard/dell/e6530/Kconfig
+index 582adddbd4..a104566890 100644
+--- a/src/mainboard/dell/e6530/Kconfig
++++ b/src/mainboard/dell/e6530/Kconfig
+@@ -20,18 +20,25 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select SYSTEM_TYPE_LAPTOP
+ 	select USE_NATIVE_RAMINIT
+ 
++config DRAM_RESET_GATE_GPIO
++	default 60
++
+ config MAINBOARD_DIR
+ 	default "dell/e6530"
+ 
+ config MAINBOARD_PART_NUMBER
+ 	default "Latitude E6530"
+ 
+-config VGA_BIOS_ID
+-	default "8086,0166"
++config PS2K_EISAID
++	default "PNP0303"
+ 
+-config DRAM_RESET_GATE_GPIO
+-	default 60
++config PS2M_EISAID
++	default "PNP0F13"
+ 
+ config USBDEBUG_HCD_INDEX
+ 	default 2
++
++config VGA_BIOS_ID
++	default "8086,0166"
++
+ endif
+diff --git a/src/mainboard/dell/e6530/cmos.layout b/src/mainboard/dell/e6530/cmos.layout
+index e85ea4c661..1aa7e77bce 100644
+--- a/src/mainboard/dell/e6530/cmos.layout
++++ b/src/mainboard/dell/e6530/cmos.layout
+@@ -25,7 +25,7 @@ entries
+ # coreboot config options: EC
+ 412	1	e	1	bluetooth
+ 413	1	e	1	wwan
+-415	1	e	1	wlan
++414	1	e	1	wlan
+ 
+ # coreboot config options: ME
+ 424	1	e	14	me_state
+diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
+index 96eed178c5..37135bcf0f 100644
+--- a/src/mainboard/dell/e6530/devicetree.cb
++++ b/src/mainboard/dell/e6530/devicetree.cb
+@@ -12,6 +12,8 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 	register "gpu_panel_power_up_delay" = "400"
+ 	register "gpu_pch_backlight" = "0x13121312"
+ 
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
+ 	device domain 0x0 on
+ 		subsystemid 0x1028 0x0535 inherit
+ 
+@@ -24,7 +26,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 			register "gen1_dec" = "0x007c0681"
+ 			register "gen2_dec" = "0x005c0921"
+ 			register "gen3_dec" = "0x003c07e1"
+-			register "gen4_dec" = "0x007c0901"
++			register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
+ 			register "gpi0_routing" = "2"
+ 			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
+ 			register "pcie_port_coalesce" = "1"
+@@ -37,7 +39,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 			register "xhci_switchable_ports" = "0x0000000f"
+ 
+ 			device ref xhci		on end # USB 3.0 Controller
+-			device ref mei1		off end # Management Engine Interface 1
++			device ref mei1		on end # Management Engine Interface 1
+ 			device ref mei2		off end # Management Engine Interface 2
+ 			device ref me_ide_r	off end # Management Engine IDE-R
+ 			device ref me_kt	on end # Management Engine KT
+@@ -48,7 +50,7 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 			device ref pcie_rp2	on end # PCIe Port #2
+ 			device ref pcie_rp3	on end # PCIe Port #3
+ 			device ref pcie_rp4	on end # PCIe Port #4
+-			device ref pcie_rp5	off end # PCIe Port #5
++			device ref pcie_rp5	on end # PCIe Port #5
+ 			device ref pcie_rp6	on end # PCIe Port #6
+ 			device ref pcie_rp7	off end # PCIe Port #7
+ 			device ref pcie_rp8	off end # PCIe Port #8
+diff --git a/src/mainboard/dell/e6530/early_init.c b/src/mainboard/dell/e6530/early_init.c
+index d57f48e7f1..2b40f6963f 100644
+--- a/src/mainboard/dell/e6530/early_init.c
++++ b/src/mainboard/dell/e6530/early_init.c
+@@ -4,7 +4,6 @@
+ #include <bootblock_common.h>
+ #include <device/pci_ops.h>
+ #include <ec/dell/mec5035/mec5035.h>
+-#include <northbridge/intel/sandybridge/raminit_native.h>
+ #include <southbridge/intel/bd82x6x/pch.h>
+ 
+ const struct southbridge_usb_port mainboard_usb_ports[] = {
+@@ -26,13 +25,8 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
+ 
+ void bootblock_mainboard_early_init(void)
+ {
+-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1c0f);
+-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000);
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
+ 	mec5035_early_init();
+ }
+-
+-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+-{
+-	read_spd(&spd[0], 0x50, id_only);
+-	read_spd(&spd[2], 0x52, id_only);
+-}
+-- 
+2.39.2
+

config/coreboot/default/patches/0028-dell-e6-30-disable-the-ME-device-in-devicetree.patch

@@ -0,0 +1,54 @@
+From 8705b719573d2159adde10af9c6a4d8806b7d27b Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Thu, 25 Jan 2024 14:37:30 +0000
+Subject: [PATCH 28/30] dell/e6*30: disable the ME device in devicetree
+
+we neuter anyway. disabling it in devicetree will prevent linux
+from ever trying to use it or load a driver for it, and thus
+might prevent benign error messages from appearing in dmesg.
+
+this change was suggested by nicholas when asked on irc.
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/mainboard/dell/e6430/devicetree.cb | 4 ++--
+ src/mainboard/dell/e6530/devicetree.cb | 4 ++--
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/src/mainboard/dell/e6430/devicetree.cb b/src/mainboard/dell/e6430/devicetree.cb
+index 054b01c5ac..2b8574c984 100644
+--- a/src/mainboard/dell/e6430/devicetree.cb
++++ b/src/mainboard/dell/e6430/devicetree.cb
+@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 			register "xhci_switchable_ports" = "0x0000000f"
+ 
+ 			device ref xhci		on end
+-			device ref mei1		on end
++			device ref mei1		off end
+ 			device ref mei2		off end
+ 			device ref me_ide_r	off end
+-			device ref me_kt	on end
++			device ref me_kt	off end
+ 			device ref gbe		on end
+ 			device ref ehci2	on end
+ 			device ref hda		on end
+diff --git a/src/mainboard/dell/e6530/devicetree.cb b/src/mainboard/dell/e6530/devicetree.cb
+index 37135bcf0f..010200bb6d 100644
+--- a/src/mainboard/dell/e6530/devicetree.cb
++++ b/src/mainboard/dell/e6530/devicetree.cb
+@@ -39,10 +39,10 @@ chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
+ 			register "xhci_switchable_ports" = "0x0000000f"
+ 
+ 			device ref xhci		on end # USB 3.0 Controller
+-			device ref mei1		on end # Management Engine Interface 1
++			device ref mei1		off end # Management Engine Interface 1
+ 			device ref mei2		off end # Management Engine Interface 2
+ 			device ref me_ide_r	off end # Management Engine IDE-R
+-			device ref me_kt	on end # Management Engine KT
++			device ref me_kt	off end # Management Engine KT
+ 			device ref gbe		on end # Intel Gigabit Ethernet
+ 			device ref ehci2	on end # USB2 EHCI #2
+ 			device ref hda		on end # High Definition Audio
+-- 
+2.39.2
+

config/coreboot/default/patches/0028-nb-gm45-Fix-Angel-s-DDR2-RCOMP-fix-on-DDR3-boards.patch

@@ -1,240 +0,0 @@
-From b6f75374fa38e0b097c9eadb4916112707cb6747 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Tue, 6 Aug 2024 00:50:24 +0100
-Subject: [PATCH 28/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
-
-We add this patch:
-
-commit commit_id_here
-Author: Angel Pons <th3fanbus@gmail.com>
-Date:   Mon May 10 22:40:59 2021 +0200
-
-    nb/intel/gm45: Make DDR2 raminit work
-
-This patch was original applied, in lbmk, only on coreboot/dell,
-separately from coreboot/default, which was wasteful because it
-meant having an entire coreboot tree just for a single board. We
-did this, because the DDR2 RCOMP fix happened to break DDR3 init
-on other boards.
-
-What *this* new patch does on top of Angel's patch, is make sure
-that their changes only apply to DDR2, while DDR3 behaviour remains
-unchanged. This means that the Dell Latitude E6400 can be supported
-in the main coreboot tree, within lbmk.
-
-Essentially, this patch restores the old behaviour, prior to applying
-Angel's patch, only when DDR3 memory is used.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/northbridge/intel/gm45/raminit.c          | 161 +++++++++---------
- .../intel/gm45/raminit_rcomp_calibration.c    |   9 +-
- 2 files changed, 88 insertions(+), 82 deletions(-)
-
-diff --git a/src/northbridge/intel/gm45/raminit.c b/src/northbridge/intel/gm45/raminit.c
-index df8f46fbbc..433db3a68c 100644
---- a/src/northbridge/intel/gm45/raminit.c
-+++ b/src/northbridge/intel/gm45/raminit.c
-@@ -1117,7 +1117,10 @@ static void dram_program_timings(const int spd_type, const timings_t *const timi
- 				reg = (reg & ~(0xf << 10)) | (2 << 10);
- 			else
- 				reg = (reg & ~(0xf << 10)) | (3 << 10);
--			reg = (reg & ~(0x7 <<  5)) | (2 << 5);
-+			if (spd_type == DDR2)
-+				reg = (reg & ~(0x7 <<  5)) | (2 << 5);
-+			else
-+				reg = (reg & ~(0x7 <<  5)) | (3 << 5);
- 		} else if (timings->mem_clock != MEM_CLOCK_1067MT) {
- 			reg = (reg & ~(0x7 << 15)) | ((9 - timings->CAS) << 15);
- 			reg = (reg & ~(0xf << 10)) | ((timings->CAS - 3) << 10);
-@@ -2209,83 +2212,85 @@ void raminit(sysinfo_t *const sysinfo, const int s3resume)
- 		raminit_write_training(timings->mem_clock, dimms, s3resume);
- 	}
- 
--	/*
--	 * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
--	 * after receiver enable calibration, otherwise raminit sometimes
--	 * completes with non-working memory.
--	 */
--	mchbar_write32(0x0530, 0x06060005);
--	mchbar_write32(0x0680, 0x06060606);
--	mchbar_write32(0x0684, 0x08070606);
--	mchbar_write32(0x0688, 0x0e0e0c0a);
--	mchbar_write32(0x068c, 0x0e0e0e0e);
--	mchbar_write32(0x0698, 0x06060606);
--	mchbar_write32(0x069c, 0x08070606);
--	mchbar_write32(0x06a0, 0x0c0c0b0a);
--	mchbar_write32(0x06a4, 0x0c0c0c0c);
--
--	mchbar_write32(0x06c0, 0x02020202);
--	mchbar_write32(0x06c4, 0x03020202);
--	mchbar_write32(0x06c8, 0x04040403);
--	mchbar_write32(0x06cc, 0x04040404);
--	mchbar_write32(0x06d8, 0x02020202);
--	mchbar_write32(0x06dc, 0x03020202);
--	mchbar_write32(0x06e0, 0x04040403);
--	mchbar_write32(0x06e4, 0x04040404);
--
--	mchbar_write32(0x0700, 0x02020202);
--	mchbar_write32(0x0704, 0x03020202);
--	mchbar_write32(0x0708, 0x04040403);
--	mchbar_write32(0x070c, 0x04040404);
--	mchbar_write32(0x0718, 0x02020202);
--	mchbar_write32(0x071c, 0x03020202);
--	mchbar_write32(0x0720, 0x04040403);
--	mchbar_write32(0x0724, 0x04040404);
--
--	mchbar_write32(0x0740, 0x02020202);
--	mchbar_write32(0x0744, 0x03020202);
--	mchbar_write32(0x0748, 0x04040403);
--	mchbar_write32(0x074c, 0x04040404);
--	mchbar_write32(0x0758, 0x02020202);
--	mchbar_write32(0x075c, 0x03020202);
--	mchbar_write32(0x0760, 0x04040403);
--	mchbar_write32(0x0764, 0x04040404);
--
--	mchbar_write32(0x0780, 0x06060606);
--	mchbar_write32(0x0784, 0x09070606);
--	mchbar_write32(0x0788, 0x0e0e0c0b);
--	mchbar_write32(0x078c, 0x0e0e0e0e);
--	mchbar_write32(0x0798, 0x06060606);
--	mchbar_write32(0x079c, 0x09070606);
--	mchbar_write32(0x07a0, 0x0d0d0c0b);
--	mchbar_write32(0x07a4, 0x0d0d0d0d);
--
--	mchbar_write32(0x07c0, 0x06060606);
--	mchbar_write32(0x07c4, 0x09070606);
--	mchbar_write32(0x07c8, 0x0e0e0c0b);
--	mchbar_write32(0x07cc, 0x0e0e0e0e);
--	mchbar_write32(0x07d8, 0x06060606);
--	mchbar_write32(0x07dc, 0x09070606);
--	mchbar_write32(0x07e0, 0x0d0d0c0b);
--	mchbar_write32(0x07e4, 0x0d0d0d0d);
--
--	mchbar_write32(0x0840, 0x06060606);
--	mchbar_write32(0x0844, 0x08070606);
--	mchbar_write32(0x0848, 0x0e0e0c0a);
--	mchbar_write32(0x084c, 0x0e0e0e0e);
--	mchbar_write32(0x0858, 0x06060606);
--	mchbar_write32(0x085c, 0x08070606);
--	mchbar_write32(0x0860, 0x0c0c0b0a);
--	mchbar_write32(0x0864, 0x0c0c0c0c);
--
--	mchbar_write32(0x0880, 0x02020202);
--	mchbar_write32(0x0884, 0x03020202);
--	mchbar_write32(0x0888, 0x04040403);
--	mchbar_write32(0x088c, 0x04040404);
--	mchbar_write32(0x0898, 0x02020202);
--	mchbar_write32(0x089c, 0x03020202);
--	mchbar_write32(0x08a0, 0x04040403);
--	mchbar_write32(0x08a4, 0x04040404);
-+	if (sysinfo->spd_type == DDR2) {
-+		/*
-+		 * Program hardcoded DDR2-800 RCOMP SRAM codes. This must be done
-+		 * after receiver enable calibration, otherwise raminit sometimes
-+		 * completes with non-working memory.
-+		 */
-+		mchbar_write32(0x0530, 0x06060005);
-+		mchbar_write32(0x0680, 0x06060606);
-+		mchbar_write32(0x0684, 0x08070606);
-+		mchbar_write32(0x0688, 0x0e0e0c0a);
-+		mchbar_write32(0x068c, 0x0e0e0e0e);
-+		mchbar_write32(0x0698, 0x06060606);
-+		mchbar_write32(0x069c, 0x08070606);
-+		mchbar_write32(0x06a0, 0x0c0c0b0a);
-+		mchbar_write32(0x06a4, 0x0c0c0c0c);
-+
-+		mchbar_write32(0x06c0, 0x02020202);
-+		mchbar_write32(0x06c4, 0x03020202);
-+		mchbar_write32(0x06c8, 0x04040403);
-+		mchbar_write32(0x06cc, 0x04040404);
-+		mchbar_write32(0x06d8, 0x02020202);
-+		mchbar_write32(0x06dc, 0x03020202);
-+		mchbar_write32(0x06e0, 0x04040403);
-+		mchbar_write32(0x06e4, 0x04040404);
-+
-+		mchbar_write32(0x0700, 0x02020202);
-+		mchbar_write32(0x0704, 0x03020202);
-+		mchbar_write32(0x0708, 0x04040403);
-+		mchbar_write32(0x070c, 0x04040404);
-+		mchbar_write32(0x0718, 0x02020202);
-+		mchbar_write32(0x071c, 0x03020202);
-+		mchbar_write32(0x0720, 0x04040403);
-+		mchbar_write32(0x0724, 0x04040404);
-+
-+		mchbar_write32(0x0740, 0x02020202);
-+		mchbar_write32(0x0744, 0x03020202);
-+		mchbar_write32(0x0748, 0x04040403);
-+		mchbar_write32(0x074c, 0x04040404);
-+		mchbar_write32(0x0758, 0x02020202);
-+		mchbar_write32(0x075c, 0x03020202);
-+		mchbar_write32(0x0760, 0x04040403);
-+		mchbar_write32(0x0764, 0x04040404);
-+
-+		mchbar_write32(0x0780, 0x06060606);
-+		mchbar_write32(0x0784, 0x09070606);
-+		mchbar_write32(0x0788, 0x0e0e0c0b);
-+		mchbar_write32(0x078c, 0x0e0e0e0e);
-+		mchbar_write32(0x0798, 0x06060606);
-+		mchbar_write32(0x079c, 0x09070606);
-+		mchbar_write32(0x07a0, 0x0d0d0c0b);
-+		mchbar_write32(0x07a4, 0x0d0d0d0d);
-+
-+		mchbar_write32(0x07c0, 0x06060606);
-+		mchbar_write32(0x07c4, 0x09070606);
-+		mchbar_write32(0x07c8, 0x0e0e0c0b);
-+		mchbar_write32(0x07cc, 0x0e0e0e0e);
-+		mchbar_write32(0x07d8, 0x06060606);
-+		mchbar_write32(0x07dc, 0x09070606);
-+		mchbar_write32(0x07e0, 0x0d0d0c0b);
-+		mchbar_write32(0x07e4, 0x0d0d0d0d);
-+
-+		mchbar_write32(0x0840, 0x06060606);
-+		mchbar_write32(0x0844, 0x08070606);
-+		mchbar_write32(0x0848, 0x0e0e0c0a);
-+		mchbar_write32(0x084c, 0x0e0e0e0e);
-+		mchbar_write32(0x0858, 0x06060606);
-+		mchbar_write32(0x085c, 0x08070606);
-+		mchbar_write32(0x0860, 0x0c0c0b0a);
-+		mchbar_write32(0x0864, 0x0c0c0c0c);
-+
-+		mchbar_write32(0x0880, 0x02020202);
-+		mchbar_write32(0x0884, 0x03020202);
-+		mchbar_write32(0x0888, 0x04040403);
-+		mchbar_write32(0x088c, 0x04040404);
-+		mchbar_write32(0x0898, 0x02020202);
-+		mchbar_write32(0x089c, 0x03020202);
-+		mchbar_write32(0x08a0, 0x04040403);
-+		mchbar_write32(0x08a4, 0x04040404);
-+	}
- 
- 	igd_compute_ggc(sysinfo);
- 
-diff --git a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-index b74765fd9c..5d4505e063 100644
---- a/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-+++ b/src/northbridge/intel/gm45/raminit_rcomp_calibration.c
-@@ -198,7 +198,7 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
- 		reg = mchbar_read32(0x518);
- 		lut_idx[channel][group][PULL_UP] = (reg >> 24) & 0x7f;
- 		lut_idx[channel][group][PULL_DOWN] = (reg >> 16) & 0x7f;
--		if (i == 1) {
-+		if ((i == 1) && (ddr_type == DDR2)) {
- 			magic_comp[0] = (reg >> 8) & 0x3f;
- 			magic_comp[1] = (reg >> 0) & 0x3f;
- 		}
-@@ -242,7 +242,8 @@ void raminit_rcomp_calibration(int ddr_type, const stepping_t stepping) {
- 		}
- 		mchbar += 0x0040;
- 	}
--
--	mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
--	mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
-+	if (ddr_type == DDR2) {
-+		mchbar_clrsetbits32(0x4d0, 0x3f << 26, magic_comp[0] << 26);
-+		mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
-+	}
- }
--- 
-2.39.5
-

config/coreboot/default/patches/0029-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch

@@ -1,52 +0,0 @@
-From d3045b3dcebd94b78df2129cd81a20adf215e46a Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Mon, 20 May 2024 10:24:16 -0600
-Subject: [PATCH 29/51] mb/dell/e6400: Use 100 MHz reference clock for display
-
-The E6400 uses a 100 MHz reference clock for spread spectrum support on
-LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
-the more common 1280 x 800 display panels, the numerical error was not
-large enough to cause noticable issues, but the actual pixel clock
-frequency derived from a 100 MHz reference using PLL configs calculated
-assuming a 96 MHz reference was not close enough for 1440 x 900 panels,
-which require a much higher pixel clock. This resulted in a garbled
-display in the pre-OS graphics environment provided by libgfxinit.
-
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/e6400/Kconfig   | 3 +++
- src/northbridge/intel/gm45/Kconfig | 4 ++++
- 2 files changed, 7 insertions(+)
-
-diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/e6400/Kconfig
-index 417d95fd5d..6fe1b1c456 100644
---- a/src/mainboard/dell/e6400/Kconfig
-+++ b/src/mainboard/dell/e6400/Kconfig
-@@ -19,6 +19,9 @@ config BOARD_SPECIFIC_OPTIONS
- 	select INTEL_GMA_HAVE_VBT
- 	select EC_DELL_MEC5035
- 
-+config INTEL_GMA_DPLL_REF_FREQ
-+	default 100000000
-+
- config MAINBOARD_DIR
- 	default "dell/e6400"
- 
-diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig
-index 8059e7ee80..5df5a93296 100644
---- a/src/northbridge/intel/gm45/Kconfig
-+++ b/src/northbridge/intel/gm45/Kconfig
-@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_GM45
- 
- if NORTHBRIDGE_INTEL_GM45
- 
-+config INTEL_GMA_DPLL_REF_FREQ
-+	int
-+	default 96000000
-+
- config VBOOT
- 	select VBOOT_STARTS_IN_BOOTBLOCK
- 
--- 
-2.39.5
-

config/coreboot/default/patches/0029-x220_edp-modification-introduced-similar-to-x230_edp.patch

@@ -0,0 +1,164 @@
+From f07ed32c36978327709a113967ec40e5ba8d828e Mon Sep 17 00:00:00 2001
+From: risapav <risapav@gmail.com>
+Date: Sun, 17 Dec 2023 16:54:07 +0100
+Subject: [PATCH 29/30] x220_edp modification introduced, similar to x230_edp
+
+---
+ src/mainboard/lenovo/x220/Kconfig             |  13 ++++++-----
+ src/mainboard/lenovo/x220/Kconfig.name        |   3 +++
+ src/mainboard/lenovo/x220/Makefile.mk         |   6 +++++
+ .../lenovo/x220/variants/x220_edp/data.vbt    | Bin 0 -> 4281 bytes
+ .../x220/variants/x220_edp/gma-mainboard.ads  |  21 ++++++++++++++++++
+ 5 files changed, 38 insertions(+), 5 deletions(-)
+ create mode 100644 src/mainboard/lenovo/x220/variants/x220_edp/data.vbt
+ create mode 100644 src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
+
+diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig
+index eeb55b4393..bc73a47df9 100644
+--- a/src/mainboard/lenovo/x220/Kconfig
++++ b/src/mainboard/lenovo/x220/Kconfig
+@@ -1,4 +1,4 @@
+-if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
++if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 || BOARD_LENOVO_X220_EDP
+ 
+ config BOARD_SPECIFIC_OPTIONS
+ 	def_bool y
+@@ -6,7 +6,7 @@ config BOARD_SPECIFIC_OPTIONS
+ 	select DRIVERS_RICOH_RCE822
+ 	select EC_LENOVO_H8
+ 	select EC_LENOVO_PMH7
+-	select GFX_GMA_PANEL_1_ON_LVDS
++	select GFX_GMA_PANEL_1_ON_LVDS if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 
+ 	select H8_HAS_BAT_THRESHOLDS_IMPL
+ 	select HAVE_ACPI_RESUME
+ 	select HAVE_ACPI_TABLES
+@@ -41,19 +41,22 @@ config MAINBOARD_DIR
+ 	default "lenovo/x220"
+ 
+ config VARIANT_DIR
+-	default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I
++	default "x220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X220_EDP
+ 	default "x1" if BOARD_LENOVO_X1
+ 
+ config FMDFILE
+ 	default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT
+ 
+ config MAINBOARD_PART_NUMBER
+-	default "ThinkPad X220" if BOARD_LENOVO_X220
++	default "ThinkPad X220" if BOARD_LENOVO_X220 || BOARD_LENOVO_X220_EDP
+ 	default "ThinkPad X220i" if BOARD_LENOVO_X220I
+ 	default "ThinkPad X1" if BOARD_LENOVO_X1
+ 
+ config OVERRIDE_DEVICETREE
+ 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
++	
++config INTEL_GMA_VBT_FILE
++       default "src/mainboard/\$(MAINBOARDDIR)/variants/x220_edp/data.vbt" if BOARD_LENOVO_X220_EDP	
+ 
+ config USBDEBUG_HCD_INDEX
+ 	int
+@@ -75,4 +78,4 @@ config PS2K_EISAID
+ config PS2M_EISAID
+ 	default "LEN0020"
+ 
+-endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1
++endif # BOARD_LENOVO_X220 || BOARD_LENOVO_X220I || BOARD_LENOVO_X1 || BOARD_LENOVO_X220_EDP
+diff --git a/src/mainboard/lenovo/x220/Kconfig.name b/src/mainboard/lenovo/x220/Kconfig.name
+index 988ac4fb55..cd501954e0 100644
+--- a/src/mainboard/lenovo/x220/Kconfig.name
++++ b/src/mainboard/lenovo/x220/Kconfig.name
+@@ -6,3 +6,6 @@ config BOARD_LENOVO_X220I
+ 
+ config BOARD_LENOVO_X1
+ 	bool "ThinkPad X1"
++	
++config BOARD_LENOVO_X220_EDP
++	bool "ThinkPad X220 eDP Mod (2K/FHD)"
+diff --git a/src/mainboard/lenovo/x220/Makefile.mk b/src/mainboard/lenovo/x220/Makefile.mk
+index b104bb52a9..052bf17a22 100644
+--- a/src/mainboard/lenovo/x220/Makefile.mk
++++ b/src/mainboard/lenovo/x220/Makefile.mk
+@@ -4,6 +4,12 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio.c
+ romstage-y += variants/$(VARIANT_DIR)/gpio.c
+ romstage-y += variants/$(VARIANT_DIR)/romstage.c
+ 
++
++ifeq ($(CONFIG_BOARD_LENOVO_X220_EDP),y)
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/x220_edp/gma-mainboard.ads
++else
+ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
++endif
++
+ bootblock-y += early_init.c
+ romstage-y += early_init.c
+diff --git a/src/mainboard/lenovo/x220/variants/x220_edp/data.vbt b/src/mainboard/lenovo/x220/variants/x220_edp/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..13384d45571ff76e592335143d01315e37893186
+GIT binary patch
+literal 4281
+zcmdT`Z)_aZ5&ym0y}P}=-MjTVC6^<yCLz$XvE%h&S*h!)@6LAcg^PXugKH2XcDRE^
+zHNiLuN+i^5TbBk=p_5vr0Ri$CB!v1Q6%yhL5TS}%ZG|E}(5mW(6!8It5AdN?tBP`+
+zx3_i!7V#AnmCow7GdpkI?0YkBW_RywafYVHi@l}UV$Y$8VyQezRd{&CInDRYR4h$Q
+zA08>p6b={56T^4V^SA+LolmX+RUx+79#iSqiP~ars*|P{j#W<|Sw32Qpw?S@B$TK!
+zT%y8#_th3_%L^xJRhpi?y+F#XZ5B@+U98gh$p??rmIq1sVr%N_-*;O-QJ>e_m+#Gc
+zeSJjvzQO*1!F<1Mj*JdZ9IBMcg_+XCI898^NNKt-Jw1A;SiXxYQxjvQVrgb{#5RMi
+z3_rAVdim%B-#tOO;ZDl)3wi>F!IEkCq2;B0R9IZ3DP?n<rfSD)%a7Em`)pG=xClcR
+zfQTY3AQJz|BVh>3(8mm!Gbk$bf{?ofjp)+WX;f0xKuMreM_FPop&M`zu|-4&b{lx}
+z6dXr%nIN^a1Q1g^?g`SApyQo+We^Ju;y^Soa0Kxp0ExE)gG^{(s5wk=5)@Iwe?zpD
+z@%1v$crW@+c=`T;{ewfYIC5a@V7W3iGdp+pJ^l}V_@k99K7NB27i?KEp$JF`50mi@
+zjG1XXrseRG7Qw69ek|x~_*Klqd$9}}jBGpu*K}~RX~1KAld;P%uwb}2&iFCo7mQyT
+zCSGP-Wc-%#2gY9*A29yLh$l?6F>Yks%;;r&gE7oF#P|+lf$=@YNyZt*<BXp%o@K;N
+z;^Rid2d9zA7a?zJayUAk?1cYJsDCEZCq4>N3Nz%%kOxj$xHTH_I6i5-#j$7@-%=}(
+z?1954MnX?xAuk79(<<Tf409Fpx$wEsNX+wNp0De7H-87y*XOlHqw#v9f#_UhUAnlg
+zi_2(JC*w<@<i}S-iI)}-&;1HW$=_hN&+7=v86dSJ5nbA)_y+kbU2PDFE??VVW9GW>
+zSr6;_4gTc~tacpa=As!xD;@CT7xX)U4}W57_`9~2N<i$1-Hq?ZdXRnseAKTSC4vUn
+zvU_KR`>pCP65!^@JyGbYMG6B#@{r1i&qF#431THdvdmK?gb!}@x&d86kH8RtSun)L
+zMg&qo8p@sxlqPr)H*t1i5Xc8fNK*dW_}wA77I--u)J{nAs;))bo<l6#G>8v<p5gy;
+z<c2$V&sxyMI7lIRD=DCSpmMmfaICgCzVKkJ#fR-<sP2F);1(})cA)7k<8|TuBs}RY
+zwKp{#FZ7<eJej>k&YfS^jD1^rM=s>0ytuB(<S=kXYsT9eI1^R*2UrsIpx#)DflmYL
+zcI2=F|Kw{2>VlIOTx;M223I$qhjl3%0pyLp$ECQ*_^UYE{?(M!zFMP3W9I<gN%(cT
+zyvs4>_cUj9w4&M7&s8K0k<cwUM!E2PTu7mct3rr`5sB*7)nZ4R`hWT~<uZuic%Tb%
+z5{?q{&YwfGl9W%nBS~{SNhgx-V@b1~q?eQKTGD(wN&iT?re$ukXwY)YmN{$Dqn7)m
+zWuCX_HOswZnSZhfw(HvFPMeChJ7b&o+O%T3=WKJ;rZ;W(kGA=)O-9Pirp&!5I+$|r
+zNtySj=%*?7xs>@rirz}Oms94I6gg>kPulEG+g%^&e&n+7+xV#SfijjY{5o+C7V}H-
+zZs9PGrN7SK-OZ8YGZ>yr(&i#tdss~q`sQ|0&fnIIOUJ;O2*-=b;v=kW?O}6KsoH4P
+z0smI&%EQn#cd@w$RZTVP=TtP?l7~|?nRTSIQO2qkgO+Z!=3#T$D-XeMvn68}T3Ey8
+zHleye(7mkLXe*JtfA{Q*lj!gc)Wck4IFj|C#q&~HiNmA&>Z|kF4(U<Y;5eIloj)C%
+zP4#WvIv2Sie|71?P3)md%>vj%v~DWNT8*x>a2}rST)i~8vd61DwO!2$JZMNNi6hyH
+z2d_)6&979w%w$-vyatVrqw??t&t%}iZhDAP3%j_I#cGANdzLq>W;J(F=Xwkxxj%^H
+zwQDmn=w}|@-y`RG{*wz0>A(ZGtk~AM=#-fE(LV1uZE98+Nk>UmiyyuJ8?##<Mr{1g
+p(B@uj-Va_SU#<T#GXLCvin_ms#}9BYOE7UKDyX7coWuJX{tbC=%boxL
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads b/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
+new file mode 100644
+index 0000000000..f7cf0bc264
+--- /dev/null
++++ b/src/mainboard/lenovo/x220/variants/x220_edp/gma-mainboard.ads
+@@ -0,0 +1,21 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (DP1,
++      DP2,
++      DP3,
++      HDMI1,
++      HDMI2,
++      HDMI3,
++      Analog,
++      others => Disabled);
++
++end GMA.Mainboard;
+-- 
+2.39.2
+

config/coreboot/default/patches/0030-mb-hp-Add-Compaq-Elite-8300-CMT-port.patch

@@ -1,7 +1,7 @@
-From 440ebbe1e10911dc3d8c53cf9eecb5519c2ecd67 Mon Sep 17 00:00:00 2001
+From 4e0b62e6f0977cf922b1947955538ddca63bb954 Mon Sep 17 00:00:00 2001
 From: Riku Viitanen <riku.viitanen@protonmail.com>
 Date: Sat, 23 Dec 2023 19:02:10 +0200
-Subject: [PATCH 20/51] mb/hp: Add Compaq Elite 8300 CMT port
+Subject: [PATCH 30/30] mb/hp: Add Compaq Elite 8300 CMT port
 
 Based on autoport and Z220 SuperIO code.
 
@@ -32,7 +32,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
 ---
  .../hp/compaq_elite_8300_cmt/Kconfig          |  39 ++++
  .../hp/compaq_elite_8300_cmt/Kconfig.name     |   2 +
- .../hp/compaq_elite_8300_cmt/Makefile.mk      |   7 +
+ .../hp/compaq_elite_8300_cmt/Makefile.inc     |   7 +
  .../hp/compaq_elite_8300_cmt/acpi/ec.asl      |   1 +
  .../compaq_elite_8300_cmt/acpi/platform.asl   |  10 +
  .../hp/compaq_elite_8300_cmt/acpi/superio.asl |  29 +++
@@ -41,17 +41,17 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
  .../hp/compaq_elite_8300_cmt/cmos.default     |   7 +
  .../hp/compaq_elite_8300_cmt/cmos.layout      |  74 +++++++
  .../hp/compaq_elite_8300_cmt/data.vbt         | Bin 0 -> 3902 bytes
- .../hp/compaq_elite_8300_cmt/devicetree.cb    | 177 ++++++++++++++++
+ .../hp/compaq_elite_8300_cmt/devicetree.cb    | 161 +++++++++++++++
  .../hp/compaq_elite_8300_cmt/dsdt.asl         |  26 +++
- .../hp/compaq_elite_8300_cmt/early_init.c     |  14 ++
+ .../hp/compaq_elite_8300_cmt/early_init.c     |  31 +++
  .../compaq_elite_8300_cmt/gma-mainboard.ads   |  17 ++
  src/mainboard/hp/compaq_elite_8300_cmt/gpio.c | 191 ++++++++++++++++++
  .../hp/compaq_elite_8300_cmt/hda_verb.c       |  33 +++
  .../hp/compaq_elite_8300_cmt/mainboard.c      |  16 ++
- 18 files changed, 660 insertions(+)
+ 18 files changed, 661 insertions(+)
  create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig
  create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Kconfig.name
- create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
+ create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
  create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/ec.asl
  create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/platform.asl
  create mode 100644 src/mainboard/hp/compaq_elite_8300_cmt/acpi/superio.asl
@@ -121,11 +121,11 @@ index 0000000000..bd399b1e76
 @@ -0,0 +1,2 @@
 +config BOARD_HP_COMPAQ_ELITE_8300_CMT
 +	bool "Compaq Elite 8300 CMT"
-diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
+diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
 new file mode 100644
 index 0000000000..fb492d3583
 --- /dev/null
-+++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.mk
++++ b/src/mainboard/hp/compaq_elite_8300_cmt/Makefile.inc
 @@ -0,0 +1,7 @@
 +## SPDX-License-Identifier: GPL-2.0-only
 +
@@ -353,10 +353,10 @@ HcmV?d00001
 
 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
 new file mode 100644
-index 0000000000..3d21739b72
+index 0000000000..f4efabd792
 --- /dev/null
 +++ b/src/mainboard/hp/compaq_elite_8300_cmt/devicetree.cb
-@@ -0,0 +1,177 @@
+@@ -0,0 +1,161 @@
 +# SPDX-License-Identifier: GPL-2.0-only
 +
 +chip northbridge/intel/sandybridge
@@ -386,22 +386,6 @@ index 0000000000..3d21739b72
 +			register "superspeed_capable_ports" = "0x0000000f"
 +			register "xhci_overcurrent_mapping" = "0x00000c03"
 +			register "xhci_switchable_ports" = "0x0000000f"
-+			register "usb_port_config" = "{
-+				{ 1, 0, 0 },
-+				{ 1, 0, 0 },
-+				{ 1, 0, 1 },
-+				{ 1, 0, 1 },
-+				{ 1, 0, 2 },
-+				{ 1, 0, 2 },
-+				{ 1, 0, 3 },
-+				{ 1, 0, 3 },
-+				{ 1, 0, 4 },
-+				{ 1, 0, 4 },
-+				{ 1, 0, 6 },
-+				{ 1, 0, 5 },
-+				{ 1, 0, 5 },
-+				{ 1, 0, 6 }
-+			}"
 +
 +			device ref xhci on   end # USB 3.0 Controller
 +			device ref mei1 off  end # Management Engine Interface 1
@@ -421,7 +405,7 @@ index 0000000000..3d21739b72
 +			device ref pcie_rp3 on end
 +			device ref pcie_rp4 on end
 +			device ref pcie_rp5 on end
-+			device ref pcie_rp6 on end
++			device ref pcie_rp5 on end
 +			device ref pcie_rp7 on end
 +			device ref pcie_rp8 on end
 +
@@ -568,10 +552,10 @@ index 0000000000..e8e2b3a3e5
 +}
 diff --git a/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
 new file mode 100644
-index 0000000000..8d10c6317c
+index 0000000000..99b7891c70
 --- /dev/null
 +++ b/src/mainboard/hp/compaq_elite_8300_cmt/early_init.c
-@@ -0,0 +1,14 @@
+@@ -0,0 +1,31 @@
 +/* SPDX-License-Identifier: GPL-2.0-only */
 +
 +#include <bootblock_common.h>
@@ -581,6 +565,23 @@ index 0000000000..8d10c6317c
 +
 +#define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
 +
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 0, 0 },
++	{ 1, 0, 0 },
++	{ 1, 0, 1 },
++	{ 1, 0, 1 },
++	{ 1, 0, 2 },
++	{ 1, 0, 2 },
++	{ 1, 0, 3 },
++	{ 1, 0, 3 },
++	{ 1, 0, 4 },
++	{ 1, 0, 4 },
++	{ 1, 0, 6 },
++	{ 1, 0, 5 },
++	{ 1, 0, 5 },
++	{ 1, 0, 6 },
++};
++
 +void bootblock_mainboard_early_init(void)
 +{
 +	if (CONFIG(CONSOLE_SERIAL))
@@ -868,5 +869,5 @@ index 0000000000..8dbd95ef96
 +	.enable_dev = mainboard_enable,
 +};
 -- 
-2.39.5
+2.39.2
 

config/coreboot/default/patches/0031-mb-dell-Add-OptiPlex-7020-9020-port_cb55232_31.patch

@@ -0,0 +1,923 @@
+From 38a713eb071dd9c1b7d5092ce686537e5d9266f5 Mon Sep 17 00:00:00 2001
+From: Mate Kukri <kukri.mate@gmail.com>
+Date: Mon, 4 Dec 2023 21:34:18 +0000
+Subject: [PATCH 1/1] mb/dell: Add OptiPlex 7020/9020 port
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The OptiPlex 7020 and 9020 use physically identical motherboards.
+
+Each model comes in the following form factors:
+- 7020: SFF, MT
+- 9020: USFF (not currently supported), SFF, MT
+
+(7020 SFF) Boots Linux and Windows 10:
+- Tested with an i3-4160 and i5-4460
+- DRAM init works using the MRC (4G, 4G+4G)
+- iGPU init works using libgfxinit (VGA, 2x DP)
+- PCIe 16x: tested, ok
+- PCIe 4x: tested, ok
+- All USB2 and USB3 ports work
+- SMSC SCH5555 Super I/O: serial works, PS/2 untested
+- Audio: back and front output works, internal speaker works,
+         mic inputs untested
+- Ethernet: tested, works
+
+(9020 MT)
+- Tested by Michael Büchler (thanks for the overridetree)
+
+Change-Id: Ie7c7089f443aef9890711c4412209bceb1f1e96a
+Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
+---
+ src/mainboard/dell/optiplex_9020/Kconfig      |  34 +++
+ src/mainboard/dell/optiplex_9020/Kconfig.name |  11 +
+ src/mainboard/dell/optiplex_9020/Makefile.inc |   5 +
+ src/mainboard/dell/optiplex_9020/acpi/ec.asl  |   3 +
+ .../dell/optiplex_9020/acpi/platform.asl      |  11 +
+ .../dell/optiplex_9020/acpi/superio.asl       |   3 +
+ .../dell/optiplex_9020/board_info.txt         |   8 +
+ src/mainboard/dell/optiplex_9020/bootblock.c  | 116 ++++++++++
+ src/mainboard/dell/optiplex_9020/cmos.default |   4 +
+ src/mainboard/dell/optiplex_9020/cmos.layout  |  58 +++++
+ src/mainboard/dell/optiplex_9020/data.vbt     | Bin 0 -> 4409 bytes
+ .../dell/optiplex_9020/devicetree.cb          |  80 +++++++
+ src/mainboard/dell/optiplex_9020/dsdt.asl     |  25 ++
+ .../dell/optiplex_9020/gma-mainboard.ads      |  18 ++
+ src/mainboard/dell/optiplex_9020/gpio.c       | 217 ++++++++++++++++++
+ src/mainboard/dell/optiplex_9020/hda_verb.c   |  27 +++
+ src/mainboard/dell/optiplex_9020/mainboard.c  |  15 ++
+ .../dell/optiplex_9020/overridetree_mt.cb     |  10 +
+ src/mainboard/dell/optiplex_9020/romstage.c   |  53 +++++
+ 19 files changed, 698 insertions(+)
+ create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig
+ create mode 100644 src/mainboard/dell/optiplex_9020/Kconfig.name
+ create mode 100644 src/mainboard/dell/optiplex_9020/Makefile.inc
+ create mode 100644 src/mainboard/dell/optiplex_9020/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/optiplex_9020/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/optiplex_9020/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/optiplex_9020/board_info.txt
+ create mode 100644 src/mainboard/dell/optiplex_9020/bootblock.c
+ create mode 100644 src/mainboard/dell/optiplex_9020/cmos.default
+ create mode 100644 src/mainboard/dell/optiplex_9020/cmos.layout
+ create mode 100644 src/mainboard/dell/optiplex_9020/data.vbt
+ create mode 100644 src/mainboard/dell/optiplex_9020/devicetree.cb
+ create mode 100644 src/mainboard/dell/optiplex_9020/dsdt.asl
+ create mode 100644 src/mainboard/dell/optiplex_9020/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/optiplex_9020/gpio.c
+ create mode 100644 src/mainboard/dell/optiplex_9020/hda_verb.c
+ create mode 100644 src/mainboard/dell/optiplex_9020/mainboard.c
+ create mode 100644 src/mainboard/dell/optiplex_9020/overridetree_mt.cb
+ create mode 100644 src/mainboard/dell/optiplex_9020/romstage.c
+
+diff --git a/src/mainboard/dell/optiplex_9020/Kconfig b/src/mainboard/dell/optiplex_9020/Kconfig
+new file mode 100644
+index 0000000000..774a72f161
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/Kconfig
+@@ -0,0 +1,34 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++if BOARD_DELL_OPTIPLEX_9020_SFF || BOARD_DELL_OPTIPLEX_9020_MT
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_12288
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_OPTION_TABLE
++	select HAVE_CMOS_DEFAULT
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select NORTHBRIDGE_INTEL_HASWELL
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_LYNXPOINT
++	select SUPERIO_SMSC_SCH555x
++
++config CBFS_SIZE
++	default 0x600000
++
++config MAINBOARD_DIR
++	default "dell/optiplex_9020"
++
++config MAINBOARD_PART_NUMBER
++	default "OptiPlex 7020/9020 SFF" if BOARD_DELL_OPTIPLEX_9020_SFF
++	default "OptiPlex 7020/9020 MT" if BOARD_DELL_OPTIPLEX_9020_MT
++
++config OVERRIDE_DEVICETREE
++	default "overridetree_mt.cb" if BOARD_DELL_OPTIPLEX_9020_MT
++
++endif
+diff --git a/src/mainboard/dell/optiplex_9020/Kconfig.name b/src/mainboard/dell/optiplex_9020/Kconfig.name
+new file mode 100644
+index 0000000000..c25c330a44
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/Kconfig.name
+@@ -0,0 +1,11 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++config BOARD_DELL_OPTIPLEX_9020_SFF
++	bool "OptiPlex 7020/9020 SFF"
++	help
++	  The 7020 SFF and 9020 SFF mainboards are physically identical.
++
++config BOARD_DELL_OPTIPLEX_9020_MT
++	bool "OptiPlex 7020/9020 MT"
++	help
++	  The 7020 MT and 9020 MT mainboards are physically identical.
+diff --git a/src/mainboard/dell/optiplex_9020/Makefile.inc b/src/mainboard/dell/optiplex_9020/Makefile.inc
+new file mode 100644
+index 0000000000..6ca2f2afaa
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/Makefile.inc
+@@ -0,0 +1,5 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
++bootblock-y += bootblock.c
+diff --git a/src/mainboard/dell/optiplex_9020/acpi/ec.asl b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
+new file mode 100644
+index 0000000000..16990d45f4
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/acpi/ec.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: CC-PDDC */
++
++/* Please update the license if adding licensable material. */
+diff --git a/src/mainboard/dell/optiplex_9020/acpi/platform.asl b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
+new file mode 100644
+index 0000000000..cda7682e3e
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/acpi/platform.asl
+@@ -0,0 +1,11 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	Return(Package() { 0, 0 })
++}
++
++Method(_PTS, 1)
++{
++
++}
+diff --git a/src/mainboard/dell/optiplex_9020/acpi/superio.asl b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
+new file mode 100644
+index 0000000000..16990d45f4
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: CC-PDDC */
++
++/* Please update the license if adding licensable material. */
+diff --git a/src/mainboard/dell/optiplex_9020/board_info.txt b/src/mainboard/dell/optiplex_9020/board_info.txt
+new file mode 100644
+index 0000000000..e30cf9c41f
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/board_info.txt
+@@ -0,0 +1,8 @@
++Vendor name: Dell Inc.
++Board name: OptiPlex 7020/9020
++Release year: 2014
++Category: desktop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
+diff --git a/src/mainboard/dell/optiplex_9020/bootblock.c b/src/mainboard/dell/optiplex_9020/bootblock.c
+new file mode 100644
+index 0000000000..2837cf9cf1
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/bootblock.c
+@@ -0,0 +1,116 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <arch/io.h>
++#include <device/pnp_ops.h>
++#include <superio/smsc/sch555x/sch555x.h>
++#include <southbridge/intel/lynxpoint/pch.h>
++
++static void ec_write(uint8_t addr1, uint16_t addr2, uint8_t val)
++{
++	// Clear EC-to-Host mailbox
++	uint8_t tmp = inb(SCH555x_EMI_IOBASE + 1);
++	outb(tmp, SCH555x_EMI_IOBASE + 1);
++
++	// Send address and value to the EC
++	sch555x_emi_write16(0, (addr1 * 2) | 0x101);
++	sch555x_emi_write32(4, val | (addr2 << 16));
++
++	// Wait for acknowledgement message from EC
++	outb(1, SCH555x_EMI_IOBASE);
++	size_t timeout = 0;
++	do {} while (++timeout < 0xfff && (inb(SCH555x_EMI_IOBASE + 1) & 1) == 0);
++}
++
++struct ec_init_entry {
++	uint16_t addr;
++	uint8_t val;
++};
++
++static void ec_init(void)
++{
++	/*
++	 * Tables from CORE_PEI
++	 */
++
++	static const struct ec_init_entry init_table1[] = {
++		{0x08cc, 0x11}, {0x08d0, 0x11}, {0x088c, 0x10}, {0x0890, 0x10},
++		{0x0894, 0x10}, {0x0898, 0x12}, {0x089c, 0x12}, {0x08a0, 0x10},
++		{0x08a4, 0x12}, {0x08a8, 0x10}, {0x0820, 0x12}, {0x0824, 0x12},
++		{0x0878, 0x12}, {0x0880, 0x12}, {0x0884, 0x12}, {0x08e0, 0x12},
++		{0x08e4, 0x12}, {0x083c, 0x10}, {0x0840, 0x10}, {0x0844, 0x10},
++		{0x0848, 0x10}, {0x084c, 0x10}, {0x0850, 0x10}, {0x0814, 0x11},
++	};
++
++	for (size_t i = 0; i < ARRAY_SIZE(init_table1); ++i)
++		ec_write(2, init_table1[i].addr, init_table1[i].val);
++
++	static const struct ec_init_entry init_table2[] = {
++		{0x0005, 0x33}, {0x0018, 0x2f}, {0x0019, 0x2f}, {0x001a, 0x2f},
++		{0x0083, 0xbb}, {0x0085, 0xd9}, {0x0086, 0x2c}, {0x008a, 0x34},
++		{0x008b, 0x60}, {0x0090, 0x5e}, {0x0091, 0x5e}, {0x0092, 0x86},
++		{0x0096, 0xa4}, {0x0097, 0xa4}, {0x0098, 0xa4}, {0x009b, 0xa4},
++		{0x00a0, 0x0a}, {0x00a1, 0x0a}, {0x00ae, 0x7c}, {0x00af, 0x7c},
++		{0x00b0, 0x9e}, {0x00b3, 0x7c}, {0x00b6, 0x08}, {0x00b7, 0x08},
++		{0x00ea, 0x64}, {0x00ef, 0xff}, {0x00f8, 0x15}, {0x00f9, 0x00},
++		{0x00f0, 0x30}, {0x00fd, 0x01}, {0x01a1, 0x00}, {0x01a2, 0x00},
++		{0x01b1, 0x08}, {0x01be, 0x90}, {0x0280, 0x24}, {0x0281, 0x13},
++		{0x0282, 0x03}, {0x0283, 0x0a}, {0x0284, 0x80}, {0x0285, 0x03},
++		{0x0288, 0x80}, {0x0289, 0x0c}, {0x028a, 0x03}, {0x028b, 0x0a},
++		{0x028c, 0x80}, {0x028d, 0x03}, {0x0040, 0x01},
++	};
++
++	for (size_t i = 0; i < ARRAY_SIZE(init_table2); ++i)
++		ec_write(1, init_table2[i].addr, init_table2[i].val);
++
++	/*
++	 * Table from PeiHwmInit
++	 */
++
++	static const struct ec_init_entry hwm_init_table[] = {
++		{0x02fc, 0xa0}, {0x02fd, 0x32}, {0x0005, 0x77}, {0x0019, 0x2f},
++		{0x001a, 0x2f}, {0x008a, 0x33}, {0x008b, 0x33}, {0x008c, 0x33},
++		{0x00ba, 0x10}, {0x00d1, 0xff}, {0x00d6, 0xff}, {0x00db, 0xff},
++		{0x0048, 0x00}, {0x0049, 0x00}, {0x007a, 0x00}, {0x007b, 0x00},
++		{0x007c, 0x00}, {0x0080, 0x00}, {0x0081, 0x00}, {0x0082, 0x00},
++		{0x0083, 0xbb}, {0x0084, 0xb0}, {0x01a1, 0x88}, {0x01a4, 0x80},
++		{0x0088, 0x00}, {0x0089, 0x00}, {0x00a0, 0x02}, {0x00a1, 0x02},
++		{0x00a2, 0x02}, {0x00a4, 0x04}, {0x00a5, 0x04}, {0x00a6, 0x04},
++		{0x00ab, 0x00}, {0x00ad, 0x3f}, {0x00b7, 0x07}, {0x0062, 0x50},
++		{0x0000, 0x46}, {0x0000, 0x50}, {0x0000, 0x46}, {0x0000, 0x50},
++		{0x0000, 0x46}, {0x0000, 0x98}, {0x0059, 0x98}, {0x0061, 0x7c},
++		{0x01bc, 0x00}, {0x01bd, 0x00}, {0x01bb, 0x00}, {0x0085, 0xdd},
++		{0x0086, 0xdd}, {0x0087, 0x07}, {0x0090, 0x82}, {0x0091, 0x5e},
++		{0x0095, 0x5d}, {0x0096, 0xa9}, {0x0097, 0x00}, {0x009b, 0x00},
++		{0x00ae, 0x86}, {0x00af, 0x86}, {0x00b3, 0x67}, {0x00c4, 0xff},
++		{0x00c5, 0xff}, {0x00c9, 0xff}, {0x0040, 0x01}, {0x02fc, 0x00},
++		{0x02b3, 0x9a}, {0x02b4, 0x05}, {0x02cc, 0x01}, {0x02d0, 0x4c},
++		{0x02d2, 0x01}, {0x02db, 0x01}, {0x006f, 0x01}, {0x0070, 0x02},
++		{0x0071, 0x03}, {0x018b, 0x03}, {0x018c, 0x03},
++	};
++
++	for (size_t i = 0; i < ARRAY_SIZE(hwm_init_table); ++i)
++		ec_write(1, hwm_init_table[i].addr, hwm_init_table[i].val);
++}
++
++#define SCH555x_IOBASE	0x2e
++#define GLOBAL_DEV	PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_GLOBAL)
++#define SERIAL_DEV	PNP_DEV(SCH555x_IOBASE, SCH555x_LDN_UART1)
++
++void mainboard_config_superio(void)
++{
++	// Super I/O early init will map Runtime and EMI registers
++	sch555x_early_init(GLOBAL_DEV);
++
++	// Changes LED color among a few other things (extracted from Dell's FW)
++	outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_STS);
++	outb(0x00, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN);
++	outb(0x18, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_PME_EN1);
++	outb(0x01, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_UNK1);
++	outb(0x0f, SCH555x_RUNTIME_IOBASE + SCH555x_RUNTIME_LED);
++
++	// Magic EC init
++	ec_init();
++
++	// Magic EC init is needed for UART1 initialization to work
++	sch555x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
++}
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.default b/src/mainboard/dell/optiplex_9020/cmos.default
+new file mode 100644
+index 0000000000..b159660aa8
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/cmos.default
+@@ -0,0 +1,4 @@
++boot_option=Fallback
++debug_level=Debug
++nmi=Disable
++power_on_after_fail=Disable
+diff --git a/src/mainboard/dell/optiplex_9020/cmos.layout b/src/mainboard/dell/optiplex_9020/cmos.layout
+new file mode 100644
+index 0000000000..c9ba76c78f
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/cmos.layout
+@@ -0,0 +1,58 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	3	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	4	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	5	power_on_after_fail
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++
++2	0	Enable
++2	1	Disable
++
++3	0	Fallback
++3	1	Normal
++
++4	0	Emergency
++4	1	Alert
++4	2	Critical
++4	3	Error
++4	4	Warning
++4	5	Notice
++4	6	Info
++4	7	Debug
++4	8	Spew
++
++5	0	Disable
++5	1	Enable
++5	2	Keep
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 415 984
+diff --git a/src/mainboard/dell/optiplex_9020/data.vbt b/src/mainboard/dell/optiplex_9020/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..1779f3b8d1018ba0aae480103b145bd7b6dd6187
+GIT binary patch
+literal 4409
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+
+diff --git a/src/mainboard/dell/optiplex_9020/devicetree.cb b/src/mainboard/dell/optiplex_9020/devicetree.cb
+new file mode 100644
+index 0000000000..c0b17a15ff
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/devicetree.cb
+@@ -0,0 +1,80 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++chip northbridge/intel/haswell
++	# This mainboard has VGA
++	register "gpu_ddi_e_connected" = "1"
++
++	chip cpu/intel/haswell
++		device cpu_cluster 0 on ops haswell_cpu_bus_ops end
++	end
++
++	device domain 0 on
++		ops haswell_pci_domain_ops
++
++		subsystemid 0x1028 0x05a5 inherit
++
++		device pci 00.0 on  end					# Host bridge
++		device pci 01.0 on  end					# PCIe graphics
++		device pci 02.0 on  end					# VGA controller
++		device pci 03.0 on  end					# Mini-HD audio
++
++		chip southbridge/intel/lynxpoint
++			register "gen1_dec" = "0x007c0a01"
++			register "gen2_dec" = "0x007c0901"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x001c0901"
++			register "sata_port_map" = "0x33"
++
++			device pci 14.0 on  end				# xHCI controller
++			device pci 16.0 on  end				# Management Engine interface 1
++			device pci 16.1 off end				# Management Engine interface 2
++			device pci 16.2 off end				# Management Engine IDE-R
++			device pci 16.3 on  end				# Management Engine KT
++			device pci 19.0 on      			# Intel Gigabit Ethernet
++				subsystemid 0x1028 0x05a4
++			end
++			device pci 1a.0 on  end				# EHCI controller #2
++			device pci 1b.0 on  end				# HD audio controller
++			device pci 1c.0 off end
++			device pci 1c.1 off end
++			device pci 1c.2 off end
++			device pci 1c.3 off end
++			device pci 1c.4 on  end				# PCIe 4x slot
++			device pci 1c.5 off end
++			device pci 1c.6 off end
++			device pci 1c.7 off end
++			device pci 1d.0 on  end				# EHCI controller #1
++			device pci 1f.0 on				# LPC bridge
++				chip superio/smsc/sch555x
++					device pnp 2e.0 on		# EMI
++						io 0x60 = 0xa00
++					end
++					device pnp 2e.1 on		# 8042
++						io 0x60 = 0x60
++						irq 0x0f = 0
++						irq 0x70 = 1
++						irq 0x72 = 12
++					end
++					device pnp 2e.7 on		# UART1
++						io 0x60 = 0x3f8
++						irq 0x0f = 2
++						irq 0x70 = 4
++					end
++					device pnp 2e.8 off end 	# UART2
++					device pnp 2e.c on		# LPC interface
++						io 0x60 = 0x2e
++					end
++					device pnp 2e.a on		# Runtime registers
++						io 0x60 = 0xa40
++					end
++					device pnp 2e.b  off end	# Floppy Controller
++					device pnp 2e.11 off end	# Parallel Port
++				end
++			end
++			device pci 1f.2 on  end				# SATA controller 1
++			device pci 1f.3 on  end				# SMBus
++			device pci 1f.5 off end				# SATA controller 2
++			device pci 1f.6 off end				# Thermal
++		end
++	end
++end
+diff --git a/src/mainboard/dell/optiplex_9020/dsdt.asl b/src/mainboard/dell/optiplex_9020/dsdt.asl
+new file mode 100644
+index 0000000000..7ec1e9775a
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/dsdt.asl
+@@ -0,0 +1,25 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi.h>
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20181031	/* OEM Revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++	#include <cpu/intel/common/acpi/cpu.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
++		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/optiplex_9020/gma-mainboard.ads b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
+new file mode 100644
+index 0000000000..173f2f1d0d
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/gma-mainboard.ads
+@@ -0,0 +1,18 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (DP1,
++      DP2,
++      DP3,
++      Analog,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/optiplex_9020/gpio.c b/src/mainboard/dell/optiplex_9020/gpio.c
+new file mode 100644
+index 0000000000..48b7707e2c
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/gpio.c
+@@ -0,0 +1,217 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_GPIO,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_GPIO,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_GPIO,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_NATIVE,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_NATIVE,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_NATIVE,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_GPIO,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_GPIO,
++	.gpio26 = GPIO_MODE_GPIO,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_NATIVE,
++	.gpio30 = GPIO_MODE_NATIVE,
++	.gpio31 = GPIO_MODE_GPIO,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio1 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio5 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio11 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_OUTPUT,
++	.gpio15 = GPIO_DIR_OUTPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_OUTPUT,
++	.gpio23 = GPIO_DIR_OUTPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio25 = GPIO_DIR_OUTPUT,
++	.gpio26 = GPIO_DIR_OUTPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_OUTPUT,
++	.gpio31 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio13 = GPIO_LEVEL_LOW,
++	.gpio15 = GPIO_LEVEL_HIGH,
++	.gpio22 = GPIO_LEVEL_HIGH,
++	.gpio23 = GPIO_LEVEL_HIGH,
++	.gpio25 = GPIO_LEVEL_HIGH,
++	.gpio26 = GPIO_LEVEL_HIGH,
++	.gpio28 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++	.gpio18 = GPIO_BLINK,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio8 = GPIO_INVERT,
++	.gpio9 = GPIO_INVERT,
++	.gpio11 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++	.gpio26 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_GPIO,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_NATIVE,
++	.gpio37 = GPIO_MODE_NATIVE,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_GPIO,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_GPIO,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_GPIO,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_GPIO,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_GPIO,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio32 = GPIO_DIR_INPUT,
++	.gpio33 = GPIO_DIR_OUTPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio44 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio46 = GPIO_DIR_INPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_INPUT,
++	.gpio50 = GPIO_DIR_OUTPUT,
++	.gpio51 = GPIO_DIR_OUTPUT,
++	.gpio52 = GPIO_DIR_OUTPUT,
++	.gpio53 = GPIO_DIR_OUTPUT,
++	.gpio54 = GPIO_DIR_OUTPUT,
++	.gpio55 = GPIO_DIR_OUTPUT,
++	.gpio57 = GPIO_DIR_OUTPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio33 = GPIO_LEVEL_HIGH,
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio50 = GPIO_LEVEL_HIGH,
++	.gpio51 = GPIO_LEVEL_HIGH,
++	.gpio52 = GPIO_LEVEL_HIGH,
++	.gpio53 = GPIO_LEVEL_HIGH,
++	.gpio54 = GPIO_LEVEL_HIGH,
++	.gpio55 = GPIO_LEVEL_HIGH,
++	.gpio57 = GPIO_LEVEL_HIGH,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_GPIO,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_GPIO,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_NATIVE,
++	.gpio71 = GPIO_MODE_NATIVE,
++	.gpio72 = GPIO_MODE_GPIO,
++	.gpio73 = GPIO_MODE_GPIO,
++	.gpio74 = GPIO_MODE_GPIO,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio64 = GPIO_DIR_OUTPUT,
++	.gpio66 = GPIO_DIR_OUTPUT,
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio72 = GPIO_DIR_OUTPUT,
++	.gpio73 = GPIO_DIR_INPUT,
++	.gpio74 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++	.gpio64 = GPIO_LEVEL_HIGH,
++	.gpio66 = GPIO_LEVEL_HIGH,
++	.gpio72 = GPIO_LEVEL_HIGH,
++	.gpio74 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 =	{
++		.mode = &pch_gpio_set1_mode,
++		.direction = &pch_gpio_set1_direction,
++		.level = &pch_gpio_set1_level,
++		.blink = &pch_gpio_set1_blink,
++		.invert = &pch_gpio_set1_invert,
++		.reset = &pch_gpio_set1_reset,
++	},
++	.set2 =	{
++		.mode = &pch_gpio_set2_mode,
++		.direction = &pch_gpio_set2_direction,
++		.level = &pch_gpio_set2_level,
++		.reset = &pch_gpio_set2_reset,
++	},
++	.set3 =	{
++		.mode = &pch_gpio_set3_mode,
++		.direction = &pch_gpio_set3_direction,
++		.level = &pch_gpio_set3_level,
++		.reset = &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/optiplex_9020/hda_verb.c b/src/mainboard/dell/optiplex_9020/hda_verb.c
+new file mode 100644
+index 0000000000..df43ade3e6
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/hda_verb.c
+@@ -0,0 +1,27 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <stdint.h>
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x10ec0280, /* Realtek ALC3220 */
++	0x102805a5, /* Subsystem ID */
++	13,	 /* Number of entries */
++	AZALIA_SUBVENDOR(0, 0x102805a5),
++	AZALIA_PIN_CFG(0, 0x12, 0x4008c000),
++	AZALIA_PIN_CFG(0, 0x13, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x14, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x15, 0x0221401f),
++	AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x18, 0x01a13040),
++	AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
++	AZALIA_PIN_CFG(0, 0x1a, 0x02a19030),
++	AZALIA_PIN_CFG(0, 0x1b, 0x01014020),
++	AZALIA_PIN_CFG(0, 0x1d, 0x40400001),
++	AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
++};
++
++const u32 pc_beep_verbs[] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/optiplex_9020/mainboard.c b/src/mainboard/dell/optiplex_9020/mainboard.c
+new file mode 100644
+index 0000000000..c834fea5d3
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/mainboard.c
+@@ -0,0 +1,15 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++
++static void mainboard_enable(struct device *dev)
++{
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+diff --git a/src/mainboard/dell/optiplex_9020/overridetree_mt.cb b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
+new file mode 100644
+index 0000000000..90205c2d68
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/overridetree_mt.cb
+@@ -0,0 +1,10 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++chip northbridge/intel/haswell
++	device domain 0 on
++		chip southbridge/intel/lynxpoint
++			device pci 1c.1 on  end	# PCI (via XIO2001 bridge)
++			device pci 1c.2 on  end	# PCIe 1x slot
++		end
++	end
++end
+diff --git a/src/mainboard/dell/optiplex_9020/romstage.c b/src/mainboard/dell/optiplex_9020/romstage.c
+new file mode 100644
+index 0000000000..2b9cdaa5fd
+--- /dev/null
++++ b/src/mainboard/dell/optiplex_9020/romstage.c
+@@ -0,0 +1,53 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <northbridge/intel/haswell/haswell.h>
++#include <northbridge/intel/haswell/raminit.h>
++#include <southbridge/intel/lynxpoint/pch.h>
++
++void mainboard_config_rcba(void)
++{
++	RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQC, PIRQD, PIRQA);
++	RCBA16(D29IR) = DIR_ROUTE(PIRQC, PIRQA, PIRQD, PIRQH);
++	RCBA16(D28IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
++	RCBA16(D27IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQG);
++	RCBA16(D26IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQF, PIRQA);
++	RCBA16(D25IR) = DIR_ROUTE(PIRQH, PIRQG, PIRQF, PIRQE);
++	RCBA16(D22IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQA);
++	RCBA16(D20IR) = DIR_ROUTE(PIRQD, PIRQC, PIRQB, PIRQA);
++}
++
++void mb_get_spd_map(struct spd_info *spdi)
++{
++	spdi->addresses[0] = 0x50;
++	spdi->addresses[1] = 0x51;
++	spdi->addresses[2] = 0x52;
++	spdi->addresses[3] = 0x53;
++}
++
++const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = {
++	/* Length, Enable, OCn#, Location */
++	{0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
++	{0x0000, 0, USB_OC_PIN_SKIP, USB_PORT_SKIP},
++	{0x0040, 1, 1, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 2, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 3, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 3, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 0, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 0, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 4, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 4, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 5, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 5, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 6, USB_PORT_BACK_PANEL},
++	{0x0040, 1, 7, USB_PORT_BACK_PANEL},
++};
++
++const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = {
++	/* Enable, OCn# */
++	{1, 6},
++	{1, 7},
++	{0, USB_OC_PIN_SKIP},
++	{0, USB_OC_PIN_SKIP},
++	{1, 1},
++	{1, 2},
++};
+-- 
+2.39.2
+

config/coreboot/default/patches/0032-mb-dell-Add-Latitude-E6420-Sandy-Bridge.patch

@@ -0,0 +1,774 @@
+From 41002e64c92e90903fa591c4a8a1cc0108833743 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sun, 26 Nov 2023 17:08:52 -0700
+Subject: [PATCH] mb/dell: Add Latitude E6420 (Sandy Bridge)
+
+Change-Id: Ic48d9ea58172a5b13958c8afebcb19c8929c4394
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6420/Kconfig           |  38 ++++
+ src/mainboard/dell/e6420/Kconfig.name      |   2 +
+ src/mainboard/dell/e6420/Makefile.inc      |   6 +
+ src/mainboard/dell/e6420/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e6420/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e6420/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e6420/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e6420/board_info.txt    |   6 +
+ src/mainboard/dell/e6420/cmos.default      |   9 +
+ src/mainboard/dell/e6420/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e6420/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e6420/devicetree.cb     |  66 +++++++
+ src/mainboard/dell/e6420/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e6420/early_init.c      |  32 ++++
+ src/mainboard/dell/e6420/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e6420/gpio.c            | 191 +++++++++++++++++++++
+ src/mainboard/dell/e6420/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e6420/mainboard.c       |  21 +++
+ 18 files changed, 582 insertions(+)
+ create mode 100644 src/mainboard/dell/e6420/Kconfig
+ create mode 100644 src/mainboard/dell/e6420/Kconfig.name
+ create mode 100644 src/mainboard/dell/e6420/Makefile.inc
+ create mode 100644 src/mainboard/dell/e6420/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e6420/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e6420/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e6420/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e6420/board_info.txt
+ create mode 100644 src/mainboard/dell/e6420/cmos.default
+ create mode 100644 src/mainboard/dell/e6420/cmos.layout
+ create mode 100644 src/mainboard/dell/e6420/data.vbt
+ create mode 100644 src/mainboard/dell/e6420/devicetree.cb
+ create mode 100644 src/mainboard/dell/e6420/dsdt.asl
+ create mode 100644 src/mainboard/dell/e6420/early_init.c
+ create mode 100644 src/mainboard/dell/e6420/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e6420/gpio.c
+ create mode 100644 src/mainboard/dell/e6420/hda_verb.c
+ create mode 100644 src/mainboard/dell/e6420/mainboard.c
+
+diff --git a/src/mainboard/dell/e6420/Kconfig b/src/mainboard/dell/e6420/Kconfig
+new file mode 100644
+index 0000000000..cff62bf70c
+--- /dev/null
++++ b/src/mainboard/dell/e6420/Kconfig
+@@ -0,0 +1,38 @@
++if BOARD_DELL_LATITUDE_E6420
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_10240
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_BD82X6X
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e6420"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E6420"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0126"
++
++endif # BOARD_DELL_LATITUDE_E6420
+diff --git a/src/mainboard/dell/e6420/Kconfig.name b/src/mainboard/dell/e6420/Kconfig.name
+new file mode 100644
+index 0000000000..1722891e7b
+--- /dev/null
++++ b/src/mainboard/dell/e6420/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E6420
++	bool "Latitude E6420"
+diff --git a/src/mainboard/dell/e6420/Makefile.inc b/src/mainboard/dell/e6420/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e6420/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6420/acpi/ec.asl b/src/mainboard/dell/e6420/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e6420/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6420/acpi/platform.asl b/src/mainboard/dell/e6420/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e6420/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e6420/acpi/superio.asl b/src/mainboard/dell/e6420/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e6420/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e6420/acpi_tables.c b/src/mainboard/dell/e6420/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e6420/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e6420/board_info.txt b/src/mainboard/dell/e6420/board_info.txt
+new file mode 100644
+index 0000000000..34d5ad9e0b
+--- /dev/null
++++ b/src/mainboard/dell/e6420/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2011
+diff --git a/src/mainboard/dell/e6420/cmos.default b/src/mainboard/dell/e6420/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e6420/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e6420/cmos.layout b/src/mainboard/dell/e6420/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e6420/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e6420/data.vbt b/src/mainboard/dell/e6420/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..d3662eea1bc78b60be6d0bd2cc38bb46b654afbd
+GIT binary patch
+literal 6144
+zcmeHKeQZ-z6hE);wSBvNZ|mO1=*HLC2BQN8uVX6{N9eY)75ORymb$R8!YYuAZEgeE
+zKk|S@Fen*n41W-viAF;r%)~^EkpLz-B{2q##)LmGAtoY;7*Qhv_1yPbw$TC$2}G0K
+z=6Ao&x#ym9?z!i_&TOh(kLzky2cN8MTpny#R<;VU4Rkn?rBIz(YL~BBw<%b&zGhSH
+z$~AQ>@D0d=Xx6RE0BwSxspWdrW9y<FZGD@&x3_JL;p$p!;!BVdcKLkht0=-%(Jj&T
+z_GkyztZ%>#t7^)^(T-R<7W?O6ZTI%A+j=`<Jw3Q%dk6N!da<_?7oyiU3)^<~_TiSk
+zE$y+=RK3PGQ`gzmXYPRBx>C|f*UP9{h|4>ANrAe~?ymV*)83AaT#FuTjP=C2cg5P~
+zt4w78r$t#300cWY_k)mevmAmFI3&oBfytoAAPQiYK$XEIgHwV@5-gJ-Q-*p8yfTDj
+zaDz=1Y!X1B3`OpQ&Ik}bM|0xHn0gYNZw0rT=7AXS2in-q8K^?)0|el+Z6geW7i7MM
+zv~!|>HqL-|Fk}EYOa@)R<X)VQ7c}d8R1b@RTn5rq(90|QRg0?wwZZz(6Dz}w>zg9Y
+z8;!mD_V*XSjT33~$`o`s>zEGBq8AQ`HaH?y!Fh2QiX1v@aCo4LaENf&DZ_cE2A2qb
+z5@cC}X)=S^1RvpXLWs~v*hqMau$!=t@B-mg!XV)|;eEm>!Z6`H;R4|&!d1d`f|S7^
+zli+B98*!TfPE&6~NVM5j3v{N3OTjpnm_L@BPh(}esd(J!gj?~iJP?n|OZZOiTqlql
+zg<NWR@g&-*W-E%A7|*1Z_`sVO$K&iAP+VIj9{<1hT%SXsK}IBk8!daftR`6-)EUiS
+zvv*HR(#-ZwhA~7wcmxbe4%E?Y7P0y{1q|nqR1L29UR8v@#No^g5MH)7!>{%-$T|cR
+zZx5|xm>Fl>;@$m};P{0WC>O~<Nl1`*PLgPN_hP2a^h+L$ls&SYrkDYr+&l*%%S?^Q
+ziPSdtHE<LNEnr7cs=ihL-C>-p>*$9CpHRLgN|POkqD^UP4nw|4nf0bc8MOBk<;%js
+zfpCAWNzqSPlz@X%j9CGrwZDKUl@K{g6pzqiIIARDQ)#@^RW&0pmNG;XZ?!SlHB?L#
+zKRAMgq(R;aQd%@Gy38-LS@ix)fR**(P3B9wI=Uk^&cWmmwB<vf21<0#LBA!;qtAh(
+zYe5g_T{+gw^mi8QzPPraBoH~8oCz%r=$nVi1A)`Y8IKqIdqm6MihqxtpFaTggaPxu
+zQP07nf#&kPkPp}Cmk$F1g7q7QK;kz~80i&oDN}~wYbPUI6AtG5H+$T!@f5FzUhp21
+z^XiPT3rb%B@sA9g!n88R7BOsLS|?+D3}0v3dyIX|@JFWo&e%<c#V)PV#g@7-=F*;V
+zvAr&Q+ogTvVxPM3XP5Smi`f;Nt7uCU)}Y`HMcbpW=M_AuXlE35PQl+4O{7m66&I@7
+zGL@}Sai^*sP}va`KTx$VRQ8REf2*1+lTFH0=UkNx+eN|1rVyipl)Du=h=@%w+iQZG
+zT6@-PdW^oyFb44AG`HMZWEnP{&OQ+jC`N4emoS)x;EPN}uaSFOf-Mn8JRRO&LTWJc
+zn6%=L94~PR)%Ua_HTZcfTXD<p{%8p|<N<;Efw$Zb4$}{m8@7c((~<7^thaau&@Wx#
+zVGNL)lmH@{o=h*{muXGc!;nXrVgpp3;1V1stMj=4AtxyzX+?SoB~zN}!*r?9Qvs1P
+zmV_(CTmt0sY&6=F=_M>E34GYvuh1uQF+BUdWyQC5SaEM1QvKlHBMs13C}n{0SwRxW
+ziekMa&kvRFruRcKCevGy5)TxUBDlur@E{TtQ^NQ>nO+Cgl)&Ga(PxqVW?e3TLH-UY
+zdL3T{z^xdd`$(STFUb8R*cKa}r>n{Wk+MXRH~o-hN}#9OF*>T#>rfhiRs(Wc-R^9@
+z%F=<}dn(E}ADc03zJ>JvZe;_8f+WFLL4%qNYs`_aa`a$Pl5H;iO^Wt*cP3W(d=(g}
+zZ%nKT1$|r-tAv8($u2-BI2Uiz#%OT&!Q3b~Ru2P2j;Gem!@wfPsTR%J>W{8z)oq^J
+k^Qm&?O@bFkw4CTocwoW<6CRlGz=Q`TJTT#bN9KWl0rH4|j{pDw
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e6420/devicetree.cb b/src/mainboard/dell/e6420/devicetree.cb
+new file mode 100644
+index 0000000000..f9259f7175
+--- /dev/null
++++ b/src/mainboard/dell/e6420/devicetree.cb
+@@ -0,0 +1,66 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x0000054f"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x0493 inherit
++
++		device ref host_bridge on end # Host bridge
++		device ref peg10 on end # PEG
++		device ref igd on end # iGPU
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x007c0901"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x001c0901"
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x3b"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++
++			device ref mei1		off end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	off end
++			device ref gbe		on end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end
++			device ref pcie_rp2	on end
++			device ref pcie_rp3	on end
++			device ref pcie_rp4	on end
++			device ref pcie_rp5	off end
++			device ref pcie_rp6	on end
++			device ref pcie_rp7	off end
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1 on end
++			device ref smbus on end
++			device ref sata2 off end
++			device ref thermal off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e6420/dsdt.asl b/src/mainboard/dell/e6420/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e6420/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e6420/early_init.c b/src/mainboard/dell/e6420/early_init.c
+new file mode 100644
+index 0000000000..0682441ed6
+--- /dev/null
++++ b/src/mainboard/dell/e6420/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 0, 2 },
++	{ 1, 1, 2 },
++	{ 1, 1, 3 },
++	{ 1, 1, 3 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 1, 7 },
++	{ 1, 1, 6 },
++	{ 1, 0, 6 },
++	{ 1, 0, 7 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e6420/gma-mainboard.ads b/src/mainboard/dell/e6420/gma-mainboard.ads
+new file mode 100644
+index 0000000000..2a16f44360
+--- /dev/null
++++ b/src/mainboard/dell/e6420/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, -- mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e6420/gpio.c b/src/mainboard/dell/e6420/gpio.c
+new file mode 100644
+index 0000000000..943c743f48
+--- /dev/null
++++ b/src/mainboard/dell/e6420/gpio.c
+@@ -0,0 +1,191 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_NATIVE,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_NATIVE,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_GPIO,
++	.gpio31 = GPIO_MODE_GPIO,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_INPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++	.gpio30 = GPIO_DIR_OUTPUT,
++	.gpio31 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio30 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_NATIVE,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_OUTPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio49 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_NATIVE,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e6420/hda_verb.c b/src/mainboard/dell/e6420/hda_verb.c
+new file mode 100644
+index 0000000000..b3803b7c65
+--- /dev/null
++++ b/src/mainboard/dell/e6420/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
++	0x10280493,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x10280493),
++	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0xd5a30130),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862805,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e6420/mainboard.c b/src/mainboard/dell/e6420/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e6420/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.43.0
+

config/coreboot/default/patches/0033-mb-dell-Add-Latitude-E6520-Sandy-Bridge.patch

@@ -0,0 +1,773 @@
+From 5e8bff81220d4d0f663feed443e4594b76e442bf Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Wed, 31 Jan 2024 22:07:25 -0700
+Subject: [PATCH] mb/dell: Add Latitude E6520 (Sandy Bridge)
+
+Change-Id: Ibdd40cc15642b8d404159d5962670ccc4167a9ec
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6520/Kconfig           |  38 +++++
+ src/mainboard/dell/e6520/Kconfig.name      |   2 +
+ src/mainboard/dell/e6520/Makefile.inc      |   6 +
+ src/mainboard/dell/e6520/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e6520/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e6520/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e6520/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e6520/board_info.txt    |   6 +
+ src/mainboard/dell/e6520/cmos.default      |   9 +
+ src/mainboard/dell/e6520/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e6520/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e6520/devicetree.cb     |  66 +++++++
+ src/mainboard/dell/e6520/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e6520/early_init.c      |  32 ++++
+ src/mainboard/dell/e6520/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e6520/gpio.c            | 190 +++++++++++++++++++++
+ src/mainboard/dell/e6520/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e6520/mainboard.c       |  21 +++
+ 18 files changed, 581 insertions(+)
+ create mode 100644 src/mainboard/dell/e6520/Kconfig
+ create mode 100644 src/mainboard/dell/e6520/Kconfig.name
+ create mode 100644 src/mainboard/dell/e6520/Makefile.inc
+ create mode 100644 src/mainboard/dell/e6520/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e6520/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e6520/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e6520/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e6520/board_info.txt
+ create mode 100644 src/mainboard/dell/e6520/cmos.default
+ create mode 100644 src/mainboard/dell/e6520/cmos.layout
+ create mode 100644 src/mainboard/dell/e6520/data.vbt
+ create mode 100644 src/mainboard/dell/e6520/devicetree.cb
+ create mode 100644 src/mainboard/dell/e6520/dsdt.asl
+ create mode 100644 src/mainboard/dell/e6520/early_init.c
+ create mode 100644 src/mainboard/dell/e6520/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e6520/gpio.c
+ create mode 100644 src/mainboard/dell/e6520/hda_verb.c
+ create mode 100644 src/mainboard/dell/e6520/mainboard.c
+
+diff --git a/src/mainboard/dell/e6520/Kconfig b/src/mainboard/dell/e6520/Kconfig
+new file mode 100644
+index 0000000000..db9f25b4ac
+--- /dev/null
++++ b/src/mainboard/dell/e6520/Kconfig
+@@ -0,0 +1,38 @@
++if BOARD_DELL_LATITUDE_E6520
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_10240
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select MAINBOARD_USES_IFD_GBE_REGION
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_BD82X6X
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e6520"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E6520"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0116"
++
++endif # BOARD_DELL_LATITUDE_E6520
+diff --git a/src/mainboard/dell/e6520/Kconfig.name b/src/mainboard/dell/e6520/Kconfig.name
+new file mode 100644
+index 0000000000..25968e80e5
+--- /dev/null
++++ b/src/mainboard/dell/e6520/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E6520
++	bool "Latitude E6520"
+diff --git a/src/mainboard/dell/e6520/Makefile.inc b/src/mainboard/dell/e6520/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e6520/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e6520/acpi/ec.asl b/src/mainboard/dell/e6520/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e6520/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e6520/acpi/platform.asl b/src/mainboard/dell/e6520/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e6520/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e6520/acpi/superio.asl b/src/mainboard/dell/e6520/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e6520/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e6520/acpi_tables.c b/src/mainboard/dell/e6520/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e6520/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e6520/board_info.txt b/src/mainboard/dell/e6520/board_info.txt
+new file mode 100644
+index 0000000000..34d5ad9e0b
+--- /dev/null
++++ b/src/mainboard/dell/e6520/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2011
+diff --git a/src/mainboard/dell/e6520/cmos.default b/src/mainboard/dell/e6520/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e6520/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e6520/cmos.layout b/src/mainboard/dell/e6520/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e6520/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e6520/data.vbt b/src/mainboard/dell/e6520/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..0ef16ee7cb482d2cb91ea80c3f419759355f7ba0
+GIT binary patch
+literal 6144
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+z@Y6|P8fx#li}c`Uv24UGyZaM0To;Ep<_AWZA1t~bFgI)uf}&Eq=L_Cs89=>wnT0Vx
+z-jp>o1ffJNommZ4?=TIPlePIw0hgQ706f*tBC`#pg>9&zRHe>J2%RxBTrOc6Adh9E
+ziJr`?VQH!N!_GkoKaoq|+3$^Ae0#sUxXlmM1Huq~g<=Ls?ILv+nQcH%PQedGOlH=Q
+z77rMcJlH4Mkc#U2(IDv>rsm1aHpsdL_RdT^i_ACcQUMIJcSus}*(?CIiy^#^=t=g1
+z+*^Zbh30&^#_bKclSy9pL$<B~pK8m*sLpIdnHM@W$nA7Ea@Z`x27K?aNK<@lCW(2L
+zb@kB3H8kKy4W3Hu)NN|kd!DL^o#iR9a{QYV-Wl&r&hmIFX{ezkIV<4zFiVUQ@K>ao
+z00DnFy~Uek!JRwhVX!of0)$Sa*X^S~LMQH0<E(UUx}L=|;Kgw(r(4q=nD)T52c|tR
+O?SW|zOncy=dEg(6JAK&z
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e6520/devicetree.cb b/src/mainboard/dell/e6520/devicetree.cb
+new file mode 100644
+index 0000000000..cfba8ef4e7
+--- /dev/null
++++ b/src/mainboard/dell/e6520/devicetree.cb
+@@ -0,0 +1,66 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00001312"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x0494 inherit
++
++		device ref host_bridge on end # Host bridge
++		device ref peg10 on end # PEG
++		device ref igd on end # iGPU
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x007c0901"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x001c0901"
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x3b"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++
++			device ref mei1		off end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	off end
++			device ref gbe		on end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end
++			device ref pcie_rp2	on end
++			device ref pcie_rp3	on end
++			device ref pcie_rp4	on end
++			device ref pcie_rp5	off end
++			device ref pcie_rp6	on end
++			device ref pcie_rp7	off end
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1 on end
++			device ref smbus on end
++			device ref sata2 off end
++			device ref thermal off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e6520/dsdt.asl b/src/mainboard/dell/e6520/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e6520/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e6520/early_init.c b/src/mainboard/dell/e6520/early_init.c
+new file mode 100644
+index 0000000000..2a37091df6
+--- /dev/null
++++ b/src/mainboard/dell/e6520/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 0, 2 },
++	{ 1, 1, 2 },
++	{ 1, 0, 3 },
++	{ 1, 0, 3 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 1, 7 },
++	{ 1, 1, 6 },
++	{ 1, 0, 6 },
++	{ 1, 0, 7 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e6520/gma-mainboard.ads b/src/mainboard/dell/e6520/gma-mainboard.ads
+new file mode 100644
+index 0000000000..2a16f44360
+--- /dev/null
++++ b/src/mainboard/dell/e6520/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, -- mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e6520/gpio.c b/src/mainboard/dell/e6520/gpio.c
+new file mode 100644
+index 0000000000..61f01816c4
+--- /dev/null
++++ b/src/mainboard/dell/e6520/gpio.c
+@@ -0,0 +1,190 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_NATIVE,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_NATIVE,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_NATIVE,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_GPIO,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_INPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++	.gpio30 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio30 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_NATIVE,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_OUTPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_HIGH,
++	.gpio45 = GPIO_LEVEL_LOW,
++	.gpio49 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_NATIVE,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e6520/hda_verb.c b/src/mainboard/dell/e6520/hda_verb.c
+new file mode 100644
+index 0000000000..d33eb3b4c5
+--- /dev/null
++++ b/src/mainboard/dell/e6520/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
++	0x10280494,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x10280494),
++	AZALIA_PIN_CFG(0, 0x0a, 0x03a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0321101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0x400000f2),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862805,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e6520/mainboard.c b/src/mainboard/dell/e6520/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e6520/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.43.0
+

config/coreboot/default/patches/0034-mb-dell-Add-Latitude-E5530-Ivy-Bridge.patch

@@ -0,0 +1,780 @@
+From 86911e57c556389eed386bc23d5e87dd520afec9 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Wed, 31 Jan 2024 22:57:07 -0700
+Subject: [PATCH] mb/dell: Add Latitude E5530 (Ivy Bridge)
+
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e5530/Kconfig           |  37 ++++
+ src/mainboard/dell/e5530/Kconfig.name      |   2 +
+ src/mainboard/dell/e5530/Makefile.inc      |   6 +
+ src/mainboard/dell/e5530/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e5530/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e5530/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e5530/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e5530/board_info.txt    |   6 +
+ src/mainboard/dell/e5530/cmos.default      |   9 +
+ src/mainboard/dell/e5530/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e5530/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e5530/devicetree.cb     |  70 ++++++++
+ src/mainboard/dell/e5530/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e5530/early_init.c      |  32 ++++
+ src/mainboard/dell/e5530/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e5530/gpio.c            | 194 +++++++++++++++++++++
+ src/mainboard/dell/e5530/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e5530/mainboard.c       |  21 +++
+ 18 files changed, 588 insertions(+)
+ create mode 100644 src/mainboard/dell/e5530/Kconfig
+ create mode 100644 src/mainboard/dell/e5530/Kconfig.name
+ create mode 100644 src/mainboard/dell/e5530/Makefile.inc
+ create mode 100644 src/mainboard/dell/e5530/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e5530/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e5530/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e5530/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e5530/board_info.txt
+ create mode 100644 src/mainboard/dell/e5530/cmos.default
+ create mode 100644 src/mainboard/dell/e5530/cmos.layout
+ create mode 100644 src/mainboard/dell/e5530/data.vbt
+ create mode 100644 src/mainboard/dell/e5530/devicetree.cb
+ create mode 100644 src/mainboard/dell/e5530/dsdt.asl
+ create mode 100644 src/mainboard/dell/e5530/early_init.c
+ create mode 100644 src/mainboard/dell/e5530/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e5530/gpio.c
+ create mode 100644 src/mainboard/dell/e5530/hda_verb.c
+ create mode 100644 src/mainboard/dell/e5530/mainboard.c
+
+diff --git a/src/mainboard/dell/e5530/Kconfig b/src/mainboard/dell/e5530/Kconfig
+new file mode 100644
+index 0000000000..3faae4ee50
+--- /dev/null
++++ b/src/mainboard/dell/e5530/Kconfig
+@@ -0,0 +1,37 @@
++if BOARD_DELL_LATITUDE_E5530
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_12288
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_C216
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e5530"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E5530"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0166"
++
++endif # BOARD_DELL_LATITUDE_E5530
+diff --git a/src/mainboard/dell/e5530/Kconfig.name b/src/mainboard/dell/e5530/Kconfig.name
+new file mode 100644
+index 0000000000..775963204a
+--- /dev/null
++++ b/src/mainboard/dell/e5530/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E5530
++	bool "Latitude E5530"
+diff --git a/src/mainboard/dell/e5530/Makefile.inc b/src/mainboard/dell/e5530/Makefile.inc
+new file mode 100644
+index 0000000000..ba64e93eb8
+--- /dev/null
++++ b/src/mainboard/dell/e5530/Makefile.inc
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0-only
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e5530/acpi/ec.asl b/src/mainboard/dell/e5530/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e5530/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e5530/acpi/platform.asl b/src/mainboard/dell/e5530/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e5530/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e5530/acpi/superio.asl b/src/mainboard/dell/e5530/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e5530/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e5530/acpi_tables.c b/src/mainboard/dell/e5530/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e5530/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e5530/board_info.txt b/src/mainboard/dell/e5530/board_info.txt
+new file mode 100644
+index 0000000000..4601a4aaba
+--- /dev/null
++++ b/src/mainboard/dell/e5530/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2012
+diff --git a/src/mainboard/dell/e5530/cmos.default b/src/mainboard/dell/e5530/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e5530/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e5530/cmos.layout b/src/mainboard/dell/e5530/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e5530/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e5530/data.vbt b/src/mainboard/dell/e5530/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..3c54b70be7856a6420d001112d7f17f8bab46ed3
+GIT binary patch
+literal 6144
+zcmeHKU2Gdg5dO}0w$JA~+qs02q)iz56C9e5vuQ#oL0l3O+%|395Q2peO{y4(2uX0t
+zuMja1N)bPb1cE+5)fYsCK!89MFQAGChyWpk5PuR<K|G+sLmxmOR4}u5=Rg`mj70g7
+zvgdDic6N4dW^QKhynd)>kS^cR)3#-(r*-?zo-O^C(kLvv8XM<+Y3tdt^YY!P?!oTe
+zJ^ed-x6w0Lh5fN#jsv5TWE#mtd*_yky}9xDK(kOwLt+C7_AQAd#iwr=o0`gvQZ`{x
+z6ZeT`x^^;8+a~jSa^o~PF@8J6N5;o#dhCwebaM;!_oisw1#O9K={qQM<@Oeu$lXeN
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+Jz~2*rUjdP?m;3+#
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e5530/devicetree.cb b/src/mainboard/dell/e5530/devicetree.cb
+new file mode 100644
+index 0000000000..2af748cf27
+--- /dev/null
++++ b/src/mainboard/dell/e5530/devicetree.cb
+@@ -0,0 +1,70 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00000000"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x03d003d0"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x053d inherit
++
++		device ref host_bridge on end
++		device ref peg10 off end
++		device ref igd on end
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x005c0921"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x00000911" # Ports 0x910/0x911 for EC
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 1, 0, 0, 0, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x33"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++			register "superspeed_capable_ports" = "0x0000000f"
++			register "xhci_overcurrent_mapping" = "0x00000c03"
++			register "xhci_switchable_ports" = "0x0000000f"
++
++			device ref xhci		on end
++			device ref mei1		off end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	off end
++			device ref gbe		off end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end # WWAN Slot
++			device ref pcie_rp2	on end # SLAN Slot
++			device ref pcie_rp3	on end # ExpressCard
++			device ref pcie_rp4	off end
++			device ref pcie_rp5	on end # Extra Half Mini PCIe slot
++			device ref pcie_rp6	on end # SD/MMC Card Reader
++			device ref pcie_rp7	on end # BCM5761 Ethernet
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1	on end
++			device ref smbus	on end
++			device ref sata2	off end
++			device ref thermal	off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e5530/dsdt.asl b/src/mainboard/dell/e5530/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e5530/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e5530/early_init.c b/src/mainboard/dell/e5530/early_init.c
+new file mode 100644
+index 0000000000..00fd5f6795
+--- /dev/null
++++ b/src/mainboard/dell/e5530/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 1, 2 },
++	{ 1, 1, 2 },
++	{ 1, 1, 3 },
++	{ 1, 0, 3 },
++	{ 1, 2, 4 },
++	{ 1, 1, 4 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 0, 6 },
++	{ 1, 1, 6 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e5530/gma-mainboard.ads b/src/mainboard/dell/e5530/gma-mainboard.ads
+new file mode 100644
+index 0000000000..1310830c8e
+--- /dev/null
++++ b/src/mainboard/dell/e5530/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, --mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e5530/gpio.c b/src/mainboard/dell/e5530/gpio.c
+new file mode 100644
+index 0000000000..0599f13921
+--- /dev/null
++++ b/src/mainboard/dell/e5530/gpio.c
+@@ -0,0 +1,194 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_GPIO,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_GPIO,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_GPIO,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_NATIVE,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio1 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio12 = GPIO_DIR_OUTPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio16 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_OUTPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio12 = GPIO_LEVEL_HIGH,
++	.gpio28 = GPIO_LEVEL_LOW,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++	.gpio30 = GPIO_RESET_RSMRST,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio13 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_GPIO,
++	.gpio46 = GPIO_MODE_NATIVE,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_GPIO,
++	.gpio50 = GPIO_MODE_NATIVE,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_GPIO,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_NATIVE,
++	.gpio56 = GPIO_MODE_NATIVE,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_INPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_INPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio45 = GPIO_DIR_INPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio49 = GPIO_DIR_INPUT,
++	.gpio51 = GPIO_DIR_INPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio53 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_GPIO,
++	.gpio69 = GPIO_MODE_GPIO,
++	.gpio70 = GPIO_MODE_GPIO,
++	.gpio71 = GPIO_MODE_GPIO,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_GPIO,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio68 = GPIO_DIR_INPUT,
++	.gpio69 = GPIO_DIR_INPUT,
++	.gpio70 = GPIO_DIR_INPUT,
++	.gpio71 = GPIO_DIR_INPUT,
++	.gpio74 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e5530/hda_verb.c b/src/mainboard/dell/e5530/hda_verb.c
+new file mode 100644
+index 0000000000..4c7c36ee05
+--- /dev/null
++++ b/src/mainboard/dell/e5530/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76df,	/* Codec Vendor / Device ID: IDT */
++	0x1028053d,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x1028053d),
++	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0xd5a301a0),
++
++	0x80862806,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e5530/mainboard.c b/src/mainboard/dell/e5530/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e5530/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.43.0
+

config/coreboot/default/patches/0035-hp8560w-Add-MXM-System-Infomation-Structure.patch

@@ -0,0 +1,41 @@
+From b2cf0657a2058118baf6f4ec96e356de3c9e493e Mon Sep 17 00:00:00 2001
+From: Riku Viitanen <riku.viitanen@protonmail.com>
+Date: Sun, 11 Feb 2024 19:02:20 +0200
+Subject: [PATCH] hp8560w: Add MXM System Infomation Structure
+
+Change-Id: I45b421f2d7baf8ca8dedbd3b1ab1e38392b6219b
+Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
+---
+ src/mainboard/hp/snb_ivb_laptops/Makefile.mk      |   6 ++++++
+ .../hp/snb_ivb_laptops/variants/8560w/mxm-30-sis  | Bin 0 -> 129 bytes
+ 2 files changed, 6 insertions(+)
+ create mode 100644 src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
+
+diff --git a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
+index c007bb68cd..7950abbc4e 100644
+--- a/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
++++ b/src/mainboard/hp/snb_ivb_laptops/Makefile.mk
+@@ -9,3 +9,9 @@ ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainb
+ 
+ # FIXME: Other variants with same size onboard RAM may exist.
+ SPD_SOURCES = hynix_4g
++
++ifeq ($(CONFIG_BOARD_HP_8560W),y)
++cbfs-files-y += mxm-30-sis
++mxm-30-sis-file := variants/$(VARIANT_DIR)/mxm-30-sis
++mxm-30-sis-type := raw
++endif
+diff --git a/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis b/src/mainboard/hp/snb_ivb_laptops/variants/8560w/mxm-30-sis
+new file mode 100644
+index 0000000000000000000000000000000000000000..7e4e245a50d8d5d36ddb22e3b1aed3fa87a2f57d
+GIT binary patch
+literal 129
+zcmeZ`@Qr6?sAMn@-0}aX9Rou`%?mKiz;Fq|&xF!hw;=rNM_^h3Dy{$(SAdE$zF=lx
+o@?l{RW{6;7W}LwIl$Vj2apDSgHUS2PJFE;0Kxqas5d=FN0HAs+0RR91
+
+literal 0
+HcmV?d00001
+
+-- 
+2.43.1
+

config/coreboot/default/patches/0035-mb-dell-Add-Latitude-E5520-Sandybridge.patch

@@ -0,0 +1,775 @@
+From 7c7ce2087e1ff5f0eedb65793254163d01be3056 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Wed, 7 Feb 2024 10:23:38 -0700
+Subject: [PATCH] mb/dell: Add Latitude E5520 (Sandybridge)
+
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e5520/Kconfig           |  37 ++++
+ src/mainboard/dell/e5520/Kconfig.name      |   2 +
+ src/mainboard/dell/e5520/Makefile.inc      |   5 +
+ src/mainboard/dell/e5520/acpi/ec.asl       |   9 +
+ src/mainboard/dell/e5520/acpi/platform.asl |  12 ++
+ src/mainboard/dell/e5520/acpi/superio.asl  |   3 +
+ src/mainboard/dell/e5520/acpi_tables.c     |  16 ++
+ src/mainboard/dell/e5520/board_info.txt    |   6 +
+ src/mainboard/dell/e5520/cmos.default      |   9 +
+ src/mainboard/dell/e5520/cmos.layout       |  88 ++++++++++
+ src/mainboard/dell/e5520/data.vbt          | Bin 0 -> 6144 bytes
+ src/mainboard/dell/e5520/devicetree.cb     |  66 +++++++
+ src/mainboard/dell/e5520/dsdt.asl          |  30 ++++
+ src/mainboard/dell/e5520/early_init.c      |  32 ++++
+ src/mainboard/dell/e5520/gma-mainboard.ads |  20 +++
+ src/mainboard/dell/e5520/gpio.c            | 195 +++++++++++++++++++++
+ src/mainboard/dell/e5520/hda_verb.c        |  33 ++++
+ src/mainboard/dell/e5520/mainboard.c       |  21 +++
+ 18 files changed, 584 insertions(+)
+ create mode 100644 src/mainboard/dell/e5520/Kconfig
+ create mode 100644 src/mainboard/dell/e5520/Kconfig.name
+ create mode 100644 src/mainboard/dell/e5520/Makefile.inc
+ create mode 100644 src/mainboard/dell/e5520/acpi/ec.asl
+ create mode 100644 src/mainboard/dell/e5520/acpi/platform.asl
+ create mode 100644 src/mainboard/dell/e5520/acpi/superio.asl
+ create mode 100644 src/mainboard/dell/e5520/acpi_tables.c
+ create mode 100644 src/mainboard/dell/e5520/board_info.txt
+ create mode 100644 src/mainboard/dell/e5520/cmos.default
+ create mode 100644 src/mainboard/dell/e5520/cmos.layout
+ create mode 100644 src/mainboard/dell/e5520/data.vbt
+ create mode 100644 src/mainboard/dell/e5520/devicetree.cb
+ create mode 100644 src/mainboard/dell/e5520/dsdt.asl
+ create mode 100644 src/mainboard/dell/e5520/early_init.c
+ create mode 100644 src/mainboard/dell/e5520/gma-mainboard.ads
+ create mode 100644 src/mainboard/dell/e5520/gpio.c
+ create mode 100644 src/mainboard/dell/e5520/hda_verb.c
+ create mode 100644 src/mainboard/dell/e5520/mainboard.c
+
+diff --git a/src/mainboard/dell/e5520/Kconfig b/src/mainboard/dell/e5520/Kconfig
+new file mode 100644
+index 0000000000..213c54cf5c
+--- /dev/null
++++ b/src/mainboard/dell/e5520/Kconfig
+@@ -0,0 +1,37 @@
++if BOARD_DELL_LATITUDE_E5520
++
++config BOARD_SPECIFIC_OPTIONS
++	def_bool y
++	select BOARD_ROMSIZE_KB_6144
++	select EC_ACPI
++	select EC_DELL_MEC5035
++	select GFX_GMA_PANEL_1_ON_LVDS
++	select HAVE_ACPI_RESUME
++	select HAVE_ACPI_TABLES
++	select HAVE_CMOS_DEFAULT
++	select HAVE_OPTION_TABLE
++	select INTEL_GMA_HAVE_VBT
++	select INTEL_INT15
++	select MAINBOARD_HAS_LIBGFXINIT
++	select NORTHBRIDGE_INTEL_SANDYBRIDGE
++	select SERIRQ_CONTINUOUS_MODE
++	select SOUTHBRIDGE_INTEL_BD82X6X
++	select SYSTEM_TYPE_LAPTOP
++	select USE_NATIVE_RAMINIT
++
++config DRAM_RESET_GATE_GPIO
++	default 60
++
++config MAINBOARD_DIR
++	default "dell/e5520"
++
++config MAINBOARD_PART_NUMBER
++	default "Latitude E5520"
++
++config USBDEBUG_HCD_INDEX
++	default 2
++
++config VGA_BIOS_ID
++	default "8086,0126"
++
++endif # BOARD_DELL_LATITUDE_E5520
+diff --git a/src/mainboard/dell/e5520/Kconfig.name b/src/mainboard/dell/e5520/Kconfig.name
+new file mode 100644
+index 0000000000..c88913e8b3
+--- /dev/null
++++ b/src/mainboard/dell/e5520/Kconfig.name
+@@ -0,0 +1,2 @@
++config BOARD_DELL_LATITUDE_E5520
++	bool "Latitude E5520"
+diff --git a/src/mainboard/dell/e5520/Makefile.inc b/src/mainboard/dell/e5520/Makefile.inc
+new file mode 100644
+index 0000000000..18391d8b18
+--- /dev/null
++++ b/src/mainboard/dell/e5520/Makefile.inc
+@@ -0,0 +1,5 @@
++bootblock-y += early_init.c
++bootblock-y += gpio.c
++romstage-y += early_init.c
++romstage-y += gpio.c
++ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
+diff --git a/src/mainboard/dell/e5520/acpi/ec.asl b/src/mainboard/dell/e5520/acpi/ec.asl
+new file mode 100644
+index 0000000000..0d429410a9
+--- /dev/null
++++ b/src/mainboard/dell/e5520/acpi/ec.asl
+@@ -0,0 +1,9 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Device(EC)
++{
++	Name (_HID, EISAID("PNP0C09"))
++	Name (_UID, 0)
++	Name (_GPE, 16)
++/* FIXME: EC support */
++}
+diff --git a/src/mainboard/dell/e5520/acpi/platform.asl b/src/mainboard/dell/e5520/acpi/platform.asl
+new file mode 100644
+index 0000000000..2d24bbd9b9
+--- /dev/null
++++ b/src/mainboard/dell/e5520/acpi/platform.asl
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++Method(_WAK, 1)
++{
++	/* FIXME: EC support  */
++	Return(Package() {0, 0})
++}
++
++Method(_PTS,1)
++{
++	/* FIXME: EC support  */
++}
+diff --git a/src/mainboard/dell/e5520/acpi/superio.asl b/src/mainboard/dell/e5520/acpi/superio.asl
+new file mode 100644
+index 0000000000..55b1db5b11
+--- /dev/null
++++ b/src/mainboard/dell/e5520/acpi/superio.asl
+@@ -0,0 +1,3 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <drivers/pc80/pc/ps2_controller.asl>
+diff --git a/src/mainboard/dell/e5520/acpi_tables.c b/src/mainboard/dell/e5520/acpi_tables.c
+new file mode 100644
+index 0000000000..e2759659bf
+--- /dev/null
++++ b/src/mainboard/dell/e5520/acpi_tables.c
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <acpi/acpi_gnvs.h>
++#include <soc/nvs.h>
++
++/* FIXME: check this function.  */
++void mainboard_fill_gnvs(struct global_nvs *gnvs)
++{
++	/* The lid is open by default. */
++	gnvs->lids = 1;
++
++	/* Temperature at which OS will shutdown */
++	gnvs->tcrt = 100;
++	/* Temperature at which OS will throttle CPU */
++	gnvs->tpsv = 90;
++}
+diff --git a/src/mainboard/dell/e5520/board_info.txt b/src/mainboard/dell/e5520/board_info.txt
+new file mode 100644
+index 0000000000..34d5ad9e0b
+--- /dev/null
++++ b/src/mainboard/dell/e5520/board_info.txt
+@@ -0,0 +1,6 @@
++Category: laptop
++ROM package: SOIC-8
++ROM protocol: SPI
++ROM socketed: n
++Flashrom support: y
++Release year: 2011
+diff --git a/src/mainboard/dell/e5520/cmos.default b/src/mainboard/dell/e5520/cmos.default
+new file mode 100644
+index 0000000000..279415dfd1
+--- /dev/null
++++ b/src/mainboard/dell/e5520/cmos.default
+@@ -0,0 +1,9 @@
++boot_option=Fallback
++debug_level=Debug
++power_on_after_fail=Disable
++nmi=Enable
++bluetooth=Enable
++wwan=Enable
++wlan=Enable
++sata_mode=AHCI
++me_state=Disabled
+diff --git a/src/mainboard/dell/e5520/cmos.layout b/src/mainboard/dell/e5520/cmos.layout
+new file mode 100644
+index 0000000000..1aa7e77bce
+--- /dev/null
++++ b/src/mainboard/dell/e5520/cmos.layout
+@@ -0,0 +1,88 @@
++## SPDX-License-Identifier: GPL-2.0-only
++
++# -----------------------------------------------------------------
++entries
++
++# -----------------------------------------------------------------
++0	120	r	0	reserved_memory
++
++# -----------------------------------------------------------------
++# RTC_BOOT_BYTE (coreboot hardcoded)
++384	1	e	4	boot_option
++388	4	h	0	reboot_counter
++
++# -----------------------------------------------------------------
++# coreboot config options: console
++395	4	e	6	debug_level
++
++#400	8	r	0	reserved for century byte
++
++# coreboot config options: southbridge
++408	1	e	1	nmi
++409	2	e	7	power_on_after_fail
++411     1       e       9       sata_mode
++
++# coreboot config options: EC
++412	1	e	1	bluetooth
++413	1	e	1	wwan
++414	1	e	1	wlan
++
++# coreboot config options: ME
++424	1	e	14	me_state
++425	2	h	0	me_state_prev
++
++# coreboot config options: northbridge
++432	3	e	11	gfx_uma_size
++435	2	e	12	hybrid_graphics_mode
++440	8	h	0	volume
++
++# VBOOT
++448	128	r	0	vbnv
++
++# SandyBridge MRC Scrambler Seed values
++896	32	r	0	mrc_scrambler_seed
++928	32	r	0	mrc_scrambler_seed_s3
++960	16	r	0	mrc_scrambler_seed_chk
++
++# coreboot config options: check sums
++984	16	h	0	check_sum
++
++# -----------------------------------------------------------------
++
++enumerations
++
++#ID	value	text
++1	0	Disable
++1	1	Enable
++2	0	Enable
++2	1	Disable
++4	0	Fallback
++4	1	Normal
++6	0	Emergency
++6	1	Alert
++6	2	Critical
++6	3	Error
++6	4	Warning
++6	5	Notice
++6	6	Info
++6	7	Debug
++6	8	Spew
++7	0	Disable
++7	1	Enable
++7	2	Keep
++9	0	AHCI
++9	1	Compatible
++11	0	32M
++11	1	64M
++11	2	96M
++11	3	128M
++11	4	160M
++11	5	192M
++11	6	224M
++14	0	Normal
++14	1	Disabled
++
++# -----------------------------------------------------------------
++checksums
++
++checksum 392 447 984
+diff --git a/src/mainboard/dell/e5520/data.vbt b/src/mainboard/dell/e5520/data.vbt
+new file mode 100644
+index 0000000000000000000000000000000000000000..b511e75262e37fa123d674e9a7b21a8dfe427729
+GIT binary patch
+literal 6144
+zcmeHKZ){Ul6hE);wSBvNZ|mL$bmQOM2BTvXUI!}^N9ejTij1vnu+)Wx6<c9(Y_%K6
+zzOV-@f<ehpWB5RHBpMBgG7}RuMuM2=l*E{6G$wq&gqTQ3#E2RZsOP@dvW*rP7>Fjj
+z&F`Lj?>YC}bI(2Z+}C+6zKyiGrosQXuW7A+&1%<rN+Y1ck(}dLrx)Ma#^x>lnvFGE
+zeD#gB>*#Tq4&j^|7Xcz1r^pp*)g#T}u1Me3ct>Pgls5Qi3!6e2W0%`a-Ic|3efWuR
+zXJ@#}wJyGMTXTcY<%@TBKh@(3hP$Gjv}E}rx-%9D_eLXhYe!c&-VyDg-Cdo1>Biji
+zNNsnlFW#|jdoOj?mZ43m>cVO%UE9@*E7x|%V~c4`XD4l9GCi~@+7pfMibfX8L?!^I
+zc~Rg1I5SxH1DAEZ0{jA41jrJBh#-l;b6^%g7QrThRe)&%tQH_!ggOD7A_PRRgGuI0
+z0zi=n#rCB66d-sO$M~^6wgeb$2fH1|0R`v}xUiWCU`4SF;Dyh&j|mK&6WJWJ&Pq9I
+zVgmFQfh+)vE}(KWwHA|Oh3fSkss|;2E(2i}s1?gRRV%8!K7U={vHD=s#+Fd)W^M1j
+z{R4$??VSvEWpgT=vCM&1-U$bI6CB~IV3Z$$Vv7o!EDnev4j~R(MHsazZ~^fLLKGF4
+zEfQFOa3dZ?1Q1P#&4?!vyAk^k&m&$z3?WV+-b0*1j37o4=MX<3E+eiYge(Ht2umAW
+zOPDmU>UL{flI9u|@JtVvfp#o8ek?VfVV9YP5(%pnZX~{PKq4WoWGmV8t$=Ri@{zLQ
+zNYYt4<$0Ry&qIoG;7s-t333)Nu8opN{NG!)&!I@eO(cVx8vBVEBvotJ7%yNl$7iQ_
+zI=xk30+V$ff`F6<wRoF(TK%j9nsr#H23umU%)_7jNOl%*FPU567qbg;4gtp711nj2
+z#+kHw`v4|5cA+`UMIvAl;slnH1nl0v=xH<al>1}ljxDE1dcda^&!do|r^eJkI?aC-
+zEQMSfm?<w*Unzumkj_w5>VYL6W4=aCiy4rk%xq~5LV?bi|GL2$G7li<%c7yd;6T34
+zQBN5huZ3~6`ChGkpb$Bg5ITb#2iK-qs|1`=sl6Dhn(Lj&8Agt?S{sTDmmtRj7Jm_1
+zFnt{w&FdFkWS3bl>OeL?eO+*i{)9G!cSI-InGt|U0eEYmRCOHm7|I;#LO8ksRIeJ#
+zGe+jTwPg4C4TYuN(9zULV3k+hI$YuPo=%N8oZ#u_4S!3Xelt6N0BmuC`hCNeg+&97
+z6*!>)uHvr%2004GZv?!_-y&|TRmil=9D%Q`1aXBsnD^gov3*UZI34&1_vn(B=T4kZ
+z_A>ClXVIBNaS^hd&^DrU6VgZMYeadMkdFxcktn|ra-Gl;n^I{bt86rCQ=YMry*B!$
+zP5ID9KDE)GZOY#^VwPyRq^y+48j0?ZlzxdkC()CV@`*&wO7vGr;qjA3rb}gIwM-gi
+zx>HsT$mEDj-<OpyWb%zn|B@A3Hkp<!FT5;hrt_SZiy?*wDaIu{h>%Ir=@rh7)SR;b
+zAEWQGv_X1)wq0y5Ha0c~&psIsln<Hiu3;#Lf;%*eI<@?p8cfMJV(IYi8q$NA#iS8`
+z_~|4t4b^wtMSAeFST^F8-Tm<zu8D&j^8=&I4;I}Im>aeSK~X8*^Z9SE44_`P#KIUL
+zf6^N2f>5HCPWM3N+f0MyWOV^kz~!-wVc4MRXOY>4Jsxd1RyBKEMzNf{RKhesKFdbq
+zJ(*d<l2Y#n?E?~iBA39P?~Pr2d#}5=#Sfl-VGzGUF$4U2KcqCIVlwkC(&7PQk_X!a
+z8}3Jgq-&U*Co|h1>l)ZQGyW_x->i#;FvQ*=Nv&nG0N5@D@jjv_Q}K}6MP?1A6`JGe
+zDwj9pN+x;T4>`I9e5x(uqdK#OGB31ikk@Xv=dxLb4fx(;ktX@rOb~M~?dYQQYiPia
+z8r;jUQ?sd2@3||-cb2Eb%JFYfxHsONoaJ^eqoKN{<g9?-%`7oWz+aJS0tEc!^d@hD
+z1-I{%hr!Y?0uVZpUbl__37xn@jkD6Z>3SATgBQlEoN7&ZV9Eni9+>jLln16fFy(=V
+H=7E0zE^L4Z
+
+literal 0
+HcmV?d00001
+
+diff --git a/src/mainboard/dell/e5520/devicetree.cb b/src/mainboard/dell/e5520/devicetree.cb
+new file mode 100644
+index 0000000000..bef96ac14c
+--- /dev/null
++++ b/src/mainboard/dell/e5520/devicetree.cb
+@@ -0,0 +1,66 @@
++chip northbridge/intel/sandybridge # FIXME: GPU registers may not always apply.
++	register "gfx" = "GMA_STATIC_DISPLAYS(1)"
++	register "gpu_cpu_backlight" = "0x00000218"
++	register "gpu_dp_b_hotplug" = "4"
++	register "gpu_dp_c_hotplug" = "4"
++	register "gpu_dp_d_hotplug" = "4"
++	register "gpu_panel_port_select" = "0"
++	register "gpu_panel_power_backlight_off_delay" = "2300"
++	register "gpu_panel_power_backlight_on_delay" = "2300"
++	register "gpu_panel_power_cycle_delay" = "6"
++	register "gpu_panel_power_down_delay" = "400"
++	register "gpu_panel_power_up_delay" = "400"
++	register "gpu_pch_backlight" = "0x13121312"
++
++	register "spd_addresses" = "{0x50, 0, 0x52, 0}"
++
++	device domain 0x0 on
++		subsystemid 0x1028 0x049a inherit
++
++		device ref host_bridge on end # Host bridge
++		device ref peg10 on end # PEG
++		device ref igd on end # iGPU
++
++		chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
++			register "docking_supported" = "1"
++			register "gen1_dec" = "0x007c0681"
++			register "gen2_dec" = "0x007c0901"
++			register "gen3_dec" = "0x003c07e1"
++			register "gen4_dec" = "0x001c0901"
++			register "gpi0_routing" = "2"
++			register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 1, 0 }"
++			register "pcie_port_coalesce" = "1"
++			register "sata_interface_speed_support" = "0x3"
++			register "sata_port_map" = "0x3b"
++			register "spi_lvscc" = "0x2005"
++			register "spi_uvscc" = "0x2005"
++
++			device ref mei1		off end
++			device ref mei2		off end
++			device ref me_ide_r	off end
++			device ref me_kt	off end
++			device ref gbe		off end
++			device ref ehci2	on end
++			device ref hda		on end
++			device ref pcie_rp1	on end
++			device ref pcie_rp2	on end
++			device ref pcie_rp3	on end
++			device ref pcie_rp4	off end
++			device ref pcie_rp5	on end
++			device ref pcie_rp6	on end
++			device ref pcie_rp7	on end
++			device ref pcie_rp8	off end
++			device ref ehci1	on end
++			device ref pci_bridge	off end
++			device ref lpc		on
++				chip ec/dell/mec5035
++					device pnp ff.0 on end
++				end
++			end
++			device ref sata1 on end
++			device ref smbus on end
++			device ref sata2 off end
++			device ref thermal off end
++		end
++	end
++end
+diff --git a/src/mainboard/dell/e5520/dsdt.asl b/src/mainboard/dell/e5520/dsdt.asl
+new file mode 100644
+index 0000000000..7d13c55b08
+--- /dev/null
++++ b/src/mainboard/dell/e5520/dsdt.asl
+@@ -0,0 +1,30 @@
++#define BRIGHTNESS_UP \_SB.PCI0.GFX0.INCB
++#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.DECB
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <acpi/acpi.h>
++
++DefinitionBlock(
++	"dsdt.aml",
++	"DSDT",
++	ACPI_DSDT_REV_2,
++	OEM_ID,
++	ACPI_TABLE_CREATOR,
++	0x20141018	/* OEM revision */
++)
++{
++	#include <acpi/dsdt_top.asl>
++	#include "acpi/platform.asl"
++	#include <cpu/intel/common/acpi/cpu.asl>
++	#include <southbridge/intel/common/acpi/platform.asl>
++	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
++	#include <southbridge/intel/common/acpi/sleepstates.asl>
++
++	Device (\_SB.PCI0)
++	{
++		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
++		#include <drivers/intel/gma/acpi/default_brightness_levels.asl>
++		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
++	}
++}
+diff --git a/src/mainboard/dell/e5520/early_init.c b/src/mainboard/dell/e5520/early_init.c
+new file mode 100644
+index 0000000000..7297921546
+--- /dev/null
++++ b/src/mainboard/dell/e5520/early_init.c
+@@ -0,0 +1,32 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++
++#include <bootblock_common.h>
++#include <device/pci_ops.h>
++#include <ec/dell/mec5035/mec5035.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++
++const struct southbridge_usb_port mainboard_usb_ports[] = {
++	{ 1, 1, 0 },
++	{ 1, 1, 0 },
++	{ 1, 1, 1 },
++	{ 1, 1, 1 },
++	{ 1, 1, 2 },
++	{ 1, 1, 2 },
++	{ 1, 1, 3 },
++	{ 1, 1, 3 },
++	{ 1, 1, 5 },
++	{ 1, 1, 5 },
++	{ 1, 1, 7 },
++	{ 1, 1, 6 },
++	{ 1, 1, 6 },
++	{ 1, 1, 7 },
++};
++
++void bootblock_mainboard_early_init(void)
++{
++	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN
++			| KBC_LPC_EN | FDD_LPC_EN | LPT_LPC_EN
++			| COMB_LPC_EN | COMA_LPC_EN);
++	mec5035_early_init();
++}
+diff --git a/src/mainboard/dell/e5520/gma-mainboard.ads b/src/mainboard/dell/e5520/gma-mainboard.ads
+new file mode 100644
+index 0000000000..2a16f44360
+--- /dev/null
++++ b/src/mainboard/dell/e5520/gma-mainboard.ads
+@@ -0,0 +1,20 @@
++-- SPDX-License-Identifier: GPL-2.0-or-later
++
++with HW.GFX.GMA;
++with HW.GFX.GMA.Display_Probing;
++
++use HW.GFX.GMA;
++use HW.GFX.GMA.Display_Probing;
++
++private package GMA.Mainboard is
++
++   ports : constant Port_List :=
++     (
++      HDMI1, -- mainboard HDMI
++      DP2, -- dock DP
++      DP3, -- dock DP
++      Analog, -- mainboard VGA
++      LVDS,
++      others => Disabled);
++
++end GMA.Mainboard;
+diff --git a/src/mainboard/dell/e5520/gpio.c b/src/mainboard/dell/e5520/gpio.c
+new file mode 100644
+index 0000000000..f76b93d9f0
+--- /dev/null
++++ b/src/mainboard/dell/e5520/gpio.c
+@@ -0,0 +1,195 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <southbridge/intel/common/gpio.h>
++
++static const struct pch_gpio_set1 pch_gpio_set1_mode = {
++	.gpio0 = GPIO_MODE_GPIO,
++	.gpio1 = GPIO_MODE_NATIVE,
++	.gpio2 = GPIO_MODE_GPIO,
++	.gpio3 = GPIO_MODE_GPIO,
++	.gpio4 = GPIO_MODE_GPIO,
++	.gpio5 = GPIO_MODE_NATIVE,
++	.gpio6 = GPIO_MODE_GPIO,
++	.gpio7 = GPIO_MODE_GPIO,
++	.gpio8 = GPIO_MODE_GPIO,
++	.gpio9 = GPIO_MODE_NATIVE,
++	.gpio10 = GPIO_MODE_NATIVE,
++	.gpio11 = GPIO_MODE_NATIVE,
++	.gpio12 = GPIO_MODE_GPIO,
++	.gpio13 = GPIO_MODE_GPIO,
++	.gpio14 = GPIO_MODE_GPIO,
++	.gpio15 = GPIO_MODE_GPIO,
++	.gpio16 = GPIO_MODE_NATIVE,
++	.gpio17 = GPIO_MODE_GPIO,
++	.gpio18 = GPIO_MODE_NATIVE,
++	.gpio19 = GPIO_MODE_GPIO,
++	.gpio20 = GPIO_MODE_NATIVE,
++	.gpio21 = GPIO_MODE_GPIO,
++	.gpio22 = GPIO_MODE_GPIO,
++	.gpio23 = GPIO_MODE_NATIVE,
++	.gpio24 = GPIO_MODE_GPIO,
++	.gpio25 = GPIO_MODE_NATIVE,
++	.gpio26 = GPIO_MODE_NATIVE,
++	.gpio27 = GPIO_MODE_GPIO,
++	.gpio28 = GPIO_MODE_GPIO,
++	.gpio29 = GPIO_MODE_GPIO,
++	.gpio30 = GPIO_MODE_GPIO,
++	.gpio31 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_direction = {
++	.gpio0 = GPIO_DIR_INPUT,
++	.gpio2 = GPIO_DIR_INPUT,
++	.gpio3 = GPIO_DIR_INPUT,
++	.gpio4 = GPIO_DIR_INPUT,
++	.gpio6 = GPIO_DIR_INPUT,
++	.gpio7 = GPIO_DIR_INPUT,
++	.gpio8 = GPIO_DIR_INPUT,
++	.gpio12 = GPIO_DIR_OUTPUT,
++	.gpio13 = GPIO_DIR_INPUT,
++	.gpio14 = GPIO_DIR_INPUT,
++	.gpio15 = GPIO_DIR_INPUT,
++	.gpio17 = GPIO_DIR_INPUT,
++	.gpio19 = GPIO_DIR_INPUT,
++	.gpio21 = GPIO_DIR_INPUT,
++	.gpio22 = GPIO_DIR_INPUT,
++	.gpio24 = GPIO_DIR_INPUT,
++	.gpio27 = GPIO_DIR_INPUT,
++	.gpio28 = GPIO_DIR_INPUT,
++	.gpio29 = GPIO_DIR_INPUT,
++	.gpio30 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_level = {
++	.gpio12 = GPIO_LEVEL_HIGH,
++	.gpio30 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_reset = {
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_invert = {
++	.gpio0 = GPIO_INVERT,
++	.gpio8 = GPIO_INVERT,
++	.gpio14 = GPIO_INVERT,
++};
++
++static const struct pch_gpio_set1 pch_gpio_set1_blink = {
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_mode = {
++	.gpio32 = GPIO_MODE_NATIVE,
++	.gpio33 = GPIO_MODE_GPIO,
++	.gpio34 = GPIO_MODE_GPIO,
++	.gpio35 = GPIO_MODE_GPIO,
++	.gpio36 = GPIO_MODE_GPIO,
++	.gpio37 = GPIO_MODE_GPIO,
++	.gpio38 = GPIO_MODE_GPIO,
++	.gpio39 = GPIO_MODE_GPIO,
++	.gpio40 = GPIO_MODE_NATIVE,
++	.gpio41 = GPIO_MODE_NATIVE,
++	.gpio42 = GPIO_MODE_NATIVE,
++	.gpio43 = GPIO_MODE_NATIVE,
++	.gpio44 = GPIO_MODE_NATIVE,
++	.gpio45 = GPIO_MODE_NATIVE,
++	.gpio46 = GPIO_MODE_GPIO,
++	.gpio47 = GPIO_MODE_NATIVE,
++	.gpio48 = GPIO_MODE_GPIO,
++	.gpio49 = GPIO_MODE_NATIVE,
++	.gpio50 = GPIO_MODE_GPIO,
++	.gpio51 = GPIO_MODE_GPIO,
++	.gpio52 = GPIO_MODE_GPIO,
++	.gpio53 = GPIO_MODE_GPIO,
++	.gpio54 = GPIO_MODE_GPIO,
++	.gpio55 = GPIO_MODE_GPIO,
++	.gpio56 = GPIO_MODE_GPIO,
++	.gpio57 = GPIO_MODE_GPIO,
++	.gpio58 = GPIO_MODE_NATIVE,
++	.gpio59 = GPIO_MODE_NATIVE,
++	.gpio60 = GPIO_MODE_GPIO,
++	.gpio61 = GPIO_MODE_NATIVE,
++	.gpio62 = GPIO_MODE_NATIVE,
++	.gpio63 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_direction = {
++	.gpio33 = GPIO_DIR_INPUT,
++	.gpio34 = GPIO_DIR_OUTPUT,
++	.gpio35 = GPIO_DIR_INPUT,
++	.gpio36 = GPIO_DIR_INPUT,
++	.gpio37 = GPIO_DIR_OUTPUT,
++	.gpio38 = GPIO_DIR_INPUT,
++	.gpio39 = GPIO_DIR_INPUT,
++	.gpio46 = GPIO_DIR_OUTPUT,
++	.gpio48 = GPIO_DIR_INPUT,
++	.gpio50 = GPIO_DIR_OUTPUT,
++	.gpio51 = GPIO_DIR_OUTPUT,
++	.gpio52 = GPIO_DIR_INPUT,
++	.gpio53 = GPIO_DIR_INPUT,
++	.gpio54 = GPIO_DIR_INPUT,
++	.gpio55 = GPIO_DIR_OUTPUT,
++	.gpio56 = GPIO_DIR_INPUT,
++	.gpio57 = GPIO_DIR_INPUT,
++	.gpio60 = GPIO_DIR_OUTPUT,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_level = {
++	.gpio34 = GPIO_LEVEL_LOW,
++	.gpio37 = GPIO_LEVEL_LOW,
++	.gpio46 = GPIO_LEVEL_HIGH,
++	.gpio50 = GPIO_LEVEL_HIGH,
++	.gpio51 = GPIO_LEVEL_LOW,
++	.gpio55 = GPIO_LEVEL_LOW,
++	.gpio60 = GPIO_LEVEL_HIGH,
++};
++
++static const struct pch_gpio_set2 pch_gpio_set2_reset = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_mode = {
++	.gpio64 = GPIO_MODE_NATIVE,
++	.gpio65 = GPIO_MODE_NATIVE,
++	.gpio66 = GPIO_MODE_NATIVE,
++	.gpio67 = GPIO_MODE_NATIVE,
++	.gpio68 = GPIO_MODE_NATIVE,
++	.gpio69 = GPIO_MODE_NATIVE,
++	.gpio70 = GPIO_MODE_NATIVE,
++	.gpio71 = GPIO_MODE_NATIVE,
++	.gpio72 = GPIO_MODE_NATIVE,
++	.gpio73 = GPIO_MODE_NATIVE,
++	.gpio74 = GPIO_MODE_GPIO,
++	.gpio75 = GPIO_MODE_NATIVE,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_direction = {
++	.gpio74 = GPIO_DIR_INPUT,
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_level = {
++};
++
++static const struct pch_gpio_set3 pch_gpio_set3_reset = {
++};
++
++const struct pch_gpio_map mainboard_gpio_map = {
++	.set1 = {
++		.mode		= &pch_gpio_set1_mode,
++		.direction	= &pch_gpio_set1_direction,
++		.level		= &pch_gpio_set1_level,
++		.blink		= &pch_gpio_set1_blink,
++		.invert		= &pch_gpio_set1_invert,
++		.reset		= &pch_gpio_set1_reset,
++	},
++	.set2 = {
++		.mode		= &pch_gpio_set2_mode,
++		.direction	= &pch_gpio_set2_direction,
++		.level		= &pch_gpio_set2_level,
++		.reset		= &pch_gpio_set2_reset,
++	},
++	.set3 = {
++		.mode		= &pch_gpio_set3_mode,
++		.direction	= &pch_gpio_set3_direction,
++		.level		= &pch_gpio_set3_level,
++		.reset		= &pch_gpio_set3_reset,
++	},
++};
+diff --git a/src/mainboard/dell/e5520/hda_verb.c b/src/mainboard/dell/e5520/hda_verb.c
+new file mode 100644
+index 0000000000..e2efee3646
+--- /dev/null
++++ b/src/mainboard/dell/e5520/hda_verb.c
+@@ -0,0 +1,33 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/azalia_device.h>
++
++const u32 cim_verb_data[] = {
++	0x111d76e7,	/* Codec Vendor / Device ID: IDT */
++	0x1028049a,	/* Subsystem ID */
++	11,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(0, 0x1028049a),
++	AZALIA_PIN_CFG(0, 0x0a, 0x04a11020),
++	AZALIA_PIN_CFG(0, 0x0b, 0x0421101f),
++	AZALIA_PIN_CFG(0, 0x0c, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
++	AZALIA_PIN_CFG(0, 0x0e, 0x23011050),
++	AZALIA_PIN_CFG(0, 0x0f, 0x23a1102e),
++	AZALIA_PIN_CFG(0, 0x10, 0x400000f3),
++	AZALIA_PIN_CFG(0, 0x11, 0xd5a301a0),
++	AZALIA_PIN_CFG(0, 0x1f, 0x400000f0),
++	AZALIA_PIN_CFG(0, 0x20, 0x400000f0),
++
++	0x80862805,	/* Codec Vendor / Device ID: Intel */
++	0x80860101,	/* Subsystem ID */
++	4,		/* Number of 4 dword sets */
++	AZALIA_SUBVENDOR(3, 0x80860101),
++	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
++	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
++	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
++
++};
++
++const u32 pc_beep_verbs[0] = {};
++
++AZALIA_ARRAY_SIZES;
+diff --git a/src/mainboard/dell/e5520/mainboard.c b/src/mainboard/dell/e5520/mainboard.c
+new file mode 100644
+index 0000000000..31e49802fc
+--- /dev/null
++++ b/src/mainboard/dell/e5520/mainboard.c
+@@ -0,0 +1,21 @@
++/* SPDX-License-Identifier: GPL-2.0-only */
++
++#include <device/device.h>
++#include <drivers/intel/gma/int15.h>
++#include <southbridge/intel/bd82x6x/pch.h>
++#include <ec/acpi/ec.h>
++#include <console/console.h>
++#include <pc80/keyboard.h>
++
++static void mainboard_enable(struct device *dev)
++{
++
++	/* FIXME: fix these values. */
++	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
++					GMA_INT15_PANEL_FIT_DEFAULT,
++					GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
++}
++
++struct chip_operations mainboard_ops = {
++	.enable_dev = mainboard_enable,
++};
+-- 
+2.43.0
+

config/coreboot/default/patches/0036-nb-haswell-disable-igpu-when-dgpu-is-used.patch

@@ -0,0 +1,47 @@
+From aa04e2b9f63aae953040816306a45bdf86a2195f Mon Sep 17 00:00:00 2001
+From: Leah Rowe <info@minifree.org>
+Date: Thu, 22 Feb 2024 17:52:03 +0000
+Subject: [PATCH 1/1] nb/haswell: disable igpu when dgpu is used
+
+normally, this is done with haswell mrc, which handles
+that, but when using broadwell, the igpu is not disabled,
+and legacy vga cycles are not routed to the dgpu
+
+add this behaviour in gma.g for broadwell mrc.bin
+
+tested on dell optiplex 9020 sff
+
+Signed-off-by: Leah Rowe <info@minifree.org>
+---
+ src/northbridge/intel/haswell/gma.c | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
+index 6e6948b70f..ee4d321261 100644
+--- a/src/northbridge/intel/haswell/gma.c
++++ b/src/northbridge/intel/haswell/gma.c
+@@ -461,12 +461,21 @@ static void gma_generate_ssdt(const struct device *dev)
+ 	drivers_intel_gma_displays_ssdt_generate(&chip->gfx);
+ }
+ 
++static void gma_func0_disable(struct device *dev)
++{
++	/* Disable VGA decode */
++	pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
++
++	dev->enabled = 0;
++}
++
+ static struct device_operations gma_func0_ops = {
+ 	.read_resources		= pci_dev_read_resources,
+ 	.set_resources		= pci_dev_set_resources,
+ 	.enable_resources	= pci_dev_enable_resources,
+ 	.init			= gma_func0_init,
+ 	.acpi_fill_ssdt		= gma_generate_ssdt,
++	.vga_disable            = gma_func0_disable,
+ 	.ops_pci		= &pci_dev_ops_pci,
+ };
+ 
+-- 
+2.39.2
+

config/coreboot/default/patches/0045-Haswell-NRI-Implement-fast-boot-path.patch

@@ -1,722 +0,0 @@
-From b6b89013630d535b68a005cede9e2540f273f4e7 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Sat, 13 Apr 2024 01:16:30 +0200
-Subject: [PATCH 45/51] Haswell NRI: Implement fast boot path
-
-When the memory configuration hasn't changed, there is no need to do
-full memory training. Instead, boot firmware can use saved training
-data to reinitialise the memory controller and memory.
-
-Unlike native RAM init for other platforms, Haswell does not save the
-main structure (the "mighty ctrl" struct) to flash. Instead, separate
-structures define the data to be saved, which can be smaller than the
-main structure.
-
-This makes S3 suspend and resume work: RAM contents MUST be preserved
-for a S3 resume to succeed, but RAM training destroys RAM contents.
-
-Change-Id: I06f6cd39ceecdca104fae89159f28e85cf7ff4e6
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.mk  |   1 +
- .../haswell/native_raminit/activate_mc.c      |  17 +
- .../intel/haswell/native_raminit/ddr3.c       |  41 ++
- .../haswell/native_raminit/raminit_main.c     |  34 +-
- .../haswell/native_raminit/raminit_native.c   |  30 +-
- .../haswell/native_raminit/raminit_native.h   |  18 +
- .../haswell/native_raminit/save_restore.c     | 387 ++++++++++++++++++
- 7 files changed, 504 insertions(+), 24 deletions(-)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/save_restore.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-index d97da72890..8fdd17c542 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-@@ -13,6 +13,7 @@ romstage-y += raminit_main.c
- romstage-y += raminit_native.c
- romstage-y += ranges.c
- romstage-y += reut.c
-+romstage-y += save_restore.c
- romstage-y += setup_wdb.c
- romstage-y += spd_bitmunching.c
- romstage-y += testing_io.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/activate_mc.c b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
-index 78a7ad27ef..0b3eb917da 100644
---- a/src/northbridge/intel/haswell/native_raminit/activate_mc.c
-+++ b/src/northbridge/intel/haswell/native_raminit/activate_mc.c
-@@ -333,6 +333,23 @@ enum raminit_status activate_mc(struct sysinfo *ctrl)
- 	return RAMINIT_STATUS_SUCCESS;
- }
- 
-+enum raminit_status normal_state(struct sysinfo *ctrl)
-+{
-+	/* Enable periodic COMP */
-+	mchbar_write32(M_COMP, (union pcu_comp_reg) {
-+		.comp_interval = COMP_INT,
-+	}.raw);
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		/* Set MC to normal mode and clean the ODT and CKE */
-+		mchbar_write32(REUT_ch_SEQ_CFG(channel), REUT_MODE_NOP << 12);
-+	}
-+	power_down_config(ctrl);
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
- static void mc_lockdown(void)
- {
- 	/* Lock memory controller registers */
-diff --git a/src/northbridge/intel/haswell/native_raminit/ddr3.c b/src/northbridge/intel/haswell/native_raminit/ddr3.c
-index 6ddb11488b..9b6368edb1 100644
---- a/src/northbridge/intel/haswell/native_raminit/ddr3.c
-+++ b/src/northbridge/intel/haswell/native_raminit/ddr3.c
-@@ -2,6 +2,7 @@
- 
- #include <assert.h>
- #include <console/console.h>
-+#include <delay.h>
- #include <northbridge/intel/haswell/haswell.h>
- #include <types.h>
- 
-@@ -215,3 +216,43 @@ enum raminit_status ddr3_jedec_init(struct sysinfo *ctrl)
- 	ddr3_program_mr0(ctrl, 1);
- 	return reut_issue_zq(ctrl, ctrl->chanmap, ZQ_INIT);
- }
-+
-+enum raminit_status exit_selfrefresh(struct sysinfo *ctrl)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		/* Fields in ctrl aren't populated on a warm boot */
-+		union ddr_data_control_0_reg data_control_0 = {
-+			.raw = mchbar_read32(DQ_CONTROL_0(channel, 0)),
-+		};
-+		data_control_0.read_rf_rd = 1;
-+		for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+			if (!rank_in_ch(ctrl, rank, channel))
-+				continue;
-+
-+			data_control_0.read_rf_rank = rank;
-+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+		}
-+	}
-+
-+	/* Time needed to stabilize the DCLK (~6 us) */
-+	udelay(6);
-+
-+	/* Pull the DIMMs out of self refresh by asserting CKE high */
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		const union reut_misc_cke_ctrl_reg reut_misc_cke_ctrl = {
-+			.cke_on = ctrl->rankmap[channel],
-+		};
-+		mchbar_write32(REUT_ch_MISC_CKE_CTRL(channel), reut_misc_cke_ctrl.raw);
-+	}
-+	mchbar_write32(REUT_MISC_ODT_CTRL, 0);
-+
-+	const enum raminit_status status = reut_issue_zq(ctrl, ctrl->chanmap, ZQ_LONG);
-+	if (status) {
-+		/* ZQCL errors don't seem to be a fatal problem here */
-+		printk(BIOS_ERR, "ZQ Long failed during S3 resume or warm reset flow\n");
-+	}
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 3a65fb01fb..056dde1adc 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -64,6 +64,22 @@ static const struct task_entry cold_boot[] = {
- 	{ train_read_mpr,                                         true, "RDMPRT",     },
- 	{ train_jedec_write_leveling,                             true, "JWRL",       },
- 	{ activate_mc,                                            true, "ACTIVATE",   },
-+	{ save_training_values,                                   true, "SAVE_TRAIN", },
-+	{ save_non_training,                                      true, "SAVE_NONT",  },
-+	{ raminit_done,                                           true, "RAMINITEND", },
-+};
-+
-+static const struct task_entry fast_boot[] = {
-+	{ collect_spd_info,                                       true, "PROCSPD",    },
-+	{ restore_non_training,                                   true, "RST_NONT",   },
-+	{ initialise_mpll,                                        true, "INITMPLL",   },
-+	{ configure_mc,                                           true, "CONFMC",     },
-+	{ configure_memory_map,                                   true, "MEMMAP",     },
-+	{ do_jedec_init,                                          true, "JEDECINIT",  },
-+	{ pre_training,                                           true, "PRETRAIN",   },
-+	{ restore_training_values,                                true, "RST_TRAIN",  },
-+	{ exit_selfrefresh,                                       true, "EXIT_SR",    },
-+	{ normal_state,                                           true, "NORMALMODE", },
- 	{ raminit_done,                                           true, "RAMINITEND", },
- };
- 
-@@ -102,11 +118,11 @@ static void initialize_ctrl(struct sysinfo *ctrl)
- 	ctrl->bootmode = bootmode;
- }
- 
--static enum raminit_status try_raminit(struct sysinfo *ctrl)
-+static enum raminit_status try_raminit(
-+	struct sysinfo *ctrl,
-+	const struct task_entry *const schedule,
-+	const size_t length)
- {
--	const struct task_entry *const schedule = cold_boot;
--	const size_t length = ARRAY_SIZE(cold_boot);
--
- 	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
- 
- 	for (size_t i = 0; i < length; i++) {
-@@ -140,8 +156,16 @@ void raminit_main(const enum raminit_boot_mode bootmode)
- 	mighty_ctrl.bootmode = bootmode;
- 	initialize_ctrl(&mighty_ctrl);
- 
-+	enum raminit_status status = RAMINIT_STATUS_UNSPECIFIED_ERROR;
-+
-+	if (bootmode != BOOTMODE_COLD) {
-+		status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot));
-+		if (status == RAMINIT_STATUS_SUCCESS)
-+			return;
-+	}
-+
- 	/** TODO: Try more than once **/
--	enum raminit_status status = try_raminit(&mighty_ctrl);
-+	status = try_raminit(&mighty_ctrl, cold_boot, ARRAY_SIZE(cold_boot));
- 
- 	if (status != RAMINIT_STATUS_SUCCESS)
- 		die("Memory initialization was met with utmost failure and misery\n");
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-index 5f7ceec222..3ad8ce29e7 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
-@@ -54,23 +54,17 @@ static bool early_init_native(enum raminit_boot_mode bootmode)
- 	return cpu_replaced;
- }
- 
--#define MRC_CACHE_VERSION 1
--
--struct mrc_data {
--	const void *buffer;
--	size_t buffer_len;
--};
--
--static void save_mrc_data(struct mrc_data *md)
-+static void save_mrc_data(void)
- {
--	mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, md->buffer, md->buffer_len);
-+	mrc_cache_stash_data(MRC_TRAINING_DATA, reg_frame_rev(),
-+			     reg_frame_ptr(), reg_frame_size());
- }
- 
- static struct mrc_data prepare_mrc_cache(void)
- {
- 	struct mrc_data md = {0};
- 	md.buffer = mrc_cache_current_mmap_leak(MRC_TRAINING_DATA,
--						MRC_CACHE_VERSION,
-+						reg_frame_rev(),
- 						&md.buffer_len);
- 	return md;
- }
-@@ -94,14 +88,15 @@ static void raminit_reset(void)
- }
- 
- static enum raminit_boot_mode do_actual_raminit(
--	struct mrc_data *md,
- 	const bool s3resume,
- 	const bool cpu_replaced,
- 	const enum raminit_boot_mode orig_bootmode)
- {
-+	struct mrc_data md = prepare_mrc_cache();
-+
- 	enum raminit_boot_mode bootmode = orig_bootmode;
- 
--	bool save_data_valid = md->buffer && md->buffer_len == USHRT_MAX; /** TODO: sizeof() **/
-+	bool save_data_valid = md.buffer && md.buffer_len == reg_frame_size();
- 
- 	if (s3resume) {
- 		if (bootmode == BOOTMODE_COLD) {
-@@ -154,7 +149,7 @@ static enum raminit_boot_mode do_actual_raminit(
- 	assert(save_data_valid != (bootmode == BOOTMODE_COLD));
- 	if (save_data_valid) {
- 		printk(BIOS_INFO, "Using cached memory parameters\n");
--		die("RAMINIT: Fast boot is not yet implemented\n");
-+		memcpy(reg_frame_ptr(), md.buffer, reg_frame_size());
- 	}
- 	printk(RAM_DEBUG, "Initial bootmode: %s\n", bm_names[orig_bootmode]);
- 	printk(RAM_DEBUG, "Current bootmode: %s\n", bm_names[bootmode]);
-@@ -181,10 +176,8 @@ void perform_raminit(const int s3resume)
- 	wait_txt_clear();
- 	wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
- 
--	struct mrc_data md = prepare_mrc_cache();
--
- 	const enum raminit_boot_mode bootmode =
--			do_actual_raminit(&md, s3resume, cpu_replaced, orig_bootmode);
-+			do_actual_raminit(s3resume, cpu_replaced, orig_bootmode);
- 
- 	/** TODO: report_memory_config **/
- 
-@@ -212,9 +205,8 @@ void perform_raminit(const int s3resume)
- 	}
- 
- 	/* Save training data on non-S3 resumes */
--	/** TODO: Enable this once training data is populated **/
--	if (0 && !s3resume)
--		save_mrc_data(&md);
-+	if (!s3resume)
-+		save_mrc_data();
- 
- 	/** TODO: setup_sdram_meminfo **/
- }
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index a0a913f926..2ac16eaad3 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -170,6 +170,8 @@ enum regfile_mode {
- 	REG_FILE_USE_CURRENT,	/* Used when changing parameters after the test */
- };
- 
-+struct register_save_frame;
-+
- struct wdb_pat {
- 	uint32_t start_ptr;	/* Starting pointer in WDB */
- 	uint32_t stop_ptr;	/* Stopping pointer in WDB */
-@@ -220,6 +222,7 @@ enum raminit_status {
- 	RAMINIT_STATUS_RCVEN_FAILURE,
- 	RAMINIT_STATUS_RMPR_FAILURE,
- 	RAMINIT_STATUS_JWRL_FAILURE,
-+	RAMINIT_STATUS_INVALID_CACHE,
- 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
- };
- 
-@@ -229,6 +232,11 @@ enum generic_stepping {
- 	STEPPING_C0 = 3,
- };
- 
-+struct mrc_data {
-+	const void *buffer;
-+	size_t buffer_len;
-+};
-+
- struct raminit_dimm_info {
- 	spd_ddr3_raw_data raw_spd;
- 	struct dimm_attr_ddr3_st data;
-@@ -448,12 +456,22 @@ enum raminit_status do_jedec_init(struct sysinfo *ctrl);
- enum raminit_status train_receive_enable(struct sysinfo *ctrl);
- enum raminit_status train_read_mpr(struct sysinfo *ctrl);
- enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
-+enum raminit_status save_training_values(struct sysinfo *ctrl);
-+enum raminit_status restore_training_values(struct sysinfo *ctrl);
-+enum raminit_status save_non_training(struct sysinfo *ctrl);
-+enum raminit_status restore_non_training(struct sysinfo *ctrl);
-+enum raminit_status exit_selfrefresh(struct sysinfo *ctrl);
-+enum raminit_status normal_state(struct sysinfo *ctrl);
- enum raminit_status activate_mc(struct sysinfo *ctrl);
- enum raminit_status raminit_done(struct sysinfo *ctrl);
- 
- void configure_timings(struct sysinfo *ctrl);
- void configure_refresh(struct sysinfo *ctrl);
- 
-+struct register_save_frame *reg_frame_ptr(void);
-+size_t reg_frame_size(void);
-+uint32_t reg_frame_rev(void);
-+
- uint32_t get_tCKE(uint32_t mem_clock_mhz, bool lpddr);
- uint32_t get_tXPDLL(uint32_t mem_clock_mhz);
- uint32_t get_tAONPD(uint32_t mem_clock_mhz);
-diff --git a/src/northbridge/intel/haswell/native_raminit/save_restore.c b/src/northbridge/intel/haswell/native_raminit/save_restore.c
-new file mode 100644
-index 0000000000..f1f50e3ff8
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/save_restore.c
-@@ -0,0 +1,387 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <assert.h>
-+#include <console/console.h>
-+#include <northbridge/intel/haswell/haswell.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+uint32_t reg_frame_rev(void)
-+{
-+	/*
-+	 * Equivalent to MRC_CACHE_REVISION, but hidden via abstraction.
-+	 * The structures that get saved to flash are contained within
-+	 * this translation unit, so changes outside this file shouldn't
-+	 * require invalidating the cache.
-+	 */
-+	return 1;
-+}
-+
-+struct register_save {
-+	uint16_t lower;
-+	uint16_t upper;
-+};
-+
-+/** TODO: Haswell DDRIO aliases writes: 0x80 .. 0xff => 0x00 .. 0x7f **/
-+static const struct register_save ddrio_per_byte_list[] = {
-+	{0x0000, 0x003c}, /* 16 registers */
-+//	{0x0048, 0x0084}, /* 16 registers */	/** TODO: BDW support **/
-+	{0x0048, 0x004c}, /*  2 registers */
-+	{0x005c, 0x0078}, /*  8 registers */
-+};
-+#define DDRIO_PER_BYTE_REGISTER_COUNT	(16 + 2 + 8)
-+
-+static const struct register_save ddrio_per_ch_list[] = {
-+	/* CKE */
-+	{0x1204, 0x1208}, /* 2 registers */
-+	{0x1214, 0x121c}, /* 3 registers */
-+	/* CMD North */
-+	{0x1404, 0x140c}, /* 3 registers */
-+	/* CLK */
-+	{0x1808, 0x1810}, /* 3 registers */
-+	/* CMD South */
-+	{0x1a04, 0x1a0c}, /* 3 registers */
-+	/* CTL */
-+	{0x1c14, 0x1c1c}, /* 3 registers */
-+};
-+#define DDRIO_PER_CH_REGISTER_COUNT	(2 + 3 * 5)
-+
-+static const struct register_save ddrio_common_list[] = {
-+	{0x2000, 0x2008}, /* 3 registers */
-+	{0x3a14, 0x3a1c}, /* 3 registers */
-+	{0x3a24, 0x3a24}, /* 1 registers */
-+};
-+
-+#define DDRIO_COMMON_REGISTER_COUNT	(3 + 3 + 1)
-+
-+static const struct register_save mcmain_per_ch_list[] = {
-+	{0x4000, 0x4014}, /* 6 registers */
-+	{0x4024, 0x4028}, /* 2 registers */
-+	{0x40d0, 0x40d0}, /* 1 registers */
-+	{0x4220, 0x4224}, /* 2 registers */
-+	{0x4294, 0x4294}, /* 1 registers */
-+	{0x429c, 0x42a0}, /* 2 registers */
-+	{0x42ec, 0x42fc}, /* 5 registers */
-+	{0x4328, 0x4328}, /* 1 registers */
-+	{0x438c, 0x4390}, /* 2 registers */
-+};
-+#define MCMAIN_PER_CH_REGISTER_COUNT	(6 + 2 + 1 + 2 + 1 + 2 + 5 + 1 + 2)
-+
-+static const struct register_save misc_common_list[] = {
-+	{0x5884, 0x5888}, /*  2 registers */
-+	{0x5890, 0x589c}, /*  4 registers */
-+	{0x58a4, 0x58a4}, /*  1 registers */
-+	{0x58d0, 0x58e4}, /*  6 registers */
-+	{0x5880, 0x5880}, /*  1 registers */
-+	{0x5000, 0x50dc}, /* 56 registers */
-+	{0x59b8, 0x59b8}  /*  1 registers */
-+};
-+#define MISC_COMMON_REGISTER_COUNT	(2 + 4 + 1 + 6 + 1 + 56 + 1)
-+
-+struct save_params {
-+	bool is_initialised;
-+
-+	/* Memory base frequency, either 100 or 133 MHz */
-+	uint8_t base_freq;
-+
-+	/* Multiplier */
-+	uint32_t multiplier;
-+
-+	/* Memory clock in MHz */
-+	uint32_t mem_clock_mhz;
-+
-+	/* Memory clock in femtoseconds */
-+	uint32_t mem_clock_fs;
-+
-+	/* Quadrature clock in picoseconds */
-+	uint16_t qclkps;
-+
-+	/* Bitfield of supported CAS latencies */
-+	uint16_t cas_supported;
-+
-+	/* CPUID value */
-+	uint32_t cpu;
-+
-+	/* Cached CPU stepping value */
-+	uint8_t stepping;
-+
-+	uint16_t vdd_mv;
-+
-+	union dimm_flags_ddr3_st flags;
-+
-+	/* Except for tCK, everything is stored in DCLKs */
-+	uint32_t tCK;
-+	uint32_t tAA;
-+	uint32_t tWR;
-+	uint32_t tRCD;
-+	uint32_t tRRD;
-+	uint32_t tRP;
-+	uint32_t tRAS;
-+	uint32_t tRC;
-+	uint32_t tRFC;
-+	uint32_t tWTR;
-+	uint32_t tRTP;
-+	uint32_t tFAW;
-+	uint32_t tCWL;
-+	uint32_t tCMD;
-+
-+	uint32_t tREFI;
-+	uint32_t tXP;
-+
-+	uint8_t lpddr_cke_rank_map[NUM_CHANNELS];
-+
-+	struct raminit_dimm_info dimms[NUM_CHANNELS][NUM_SLOTS];
-+
-+	uint8_t chanmap;
-+
-+	uint32_t channel_size_mb[NUM_CHANNELS];
-+
-+	/* DIMMs per channel */
-+	uint8_t dpc[NUM_CHANNELS];
-+
-+	uint8_t rankmap[NUM_CHANNELS];
-+
-+	/* Whether a rank is mirrored or not (only rank 1 of each DIMM can be) */
-+	uint8_t rank_mirrored[NUM_CHANNELS];
-+
-+	/*
-+	 * FIXME: LPDDR support is incomplete. The largest chunks are missing,
-+	 * but some LPDDR-specific variations in algorithms have been handled.
-+	 * LPDDR-specific functions have stubs which will halt upon execution.
-+	 */
-+	bool lpddr;
-+
-+	uint8_t lanes;
-+
-+	/* FIXME: ECC support missing */
-+	bool is_ecc;
-+};
-+
-+struct register_save_frame {
-+	uint32_t ddrio_per_byte[NUM_CHANNELS][NUM_LANES][DDRIO_PER_BYTE_REGISTER_COUNT];
-+	uint32_t ddrio_per_ch[NUM_CHANNELS][DDRIO_PER_CH_REGISTER_COUNT];
-+	uint32_t ddrio_common[DDRIO_COMMON_REGISTER_COUNT];
-+	uint32_t mcmain_per_ch[NUM_CHANNELS][MCMAIN_PER_CH_REGISTER_COUNT];
-+	uint32_t misc_common[MISC_COMMON_REGISTER_COUNT];
-+	struct save_params params;
-+};
-+
-+struct register_save_frame *reg_frame_ptr(void)
-+{
-+	/* The chonky register save frame struct, used for fast boot and S3 resume */
-+	static struct register_save_frame register_frame = { 0 };
-+	return &register_frame;
-+}
-+
-+size_t reg_frame_size(void)
-+{
-+	return sizeof(struct register_save_frame);
-+}
-+
-+typedef void (*reg_func_t)(const uint16_t offset, uint32_t *const value);
-+
-+static void save_value(const uint16_t offset, uint32_t *const value)
-+{
-+	*value = mchbar_read32(offset);
-+}
-+
-+static void restore_value(const uint16_t offset, uint32_t *const value)
-+{
-+	mchbar_write32(offset, *value);
-+}
-+
-+static void save_restore(
-+	uint32_t *reg_frame,
-+	const uint16_t g_offset,
-+	const struct register_save *reg_save_list,
-+	const size_t reg_save_length,
-+	reg_func_t handle_reg)
-+{
-+	for (size_t i = 0; i < reg_save_length; i++) {
-+		const struct register_save *entry = &reg_save_list[i];
-+		for (uint16_t offset = entry->lower; offset <= entry->upper; offset += 4) {
-+			handle_reg(offset + g_offset, reg_frame++);
-+		}
-+	}
-+}
-+
-+static void save_restore_all(struct register_save_frame *reg_frame, reg_func_t handle_reg)
-+{
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		for (uint8_t byte = 0; byte < NUM_LANES; byte++) {
-+			const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, byte);
-+			save_restore(
-+				reg_frame->ddrio_per_byte[channel][byte],
-+				g_offset,
-+				ddrio_per_byte_list,
-+				ARRAY_SIZE(ddrio_per_byte_list),
-+				handle_reg);
-+		}
-+	}
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		const uint16_t g_offset = _DDRIO_C_R_B(0, channel, 0, 0);
-+		save_restore(
-+			reg_frame->ddrio_per_ch[channel],
-+			g_offset,
-+			ddrio_per_ch_list,
-+			ARRAY_SIZE(ddrio_per_ch_list),
-+			handle_reg);
-+	}
-+	save_restore(
-+		reg_frame->ddrio_common,
-+		0,
-+		ddrio_common_list,
-+		ARRAY_SIZE(ddrio_common_list),
-+		handle_reg);
-+
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		const uint16_t g_offset = _MCMAIN_C(0, channel);
-+		save_restore(
-+			reg_frame->mcmain_per_ch[channel],
-+			g_offset,
-+			mcmain_per_ch_list,
-+			ARRAY_SIZE(mcmain_per_ch_list),
-+			handle_reg);
-+	}
-+	save_restore(
-+		reg_frame->misc_common,
-+		0,
-+		misc_common_list,
-+		ARRAY_SIZE(misc_common_list),
-+		handle_reg);
-+}
-+
-+enum raminit_status save_training_values(struct sysinfo *ctrl)
-+{
-+	save_restore_all(reg_frame_ptr(), save_value);
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
-+enum raminit_status restore_training_values(struct sysinfo *ctrl)
-+{
-+	save_restore_all(reg_frame_ptr(), restore_value);
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
-+enum raminit_status save_non_training(struct sysinfo *ctrl)
-+{
-+	struct register_save_frame *reg_frame = reg_frame_ptr();
-+	struct save_params *params = &reg_frame->params;
-+
-+	params->is_initialised = true;
-+
-+	params->base_freq     = ctrl->base_freq;
-+	params->multiplier    = ctrl->multiplier;
-+	params->mem_clock_mhz = ctrl->mem_clock_mhz;
-+	params->mem_clock_fs  = ctrl->mem_clock_fs;
-+	params->qclkps        = ctrl->qclkps;
-+	params->cas_supported = ctrl->cas_supported;
-+	params->cpu           = ctrl->cpu;
-+	params->stepping      = ctrl->stepping;
-+	params->vdd_mv        = ctrl->vdd_mv;
-+	params->flags         = ctrl->flags;
-+
-+	params->tCK       = ctrl->tCK;
-+	params->tAA       = ctrl->tAA;
-+	params->tWR       = ctrl->tWR;
-+	params->tRCD      = ctrl->tRCD;
-+	params->tRRD      = ctrl->tRRD;
-+	params->tRP       = ctrl->tRP;
-+	params->tRAS      = ctrl->tRAS;
-+	params->tRC       = ctrl->tRC;
-+	params->tRFC      = ctrl->tRFC;
-+	params->tWTR      = ctrl->tWTR;
-+	params->tRTP      = ctrl->tRTP;
-+	params->tFAW      = ctrl->tFAW;
-+	params->tCWL      = ctrl->tCWL;
-+	params->tCMD      = ctrl->tCMD;
-+	params->tREFI     = ctrl->tREFI;
-+	params->tXP       = ctrl->tXP;
-+
-+	params->chanmap = ctrl->chanmap;
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		params->lpddr_cke_rank_map[channel] = ctrl->lpddr_cke_rank_map[channel];
-+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++)
-+			params->dimms[channel][slot] = ctrl->dimms[channel][slot];
-+	}
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		params->dpc[channel] = ctrl->dpc[channel];
-+		params->rankmap[channel] = ctrl->rankmap[channel];
-+		params->rank_mirrored[channel] = ctrl->rank_mirrored[channel];
-+		params->channel_size_mb[channel] = ctrl->channel_size_mb[channel];
-+	}
-+	params->lpddr = ctrl->lpddr;
-+	params->lanes = ctrl->lanes;
-+	params->is_ecc = ctrl->is_ecc;
-+	return RAMINIT_STATUS_SUCCESS;
-+}
-+
-+#define RAMINIT_COMPARE(_s1, _s2) \
-+	((sizeof(_s1) == sizeof(_s2)) && !memcmp(_s1, _s2, sizeof(_s1)))
-+
-+enum raminit_status restore_non_training(struct sysinfo *ctrl)
-+{
-+	struct register_save_frame *reg_frame = reg_frame_ptr();
-+	struct save_params *params = &reg_frame->params;
-+
-+	if (!params->is_initialised) {
-+		printk(BIOS_WARNING, "Cannot fast boot: saved data is invalid\n");
-+		return RAMINIT_STATUS_INVALID_CACHE;
-+	}
-+
-+	if (!RAMINIT_COMPARE(ctrl->dimms, params->dimms)) {
-+		printk(BIOS_WARNING, "Cannot fast boot: DIMMs have changed\n");
-+		return RAMINIT_STATUS_INVALID_CACHE;
-+	}
-+
-+	if (ctrl->cpu != params->cpu) {
-+		printk(BIOS_WARNING, "Cannot fast boot: CPU has changed\n");
-+		return RAMINIT_STATUS_INVALID_CACHE;
-+	}
-+
-+	ctrl->base_freq     = params->base_freq;
-+	ctrl->multiplier    = params->multiplier;
-+	ctrl->mem_clock_mhz = params->mem_clock_mhz;
-+	ctrl->mem_clock_fs  = params->mem_clock_fs;
-+	ctrl->qclkps        = params->qclkps;
-+	ctrl->cas_supported = params->cas_supported;
-+	ctrl->cpu           = params->cpu;
-+	ctrl->stepping      = params->stepping;
-+	ctrl->vdd_mv        = params->vdd_mv;
-+	ctrl->flags         = params->flags;
-+
-+	ctrl->tCK       = params->tCK;
-+	ctrl->tAA       = params->tAA;
-+	ctrl->tWR       = params->tWR;
-+	ctrl->tRCD      = params->tRCD;
-+	ctrl->tRRD      = params->tRRD;
-+	ctrl->tRP       = params->tRP;
-+	ctrl->tRAS      = params->tRAS;
-+	ctrl->tRC       = params->tRC;
-+	ctrl->tRFC      = params->tRFC;
-+	ctrl->tWTR      = params->tWTR;
-+	ctrl->tRTP      = params->tRTP;
-+	ctrl->tFAW      = params->tFAW;
-+	ctrl->tCWL      = params->tCWL;
-+	ctrl->tCMD      = params->tCMD;
-+	ctrl->tREFI     = params->tREFI;
-+	ctrl->tXP       = params->tXP;
-+
-+	ctrl->chanmap = params->chanmap;
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		ctrl->lpddr_cke_rank_map[channel] = params->lpddr_cke_rank_map[channel];
-+		for (uint8_t slot = 0; slot < NUM_SLOTS; slot++)
-+			ctrl->dimms[channel][slot] = params->dimms[channel][slot];
-+	}
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		ctrl->dpc[channel] = params->dpc[channel];
-+		ctrl->rankmap[channel] = params->rankmap[channel];
-+		ctrl->rank_mirrored[channel] = params->rank_mirrored[channel];
-+		ctrl->channel_size_mb[channel] = params->channel_size_mb[channel];
-+	}
-+	ctrl->lpddr = params->lpddr;
-+	ctrl->lanes = params->lanes;
-+	ctrl->is_ecc = params->is_ecc;
-+	return RAMINIT_STATUS_SUCCESS;
-+}
--- 
-2.39.5
-

config/coreboot/default/patches/0046-haswell-NRI-Do-sense-amplifier-offset-training.patch

@@ -1,476 +0,0 @@
-From 02aa0c5612388e35f5dd1ff9c5f7a7b5b48fb9c0 Mon Sep 17 00:00:00 2001
-From: Angel Pons <th3fanbus@gmail.com>
-Date: Wed, 17 Apr 2024 13:20:32 +0200
-Subject: [PATCH 46/51] haswell NRI: Do sense amplifier offset training
-
-Quoting Wikipedia:
-
-  A sense amplifier is a circuit that is used to amplify and detect
-  small signals in electronic systems. It is commonly used in memory
-  circuits, such as dynamic random access memory (DRAM), to read and
-  amplify the weak signals stored in memory cells.
-
-In this case, we're calibrating the sense amplifiers in the memory
-controller. This training procedure uses a magic "sense amp offset
-cancel" mode of the DDRIO to observe the sampled logic levels, and
-sweeps Vref to find the low-high transition for each bit lane. The
-procedure consists of two stages: the first stage centers per-byte
-Vref (to ensure per-bit Vref offsets are as small as possible) and
-the second stage centers per-bit Vref.
-
-Because this procedure uses the "sense amp offset cancel" mode, it
-does not rely on DRAM being trained. It is assumed that the memory
-controller simply makes sense amp output levels observable via the
-`DDR_DATA_TRAIN_FEEDBACK` register and that the memory bus is idle
-during this training step (so the lane voltage is Vdd / 2).
-
-Note: This procedure will need to be adapted for Broadwell because
-it has per-rank per-bit RxVref registers, whereas Haswell only has
-a single per-bit RxVref register for all ranks.
-
-Change-Id: Ia07db68763f90e9701c8a376e01279ada8dbbe07
-Signed-off-by: Angel Pons <th3fanbus@gmail.com>
----
- .../intel/haswell/native_raminit/Makefile.mk  |   1 +
- .../haswell/native_raminit/raminit_main.c     |   1 +
- .../haswell/native_raminit/raminit_native.h   |  12 +
- .../native_raminit/train_sense_amp_offset.c   | 341 ++++++++++++++++++
- .../intel/haswell/registers/mchbar.h          |   2 +
- 5 files changed, 357 insertions(+)
- create mode 100644 src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
-
-diff --git a/src/northbridge/intel/haswell/native_raminit/Makefile.mk b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-index 8fdd17c542..4bd668a2d6 100644
---- a/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-+++ b/src/northbridge/intel/haswell/native_raminit/Makefile.mk
-@@ -21,3 +21,4 @@ romstage-y += timings_refresh.c
- romstage-y += train_jedec_write_leveling.c
- romstage-y += train_read_mpr.c
- romstage-y += train_receive_enable.c
-+romstage-y += train_sense_amp_offset.c
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-index 056dde1adc..ce637e2d03 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
-@@ -60,6 +60,7 @@ static const struct task_entry cold_boot[] = {
- 	{ configure_memory_map,                                   true, "MEMMAP",     },
- 	{ do_jedec_init,                                          true, "JEDECINIT",  },
- 	{ pre_training,                                           true, "PRETRAIN",   },
-+	{ train_sense_amp_offset,                                 true, "SOT",        },
- 	{ train_receive_enable,                                   true, "RCVET",      },
- 	{ train_read_mpr,                                         true, "RDMPRT",     },
- 	{ train_jedec_write_leveling,                             true, "JWRL",       },
-diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-index 2ac16eaad3..07eea98831 100644
---- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
-@@ -23,6 +23,8 @@
- #define NUM_LANES		9
- #define NUM_LANES_NO_ECC	8
- 
-+#define NUM_BITS		8
-+
- #define COMP_INT		10
- 
- /* Always use 12 legs for emphasis (not trained) */
-@@ -219,6 +221,7 @@ enum raminit_status {
- 	RAMINIT_STATUS_MPLL_INIT_FAILURE,
- 	RAMINIT_STATUS_POLL_TIMEOUT,
- 	RAMINIT_STATUS_REUT_ERROR,
-+	RAMINIT_STATUS_SAMP_OFFSET_FAILURE,
- 	RAMINIT_STATUS_RCVEN_FAILURE,
- 	RAMINIT_STATUS_RMPR_FAILURE,
- 	RAMINIT_STATUS_JWRL_FAILURE,
-@@ -244,6 +247,12 @@ struct raminit_dimm_info {
- 	bool valid;
- };
- 
-+struct vref_margin {
-+	uint8_t low;
-+	uint8_t center;
-+	uint8_t high;
-+};
-+
- struct sysinfo {
- 	enum raminit_boot_mode bootmode;
- 	enum generic_stepping stepping;
-@@ -331,6 +340,8 @@ struct sysinfo {
- 	uint8_t rxdqsn[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
- 	int8_t  rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
- 
-+	struct vref_margin rxdqvrefpb[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES][NUM_BITS];
-+
- 	uint8_t clk_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
- 	uint8_t ctl_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
- 	uint8_t cke_pi_code[NUM_CHANNELS][NUM_SLOTRANKS];
-@@ -453,6 +464,7 @@ enum raminit_status convert_timings(struct sysinfo *ctrl);
- enum raminit_status configure_mc(struct sysinfo *ctrl);
- enum raminit_status configure_memory_map(struct sysinfo *ctrl);
- enum raminit_status do_jedec_init(struct sysinfo *ctrl);
-+enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl);
- enum raminit_status train_receive_enable(struct sysinfo *ctrl);
- enum raminit_status train_read_mpr(struct sysinfo *ctrl);
- enum raminit_status train_jedec_write_leveling(struct sysinfo *ctrl);
-diff --git a/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
-new file mode 100644
-index 0000000000..d4f199fefb
---- /dev/null
-+++ b/src/northbridge/intel/haswell/native_raminit/train_sense_amp_offset.c
-@@ -0,0 +1,341 @@
-+/* SPDX-License-Identifier: GPL-2.0-or-later */
-+
-+#include <assert.h>
-+#include <commonlib/bsd/clamp.h>
-+#include <console/console.h>
-+#include <delay.h>
-+#include <lib.h>
-+#include <types.h>
-+
-+#include "raminit_native.h"
-+
-+#define VREF_OFFSET_PLOT	RAM_DEBUG
-+#define SAMP_OFFSET_PLOT	RAM_DEBUG
-+
-+struct vref_train_data {
-+	int8_t best_sum;
-+	int8_t best_vref;
-+	int8_t sum_bits;
-+	uint8_t high_mask;
-+	uint8_t low_mask;
-+};
-+
-+static enum raminit_status train_vref_offset(struct sysinfo *ctrl)
-+{
-+	const int8_t vref_start = -15;
-+	const int8_t vref_stop  = 15;
-+	const struct vref_train_data initial_vref_values = {
-+		.best_sum  = -NUM_LANES,
-+		.best_vref = 0,
-+		.high_mask = 0,
-+		.low_mask  = 0xff,
-+	};
-+	struct vref_train_data vref_data[NUM_CHANNELS][NUM_LANES];
-+
-+	printk(VREF_OFFSET_PLOT, "Plot of sum_bits across Vref settings\nChannel");
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		printk(VREF_OFFSET_PLOT, "\t%u\t\t", channel);
-+	}
-+
-+	printk(VREF_OFFSET_PLOT, "\nByte");
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		printk(VREF_OFFSET_PLOT, "\t");
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			printk(VREF_OFFSET_PLOT, "%u ", byte);
-+			vref_data[channel][byte] = initial_vref_values;
-+			union ddr_data_control_2_reg data_control_2 = {
-+				.raw = ctrl->dq_control_2[channel][byte],
-+			};
-+			data_control_2.force_bias_on = 1;
-+			data_control_2.force_rx_on   = 1;
-+			mchbar_write32(DQ_CONTROL_2(channel, byte), data_control_2.raw);
-+		}
-+	}
-+
-+	/* Sweep through Vref settings and find point SampOffset of +/- 7 passes */
-+	printk(VREF_OFFSET_PLOT, "\n1/2 Vref");
-+	for (int8_t vref = vref_start; vref <= vref_stop; vref++) {
-+		printk(VREF_OFFSET_PLOT, "\n% 3d", vref);
-+
-+		/*
-+		 * To perform this test, enable offset cancel mode and enable ODT.
-+		 * Check results and update variables. Ideal result is all zeroes.
-+		 * Clear offset cancel mode at end of test to write RX_OFFSET_VDQ.
-+		 */
-+		change_1d_margin_multicast(ctrl, RdV, vref, 0, false, REG_FILE_USE_RANK);
-+
-+		/* Program settings for Vref and SampOffset = 7 (8 + 7) */
-+		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0xffffffff);
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!does_ch_exist(ctrl, channel))
-+				continue;
-+
-+			/* Propagate delay values (without a read command) */
-+			union ddr_data_control_0_reg data_control_0 = {
-+				.raw = ctrl->dq_control_0[channel],
-+			};
-+			data_control_0.read_rf_rd      = 1;
-+			data_control_0.read_rf_wr      = 0;
-+			data_control_0.read_rf_rank    = 0;
-+			data_control_0.force_odt_on    = 1;
-+			data_control_0.samp_train_mode = 1;
-+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+			udelay(1);
-+			data_control_0.samp_train_mode = 0;
-+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				const uint8_t feedback = get_data_train_feedback(channel, byte);
-+				struct vref_train_data *curr_data = &vref_data[channel][byte];
-+				curr_data->low_mask &= feedback;
-+				curr_data->sum_bits = -popcnt(feedback);
-+			}
-+		}
-+
-+		/* Program settings for Vref and SampOffset = -7 (8 - 7) */
-+		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, 0x11111111);
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!does_ch_exist(ctrl, channel))
-+				continue;
-+
-+			/* Propagate delay values (without a read command) */
-+			union ddr_data_control_0_reg data_control_0 = {
-+				.raw = ctrl->dq_control_0[channel],
-+			};
-+			data_control_0.read_rf_rd      = 1;
-+			data_control_0.read_rf_wr      = 0;
-+			data_control_0.read_rf_rank    = 0;
-+			data_control_0.force_odt_on    = 1;
-+			data_control_0.samp_train_mode = 1;
-+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+			udelay(1);
-+			data_control_0.samp_train_mode = 0;
-+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+			printk(VREF_OFFSET_PLOT, "\t");
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				const uint8_t feedback = get_data_train_feedback(channel, byte);
-+				struct vref_train_data *curr_data = &vref_data[channel][byte];
-+				curr_data->high_mask |= feedback;
-+				curr_data->sum_bits += popcnt(feedback);
-+				printk(VREF_OFFSET_PLOT, "%d ", curr_data->sum_bits);
-+				if (curr_data->sum_bits > curr_data->best_sum) {
-+					curr_data->best_sum  = curr_data->sum_bits;
-+					curr_data->best_vref = vref;
-+					ctrl->rxvref[channel][0][byte] = vref;
-+				} else if (curr_data->sum_bits == curr_data->best_sum) {
-+					curr_data->best_vref = vref;
-+				}
-+			}
-+		}
-+	}
-+	printk(BIOS_DEBUG, "\n\nHi-Lo (XOR):");
-+	enum raminit_status status = RAMINIT_STATUS_SUCCESS;
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		printk(BIOS_DEBUG, "\n  C%u:", channel);
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			struct vref_train_data *const curr_data = &vref_data[channel][byte];
-+			const uint8_t bit_xor = curr_data->high_mask ^ curr_data->low_mask;
-+			printk(BIOS_DEBUG, "\t0x%02x", bit_xor);
-+			if (bit_xor == 0xff)
-+				continue;
-+
-+			/* Report an error if any bit did not change */
-+			status = RAMINIT_STATUS_SAMP_OFFSET_FAILURE;
-+		}
-+	}
-+	if (status)
-+		printk(BIOS_ERR, "\nUnexpected bit error in Vref offset training\n");
-+
-+	printk(BIOS_DEBUG, "\n\nRdVref:");
-+	change_1d_margin_multicast(ctrl, RdV, 0, 0, false, REG_FILE_USE_RANK);
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		printk(BIOS_DEBUG, "\n  C%u:", channel);
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			struct vref_train_data *const curr_data = &vref_data[channel][byte];
-+			const int8_t vref_width =
-+				curr_data->best_vref - ctrl->rxvref[channel][0][byte];
-+
-+			/*
-+			 * Step size for Rx Vref in DATA_OFFSET_TRAIN is about 3.9 mV
-+			 * whereas Rx Vref step size in RX_TRAIN_RANK is about 7.8 mV
-+			 */
-+			int8_t vref = ctrl->rxvref[channel][0][byte] + vref_width / 2;
-+			if (vref < 0)
-+				vref--;
-+			else
-+				vref++;
-+
-+			for (uint8_t rank = 0; rank < NUM_SLOTRANKS; rank++) {
-+				if (!rank_in_ch(ctrl, rank, channel))
-+					continue;
-+
-+				ctrl->rxvref[channel][rank][byte] = vref / 2;
-+				update_rxt(ctrl, channel, rank, byte, RXT_RESTORE, 0);
-+			}
-+			printk(BIOS_DEBUG, "\t% 4d", ctrl->rxvref[channel][0][byte]);
-+		}
-+	}
-+	printk(BIOS_DEBUG, "\n\n");
-+	return status;
-+}
-+
-+/**
-+ * LPDDR has an additional bit for DQS per each byte.
-+ *
-+ * TODO: The DQS value must be written into Data Control 2.
-+ */
-+#define NUM_OFFSET_TRAIN_BITS	(NUM_BITS + 1)
-+
-+#define PLOT_CH_SPACE		"  "
-+
-+struct samp_train_data {
-+	uint8_t first_zero;
-+	uint8_t last_one;
-+};
-+
-+static void train_samp_offset(struct sysinfo *ctrl)
-+{
-+	const uint8_t max_train_bits = ctrl->lpddr ? NUM_OFFSET_TRAIN_BITS : NUM_BITS;
-+
-+	struct samp_train_data samp_data[NUM_CHANNELS][NUM_LANES][NUM_OFFSET_TRAIN_BITS] = {0};
-+
-+	printk(BIOS_DEBUG, "Channel ");
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		printk(BIOS_DEBUG, "%u ", channel); /* Same length as PLOT_CH_SPACE */
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+			printk(BIOS_DEBUG, "        %s ", ctrl->lpddr ? " " : "");
-+	}
-+	printk(BIOS_DEBUG, "\nByte    ");
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+			printk(BIOS_DEBUG, "%u       %s ", byte, ctrl->lpddr ? " " : "");
-+
-+		printk(BIOS_DEBUG, PLOT_CH_SPACE);
-+	}
-+	printk(SAMP_OFFSET_PLOT, "\nBits    ");
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+			printk(SAMP_OFFSET_PLOT, "01234567%s ", ctrl->lpddr ? "S" : "");
-+
-+		printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
-+	}
-+	printk(SAMP_OFFSET_PLOT, "\n SAmp\n");
-+	for (uint8_t samp_offset = 1; samp_offset <= 15; samp_offset++) {
-+		printk(SAMP_OFFSET_PLOT, "% 5d\t", samp_offset);
-+
-+		uint32_t rx_offset_vdq = 0;
-+		for (uint8_t bit = 0; bit < NUM_BITS; bit++) {
-+			rx_offset_vdq += samp_offset << (4 * bit);
-+		}
-+		mchbar_write32(DDR_DATA_RX_OFFSET_VDQ, rx_offset_vdq);
-+		for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+			if (!does_ch_exist(ctrl, channel))
-+				continue;
-+
-+			/* Propagate delay values (without a read command) */
-+			union ddr_data_control_0_reg data_control_0 = {
-+				.raw = ctrl->dq_control_0[channel],
-+			};
-+			data_control_0.read_rf_rd      = 1;
-+			data_control_0.read_rf_wr      = 0;
-+			data_control_0.read_rf_rank    = 0;
-+			data_control_0.force_odt_on    = 1;
-+			data_control_0.samp_train_mode = 1;
-+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+			udelay(1);
-+			for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+				const uint32_t feedback =
-+					get_data_train_feedback(channel, byte);
-+
-+				for (uint8_t bit = 0; bit < max_train_bits; bit++) {
-+					struct samp_train_data *const curr_data =
-+							&samp_data[channel][byte][bit];
-+					const bool result = feedback & BIT(bit);
-+					if (result) {
-+						curr_data->last_one = samp_offset;
-+					} else if (curr_data->first_zero == 0) {
-+						curr_data->first_zero = samp_offset;
-+					}
-+					printk(SAMP_OFFSET_PLOT, result ? "." : "#");
-+				}
-+				printk(SAMP_OFFSET_PLOT, " ");
-+			}
-+			printk(SAMP_OFFSET_PLOT, PLOT_CH_SPACE);
-+			data_control_0.samp_train_mode = 0;
-+			mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), data_control_0.raw);
-+		}
-+		printk(SAMP_OFFSET_PLOT, "\n");
-+	}
-+	printk(BIOS_DEBUG, "\nBitSAmp ");
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++) {
-+			uint32_t rx_offset_vdq = 0;
-+			for (uint8_t bit = 0; bit < max_train_bits; bit++) {
-+				struct samp_train_data *const curr_data =
-+						&samp_data[channel][byte][bit];
-+
-+				uint8_t vref = curr_data->first_zero + curr_data->last_one;
-+				vref = clamp_u8(0, vref / 2, 15);
-+				/*
-+				 * Check for saturation conditions to make sure
-+				 * we are as close as possible to Vdd/2 (750 mV).
-+				 */
-+				if (curr_data->first_zero == 0)
-+					vref = 15;
-+				if (curr_data->last_one == 0)
-+					vref = 0;
-+
-+				ctrl->rxdqvrefpb[channel][0][byte][bit].center = vref;
-+				rx_offset_vdq += vref & 0xf << (4 * bit);
-+				printk(BIOS_DEBUG, "%x", vref);
-+			}
-+			mchbar_write32(RX_OFFSET_VDQ(channel, byte), rx_offset_vdq);
-+			printk(BIOS_DEBUG, " ");
-+			download_regfile(ctrl, channel, 1, 0, REG_FILE_USE_RANK, 0, 1, 0);
-+		}
-+		printk(BIOS_DEBUG, PLOT_CH_SPACE);
-+	}
-+	printk(BIOS_DEBUG, "\n");
-+}
-+
-+enum raminit_status train_sense_amp_offset(struct sysinfo *ctrl)
-+{
-+	printk(BIOS_DEBUG, "Stage 1: Vref offset training\n");
-+	const enum raminit_status status = train_vref_offset(ctrl);
-+
-+	printk(BIOS_DEBUG, "Stage 2: Samp offset training\n");
-+	train_samp_offset(ctrl);
-+
-+	/* Clean up after test */
-+	for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
-+		if (!does_ch_exist(ctrl, channel))
-+			continue;
-+
-+		mchbar_write32(DDR_DATA_ch_CONTROL_0(channel), ctrl->dq_control_0[channel]);
-+		for (uint8_t byte = 0; byte < ctrl->lanes; byte++)
-+			mchbar_write32(DQ_CONTROL_2(channel, byte),
-+				ctrl->dq_control_2[channel][byte]);
-+	}
-+	io_reset();
-+	return status;
-+}
-diff --git a/src/northbridge/intel/haswell/registers/mchbar.h b/src/northbridge/intel/haswell/registers/mchbar.h
-index 49a215aa71..1a168a3fc8 100644
---- a/src/northbridge/intel/haswell/registers/mchbar.h
-+++ b/src/northbridge/intel/haswell/registers/mchbar.h
-@@ -18,6 +18,8 @@
- #define RX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0000, ch, rank, byte)
- #define TX_TRAIN_ch_r_b(ch, rank, byte)		_DDRIO_C_R_B(0x0020, ch, rank, byte)
- 
-+#define RX_OFFSET_VDQ(ch, byte)			_DDRIO_C_R_B(0x004c, ch, 0, byte)
-+
- #define DDR_DATA_TRAIN_FEEDBACK(ch, byte)	_DDRIO_C_R_B(0x0054, ch, 0, byte)
- 
- #define DQ_CONTROL_1(ch, byte)			_DDRIO_C_R_B(0x0060, ch, 0, byte)
--- 
-2.39.5
-

config/coreboot/default/patches/0047-nb-x4x-define-INTEL_GMA_DPLL_REF_FREQ.patch

@@ -1,52 +0,0 @@
-From 53f2d47ee6ebaa8d47b076a6c2a1514c91247b95 Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
-Date: Mon, 12 Aug 2024 02:15:24 +0100
-Subject: [PATCH 47/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
-
-set it to 96MHz. fixes the following build error when
-building for x4x boards e.g. gigabyte ga-g41m-es2l:
-
-hw-gfx-gma-plls.adb:465:46: error: "INTEL_GMA_DPLL_REF_FREQ" not declared in "Config"
-make: *** [Makefile:423: build/ramstage/libgfxinit/common/g45/hw-gfx-gma-plls.o] Error 1
-
-this error was introduced when merging coreboot/dell
-into coreboot/default in lbmk. nicholas chin's fix in lbmk
-was as follows:
-
-commit 8629873a6043067affc137be275b7aa69cb1f10c
-Author: Nicholas Chin <nic.c3.14@gmail.com>
-Date:   Mon May 20 10:46:25 2024 -0600
-
-    Fix E6400 display issue with 1440 x 900 panel
-
-this currently corresponds to the patch in lbmk,
-as of 12 august 2024:
-
-0042-mb-dell-e6400-Use-100-MHz-reference-clock-for-displa.patch
-
-The assumption prior to Nicholas's fix was 96MHz, so set
-it accordingly on x4x northbridge.
-
-Signed-off-by: Leah Rowe <info@minifree.org>
----
- src/northbridge/intel/x4x/Kconfig | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig
-index 9af063819b..93ba575b95 100644
---- a/src/northbridge/intel/x4x/Kconfig
-+++ b/src/northbridge/intel/x4x/Kconfig
-@@ -14,6 +14,10 @@ config NORTHBRIDGE_INTEL_X4X
- 
- if NORTHBRIDGE_INTEL_X4X
- 
-+config INTEL_GMA_DPLL_REF_FREQ
-+	int
-+	default 96000000
-+
- config CBFS_SIZE
- 	default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX
- 
--- 
-2.39.5
-

config/coreboot/default/patches/0048-mb-dell-Convert-E6400-into-a-variant.patch

@@ -1,243 +0,0 @@
-From 92556743e92cc02524296b653de5241160876218 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Thu, 26 Sep 2024 19:48:26 -0600
-Subject: [PATCH 48/51] mb/dell: Convert E6400 into a variant
-
-All the GM45 Dell Latitudes should be nearly identical, so convert the
-E6400 port into a variant so that future ports for the other systems can
-share code with each other.
-
-Change-Id: I8094fce56eaaadb20aef173644cd3b2c0b008e95
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/e6400/Makefile.mk          |  10 --------
- .../dell/{e6400 => gm45_latitude}/Kconfig     |  22 +++++++++++++-----
- .../{e6400 => gm45_latitude}/Kconfig.name     |   0
- src/mainboard/dell/gm45_latitude/Makefile.mk  |  11 +++++++++
- .../dell/{e6400 => gm45_latitude}/acpi/ec.asl |   0
- .../acpi/ich9_pci_irqs.asl                    |   0
- .../{e6400 => gm45_latitude}/acpi/superio.asl |   0
- .../dell/{e6400 => gm45_latitude}/blc.c       |   0
- .../{e6400 => gm45_latitude}/board_info.txt   |   0
- .../dell/{e6400 => gm45_latitude}/bootblock.c |   0
- .../{e6400 => gm45_latitude}/cmos.default     |   0
- .../dell/{e6400 => gm45_latitude}/cmos.layout |   0
- .../dell/{e6400 => gm45_latitude}/cstates.c   |   0
- .../{e6400 => gm45_latitude}/devicetree.cb    |   1 -
- .../dell/{e6400 => gm45_latitude}/dsdt.asl    |   0
- .../dell/{e6400 => gm45_latitude}/mainboard.c |   0
- .../dell/{e6400 => gm45_latitude}/romstage.c  |   0
- .../variants}/e6400/data.vbt                  | Bin
- .../variants}/e6400/gma-mainboard.ads         |   0
- .../{ => gm45_latitude/variants}/e6400/gpio.c |   0
- .../variants}/e6400/hda_verb.c                |   0
- .../variants/e6400/overridetree.cb            |   7 ++++++
- 22 files changed, 34 insertions(+), 17 deletions(-)
- delete mode 100644 src/mainboard/dell/e6400/Makefile.mk
- rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig (64%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/Kconfig.name (100%)
- create mode 100644 src/mainboard/dell/gm45_latitude/Makefile.mk
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ec.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/ich9_pci_irqs.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/acpi/superio.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/blc.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/board_info.txt (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/bootblock.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.default (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cmos.layout (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/cstates.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/devicetree.cb (98%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/dsdt.asl (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/mainboard.c (100%)
- rename src/mainboard/dell/{e6400 => gm45_latitude}/romstage.c (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/data.vbt (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gma-mainboard.ads (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/gpio.c (100%)
- rename src/mainboard/dell/{ => gm45_latitude/variants}/e6400/hda_verb.c (100%)
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-
-diff --git a/src/mainboard/dell/e6400/Makefile.mk b/src/mainboard/dell/e6400/Makefile.mk
-deleted file mode 100644
-index ca3a82db48..0000000000
---- a/src/mainboard/dell/e6400/Makefile.mk
-+++ /dev/null
-@@ -1,10 +0,0 @@
--## SPDX-License-Identifier: GPL-2.0-only
--
--bootblock-y += bootblock.c
--
--romstage-y += gpio.c
--
--ramstage-y += cstates.c
--ramstage-y += blc.c
--
--ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
-similarity index 64%
-rename from src/mainboard/dell/e6400/Kconfig
-rename to src/mainboard/dell/gm45_latitude/Kconfig
-index 6fe1b1c456..ba76fb6e8c 100644
---- a/src/mainboard/dell/e6400/Kconfig
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig
-@@ -1,9 +1,7 @@
- ## SPDX-License-Identifier: GPL-2.0-only
- 
--if BOARD_DELL_E6400
--
--config BOARD_SPECIFIC_OPTIONS
--	def_bool y
-+config BOARD_DELL_GM45_LATITUDE_COMMON
-+	def_bool n
- 	select SYSTEM_TYPE_LAPTOP
- 	select CPU_INTEL_SOCKET_P
- 	select NORTHBRIDGE_INTEL_GM45
-@@ -19,19 +17,31 @@ config BOARD_SPECIFIC_OPTIONS
- 	select INTEL_GMA_HAVE_VBT
- 	select EC_DELL_MEC5035
- 
-+
-+config BOARD_DELL_E6400
-+	select BOARD_DELL_GM45_LATITUDE_COMMON
-+
-+if BOARD_DELL_GM45_LATITUDE_COMMON
-+
- config INTEL_GMA_DPLL_REF_FREQ
- 	default 100000000
- 
- config MAINBOARD_DIR
--	default "dell/e6400"
-+	default "dell/gm45_latitude"
- 
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E6400" if BOARD_DELL_E6400
- 
-+config OVERRIDE_DEVICETREE
-+	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
-+
-+config VARIANT_DIR
-+	default "e6400" if BOARD_DELL_E6400
-+
- config USBDEBUG_HCD_INDEX
- 	default 1
- 
- config CBFS_SIZE
- 	default 0x1A0000
- 
--endif # BOARD_DELL_E6400
-+endif # BOARD_DELL_GM45_LATITUDE_COMMON
-diff --git a/src/mainboard/dell/e6400/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
-similarity index 100%
-rename from src/mainboard/dell/e6400/Kconfig.name
-rename to src/mainboard/dell/gm45_latitude/Kconfig.name
-diff --git a/src/mainboard/dell/gm45_latitude/Makefile.mk b/src/mainboard/dell/gm45_latitude/Makefile.mk
-new file mode 100644
-index 0000000000..5295d5be22
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/Makefile.mk
-@@ -0,0 +1,11 @@
-+## SPDX-License-Identifier: GPL-2.0-only
-+
-+bootblock-y += bootblock.c
-+
-+romstage-y += variants/$(VARIANT_DIR)/gpio.c
-+
-+ramstage-y += cstates.c
-+ramstage-y += blc.c
-+ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
-+
-+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/acpi/ec.asl b/src/mainboard/dell/gm45_latitude/acpi/ec.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/ec.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/ec.asl
-diff --git a/src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl b/src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/ich9_pci_irqs.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/ich9_pci_irqs.asl
-diff --git a/src/mainboard/dell/e6400/acpi/superio.asl b/src/mainboard/dell/gm45_latitude/acpi/superio.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/acpi/superio.asl
-rename to src/mainboard/dell/gm45_latitude/acpi/superio.asl
-diff --git a/src/mainboard/dell/e6400/blc.c b/src/mainboard/dell/gm45_latitude/blc.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/blc.c
-rename to src/mainboard/dell/gm45_latitude/blc.c
-diff --git a/src/mainboard/dell/e6400/board_info.txt b/src/mainboard/dell/gm45_latitude/board_info.txt
-similarity index 100%
-rename from src/mainboard/dell/e6400/board_info.txt
-rename to src/mainboard/dell/gm45_latitude/board_info.txt
-diff --git a/src/mainboard/dell/e6400/bootblock.c b/src/mainboard/dell/gm45_latitude/bootblock.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/bootblock.c
-rename to src/mainboard/dell/gm45_latitude/bootblock.c
-diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/gm45_latitude/cmos.default
-similarity index 100%
-rename from src/mainboard/dell/e6400/cmos.default
-rename to src/mainboard/dell/gm45_latitude/cmos.default
-diff --git a/src/mainboard/dell/e6400/cmos.layout b/src/mainboard/dell/gm45_latitude/cmos.layout
-similarity index 100%
-rename from src/mainboard/dell/e6400/cmos.layout
-rename to src/mainboard/dell/gm45_latitude/cmos.layout
-diff --git a/src/mainboard/dell/e6400/cstates.c b/src/mainboard/dell/gm45_latitude/cstates.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/cstates.c
-rename to src/mainboard/dell/gm45_latitude/cstates.c
-diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/gm45_latitude/devicetree.cb
-similarity index 98%
-rename from src/mainboard/dell/e6400/devicetree.cb
-rename to src/mainboard/dell/gm45_latitude/devicetree.cb
-index e9f3915d17..76dae87153 100644
---- a/src/mainboard/dell/e6400/devicetree.cb
-+++ b/src/mainboard/dell/gm45_latitude/devicetree.cb
-@@ -15,7 +15,6 @@ chip northbridge/intel/gm45
- 	register "pci_mmio_size" = "2048"
- 
- 	device domain 0 on
--		subsystemid 0x1028 0x0233 inherit
- 		ops gm45_pci_domain_ops
- 
- 		device pci 00.0 on end # host bridge
-diff --git a/src/mainboard/dell/e6400/dsdt.asl b/src/mainboard/dell/gm45_latitude/dsdt.asl
-similarity index 100%
-rename from src/mainboard/dell/e6400/dsdt.asl
-rename to src/mainboard/dell/gm45_latitude/dsdt.asl
-diff --git a/src/mainboard/dell/e6400/mainboard.c b/src/mainboard/dell/gm45_latitude/mainboard.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/mainboard.c
-rename to src/mainboard/dell/gm45_latitude/mainboard.c
-diff --git a/src/mainboard/dell/e6400/romstage.c b/src/mainboard/dell/gm45_latitude/romstage.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/romstage.c
-rename to src/mainboard/dell/gm45_latitude/romstage.c
-diff --git a/src/mainboard/dell/e6400/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
-similarity index 100%
-rename from src/mainboard/dell/e6400/data.vbt
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/data.vbt
-diff --git a/src/mainboard/dell/e6400/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
-similarity index 100%
-rename from src/mainboard/dell/e6400/gma-mainboard.ads
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/gma-mainboard.ads
-diff --git a/src/mainboard/dell/e6400/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/gpio.c
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/gpio.c
-diff --git a/src/mainboard/dell/e6400/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
-similarity index 100%
-rename from src/mainboard/dell/e6400/hda_verb.c
-rename to src/mainboard/dell/gm45_latitude/variants/e6400/hda_verb.c
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-new file mode 100644
-index 0000000000..acc34a2252
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e6400/overridetree.cb
-@@ -0,0 +1,7 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/gm45
-+	device domain 0 on
-+		subsystemid 0x1028 0x0233 inherit
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0049-mb-dell-gm45_latitudes-Add-E4300-variant.patch

@@ -1,332 +0,0 @@
-From ac8ac2543e3ebbc05f79f37d1460cde532a7ee1c Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Thu, 26 Sep 2024 19:51:25 -0600
-Subject: [PATCH 49/51] mb/dell/gm45_latitudes: Add E4300 variant
-
-Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/gm45_latitude/Kconfig      |   5 +
- src/mainboard/dell/gm45_latitude/Kconfig.name |   3 +
- .../gm45_latitude/variants/e4300/data.vbt     | Bin 0 -> 3881 bytes
- .../variants/e4300/gma-mainboard.ads          |  17 +++
- .../dell/gm45_latitude/variants/e4300/gpio.c  | 138 ++++++++++++++++++
- .../gm45_latitude/variants/e4300/hda_verb.c   |  37 +++++
- .../variants/e4300/overridetree.cb            |  10 ++
- 7 files changed, 210 insertions(+)
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
- create mode 100644 src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-
-diff --git a/src/mainboard/dell/gm45_latitude/Kconfig b/src/mainboard/dell/gm45_latitude/Kconfig
-index ba76fb6e8c..144f9bcdf0 100644
---- a/src/mainboard/dell/gm45_latitude/Kconfig
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig
-@@ -21,6 +21,9 @@ config BOARD_DELL_GM45_LATITUDE_COMMON
- config BOARD_DELL_E6400
- 	select BOARD_DELL_GM45_LATITUDE_COMMON
- 
-+config BOARD_DELL_E4300
-+	select BOARD_DELL_GM45_LATITUDE_COMMON
-+
- if BOARD_DELL_GM45_LATITUDE_COMMON
- 
- config INTEL_GMA_DPLL_REF_FREQ
-@@ -31,12 +34,14 @@ config MAINBOARD_DIR
- 
- config MAINBOARD_PART_NUMBER
- 	default "Latitude E6400" if BOARD_DELL_E6400
-+	default "Latitude E4300" if BOARD_DELL_E4300
- 
- config OVERRIDE_DEVICETREE
- 	default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
- 
- config VARIANT_DIR
- 	default "e6400" if BOARD_DELL_E6400
-+	default "e4300" if BOARD_DELL_E4300
- 
- config USBDEBUG_HCD_INDEX
- 	default 1
-diff --git a/src/mainboard/dell/gm45_latitude/Kconfig.name b/src/mainboard/dell/gm45_latitude/Kconfig.name
-index aefe777109..4dc95f46be 100644
---- a/src/mainboard/dell/gm45_latitude/Kconfig.name
-+++ b/src/mainboard/dell/gm45_latitude/Kconfig.name
-@@ -1,4 +1,7 @@
- ## SPDX-License-Identifier: GPL-2.0-only
- 
-+config BOARD_DELL_E4300
-+	bool "Latitude E4300"
-+
- config BOARD_DELL_E6400
- 	bool "Latitude E6400"
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt b/src/mainboard/dell/gm45_latitude/variants/e4300/data.vbt
-new file mode 100644
-index 0000000000000000000000000000000000000000..fa2f3db13f688b5687df16a155781d8674ea26f3
-GIT binary patch
-literal 3881
-zcmdT`eQXp(6#wnV-R;foUbovquV-n84`GWGmlkRzXWaG>Td6>yG#51CN?M@?>DeM+
-zBI$}GlK6F+nD{}Y|ClJzh>3}Rm=N?2Y5a<biIGGii6#d8gP4#QmGpeGyBx))(i;53
-zx0(69nR)Nco0&Inc1d4HFVD7b?CrX@org342aOf$sh&<9U7NP<Sl8a$zN4diQ+5M?
-z9rN*fa`GZDAW257d6jcVwtw%wp<VsFPss9IbIT6VyT7@GKQuhTyNCDm-+uql-l6R9
-zaA9y{CEr#U=-)Ruz;_Pq?H?H$9GyPr&Fjey7akuO+O>Nhx3i7B*>RjEs#<v0-hG36
-zcy@TCu#&g$*~7O8nNhxFaCC5F|KPw%gBc7st!SzQND;)Ih9pfkBd$T$U~A~qu#ltO
-zMczfDhAs`eH4JHpsJLH4lZIP4`dyfi4M|pkg+SayZ(n(7kunGFvl<qe=w81$=+A#a
-zN=hgb2&njUcPLB!=P$(o-$={^mxQGIHvtVGBS4IU%YyNVhd3krw*m^es@B12UftTZ
-zHsf}zTi<zK_vS6VeYx!qdQTpH>PQ-s5C6@#q~ze8SUuLOHbzw$htxKlQYWCt9NZmC
-zVLO$_s2tQZ9MvqmM&%tUr>K0RF`T3FGnHSdOj6O}3>K9-D$(bpD<v6uK&w=s5=N^P
-zn1nKYZrHyr#A-t5vRX$dPN$Pl=yivfA{67CP>h$)OQqAIh6jOwCxuw)qvS0N+Nk!?
-zI~I-~3&u$!iZQuCQ3;=xYZQ&}1^JS!6aFCSvPt-}q{`KV7o=aLI=_ERh8gM+`g(-E
-z9-*&C=<5;sdVc?y{2iwmrKs|~Kw5}Heji&vYYqJOG&As1`1?G0hsr2Y&r%2qq-H)u
-z>=c836bj~sR4T<{m@IvjLaC(P1v(j%W}uLfs)L<DD#SV;6@`cGC4?jgJ8YLq>~qi^
-z4yaW6zjKK*SSa$dvbC#eRZDAgQ@dDEfr?l)G{1I<Q#e&+8Yy!=BeKi&0@sfte<K0&
-zMgsgs0(vE~6cP&098SWEom4ZZF%<l!OeEuw4n?=)Y_tg#&wy^{e@5{s`F9qRm`5m;
-zi_|4iQq@4&R8mD)tJIvCw3$`@-B9JV=`1}s_;B_rjtcVXpQ!o`MAJ$M5w65C7t<Ku
-z%xfIo$p$+0N}Qe(C7MY#!0SQ1({^-qFj5ylEHjhwn>8}OhGtOw#1e$Fn9w<r1Zp}l
-zPz$#mOP$ow*1(UHvmCGVz;T^IRnSxa*6jz+_oSD)xmT|Cbl&YcJ5M&d?&+&NDI2Y0
-zO0ai&>sUmbC8g}vF{$V$Y~rFp!qRJP)Z!2NYEhIpf^PzD_^ptxacQ#R+9@(N>ibe6
-z@|mz|d=bjIxSe3u0>+jxdmFQMG4?34k2C9i#y(>91!n!pSR`S$B&>T9Y*WHMl(1e%
-zuvZiInS^yV!G28GmAbW9XHB~OfNnjavje*Qrfz+xvyXNAl5R-`OBnW@hPA<9+YI|D
-z!+P0Z#|`^S!}`Hs7Yw^5X*DKUOVaL7TBAv}d|dV9^O8rYn%=4o&5GjdSWeb`yeyf7
-zk&0z-2#I*9^ljWL^79K!Ex#yORz2-nxRYGT$+NdKUcs>{SI2Fyx@<{2w?w*#&%hG*
-zeY&DumV{4Nw4(1*^g5r`avbR44Nj-miiQs;Ii;O}*rL^|oYl8hQ9P@{Qf5}Gn;uRg
-zI{c?gKNv~R$<jgIlQvzm9GD`y{Dh<T(H)!WlUUWvtFvzDqaVV>&eHj<So5w}UG%+7
-zt=J~1YHpT3TjRY{XlrmCz6QBZ$WqGr>8!uus22Br_GkCD$Q)pf!<P$30Ez;o=qDzr
-z7@f;LJ+ZPlo=?}4PvMm&OKLGLZ0h1&n7U8@9GP~;8!wz(OqQ<s6e;@8hfYU0ht*9>
-zGh%f}_&(hXOZrW-WCWJVw`DdrczV_sXGaOvzjt%F!O;{7J-K<j&AXad#XeO8mgw(v
-z_Gj1VBJZIpZ<>`tJBTNGZHe^T`VrkY0pv~u^?l~DG9UD8p8(692<oYlGx5_cte6LX
-JE5(FU=`RLB=-&VU
-
-literal 0
-HcmV?d00001
-
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
-new file mode 100644
-index 0000000000..89b81b3d69
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gma-mainboard.ads
-@@ -0,0 +1,17 @@
-+-- SPDX-License-Identifier: GPL-2.0-or-later
-+
-+with HW.GFX.GMA;
-+with HW.GFX.GMA.Display_Probing;
-+
-+use HW.GFX.GMA;
-+use HW.GFX.GMA.Display_Probing;
-+
-+private package GMA.Mainboard is
-+
-+   ports : constant Port_List :=
-+     (DP2, -- dock DP
-+      Analog, -- mainboard VGA
-+      LVDS,
-+      others => Disabled);
-+
-+end GMA.Mainboard;
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
-new file mode 100644
-index 0000000000..b50f8da0b5
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/gpio.c
-@@ -0,0 +1,138 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <southbridge/intel/common/gpio.h>
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
-+	.gpio0  = GPIO_MODE_NATIVE,
-+	.gpio1  = GPIO_MODE_GPIO,
-+	.gpio2  = GPIO_MODE_GPIO,
-+	.gpio3  = GPIO_MODE_GPIO,
-+	.gpio4  = GPIO_MODE_GPIO,
-+	.gpio5  = GPIO_MODE_GPIO,
-+	.gpio6  = GPIO_MODE_GPIO,
-+	.gpio7  = GPIO_MODE_GPIO,
-+	.gpio8  = GPIO_MODE_GPIO,
-+	.gpio9  = GPIO_MODE_NATIVE,
-+	.gpio10 = GPIO_MODE_NATIVE,
-+	.gpio11 = GPIO_MODE_NATIVE,
-+	.gpio12 = GPIO_MODE_NATIVE,
-+	.gpio13 = GPIO_MODE_GPIO,
-+	.gpio14 = GPIO_MODE_GPIO,
-+	.gpio15 = GPIO_MODE_NATIVE,
-+	.gpio16 = GPIO_MODE_NATIVE,
-+	.gpio17 = GPIO_MODE_GPIO,
-+	.gpio18 = GPIO_MODE_GPIO,
-+	.gpio19 = GPIO_MODE_GPIO,
-+	.gpio20 = GPIO_MODE_GPIO,
-+	.gpio21 = GPIO_MODE_GPIO,
-+	.gpio22 = GPIO_MODE_GPIO,
-+	.gpio23 = GPIO_MODE_NATIVE,
-+	.gpio24 = GPIO_MODE_GPIO,
-+	.gpio25 = GPIO_MODE_NATIVE,
-+	.gpio26 = GPIO_MODE_NATIVE,
-+	.gpio27 = GPIO_MODE_GPIO,
-+	.gpio28 = GPIO_MODE_GPIO,
-+	.gpio29 = GPIO_MODE_NATIVE,
-+	.gpio30 = GPIO_MODE_NATIVE,
-+	.gpio31 = GPIO_MODE_NATIVE,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
-+	.gpio1  = GPIO_DIR_INPUT,
-+	.gpio2  = GPIO_DIR_INPUT,
-+	.gpio3  = GPIO_DIR_INPUT,
-+	.gpio4  = GPIO_DIR_INPUT,
-+	.gpio5  = GPIO_DIR_INPUT,
-+	.gpio6  = GPIO_DIR_INPUT,
-+	.gpio7  = GPIO_DIR_INPUT,
-+	.gpio8  = GPIO_DIR_INPUT,
-+	.gpio13 = GPIO_DIR_INPUT,
-+	.gpio14 = GPIO_DIR_INPUT,
-+	.gpio17 = GPIO_DIR_INPUT,
-+	.gpio18 = GPIO_DIR_INPUT,
-+	.gpio19 = GPIO_DIR_INPUT,
-+	.gpio20 = GPIO_DIR_INPUT,
-+	.gpio21 = GPIO_DIR_INPUT,
-+	.gpio22 = GPIO_DIR_INPUT,
-+	.gpio24 = GPIO_DIR_INPUT,
-+	.gpio27 = GPIO_DIR_INPUT,
-+	.gpio28 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_level = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_blink = {
-+};
-+
-+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
-+	.gpio1  = GPIO_INVERT,
-+	.gpio7  = GPIO_INVERT,
-+	.gpio8  = GPIO_INVERT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
-+	.gpio32 = GPIO_MODE_NATIVE,
-+	.gpio33 = GPIO_MODE_GPIO,
-+	.gpio34 = GPIO_MODE_GPIO,
-+	.gpio35 = GPIO_MODE_NATIVE,
-+	.gpio36 = GPIO_MODE_GPIO,
-+	.gpio37 = GPIO_MODE_GPIO,
-+	.gpio38 = GPIO_MODE_GPIO,
-+	.gpio39 = GPIO_MODE_GPIO,
-+	.gpio40 = GPIO_MODE_NATIVE,
-+	.gpio41 = GPIO_MODE_NATIVE,
-+	.gpio42 = GPIO_MODE_NATIVE,
-+	.gpio43 = GPIO_MODE_NATIVE,
-+	.gpio44 = GPIO_MODE_NATIVE,
-+	.gpio45 = GPIO_MODE_NATIVE,
-+	.gpio46 = GPIO_MODE_NATIVE,
-+	.gpio47 = GPIO_MODE_NATIVE,
-+	.gpio48 = GPIO_MODE_GPIO,
-+	.gpio49 = GPIO_MODE_GPIO,
-+	.gpio50 = GPIO_MODE_NATIVE,
-+	.gpio51 = GPIO_MODE_NATIVE,
-+	.gpio52 = GPIO_MODE_GPIO,
-+	.gpio53 = GPIO_MODE_GPIO,
-+	.gpio54 = GPIO_MODE_NATIVE,
-+	.gpio55 = GPIO_MODE_NATIVE,
-+	.gpio56 = GPIO_MODE_GPIO,
-+	.gpio57 = GPIO_MODE_GPIO,
-+	.gpio58 = GPIO_MODE_NATIVE,
-+	.gpio59 = GPIO_MODE_NATIVE,
-+	.gpio60 = GPIO_MODE_GPIO,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
-+	.gpio33 = GPIO_DIR_INPUT,
-+	.gpio34 = GPIO_DIR_INPUT,
-+	.gpio36 = GPIO_DIR_INPUT,
-+	.gpio37 = GPIO_DIR_INPUT,
-+	.gpio38 = GPIO_DIR_INPUT,
-+	.gpio39 = GPIO_DIR_INPUT,
-+	.gpio48 = GPIO_DIR_INPUT,
-+	.gpio49 = GPIO_DIR_INPUT,
-+	.gpio52 = GPIO_DIR_INPUT,
-+	.gpio53 = GPIO_DIR_INPUT,
-+	.gpio56 = GPIO_DIR_INPUT,
-+	.gpio57 = GPIO_DIR_INPUT,
-+	.gpio60 = GPIO_DIR_INPUT,
-+};
-+
-+static const struct pch_gpio_set2 pch_gpio_set2_level = {
-+};
-+
-+const struct pch_gpio_map mainboard_gpio_map = {
-+	.set1 = {
-+		.mode      = &pch_gpio_set1_mode,
-+		.direction = &pch_gpio_set1_direction,
-+		.level     = &pch_gpio_set1_level,
-+		.blink     = &pch_gpio_set1_blink,
-+		.invert    = &pch_gpio_set1_invert,
-+	},
-+	.set2 = {
-+		.mode      = &pch_gpio_set2_mode,
-+		.direction = &pch_gpio_set2_direction,
-+		.level     = &pch_gpio_set2_level,
-+	},
-+};
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
-new file mode 100644
-index 0000000000..a9948a93dd
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/hda_verb.c
-@@ -0,0 +1,37 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <device/azalia_device.h>
-+
-+const u32 cim_verb_data[] = {
-+	/* coreboot specific header */
-+	0x111d76b2, /* IDT 92HD71B7X */
-+	0x1028024d, /* Subsystem ID */
-+	13,	    /* Number of entries */
-+
-+	/* Pin Widget Verb Table */
-+
-+	AZALIA_PIN_CFG(0, 0x0a, 0x0421101f),
-+	AZALIA_PIN_CFG(0, 0x0b, 0x04a11021),
-+	AZALIA_PIN_CFG(0, 0x0c, 0x40f000f0),
-+	AZALIA_PIN_CFG(0, 0x0d, 0x90170110),
-+	AZALIA_PIN_CFG(0, 0x0e, 0x23a1102e),
-+	AZALIA_PIN_CFG(0, 0x0f, 0x23011050),
-+	AZALIA_PIN_CFG(0, 0x14, 0x40f000f2),
-+	AZALIA_PIN_CFG(0, 0x18, 0x90a601a0),
-+	AZALIA_PIN_CFG(0, 0x19, 0x40f000f4),
-+	AZALIA_PIN_CFG(0, 0x1e, 0x40f000f5),
-+	AZALIA_PIN_CFG(0, 0x1f, 0x40f000f6),
-+	AZALIA_PIN_CFG(0, 0x20, 0x40f000f7),
-+	AZALIA_PIN_CFG(0, 0x27, 0x40f000f0),
-+};
-+
-+const u32 pc_beep_verbs[] = {
-+	0x00170500, /* power up codec */
-+	0x00d70500, /* power up speakers */
-+	0x00d70102, /* select mixer (input 0x2) for speakers */
-+	0x00d70740, /* enable speakers output */
-+	0x02770720, /* enable beep input */
-+	0x01737217, /* unmute beep (mixer's input 0x2), set amp 0dB */
-+	0x00d37000, /* unmute speakers */
-+};
-+AZALIA_ARRAY_SIZES;
-diff --git a/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-new file mode 100644
-index 0000000000..20dfa245fb
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/variants/e4300/overridetree.cb
-@@ -0,0 +1,10 @@
-+## SPDX-License-Identifier: GPL-2.0-or-later
-+
-+chip northbridge/intel/gm45
-+	device domain 0 on
-+		subsystemid 0x1028 0x024d inherit
-+		chip southbridge/intel/i82801ix
-+			device pci 1c.2 off end # PCIe Port #3
-+		end
-+	end
-+end
--- 
-2.39.5
-

config/coreboot/default/patches/0050-mb-dell-Add-S3-SMI-handler-for-Dell-Latitudes.patch

@@ -1,70 +0,0 @@
-From 5e8b899654c31fe771e4b1e96c74c93d4509c3b2 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Fri, 3 May 2024 16:31:12 -0600
-Subject: [PATCH 50/51] mb/dell: Add S3 SMI handler for Dell Latitudes
-
-Integrate the previously added mec5035_smi_sleep() function into
-mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
-The E6400 does not require the EC command to sucessfully suspend and
-resume from S3, though sending it does enable the breathing effect on
-the power LED while in S3. Without it, all LEDs turn off during S3.
-
-Change-Id: Ic0d887f75be13c3fb9f6df62153ac458895e0283
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/mainboard/dell/e7240/smihandler.c            | 9 +++++++++
- src/mainboard/dell/gm45_latitude/smihandler.c    | 9 +++++++++
- src/mainboard/dell/snb_ivb_latitude/smihandler.c | 9 +++++++++
- 3 files changed, 27 insertions(+)
- create mode 100644 src/mainboard/dell/e7240/smihandler.c
- create mode 100644 src/mainboard/dell/gm45_latitude/smihandler.c
- create mode 100644 src/mainboard/dell/snb_ivb_latitude/smihandler.c
-
-diff --git a/src/mainboard/dell/e7240/smihandler.c b/src/mainboard/dell/e7240/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
---- /dev/null
-+++ b/src/mainboard/dell/e7240/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_smi_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/gm45_latitude/smihandler.c b/src/mainboard/dell/gm45_latitude/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
---- /dev/null
-+++ b/src/mainboard/dell/gm45_latitude/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_smi_sleep(slp_typ);
-+}
-diff --git a/src/mainboard/dell/snb_ivb_latitude/smihandler.c b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
-new file mode 100644
-index 0000000000..00e55b51db
---- /dev/null
-+++ b/src/mainboard/dell/snb_ivb_latitude/smihandler.c
-@@ -0,0 +1,9 @@
-+/* SPDX-License-Identifier: GPL-2.0-only */
-+
-+#include <cpu/x86/smm.h>
-+#include <ec/dell/mec5035/mec5035.h>
-+
-+void mainboard_smi_sleep(u8 slp_typ)
-+{
-+	mec5035_smi_sleep(slp_typ);
-+}
--- 
-2.39.5
-

config/coreboot/default/patches/0051-ec-dell-mec5035-Route-power-button-event-to-host.patch

@@ -1,92 +0,0 @@
-From 1a342c20b8705bbea02d27a73e383ee2808f2558 Mon Sep 17 00:00:00 2001
-From: Nicholas Chin <nic.c3.14@gmail.com>
-Date: Tue, 18 Jun 2024 21:31:08 -0600
-Subject: [PATCH 51/51] ec/dell/mec5035: Route power button event to host
-
-If command 0x3e with an argument of 1 isn't sent to the EC, pressing the
-power button results in the EC powering off the system without letting
-the OS cleanly shutting itself down. This command and argument tells the
-EC to route power button events to the host so that it can determine
-what to do.
-
-The EC command was identified from the ec/google/wilco code, which is
-used for Dell's Latitude Chromebooks. According to the EC_GOOGLE_WILCO
-Kconfig help text, those ECs run a modified version of Dell's typical
-Latitude EC firmware, so it is likely that the two firmware
-implementations use similar commands. Examining LPC traffic between the
-host and the EC on the Latitude E6400 did reveal that the same command
-was being sent by the vendor firmware to the EC, but this does not
-confirm that it has the same meaning as the command from the Wilco code.
-Sending the command using inb/outb calls in a userspace C program while
-running coreboot without this patch did allow subsequent power button
-events to be handled by the host, confirming that the command was indeed
-the same.
-
-Change-Id: I5ded315270c0e1efbbc90cfa9d9d894b872e99a2
-Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
----
- src/ec/dell/mec5035/mec5035.c | 8 ++++++++
- src/ec/dell/mec5035/mec5035.h | 7 +++++++
- 2 files changed, 15 insertions(+)
-
-diff --git a/src/ec/dell/mec5035/mec5035.c b/src/ec/dell/mec5035/mec5035.c
-index 85c2ab0140..bdae929a27 100644
---- a/src/ec/dell/mec5035/mec5035.c
-+++ b/src/ec/dell/mec5035/mec5035.c
-@@ -94,6 +94,13 @@ void mec5035_control_radio(enum ec_radio_dev dev, enum ec_radio_state state)
- 	ec_command(CMD_RADIO_CTRL);
- }
- 
-+void mec5035_power_button_route(enum ec_power_button_route target)
-+{
-+	u8 buf = (u8)target;
-+	write_mailbox_regs(&buf, 2, 1);
-+	ec_command(CMD_POWER_BUTTON_TO_HOST);
-+}
-+
- void mec5035_change_wake(u8 source, enum ec_wake_change change)
- {
- 	u8 buf[ACPI_WAKEUP_NUM_ARGS] = {change, source, 0, 0x40};
-@@ -121,6 +128,7 @@ static void mec5035_init(struct device *dev)
- 	/* Unconditionally use this argument for now as this setting
- 	   is probably the most sensible default out of the 3 choices. */
- 	mec5035_mouse_touchpad(TP_PS2_MOUSE);
-+	mec5035_power_button_route(HOST);
- 
- 	pc_keyboard_init(NO_AUX_DEVICE);
- 
-diff --git a/src/ec/dell/mec5035/mec5035.h b/src/ec/dell/mec5035/mec5035.h
-index 8d4fded28b..51422598c4 100644
---- a/src/ec/dell/mec5035/mec5035.h
-+++ b/src/ec/dell/mec5035/mec5035.h
-@@ -11,6 +11,7 @@
- enum mec5035_cmd {
- 	CMD_MOUSE_TP = 0x1a,
- 	CMD_RADIO_CTRL = 0x2b,
-+	CMD_POWER_BUTTON_TO_HOST = 0x3e,
- 	CMD_ACPI_WAKEUP_CHANGE = 0x4a,
- 	CMD_SLEEP_ENABLE = 0x64,
- 	CMD_CPU_OK = 0xc2,
-@@ -36,6 +37,11 @@ enum ec_radio_state {
- 	RADIO_ON
- };
- 
-+enum ec_power_button_route {
-+	EC = 0,
-+	HOST
-+};
-+
- #define ACPI_WAKEUP_NUM_ARGS 4
- enum ec_wake_change {
- 	WAKE_OFF = 0,
-@@ -55,6 +61,7 @@ u8 mec5035_mouse_touchpad(enum ec_mouse_setting setting);
- void mec5035_cpu_ok(void);
- void mec5035_early_init(void);
- void mec5035_control_radio(enum ec_radio_dev device, enum ec_radio_state state);
-+void mec5035_power_button_route(enum ec_power_button_route target);
- void mec5035_change_wake(u8 source, enum ec_wake_change change);
- void mec5035_sleep_enable(void);
- 
--- 
-2.39.5
-

config/coreboot/default/target.cfg

@@ -1,2 +1,2 @@
 tree="default"
-rev="97bc693abc482139774a656212935387d43df8e2"
+rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"

config/coreboot/dell/patches/0001-util-ifdtool-add-nuke-flag-all-0xFF-on-region.patch

@@ -1,7 +1,7 @@
-From 851043846f589e718a69009a6b157b4ff5315471 Mon Sep 17 00:00:00 2001
+From 4fbd327df271d613d4a56a36eafd88d9d642ec6b Mon Sep 17 00:00:00 2001
-From: Leah Rowe <info@minifree.org>
+From: Leah Rowe <leah@libreboot.org>
 Date: Sun, 19 Feb 2023 18:21:43 +0000
-Subject: [PATCH 6/8] util/ifdtool: add --nuke flag (all 0xFF on region)
+Subject: [PATCH 1/9] util/ifdtool: add --nuke flag (all 0xFF on region)
 
 When this option is used, the region's contents are overwritten
 with all ones (0xFF).
@@ -16,14 +16,14 @@ Rebased since the last revision update in lbmk.
 
 Signed-off-by: Leah Rowe <leah@libreboot.org>
 ---
- util/ifdtool/ifdtool.c | 114 ++++++++++++++++++++++++++++++-----------
+ util/ifdtool/ifdtool.c | 112 +++++++++++++++++++++++++++++------------
- 1 file changed, 83 insertions(+), 31 deletions(-)
+ 1 file changed, 81 insertions(+), 31 deletions(-)
 
 diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
-index ace05e2265..ba292fd142 100644
+index 191b3216de..38132b4a28 100644
 --- a/util/ifdtool/ifdtool.c
 +++ b/util/ifdtool/ifdtool.c
-@@ -2230,6 +2230,7 @@ static void print_usage(const char *name)
+@@ -1942,6 +1942,7 @@ static void print_usage(const char *name)
  	       "                                         tgl    - Tiger Lake\n"
  	       "                                         wbg    - Wellsburg\n"
  	       "   -S | --setpchstrap                    Write a PCH strap\n"
@@ -31,7 +31,7 @@ index ace05e2265..ba292fd142 100644
  	       "   -V | --newvalue                       The new value to write into PCH strap specified by -S\n"
  	       "   -v | --version:                       print the version\n"
  	       "   -h | --help:                          print this help\n\n"
-@@ -2238,6 +2239,60 @@ static void print_usage(const char *name)
+@@ -1950,6 +1951,60 @@ static void print_usage(const char *name)
  	       "\n");
  }
  
@@ -92,15 +92,15 @@ index ace05e2265..ba292fd142 100644
  int main(int argc, char *argv[])
  {
  	int opt, option_index = 0;
-@@ -2245,6 +2300,7 @@ int main(int argc, char *argv[])
+@@ -1957,6 +2012,7 @@ int main(int argc, char *argv[])
  	int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
  	int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
  	int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
 +	int mode_nuke = 0;
- 	int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
+ 	int mode_gpr0_disable = 0;
  	char *region_type_string = NULL, *region_fname = NULL;
  	const char *layout_fname = NULL;
-@@ -2280,6 +2336,7 @@ int main(int argc, char *argv[])
+@@ -1990,6 +2046,7 @@ int main(int argc, char *argv[])
  		{"validate", 0, NULL, 't'},
  		{"setpchstrap", 1, NULL, 'S'},
  		{"newvalue", 1, NULL, 'V'},
@@ -108,7 +108,7 @@ index ace05e2265..ba292fd142 100644
  		{0, 0, 0, 0}
  	};
  
-@@ -2329,35 +2386,8 @@ int main(int argc, char *argv[])
+@@ -2039,35 +2096,8 @@ int main(int argc, char *argv[])
  			region_fname++;
  			// Descriptor, BIOS, ME, GbE, Platform
  			// valid type?
@@ -141,12 +141,12 @@ index ace05e2265..ba292fd142 100644
 -			else if (!strcasecmp("PTT", region_type_string))
 -				region_type = 15;
 -			if (region_type == -1) {
-+			if ((region_type =
++                       if ((region_type =
-+			    get_region_type_string(region_type_string)) == -1) {
++                           get_region_type_string(region_type_string)) == -1) {
  				fprintf(stderr, "No such region type: '%s'\n\n",
  					region_type_string);
  				fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
-@@ -2534,6 +2564,22 @@ int main(int argc, char *argv[])
+@@ -2236,6 +2266,22 @@ int main(int argc, char *argv[])
  		case 't':
  			mode_validate = 1;
  			break;
@@ -169,37 +169,35 @@ index ace05e2265..ba292fd142 100644
  		case 'v':
  			print_version();
  			exit(EXIT_SUCCESS);
-@@ -2553,7 +2599,8 @@ int main(int argc, char *argv[])
+@@ -2252,7 +2298,7 @@ int main(int argc, char *argv[])
  	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
  			mode_setstrap + mode_newlayout + (mode_spifreq | mode_em100 |
  			mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
--			(mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) > 1) {
+-			mode_gpr0_disable) > 1) {
-+			(mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
++			mode_gpr0_disable + mode_nuke) > 1) {
-+			mode_nuke) > 1) {
  		fprintf(stderr, "You may not specify more than one mode.\n\n");
  		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
  		exit(EXIT_FAILURE);
-@@ -2562,7 +2609,8 @@ int main(int argc, char *argv[])
+@@ -2261,7 +2307,7 @@ int main(int argc, char *argv[])
  	if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
  			mode_setstrap + mode_newlayout + mode_spifreq + mode_em100 +
  			mode_locked + mode_unlocked + mode_density + mode_altmedisable +
--			mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status) == 0) {
+-			mode_validate + mode_gpr0_disable) == 0) {
-+			mode_validate + (mode_gpr0_disable | mode_gpr0_enable) + mode_gpr0_status +
++			mode_validate + mode_gpr0_disable + mode_nuke) == 0) {
-+			mode_nuke) == 0) {
  		fprintf(stderr, "You need to specify a mode.\n\n");
  		fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
  		exit(EXIT_FAILURE);
-@@ -2675,6 +2723,10 @@ int main(int argc, char *argv[])
+@@ -2368,6 +2414,10 @@ int main(int argc, char *argv[])
  		write_image(new_filename, image, size);
  	}
  
-+	if (mode_nuke) {
++       if (mode_nuke) {
-+		nuke(new_filename, image, size, region_type);
++               nuke(new_filename, image, size, region_type);
-+	}
++       }
 +
  	if (mode_altmedisable) {
  		struct fpsba *fpsba = find_fpsba(image, size);
  		struct fmsba *fmsba = find_fmsba(image, size);
 -- 
-2.39.5
+2.39.2
 

config/coreboot/dell/patches/0002-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch

@@ -0,0 +1,47 @@
+From 362e86f89b3980699e7e794df9b98018397fe2d8 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Wed, 1 Dec 2021 02:53:00 +0000
+Subject: [PATCH 2/9] fix speedstep on x200/t400: Revert
+ "cpu/intel/model_1067x: enable PECI"
+
+This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
+
+Enabling PECI without microcode updates loaded causes the CPUID feature set
+to become corrupted. And one consequence is broken SpeedStep. At least, that's
+my understanding looking at Intel Errata. This revert is not a fix, because
+upstream is correct (upstream assumes microcode updates). We will simply
+maintain this revert patch in Libreboot, from now on.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
+ 1 file changed, 9 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 315e7c36fc..1423fd72bc 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -141,8 +141,6 @@ static void configure_emttm_tables(void)
+ 	wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
+ }
+ 
+-#define IA32_PECI_CTL		0x5a0
+-
+ static void configure_misc(const int eist, const int tm2, const int emttm)
+ {
+ 	msr_t msr;
+@@ -185,13 +183,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
+ 		msr.lo |= (1 << 20);	/* Lock Enhanced SpeedStep Enable */
+ 		wrmsr(IA32_MISC_ENABLE, msr);
+ 	}
+-
+-	/* Enable PECI
+-	   WARNING: due to Erratum AW67 described in Intel document #318733
+-	   the microcode must be updated before this MSR is written to. */
+-	msr = rdmsr(IA32_PECI_CTL);
+-	msr.lo |= 1;
+-	wrmsr(IA32_PECI_CTL, msr);
+ }
+ 
+ #define PIC_SENS_CFG	0x1aa
+-- 
+2.39.2
+

config/coreboot/dell/patches/0003-GM45-type-CPUs-don-t-enable-alternative-SMRR.patch

@@ -0,0 +1,173 @@
+From 883455573f07551eaf2b12ab80bedcd2b4904a17 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Mon, 17 Apr 2023 15:49:57 +0100
+Subject: [PATCH 3/9] GM45-type CPUs: don't enable alternative SMRR
+
+This reverts the changes in coreboot revision:
+df7aecd92643d207feaf7fd840f8835097346644
+
+While this fix is *technically correct*, the one in
+coreboot, it breaks rebooting as tested on several
+GM45 ThinkPads e.g. X200, T400, when microcode
+updates are not applied.
+
+Since November 2022, Libreboot includes microcode
+updates by default, but it tells users how to remove
+it from the ROM (with cbfstool) if they wish.
+
+Well, with Libreboot 20221214, 20230319 and 20230413,
+mitigations present in Libreboot 20220710 (which did
+not have microcode updates) do not exist.
+
+This patch, along with the other patch to remove PECI
+support (which breaks speedstep when microcode updates
+are not applied) have now been re-added to Libreboot.
+
+It is still best to use microcode updates by default.
+These patches in coreboot are not critically urgent,
+and you can use the machines with or without them,
+regardless of ucode.
+
+I'll probably re-write this and the other patch at
+some point, applying the change conditionally upon
+whether or not microcode is applied.
+
+Pragmatism is a good thing. I recommend it.
+---
+ src/cpu/intel/model_1067x/model_1067x_init.c |  4 +++
+ src/cpu/intel/model_1067x/mp_init.c          | 26 --------------------
+ src/cpu/intel/model_106cx/model_106cx_init.c |  4 +++
+ src/cpu/intel/model_6ex/model_6ex_init.c     |  4 +++
+ src/cpu/intel/model_6fx/model_6fx_init.c     |  4 +++
+ 5 files changed, 16 insertions(+), 26 deletions(-)
+
+diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
+index 1423fd72bc..d1f98ca43a 100644
+--- a/src/cpu/intel/model_1067x/model_1067x_init.c
++++ b/src/cpu/intel/model_1067x/model_1067x_init.c
+@@ -8,6 +8,7 @@
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
+ #include <cpu/intel/smm_reloc.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define MSR_BBL_CR_CTL3		0x11e
+ 
+@@ -234,6 +235,9 @@ static void model_1067x_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states(quad);
+ 
+diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
+index bc53214310..72f40f6762 100644
+--- a/src/cpu/intel/model_1067x/mp_init.c
++++ b/src/cpu/intel/model_1067x/mp_init.c
+@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
+ 	smm_initialize();
+ }
+ 
+-#define SMRR_SUPPORTED (1 << 11)
+-
+ static void per_cpu_smm_trigger(void)
+ {
+-	msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
+-	if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
+-		set_feature_ctrl_vmx();
+-		msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
+-		/* We don't care if the lock is already setting
+-		   as our smm relocation handler is able to handle
+-		   setups where SMRR is not enabled here. */
+-		if (ia32_ft_ctrl.lo & (1 << 0)) {
+-			/* IA32_FEATURE_CONTROL locked. If we set it again we
+-			   get an illegal instruction. */
+-			printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
+-			printk(BIOS_DEBUG, "SMRR status: %senabled\n",
+-			       ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
+-		} else {
+-			if (!CONFIG(SET_IA32_FC_LOCK_BIT))
+-				printk(BIOS_INFO,
+-				       "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
+-			ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
+-			wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
+-		}
+-	} else {
+-		set_vmx_and_lock();
+-	}
+-
+ 	/* Relocate the SMM handler. */
+ 	smm_relocate();
+ }
+diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
+index 05f5f327cc..0450c2ad83 100644
+--- a/src/cpu/intel/model_106cx/model_106cx_init.c
++++ b/src/cpu/intel/model_106cx/model_106cx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -66,6 +67,9 @@ static void model_106cx_init(struct device *cpu)
+ 	fill_processor_name(processor_name);
+ 	printk(BIOS_INFO, "CPU: %s.\n", processor_name);
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
+index 5bd1c32815..f3bb08cde3 100644
+--- a/src/cpu/intel/model_6ex/model_6ex_init.c
++++ b/src/cpu/intel/model_6ex/model_6ex_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -105,6 +106,9 @@ static void model_6ex_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
+index 535fb8fae7..f7b05facd2 100644
+--- a/src/cpu/intel/model_6fx/model_6fx_init.c
++++ b/src/cpu/intel/model_6fx/model_6fx_init.c
+@@ -7,6 +7,7 @@
+ #include <cpu/intel/speedstep.h>
+ #include <cpu/x86/cache.h>
+ #include <cpu/x86/name.h>
++#include <cpu/intel/common/common.h>
+ 
+ #define HIGHEST_CLEVEL		3
+ static void configure_c_states(void)
+@@ -118,6 +119,9 @@ static void model_6fx_init(struct device *cpu)
+ 	/* Setup Page Attribute Tables (PAT) */
+ 	// TODO set up PAT
+ 
++	/* Set virtualization based on Kconfig option */
++	set_vmx_and_lock();
++
+ 	/* Configure C States */
+ 	configure_c_states();
+ 
+-- 
+2.39.2
+

config/coreboot/dell/patches/0004-mb-dell-e6400-Enable-01.0-device-in-devicetree-for-d.patch

@@ -0,0 +1,28 @@
+From 458fe39e9cd2536cfa8671427e6f557396143339 Mon Sep 17 00:00:00 2001
+From: Nicholas Chin <nic.c3.14@gmail.com>
+Date: Sat, 6 May 2023 15:53:41 -0600
+Subject: [PATCH 4/9] mb/dell/e6400: Enable 01.0 device in devicetree for dGPU
+ models
+
+Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
+Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
+---
+ src/mainboard/dell/e6400/devicetree.cb | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/dell/e6400/devicetree.cb b/src/mainboard/dell/e6400/devicetree.cb
+index bb954cbd7b..e9f3915d17 100644
+--- a/src/mainboard/dell/e6400/devicetree.cb
++++ b/src/mainboard/dell/e6400/devicetree.cb
+@@ -19,7 +19,7 @@ chip northbridge/intel/gm45
+ 		ops gm45_pci_domain_ops
+ 
+ 		device pci 00.0 on end # host bridge
+-		device pci 01.0 off end
++		device pci 01.0 on end
+ 		device pci 02.0 on end # VGA
+ 		device pci 02.1 on end # Display
+ 		device pci 03.0 on end # ME
+-- 
+2.39.2
+

config/coreboot/dell/patches/0005-Remove-warning-for-coreboot-images-built-without-a-p.patch

@@ -1,7 +1,7 @@
-From fa6ac5b7f134b98a4f68f0f6b8bdeb6c7b6871ab Mon Sep 17 00:00:00 2001
+From de4eeaf6d44cb05c60c0b0d54b43cdb88686b998 Mon Sep 17 00:00:00 2001
 From: Nicholas Chin <nic.c3.14@gmail.com>
 Date: Fri, 12 May 2023 19:55:15 -0600
-Subject: [PATCH 7/8] Remove warning for coreboot images built without a
+Subject: [PATCH 5/9] Remove warning for coreboot images built without a
  payload
 
 I added this in upstream to prevent people from accidentally flashing
@@ -13,10 +13,10 @@ up. This has caused confusion and concern so just patch it out.
  1 file changed, 1 insertion(+), 12 deletions(-)
 
 diff --git a/payloads/Makefile.mk b/payloads/Makefile.mk
-index 5f988dac1b..516133880f 100644
+index a2336aa876..4f1692a873 100644
 --- a/payloads/Makefile.mk
 +++ b/payloads/Makefile.mk
-@@ -50,16 +50,5 @@ distclean-payloads:
+@@ -49,16 +49,5 @@ distclean-payloads:
  print-repo-info-payloads:
  	-$(foreach payload, $(PAYLOADS_LIST), $(MAKE) -C $(payload) print-repo-info 2>/dev/null; )
  
@@ -35,5 +35,5 @@ index 5f988dac1b..516133880f 100644
 -.PHONY: clean-payloads distclean-payloads print-repo-info-payloads warn_no_payload
 +.PHONY: clean-payloads distclean-payloads print-repo-info-payloads
 -- 
-2.39.5
+2.39.2
 

config/coreboot/dell/patches/0006-don-t-use-github-for-the-acpica-download.patch

@@ -0,0 +1,39 @@
+From 261454e47783b973b088e9dbea47bda02758dcb4 Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 22 Oct 2023 15:02:25 +0100
+Subject: [PATCH 6/9] don't use github for the acpica download
+
+i have the tarball from a previous download, and i placed
+it on libreboot rsync, which then got mirrored to princeton.
+
+today, github's ssl cert was b0rking the hell out and i really
+really wanted to finish a build, and didn't want to wait for
+github to fix their httpd.
+
+so i'm now hosting this specific acpica tarball on rsync.
+
+this patch makes that URL be used, instead of the github one.
+
+that's the 2nd time i've had to patch coreboot's acpica download!
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 23a5caf2bb..36565a906c 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -72,7 +72,7 @@ MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+ MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+ GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+ BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
+-IASL_BASE_URL="https://github.com/acpica/acpica/archive/refs/tags"
++IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+ CLANG_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/dell/patches/0007-use-mirrorservice.org-for-gcc-downloads.patch

@@ -0,0 +1,36 @@
+From 622daa7c46de01530de60a7be32c8b9e48b356fd Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Sun, 5 Nov 2023 22:57:08 +0000
+Subject: [PATCH 7/9] use mirrorservice.org for gcc downloads
+
+the gnu.org 302 redirect often fails
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ util/crossgcc/buildgcc | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc
+index 36565a906c..4d4ca06113 100755
+--- a/util/crossgcc/buildgcc
++++ b/util/crossgcc/buildgcc
+@@ -67,11 +67,11 @@ NASM_ARCHIVE="nasm-${NASM_VERSION}.tar.bz2"
+ # to the jenkins build as well, or the builder won't download it.
+ 
+ # GCC toolchain archive locations
+-GMP_BASE_URL="https://ftpmirror.gnu.org/gmp"
+-MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr"
+-MPC_BASE_URL="https://ftpmirror.gnu.org/mpc"
+-GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}"
+-BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils"
++GMP_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gmp"
++MPFR_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpfr"
++MPC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/mpc"
++GCC_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}"
++BINUTILS_BASE_URL="https://www.mirrorservice.org/sites/ftp.gnu.org/gnu/binutils"
+ IASL_BASE_URL="https://www.mirrorservice.org/sites/libreboot.org/release/misc/acpica"
+ # CLANG toolchain archive locations
+ LLVM_BASE_URL="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERSION}"
+-- 
+2.39.2
+

config/coreboot/dell/patches/0008-nb-intel-gm45-Make-DDR2-raminit-work.patch

@@ -1,7 +1,7 @@
-From c6181fe0c8b58cb5a4523d5763fc5fcdf61b3f10 Mon Sep 17 00:00:00 2001
+From f26df5dff7be4b0c9d8dced1cf6ed07472a174c7 Mon Sep 17 00:00:00 2001
 From: Angel Pons <th3fanbus@gmail.com>
 Date: Mon, 10 May 2021 22:40:59 +0200
-Subject: [PATCH 27/51] nb/intel/gm45: Make DDR2 raminit work
+Subject: [PATCH 8/9] nb/intel/gm45: Make DDR2 raminit work
 
 List of changes:
  - Update some timing and ODT values
@@ -20,10 +20,10 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
  3 files changed, 106 insertions(+), 13 deletions(-)
 
 diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
-index 5d9ac56606..338260ea7a 100644
+index d929533d92..997f8a0e5a 100644
 --- a/src/northbridge/intel/gm45/gm45.h
 +++ b/src/northbridge/intel/gm45/gm45.h
-@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
+@@ -419,7 +419,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
  int raminit_read_vco_index(void);
  u32 raminit_get_rank_addr(unsigned int channel, unsigned int rank);
  
@@ -219,5 +219,5 @@ index aef863f05a..b74765fd9c 100644
 +	mchbar_clrsetbits32(0x4d0, 0x3f << 20, magic_comp[1] << 20);
  }
 -- 
-2.39.5
+2.39.2
 

config/coreboot/dell/patches/0009-dell-e6400-crank-up-vram-to-256MB-max.patch

@@ -0,0 +1,23 @@
+From f318da0563ecb2386ac368e04bad88a8aacbc83d Mon Sep 17 00:00:00 2001
+From: Leah Rowe <leah@libreboot.org>
+Date: Wed, 1 Nov 2023 16:33:11 +0000
+Subject: [PATCH 9/9] dell/e6400: crank up vram to 256MB (max)
+
+Signed-off-by: Leah Rowe <leah@libreboot.org>
+---
+ src/mainboard/dell/e6400/cmos.default | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+diff --git a/src/mainboard/dell/e6400/cmos.default b/src/mainboard/dell/e6400/cmos.default
+index eeb6f47364..25dfa38cb5 100644
+--- a/src/mainboard/dell/e6400/cmos.default
++++ b/src/mainboard/dell/e6400/cmos.default
+@@ -2,4 +2,4 @@ boot_option=Fallback
+ debug_level=Debug
+ power_on_after_fail=Disable
+ sata_mode=AHCI
+-gfx_uma_size=32M
++gfx_uma_size=256M
+-- 
+2.39.2
+

config/coreboot/dell/target.cfg

@@ -0,0 +1,4 @@
+tree="dell"
+tree_depend="default"
+xtree="default"
+rev="b6cbfa977f63d57d5d6b9e9f7c1cef30162f575a"

config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_corebootfb

@@ -1,815 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-CONFIG_OPTION_BACKEND_NONE=y
-# CONFIG_USE_OPTION_TABLE is not set
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_3050"
-CONFIG_VGA_BIOS_ID="8086,0406"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=512
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0xEEE000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
-CONFIG_MAX_CPUS=16
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_OVERRIDE_DEVICETREE=""
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-CONFIG_PCIEXP_L1_SUB_STATE=y
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-CONFIG_USE_PM_ACPI_TIMER=y
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_3050=y
-# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_DCACHE_RAM_BASE=0xfef00000
-CONFIG_DCACHE_RAM_SIZE=0x40000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_USE_LEGACY_8254_TIMER=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
-CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
-# CONFIG_DEBUG_SMI is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
-CONFIG_TTYS0_BAUD=115200
-CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
-CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
-CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd"
-CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x200000
-CONFIG_SMM_MODULE_STACK_SIZE=0x800
-CONFIG_ACPI_BERT_SIZE=0x0
-CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IFD_CHIPSET="sklkbl"
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_MAX_ROOT_PORTS=24
-CONFIG_PCR_BASE_ADDRESS=0xfd000000
-CONFIG_CPU_BCLK_MHZ=100
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
-CONFIG_CPU_XTAL_HZ=24000000
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
-CONFIG_SOC_INTEL_I2C_DEV_MAX=6
-# CONFIG_ENABLE_SATA_TEST_MODE is not set
-CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
-CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
-CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
-CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
-CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_FSP_PUBLISH_MBP_HOB=y
-CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
-CONFIG_MAX_HECI_DEVICES=5
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HAVE_PAM0_REGISTER=y
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
-CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
-CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
-CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
-CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
-CONFIG_SOC_INTEL_KABYLAKE=y
-CONFIG_SKYLAKE_SOC_PCH_H=y
-CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
-CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
-CONFIG_FSP_T_LOCATION=0xfffe0000
-CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
-CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_SOC_INTEL_COMMON=y
-
-#
-# Intel SoC Common Code for IP blocks
-#
-CONFIG_SOC_INTEL_COMMON_BLOCK=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
-CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
-# CONFIG_USE_COREBOOT_MP_INIT is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
-CONFIG_INTEL_CAR_NEM_ENHANCED=y
-# CONFIG_USE_INTEL_FSP_MP_INIT is not set
-CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
-CONFIG_HAVE_HYPERTHREADING=y
-CONFIG_FSP_HYPERTHREADING=y
-# CONFIG_INTEL_KEYLOCKER is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
-CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
-CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME="ME_RW_A"
-CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME="ME_RW_B"
-CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
-CONFIG_SOC_INTEL_CSE_RW_HASH_CBFS_NAME="me_rw.hash"
-CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
-CONFIG_SOC_INTEL_CSE_RW_FILE=""
-CONFIG_SOC_INTEL_CSE_RW_VERSION=""
-CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
-CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
-CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
-CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
-CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
-CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
-CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
-# CONFIG_SOC_INTEL_DISABLE_IGD is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
-CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
-# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
-CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
-CONFIG_SA_ENABLE_DPR=y
-CONFIG_HAVE_CAPID_A_REGISTER=y
-CONFIG_HAVE_BDSM_BGSM_REGISTER=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
-
-#
-# Intel SoC Common PCH Code
-#
-CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
-CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
-CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
-CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
-CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
-CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
-
-#
-# Intel SoC Common coreboot stages and non-IP blocks
-#
-CONFIG_SOC_INTEL_COMMON_BASECODE=y
-CONFIG_SOC_INTEL_COMMON_RESET=y
-CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
-CONFIG_PAVP=y
-# CONFIG_MMA is not set
-CONFIG_SOC_INTEL_COMMON_NHLT=y
-# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_PARALLEL_MP_AP_WORK=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-
-#
-# Southbridge
-#
-# CONFIG_PCIEXP_HOTPLUG is not set
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_SMSC_SCH555x=y
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-CONFIG_UDK_BASE=y
-CONFIG_UDK_2017_BINDING=y
-CONFIG_UDK_2013_VERSION=2013
-CONFIG_UDK_2017_VERSION=2017
-CONFIG_UDK_202005_VERSION=202005
-CONFIG_UDK_202111_VERSION=202111
-CONFIG_UDK_202302_VERSION=202302
-CONFIG_UDK_202305_VERSION=202305
-CONFIG_UDK_VERSION=2017
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_HAVE_FSP_GOP=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_RUN_FSP_GOP is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_NONE=y
-# CONFIG_DEFAULT_SCREEN_ROTATION_90 is not set
-# CONFIG_DEFAULT_SCREEN_ROTATION_180 is not set
-# CONFIG_DEFAULT_SCREEN_ROTATION_270 is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
-# CONFIG_DRIVERS_EFI_FW_INFO is not set
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-CONFIG_MRC_SETTINGS_PROTECT=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_DESIGNWARE=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_FSP_USE_REPO=y
-# CONFIG_DISPLAY_HOBS is not set
-# CONFIG_DISPLAY_UPD_DATA is not set
-# CONFIG_BMP_LOGO is not set
-CONFIG_PLATFORM_USES_FSP2_0=y
-CONFIG_PLATFORM_USES_FSP2_X86_32=y
-CONFIG_HAVE_INTEL_FSP_REPO=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_FSP_S_CBFS="fsps.bin"
-CONFIG_FSP_M_CBFS="fspm.bin"
-CONFIG_FSP_FULL_FD=y
-CONFIG_FSP_T_RESERVED_SIZE=0x0
-CONFIG_FSP_M_XIP=y
-CONFIG_HAVE_FSP_LOGO_SUPPORT=y
-CONFIG_FSP_COMPRESS_FSP_S_LZ4=y
-CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
-CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
-CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
-CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
-# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
-# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Skylake"
-CONFIG_GFX_GMA_PCH="Sunrise_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-CONFIG_USE_PC_CMOS_ALTCENTURY=y
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_USB_ACPI=y
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
-# end of Memory initialization
-
-# CONFIG_STM is not set
-# CONFIG_INTEL_CBNT_SUPPORT is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_CUSTOM_MADT=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_ACPI_LPIT=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_ACPI_S1_NOT_SUPPORTED=y
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_ACPI_NHLT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
-# CONFIG_DISPLAY_FSP_HEADER is not set
-# CONFIG_VERIFY_HOBS is not set
-# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
-CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
-# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-CONFIG_HAVE_DEBUG_GPIO=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_GENERIC_GPIO_LIB=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/dell3050micro_fsp_16mb/config/libgfxinit_txtmode

@@ -1,808 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-CONFIG_OPTION_BACKEND_NONE=y
-# CONFIG_USE_OPTION_TABLE is not set
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_BOARD_SPECIFIC_OPTIONS=y
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 3050 Micro"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_3050"
-CONFIG_VGA_BIOS_ID="8086,0406"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=512
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0xEEE000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_MAX_CPUS=16
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_OVERRIDE_DEVICETREE=""
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-CONFIG_PCIEXP_L1_SUB_STATE=y
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
-# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3050 Micro"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-CONFIG_USE_PM_ACPI_TIMER=y
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_3050=y
-# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_DCACHE_RAM_BASE=0xfef00000
-CONFIG_DCACHE_RAM_SIZE=0x40000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x4000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_USE_LEGACY_8254_TIMER=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
-CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
-CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
-# CONFIG_DEBUG_SMI is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_ENABLE is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-# CONFIG_SOC_INTEL_CSE_SEND_EOP_EARLY is not set
-CONFIG_TTYS0_BAUD=115200
-CONFIG_POWER_STATE_DEFAULT_ON_AFTER_FAILURE=y
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_16384=y
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=16384
-CONFIG_ROM_SIZE=0x01000000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_OFF_AFTER_FAILURE is not set
-CONFIG_POWER_STATE_ON_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=1
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE="soc/intel/skylake/chipset.cb"
-CONFIG_FSP_M_FILE="$(obj)/Fsp_M.fd"
-CONFIG_FSP_S_FILE="$(obj)/Fsp_S.fd"
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_TSEG_SIZE=0x800000
-CONFIG_SMM_RESERVED_SIZE=0x200000
-CONFIG_SMM_MODULE_STACK_SIZE=0x800
-CONFIG_ACPI_BERT_SIZE=0x0
-CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_IFD_CHIPSET="sklkbl"
-CONFIG_IED_REGION_SIZE=0x400000
-CONFIG_MAX_ROOT_PORTS=24
-CONFIG_PCR_BASE_ADDRESS=0xfd000000
-CONFIG_CPU_BCLK_MHZ=100
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ=120
-CONFIG_CPU_XTAL_HZ=24000000
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX=2
-CONFIG_SOC_INTEL_I2C_DEV_MAX=6
-# CONFIG_ENABLE_SATA_TEST_MODE is not set
-CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
-CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
-CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
-CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
-CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_FSP_PUBLISH_MBP_HOB=y
-CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
-CONFIG_MAX_HECI_DEVICES=5
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HAVE_PAM0_REGISTER=y
-CONFIG_PCIEXP_COMMON_CLOCK=y
-CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
-CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
-CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
-CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
-CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
-CONFIG_SOC_INTEL_KABYLAKE=y
-CONFIG_SKYLAKE_SOC_PCH_H=y
-CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU=y
-CONFIG_MAINBOARD_SUPPORTS_COFFEELAKE_CPU=y
-CONFIG_FSP_T_LOCATION=0xfffe0000
-CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
-CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
-CONFIG_CBFS_CACHE_ALIGN=8
-CONFIG_SOC_INTEL_COMMON=y
-
-#
-# Intel SoC Common Code for IP blocks
-#
-CONFIG_SOC_INTEL_COMMON_BLOCK=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_GPIO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_LPIT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_PEP=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ACPI_CPPC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT=y
-CONFIG_USE_FSP_FEATURE_PROGRAM_ON_APS=y
-# CONFIG_USE_COREBOOT_MP_INIT is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_SMMRELOCATE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CAR=y
-CONFIG_INTEL_CAR_NEM_ENHANCED=y
-# CONFIG_USE_INTEL_FSP_MP_INIT is not set
-CONFIG_CPU_SUPPORTS_PM_TIMER_EMULATION=y
-CONFIG_HAVE_HYPERTHREADING=y
-CONFIG_FSP_HYPERTHREADING=y
-# CONFIG_INTEL_KEYLOCKER is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_MAX is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_256MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_128MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_64MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_32MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_16MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_8MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_4MB is not set
-# CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_2MB is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_PRMRR_SIZE_0MB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_CSE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR=y
-CONFIG_SOC_INTEL_CSE_FMAP_NAME="SI_ME"
-CONFIG_SOC_INTEL_CSE_RW_A_FMAP_NAME="ME_RW_A"
-CONFIG_SOC_INTEL_CSE_RW_B_FMAP_NAME="ME_RW_B"
-CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME="me_rw"
-CONFIG_SOC_INTEL_CSE_RW_HASH_CBFS_NAME="me_rw.hash"
-CONFIG_SOC_INTEL_CSE_RW_VERSION_CBFS_NAME="me_rw.version"
-CONFIG_SOC_INTEL_CSE_RW_FILE=""
-CONFIG_SOC_INTEL_CSE_RW_VERSION=""
-CONFIG_SOC_INTEL_CSE_IOM_CBFS_NAME="cse_iom"
-CONFIG_SOC_INTEL_CSE_IOM_CBFS_FILE=""
-CONFIG_SOC_INTEL_CSE_NPHY_CBFS_NAME="cse_nphy"
-CONFIG_SOC_INTEL_CSE_NPHY_CBFS_FILE=""
-CONFIG_CSE_RESET_CLEAR_EC_AP_IDLE_FLAG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_DSP=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_FAST_SPI=y
-CONFIG_FAST_SPI_DISABLE_WRITE_STATUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GPMR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_GRAPHICS=y
-CONFIG_SOC_INTEL_GFX_HAVE_DDI_A_BIFURCATION=y
-# CONFIG_SOC_INTEL_DISABLE_IGD is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HDA=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_I2C=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_ITSS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPC_MIRROR_TO_GPMR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_BASE_P2SB=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PCIE=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PCR=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PMC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE=y
-CONFIG_PMC_GLOBAL_RESET_ENABLE_LOCK=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_POWER_LIMIT=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_RTC=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SATA=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SCS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SGX=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SGX_LOCK_MEMORY=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TCO=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP=y
-# CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE is not set
-CONFIG_SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS=0
-CONFIG_SOC_INTEL_COMMON_BLOCK_SPI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_SA=y
-CONFIG_SA_ENABLE_DPR=y
-CONFIG_HAVE_CAPID_A_REGISTER=y
-CONFIG_HAVE_BDSM_BGSM_REGISTER=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_TIMER=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_UART=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
-CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
-
-#
-# Intel SoC Common PCH Code
-#
-CONFIG_SOC_INTEL_COMMON_PCH_CLIENT=y
-CONFIG_SOC_INTEL_COMMON_PCH_BASE=y
-CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN=y
-CONFIG_PCH_SPECIFIC_BASE_OPTIONS=y
-CONFIG_PCH_SPECIFIC_DISCRETE_OPTIONS=y
-CONFIG_PCH_SPECIFIC_CLIENT_OPTIONS=y
-
-#
-# Intel SoC Common coreboot stages and non-IP blocks
-#
-CONFIG_SOC_INTEL_COMMON_BASECODE=y
-CONFIG_SOC_INTEL_COMMON_RESET=y
-CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE=y
-CONFIG_PAVP=y
-# CONFIG_MMA is not set
-CONFIG_SOC_INTEL_COMMON_NHLT=y
-# CONFIG_SOC_INTEL_DEBUG_CONSENT is not set
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_PARALLEL_MP_AP_WORK=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-
-#
-# Southbridge
-#
-# CONFIG_PCIEXP_HOTPLUG is not set
-CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-CONFIG_SUPERIO_SMSC_SCH555x=y
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-CONFIG_HAVE_ME_BIN=y
-# CONFIG_STITCH_ME_BIN is not set
-# CONFIG_CHECK_ME is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-# CONFIG_USE_ME_CLEANER is not set
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-CONFIG_UDK_BASE=y
-CONFIG_UDK_2017_BINDING=y
-CONFIG_UDK_2013_VERSION=2013
-CONFIG_UDK_2017_VERSION=2017
-CONFIG_UDK_202005_VERSION=202005
-CONFIG_UDK_202111_VERSION=202111
-CONFIG_UDK_202302_VERSION=202302
-CONFIG_UDK_202305_VERSION=202305
-CONFIG_UDK_VERSION=2017
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_HAVE_FSP_GOP=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_RUN_FSP_GOP is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
-# CONFIG_DRIVERS_EFI_FW_INFO is not set
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-CONFIG_MRC_SETTINGS_PROTECT=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_DESIGNWARE=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_FSP_USE_REPO=y
-# CONFIG_DISPLAY_HOBS is not set
-# CONFIG_DISPLAY_UPD_DATA is not set
-# CONFIG_BMP_LOGO is not set
-CONFIG_PLATFORM_USES_FSP2_0=y
-CONFIG_PLATFORM_USES_FSP2_X86_32=y
-CONFIG_HAVE_INTEL_FSP_REPO=y
-CONFIG_ADD_FSP_BINARIES=y
-CONFIG_FSP_S_CBFS="fsps.bin"
-CONFIG_FSP_M_CBFS="fspm.bin"
-CONFIG_FSP_FULL_FD=y
-CONFIG_FSP_T_RESERVED_SIZE=0x0
-CONFIG_FSP_M_XIP=y
-CONFIG_HAVE_FSP_LOGO_SUPPORT=y
-CONFIG_FSP_COMPRESS_FSP_S_LZ4=y
-CONFIG_SOC_INTEL_COMMON_FSP_RESET=y
-CONFIG_USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM=y
-CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
-CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
-# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
-# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="Skylake"
-CONFIG_GFX_GMA_PCH="Sunrise_Point"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-CONFIG_USE_PC_CMOS_ALTCENTURY=y
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_USB_ACPI=y
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-# CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT is not set
-# end of Memory initialization
-
-# CONFIG_STM is not set
-# CONFIG_INTEL_CBNT_SUPPORT is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_SOC_NVS=y
-CONFIG_ACPI_CUSTOM_MADT=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_ACPI_LPIT=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-CONFIG_RTC=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_ACPI_S1_NOT_SUPPORTED=y
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_ACPI_NHLT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-# CONFIG_DISPLAY_FSP_CALLS_AND_STATUS is not set
-# CONFIG_DISPLAY_FSP_HEADER is not set
-# CONFIG_VERIFY_HOBS is not set
-# CONFIG_DISPLAY_FSP_VERSION_INFO is not set
-CONFIG_HAVE_GPIO_SNAPSHOT_VERIFY_SUPPORT=y
-# CONFIG_CHECK_GPIO_CONFIG_CHANGES is not set
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-CONFIG_HAVE_DEBUG_GPIO=y
-# CONFIG_DEBUG_GPIO is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_GENERIC_GPIO_LIB=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/dell3050micro_fsp_16mb/target.cfg

@@ -1,11 +0,0 @@
-tree="next"
-xarch="i386-elf"
-payload_seabios="y"
-payload_grub="y"
-payload_memtest="y"
-grub_scan_disk="nvme ahci"
-grubtree="xhci"
-vcfg="3050micro"
-build_depend="seabios/default grub/xhci memtest86plus u-boot/amd64coreboot"
-IFD_platform="sklkbl"
-payload_uboot_amd64="y"

config/coreboot/dell7010sff_12mb/target.cfg

@@ -1,10 +0,0 @@
-tree="default"
-xarch="i386-elf"
-payload_seabios="y"
-payload_grub="y"
-payload_memtest="y"
-grub_scan_disk="nvme ahci"
-grubtree="nvme"
-vcfg="t1650"
-build_depend="seabios/default grub/nvme memtest86plus u-boot/amd64coreboot"
-payload_uboot_amd64="y"

config/coreboot/dell780mt_8mb/config/libgfxinit_corebootfb

@@ -1,656 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_780"
-CONFIG_VGA_BIOS_ID="8086,2e22"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x7FD000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_VARIANT_DIR="780_mt"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
-# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
-CONFIG_DCACHE_RAM_BASE=0xfeff8000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=8192
-CONFIG_ROM_SIZE=0x00800000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_X86_64_SUPPORT is not set
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_MODEL_F3X=y
-CONFIG_CPU_INTEL_MODEL_F4X=y
-CONFIG_CPU_INTEL_SOCKET_LGA775=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_X4X=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-# CONFIG_HAVE_ME_BIN is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/dell780mt_8mb/config/libgfxinit_txtmode

@@ -1,652 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_780"
-CONFIG_VGA_BIOS_ID="8086,2e22"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x7FD000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_VARIANT_DIR="780_mt"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
-# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
-CONFIG_DCACHE_RAM_BASE=0xfeff8000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=8192
-CONFIG_ROM_SIZE=0x00800000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_X86_64_SUPPORT is not set
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_MODEL_F3X=y
-CONFIG_CPU_INTEL_MODEL_F4X=y
-CONFIG_CPU_INTEL_SOCKET_LGA775=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_X4X=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-# CONFIG_HAVE_ME_BIN is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/dell780mt_8mb/target.cfg

@@ -1,9 +0,0 @@
-tree="next"
-xarch="i386-elf"
-payload_seabios="y"
-payload_grub="y"
-payload_memtest="y"
-grub_scan_disk="nvme ahci ata"
-grubtree="nvme"
-build_depend="seabios/default grub/nvme memtest86plus u-boot/amd64coreboot"
-payload_uboot_amd64="y"

config/coreboot/dell780mt_truncate_8mb/config/libgfxinit_corebootfb

@@ -1,656 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_780"
-CONFIG_VGA_BIOS_ID="8086,2e22"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x5FD000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_VARIANT_DIR="780_mt"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
-# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
-CONFIG_DCACHE_RAM_BASE=0xfeff8000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8_truncate"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=6144
-CONFIG_ROM_SIZE=0x00600000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_X86_64_SUPPORT is not set
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_MODEL_F3X=y
-CONFIG_CPU_INTEL_MODEL_F4X=y
-CONFIG_CPU_INTEL_SOCKET_LGA775=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_X4X=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-# CONFIG_HAVE_ME_BIN is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/dell780mt_truncate_8mb/config/libgfxinit_txtmode

@@ -1,652 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 MT"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_780"
-CONFIG_VGA_BIOS_ID="8086,2e22"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x5FD000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_VARIANT_DIR="780_mt"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
-# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
-CONFIG_DCACHE_RAM_BASE=0xfeff8000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8_truncate"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=6144
-CONFIG_ROM_SIZE=0x00600000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_X86_64_SUPPORT is not set
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_MODEL_F3X=y
-CONFIG_CPU_INTEL_MODEL_F4X=y
-CONFIG_CPU_INTEL_SOCKET_LGA775=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_X4X=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-# CONFIG_HAVE_ME_BIN is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/dell780mt_truncate_8mb/target.cfg

@@ -1,9 +0,0 @@
-tree="next"
-xarch="i386-elf"
-payload_seabios="y"
-payload_grub="y"
-payload_memtest="y"
-grub_scan_disk="nvme ahci ata"
-grubtree="nvme"
-build_depend="seabios/default grub/nvme memtest86plus u-boot/amd64coreboot"
-payload_uboot_amd64="y"

config/coreboot/dell780usff_8mb/config/libgfxinit_corebootfb

@@ -1,656 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 USFF"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_780"
-CONFIG_VGA_BIOS_ID="8086,2e22"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x7FD000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_VARIANT_DIR="780_usff"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
-CONFIG_DCACHE_RAM_BASE=0xfeff8000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=8192
-CONFIG_ROM_SIZE=0x00800000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_X86_64_SUPPORT is not set
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_MODEL_F3X=y
-CONFIG_CPU_INTEL_MODEL_F4X=y
-CONFIG_CPU_INTEL_SOCKET_LGA775=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_X4X=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-# CONFIG_HAVE_ME_BIN is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/dell780usff_8mb/config/libgfxinit_txtmode

@@ -1,652 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 USFF"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_780"
-CONFIG_VGA_BIOS_ID="8086,2e22"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x7FD000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_VARIANT_DIR="780_usff"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
-CONFIG_DCACHE_RAM_BASE=0xfeff8000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_6144 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=8192
-CONFIG_ROM_SIZE=0x00800000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_X86_64_SUPPORT is not set
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_MODEL_F3X=y
-CONFIG_CPU_INTEL_MODEL_F4X=y
-CONFIG_CPU_INTEL_SOCKET_LGA775=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_X4X=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-# CONFIG_HAVE_ME_BIN is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-CONFIG_VGA_TEXT_FRAMEBUFFER=y
-# CONFIG_GENERIC_LINEAR_FRAMEBUFFER is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y

config/coreboot/dell780usff_8mb/target.cfg

@@ -1,9 +0,0 @@
-tree="next"
-xarch="i386-elf"
-payload_seabios="y"
-payload_grub="y"
-payload_memtest="y"
-grub_scan_disk="nvme ahci ata"
-grubtree="nvme"
-build_depend="seabios/default grub/nvme memtest86plus u-boot/amd64coreboot"
-payload_uboot_amd64="y"

config/coreboot/dell780usff_truncate_8mb/config/libgfxinit_corebootfb

@@ -1,656 +0,0 @@
-#
-# Automatically generated file; DO NOT EDIT.
-# coreboot configuration
-#
-
-#
-# General setup
-#
-CONFIG_LOCALVERSION=""
-CONFIG_CBFS_PREFIX="fallback"
-CONFIG_COMPILER_GCC=y
-# CONFIG_COMPILER_LLVM_CLANG is not set
-# CONFIG_ANY_TOOLCHAIN is not set
-# CONFIG_CCACHE is not set
-# CONFIG_LTO is not set
-# CONFIG_IWYU is not set
-# CONFIG_FMD_GENPARSER is not set
-# CONFIG_UTIL_GENPARSER is not set
-# CONFIG_OPTION_BACKEND_NONE is not set
-CONFIG_USE_OPTION_TABLE=y
-CONFIG_STATIC_OPTION_TABLE=y
-CONFIG_COMPRESS_RAMSTAGE_LZMA=y
-# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
-CONFIG_SEPARATE_ROMSTAGE=y
-CONFIG_INCLUDE_CONFIG_FILE=y
-CONFIG_COLLECT_TIMESTAMPS=y
-# CONFIG_TIMESTAMPS_ON_CONSOLE is not set
-CONFIG_USE_BLOBS=y
-# CONFIG_USE_AMD_BLOBS is not set
-# CONFIG_USE_QC_BLOBS is not set
-# CONFIG_COVERAGE is not set
-# CONFIG_UBSAN is not set
-CONFIG_HAVE_ASAN_IN_RAMSTAGE=y
-# CONFIG_ASAN is not set
-# CONFIG_NO_STAGE_CACHE is not set
-CONFIG_TSEG_STAGE_CACHE=y
-# CONFIG_UPDATE_IMAGE is not set
-# CONFIG_BOOTSPLASH_IMAGE is not set
-
-#
-# Software Bill Of Materials (SBOM)
-#
-# CONFIG_SBOM is not set
-# end of Software Bill Of Materials (SBOM)
-# end of General setup
-
-#
-# Mainboard
-#
-
-#
-# Important: Run 'make distclean' before switching boards
-#
-# CONFIG_VENDOR_51NB is not set
-# CONFIG_VENDOR_ACER is not set
-# CONFIG_VENDOR_AMD is not set
-# CONFIG_VENDOR_AOOSTAR is not set
-# CONFIG_VENDOR_AOPEN is not set
-# CONFIG_VENDOR_APPLE is not set
-# CONFIG_VENDOR_ARM is not set
-# CONFIG_VENDOR_ASROCK is not set
-# CONFIG_VENDOR_ASUS is not set
-# CONFIG_VENDOR_BIOSTAR is not set
-# CONFIG_VENDOR_BOSTENTECH is not set
-# CONFIG_VENDOR_BYTEDANCE is not set
-# CONFIG_VENDOR_CAVIUM is not set
-# CONFIG_VENDOR_CLEVO is not set
-# CONFIG_VENDOR_COMPULAB is not set
-# CONFIG_VENDOR_CWWK is not set
-CONFIG_VENDOR_DELL=y
-# CONFIG_VENDOR_EMULATION is not set
-# CONFIG_VENDOR_ERYING is not set
-# CONFIG_VENDOR_EXAMPLE is not set
-# CONFIG_VENDOR_FACEBOOK is not set
-# CONFIG_VENDOR_FOXCONN is not set
-# CONFIG_VENDOR_FRAMEWORK is not set
-# CONFIG_VENDOR_GETAC is not set
-# CONFIG_VENDOR_GIGABYTE is not set
-# CONFIG_VENDOR_GOOGLE is not set
-# CONFIG_VENDOR_HARDKERNEL is not set
-# CONFIG_VENDOR_HP is not set
-# CONFIG_VENDOR_IBASE is not set
-# CONFIG_VENDOR_IBM is not set
-# CONFIG_VENDOR_INTEL is not set
-# CONFIG_VENDOR_INVENTEC is not set
-# CONFIG_VENDOR_KONTRON is not set
-# CONFIG_VENDOR_LATTEPANDA is not set
-# CONFIG_VENDOR_LENOVO is not set
-# CONFIG_VENDOR_LIBRETREND is not set
-# CONFIG_VENDOR_MSI is not set
-# CONFIG_VENDOR_OCP is not set
-# CONFIG_VENDOR_OPENCELLULAR is not set
-# CONFIG_VENDOR_PACKARDBELL is not set
-# CONFIG_VENDOR_PCENGINES is not set
-# CONFIG_VENDOR_PINE64 is not set
-# CONFIG_VENDOR_PORTWELL is not set
-# CONFIG_VENDOR_PRODRIVE is not set
-# CONFIG_VENDOR_PROTECTLI is not set
-# CONFIG_VENDOR_PURISM is not set
-# CONFIG_VENDOR_RAPTOR_CS is not set
-# CONFIG_VENDOR_RAZER is not set
-# CONFIG_VENDOR_RODA is not set
-# CONFIG_VENDOR_SAMSUNG is not set
-# CONFIG_VENDOR_SAPPHIRE is not set
-# CONFIG_VENDOR_SIEMENS is not set
-# CONFIG_VENDOR_SIFIVE is not set
-# CONFIG_VENDOR_STARLABS is not set
-# CONFIG_VENDOR_SUPERMICRO is not set
-# CONFIG_VENDOR_SYSTEM76 is not set
-# CONFIG_VENDOR_TI is not set
-# CONFIG_VENDOR_TOPTON is not set
-# CONFIG_VENDOR_UP is not set
-# CONFIG_VENDOR_VIA is not set
-CONFIG_MAINBOARD_PART_NUMBER="OptiPlex 780 USFF"
-CONFIG_MAINBOARD_VERSION="1.0"
-CONFIG_MAINBOARD_DIR="dell/optiplex_780"
-CONFIG_VGA_BIOS_ID="8086,2e22"
-CONFIG_DIMM_MAX=4
-CONFIG_DIMM_SPD_SIZE=256
-CONFIG_FMDFILE=""
-# CONFIG_NO_POST is not set
-CONFIG_MAINBOARD_VENDOR="Dell Inc."
-CONFIG_CBFS_SIZE=0x5FD000
-CONFIG_CONSOLE_SERIAL=y
-CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
-CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
-CONFIG_MAX_CPUS=4
-# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
-CONFIG_POST_DEVICE=y
-CONFIG_POST_IO=y
-CONFIG_UART_FOR_CONSOLE=0
-CONFIG_VARIANT_DIR="780_usff"
-CONFIG_OVERRIDE_DEVICETREE="variants/$(CONFIG_VARIANT_DIR)/overridetree.cb"
-CONFIG_DEVICETREE="devicetree.cb"
-# CONFIG_VBOOT is not set
-# CONFIG_VGA_BIOS is not set
-CONFIG_PCIEXP_ASPM=y
-# CONFIG_PCIEXP_L1_SUB_STATE is not set
-CONFIG_PCIEXP_CLK_PM=y
-CONFIG_MAINBOARD_SMBIOS_MANUFACTURER="Dell Inc."
-CONFIG_ECAM_MMCONF_BASE_ADDRESS=0xe0000000
-CONFIG_ECAM_MMCONF_BUS_NUMBER=256
-CONFIG_MEMLAYOUT_LD_FILE="src/arch/x86/memlayout.ld"
-# CONFIG_FATAL_ASSERTS is not set
-CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/data.vbt"
-CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
-CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 780 MT"
-# CONFIG_CONSOLE_POST is not set
-CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
-CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
-CONFIG_MAX_SOCKET=1
-CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
-# CONFIG_BOARD_DELL_E6400 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6320 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6420 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6520 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E5530 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6230 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6330 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6430 is not set
-# CONFIG_BOARD_DELL_LATITUDE_E6530 is not set
-# CONFIG_BOARD_DELL_OPTIPLEX_9010 is not set
-# CONFIG_BOARD_DELL_PRECISION_T1650 is not set
-# CONFIG_BOARD_DELL_XPS_8300 is not set
-CONFIG_BOARD_DELL_OPTIPLEX_780_COMMON=y
-CONFIG_DCACHE_RAM_BASE=0xfeff8000
-CONFIG_DCACHE_RAM_SIZE=0x8000
-CONFIG_C_ENV_BOOTBLOCK_SIZE=0x40000
-CONFIG_DCACHE_BSP_STACK_SIZE=0x2000
-CONFIG_MAX_ACPI_TABLE_SIZE_KB=144
-CONFIG_HAVE_INTEL_FIRMWARE=y
-CONFIG_MRC_SETTINGS_CACHE_SIZE=0x10000
-CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y
-CONFIG_SPI_FLASH_WINBOND=y
-CONFIG_DRIVERS_INTEL_WIFI=y
-CONFIG_IFD_BIN_PATH="../../../config/ifd/ich10/ifd_8_truncate"
-CONFIG_GBE_BIN_PATH="../../../config/ifd/ich10/gbe"
-CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
-CONFIG_CARDBUS_PLUGIN_SUPPORT=y
-CONFIG_SPI_FLASH_GIGADEVICE=y
-CONFIG_SPI_FLASH_STMICRO=y
-# CONFIG_DEBUG_SMI is not set
-CONFIG_HAVE_IFD_BIN=y
-CONFIG_PCIEXP_HOTPLUG_BUSES=8
-CONFIG_PCIEXP_HOTPLUG_MEM=0x800000
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM=0x10000000
-CONFIG_PS2K_EISAID="PNP0303"
-CONFIG_PS2M_EISAID="PNP0F13"
-CONFIG_GFX_GMA_PANEL_1_PORT="eDP"
-CONFIG_TTYS0_BAUD=115200
-CONFIG_D3COLD_SUPPORT=y
-CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
-CONFIG_DRIVERS_UART_8250IO=y
-CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x100000
-CONFIG_EC_GPE_SCI=0x50
-CONFIG_EC_STARLABS_BATTERY_MODEL="Unknown"
-CONFIG_EC_STARLABS_BATTERY_TYPE="LION"
-CONFIG_EC_STARLABS_BATTERY_OEM="Unknown"
-CONFIG_BOARD_ROMSIZE_KB_8192=y
-# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_1024 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_2048 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_4096 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_5120 is not set
-CONFIG_COREBOOT_ROMSIZE_KB_6144=y
-# CONFIG_COREBOOT_ROMSIZE_KB_8192 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_10240 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_12288 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_16384 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_24576 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_32768 is not set
-# CONFIG_COREBOOT_ROMSIZE_KB_65536 is not set
-CONFIG_COREBOOT_ROMSIZE_KB=6144
-CONFIG_ROM_SIZE=0x00600000
-CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=y
-CONFIG_HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE=y
-CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y
-# CONFIG_POWER_STATE_ON_AFTER_FAILURE is not set
-# CONFIG_POWER_STATE_PREVIOUS_AFTER_FAILURE is not set
-CONFIG_MAINBOARD_POWER_FAILURE_STATE=0
-# end of Mainboard
-
-#
-# Chipset
-#
-
-#
-# SoC
-#
-CONFIG_CHIPSET_DEVICETREE=""
-CONFIG_CBFS_MCACHE_SIZE=0x4000
-CONFIG_ROMSTAGE_ADDR=0x2000000
-CONFIG_VERSTAGE_ADDR=0x2000000
-CONFIG_SMM_RESERVED_SIZE=0x100000
-CONFIG_SMM_MODULE_STACK_SIZE=0x400
-# CONFIG_USE_X86_64_SUPPORT is not set
-CONFIG_PRERAM_CBFS_CACHE_SIZE=0x0
-CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xfec00000
-CONFIG_EHCI_BAR=0xfef00000
-CONFIG_ACPI_CPU_STRING="CP%02X"
-CONFIG_STACK_SIZE=0x2000
-CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
-CONFIG_INTEL_GMA_BCLV_WIDTH=16
-CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
-CONFIG_INTEL_GMA_BCLM_WIDTH=16
-CONFIG_BOOTBLOCK_IN_CBFS=y
-CONFIG_HPET_MIN_TICKS=0x80
-CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
-CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
-CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
-# CONFIG_PCIEXP_COMMON_CLOCK is not set
-CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
-CONFIG_FIXED_SMBUS_IO_BASE=0x400
-CONFIG_CBFS_CACHE_ALIGN=8
-
-#
-# CPU
-#
-CONFIG_CPU_INTEL_MODEL_6FX=y
-CONFIG_CPU_INTEL_MODEL_1067X=y
-CONFIG_CPU_INTEL_MODEL_F3X=y
-CONFIG_CPU_INTEL_MODEL_F4X=y
-CONFIG_CPU_INTEL_SOCKET_LGA775=y
-CONFIG_CPU_INTEL_COMMON=y
-CONFIG_ENABLE_VMX=y
-CONFIG_SET_IA32_FC_LOCK_BIT=y
-CONFIG_SET_MSR_AESNI_LOCK_BIT=y
-CONFIG_CPU_INTEL_COMMON_TIMEBASE=y
-CONFIG_CPU_INTEL_COMMON_SMM=y
-CONFIG_MICROCODE_UPDATE_PRE_RAM=y
-CONFIG_PARALLEL_MP=y
-CONFIG_XAPIC_ONLY=y
-# CONFIG_X2APIC_ONLY is not set
-# CONFIG_X2APIC_RUNTIME is not set
-# CONFIG_X2APIC_LATE_WORKAROUND is not set
-CONFIG_UDELAY_TSC=y
-CONFIG_TSC_MONOTONIC_TIMER=y
-CONFIG_TSC_SYNC_MFENCE=y
-CONFIG_SETUP_XIP_CACHE=y
-CONFIG_HAVE_SMI_HANDLER=y
-CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
-CONFIG_SMM_TSEG=y
-CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
-CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
-CONFIG_AP_STACK_SIZE=0x800
-CONFIG_SMP=y
-CONFIG_SSE=y
-CONFIG_SSE2=y
-CONFIG_SUPPORT_CPU_UCODE_IN_CBFS=y
-CONFIG_USE_CPU_MICROCODE_CBFS_BINS=y
-CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS is not set
-# CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER is not set
-# CONFIG_CPU_MICROCODE_CBFS_NONE is not set
-
-#
-# Northbridge
-#
-CONFIG_NORTHBRIDGE_INTEL_X4X=y
-
-#
-# Southbridge
-#
-CONFIG_PCIEXP_HOTPLUG=y
-CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMBASE=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_GPIO=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_ICH9=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_PIRQ_ACPI_GEN=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMM=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_USB_DEBUG=y
-CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
-# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
-CONFIG_TCO_SPACE_NOT_YET_SPLIT=y
-CONFIG_SOUTHBRIDGE_INTEL_COMMON_WATCHDOG=y
-CONFIG_FIXED_RCBA_MMIO_BASE=0xfed1c000
-CONFIG_RCBA_LENGTH=0x4000
-
-#
-# Super I/O
-#
-
-#
-# Embedded Controllers
-#
-
-#
-# Intel Firmware
-#
-# CONFIG_HAVE_ME_BIN is not set
-# CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS is not set
-CONFIG_MAINBOARD_USES_IFD_GBE_REGION=y
-CONFIG_HAVE_GBE_BIN=y
-# CONFIG_DO_NOT_TOUCH_DESCRIPTOR_REGION is not set
-# CONFIG_LOCK_MANAGEMENT_ENGINE is not set
-CONFIG_UNLOCK_FLASH_REGIONS=y
-CONFIG_ACPI_FNKEY_GEN_SCANCODE=0
-CONFIG_ARCH_X86=y
-CONFIG_ARCH_BOOTBLOCK_X86_32=y
-CONFIG_ARCH_VERSTAGE_X86_32=y
-CONFIG_ARCH_ROMSTAGE_X86_32=y
-CONFIG_ARCH_POSTCAR_X86_32=y
-CONFIG_ARCH_RAMSTAGE_X86_32=y
-CONFIG_ARCH_ALL_STAGES_X86_32=y
-CONFIG_HAVE_X86_64_SUPPORT=y
-CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
-CONFIG_AP_IN_SIPI_WAIT=y
-CONFIG_SIPI_VECTOR_IN_ROM=y
-CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
-CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
-CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
-CONFIG_PC80_SYSTEM=y
-CONFIG_HAVE_CMOS_DEFAULT=y
-CONFIG_POSTCAR_STAGE=y
-CONFIG_BOOTBLOCK_SIMPLE=y
-# CONFIG_BOOTBLOCK_NORMAL is not set
-CONFIG_COLLECT_TIMESTAMPS_TSC=y
-CONFIG_HAVE_CF9_RESET=y
-CONFIG_DEBUG_HW_BREAKPOINTS=y
-CONFIG_DEBUG_NULL_DEREF_BREAKPOINTS=y
-# CONFIG_DUMP_SMBIOS_TYPE17 is not set
-CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
-CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
-CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
-CONFIG_DEFAULT_EBDA_SIZE=0x400
-# end of Chipset
-
-#
-# Devices
-#
-CONFIG_HAVE_VGA_TEXT_FRAMEBUFFER=y
-CONFIG_HAVE_LINEAR_FRAMEBUFFER=y
-CONFIG_MAINBOARD_HAS_LIBGFXINIT=y
-CONFIG_MAINBOARD_USE_LIBGFXINIT=y
-# CONFIG_VGA_ROM_RUN is not set
-# CONFIG_NO_GFX_INIT is not set
-CONFIG_NO_EARLY_GFX_INIT=y
-
-#
-# Display
-#
-# CONFIG_VGA_TEXT_FRAMEBUFFER is not set
-CONFIG_GENERIC_LINEAR_FRAMEBUFFER=y
-CONFIG_LINEAR_FRAMEBUFFER=y
-# CONFIG_BOOTSPLASH is not set
-CONFIG_DEFAULT_SCREEN_ROTATION_INT=0
-# end of Display
-
-CONFIG_PCI=y
-CONFIG_ECAM_MMCONF_SUPPORT=y
-CONFIG_PCIX_PLUGIN_SUPPORT=y
-CONFIG_AZALIA_HDA_CODEC_SUPPORT=y
-CONFIG_PCIEXP_PLUGIN_SUPPORT=y
-CONFIG_ECAM_MMCONF_LENGTH=0x10000000
-CONFIG_PCI_ALLOW_BUS_MASTER=y
-CONFIG_PCI_SET_BUS_MASTER_PCI_BRIDGES=y
-CONFIG_PCI_ALLOW_BUS_MASTER_ANY_DEVICE=y
-# CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS is not set
-# CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR is not set
-CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_ABOVE_4G=y
-# CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G is not set
-CONFIG_PCIEXP_HOTPLUG_IO=0x800
-# CONFIG_EARLY_PCI_BRIDGE is not set
-CONFIG_SUBSYSTEM_VENDOR_ID=0x0000
-CONFIG_SUBSYSTEM_DEVICE_ID=0x0000
-CONFIG_INTEL_GMA_HAVE_VBT=y
-CONFIG_INTEL_GMA_ADD_VBT=y
-# CONFIG_SOFTWARE_I2C is not set
-CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
-CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
-CONFIG_USE_DDR3=y
-CONFIG_USE_DDR2=y
-# end of Devices
-
-#
-# Generic Drivers
-#
-CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
-# CONFIG_ELOG is not set
-CONFIG_CACHE_MRC_SETTINGS=y
-# CONFIG_MRC_SETTINGS_PROTECT is not set
-CONFIG_MRC_STASH_TO_CBMEM=y
-# CONFIG_SMMSTORE is not set
-CONFIG_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y
-CONFIG_BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES=y
-# CONFIG_SPI_FLASH_NO_FAST_READ is not set
-CONFIG_SPI_FLASH_ADESTO=y
-CONFIG_SPI_FLASH_AMIC=y
-CONFIG_SPI_FLASH_ATMEL=y
-CONFIG_SPI_FLASH_EON=y
-CONFIG_SPI_FLASH_MACRONIX=y
-CONFIG_SPI_FLASH_SPANSION=y
-CONFIG_SPI_FLASH_SST=y
-CONFIG_SPI_FLASH_ISSI=y
-CONFIG_DRIVERS_UART=y
-# CONFIG_DRIVERS_UART_OXPCIE is not set
-CONFIG_HAVE_USBDEBUG=y
-CONFIG_HAVE_USBDEBUG_OPTIONS=y
-# CONFIG_USBDEBUG is not set
-# CONFIG_VPD is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_SERIAL is not set
-# CONFIG_DRIVERS_GENERIC_CBFS_UUID is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9750 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
-# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
-CONFIG_DRIVERS_I2C_CK505=y
-# CONFIG_DRIVERS_I2C_MAX98396 is not set
-CONFIG_INTEL_GMA_ACPI=y
-CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
-# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
-# CONFIG_VBT_CBFS_COMPRESSION_NONE is not set
-CONFIG_VBT_CBFS_COMPRESSION_ALGORITHM="lzma"
-CONFIG_GFX_GMA=y
-CONFIG_GFX_GMA_DYN_CPU=y
-CONFIG_GFX_GMA_GENERATION="G45"
-CONFIG_GFX_GMA_PCH="No_PCH"
-CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
-CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
-# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
-# CONFIG_DRIVERS_PS2_KEYBOARD is not set
-CONFIG_DRIVERS_MC146818=y
-# CONFIG_USE_PC_CMOS_ALTCENTURY is not set
-CONFIG_PC_CMOS_BASE_PORT_BANK0=0x70
-CONFIG_VGA=y
-# CONFIG_DRIVERS_SIL_3114 is not set
-CONFIG_DRIVERS_WIFI_GENERIC=y
-CONFIG_DRIVERS_MTK_WIFI=y
-# end of Generic Drivers
-
-#
-# Security
-#
-
-#
-# CBFS verification
-#
-# CONFIG_CBFS_VERIFICATION is not set
-# end of CBFS verification
-
-#
-# Verified Boot (vboot)
-#
-# end of Verified Boot (vboot)
-
-#
-# Trusted Platform Module
-#
-CONFIG_NO_TPM=y
-CONFIG_PCR_BOOT_MODE=1
-CONFIG_PCR_HWID=1
-CONFIG_PCR_SRTM=2
-CONFIG_PCR_FW_VER=10
-CONFIG_PCR_RUNTIME_DATA=3
-# end of Trusted Platform Module
-
-#
-# Memory initialization
-#
-CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
-CONFIG_SECURITY_CLEAR_DRAM_ON_REGULAR_BOOT=y
-# end of Memory initialization
-
-# CONFIG_STM is not set
-CONFIG_BOOTMEDIA_LOCK_NONE=y
-# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
-# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
-# CONFIG_BOOTMEDIA_SMM_BWP is not set
-# end of Security
-
-CONFIG_ACPI_HAVE_PCAT_8259=y
-CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES=y
-CONFIG_ACPI_NO_CUSTOM_MADT=y
-CONFIG_ACPI_COMMON_MADT_LAPIC=y
-CONFIG_ACPI_COMMON_MADT_IOAPIC=y
-CONFIG_HAVE_ACPI_TABLES=y
-CONFIG_BOOT_DEVICE_SPI_FLASH=y
-CONFIG_BOOT_DEVICE_MEMORY_MAPPED=y
-CONFIG_BOOT_DEVICE_SUPPORTS_WRITES=y
-
-#
-# Console
-#
-CONFIG_BOOTBLOCK_CONSOLE=y
-CONFIG_POSTCAR_CONSOLE=y
-CONFIG_SQUELCH_EARLY_SMP=y
-
-#
-# I/O mapped, 8250-compatible
-#
-CONFIG_TTYS0_BASE=0x3f8
-
-#
-# Serial port base address = 0x3f8
-#
-# CONFIG_CONSOLE_SERIAL_921600 is not set
-# CONFIG_CONSOLE_SERIAL_460800 is not set
-# CONFIG_CONSOLE_SERIAL_230400 is not set
-CONFIG_CONSOLE_SERIAL_115200=y
-# CONFIG_CONSOLE_SERIAL_57600 is not set
-# CONFIG_CONSOLE_SERIAL_38400 is not set
-# CONFIG_CONSOLE_SERIAL_19200 is not set
-# CONFIG_CONSOLE_SERIAL_9600 is not set
-CONFIG_TTYS0_LCS=3
-# CONFIG_SPKMODEM is not set
-# CONFIG_CONSOLE_NE2K is not set
-CONFIG_CONSOLE_CBMEM=y
-# CONFIG_CONSOLE_SPI_FLASH is not set
-# CONFIG_CONSOLE_I2C_SMBUS is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7=y
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_6 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_5 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_4 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_3 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_2 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1 is not set
-# CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0 is not set
-CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
-CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX=y
-CONFIG_CONSOLE_USE_ANSI_ESCAPES=y
-# CONFIG_CMOS_POST is not set
-CONFIG_POST_DEVICE_NONE=y
-# CONFIG_POST_DEVICE_LPC is not set
-# CONFIG_POST_DEVICE_PCI_PCIE is not set
-CONFIG_POST_IO_PORT=0x80
-CONFIG_HWBASE_DEBUG_CB=y
-# end of Console
-
-CONFIG_HAVE_ACPI_RESUME=y
-CONFIG_RESUME_PATH_SAME_AS_BOOT=y
-CONFIG_HAVE_MONOTONIC_TIMER=y
-CONFIG_HAVE_OPTION_TABLE=y
-CONFIG_IOAPIC=y
-CONFIG_USE_WATCHDOG_ON_BOOT=y
-
-#
-# System tables
-#
-CONFIG_GENERATE_SMBIOS_TABLES=y
-CONFIG_BIOS_VENDOR="coreboot"
-CONFIG_MAINBOARD_SERIAL_NUMBER="123456789"
-# end of System tables
-
-#
-# Payload
-#
-CONFIG_PAYLOAD_NONE=y
-# end of Payload
-
-#
-# Debugging
-#
-
-#
-# CPU Debug Settings
-#
-# CONFIG_DISPLAY_MTRRS is not set
-
-#
-# Vendorcode Debug Settings
-#
-
-#
-# BLOB Debug Settings
-#
-
-#
-# General Debug Settings
-#
-# CONFIG_GDB_STUB is not set
-# CONFIG_DEBUG_CBFS is not set
-CONFIG_HAVE_DEBUG_RAM_SETUP=y
-# CONFIG_DEBUG_RAM_SETUP is not set
-CONFIG_HAVE_DEBUG_SMBUS=y
-# CONFIG_DEBUG_SMBUS is not set
-# CONFIG_DEBUG_MALLOC is not set
-# CONFIG_DEBUG_CONSOLE_INIT is not set
-# CONFIG_DEBUG_SPI_FLASH is not set
-# CONFIG_DEBUG_BOOT_STATE is not set
-# CONFIG_DEBUG_ADA_CODE is not set
-CONFIG_HAVE_EM100_SUPPORT=y
-# CONFIG_EM100 is not set
-# CONFIG_DEBUG_ACPICA_COMPATIBLE is not set
-# end of Debugging
-
-CONFIG_RAMSTAGE_ADA=y
-CONFIG_RAMSTAGE_LIBHWBASE=y
-CONFIG_HWBASE_DYNAMIC_MMIO=y
-CONFIG_HWBASE_DEFAULT_MMCONF=0xe0000000
-CONFIG_HWBASE_DIRECT_PCIDEV=y
-CONFIG_DECOMPRESS_OFAST=y
-CONFIG_WARNINGS_ARE_ERRORS=y
-CONFIG_MAX_REBOOT_CNT=3
-CONFIG_RELOCATABLE_MODULES=y
-CONFIG_HAVE_BOOTBLOCK=y
-CONFIG_HAVE_ROMSTAGE=y
-CONFIG_HAVE_RAMSTAGE=y