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https://codeberg.org/libreboot/lbmk.git
synced 2026-07-11 05:52:36 +02:00
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5 Commits
0aa019d323
...
0e1e0fd0e8
| Author | SHA1 | Date | |
|---|---|---|---|
| 0e1e0fd0e8 | |||
| ad2d082bc2 | |||
| 9a132f96a2 | |||
| e90e1df74d | |||
| 154c5ff319 |
@@ -237,7 +237,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -288,6 +287,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -323,7 +326,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -340,9 +342,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
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||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
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||||
|
||||
#
|
||||
@@ -350,7 +349,6 @@ CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
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||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
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||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
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||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -388,7 +386,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
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||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
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||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
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||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
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||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
@@ -409,7 +406,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
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||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -533,11 +529,6 @@ CONFIG_PCR_FW_VER=10
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||||
CONFIG_PCR_RUNTIME_DATA=3
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||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -598,6 +589,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -653,10 +645,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -237,7 +237,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_1024=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -288,6 +287,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -323,7 +326,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -340,9 +342,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
|
||||
|
||||
#
|
||||
@@ -350,7 +349,6 @@ CONFIG_NORTHBRIDGE_INTEL_PINEVIEW=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -388,7 +386,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
@@ -409,7 +406,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -533,11 +529,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -598,6 +589,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -653,10 +645,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -236,7 +236,6 @@ CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
CONFIG_COREBOOT_ROMSIZE_KB_512=y
|
||||
@@ -287,6 +286,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -322,7 +325,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -339,9 +341,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_I945=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
|
||||
|
||||
@@ -350,7 +349,6 @@ CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -387,7 +385,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
@@ -408,7 +405,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -527,11 +523,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -592,6 +583,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
CONFIG_HAVE_MP_TABLE=y
|
||||
CONFIG_HAVE_PIRQ_TABLE=y
|
||||
@@ -652,10 +644,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -236,7 +236,6 @@ CONFIG_MAXIMUM_SUPPORTED_FREQUENCY=0
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_512=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -287,6 +286,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -322,7 +325,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -339,9 +341,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_I945=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
|
||||
|
||||
@@ -350,7 +349,6 @@ CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GC=y
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801GX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -387,7 +385,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_AP_IN_SIPI_WAIT=y
|
||||
@@ -408,7 +405,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -527,11 +523,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -592,6 +583,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
CONFIG_HAVE_MP_TABLE=y
|
||||
CONFIG_HAVE_PIRQ_TABLE=y
|
||||
@@ -652,10 +644,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -1,30 +1,30 @@
|
||||
From b6cbef6dc28cfe5c376310391a7bc0869ea5ffdb Mon Sep 17 00:00:00 2001
|
||||
From 03e8f5f33723fd291e30c5305fa2f5eb22bdf656 Mon Sep 17 00:00:00 2001
|
||||
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
|
||||
Date: Wed, 27 Oct 2021 13:36:01 +0200
|
||||
Subject: [PATCH 01/51] add c3 and clockgen to apple/macbook21
|
||||
Subject: [PATCH 01/48] add c3 and clockgen to apple/macbook21
|
||||
|
||||
---
|
||||
src/mainboard/apple/i945_macs/Kconfig | 1 +
|
||||
src/mainboard/apple/i945_macs/cstates.c | 13 +++++++++++++
|
||||
src/mainboard/apple/i945_macs/devicetree.cb | 6 ++++++
|
||||
src/mainboard/apple/macbook21/Kconfig | 1 +
|
||||
src/mainboard/apple/macbook21/cstates.c | 13 +++++++++++++
|
||||
src/mainboard/apple/macbook21/devicetree.cb | 6 ++++++
|
||||
3 files changed, 20 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/apple/i945_macs/Kconfig b/src/mainboard/apple/i945_macs/Kconfig
|
||||
index 42774e484a..cd5155e81a 100644
|
||||
--- a/src/mainboard/apple/i945_macs/Kconfig
|
||||
+++ b/src/mainboard/apple/i945_macs/Kconfig
|
||||
@@ -20,6 +20,7 @@ config BOARD_APPLE_MACBOOK11
|
||||
bool
|
||||
select BOARD_APPLE_I945_MACS_COMMON
|
||||
diff --git a/src/mainboard/apple/macbook21/Kconfig b/src/mainboard/apple/macbook21/Kconfig
|
||||
index 330d8efae2..cf10343554 100644
|
||||
--- a/src/mainboard/apple/macbook21/Kconfig
|
||||
+++ b/src/mainboard/apple/macbook21/Kconfig
|
||||
@@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS
|
||||
select HAVE_ACPI_TABLES
|
||||
select HAVE_ACPI_RESUME
|
||||
select I945_LVDS
|
||||
+ select DRIVERS_I2C_CK505
|
||||
|
||||
config BOARD_APPLE_MACBOOK21
|
||||
bool
|
||||
diff --git a/src/mainboard/apple/i945_macs/cstates.c b/src/mainboard/apple/i945_macs/cstates.c
|
||||
config MAINBOARD_DIR
|
||||
default "apple/macbook21"
|
||||
diff --git a/src/mainboard/apple/macbook21/cstates.c b/src/mainboard/apple/macbook21/cstates.c
|
||||
index 13d06f0839..88b8669c61 100644
|
||||
--- a/src/mainboard/apple/i945_macs/cstates.c
|
||||
+++ b/src/mainboard/apple/i945_macs/cstates.c
|
||||
--- a/src/mainboard/apple/macbook21/cstates.c
|
||||
+++ b/src/mainboard/apple/macbook21/cstates.c
|
||||
@@ -29,6 +29,19 @@ static const acpi_cstate_t cst_entries[] = {
|
||||
.addrh = 0,
|
||||
}
|
||||
@@ -45,11 +45,11 @@ index 13d06f0839..88b8669c61 100644
|
||||
};
|
||||
|
||||
int get_cst_entries(const acpi_cstate_t **entries)
|
||||
diff --git a/src/mainboard/apple/i945_macs/devicetree.cb b/src/mainboard/apple/i945_macs/devicetree.cb
|
||||
index b17f8ae529..18731b067f 100644
|
||||
--- a/src/mainboard/apple/i945_macs/devicetree.cb
|
||||
+++ b/src/mainboard/apple/i945_macs/devicetree.cb
|
||||
@@ -89,7 +89,13 @@ chip northbridge/intel/i945
|
||||
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb
|
||||
index fd86e939b9..263fbabcd1 100644
|
||||
--- a/src/mainboard/apple/macbook21/devicetree.cb
|
||||
+++ b/src/mainboard/apple/macbook21/devicetree.cb
|
||||
@@ -100,7 +100,13 @@ chip northbridge/intel/i945
|
||||
end
|
||||
device pci 1f.3 on # SMBUS
|
||||
subsystemid 0x8086 0x7270
|
||||
|
||||
-1097
File diff suppressed because it is too large
Load Diff
+2
-2
@@ -1,7 +1,7 @@
|
||||
From c1fd80b55e3ab8f651c2ad6e6eec6cdcb3922f9b Mon Sep 17 00:00:00 2001
|
||||
From da742084f51bb7e97472605d6eff0726fd7a5863 Mon Sep 17 00:00:00 2001
|
||||
From: persmule <persmule@gmail.com>
|
||||
Date: Sun, 31 Oct 2021 23:33:26 +0000
|
||||
Subject: [PATCH 03/51] lenovo/t400: Enable all SATA ports
|
||||
Subject: [PATCH 02/48] lenovo/t400: Enable all SATA ports
|
||||
|
||||
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
|
||||
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From bf1bb17d48b43ca468bca0b2d31315450f8cf8c6 Mon Sep 17 00:00:00 2001
|
||||
From 278c2a989c025c1b3a097966968c8d253c973a3e Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 3 Jan 2022 19:06:22 +0000
|
||||
Subject: [PATCH 04/51] lenovo/x230: set me_state=Disabled in cmos.default
|
||||
Subject: [PATCH 03/48] lenovo/x230: set me_state=Disabled in cmos.default
|
||||
|
||||
I only recently found out about this. It's possible to use me_cleaner to
|
||||
do the same thing, but some people might just flash coreboot and not do
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
From c0b5b390507c1a46af3224bd61f5c971e99607a2 Mon Sep 17 00:00:00 2001
|
||||
From 63357b7f8c9da3a8d644542c70f50fc9bc77a8fc Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Wed, 2 Mar 2022 21:50:01 +0000
|
||||
Subject: [PATCH 05/51] set me_state=Disabled on all cmos.default files!
|
||||
Subject: [PATCH 04/48] set me_state=Disabled on all cmos.default files!
|
||||
|
||||
yeah. why the hell isn't this the default
|
||||
|
||||
@@ -50,13 +50,13 @@ index 6fd26c5fe3..27a62d07b3 100644
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
|
||||
index 4857f92f67..ab1be1a678 100644
|
||||
index c896eadec1..6d1e172056 100644
|
||||
--- a/src/mainboard/lenovo/t430/cmos.default
|
||||
+++ b/src/mainboard/lenovo/t430/cmos.default
|
||||
@@ -17,4 +17,4 @@ trackpoint=Enable
|
||||
backlight=Both
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
usb_always_on=Disable
|
||||
hybrid_graphics_mode=Integrated Only
|
||||
-me_state=Normal
|
||||
+me_state=Disabled
|
||||
diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
|
||||
+12
-12
@@ -1,7 +1,7 @@
|
||||
From 75892a195d53054ceee67e23c487c4103f559332 Mon Sep 17 00:00:00 2001
|
||||
From 434136e0aca4839e449e3841a5e993688b4586f0 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sun, 19 Feb 2023 18:21:43 +0000
|
||||
Subject: [PATCH 06/51] util/ifdtool: add --nuke flag (all 0xFF on region)
|
||||
Subject: [PATCH 05/48] util/ifdtool: add --nuke flag (all 0xFF on region)
|
||||
|
||||
When this option is used, the region's contents are overwritten
|
||||
with all ones (0xFF).
|
||||
@@ -20,10 +20,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
1 file changed, 84 insertions(+), 32 deletions(-)
|
||||
|
||||
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
|
||||
index 0b75db54bd..7f0c10bd0b 100644
|
||||
index 0592785bf6..cab934c3a5 100644
|
||||
--- a/util/ifdtool/ifdtool.c
|
||||
+++ b/util/ifdtool/ifdtool.c
|
||||
@@ -2252,6 +2252,7 @@ static void print_usage(const char *name)
|
||||
@@ -2240,6 +2240,7 @@ static void print_usage(const char *name)
|
||||
" tgl - Tiger Lake\n"
|
||||
" wbg - Wellsburg\n"
|
||||
" -S | --setpchstrap Write a PCH strap\n"
|
||||
@@ -31,7 +31,7 @@ index 0b75db54bd..7f0c10bd0b 100644
|
||||
" -V | --newvalue The new value to write into PCH strap specified by -S\n"
|
||||
" -T | --topswapsize Set the Top Swap Block Size PCH strap value\n"
|
||||
" Possible values: 0x10000, 0x20000, 0x40000, 0x80000,\n"
|
||||
@@ -2263,6 +2264,60 @@ static void print_usage(const char *name)
|
||||
@@ -2251,6 +2252,60 @@ static void print_usage(const char *name)
|
||||
"\n");
|
||||
}
|
||||
|
||||
@@ -92,7 +92,7 @@ index 0b75db54bd..7f0c10bd0b 100644
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int opt, option_index = 0;
|
||||
@@ -2270,6 +2325,7 @@ int main(int argc, char *argv[])
|
||||
@@ -2258,6 +2313,7 @@ int main(int argc, char *argv[])
|
||||
int mode_em100 = 0, mode_locked = 0, mode_unlocked = 0, mode_validate = 0;
|
||||
int mode_layout = 0, mode_newlayout = 0, mode_density = 0, mode_setstrap = 0;
|
||||
int mode_read = 0, mode_altmedisable = 0, altmedisable = 0, mode_fmap_template = 0;
|
||||
@@ -100,7 +100,7 @@ index 0b75db54bd..7f0c10bd0b 100644
|
||||
int mode_gpr0_disable = 0, mode_gpr0_enable = 0, mode_gpr0_status = 0;
|
||||
int mode_settopswapsize = 0;
|
||||
char *region_type_string = NULL, *region_fname = NULL, *layout_fname = NULL;
|
||||
@@ -2306,6 +2362,7 @@ int main(int argc, char *argv[])
|
||||
@@ -2294,6 +2350,7 @@ int main(int argc, char *argv[])
|
||||
{"setpchstrap", 1, NULL, 'S'},
|
||||
{"newvalue", 1, NULL, 'V'},
|
||||
{"topswapsize", 1, NULL, 'T'},
|
||||
@@ -108,7 +108,7 @@ index 0b75db54bd..7f0c10bd0b 100644
|
||||
{0, 0, 0, 0}
|
||||
};
|
||||
|
||||
@@ -2355,35 +2412,8 @@ int main(int argc, char *argv[])
|
||||
@@ -2343,35 +2400,8 @@ int main(int argc, char *argv[])
|
||||
region_fname++;
|
||||
// Descriptor, BIOS, ME, GbE, Platform
|
||||
// valid type?
|
||||
@@ -146,7 +146,7 @@ index 0b75db54bd..7f0c10bd0b 100644
|
||||
fprintf(stderr, "No such region type: '%s'\n\n",
|
||||
region_type_string);
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
@@ -2564,7 +2594,23 @@ int main(int argc, char *argv[])
|
||||
@@ -2552,7 +2582,23 @@ int main(int argc, char *argv[])
|
||||
mode_settopswapsize = 1;
|
||||
top_swap_size_arg = optarg;
|
||||
break;
|
||||
@@ -171,7 +171,7 @@ index 0b75db54bd..7f0c10bd0b 100644
|
||||
print_version();
|
||||
exit(EXIT_SUCCESS);
|
||||
break;
|
||||
@@ -2583,7 +2629,8 @@ int main(int argc, char *argv[])
|
||||
@@ -2571,7 +2617,8 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_settopswapsize + mode_newlayout + (mode_spifreq | mode_em100 |
|
||||
mode_unlocked | mode_locked) + mode_altmedisable + mode_validate +
|
||||
@@ -181,7 +181,7 @@ index 0b75db54bd..7f0c10bd0b 100644
|
||||
fprintf(stderr, "You may not specify more than one mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2592,7 +2639,8 @@ int main(int argc, char *argv[])
|
||||
@@ -2580,7 +2627,8 @@ int main(int argc, char *argv[])
|
||||
if ((mode_dump + mode_layout + mode_fmap_template + mode_extract + mode_inject +
|
||||
mode_setstrap + mode_settopswapsize + mode_newlayout + mode_spifreq + mode_em100 +
|
||||
mode_locked + mode_unlocked + mode_density + mode_altmedisable +
|
||||
@@ -191,7 +191,7 @@ index 0b75db54bd..7f0c10bd0b 100644
|
||||
fprintf(stderr, "You need to specify a mode.\n\n");
|
||||
fprintf(stderr, "run '%s -h' for usage\n", argv[0]);
|
||||
exit(EXIT_FAILURE);
|
||||
@@ -2758,6 +2806,10 @@ int main(int argc, char *argv[])
|
||||
@@ -2746,6 +2794,10 @@ int main(int argc, char *argv[])
|
||||
write_image(new_filename, image, size);
|
||||
}
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From e4682c184ded28dc9daf7ae6cae9d121f3803bef Mon Sep 17 00:00:00 2001
|
||||
From 91e4334541da6522d5a0bf5277ac478c891e7117 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sat, 6 May 2023 15:53:41 -0600
|
||||
Subject: [PATCH 07/51] mb/dell/e6400: Enable 01.0 device in devicetree for
|
||||
Subject: [PATCH 06/48] mb/dell/e6400: Enable 01.0 device in devicetree for
|
||||
dGPU models
|
||||
|
||||
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 83a4706b4948797ff57f314c9518f256aea08e79 Mon Sep 17 00:00:00 2001
|
||||
From 3ebe9e03ec563e5adb43337340fe973aa66a984a Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Fri, 12 May 2023 19:55:15 -0600
|
||||
Subject: [PATCH 08/51] Remove warning for coreboot images built without a
|
||||
Subject: [PATCH 07/48] Remove warning for coreboot images built without a
|
||||
payload
|
||||
|
||||
I added this in upstream to prevent people from accidentally flashing
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
From 9dbbefa5297329f316adeb95c2a78267be146509 Mon Sep 17 00:00:00 2001
|
||||
From 0e2fa472354b2e68ffbfc01d5bb225ca9d8973f0 Mon Sep 17 00:00:00 2001
|
||||
From: Alper Nebi Yasak <alpernebiyasak@gmail.com>
|
||||
Date: Thu, 22 Jun 2023 16:44:27 +0300
|
||||
Subject: [PATCH 09/51] HACK: Disable coreboot related BL31 features
|
||||
Subject: [PATCH 08/48] HACK: Disable coreboot related BL31 features
|
||||
|
||||
I don't know why, but removing this BL31 make argument lets gru-kevin
|
||||
power off properly when shut down from Linux. Needs investigation.
|
||||
@@ -10,10 +10,10 @@ power off properly when shut down from Linux. Needs investigation.
|
||||
1 file changed, 3 deletions(-)
|
||||
|
||||
diff --git a/src/arch/arm64/Makefile.mk b/src/arch/arm64/Makefile.mk
|
||||
index 7310ce1c1f..b0a6ed1f84 100644
|
||||
index efd628fee7..6c4f3d702e 100644
|
||||
--- a/src/arch/arm64/Makefile.mk
|
||||
+++ b/src/arch/arm64/Makefile.mk
|
||||
@@ -158,9 +158,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
|
||||
@@ -156,9 +156,6 @@ BL31_MAKEARGS += LOG_LEVEL=40
|
||||
# Always enable crash reporting, even on a release build
|
||||
BL31_MAKEARGS += CRASH_REPORTING=1
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 6b112300df5d4538cf19e3f914f0a44628733204 Mon Sep 17 00:00:00 2001
|
||||
From f692cd96a4484b8e60bd112454d1bdbc3c689017 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 5 Nov 2023 11:41:41 +0000
|
||||
Subject: [PATCH 10/51] dell/e6430: use ME Soft Temporary Disable
|
||||
Subject: [PATCH 09/48] dell/e6430: use ME Soft Temporary Disable
|
||||
|
||||
i overlooked this. it's set on other boards.
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 42e64e41ec9ce997f6615b7a67655715a67651b4 Mon Sep 17 00:00:00 2001
|
||||
From 78db6c595ff816ad4344d541688605ae720a83c4 Mon Sep 17 00:00:00 2001
|
||||
From: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
Date: Sat, 23 Dec 2023 19:02:10 +0200
|
||||
Subject: [PATCH 11/51] mb/hp: Add Compaq Elite 8300 CMT port
|
||||
Subject: [PATCH 10/48] mb/hp: Add Compaq Elite 8300 CMT port
|
||||
|
||||
Based on autoport and Z220 SuperIO code.
|
||||
|
||||
+26
-39
@@ -1,7 +1,7 @@
|
||||
From 601661d628ff7b8ffee8c1ed13307caa23d489ce Mon Sep 17 00:00:00 2001
|
||||
From beb9b1650fb3aec96544b683fbe53ee16584f3d8 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 2 Mar 2024 22:51:09 +0000
|
||||
Subject: [PATCH 12/51] nb/intel/haswell: make IOMMU a runtime option
|
||||
Subject: [PATCH 11/48] nb/intel/haswell: make IOMMU a runtime option
|
||||
|
||||
When I tested graphics cards on a coreboot port for Dell
|
||||
OptiPlex 9020 SFF, I could not use a graphics card unless
|
||||
@@ -19,23 +19,23 @@ performed, and the IOMMU will be left disabled. This option
|
||||
has been added to all current Haswell boards, though it is
|
||||
recommended to leave the IOMMU turned on in most setups.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/mainboard/asrock/b85m_pro4/cmos.default | 1 +
|
||||
src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++
|
||||
src/mainboard/asrock/h81m-hds/cmos.default | 1 +
|
||||
src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 1 +
|
||||
src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++
|
||||
src/mainboard/google/beltino/cmos.layout | 5 +++++
|
||||
src/mainboard/google/slippy/cmos.layout | 5 +++++
|
||||
src/mainboard/intel/baskingridge/cmos.layout | 4 ++++
|
||||
src/mainboard/lenovo/haswell/cmos.default | 1 +
|
||||
src/mainboard/lenovo/haswell/cmos.layout | 3 +++
|
||||
src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
|
||||
src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++
|
||||
src/northbridge/intel/haswell/early_init.c | 15 ++++++++++-----
|
||||
14 files changed, 53 insertions(+), 5 deletions(-)
|
||||
src/mainboard/asrock/b85m_pro4/cmos.default | 1 +
|
||||
src/mainboard/asrock/b85m_pro4/cmos.layout | 3 +++
|
||||
src/mainboard/asrock/h81m-hds/cmos.default | 1 +
|
||||
src/mainboard/asrock/h81m-hds/cmos.layout | 6 ++++++
|
||||
src/mainboard/dell/optiplex_9020/cmos.default | 1 +
|
||||
src/mainboard/dell/optiplex_9020/cmos.layout | 6 ++++++
|
||||
src/mainboard/google/beltino/cmos.layout | 5 +++++
|
||||
src/mainboard/google/slippy/cmos.layout | 5 +++++
|
||||
src/mainboard/intel/baskingridge/cmos.layout | 4 ++++
|
||||
src/mainboard/lenovo/haswell/cmos.default | 1 +
|
||||
src/mainboard/lenovo/haswell/cmos.layout | 3 +++
|
||||
src/mainboard/supermicro/x10slm-f/cmos.default | 1 +
|
||||
src/mainboard/supermicro/x10slm-f/cmos.layout | 6 ++++++
|
||||
src/northbridge/intel/haswell/early_init.c | 5 +++++
|
||||
14 files changed, 48 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/asrock/b85m_pro4/cmos.default b/src/mainboard/asrock/b85m_pro4/cmos.default
|
||||
index 01bf20ad16..dfc8b80fb0 100644
|
||||
@@ -265,41 +265,28 @@ index 38ba87aa45..24d39e97ee 100644
|
||||
checksums
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
|
||||
index 6a5ce53a40..e0007f72ee 100644
|
||||
index e47deb5da6..1a7e0b1076 100644
|
||||
--- a/src/northbridge/intel/haswell/early_init.c
|
||||
+++ b/src/northbridge/intel/haswell/early_init.c
|
||||
@@ -6,6 +6,7 @@
|
||||
@@ -5,6 +5,7 @@
|
||||
#include <device/mmio.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <types.h>
|
||||
+#include <option.h>
|
||||
|
||||
#include "haswell.h"
|
||||
|
||||
@@ -80,14 +81,18 @@ static void haswell_setup_misc(void)
|
||||
static void northbridge_setup_iommu(void)
|
||||
@@ -157,6 +158,10 @@ static void haswell_setup_misc(void)
|
||||
static void haswell_setup_iommu(void)
|
||||
{
|
||||
const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
|
||||
+ u8 enable_iommu = get_uint_option("iommu", 1);
|
||||
+
|
||||
+ if (!enable_iommu)
|
||||
+ return;
|
||||
|
||||
if (capid0_a & VTD_DISABLE)
|
||||
return;
|
||||
|
||||
- /* Setup BARs: zeroize top 32 bits; set enable bit */
|
||||
- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
|
||||
- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
|
||||
- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
|
||||
- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
|
||||
+ if (enable_iommu) {
|
||||
+ /* Setup BARs: zeroize top 32 bits; set enable bit */
|
||||
+ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
|
||||
+ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
|
||||
+ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
|
||||
+ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
|
||||
+ }
|
||||
|
||||
if (cpu_is_haswell()) {
|
||||
/*
|
||||
--
|
||||
2.47.3
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 1586b045a75b9cf8cd68a44739beefa501e6cbd3 Mon Sep 17 00:00:00 2001
|
||||
From 0f76a919522c9624c2b5df2a9c17525ab21bd6b9 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 2 Mar 2024 23:00:09 +0000
|
||||
Subject: [PATCH 13/51] dell/optiplex_9020: Disable IOMMU by default
|
||||
Subject: [PATCH 12/48] dell/optiplex_9020: Disable IOMMU by default
|
||||
|
||||
Needed to make graphics cards work. Turning it on is
|
||||
recommended if only using iGPU, otherwise leave it off
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
From 64e0140fec07d7062b147419781e200509c63053 Mon Sep 17 00:00:00 2001
|
||||
From df64f2825157226b98e002e746114e25b0047438 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 6 Apr 2024 01:22:47 +0100
|
||||
Subject: [PATCH 14/51] nb/haswell: Fully disable iGPU when dGPU is used
|
||||
Subject: [PATCH 13/48] nb/haswell: Fully disable iGPU when dGPU is used
|
||||
|
||||
My earlier patch disabled decode *and* disabled the iGPU itself, but
|
||||
a subsequent revision disabled only VGA decode. Upon revisiting, I
|
||||
@@ -33,10 +33,10 @@ Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
1 file changed, 3 insertions(+)
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
|
||||
index fc44a98a57..451147d082 100644
|
||||
index f7fad3183d..1b188e92e1 100644
|
||||
--- a/src/northbridge/intel/haswell/gma.c
|
||||
+++ b/src/northbridge/intel/haswell/gma.c
|
||||
@@ -655,6 +655,9 @@ static void gma_func0_disable(struct device *dev)
|
||||
@@ -466,6 +466,9 @@ static void gma_func0_disable(struct device *dev)
|
||||
{
|
||||
/* Disable VGA decode */
|
||||
pci_or_config16(pcidev_on_root(0, 0), GGC, 1 << 1);
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From f19a3eb6eee94881ac1c6c6fe28c1f523a12dcda Mon Sep 17 00:00:00 2001
|
||||
From fdf4774a6e80b1f94079abb346049113dfbf5241 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Fri, 3 May 2024 11:03:32 -0600
|
||||
Subject: [PATCH 15/51] ec/dell/mec5035: Add S3 suspend SMI handler
|
||||
Subject: [PATCH 14/48] ec/dell/mec5035: Add S3 suspend SMI handler
|
||||
|
||||
This is necessary for S3 resume to work on SNB and newer Dell Latitude
|
||||
laptops. If a command isn't sent, the EC cuts power to the DIMMs,
|
||||
+55
@@ -0,0 +1,55 @@
|
||||
From 18216387e5c40ec3c80c63ec25e9b0c55a009cff Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Sat, 4 May 2024 02:00:53 +0100
|
||||
Subject: [PATCH 15/48] nb/haswell: lock policy regs when disabling IOMMU
|
||||
|
||||
Angel Pons told me I should do it. See comments here:
|
||||
https://review.coreboot.org/c/coreboot/+/81016
|
||||
|
||||
I see no harm in complying with the request. I'll merge
|
||||
this into the main patch at a later date and try to
|
||||
get this upstreamed.
|
||||
|
||||
Just a reminder: on Optiplex 9020 variants, Xorg locks up
|
||||
under Linux when tested with a graphics card; disabling
|
||||
IOMMU works around the issue. Intel graphics work just fine
|
||||
with IOMMU turned on. Libreboot disables IOMMU by default,
|
||||
on the 9020, so that users can install graphics cards easily.
|
||||
|
||||
Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
---
|
||||
src/northbridge/intel/haswell/early_init.c | 15 +++++++--------
|
||||
1 file changed, 7 insertions(+), 8 deletions(-)
|
||||
|
||||
diff --git a/src/northbridge/intel/haswell/early_init.c b/src/northbridge/intel/haswell/early_init.c
|
||||
index 1a7e0b1076..e9506ee830 100644
|
||||
--- a/src/northbridge/intel/haswell/early_init.c
|
||||
+++ b/src/northbridge/intel/haswell/early_init.c
|
||||
@@ -160,17 +160,16 @@ static void haswell_setup_iommu(void)
|
||||
const u32 capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
|
||||
u8 enable_iommu = get_uint_option("iommu", 1);
|
||||
|
||||
- if (!enable_iommu)
|
||||
- return;
|
||||
-
|
||||
if (capid0_a & VTD_DISABLE)
|
||||
return;
|
||||
|
||||
- /* Setup BARs: zeroize top 32 bits; set enable bit */
|
||||
- mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
|
||||
- mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
|
||||
- mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
|
||||
- mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
|
||||
+ if (enable_iommu) {
|
||||
+ /* Setup BARs: zeroize top 32 bits; set enable bit */
|
||||
+ mchbar_write32(GFXVTBAR + 4, GFXVT_BASE_ADDRESS >> 32);
|
||||
+ mchbar_write32(GFXVTBAR + 0, GFXVT_BASE_ADDRESS | 1);
|
||||
+ mchbar_write32(VTVC0BAR + 4, VTVC0_BASE_ADDRESS >> 32);
|
||||
+ mchbar_write32(VTVC0BAR + 0, VTVC0_BASE_ADDRESS | 1);
|
||||
+ }
|
||||
|
||||
/* Set L3HIT2PEND_DIS, lock GFXVTBAR policy config registers */
|
||||
u32 reg32;
|
||||
--
|
||||
2.47.3
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From c99ef7e409f450dbc66d2de930160f29a0c0d68e Mon Sep 17 00:00:00 2001
|
||||
From d797b9d19c6bc3224897000756caef29e98dd266 Mon Sep 17 00:00:00 2001
|
||||
From: Angel Pons <th3fanbus@gmail.com>
|
||||
Date: Mon, 10 May 2021 22:40:59 +0200
|
||||
Subject: [PATCH 16/51] nb/intel/gm45: Make DDR2 raminit work
|
||||
Subject: [PATCH 16/48] nb/intel/gm45: Make DDR2 raminit work
|
||||
|
||||
List of changes:
|
||||
- Update some timing and ODT values
|
||||
@@ -20,7 +20,7 @@ Signed-off-by: Angel Pons <th3fanbus@gmail.com>
|
||||
3 files changed, 106 insertions(+), 13 deletions(-)
|
||||
|
||||
diff --git a/src/northbridge/intel/gm45/gm45.h b/src/northbridge/intel/gm45/gm45.h
|
||||
index 90ab570524..d537ef82af 100644
|
||||
index f68bfdee7a..b76117bc3a 100644
|
||||
--- a/src/northbridge/intel/gm45/gm45.h
|
||||
+++ b/src/northbridge/intel/gm45/gm45.h
|
||||
@@ -420,7 +420,7 @@ void igd_compute_ggc(sysinfo_t *const sysinfo);
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From fcfd8484d5b7a50c170a7f5cc8a973c890e48afc Mon Sep 17 00:00:00 2001
|
||||
From e573065ac900d4decfd4dbd0a1464d82501ac3c5 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Tue, 6 Aug 2024 00:50:24 +0100
|
||||
Subject: [PATCH 17/51] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
|
||||
Subject: [PATCH 17/48] nb/gm45: Fix Angel's DDR2 RCOMP fix on DDR3 boards
|
||||
|
||||
We add this patch:
|
||||
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 499885b662b703c472309f64c123d99e65ebe9d2 Mon Sep 17 00:00:00 2001
|
||||
From 130a5ca25fbedb58e49b613e4a7cece715b545ae Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Mon, 20 May 2024 10:24:16 -0600
|
||||
Subject: [PATCH 18/51] mb/dell/e6400: Use 100 MHz reference clock for display
|
||||
Subject: [PATCH 18/48] mb/dell/e6400: Use 100 MHz reference clock for display
|
||||
|
||||
The E6400 uses a 100 MHz reference clock for spread spectrum support on
|
||||
LVDS, whereas libgfxinit previously assumed a 96 MHz input clock. For
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From db3148d6762fb16ca79d9bfb3df51210e04a580e Mon Sep 17 00:00:00 2001
|
||||
From 7641a4b9b91c385223026cd566e0ffc2a2aa0d8f Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Mon, 12 Aug 2024 02:15:24 +0100
|
||||
Subject: [PATCH 19/51] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
|
||||
Subject: [PATCH 19/48] nb/x4x: define INTEL_GMA_DPLL_REF_FREQ
|
||||
|
||||
set it to 96MHz. fixes the following build error when
|
||||
building for x4x boards e.g. gigabyte ga-g41m-es2l:
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From da070b56c01b5ffe35d8dfdac2e7681be5392fc2 Mon Sep 17 00:00:00 2001
|
||||
From 36126c093a9b9e01d41f0a68977cd09070c3c276 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Thu, 26 Sep 2024 19:51:25 -0600
|
||||
Subject: [PATCH 20/51] mb/dell/gm45_latitudes: Add E4300 variant
|
||||
Subject: [PATCH 20/48] mb/dell/gm45_latitudes: Add E4300 variant
|
||||
|
||||
Change-Id: I0f2059501b11be103187e3ce1a7c04ab85ae63d2
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 78cf7a8186ad389f6402da9e55f94830f368fcea Mon Sep 17 00:00:00 2001
|
||||
From 4caca6e6e349fa1913df622081025ea53bfd136f Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Fri, 3 May 2024 16:31:12 -0600
|
||||
Subject: [PATCH 21/51] mb/dell: Add S3 SMI handler for Dell Latitudes
|
||||
Subject: [PATCH 21/48] mb/dell: Add S3 SMI handler for Dell Latitudes
|
||||
|
||||
Integrate the previously added mec5035_smi_sleep() function into
|
||||
mainboard code to fix S3 suspend on the SNB/IVB Latitudes and the E7240.
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From 7f131cd791eb2dcf68f0e1e9049cc5b4c301232b Mon Sep 17 00:00:00 2001
|
||||
From 669ef0d2c72326134f64a4fe70f67220ec690c5e Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Tue, 31 Dec 2024 14:42:24 +0000
|
||||
Subject: [PATCH 22/51] Disable compression on refcode insertion
|
||||
Subject: [PATCH 22/48] Disable compression on refcode insertion
|
||||
|
||||
Compression is not reliably reproducible. In an lbmk release
|
||||
context, this means we cannot rely on vendorfile insertion.
|
||||
@@ -14,10 +14,10 @@ Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/Makefile.mk b/Makefile.mk
|
||||
index dbad313911..8f541ad187 100644
|
||||
index 5fccb4a52d..c40e06c453 100644
|
||||
--- a/Makefile.mk
|
||||
+++ b/Makefile.mk
|
||||
@@ -1432,7 +1432,7 @@ endif
|
||||
@@ -1414,7 +1414,7 @@ endif
|
||||
cbfs-files-$(CONFIG_HAVE_REFCODE_BLOB) += $(CONFIG_CBFS_PREFIX)/refcode
|
||||
$(CONFIG_CBFS_PREFIX)/refcode-file := $(REFCODE_BLOB)
|
||||
$(CONFIG_CBFS_PREFIX)/refcode-type := stage
|
||||
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
From 0ef9596d987ae2f9d5d63f7961b60e7d05529d1b Mon Sep 17 00:00:00 2001
|
||||
From c7b136f1f4fa2bc1a783711b5a1ee82c5d9ce69f Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 21 Apr 2025 02:58:47 +0100
|
||||
Subject: [PATCH 23/51] nb/intel/*: Disable stack overflow debug options
|
||||
Subject: [PATCH 23/48] nb/intel/*: Disable stack overflow debug options
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
@@ -52,10 +52,10 @@ index 35e89b0c88..c5456d0ddf 100644
|
||||
+
|
||||
endif
|
||||
diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig
|
||||
index d67cc14660..fa22e35ccb 100644
|
||||
index c57f1ec380..0a5181b183 100644
|
||||
--- a/src/northbridge/intel/haswell/Kconfig
|
||||
+++ b/src/northbridge/intel/haswell/Kconfig
|
||||
@@ -9,6 +9,15 @@ config NORTHBRIDGE_INTEL_HASWELL
|
||||
@@ -10,6 +10,15 @@ config NORTHBRIDGE_INTEL_HASWELL
|
||||
|
||||
if NORTHBRIDGE_INTEL_HASWELL
|
||||
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From 57f57075c69ce6e1caf9d0daf991b1f373d7f04b Mon Sep 17 00:00:00 2001
|
||||
From c15a0ef9b964e9df9a5578ed271af4f1c0419f38 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Mon, 30 Sep 2024 20:44:38 -0400
|
||||
Subject: [PATCH 24/51] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
|
||||
Subject: [PATCH 24/48] mb/dell: Add Optiplex 780 MT (x4x/ICH10)
|
||||
|
||||
Change-Id: Idb45737ce95bfd26e978323c650de7d308b5079c
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From e1ed4a9739d2cfc691d71c165d984ef171a2ea76 Mon Sep 17 00:00:00 2001
|
||||
From bfd5f6628a69d8704a84b30c4027149fe1b21efa Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Wed, 30 Oct 2024 20:55:25 -0600
|
||||
Subject: [PATCH 25/51] mb/dell/optiplex_780: Add USFF variant
|
||||
Subject: [PATCH 25/48] mb/dell/optiplex_780: Add USFF variant
|
||||
|
||||
Change-Id: I3aa21c743749f4a11a2501f4c121316bd2f1a103
|
||||
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 55a33798ec9aadd38222f736d4c1b77f9902f3f4 Mon Sep 17 00:00:00 2001
|
||||
From 82f47133c20abc720f5d5fa8a54be465ebd95f28 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 6 Jan 2025 01:53:53 +0000
|
||||
Subject: [PATCH 26/51] src/intel/x4x: Disable stack overflow debug
|
||||
Subject: [PATCH 26/48] src/intel/x4x: Disable stack overflow debug
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 56a581aeadb4efafc62efaba742b06b25852ccf8 Mon Sep 17 00:00:00 2001
|
||||
From 5c4439fb513c315ef3effff19146b331c492fa9b Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Tue, 22 Apr 2025 10:21:59 +0100
|
||||
Subject: [PATCH 27/51] hp/8300cmt: remove xhci_overcurrent_mapping
|
||||
Subject: [PATCH 27/48] hp/8300cmt: remove xhci_overcurrent_mapping
|
||||
|
||||
No longer needed, as per the following commit:
|
||||
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From 4470d8fb6760173090c43e6a82a8865f5917dd9b Mon Sep 17 00:00:00 2001
|
||||
From 71ec1f7a6480e72b77a567f8cc0c2673a5e7905f Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Wed, 11 Dec 2024 01:06:01 +0000
|
||||
Subject: [PATCH 28/51] dell/3050micro: disable nvme hotplug
|
||||
Subject: [PATCH 28/48] dell/3050micro: disable nvme hotplug
|
||||
|
||||
in my testing, when running my 3050micro for a few days,
|
||||
the nvme would sometimes randomly rename.
|
||||
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
From f6b82e0483d7f9e47f465bb4884b199cfd9fe04b Mon Sep 17 00:00:00 2001
|
||||
From 95a0af0eea56e1bddcb243ed135835448b90fa56 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 6 Jan 2025 01:36:23 +0000
|
||||
Subject: [PATCH 29/51] src/intel/skylake: Disable stack overflow debug options
|
||||
Subject: [PATCH 29/48] src/intel/skylake: Disable stack overflow debug options
|
||||
|
||||
The option was appearing in T480/3050micro configs of lbmk,
|
||||
after updating on the coreboot/next uprev for 20241206 rev8:
|
||||
@@ -37,10 +37,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
|
||||
index c76239936a..f8ff8cfa7a 100644
|
||||
index 7c530f2c75..70c2a7643c 100644
|
||||
--- a/src/soc/intel/skylake/Kconfig
|
||||
+++ b/src/soc/intel/skylake/Kconfig
|
||||
@@ -136,6 +136,15 @@ config DCACHE_RAM_SIZE
|
||||
@@ -131,6 +131,15 @@ config DCACHE_RAM_SIZE
|
||||
The size of the cache-as-ram region required during bootblock
|
||||
and/or romstage.
|
||||
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From 025eae54ed31b728866db1279a7cd86d7280dc58 Mon Sep 17 00:00:00 2001
|
||||
From 7d94457ba0e2be10d781c5fd0659d895c9b558b1 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Thu, 26 Dec 2024 19:45:20 +0000
|
||||
Subject: [PATCH 30/51] soc/intel/skylake: Don't compress FSP-S
|
||||
Subject: [PATCH 30/48] soc/intel/skylake: Don't compress FSP-S
|
||||
|
||||
Build systems like lbmk need to reproducibly insert
|
||||
certain vendor files on release images.
|
||||
@@ -19,10 +19,10 @@ Signed-off-by: Leah Rowe <info@minifree.org>
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
|
||||
index f8ff8cfa7a..97354cdaa5 100644
|
||||
index 70c2a7643c..a2854923e7 100644
|
||||
--- a/src/soc/intel/skylake/Kconfig
|
||||
+++ b/src/soc/intel/skylake/Kconfig
|
||||
@@ -15,7 +15,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
|
||||
@@ -14,7 +14,7 @@ config SOC_INTEL_COMMON_SKYLAKE_BASE
|
||||
select DRAM_SUPPORT_DDR4
|
||||
select DRIVERS_USB_ACPI
|
||||
select EDK2_CPU_TIMER_LIB if PAYLOAD_EDK2
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From ca198ab68579cee7297c3675b440c0fd78ed7511 Mon Sep 17 00:00:00 2001
|
||||
From 8768e53f3b2ceb00ec0c8abf0fc0af03993820b1 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <info@minifree.org>
|
||||
Date: Wed, 18 Dec 2024 02:06:18 +0000
|
||||
Subject: [PATCH 31/51] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
|
||||
Subject: [PATCH 31/48] lenovo: Add Kconfig option CONFIG_LENOVO_TBFW_BIN
|
||||
|
||||
This is used by lbmk to know where a tb.bin file goes,
|
||||
when extracting and padding TBT.bin from Lenovo ThunderBolt
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From cb3b76b4805886d5afc5846d351a292639b91bc6 Mon Sep 17 00:00:00 2001
|
||||
From 579c60fd77517497eb18dfeca8d73cdca94c15da Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 21 Apr 2025 05:14:45 +0100
|
||||
Subject: [PATCH 32/51] Conditional TBFW setting for kabylake thinkpads
|
||||
Subject: [PATCH 32/48] Conditional TBFW setting for kabylake thinkpads
|
||||
|
||||
Otherwise, other boards will define it, which
|
||||
might trigger the vendor download script, and
|
||||
|
||||
+3
-3
@@ -1,7 +1,7 @@
|
||||
From bb04b8f8db08f06100f801ddeb076f165c3d503a Mon Sep 17 00:00:00 2001
|
||||
From 23d8a97ff213f744b4e6333d92fc90e9ea97e879 Mon Sep 17 00:00:00 2001
|
||||
From: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
Date: Sat, 27 Sep 2025 23:30:46 +0300
|
||||
Subject: [PATCH 33/51] soc/intel/alderlake: Disable
|
||||
Subject: [PATCH 33/48] soc/intel/alderlake: Disable
|
||||
MRC_CACHE_USING_MRC_VERSION
|
||||
|
||||
There's some issue with building against the FSP headers in src/vendorcode.
|
||||
@@ -14,7 +14,7 @@ Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
|
||||
1 file changed, 1 deletion(-)
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index 334ea26e5b..0f1404ea49 100644
|
||||
index 34c9baf544..e0ab6b10fd 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -36,7 +36,6 @@ config SOC_INTEL_ALDERLAKE
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From de90c8706495b73e24e362dd7c80f211581a2ad6 Mon Sep 17 00:00:00 2001
|
||||
From e2e070ab1f080c0ae59c43131faa57f3499fd813 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sun, 28 Sep 2025 03:17:50 +0100
|
||||
Subject: [PATCH 34/51] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks)
|
||||
Subject: [PATCH 34/48] Subject: [PATCH 1/1] Add a -p option (skip FPTR checks)
|
||||
|
||||
if you pass -k (keep fptr modules), don't use -r, don't
|
||||
use -t, you can essentially just use me_cleaner to
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From 9887eeeb89b29ca8483c9742733fd78ccd7e171b Mon Sep 17 00:00:00 2001
|
||||
From fee89a6c872ec26c2ea128ecdce62d6c3abe53f1 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sat, 4 Oct 2025 21:57:43 +0100
|
||||
Subject: [PATCH 35/51] soc/intel/alderlake: Don't compress FSP-S
|
||||
Subject: [PATCH 35/48] soc/intel/alderlake: Don't compress FSP-S
|
||||
|
||||
Build systems like lbmk need to reproducibly insert
|
||||
certain vendor files on release images.
|
||||
@@ -18,7 +18,7 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index 0f1404ea49..f78729a9c4 100644
|
||||
index e0ab6b10fd..a2e7cff6f6 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -16,7 +16,7 @@ config SOC_INTEL_ALDERLAKE
|
||||
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
From 1f62cd582614cb3739475dd4439e132b931c5619 Mon Sep 17 00:00:00 2001
|
||||
From abd26006eff71c9570bc90fdbce3a76f8f559cea Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sat, 4 Oct 2025 22:20:11 +0100
|
||||
Subject: [PATCH 36/51] alderlake: don't require full fsp repo for fd path
|
||||
Subject: [PATCH 36/48] alderlake: don't require full fsp repo for fd path
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
@@ -9,10 +9,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
1 file changed, 8 insertions(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index f78729a9c4..c05d06289e 100644
|
||||
index a2e7cff6f6..3402c1e3d5 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -442,7 +442,14 @@ config FSP_HEADER_PATH
|
||||
@@ -430,7 +430,14 @@ config FSP_HEADER_PATH
|
||||
|
||||
config FSP_FD_PATH
|
||||
string
|
||||
|
||||
+4
-4
@@ -1,7 +1,7 @@
|
||||
From 0af11ee58ae38a385431253b1f5f0e9dbce98d3d Mon Sep 17 00:00:00 2001
|
||||
From 6a4a79d82df982c2fca859101040e407623f519c Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Mon, 6 Oct 2025 04:47:06 +0100
|
||||
Subject: [PATCH 37/51] soc/alderlake: disable stack overflow debug option
|
||||
Subject: [PATCH 37/48] soc/alderlake: disable stack overflow debug option
|
||||
|
||||
same as on other boards. based on this commit:
|
||||
|
||||
@@ -22,10 +22,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
1 file changed, 9 insertions(+)
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index c05d06289e..acb87275d4 100644
|
||||
index 3402c1e3d5..06b9199e84 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -343,6 +343,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ
|
||||
@@ -331,6 +331,15 @@ config SOC_INTEL_UFS_CLK_FREQ_HZ
|
||||
int
|
||||
default 19200000
|
||||
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From f1369485a721aa4ed239f6a8c0b0ad1b82884c7b Mon Sep 17 00:00:00 2001
|
||||
From bb286d13cb7702e9396deab04023cc58dcc01a15 Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sun, 11 May 2025 15:41:22 -0600
|
||||
Subject: [PATCH 38/51] ec/dell/mec5035: Add command to disable EC-initiated
|
||||
Subject: [PATCH 38/48] ec/dell/mec5035: Add command to disable EC-initiated
|
||||
thermal shutdown
|
||||
|
||||
If command 0xBF isn't sent, the EC shuts down the system without warning
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 3e63073e195446ea3adef0e21f5369e7ef27494a Mon Sep 17 00:00:00 2001
|
||||
From a93c01173c2f88b4a09286740c030314040c39fc Mon Sep 17 00:00:00 2001
|
||||
From: Nicholas Chin <nic.c3.14@gmail.com>
|
||||
Date: Sun, 11 May 2025 16:28:23 -0600
|
||||
Subject: [PATCH 39/51] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown
|
||||
Subject: [PATCH 39/48] mb/dell/snb_ivb_latitude: Disable EC initiated shutdown
|
||||
at 87 degrees
|
||||
|
||||
If command 0xBF isn't sent, the EC will shut down the system without
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From f05e8514654cddb5041fa65a90ab5260ec55d1e5 Mon Sep 17 00:00:00 2001
|
||||
From dc4036353483c5fc0c140fc269d9bddb0bb7a967 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sat, 20 Dec 2025 20:12:48 +0100
|
||||
Subject: [PATCH 40/51] fix ifdtool build
|
||||
Subject: [PATCH 40/48] fix ifdtool build
|
||||
|
||||
not my mistake. someone messed up.
|
||||
|
||||
@@ -11,10 +11,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
|
||||
index 7f0c10bd0b..2a5365efe7 100644
|
||||
index cab934c3a5..d181888e0f 100644
|
||||
--- a/util/ifdtool/ifdtool.c
|
||||
+++ b/util/ifdtool/ifdtool.c
|
||||
@@ -2610,7 +2610,7 @@ int main(int argc, char *argv[])
|
||||
@@ -2598,7 +2598,7 @@ int main(int argc, char *argv[])
|
||||
}
|
||||
mode_nuke = 1;
|
||||
break;
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 76a1f9c12fedcd595b540168efdd9a8439be3bcd Mon Sep 17 00:00:00 2001
|
||||
From 5b7bbc6fcc6f737f259906f1919c1e28b6628a7e Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Sat, 20 Dec 2025 22:36:18 +0100
|
||||
Subject: [PATCH 41/51] tests/Makefile.mk: use 3rdparty/cmocka by default
|
||||
Subject: [PATCH 41/48] tests/Makefile.mk: use 3rdparty/cmocka by default
|
||||
|
||||
(tests)
|
||||
|
||||
|
||||
+2
-2
@@ -1,7 +1,7 @@
|
||||
From 942ef84be2203c6a784e5dd80a0e1caeb1d8c98c Mon Sep 17 00:00:00 2001
|
||||
From ecbf5a133d839b6c8579e384e9db0a036eca939d Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Tue, 23 Dec 2025 18:41:27 +0100
|
||||
Subject: [PATCH 42/51] mb/dell/optiplex_780: use legacy HDA verb table
|
||||
Subject: [PATCH 42/48] mb/dell/optiplex_780: use legacy HDA verb table
|
||||
|
||||
See:
|
||||
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From eb141cc6c1372b754fc1cbe9f1dad9aade066e70 Mon Sep 17 00:00:00 2001
|
||||
From 962bfe1366598145a93cf6a7ed0f78393e5e9ff7 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Tue, 23 Dec 2025 18:46:45 +0100
|
||||
Subject: [PATCH 43/51] hp8300cmt: use legacy verb table
|
||||
Subject: [PATCH 43/48] hp8300cmt: use legacy verb table
|
||||
|
||||
same as for the 780 optiplex patch
|
||||
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From 58f8869dbd58fb9bbb205b5b3bc37cc4ae58dd5b Mon Sep 17 00:00:00 2001
|
||||
From 88d29f792de89bb0a138e671432227cb5679b5ae Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Tue, 6 Jan 2026 21:42:21 +0000
|
||||
Subject: [PATCH 44/51] topton x2e n150: use old fsp
|
||||
Subject: [PATCH 44/48] topton x2e n150: use old fsp
|
||||
|
||||
i added the old fsp back, so that we didn't have to
|
||||
mess around with vendor files in lbmk, because coreboot
|
||||
@@ -18,10 +18,10 @@ Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
1 file changed, 1 insertion(+)
|
||||
|
||||
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig
|
||||
index acb87275d4..6f1e8b9107 100644
|
||||
index 06b9199e84..f260d10285 100644
|
||||
--- a/src/soc/intel/alderlake/Kconfig
|
||||
+++ b/src/soc/intel/alderlake/Kconfig
|
||||
@@ -463,6 +463,7 @@ config FSP_FD_PATH
|
||||
@@ -451,6 +451,7 @@ config FSP_FD_PATH
|
||||
default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S
|
||||
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P
|
||||
default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S
|
||||
|
||||
+3
-3
@@ -1,7 +1,7 @@
|
||||
From c4a5a3f5d01e8947c168cf5cf22755cba3cdf2fa Mon Sep 17 00:00:00 2001
|
||||
From 5b52abaa8529f7493f9d4ecf402e9ee130f4f8d2 Mon Sep 17 00:00:00 2001
|
||||
From: Ron Nazarov <ron@noisytoot.org>
|
||||
Date: Sat, 14 Feb 2026 20:13:01 +0000
|
||||
Subject: [PATCH 45/51] mb/supermicro/x11-lga1151-series: Disable ME HECI in
|
||||
Subject: [PATCH 45/48] mb/supermicro/x11-lga1151-series: Disable ME HECI in
|
||||
devicetree
|
||||
|
||||
Since we always use me_cleaner, this speeds up boot time by preventing
|
||||
@@ -14,7 +14,7 @@ Signed-off-by: Ron Nazarov <ron@noisytoot.org>
|
||||
1 file changed, 1 insertion(+), 1 deletion(-)
|
||||
|
||||
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
|
||||
index d25288420f..edbb485969 100644
|
||||
index fbf896c6ae..aa09a41f2f 100644
|
||||
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
|
||||
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
|
||||
@@ -15,7 +15,7 @@ chip soc/intel/skylake
|
||||
|
||||
+9
-17
@@ -1,15 +1,15 @@
|
||||
From 763c811b82b631ab85e64e150ec70df76b57fd91 Mon Sep 17 00:00:00 2001
|
||||
From b9cc1be6f9d591dbc4f73b1448f8fce5ea20a0b4 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Fri, 20 Feb 2026 01:23:32 +0000
|
||||
Subject: [PATCH 46/51] util/ifdtool: option to allow region override
|
||||
Subject: [PATCH 46/48] util/ifdtool: option to allow region override
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
util/ifdtool/ifdtool.c | 13 +++++++++++--
|
||||
1 file changed, 11 insertions(+), 2 deletions(-)
|
||||
util/ifdtool/ifdtool.c | 12 ++++++++++--
|
||||
1 file changed, 10 insertions(+), 2 deletions(-)
|
||||
|
||||
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
|
||||
index 2a5365efe7..c5c3570e6a 100644
|
||||
index d181888e0f..dfefe316a9 100644
|
||||
--- a/util/ifdtool/ifdtool.c
|
||||
+++ b/util/ifdtool/ifdtool.c
|
||||
@@ -78,6 +78,8 @@ static unsigned int max_regions = 0;
|
||||
@@ -21,7 +21,7 @@ index 2a5365efe7..c5c3570e6a 100644
|
||||
static const struct region_name region_names[MAX_REGIONS] = {
|
||||
{ "Flash Descriptor", "fd", "flashregion_0_flashdescriptor.bin", "SI_DESC" },
|
||||
{ "BIOS", "bios", "flashregion_1_bios.bin", "SI_BIOS" },
|
||||
@@ -2094,7 +2096,9 @@ static void new_layout(const char *filename, char *image, int size,
|
||||
@@ -2093,7 +2095,9 @@ static void new_layout(const char *filename, char *image, int size,
|
||||
}
|
||||
|
||||
for (j = i + 1; j < max_regions; j++) {
|
||||
@@ -29,18 +29,10 @@ index 2a5365efe7..c5c3570e6a 100644
|
||||
+ if (ignore_region_override) {
|
||||
+ printf("Ignoring region overlap by user's will.\n");
|
||||
+ } else if (regions_collide(&new_regions[i], &new_regions[j])) {
|
||||
fprintf(stderr, "Regions would overlap:\n");
|
||||
|
||||
/* See which string is longer and make sure we pad the shorter one */
|
||||
@@ -2107,6 +2111,7 @@ static void new_layout(const char *filename, char *image, int size,
|
||||
new_regions[i].base, new_regions[i].limit);
|
||||
fprintf(stderr, " %*s : %x-%x\n", padding, region_name(j),
|
||||
new_regions[j].base, new_regions[j].limit);
|
||||
+
|
||||
fprintf(stderr, "Regions would overlap.\n");
|
||||
exit(EXIT_FAILURE);
|
||||
}
|
||||
}
|
||||
@@ -2363,10 +2368,11 @@ int main(int argc, char *argv[])
|
||||
@@ -2351,10 +2355,11 @@ int main(int argc, char *argv[])
|
||||
{"newvalue", 1, NULL, 'V'},
|
||||
{"topswapsize", 1, NULL, 'T'},
|
||||
{"nuke", 1, NULL, 'N'},
|
||||
@@ -53,7 +45,7 @@ index 2a5365efe7..c5c3570e6a 100644
|
||||
long_options, &option_index)) != EOF) {
|
||||
switch (opt) {
|
||||
case 'd':
|
||||
@@ -2610,6 +2616,9 @@ int main(int argc, char *argv[])
|
||||
@@ -2598,6 +2603,9 @@ int main(int argc, char *argv[])
|
||||
}
|
||||
mode_nuke = 1;
|
||||
break;
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
From 3e12bbbac3b15803de4053f8983dc908029832ac Mon Sep 17 00:00:00 2001
|
||||
From 1bc6028bf88ca6306ad89fc17fa6f31b9788b248 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Fri, 20 Feb 2026 19:31:19 +0000
|
||||
Subject: [PATCH 47/51] me_cleaner: don't modify if -k is used
|
||||
Subject: [PATCH 47/48] me_cleaner: don't modify if -k is used
|
||||
|
||||
don't remove *anything*. in libreboot, we only
|
||||
ever use -k when we werely want to extract the
|
||||
|
||||
+6
-6
@@ -1,7 +1,7 @@
|
||||
From 6f301fe881df4ed8759bf5b16d59d530798fee30 Mon Sep 17 00:00:00 2001
|
||||
From f5f73c2539e05cf85bf5eec795e4f91da50838ba Mon Sep 17 00:00:00 2001
|
||||
From: Kat Inskip <kat@inskip.me>
|
||||
Date: Tue, 17 Feb 2026 16:18:15 -0800
|
||||
Subject: [PATCH 48/51] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant
|
||||
Subject: [PATCH 48/48] mb/lenovo/sklkbl: Add Lenovo Thinkpad X270 as a variant
|
||||
|
||||
This machine is somewhat dissimilar from the X280 in the PCIe allocations in the overridetree. It also lacks soldered RAM, having a single SODIMM slot.
|
||||
|
||||
@@ -28,10 +28,10 @@ An untested variety allowing for a Skylake CPU (for 20K5 and 20K6) has been incl
|
||||
create mode 100644 src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/overridetree.cb
|
||||
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
|
||||
index 9d4b5f4965..1aaef40a0c 100644
|
||||
index b7cc705699..5945fe7b99 100644
|
||||
--- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
|
||||
+++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig
|
||||
@@ -59,6 +59,16 @@ config BOARD_LENOVO_X280
|
||||
@@ -58,6 +58,16 @@ config BOARD_LENOVO_X280
|
||||
select SOC_INTEL_KABYLAKE
|
||||
select HAVE_SPD_IN_CBFS
|
||||
|
||||
@@ -48,7 +48,7 @@ index 9d4b5f4965..1aaef40a0c 100644
|
||||
if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
|
||||
|
||||
config MAINBOARD_DIR
|
||||
@@ -70,6 +80,8 @@ config VARIANT_DIR
|
||||
@@ -69,6 +79,8 @@ config VARIANT_DIR
|
||||
default "t480s" if BOARD_LENOVO_T480S
|
||||
default "t580" if BOARD_LENOVO_T580
|
||||
default "x280" if BOARD_LENOVO_X280
|
||||
@@ -57,7 +57,7 @@ index 9d4b5f4965..1aaef40a0c 100644
|
||||
|
||||
config OVERRIDE_DEVICETREE
|
||||
default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
|
||||
@@ -80,6 +92,8 @@ config MAINBOARD_PART_NUMBER
|
||||
@@ -79,6 +91,8 @@ config MAINBOARD_PART_NUMBER
|
||||
default "T480s" if BOARD_LENOVO_T480S
|
||||
default "T580" if BOARD_LENOVO_T580
|
||||
default "X280" if BOARD_LENOVO_X280
|
||||
|
||||
+32
-29
@@ -1,7 +1,7 @@
|
||||
From 4557102ed2f7e1355cc3a331c6452884458b7a5e Mon Sep 17 00:00:00 2001
|
||||
From 9d39437b9447ab6e6164440bddf459111bd4903f Mon Sep 17 00:00:00 2001
|
||||
From: Kat Inskip <kat@inskip.me>
|
||||
Date: Sat, 21 Feb 2026 19:48:17 +0000
|
||||
Subject: [PATCH 49/51] mb/lenovo/x270: Provide correct vbt and hda_verb
|
||||
Subject: [PATCH] mb/lenovo/x270: Provide correct vbt and hda_verb
|
||||
|
||||
---
|
||||
.../sklkbl_thinkpad/variants/x270/data.vbt | Bin 6144 -> 4449 bytes
|
||||
@@ -12,34 +12,37 @@ diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/data.vbt b/src/m
|
||||
index bfb312850e0ab4ea834c535df35edb45834ed248..c6561a9c57e4e600bc0adb5f6679f2f5d6b6c640 100644
|
||||
GIT binary patch
|
||||
delta 1043
|
||||
zcmcgq-Afcv6hC)nXFtw-?CgzfEwH0L<XY;iA6b&MqFA;<TNWfjpGpWJ1oe;wyAeeY
|
||||
zMcY(Q_7B)gu#XWD5&2>gQ9&f-Qz1ka^prZC-JMFP=YHJZ{oQls$2s?7a?V`MjktC+
|
||||
zmIBAkE35L3T{R08;KY{a0fvRBG?I>!>>E2ha<Xn;f(Fw0W827aDAP^J*2b1rqGVGu
|
||||
z4=35iOQ$2bxub1s{!x>F{QO$c=4v8Y8%=?LrDlLIKmZ^Gf5CQN1XgElP&$RejtyZ5
|
||||
z##fpUKrO{7px=4oVy};I82ZMAiwFT|EMc$(iBg6qn;Wt%1))HsoGWjGZ6rwfW9y;f
|
||||
z+P1?LzVFv3072#UoFOjAux+UOm(9&6an}i+$f~@7#c_7}8xbIi0I-AuW05M@qt?NB
|
||||
zRe{Uu7N`$QfgK@eiP+G~9Av)K5N4SlnO~Vdm|74a%B*D8G8>rf%r0h{d4PGCIT}nO
|
||||
z1kb>tr{s#a!pI3<V`T+90M`?coAC1!em=6m55PcQ^@V_29c<|Lyif?1z2|Z8yl`i+
|
||||
za*7>%9?|1Fclp|1QdQ0P@qX6gB^>l)&nqO<`-*_VTP>kxOWk0S0g$)_YB$m-%5#X9
|
||||
zknW*;i1-ZYGfEFJqEnMDyL3$JbV`>Ob-boiL6=W;oYCpKE<*;!3~D!IpMe7goi*fD
|
||||
z18*Djz>w1hzA<RYkWmvWP1<3~y(SKswDE!|T@&w`^u&~}Onh&WX2~@cR$H{wl7ki=
|
||||
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|
||||
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|
||||
zcmZoLc&Ic%f;Calfx%$%L?+>h1_E+-8N?V21pmEaU`SzPl;klqFfjDYD@o1K2+~vt
|
||||
z_MVtzqhMg55a6s}XrgCqqM%@?Z)B)%WMF8jpkQcVWoTw)YB_PgJ|n}#S5l0olUW%J
|
||||
zmH8bQ7#aQ=F)(m2Ft9K%I51!UfyozHMC%0@m~0uDSQr@8IT+X^kQH$;FffDp4h#xl
|
||||
z8bl~CurORpU|?Wi|HJ{}Gcd3-Ft9R!tPx;TV1x)UFbFU>fRs5fu(NPN#30UK;9yW-
|
||||
zRA7P#ft0y`jTR8#5QD0NNii@mDnP7fU|>*S5CDk_2ry`1Q#Lt(Nn)}ATY5b+BLl;q
|
||||
zDh37ys6!YT7(sx6fsfIEA&*mz!Jk=!p@x}>p^e#sL5t-Cg8-)jgE6N7gBzy+LnNmF
|
||||
z!(~=3hP$j>49{7)7(TLcG5lubVqj(CV&G@vVvuCxVo+w|V$fydVlZdpVsK>RV(@0;
|
||||
zVhCm9Vu)wsV#s9k=3-zgW%%=-sR0x!3=9knjO-wHGc*W7Xa)fmhCWS(hB;92IZ$!V
|
||||
z4=iAHTu_?(1IuJZHeH|p|Jm6Y{{25E!SMe-hb_othYu_u&oR0{ReC^aA27|#8~~;n
|
||||
z7(yWG7$Ttj|Nl2@GH+mFWY~O*Rg<|MY#YO>RjXDpFlbI;V0PwG$m9~L=HhDQQdrF;
|
||||
zw3mzPIG4g(E}{QiT%6nr`rJZ}++5z=3WeN4&D>nQ+zOkyg^qG_o#$5g$}Pms!zIY0
|
||||
zV9q1t$-@=Qqfp5s)Xl>+l}BMWkI-2juIoGse|d!XdATHc73_J10(rTjc@?x9d4(qP
|
||||
za?RycILs?_m6z*2uL3KdkT@TgBA<dgpHL(pS27>3mJn+L(*wrIjyy_}&vV92KFDLv
|
||||
zD6u(}E1HG>1Or3FDlZ6mhk<$WLq5C7@A-r#%kwKri!pS#F)%QAGH@}3G6XQBFz7H&
|
||||
kV|c;Lpl851c_M$+Bmr(DBv}6+5)=${r;WiWnGIq+0Ot0jSpWb4
|
||||
|
||||
delta 808
|
||||
zcmX|<OGp)A6vxjzu6O3ljQ8{Nk(S9(BbCHE<JFt5XtK0?gjPgG5JI{rvIi7a80sQQ
|
||||
zg6uLC1c5Drz(r|y5!E6?2%}X52`vJ5*`f#+6=ig;dixJQ&i|b6%=hA3C>e2Y=7&(6
|
||||
z1vl8CW+z-x@(%LgW907_fIdYjust^(YddwW|77|83Odly8SQ9J9BnF&$EbTJc{NqB
|
||||
z8Y0(=dhuwr>(#T5HPpr%yse4n(Ztt0#S21;HymyT1(vJ9HuOD)Uv5yoA$IBhCY^G0
|
||||
z(d~;~pIj21x?ibNp&{7!_@YPn0@PYX)d4me@cII*iNKvl04<fOJ`e{MF*<zc1s|X%
|
||||
zJC(chVSo^qn;|R|QrNAw`D<+_*4m8JpR6z`q^3-IP5>c{p;T8;tmbA>dO!%ck**r)
|
||||
zYT&6wLA@%NymTDqLC|>RKbP37?tsmjG8Gpd7)9xHCH87_(8_ZjHv|kZ<BS<X$YwS&
|
||||
zWsJu(GA&FObC@~C3^0StD07{;9m+tMV3S<Zrc_h#0)js;n95j}oXtROc;(nI$pWaj
|
||||
z1=>ZECQLbP;tP`&Ou1y@vPq>VYZ132^`jg_97TGF@)_bR(jv;=h#`x%SaO?%yDb{9
|
||||
z<gkTf7CpA)D+}LR^xcx0jgCz*TejHPWz%_EUbQh{Q|VJ%zOnJWO}}huIhgBEqa*h^
|
||||
zc*vp4jvROJt`nTbYt~4(P9Mq2geJ`mW^jY-ijUksQ&-|wH$8%!dwj5hWYjvMM?@L)
|
||||
zOt#PQ3z%&Gr0KzQq%L?F$qyDI#p`ontd(z|4G<1OH}pZJatA(ZRZ|e`6IX&6k;fD!
|
||||
Re`fqpo`k>sC+JqU`~#!PkzxP<
|
||||
zcmaE;)L<|{f|X04kilTGBa`q%0|BLr3}Oto`2W3PU`SzPl;klqFf;bdD@o1K2+~vt
|
||||
z_V&^DcA6MxqiANV5a6s}XrgCqqM%@4sBdVdZ)9L-si0tBY-MU@WoSNem;S_eVvL59
|
||||
zSs4xM*_{{|8U7kE@Nlqra5!jiC`fP!xUe{=uqcSI2n09?BseG-C<yqlIOwn_$Z!Z4
|
||||
zC<sJ22t)`t2rw|2GBU9+FsN}b9IIe}0tE(x>s$;B%pfk41A_vHW&l$x4A&AE92giP
|
||||
zgh70R>+B2+tPBhcP7Le<j0%ikbs*IaP-R(AWgH9)EFejC1x5uX5Cd!&m?0p*Q3Fyn
|
||||
zS&>OpPyu8rNLWCCp${g?0TZ2U$Rsz}l1X5)C6gG8t_NAi%*ep-r;34r0pbFX0T9f`
|
||||
zXuz<9Lk_}$k_pTw7~D7%7&18o7-~2K82UK`7&uwE7=&557-U(w7}Qz07z|mt7_3>j
|
||||
z7+hJo82nke7$RA@7?N4J7;;&;7|L0>7#dl*7`j=x7^bqaaWTwi<zm?UnRx>frvL*3
|
||||
zg8+j7gW=>2Y~q^_vvD!kgT2kLYSpS$3=Eo67?>+L73OmaZRF(I&8hH^Q|L1%*I!Nr
|
||||
zWiBC8E-rg6g;Xw~axSh$E`{Y>LOZ#*4s$8I<P!SL#l_04pv^60%gyD^t&qztRL{-T
|
||||
z$*r)STj(G+*J*BrkK97cJY2jy3dTG_t~^}+JPM^eLhU?U6L}PrxAO>{<l(x^qwteQ
|
||||
zh?|#7lvlx;SIC!_E1XxMmRG2smun{P<b19U?gn-XmIgsS1{-FB$p^Tkh5XGL78F=0
|
||||
zIT+cjV-T4mz`!86S)V(ag<n9OA!3!+2?h{(kC|oiMt+OQ`}rj%zvNex5@qOgV_;zL
|
||||
yWZ+^5We8wMVbEcm#_)n!Zv(^RK!MiD2L!|>9}tk){DbW~<0kg^a6CDHNgDv8%8_CK
|
||||
|
||||
diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x270/hda_verb.c
|
||||
index 089e605eaf..60289355f8 100644
|
||||
@@ -125,5 +128,5 @@ index 089e605eaf..60289355f8 100644
|
||||
};
|
||||
|
||||
--
|
||||
2.47.3
|
||||
2.52.0
|
||||
|
||||
|
||||
+29
-31
@@ -1,8 +1,7 @@
|
||||
From 9c21961d34b4c8c410f657f478de82025124dcab Mon Sep 17 00:00:00 2001
|
||||
From 24856e5e383b1b9aa078b879064b8c2b99f4494c Mon Sep 17 00:00:00 2001
|
||||
From: Todd Baker <todd_baker@student.uml.edu>
|
||||
Date: Thu, 12 Mar 2026 13:12:04 -0400
|
||||
Subject: [PATCH 50/51] mb/dell: Add OptiPlex 3040 Micro port
|
||||
(upstream-compatible)
|
||||
Subject: [PATCH] mb/dell: Add OptiPlex 3040 Micro port (upstream-compatible)
|
||||
|
||||
Based on the OptiPlex 3050 Micro (same Skylake H110 PCH-H platform).
|
||||
Key differences from 3050:
|
||||
@@ -348,33 +347,32 @@ new file mode 100644
|
||||
index 0000000000000000000000000000000000000000..b503dfc20277775982256a4bdc9108c2ad96f856
|
||||
GIT binary patch
|
||||
literal 4300
|
||||
zcmeHJU2GIp6h1SvzjtP~vs09^U_BzjZlPs%m0GmOY<DRwEwT%>uF-@o*+oezEo~tM
|
||||
ze;7keND#9RYS0kU#1~Uvni!wdNMej6_=85_(Y}}{(ZmFdFTi^4%(PpVU{|7163*n@
|
||||
z^D}3@x%b>Ncg~9bjy~Mc^F(j5XA`<q00TbPF41^Bb#!mru``|QOYZFG-InUXui;KO
|
||||
zsa?AWP!NPAO59i%@7_CB9E@&{VNXXd_VWjjyAK!%Ot<0I&Q8q5<7+U}v7sxywHu?G
|
||||
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|
||||
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|
||||
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|
||||
zJZM_r&?0VUz7+txAMU3C1SFjZiA^|fN4;W4&0Gio&?_L|M*&4r>?lVetW$OrKoG#k
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
zx%(-qNijeNg97yLhpzeWnbQLxcG2J5339x)D^1T-h+H1~pI>nyLLL7=|AL|ssDsh!
|
||||
z0Bec}Aodza4>KHK`Y2;BFnpWo?=$u>!ylObJ7a>3t7Lt>%u+J$k@e?f_Oguc%KAq#
|
||||
z`%K1PWW6l2pn_`^J*luB1@|fX5rrLB@I6KURAFB!_?x2pRTft9K~?Wo*$x#Cs`@dN
|
||||
zy{_U1s{Vz_E~t1_)$2lRNeDNF^lXSd8B&{cuO-e1RybrgI)M>|&Yqm8*z&TVk@VKB
|
||||
zqQBhro6>rinl8Rt1*M$0Fv4UVLOiz&qZairoElpXi(uze;m7&H2!$nJCSj$~aJ1Dy
|
||||
zXlOkw+5H*qxfeVfp`CiB8?VA>f)iOVOk=p-L7+L%gIrg}y^)#_#xWbwOl=;5Q1bo_
|
||||
zgm>1C&txMj&D@E~9E6hH^C_lpx`sJ)Z8VKt(+Sf&T|w|U9gx!RttFGY@9Ce)LZi`H
|
||||
za`%E~vSj}|X)3kk;rW)*WIobp8tCo?Wztik=9MyO`D<B4wB4E<p1zk5n)p+8J$OrY
|
||||
zpQ229Cu*pNw_=m$vJ=aV%$tkn5G1f$W6ESL2u726CO=Uy8nRA5$ZJxfVj{ZPnzRvA
|
||||
z2f>Rqtm0w>CNsF$P>fV%6(#x}?M$}W^}vh###JpoWHsz-Yc_MumA#PYEaC`sjQJM+
|
||||
zE@CF+EvV0HT9`j&?}bF?DUs6Knc0~c*jpTYbl}<It!Wg~ndY&f=Kjq|zM=(b^-JK}
|
||||
zqOF45)Rr^UssHmM%T1N5NUWkYcfgTOnrSz6?vFtR3b00a1AdfRrU8!5(Ji6=0mD|k
|
||||
A9{>OV
|
||||
zcmeHJU2GIp6#nLSXYbBzr$d#pV7($jx3pz;m0GlwX?H0tEiwzWuF-@o*+oezEo~tM
|
||||
zf4YX6kSJy!)Szid6JN~w(!}_rMiOHr!Jldr9_@>X5=}_J_yVk%JJapDM0Z0%l!R}R
|
||||
zIrp4<=DX+Id*|M>Zm4^Z?&*JOpsRly^^k^%uk_0>aU;6>cJ0|4?;7md+dZ%=)=$5~
|
||||
z-I&#{Uj)(|w@Qten<IS(Co?0ByTi1<dw>o(A5h19#EjB-JKfpSLz9t6Gqt-rd*eI%
|
||||
zXydjXI}&cDcC0gQN0=IQ)OcsyjxzPZa5LT3V@D}H&^<ajF-bEAhxd(S(l<s|39-?!
|
||||
zqvHpjeQuIA#=<menr2JXj6^64nZ`!P$69IE$Ozr-_)O5<nTgE!kxaT(BN_qDKoL1`
|
||||
zoP?SzI9!V&Wx=)(w_sAN6HzB(%tG42poNDhCav;#bnu%wUIf;c_D}!>5CAB!m<l+8
|
||||
z6Y+ftx~?3nb9DO$4v;=M3`pQ8$0(d{Eu3dwuQRX33ko1QTt3QCe#y&i=(=*6c>#Vv
|
||||
zb~=3~N1dVBi0<IJj(LwOz<L1QD)Dj#E#hxV5#`o$-9@>zTwnGQIN<6r&rpgWXJWs<
|
||||
z0o#Q}ObR?+7TU2^JPXB7vC*&NF~5$4U&lF#;75tzCyC%!iQuwCa7`lc$pp1B!D^Y{
|
||||
z0hwTvOt3{Jh{*&yWr8PVf?=6JK8&jcJ_{ckJj;2q)|Jpjyb(rr*0axgcK;=3B>>{d
|
||||
zfG4X(q2Tl3df}UT6beeG6M=O}1P5?&kEz#_1565n?dgNAACjJ4DELzVqKMv-x4@Xm
|
||||
zIcFogC=_n@mbwBvAVN?&W<+Ft?P3S`&rfOsra)?yrR-p+&Vm$CcN%iY)qEXAYZ?B_
|
||||
zo{)1Ctp1H(@DVKdu5c$-{6AaHl<5_oCDeLY((m97O0lLF=l$6nUA#wEQfu9whMTk8
|
||||
z`;2pqD-fZ=LL9xN;}oHQ@5Pdn3ucO=v?x%(i|o!{2BoNR@9KX<V+b{vDDTeZ^Z7gw
|
||||
zeiOo@gbov9f{>R8eUBI)5%L+KKNI6mLbw3k5HPj`NGw1P1dJB~<kbNEAYgnNAYTUP
|
||||
z?*XF_Abyo@QjIQ^^sDrcY8+R|NtJ%68egd7Tb2Hy8a|EGYV={v=+np^jULsE*EI5$
|
||||
zMnBe!uQhT(qt`T}CP-EV>DHi;2$H9RT9YAV`9&^U8)Su!GOl95m*iC@uW<Uf3aMrT
|
||||
z3WXaNrEQvX4_K87Nxm|}Tn$AexrR1o>)bhNXq)EU`bTw+^U4hARj|6S-mE{-<}%c`
|
||||
zO$)3(g9-_v!_Xn%U$QWpa4G@QGRN341}6rIRb^18q)=51Q#29MExm++%Slc=RWiK4
|
||||
zX=*VMT5ly!Eyuv+Sk0$e@_ZFB^lr7xee+SvI<w3myA_Z+Bvmt$`|lgdC(vN_<h-?T
|
||||
zW-`a_PA(@`GY>De=H^nN2Fs-0S~Rpxi#b1=hpexfEE+qqb7S-OTPAHP?guHy>J)WO
|
||||
znyF$xyc?cdNX)D??RQod83eG>SheJ87|bT?Y-%QL)+gM0(8)r8%Cfl0J;@j}mqDUc
|
||||
zWN|TsIh(FDRWr7nMJ~t~oa(0Xf5AVJtv}S>VkKLa*Fr#z8-oJ5@_!Mwkji33O4q%s
|
||||
znq{FghJhY?uRVM)GxGTG^O@UI$;9oJ$<daf?OpB+SHQ+sAn(vOAerBB7PsO}lKDaz
|
||||
g_%bx#h2uQ{`atjmY^2f5y^UXl)_LGW5w}J2FT+;79{>OV
|
||||
|
||||
literal 0
|
||||
HcmV?d00001
|
||||
@@ -1526,5 +1524,5 @@ index 0000000000..9d262d5787
|
||||
+
|
||||
+#endif
|
||||
--
|
||||
2.47.3
|
||||
2.53.0
|
||||
|
||||
-411
@@ -1,411 +0,0 @@
|
||||
From 31f8f8de88963b1329aeac1b5c09de53165e7ce8 Mon Sep 17 00:00:00 2001
|
||||
From: Leah Rowe <leah@libreboot.org>
|
||||
Date: Thu, 23 Apr 2026 20:27:35 +0100
|
||||
Subject: [PATCH 51/51] disable -Werror in the coreboot build system
|
||||
|
||||
we don't want it in libreboot, a coreboot distro.
|
||||
|
||||
you have NO IDEA how many times users have complained
|
||||
in the past that libreboot doesn't build, and it was
|
||||
code that was actually fine in practice, but the compiler
|
||||
was just being overly pedantic. i often sit there and
|
||||
fix each one. no more.
|
||||
|
||||
just remove Werror. this shall be libreboot policy from now
|
||||
on. it makes sense for coreboot to enable this, because that
|
||||
is for developers. coreboot-distro is for coreboot users.
|
||||
|
||||
Signed-off-by: Leah Rowe <leah@libreboot.org>
|
||||
---
|
||||
Makefile.mk | 2 --
|
||||
payloads/libpayload/Makefile.mk | 2 +-
|
||||
payloads/libpayload/Makefile.payload | 2 +-
|
||||
payloads/libpayload/sample/Makefile | 2 +-
|
||||
payloads/libpayload/sample/arch_mock/Makefile | 2 +-
|
||||
payloads/libpayload/tests/Makefile.mk | 2 +-
|
||||
payloads/linuxcheck/Makefile | 2 +-
|
||||
src/lib/gnat/Makefile.mk | 1 -
|
||||
tests/Makefile.common | 2 +-
|
||||
util/amdfwtool/Makefile.mk | 3 ++-
|
||||
util/archive/Makefile | 3 ++-
|
||||
util/bincfg/Makefile | 3 ++-
|
||||
util/bucts/Makefile | 3 ++-
|
||||
util/cbfstool/Makefile.mk | 2 +-
|
||||
util/cbfstool/lz4/Makefile | 8 ++++----
|
||||
util/cbmem/Makefile | 3 ++-
|
||||
util/ectool/Makefile | 2 +-
|
||||
util/futility/Makefile.mk | 2 +-
|
||||
util/ifdtool/Makefile.mk | 2 +-
|
||||
util/intelvbttool/Makefile | 2 +-
|
||||
util/msrtool/configure | 2 +-
|
||||
util/pmh7tool/Makefile | 2 +-
|
||||
util/superiotool/Makefile | 6 +++---
|
||||
util/uio_usbdebug/Makefile | 2 +-
|
||||
util/xcompile/xcompile | 2 +-
|
||||
25 files changed, 33 insertions(+), 31 deletions(-)
|
||||
|
||||
diff --git a/Makefile.mk b/Makefile.mk
|
||||
index 8f541ad187..ff9ed89e00 100644
|
||||
--- a/Makefile.mk
|
||||
+++ b/Makefile.mk
|
||||
@@ -555,7 +555,6 @@ CFLAGS_common += -ffunction-sections
|
||||
CFLAGS_common += -fdata-sections
|
||||
CFLAGS_common += -fno-pie
|
||||
CFLAGS_common += -Wstring-compare
|
||||
-CFLAGS_common += -Werror
|
||||
ifeq ($(CONFIG_COMPILER_GCC),y)
|
||||
CFLAGS_common += -Wold-style-declaration
|
||||
CFLAGS_common += -Wcast-function-type
|
||||
@@ -581,7 +580,6 @@ endif
|
||||
ADAFLAGS_common += -gnatp
|
||||
ADAFLAGS_common += -Wuninitialized
|
||||
ADAFLAGS_common += -Wall
|
||||
-ADAFLAGS_common += -Werror
|
||||
ADAFLAGS_common += -pipe
|
||||
ADAFLAGS_common += -g
|
||||
ADAFLAGS_common += -nostdinc
|
||||
diff --git a/payloads/libpayload/Makefile.mk b/payloads/libpayload/Makefile.mk
|
||||
index 0f5d1a0e11..45c2c5ad74 100644
|
||||
--- a/payloads/libpayload/Makefile.mk
|
||||
+++ b/payloads/libpayload/Makefile.mk
|
||||
@@ -80,7 +80,7 @@ CFLAGS += -nostdlib -fno-builtin -ffreestanding -fomit-frame-pointer
|
||||
CFLAGS += -ffunction-sections -fdata-sections
|
||||
CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes -Wvla
|
||||
CFLAGS += -Wwrite-strings -Wredundant-decls -Wimplicit-fallthrough
|
||||
-CFLAGS += -Wstrict-aliasing -Wshadow -Wno-address-of-packed-member -Werror
|
||||
+CFLAGS += -Wstrict-aliasing -Wshadow -Wno-address-of-packed-member
|
||||
|
||||
ifeq ($(CONFIG_LP_LTO),y)
|
||||
CFLAGS += -flto
|
||||
diff --git a/payloads/libpayload/Makefile.payload b/payloads/libpayload/Makefile.payload
|
||||
index 2eafd4bec3..c74704c58d 100644
|
||||
--- a/payloads/libpayload/Makefile.payload
|
||||
+++ b/payloads/libpayload/Makefile.payload
|
||||
@@ -84,7 +84,7 @@ endif
|
||||
|
||||
CFLAGS = $(CFLAGS_$(ARCH))
|
||||
CFLAGS += -Os -ffreestanding
|
||||
-CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla -Werror
|
||||
+CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wvla
|
||||
ifeq ($(CONFIG_LP_LTO),y)
|
||||
CFLAGS += -flto
|
||||
endif
|
||||
diff --git a/payloads/libpayload/sample/Makefile b/payloads/libpayload/sample/Makefile
|
||||
index 1249e9a017..269511d7df 100644
|
||||
--- a/payloads/libpayload/sample/Makefile
|
||||
+++ b/payloads/libpayload/sample/Makefile
|
||||
@@ -44,7 +44,7 @@ AS := $(AS_$(ARCH-y))
|
||||
LIBPAYLOAD_DIR := ../install/libpayload
|
||||
XCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/bin/lpgcc
|
||||
XAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/bin/lpas
|
||||
-CFLAGS := -fno-builtin -Wall -Werror -Os
|
||||
+CFLAGS := -fno-builtin -Wall -Os
|
||||
TARGET := hello
|
||||
OBJS := $(TARGET).o
|
||||
|
||||
diff --git a/payloads/libpayload/sample/arch_mock/Makefile b/payloads/libpayload/sample/arch_mock/Makefile
|
||||
index a1e748111e..a146c2b3be 100644
|
||||
--- a/payloads/libpayload/sample/arch_mock/Makefile
|
||||
+++ b/payloads/libpayload/sample/arch_mock/Makefile
|
||||
@@ -12,7 +12,7 @@ CC := gcc
|
||||
AS := as
|
||||
OBJCOPY := objcopy
|
||||
LIBPAYLOAD_DIR := ../../install/libpayload
|
||||
-CFLAGS := -fno-builtin -Wall -Werror -Os \
|
||||
+CFLAGS := -fno-builtin -Wall -Os \
|
||||
-include $(LIBPAYLOAD_DIR)/include/kconfig.h \
|
||||
-include $(LIBPAYLOAD_DIR)/include/compiler.h \
|
||||
-I $(LIBPAYLOAD_DIR)/include \
|
||||
diff --git a/payloads/libpayload/tests/Makefile.mk b/payloads/libpayload/tests/Makefile.mk
|
||||
index 6b6c78d835..b2e7433b65 100644
|
||||
--- a/payloads/libpayload/tests/Makefile.mk
|
||||
+++ b/payloads/libpayload/tests/Makefile.mk
|
||||
@@ -45,7 +45,7 @@ TEST_CFLAGS += -I$(cmockasrc)/include
|
||||
# Minimal subset of warnings and errors. Tests can be less strict than actual build.
|
||||
TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wvla
|
||||
TEST_CFLAGS += -Wwrite-strings -Wno-address-of-packed-member -Wimplicit-fallthrough
|
||||
-TEST_CFLAGS += -Wstrict-aliasing -Wshadow -Werror
|
||||
+TEST_CFLAGS += -Wstrict-aliasing -Wshadow
|
||||
TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type
|
||||
|
||||
TEST_CFLAGS += -std=gnu11 -ffunction-sections -fdata-sections -fno-builtin
|
||||
diff --git a/payloads/linuxcheck/Makefile b/payloads/linuxcheck/Makefile
|
||||
index 838c90df0c..a9d016db36 100644
|
||||
--- a/payloads/linuxcheck/Makefile
|
||||
+++ b/payloads/linuxcheck/Makefile
|
||||
@@ -3,7 +3,7 @@ XCOMPILE=$(LIBPAYLOAD_DIR)/libpayload.xcompile
|
||||
# build libpayload and put .config file in $(CURDIR) instead of ../libpayload
|
||||
# to avoid pollute the libpayload source directory and possible conflicts
|
||||
LPOPTS=obj="$(CURDIR)/build" DESTDIR="$(CURDIR)" DOTCONFIG="$(CURDIR)/.config"
|
||||
-CFLAGS += -Wall -Wvla -Werror -Os -ffreestanding -nostdinc -nostdlib
|
||||
+CFLAGS += -Wall -Wvla -Os -ffreestanding -nostdinc -nostdlib
|
||||
ifeq ($(CONFIG_ARCH_X86),y)
|
||||
TARGETARCH = i386
|
||||
endif
|
||||
diff --git a/src/lib/gnat/Makefile.mk b/src/lib/gnat/Makefile.mk
|
||||
index 150a715067..9d9591bc00 100644
|
||||
--- a/src/lib/gnat/Makefile.mk
|
||||
+++ b/src/lib/gnat/Makefile.mk
|
||||
@@ -12,7 +12,6 @@ ADAFLAGS_libgnat-$(1) := \
|
||||
-gnatpg \
|
||||
-I$$(src)/lib/gnat/ \
|
||||
$$(GCC_ADAFLAGS_$(1)) \
|
||||
- -Werror \
|
||||
-fno-pie \
|
||||
|
||||
libgnat-$(1)-y += a-unccon.ads
|
||||
diff --git a/tests/Makefile.common b/tests/Makefile.common
|
||||
index 085e4cffc4..831867cf5c 100644
|
||||
--- a/tests/Makefile.common
|
||||
+++ b/tests/Makefile.common
|
||||
@@ -46,7 +46,7 @@ TEST_INCLUDES += -I$(dir $(TEST_KCONFIG_AUTOHEADER))
|
||||
# -Wmissing-prototypes just make working with the test framework cumbersome.
|
||||
# Only put conservative warnings here that really detect code that's obviously
|
||||
# unintentional.
|
||||
-TEST_CFLAGS += -Wall -Werror -Wundef -Wstrict-prototypes -Wno-inline-asm
|
||||
+TEST_CFLAGS += -Wall -Wundef -Wstrict-prototypes -Wno-inline-asm
|
||||
TEST_CFLAGS += -Wno-unknown-warning-option -Wno-source-mgr -Wno-main-return-type
|
||||
TEST_CFLAGS += -Wno-array-compare -Wno-trigraphs
|
||||
TEST_CFLAGS += -Wno-unused-but-set-variables
|
||||
diff --git a/util/amdfwtool/Makefile.mk b/util/amdfwtool/Makefile.mk
|
||||
index 0b9cc1b644..271afce4a7 100644
|
||||
--- a/util/amdfwtool/Makefile.mk
|
||||
+++ b/util/amdfwtool/Makefile.mk
|
||||
@@ -6,7 +6,8 @@ amdfwtoolobj = amdfwtool.o data_parse.o signed_psp.o handle_file.o opts.o
|
||||
amdfwreadobj = amdfwread.o
|
||||
amdfwheader = amdfwtool.h
|
||||
|
||||
-WERROR ?= -Werror
|
||||
+# no werror for you
|
||||
+WERROR ?=
|
||||
AMDFWTOOLCFLAGS :=-O2 -Wall -Wextra -Wshadow $(WERROR)
|
||||
AMDFWTOOLCFLAGS += -I $(top)/src/commonlib/bsd/include
|
||||
AMDFWTOOLCFLAGS += -D_GNU_SOURCE # memmem() from string.h
|
||||
diff --git a/util/archive/Makefile b/util/archive/Makefile
|
||||
index 2de6a6294a..70820aeba2 100644
|
||||
--- a/util/archive/Makefile
|
||||
+++ b/util/archive/Makefile
|
||||
@@ -1,7 +1,8 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
PROGRAM = archive
|
||||
HOSTCC ?= gcc
|
||||
-WERROR=-Werror
|
||||
+# no werror for u
|
||||
+WERROR=
|
||||
CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR}
|
||||
|
||||
SRCS = $(PROGRAM).c
|
||||
diff --git a/util/bincfg/Makefile b/util/bincfg/Makefile
|
||||
index dbcbc7711c..debef6c597 100644
|
||||
--- a/util/bincfg/Makefile
|
||||
+++ b/util/bincfg/Makefile
|
||||
@@ -3,7 +3,8 @@ CC = gcc
|
||||
YACC = bison
|
||||
LEX = flex
|
||||
TARGET=bincfg
|
||||
-WERROR=-Werror
|
||||
+# no werror for u
|
||||
+WERROR=
|
||||
CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR}
|
||||
CFLAGS+=-Wno-unused-function
|
||||
LDFLAGS= -lfl
|
||||
diff --git a/util/bucts/Makefile b/util/bucts/Makefile
|
||||
index d32258d1ec..a81aa5e1ae 100644
|
||||
--- a/util/bucts/Makefile
|
||||
+++ b/util/bucts/Makefile
|
||||
@@ -3,7 +3,8 @@ CC:=gcc
|
||||
OBJ:=bucts.o
|
||||
TARGET=bucts
|
||||
VERSION:=$(shell git describe)
|
||||
-WERROR=-Werror
|
||||
+# no werror for u
|
||||
+WERROR=
|
||||
CFLAGS=-O2 -Wall -Wextra -Wshadow ${WERROR}
|
||||
|
||||
ifeq ($(shell uname), FreeBSD)
|
||||
diff --git a/util/cbfstool/Makefile.mk b/util/cbfstool/Makefile.mk
|
||||
index d3f07f9777..e34f69c1f1 100644
|
||||
--- a/util/cbfstool/Makefile.mk
|
||||
+++ b/util/cbfstool/Makefile.mk
|
||||
@@ -140,7 +140,7 @@ cse_serger_obj += common.o
|
||||
cse_serger_obj += cse_helpers.o
|
||||
cse_serger_obj += $(foreach var, $(bpdt_formats_obj), $(var))
|
||||
|
||||
-TOOLCFLAGS ?= -Werror -Wall -Wextra -Wshadow
|
||||
+TOOLCFLAGS ?= -Wall -Wextra -Wshadow
|
||||
TOOLCFLAGS += -Wcast-qual -Wmissing-prototypes -Wredundant-decls -Wshadow
|
||||
TOOLCFLAGS += -Wstrict-prototypes -Wwrite-strings
|
||||
TOOLCFLAGS += -O2
|
||||
diff --git a/util/cbfstool/lz4/Makefile b/util/cbfstool/lz4/Makefile
|
||||
index d624e84703..be484c805f 100644
|
||||
--- a/util/cbfstool/lz4/Makefile
|
||||
+++ b/util/cbfstool/lz4/Makefile
|
||||
@@ -72,10 +72,10 @@ cmake:
|
||||
@cd cmake_unofficial; cmake CMakeLists.txt; $(MAKE)
|
||||
|
||||
gpptest: clean
|
||||
- $(MAKE) all CC=g++ CFLAGS="-O3 -I../lib -Wall -Wextra -Wundef -Wshadow -Wcast-align -Werror"
|
||||
+ $(MAKE) all CC=g++ CFLAGS="-O3 -I../lib -Wall -Wextra -Wundef -Wshadow -Wcast-align"
|
||||
|
||||
clangtest: clean
|
||||
- CFLAGS="-O3 -Werror -Wconversion -Wno-sign-conversion" $(MAKE) all CC=clang
|
||||
+ CFLAGS="-O3 -Wconversion -Wno-sign-conversion" $(MAKE) all CC=clang
|
||||
|
||||
sanitize: clean
|
||||
CFLAGS="-O3 -g -fsanitize=undefined" $(MAKE) test CC=clang FUZZER_TIME="-T1mn" NB_LOOPS=-i1
|
||||
@@ -84,8 +84,8 @@ staticAnalyze: clean
|
||||
CFLAGS=-g clang-tidy $(CLANG_TIDY_CHECKS) $(CLANG_TIDY_ARGS) $(SRCS)
|
||||
|
||||
armtest: clean
|
||||
- CFLAGS="-O3 -Werror" $(MAKE) -C $(LZ4DIR) all CC=arm-linux-gnueabi-gcc
|
||||
- CFLAGS="-O3 -Werror" $(MAKE) -C $(PRGDIR) bins CC=arm-linux-gnueabi-gcc
|
||||
+ CFLAGS="-O3" $(MAKE) -C $(LZ4DIR) all CC=arm-linux-gnueabi-gcc
|
||||
+ CFLAGS="-O3" $(MAKE) -C $(PRGDIR) bins CC=arm-linux-gnueabi-gcc
|
||||
|
||||
versionsTest: clean
|
||||
$(MAKE) -C versionsTest
|
||||
diff --git a/util/cbmem/Makefile b/util/cbmem/Makefile
|
||||
index e265ea6693..3aaaeac794 100644
|
||||
--- a/util/cbmem/Makefile
|
||||
+++ b/util/cbmem/Makefile
|
||||
@@ -9,7 +9,8 @@ CC ?= $(CROSS_COMPILE)gcc
|
||||
INSTALL ?= /usr/bin/env install
|
||||
PREFIX ?= /usr/local
|
||||
CFLAGS ?= -O2
|
||||
-WERROR=-Werror
|
||||
+# no werror for you!
|
||||
+WERROR=
|
||||
CFLAGS += -Wall -Wextra -Wmissing-prototypes -Wshadow $(WERROR)
|
||||
CPPFLAGS += -I . -I $(ROOT)/commonlib/include -I $(ROOT)/commonlib/bsd/include
|
||||
CPPFLAGS += -include $(ROOT)/commonlib/bsd/include/commonlib/bsd/compiler.h
|
||||
diff --git a/util/ectool/Makefile b/util/ectool/Makefile
|
||||
index a90773e5c6..5724ac6009 100644
|
||||
--- a/util/ectool/Makefile
|
||||
+++ b/util/ectool/Makefile
|
||||
@@ -1,7 +1,7 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
CC ?= gcc
|
||||
-WERROR=-Werror
|
||||
+WERROR=
|
||||
CFLAGS = -O2 -Wall -Wextra -Wshadow $(WERROR)
|
||||
PROGRAM = ectool
|
||||
INSTALL ?= /usr/bin/env install
|
||||
diff --git a/util/futility/Makefile.mk b/util/futility/Makefile.mk
|
||||
index a7bcee50d3..cb5363b93e 100644
|
||||
--- a/util/futility/Makefile.mk
|
||||
+++ b/util/futility/Makefile.mk
|
||||
@@ -10,7 +10,7 @@ $(VBOOT_FUTILITY): | check-openssl-presence
|
||||
unset CFLAGS LDFLAGS; $(MAKE) -C $(VBOOT_SOURCE) \
|
||||
BUILD=$(VBOOT_HOST_BUILD) \
|
||||
CC="$(HOSTCC)" \
|
||||
- WERROR="-Werror -Wno-deprecated-declarations" \
|
||||
+ WERROR="-Wno-deprecated-declarations" \
|
||||
PKG_CONFIG="$(HOSTPKGCONFIG)" \
|
||||
V=$(V) \
|
||||
USE_FLASHROM=0 \
|
||||
diff --git a/util/ifdtool/Makefile.mk b/util/ifdtool/Makefile.mk
|
||||
index 2b97bf51c8..47953aedb1 100644
|
||||
--- a/util/ifdtool/Makefile.mk
|
||||
+++ b/util/ifdtool/Makefile.mk
|
||||
@@ -2,7 +2,7 @@
|
||||
|
||||
ifdtoolobj = ifdtool.o fmap.o kv_pair.o valstr.o
|
||||
|
||||
-IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes -Werror
|
||||
+IFDTOOLCFLAGS = -O2 -g -Wall -Wextra -Wmissing-prototypes
|
||||
IFDTOOLCFLAGS += -I$(top)/src/commonlib/include -I$(top)/src/commonlib/bsd/include
|
||||
IFDTOOLCFLAGS += -I$(top)/util/cbfstool/flashmap
|
||||
IFDTOOLCFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h
|
||||
diff --git a/util/intelvbttool/Makefile b/util/intelvbttool/Makefile
|
||||
index 5c770dec9e..8963263354 100644
|
||||
--- a/util/intelvbttool/Makefile
|
||||
+++ b/util/intelvbttool/Makefile
|
||||
@@ -6,7 +6,7 @@ CC ?= gcc
|
||||
INSTALL ?= /usr/bin/env install
|
||||
PREFIX ?= /usr/local
|
||||
CFLAGS ?= -O2 -g
|
||||
-CFLAGS += -Wall -Werror
|
||||
+CFLAGS += -Wall
|
||||
CFLAGS += -I../../src/commonlib/include -I ../../src/commonlib/bsd/include
|
||||
|
||||
all: $(PROGRAM)
|
||||
diff --git a/util/msrtool/configure b/util/msrtool/configure
|
||||
index 659cbcd66b..731e24f550 100755
|
||||
--- a/util/msrtool/configure
|
||||
+++ b/util/msrtool/configure
|
||||
@@ -133,7 +133,7 @@ CC=`findprog "compiler" "${CC}" clang gcc cc icc` || exit
|
||||
INSTALL=`findprog "install" "${INSTALL}" install ginstall` || exit
|
||||
|
||||
test -n "$DEBUG" && myCFLAGS="-O2 -g" || myCFLAGS="-Os"
|
||||
-CFLAGS="${CFLAGS} ${myCFLAGS} -Wall -Werror"
|
||||
+CFLAGS="${CFLAGS} ${myCFLAGS} -Wall"
|
||||
|
||||
cat > .config.c << EOF
|
||||
#include <pci/pci.h>
|
||||
diff --git a/util/pmh7tool/Makefile b/util/pmh7tool/Makefile
|
||||
index 0a2ebbe147..c04d7e9bf9 100644
|
||||
--- a/util/pmh7tool/Makefile
|
||||
+++ b/util/pmh7tool/Makefile
|
||||
@@ -1,7 +1,7 @@
|
||||
## SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
CC = gcc
|
||||
-CFLAGS = -O2 -Wall -Wextra -Werror
|
||||
+CFLAGS = -O2 -Wall -Wextra
|
||||
PROGRAM = pmh7tool
|
||||
INSTALL = /usr/bin/env install
|
||||
PREFIX = /usr/local
|
||||
diff --git a/util/superiotool/Makefile b/util/superiotool/Makefile
|
||||
index 39839d9aa6..06aa7b6571 100644
|
||||
--- a/util/superiotool/Makefile
|
||||
+++ b/util/superiotool/Makefile
|
||||
@@ -12,7 +12,7 @@ PREFIX ?= /usr/local
|
||||
VERSION := -D'SUPERIOTOOL_VERSION="$(shell git describe 2>/dev/null)"'
|
||||
|
||||
CFLAGS += -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \
|
||||
- -Werror-implicit-function-declaration -std=c11 -pedantic $(VERSION) \
|
||||
+ -std=c11 -pedantic $(VERSION) \
|
||||
-Wno-variadic-macros -I $(TOP)/src/commonlib/bsd/include
|
||||
LDFLAGS += -lz
|
||||
|
||||
@@ -24,8 +24,8 @@ ifeq ($(OS_ARCH), Darwin)
|
||||
LIBS = -framework IOKit -framework DirectHW -lpci -lz
|
||||
endif
|
||||
ifeq ($(OS_ARCH), FreeBSD)
|
||||
-CFLAGS = -O2 -Wall -Werror -Wstrict-prototypes -Wundef -Wstrict-aliasing \
|
||||
- -Werror-implicit-function-declaration -std=c11 $(VERSION) \
|
||||
+CFLAGS = -O2 -Wall -Wstrict-prototypes -Wundef -Wstrict-aliasing \
|
||||
+ -std=c11 $(VERSION) \
|
||||
-I/usr/local/include
|
||||
LDFLAGS += -L/usr/local/lib
|
||||
LIBS = -lz
|
||||
diff --git a/util/uio_usbdebug/Makefile b/util/uio_usbdebug/Makefile
|
||||
index af1cc8e1ec..2ceb28cd53 100644
|
||||
--- a/util/uio_usbdebug/Makefile
|
||||
+++ b/util/uio_usbdebug/Makefile
|
||||
@@ -30,7 +30,7 @@ KCONFIG_H := ../../src/include/kconfig.h
|
||||
|
||||
CFLAGS += \
|
||||
-m32 -g \
|
||||
- -Wall -Wextra -Werror \
|
||||
+ -Wall -Wextra \
|
||||
-Wno-unused-parameter -Wno-error=sign-compare
|
||||
CPPFLAGS += \
|
||||
-Iinclude/ \
|
||||
diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile
|
||||
index f88da69306..ef43e28683 100755
|
||||
--- a/util/xcompile/xcompile
|
||||
+++ b/util/xcompile/xcompile
|
||||
@@ -124,7 +124,7 @@ testcc() {
|
||||
local tmp_o="$TMPFILE.o"
|
||||
rm -f "$tmp_c" "$tmp_o"
|
||||
echo "void _start(void) {}" >"$tmp_c"
|
||||
- "$cc" -nostdlib -Werror $cflags -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1
|
||||
+ "$cc" -nostdlib $cflags -c "$tmp_c" -o "$tmp_o" >/dev/null 2>&1
|
||||
}
|
||||
|
||||
testld() {
|
||||
--
|
||||
2.47.3
|
||||
|
||||
+46
@@ -0,0 +1,46 @@
|
||||
From 88519aed6c7f305f7f2319e335c1421137df7ce3 Mon Sep 17 00:00:00 2001
|
||||
From: Ron Nazarov <ron@noisytoot.org>
|
||||
Date: Mon, 23 Mar 2026 17:04:03 +0000
|
||||
Subject: [PATCH] mb/supermicro/x11-lga1151-series: Enable SATA hotplug
|
||||
|
||||
Before this patch, hotplugging only worked to replace drives (if you
|
||||
tried to plug a drive into a SATA port that no drive was plugged in to
|
||||
at boot, it wouldn't be detected) and you'd have to manually rescan
|
||||
the bus (echo "- - -" > /sys/class/scsi_host/host*/scan) to make
|
||||
plugs/unplugs get detected by the operating system.
|
||||
|
||||
Now, hotplugging works for all ports (tested and working on Supermicro
|
||||
X11SSH-LN4F) and there's no need to manually rescan (it sometimes
|
||||
takes a few seconds for unplugs to be detected, but plugs are detected
|
||||
instantly).
|
||||
|
||||
Change-Id: Id978a047697795ea657048fb6dc6665736c293f9
|
||||
Signed-off-by: Ron Nazarov <ron@noisytoot.org>
|
||||
---
|
||||
.../supermicro/x11-lga1151-series/devicetree.cb | 10 ++++++++++
|
||||
1 file changed, 10 insertions(+)
|
||||
|
||||
diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
|
||||
index fbf896c6ae..d25288420f 100644
|
||||
--- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
|
||||
+++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb
|
||||
@@ -28,6 +28,16 @@ chip soc/intel/skylake
|
||||
[6] = 1,
|
||||
[7] = 1,
|
||||
}"
|
||||
+ register "SataPortsHotPlug" = "{
|
||||
+ [0] = 1,
|
||||
+ [1] = 1,
|
||||
+ [2] = 1,
|
||||
+ [3] = 1,
|
||||
+ [4] = 1,
|
||||
+ [5] = 1,
|
||||
+ [6] = 1,
|
||||
+ [7] = 1,
|
||||
+ }"
|
||||
end
|
||||
device ref lpc_espi on
|
||||
register "serirq_mode" = "SERIRQ_CONTINUOUS"
|
||||
--
|
||||
2.52.0
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
# SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
tree="default"
|
||||
rev="62c8197dd25376cb7b18d272af167cb176d28bcf"
|
||||
rev="ed5a993f0f98a47d5e780e375e5861860019b183"
|
||||
|
||||
@@ -21,7 +21,6 @@ CONFIG_OPTION_BACKEND_NONE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
@@ -100,7 +99,6 @@ CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
@@ -129,7 +127,7 @@ CONFIG_CBFS_SIZE=0xEEE000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_HEIGHT=2160
|
||||
CONFIG_LINEAR_FRAMEBUFFER_MAX_WIDTH=3840
|
||||
CONFIG_MAX_CPUS=8
|
||||
CONFIG_MAX_CPUS=16
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
@@ -151,21 +149,19 @@ CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3040 Micro"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_USE_PM_ACPI_TIMER=y
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_USE_PM_ACPI_TIMER=y
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_3040=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
@@ -192,7 +188,6 @@ CONFIG_IFD_BIN_PATH="../../../config/ifd/3040micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3040micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
@@ -210,9 +205,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -256,7 +249,6 @@ CONFIG_SMM_RESERVED_SIZE=0x200000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x800
|
||||
CONFIG_ACPI_BERT_SIZE=0x0
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
@@ -274,6 +266,7 @@ CONFIG_SOC_INTEL_I2C_DEV_MAX=6
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
|
||||
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
|
||||
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
@@ -284,14 +277,13 @@ CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
|
||||
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
|
||||
CONFIG_SOC_INTEL_KABYLAKE=y
|
||||
CONFIG_SKYLAKE_SOC_PCH_H=y
|
||||
@@ -301,7 +293,7 @@ CONFIG_SKYLAKE_SOC_PCH_H=y
|
||||
CONFIG_FSP_T_LOCATION=0xfffe0000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_SOC_INTEL_COMMON=y
|
||||
|
||||
#
|
||||
@@ -399,14 +391,6 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
@@ -447,8 +431,8 @@ CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -470,7 +454,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
@@ -513,11 +496,11 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
@@ -532,7 +515,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -582,8 +564,6 @@ CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR4=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
@@ -591,8 +571,8 @@ CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
CONFIG_MRC_SETTINGS_PROTECT=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
@@ -630,7 +610,6 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
|
||||
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
|
||||
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
|
||||
CONFIG_FSP_VGA_MODE12_BPP=0x0
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
@@ -642,7 +621,6 @@ CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
@@ -680,11 +658,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -697,6 +670,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
@@ -767,6 +741,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
@@ -836,11 +811,9 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -21,7 +21,6 @@ CONFIG_OPTION_BACKEND_NONE=y
|
||||
# CONFIG_USE_CBFS_FILE_OPTION_BACKEND is not set
|
||||
CONFIG_COMPRESS_RAMSTAGE_LZMA=y
|
||||
# CONFIG_COMPRESS_RAMSTAGE_LZ4 is not set
|
||||
# CONFIG_COMPRESS_RAMSTAGE_ZSTD is not set
|
||||
CONFIG_SEPARATE_ROMSTAGE=y
|
||||
CONFIG_INCLUDE_CONFIG_FILE=y
|
||||
CONFIG_COLLECT_TIMESTAMPS=y
|
||||
@@ -100,7 +99,6 @@ CONFIG_VENDOR_DELL=y
|
||||
# CONFIG_VENDOR_PRODRIVE is not set
|
||||
# CONFIG_VENDOR_PROTECTLI is not set
|
||||
# CONFIG_VENDOR_PURISM is not set
|
||||
# CONFIG_VENDOR_QOTOM is not set
|
||||
# CONFIG_VENDOR_RAPTOR_CS is not set
|
||||
# CONFIG_VENDOR_RAZER is not set
|
||||
# CONFIG_VENDOR_RODA is not set
|
||||
@@ -127,7 +125,7 @@ CONFIG_FMDFILE=""
|
||||
CONFIG_MAINBOARD_VENDOR="Dell Inc."
|
||||
CONFIG_CBFS_SIZE=0xEEE000
|
||||
CONFIG_CONSOLE_SERIAL=y
|
||||
CONFIG_MAX_CPUS=8
|
||||
CONFIG_MAX_CPUS=16
|
||||
# CONFIG_ONBOARD_VGA_IS_PRIMARY is not set
|
||||
CONFIG_POST_DEVICE=y
|
||||
CONFIG_POST_IO=y
|
||||
@@ -149,21 +147,19 @@ CONFIG_INTEL_GMA_VBT_FILE="src/mainboard/$(MAINBOARDDIR)/data.vbt"
|
||||
CONFIG_PRERAM_CBMEM_CONSOLE_SIZE=0xc00
|
||||
CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME="OptiPlex 3040 Micro"
|
||||
# CONFIG_CONSOLE_POST is not set
|
||||
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_CMOS_DEFAULT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.default"
|
||||
CONFIG_CMOS_LAYOUT_FILE="src/mainboard/$(MAINBOARDDIR)/cmos.layout"
|
||||
CONFIG_USE_PM_ACPI_TIMER=y
|
||||
CONFIG_MAX_SOCKET=1
|
||||
CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_USE_PM_ACPI_TIMER=y
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_3040=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3050 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5420 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E5520 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E6220 is not set
|
||||
@@ -190,7 +186,6 @@ CONFIG_IFD_BIN_PATH="../../../config/ifd/3040micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3040micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
@@ -208,9 +203,7 @@ CONFIG_GFX_GMA_PANEL_1_ON_EDP=y
|
||||
CONFIG_DRIVERS_UART_8250IO=y
|
||||
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_EC_GPE_SCI=0x50
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -254,7 +247,6 @@ CONFIG_SMM_RESERVED_SIZE=0x200000
|
||||
CONFIG_SMM_MODULE_STACK_SIZE=0x800
|
||||
CONFIG_ACPI_BERT_SIZE=0x0
|
||||
CONFIG_DRIVERS_I2C_DESIGNWARE_CLOCK_MHZ=120
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_PRERAM_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT=0xe0000000
|
||||
CONFIG_ACPI_CPU_STRING="CP%02X"
|
||||
@@ -272,6 +264,7 @@ CONFIG_SOC_INTEL_I2C_DEV_MAX=6
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_M_VAL=0x30
|
||||
CONFIG_SOC_INTEL_COMMON_LPSS_UART_CLK_N_VAL=0xc35
|
||||
CONFIG_FSP_HEADER_PATH="3rdparty/fsp/KabylakeFspBinPkg/Include/"
|
||||
CONFIG_FSP_FD_PATH="3rdparty/fsp/KabylakeFspBinPkg/Fsp.fd"
|
||||
CONFIG_SOC_INTEL_COMMON_DEBUG_CONSENT=0
|
||||
CONFIG_INTEL_GMA_BCLV_OFFSET=0xc8254
|
||||
CONFIG_INTEL_GMA_BCLV_WIDTH=16
|
||||
@@ -282,14 +275,13 @@ CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
CONFIG_PCIE_LTR_MAX_SNOOP_LATENCY=0x1003
|
||||
CONFIG_PCIE_LTR_MAX_NO_SNOOP_LATENCY=0x1003
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_SOC_INTEL_COMMON_SKYLAKE_BASE=y
|
||||
CONFIG_SOC_INTEL_KABYLAKE=y
|
||||
CONFIG_SKYLAKE_SOC_PCH_H=y
|
||||
@@ -299,7 +291,7 @@ CONFIG_SKYLAKE_SOC_PCH_H=y
|
||||
CONFIG_FSP_T_LOCATION=0xfffe0000
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_P2SB=y
|
||||
CONFIG_FIXED_SMBUS_IO_BASE=0xefa0
|
||||
CONFIG_UART_BITBANG_TX_DELAY_MS=5
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
CONFIG_SOC_INTEL_COMMON=y
|
||||
|
||||
#
|
||||
@@ -397,14 +389,6 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
@@ -445,8 +429,8 @@ CONFIG_UDELAY_TSC=y
|
||||
CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_CPU_PT_ROM_MAP_GB=512
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -468,7 +452,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
@@ -511,11 +494,11 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
CONFIG_POSTRAM_CBFS_CACHE_IN_BSS=y
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_PC80_SYSTEM=y
|
||||
CONFIG_HAVE_CMOS_DEFAULT=y
|
||||
CONFIG_POSTCAR_STAGE=y
|
||||
@@ -530,7 +513,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -574,8 +556,6 @@ CONFIG_INTEL_GMA_ADD_VBT=y
|
||||
# CONFIG_SOFTWARE_I2C is not set
|
||||
CONFIG_I2C_TRANSFER_TIMEOUT_US=500000
|
||||
CONFIG_RESOURCE_ALLOCATION_TOP_DOWN=y
|
||||
CONFIG_DRAM_SUPPORT_DDR4=y
|
||||
CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
# end of Devices
|
||||
|
||||
#
|
||||
@@ -583,8 +563,8 @@ CONFIG_DRAM_SUPPORT_DDR3=y
|
||||
#
|
||||
CONFIG_CRB_TPM_BASE_ADDRESS=0xfed40000
|
||||
# CONFIG_DRIVERS_EFI_VARIABLE_STORE is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_ELOG is not set
|
||||
# CONFIG_DRIVERS_HWID_DMI is not set
|
||||
CONFIG_CACHE_MRC_SETTINGS=y
|
||||
CONFIG_MRC_SETTINGS_PROTECT=y
|
||||
# CONFIG_DRIVERS_OPTION_CFR is not set
|
||||
@@ -622,7 +602,6 @@ CONFIG_USE_FSP_NOTIFY_PHASE_READY_TO_BOOT=y
|
||||
CONFIG_USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE=y
|
||||
# CONFIG_DISPLAY_FSP_TIMESTAMPS is not set
|
||||
# CONFIG_BUILDING_WITH_DEBUG_FSP is not set
|
||||
CONFIG_FSP_VGA_MODE12_BPP=0x0
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
# CONFIG_VBT_CBFS_COMPRESSION_LZ4 is not set
|
||||
@@ -634,7 +613,6 @@ CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
@@ -673,11 +651,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -690,6 +663,7 @@ CONFIG_PLATFORM_HAS_DRAM_CLEAR=y
|
||||
CONFIG_BOOTMEDIA_LOCK_NONE=y
|
||||
# CONFIG_BOOTMEDIA_LOCK_CONTROLLER is not set
|
||||
# CONFIG_BOOTMEDIA_LOCK_CHIP is not set
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# end of Security
|
||||
|
||||
CONFIG_ACPI_HAVE_PCAT_8259=y
|
||||
@@ -760,6 +734,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
@@ -829,11 +804,9 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
# Boot Logo Configuration
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -161,7 +161,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -194,7 +193,6 @@ CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
@@ -214,7 +212,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -286,6 +283,7 @@ CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
@@ -401,14 +399,6 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
@@ -450,7 +440,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -472,7 +461,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
@@ -515,7 +503,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
@@ -534,7 +521,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -644,7 +630,6 @@ CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
@@ -682,11 +667,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -769,6 +749,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
@@ -839,10 +820,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -159,7 +159,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -192,7 +191,6 @@ CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
@@ -212,7 +210,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -284,6 +281,7 @@ CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
@@ -399,14 +397,6 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
@@ -448,7 +438,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -470,7 +459,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
@@ -513,7 +501,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
@@ -532,7 +519,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -636,7 +622,6 @@ CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
@@ -675,11 +660,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -762,6 +742,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
@@ -832,10 +813,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -160,7 +160,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -193,7 +192,6 @@ CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
@@ -212,7 +210,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -284,6 +281,7 @@ CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
@@ -399,14 +397,6 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
@@ -448,7 +438,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -470,7 +459,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
@@ -513,7 +501,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
@@ -532,7 +519,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -642,7 +628,6 @@ CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
@@ -680,11 +665,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -752,6 +732,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
@@ -821,10 +802,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -191,7 +190,6 @@ CONFIG_IFD_BIN_PATH="../../../config/ifd/3050micro/ifd"
|
||||
CONFIG_ME_BIN_PATH="../../../vendorfiles/3050micro/me.bin"
|
||||
CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU=y
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_DONT_INCLUDE_ALL_DRIVERS=y
|
||||
CONFIG_USE_LEGACY_8254_TIMER=y
|
||||
@@ -210,7 +208,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_16384=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -282,6 +279,7 @@ CONFIG_FSP_STATUS_GLOBAL_RESET=0x40000003
|
||||
CONFIG_MAX_HECI_DEVICES=5
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HAVE_PAM0_REGISTER=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_INTEL_TXT_BIOSACM_ALIGNMENT=0x40000
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=10
|
||||
CONFIG_SOC_INTEL_GFX_FRAMEBUFFER_OFFSET=0x0
|
||||
@@ -397,14 +395,6 @@ CONFIG_SOC_INTEL_COMMON_BLOCK_XDCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI=y
|
||||
CONFIG_SOC_INTEL_COMMON_BLOCK_XHCI_ELOG=y
|
||||
|
||||
#
|
||||
# Intel SoC Common Code for features
|
||||
#
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_GSPI_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_I2C_DEVFN=y
|
||||
CONFIG_SOC_INTEL_COMMON_FEATURE_UART_DEVICES=y
|
||||
|
||||
#
|
||||
# Intel SoC Common PCH Code
|
||||
#
|
||||
@@ -446,7 +436,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -468,7 +457,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# CONFIG_PCIEXP_HOTPLUG is not set
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_SMBUS=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_CAPABLE=y
|
||||
# CONFIG_VALIDATE_INTEL_DESCRIPTOR is not set
|
||||
@@ -511,7 +499,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
@@ -530,7 +517,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -634,7 +620,6 @@ CONFIG_GFX_GMA_GENERATION="Skylake"
|
||||
CONFIG_GFX_GMA_PCH="Sunrise_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
@@ -673,11 +658,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -745,6 +725,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_ACPI_NHLT=y
|
||||
|
||||
#
|
||||
@@ -814,10 +795,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -159,7 +159,6 @@ CONFIG_TPM_PIRQ=0x0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -215,7 +214,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -272,6 +270,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -301,7 +303,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -317,9 +318,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -341,7 +339,6 @@ CONFIG_SOUTHBRIDGE_INTEL_C216=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -395,7 +392,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -415,7 +411,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -557,11 +552,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -641,6 +631,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -705,10 +696,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -212,7 +211,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -264,6 +262,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -298,7 +300,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -315,9 +316,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
@@ -325,7 +323,6 @@ CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -371,7 +368,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -393,7 +389,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -530,11 +525,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -611,6 +601,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -675,10 +666,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -210,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -262,6 +260,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -296,7 +298,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
@@ -323,7 +321,6 @@ CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -369,7 +366,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -391,7 +387,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -526,11 +521,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -607,6 +597,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -671,10 +662,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -212,7 +211,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -264,6 +262,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -298,7 +300,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -315,9 +316,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
@@ -325,7 +323,6 @@ CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -371,7 +368,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -393,7 +389,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -530,11 +525,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -611,6 +601,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -675,10 +666,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_MT=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -210,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -262,6 +260,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -296,7 +298,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
@@ -323,7 +321,6 @@ CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -369,7 +366,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -391,7 +387,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -526,11 +521,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -607,6 +597,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -671,10 +662,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -212,7 +211,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -264,6 +262,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -298,7 +300,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -315,9 +316,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
@@ -325,7 +323,6 @@ CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -371,7 +368,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -393,7 +389,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -530,11 +525,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -611,6 +601,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -675,10 +666,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -210,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -262,6 +260,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -296,7 +298,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
@@ -323,7 +321,6 @@ CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -369,7 +366,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -391,7 +387,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -526,11 +521,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -607,6 +597,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -671,10 +662,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -212,7 +211,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -264,6 +262,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -298,7 +300,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -315,9 +316,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
@@ -325,7 +323,6 @@ CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -371,7 +368,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -393,7 +389,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -530,11 +525,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -611,6 +601,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -675,10 +666,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_780_USFF=y
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -210,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_8192=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -262,6 +260,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0xc8256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -296,7 +298,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
|
||||
#
|
||||
@@ -323,7 +321,6 @@ CONFIG_NORTHBRIDGE_INTEL_X4X=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801JX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -369,7 +366,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -391,7 +387,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -526,11 +521,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -607,6 +597,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -671,10 +662,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -160,7 +160,6 @@ CONFIG_TPM_PIRQ=0x0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -196,7 +195,6 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
@@ -213,7 +211,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -269,6 +266,11 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
@@ -299,7 +301,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -315,9 +316,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
@@ -328,8 +326,6 @@ CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -381,7 +377,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
@@ -400,7 +395,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -486,6 +480,7 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
@@ -498,8 +493,6 @@ CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
CONFIG_HAS_DIGITAL_IO_POWER_DOMAIN=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
@@ -543,11 +536,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -629,6 +617,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -693,10 +682,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_TPM_PIRQ=0x0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -194,7 +193,6 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
@@ -211,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -267,6 +264,11 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
@@ -297,7 +299,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
@@ -326,8 +324,6 @@ CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -379,7 +375,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
@@ -398,7 +393,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -482,6 +476,7 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
@@ -494,8 +489,6 @@ CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
CONFIG_HAS_DIGITAL_IO_POWER_DOMAIN=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
@@ -540,11 +533,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -626,6 +614,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -690,10 +679,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -160,7 +160,6 @@ CONFIG_TPM_PIRQ=0x0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
|
||||
@@ -196,7 +195,6 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
@@ -213,7 +211,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -269,6 +266,11 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
@@ -299,7 +301,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -315,9 +316,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
@@ -328,8 +326,6 @@ CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -381,7 +377,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
@@ -400,7 +395,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -486,6 +480,7 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
@@ -498,8 +493,6 @@ CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
CONFIG_HAS_DIGITAL_IO_POWER_DOMAIN=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
@@ -543,11 +536,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -629,6 +617,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -693,10 +682,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_TPM_PIRQ=0x0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF=y
|
||||
@@ -194,7 +193,6 @@ CONFIG_GBE_BIN_PATH="../../../config/ifd/dell9020mt/gbe"
|
||||
CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000
|
||||
# CONFIG_ENABLE_DDR_2X_REFRESH is not set
|
||||
CONFIG_PCIEXP_AER=y
|
||||
# CONFIG_INTEL_OC_MAILBOX_ENABLE_UNDERVOLTING is not set
|
||||
CONFIG_CARDBUS_PLUGIN_SUPPORT=y
|
||||
CONFIG_SPI_FLASH_GIGADEVICE=y
|
||||
CONFIG_SPI_FLASH_STMICRO=y
|
||||
@@ -211,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
# CONFIG_TPM_MEASURED_BOOT is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
@@ -267,6 +264,11 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_CPU_INTEL_NUM_FIT_ENTRIES=6
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
@@ -297,7 +299,6 @@ CONFIG_TSC_MONOTONIC_TIMER=y
|
||||
CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_HASWELL=y
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
|
||||
@@ -326,8 +324,6 @@ CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_LYNXPOINT=y
|
||||
CONFIG_FINALIZE_USB_ROUTE_XHCI=y
|
||||
CONFIG_DISABLE_ME_PCI=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -379,7 +375,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
CONFIG_X86_TOP4G_BOOTMEDIA_MAP=y
|
||||
@@ -398,7 +393,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -482,6 +476,7 @@ CONFIG_HAVE_USBDEBUG_OPTIONS=y
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9755 is not set
|
||||
# CONFIG_DRIVERS_GENESYSLOGIC_GL9763E is not set
|
||||
# CONFIG_DRIVERS_I2C_MAX98396 is not set
|
||||
CONFIG_INTEL_DDI=y
|
||||
CONFIG_INTEL_INT15=y
|
||||
CONFIG_INTEL_GMA_ACPI=y
|
||||
CONFIG_VBT_CBFS_COMPRESSION_LZMA=y
|
||||
@@ -494,8 +489,6 @@ CONFIG_GFX_GMA_GENERATION="Haswell"
|
||||
CONFIG_GFX_GMA_PCH="Lynx_Point"
|
||||
CONFIG_GFX_GMA_PANEL_2_PORT="Disabled"
|
||||
CONFIG_GFX_GMA_ANALOG_I2C_PORT="PCH_DAC"
|
||||
CONFIG_DRIVERS_INTEL_OC_MAILBOX=y
|
||||
CONFIG_HAS_DIGITAL_IO_POWER_DOMAIN=y
|
||||
# CONFIG_DRIVERS_NXP_UWB_SR1XX is not set
|
||||
# CONFIG_DRIVERS_PS2_KEYBOARD is not set
|
||||
CONFIG_DRIVERS_MC146818=y
|
||||
@@ -540,11 +533,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -626,6 +614,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -690,10 +679,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -157,7 +157,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_BOARD_DELL_E4300=y
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -208,7 +207,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -262,6 +260,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -294,7 +296,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -311,9 +312,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
|
||||
#
|
||||
@@ -321,7 +319,6 @@ CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -368,7 +365,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -389,7 +385,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -525,11 +520,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -590,6 +580,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -652,10 +643,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -155,7 +155,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
CONFIG_BOARD_DELL_E4300=y
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -206,7 +205,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -260,6 +258,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -292,7 +294,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -309,9 +310,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
|
||||
#
|
||||
@@ -319,7 +317,6 @@ CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -366,7 +363,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -387,7 +383,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -521,11 +516,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -586,6 +576,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -648,10 +639,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -209,7 +208,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -267,6 +265,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -296,7 +298,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -312,9 +313,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -336,7 +334,6 @@ CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -389,7 +386,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -409,7 +405,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -543,11 +538,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -609,6 +599,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -672,10 +663,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -207,7 +206,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -265,6 +263,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -294,7 +296,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -310,9 +311,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -334,7 +332,6 @@ CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -387,7 +384,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -407,7 +403,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -540,11 +535,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -606,6 +596,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -669,10 +660,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -209,7 +208,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -267,6 +265,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -296,7 +298,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -312,9 +313,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -336,7 +334,6 @@ CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -389,7 +386,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -409,7 +405,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -543,11 +538,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -609,6 +599,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -672,10 +663,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -207,7 +206,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_6144=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -265,6 +263,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -294,7 +296,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -310,9 +311,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -334,7 +332,6 @@ CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -387,7 +384,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -407,7 +403,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -540,11 +535,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -606,6 +596,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -669,10 +660,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -209,7 +208,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -267,6 +265,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -296,7 +298,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -312,9 +313,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -336,7 +334,6 @@ CONFIG_SOUTHBRIDGE_INTEL_C216=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -389,7 +386,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -409,7 +405,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -543,11 +538,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -609,6 +599,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -672,10 +663,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -207,7 +206,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -265,6 +263,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -294,7 +296,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -310,9 +311,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -334,7 +332,6 @@ CONFIG_SOUTHBRIDGE_INTEL_C216=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -387,7 +384,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -407,7 +403,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -540,11 +535,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -606,6 +596,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -669,10 +660,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -210,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_10240=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -268,6 +266,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -297,7 +299,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -337,7 +335,6 @@ CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -392,7 +389,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -412,7 +408,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -546,11 +541,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -612,6 +602,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -675,10 +666,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -208,7 +207,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_10240=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -266,6 +264,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -295,7 +297,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -311,9 +312,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -335,7 +333,6 @@ CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -390,7 +387,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -410,7 +406,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -543,11 +538,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -609,6 +599,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -672,10 +663,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -210,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -268,6 +266,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -297,7 +299,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -337,7 +335,6 @@ CONFIG_SOUTHBRIDGE_INTEL_C216=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -392,7 +389,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -412,7 +408,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -546,11 +541,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -612,6 +602,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -675,10 +666,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -208,7 +207,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -266,6 +264,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -295,7 +297,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -311,9 +312,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -335,7 +333,6 @@ CONFIG_SOUTHBRIDGE_INTEL_C216=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -390,7 +387,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -410,7 +406,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -543,11 +538,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -609,6 +599,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -672,10 +663,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -210,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_10240=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -268,6 +266,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -297,7 +299,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -337,7 +335,6 @@ CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -392,7 +389,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -412,7 +408,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -546,11 +541,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -612,6 +602,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -675,10 +666,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -208,7 +207,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_10240=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -266,6 +264,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -295,7 +297,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -311,9 +312,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -335,7 +333,6 @@ CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -390,7 +387,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -410,7 +406,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -543,11 +538,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -609,6 +599,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -672,10 +663,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -210,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -268,6 +266,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -297,7 +299,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -337,7 +335,6 @@ CONFIG_SOUTHBRIDGE_INTEL_C216=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -392,7 +389,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -412,7 +408,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -546,11 +541,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -612,6 +602,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -675,10 +666,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -208,7 +207,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -266,6 +264,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -295,7 +297,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -311,9 +312,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -335,7 +333,6 @@ CONFIG_SOUTHBRIDGE_INTEL_C216=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -390,7 +387,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -410,7 +406,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -543,11 +538,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -609,6 +599,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -672,10 +663,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -157,7 +157,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
CONFIG_BOARD_DELL_E6400=y
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -209,7 +208,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -264,6 +262,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -296,7 +298,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
|
||||
#
|
||||
@@ -323,7 +321,6 @@ CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -370,7 +367,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -391,7 +387,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -529,11 +524,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -594,6 +584,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -656,10 +647,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -155,7 +155,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
CONFIG_BOARD_DELL_E6400=y
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -207,7 +206,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -262,6 +260,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -294,7 +296,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -311,9 +312,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
|
||||
#
|
||||
@@ -321,7 +319,6 @@ CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -368,7 +365,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -389,7 +385,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -525,11 +520,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -590,6 +580,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -652,10 +643,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -154,7 +154,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
CONFIG_BOARD_DELL_E6400=y
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -205,7 +204,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_4096=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -260,6 +258,10 @@ CONFIG_INTEL_GMA_BCLM_OFFSET=0x61256
|
||||
CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -292,7 +294,6 @@ CONFIG_SETUP_XIP_CACHE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_LAPIC_REMAP_MITIGATION=y
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
@@ -309,9 +310,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed14000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
|
||||
#
|
||||
@@ -319,7 +317,6 @@ CONFIG_NORTHBRIDGE_INTEL_GM45=y
|
||||
#
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_I82801IX=y
|
||||
# CONFIG_PCIEXP_COMMON_CLOCK is not set
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -366,7 +363,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -387,7 +383,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -502,11 +497,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -567,6 +557,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -624,10 +615,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -210,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_10240=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -268,6 +266,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -297,7 +299,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -337,7 +335,6 @@ CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -392,7 +389,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -412,7 +408,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -546,11 +541,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -612,6 +602,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -675,10 +666,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -208,7 +207,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_10240=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -266,6 +264,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -295,7 +297,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -311,9 +312,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -335,7 +333,6 @@ CONFIG_SOUTHBRIDGE_INTEL_BD82X6X=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -390,7 +387,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -410,7 +406,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -543,11 +538,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -609,6 +599,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -672,10 +663,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -158,7 +158,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -210,7 +209,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -268,6 +266,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -297,7 +299,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -313,9 +314,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -337,7 +335,6 @@ CONFIG_SOUTHBRIDGE_INTEL_C216=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -392,7 +389,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -412,7 +408,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -546,11 +541,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -612,6 +602,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -675,10 +666,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
@@ -156,7 +156,6 @@ CONFIG_BOOT_DEVICE_SPI_FLASH_BUS=0
|
||||
# CONFIG_BOARD_DELL_E4300 is not set
|
||||
# CONFIG_BOARD_DELL_E6400 is not set
|
||||
# CONFIG_BOARD_DELL_LATITUDE_E7240 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_3040 is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_MT is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_780_USFF is not set
|
||||
# CONFIG_BOARD_DELL_OPTIPLEX_9020_SFF is not set
|
||||
@@ -208,7 +207,6 @@ CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
|
||||
CONFIG_HEAP_SIZE=0x100000
|
||||
# CONFIG_BOOTMEDIA_SMM_BWP is not set
|
||||
# CONFIG_DRIVERS_EFI_FW_INFO is not set
|
||||
# CONFIG_TCG_OPAL_S3_UNLOCK is not set
|
||||
CONFIG_BOARD_ROMSIZE_KB_12288=y
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
|
||||
# CONFIG_COREBOOT_ROMSIZE_KB_512 is not set
|
||||
@@ -266,6 +264,10 @@ CONFIG_INTEL_GMA_BCLM_WIDTH=16
|
||||
CONFIG_BOOTBLOCK_IN_CBFS=y
|
||||
CONFIG_DCACHE_RAM_MRC_VAR_SIZE=0x0
|
||||
CONFIG_HPET_MIN_TICKS=0x80
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOC_PHYSICAL_ADDRESS_WIDTH=0
|
||||
CONFIG_RAMSTAGE_CBFS_CACHE_SIZE=0x4000
|
||||
CONFIG_CBFS_CACHE_ALIGN=8
|
||||
@@ -295,7 +297,6 @@ CONFIG_TSC_SYNC_MFENCE=y
|
||||
CONFIG_HAVE_SMI_HANDLER=y
|
||||
CONFIG_NEED_SMALL_2MB_PAGE_TABLES=y
|
||||
CONFIG_SMM_TSEG=y
|
||||
CONFIG_SMM_OPAL_S3_STATE_SMRAM_SIZE=0x0
|
||||
CONFIG_SMM_PCI_RESOURCE_STORE_NUM_SLOTS=8
|
||||
CONFIG_AP_STACK_SIZE=0x800
|
||||
CONFIG_SMP=y
|
||||
@@ -311,9 +312,6 @@ CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS=y
|
||||
#
|
||||
# Northbridge
|
||||
#
|
||||
CONFIG_FIXED_MCHBAR_MMIO_BASE=0xfed10000
|
||||
CONFIG_FIXED_DMIBAR_MMIO_BASE=0xfed18000
|
||||
CONFIG_FIXED_EPBAR_MMIO_BASE=0xfed19000
|
||||
CONFIG_USE_NATIVE_RAMINIT=y
|
||||
CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE=y
|
||||
# CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES is not set
|
||||
@@ -335,7 +333,6 @@ CONFIG_SOUTHBRIDGE_INTEL_C216=y
|
||||
# CONFIG_HIDE_MEI_ON_ERROR is not set
|
||||
CONFIG_PCIEXP_HOTPLUG=y
|
||||
CONFIG_INTEL_DESCRIPTOR_MODE_REQUIRED=y
|
||||
CONFIG_PCIEXP_COMMON_CLOCK=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RESET=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC=y
|
||||
CONFIG_SOUTHBRIDGE_INTEL_COMMON_PMCLIB=y
|
||||
@@ -390,7 +387,6 @@ CONFIG_ARCH_VERSTAGE_X86_32=y
|
||||
CONFIG_ARCH_ROMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_POSTCAR_X86_32=y
|
||||
CONFIG_ARCH_RAMSTAGE_X86_32=y
|
||||
CONFIG_ARCH_SMM_X86_32=y
|
||||
CONFIG_ARCH_ALL_STAGES_X86_32=y
|
||||
CONFIG_HAVE_X86_64_SUPPORT=y
|
||||
CONFIG_RESERVED_PHYSICAL_ADDRESS_BITS_SUPPORT=y
|
||||
@@ -410,7 +406,6 @@ CONFIG_X86_BOOTBLOCK_EXTRA_PROGRAM_SZ=0
|
||||
CONFIG_DEFAULT_EBDA_LOWMEM=0x100000
|
||||
CONFIG_DEFAULT_EBDA_SEGMENT=0xF600
|
||||
CONFIG_DEFAULT_EBDA_SIZE=0x400
|
||||
CONFIG_IOAPIC=y
|
||||
# end of Chipset
|
||||
|
||||
#
|
||||
@@ -543,11 +538,6 @@ CONFIG_PCR_FW_VER=10
|
||||
CONFIG_PCR_RUNTIME_DATA=3
|
||||
# end of Trusted Platform Module
|
||||
|
||||
#
|
||||
# TCG storage
|
||||
#
|
||||
# end of TCG storage
|
||||
|
||||
#
|
||||
# Memory initialization
|
||||
#
|
||||
@@ -609,6 +599,7 @@ CONFIG_HAVE_ACPI_RESUME=y
|
||||
CONFIG_RESUME_PATH_SAME_AS_BOOT=y
|
||||
CONFIG_HAVE_MONOTONIC_TIMER=y
|
||||
CONFIG_HAVE_OPTION_TABLE=y
|
||||
CONFIG_IOAPIC=y
|
||||
CONFIG_USE_WATCHDOG_ON_BOOT=y
|
||||
|
||||
#
|
||||
@@ -672,10 +663,11 @@ CONFIG_DECOMPRESS_OFAST=y
|
||||
#
|
||||
# CONFIG_BMP_LOGO is not set
|
||||
CONFIG_PLATFORM_POST_RENDER_DELAY_SEC=5
|
||||
# CONFIG_PLATFORM_HAS_SECONDARY_BOOT_INDICATOR_LOGO is not set
|
||||
CONFIG_PLATFORM_OFF_MODE_CHARGING_INDICATOR_LOGO_PATH="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/off_mode_charging.bmp"
|
||||
# CONFIG_FRAMEBUFFER_SPLASH_TEXT is not set
|
||||
# end of Boot Logo Configuration
|
||||
|
||||
CONFIG_WARNINGS_ARE_ERRORS=y
|
||||
CONFIG_MAX_REBOOT_CNT=3
|
||||
CONFIG_RELOCATABLE_MODULES=y
|
||||
CONFIG_GENERIC_GPIO_LIB=y
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user