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config/coreboot/default: Add Haswell NRI SMBIOS type 16/17 patch
This patch implements SMBIOS type 16 and 17 for Haswell NRI, making `dmidecode -t memory` work. From https://review.coreboot.org/c/coreboot/+/89385
This commit is contained in:
Ron Nazarov
@@ -0,0 +1,184 @@
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From b00d35efc78b13d53c8f0b35b869811c5a2c56cf Mon Sep 17 00:00:00 2001
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From: Ron Nazarov <ron@noisytoot.org>
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Date: Tue, 30 Sep 2025 22:36:53 +0100
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Subject: [PATCH] Haswell NRI: Implement SMBIOS type 16/17
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Based on the implementation from Ivy/Sandy Bridge NRI.
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Tested on a Dell OptiPlex 9020 SFF with libreboot.
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Change-Id: I5e153258f9f88726f54c98baac0b1788a839f934
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Signed-off-by: Ron Nazarov <ron@noisytoot.org>
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---
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.../haswell/native_raminit/raminit_main.c | 6 +-
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.../haswell/native_raminit/raminit_native.c | 83 +++++++++++++++++--
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.../haswell/native_raminit/raminit_native.h | 2 +-
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3 files changed, 81 insertions(+), 10 deletions(-)
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diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_main.c b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
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index 84db33ebdf..328f777ee1 100644
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--- a/src/northbridge/intel/haswell/native_raminit/raminit_main.c
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+++ b/src/northbridge/intel/haswell/native_raminit/raminit_main.c
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@@ -245,7 +245,7 @@ static enum raminit_status try_raminit(
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return status;
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}
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-void raminit_main(const enum raminit_boot_mode bootmode)
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+const struct sysinfo *raminit_main(const enum raminit_boot_mode bootmode)
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{
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/*
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* The mighty_ctrl struct. Will happily nuke the pre-RAM stack
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@@ -261,7 +261,7 @@ void raminit_main(const enum raminit_boot_mode bootmode)
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if (bootmode != BOOTMODE_COLD) {
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status = try_raminit(&mighty_ctrl, fast_boot, ARRAY_SIZE(fast_boot));
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if (status == RAMINIT_STATUS_SUCCESS)
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- return;
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+ return &mighty_ctrl;
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}
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/** TODO: Try more than once **/
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@@ -269,4 +269,6 @@ void raminit_main(const enum raminit_boot_mode bootmode)
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if (status != RAMINIT_STATUS_SUCCESS)
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die("Memory initialization was met with utmost failure and misery\n");
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+
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+ return &mighty_ctrl;
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}
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diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.c b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
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index 3ad8ce29e7..73532592e8 100644
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--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.c
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+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.c
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@@ -16,6 +16,73 @@
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#include "raminit_native.h"
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+static uint8_t nb_get_ecc_type(const uint32_t capid0_a)
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+{
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+ return capid0_a & CAPID_ECCDIS ? MEMORY_ARRAY_ECC_NONE : MEMORY_ARRAY_ECC_SINGLE_BIT;
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+}
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+
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+static uint16_t nb_slots_per_channel(const uint32_t capid0_a)
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+{
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+ return !(capid0_a & CAPID_DDPCD) + 1;
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+}
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+
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+static uint16_t nb_number_of_channels(const uint32_t capid0_a)
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+{
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+ return !(capid0_a & CAPID_PDCD) + 1;
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+}
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+
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+static uint32_t nb_max_chan_capacity_mib(const uint32_t capid0_a)
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+{
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+ uint32_t ddrsz;
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+
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+ /* Values from documentation, which assume two DIMMs per channel */
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+ switch (CAPID_DDRSZ(capid0_a)) {
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+ case 1:
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+ ddrsz = 8192;
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+ break;
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+ case 2:
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+ ddrsz = 2048;
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+ break;
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+ case 3:
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+ ddrsz = 512;
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+ break;
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+ default:
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+ ddrsz = 16384;
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+ break;
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+ }
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+
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+ /* Account for the maximum number of DIMMs per channel */
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+ return (ddrsz / 2) * nb_slots_per_channel(capid0_a);
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+}
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+
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+/* Fill cbmem with information for SMBIOS type 16 and type 17 */
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+static void setup_sdram_meminfo(const struct sysinfo *ctrl)
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+{
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+ const u16 ddr_freq = (1000 << 8) / ctrl->tCK;
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+
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+ for (uint8_t channel = 0; channel < NUM_CHANNELS; channel++) {
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+ for (uint8_t slot = 0; slot < NUM_SLOTS; slot++) {
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+ enum cb_err ret = spd_add_smbios17(channel, slot, ddr_freq,
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+ &ctrl->dimms[channel][slot].data);
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+ if (ret != CB_SUCCESS)
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+ printk(BIOS_ERR, "RAMINIT: Failed to add SMBIOS17\n");
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+ }
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+ }
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+
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+ /* The 'spd_add_smbios17' function allocates this CBMEM area */
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+ struct memory_info *m = cbmem_find(CBMEM_ID_MEMINFO);
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+ if (!m)
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+ return;
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+
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+ const uint32_t capid0_a = pci_read_config32(HOST_BRIDGE, CAPID0_A);
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+
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+ const uint16_t channels = nb_number_of_channels(capid0_a);
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+
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+ m->ecc_type = nb_get_ecc_type(capid0_a);
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+ m->max_capacity_mib = channels * nb_max_chan_capacity_mib(capid0_a);
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+ m->number_of_devices = channels * nb_slots_per_channel(capid0_a);
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+}
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+
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static void wait_txt_clear(void)
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{
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const struct cpuid_result cpuid = cpuid_ext(1, 0);
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@@ -90,7 +157,8 @@ static void raminit_reset(void)
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static enum raminit_boot_mode do_actual_raminit(
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const bool s3resume,
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const bool cpu_replaced,
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- const enum raminit_boot_mode orig_bootmode)
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+ const enum raminit_boot_mode orig_bootmode,
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+ const struct sysinfo **ctrl)
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{
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struct mrc_data md = prepare_mrc_cache();
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@@ -158,7 +226,7 @@ static enum raminit_boot_mode do_actual_raminit(
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* And now, the actual memory initialization thing.
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*/
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printk(RAM_DEBUG, "\nStarting native raminit\n");
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- raminit_main(bootmode);
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+ *ctrl = raminit_main(bootmode);
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return bootmode;
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}
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@@ -176,8 +244,9 @@ void perform_raminit(const int s3resume)
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wait_txt_clear();
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wrmsr(0x2e6, (msr_t) {.lo = 0, .hi = 0});
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+ const struct sysinfo *ctrl;
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const enum raminit_boot_mode bootmode =
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- do_actual_raminit(s3resume, cpu_replaced, orig_bootmode);
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+ do_actual_raminit(s3resume, cpu_replaced, orig_bootmode, &ctrl);
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/** TODO: report_memory_config **/
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@@ -204,9 +273,9 @@ void perform_raminit(const int s3resume)
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system_reset();
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}
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- /* Save training data on non-S3 resumes */
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- if (!s3resume)
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+ /* Save training data and set up SMBIOS type 16/17 on non-S3 resumes */
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+ if (!s3resume) {
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save_mrc_data();
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-
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- /** TODO: setup_sdram_meminfo **/
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+ setup_sdram_meminfo(ctrl);
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+ }
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}
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diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
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index b9e84a11df..1401feedc5 100644
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--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
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+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
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@@ -476,7 +476,7 @@ static inline void mchbar_write64(const uintptr_t x, const uint64_t v)
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"m"(mmxsave));
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}
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-void raminit_main(enum raminit_boot_mode bootmode);
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+const struct sysinfo *raminit_main(enum raminit_boot_mode bootmode);
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enum raminit_status collect_spd_info(struct sysinfo *ctrl);
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enum raminit_status initialise_mpll(struct sysinfo *ctrl);
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--
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2.50.1
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