coja/lbmk
1
0
Fork 0
mirror of https://codeberg.org/libreboot/lbmk.git synced 2026-07-20 05:18:07 +02:00
Code Issues Packages Projects Releases Wiki Activity

rebase haswell nri patches to coreboot/default

Browse Source 
scrap the haswell tree. handle mrc- and nri-based haswell
configurations from the same default coreboot tree

this means that it will now be possible to use it on the
dell 9020 sff/mt ports

only txtmode configs were available before, on libremrc
setups for w541/t440p. because the grub payload was added,
i've now added the corebootfb configs.

the libremrc configs have been re-done, by re-copying the
mrc ones and then turning off mrc, instead enabling nri

Signed-off-by: Leah Rowe <leah@libreboot.org>
This commit is contained in:
Leah Rowe
2024-04-07 23:34:17 +01:00
parent 6da91df6b9
commit a43d2e60e8
38 changed files with 1776 additions and 4039 deletions
Download Patch File Download Diff File Expand all files Collapse all files
config/coreboot/default/patches/0059-haswell-NRI-mitigate-compiler-warnings.patch
+81
View File
@@ -0,0 +1,81 @@
From 2728c87b7f792aa8e4db29d4dc3d2d2f71f6dafd Mon Sep 17 00:00:00 2001
From: Leah Rowe <info@minifree.org>
Date: Mon, 8 Apr 2024 00:54:44 +0100
Subject: [PATCH 1/1] haswell NRI: mitigate compiler warnings
Random -Werror warnings. I'd rather patch these up
than disable warnings-as-errors in the code.
Signed-off-by: Leah Rowe <info@minifree.org>
---
.../intel/haswell/native_raminit/raminit_native.h | 1 +
src/northbridge/intel/haswell/native_raminit/reut.c | 5 +++--
src/northbridge/intel/haswell/native_raminit/testing_io.c | 2 +-
.../intel/haswell/native_raminit/timings_refresh.c | 2 +-
4 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/northbridge/intel/haswell/native_raminit/raminit_native.h b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
index 98e39cb76e..76a74d6569 100644
--- a/src/northbridge/intel/haswell/native_raminit/raminit_native.h
+++ b/src/northbridge/intel/haswell/native_raminit/raminit_native.h
@@ -397,6 +397,7 @@ static inline void tick_delay(const uint32_t delay)
/* Just perform reads to a random register */
for (uint32_t start = 0; start <= delay; start++)
junk = mchbar_read32(REUT_ERR_DATA_STATUS);
+ (void)junk; /* mitigate -Werror=unused-but-set-variable */
}
/*
diff --git a/src/northbridge/intel/haswell/native_raminit/reut.c b/src/northbridge/intel/haswell/native_raminit/reut.c
index c55cdd9c7e..c861528a92 100644
--- a/src/northbridge/intel/haswell/native_raminit/reut.c
+++ b/src/northbridge/intel/haswell/native_raminit/reut.c
@@ -153,7 +153,7 @@ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_
{
/** TODO: Issuing ZQ commands differs for LPDDR **/
if (ctrl->lpddr)
- die("%s: LPDDR not yet supported in ZQ calibration\n");
+ die("LPDDR not yet supported in ZQ calibration\n");
uint8_t opcode; /* NOTE: Only used for LPDDR */
uint16_t zq = 0;
@@ -173,8 +173,9 @@ enum raminit_status reut_issue_zq(struct sysinfo *ctrl, uint8_t chanmask, uint8_
opcode = 0xc3;
break;
default:
- die("%s: ZQ type %u is invalid\n", zq_type);
+ die("ZQ type %u is invalid\n", zq_type);
}
+ (void)opcode; /* Mitigate -Werror=unused-but-set-variable */
/* ZQCS on single-channel needs a longer delay */
const uint8_t delay = zq_type == ZQ_SHORT && (!ctrl->dpc[0] || !ctrl->dpc[1]) ? 7 : 1;
diff --git a/src/northbridge/intel/haswell/native_raminit/testing_io.c b/src/northbridge/intel/haswell/native_raminit/testing_io.c
index 7716fc4285..63ae59c33e 100644
--- a/src/northbridge/intel/haswell/native_raminit/testing_io.c
+++ b/src/northbridge/intel/haswell/native_raminit/testing_io.c
@@ -221,7 +221,7 @@ void setup_io_test(
const uint8_t subseq_wait)
{
if (!chanmask)
- die("\n%s: invalid chanmask\n", __func__, chanmask);
+ die("\n%d: invalid chanmask\n", chanmask);
/*
* Prepare variables needed for both channels.
diff --git a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
index 820bb336b0..e5d8088912 100644
--- a/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
+++ b/src/northbridge/intel/haswell/native_raminit/timings_refresh.c
@@ -189,7 +189,7 @@ static union tc_srftp_reg make_tc_srftp(const struct sysinfo *const ctrl)
void configure_timings(struct sysinfo *ctrl)
{
if (ctrl->lpddr)
- die("%s: Missing support for LPDDR\n");
+ die("Missing support for LPDDR\n");
const uint8_t odt_stretch = get_odt_stretch(ctrl);
const union tc_bank_reg tc_bank = make_tc_bank(ctrl);
--
2.39.2