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https://codeberg.org/libreboot/lbmk.git
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coreboot/fam15h: re-add kgpe-d16 and kcma-d8
also kfsn4-dre this is still based on the old coreboot 4.11 version. i have on todo to adapt dasharo coreboot for use in the master branch of lbmk, for mainline libreboot releases. since i'm doing c-libreboot for the GNU project, namely GNU Boot, and since GNU Boot has dre/d8/d16 in their tree, re-add it here for them. i literally just copied this from them, who in turn copied it from libreboot in an older revision anyway. but there is one fix: src/vendorcode/cavium/bdk/libbdk-hal/if/bdk-if-phy-vetesse.c ^ this blob wasn't being deleted by gnuboot, nor by libreboot in the older revision that it forked from. an oversight. i decided to audit the deblobbing and found this one was overlooked, out of about 900 files picked up by deblob-check. so this re-addition of dre/d8/d16 support is actually even better deblobbed than gnuboot, or old-libreboot. Signed-off-by: Leah Rowe <leah@libreboot.org>
This commit is contained in:
Leah Rowe
+31
@@ -0,0 +1,31 @@
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From 8f2988cba4fffef1bd4f65e123c76bf4b7a18672 Mon Sep 17 00:00:00 2001
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From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
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Date: Sun, 7 Feb 2021 15:29:40 +0100
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Subject: [PATCH 1/6] Revert "Revert "nb/amd/mct_ddr3: Fix RDIMM training
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failure on Fam15h" (fixes a bug that prevent certain RAM modules from
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booting)
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This reverts commit 610d1c67b2298a9840681c2b4492b6d3fdf44a46.
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After 610d1c67b2298a9840681c2b4492b6d3fdf44a46 many RAM modules wouldn't work and you couldn't even see any output on the screen.
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---
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src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 +++
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1 file changed, 3 insertions(+)
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diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
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index ddaaaab8d5..3b07786b91 100644
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--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
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+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
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@@ -71,6 +71,9 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
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misc2 |= ((cs_mux_67 & 0x1) << 27);
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misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */
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misc2 |= ((cs_mux_45 & 0x1) << 26);
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+
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+ if (pDCTstat->Status & (1 << SB_Registered))
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+ misc2 |= 1 << SubMemclkRegDly;
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} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
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if (pDCTstat->Status & (1 << SB_Registered)) {
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misc2 |= 1 << SubMemclkRegDly;
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--
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2.25.1
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+38
@@ -0,0 +1,38 @@
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From 7a00638cea41ad939a59fc0e5996959435fbdb7f Mon Sep 17 00:00:00 2001
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From: "D.d.P.F. Lombard" <lombard@lombards.xyz>
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Date: Sun, 7 Feb 2021 16:40:05 +0100
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Subject: [PATCH 3/6] Tweak cmos defaults for KCMA-D8 (for a little speed
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boost)
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63xx CPUs have the option to use a reduced latency value inside the crossbar.
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Setting "experimental_memory_speed_boost=Enable" aparently only has an effect
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on 63xx CPUs and may, in certain cases, yield a slight memory bandwidth
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increase (according to Timothy Pearson), but maybe it also works for
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43xx CPUs.
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Setting "l3_cache_partitioning=Enable" will increase performance in certain
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situations. See:
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https://developer.arm.com/documentation/100453/0401/functional-description/l3-cache/l3-cache-partitioning?lang=en
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---
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src/mainboard/asus/kcma-d8/cmos.default | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/src/mainboard/asus/kcma-d8/cmos.default b/src/mainboard/asus/kcma-d8/cmos.default
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index 306687157f..4e033d756f 100644
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--- a/src/mainboard/asus/kcma-d8/cmos.default
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+++ b/src/mainboard/asus/kcma-d8/cmos.default
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@@ -21,9 +21,9 @@ sata_ahci_mode=Enable
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sata_alpm=Disable
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maximum_p_state_limit=0xf
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probe_filter=Auto
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-l3_cache_partitioning=Disable
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+l3_cache_partitioning=Enable
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gart=Enable
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ehci_async_data_cache=Enable
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-experimental_memory_speed_boost=Disable
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+experimental_memory_speed_boost=Enable
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power_on_after_fail=On
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boot_option=Fallback
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--
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2.25.1
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+108
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From 2b1d40b970d9cbbb4f8fe30679e9b6909aa3d99a Mon Sep 17 00:00:00 2001
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From: Leah Rowe <leah@libreboot.org>
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Date: Thu, 6 May 2021 17:07:06 +0100
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Subject: [PATCH 4/6] Do not use microcode updates on AMD platforms
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Coreboot is hardcoding the use of microcode updates on some platforms.
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Just nuke it from orbit. This is the libre branch of osboot, so microcode must
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not be used.
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---
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src/cpu/Makefile.inc | 52 +------------------
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src/cpu/amd/family_10h-family_15h/Kconfig | 1 -
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.../amd/family_10h-family_15h/Makefile.inc | 10 +---
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3 files changed, 2 insertions(+), 61 deletions(-)
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diff --git a/src/cpu/Makefile.inc b/src/cpu/Makefile.inc
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index b80c30d72b..e7909d32ed 100644
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--- a/src/cpu/Makefile.inc
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+++ b/src/cpu/Makefile.inc
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@@ -14,54 +14,4 @@ $(eval $(call create_class_compiler,cpu_microcode,x86_32))
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## Rules for building the microcode blob in CBFS
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################################################################################
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-ifneq ($(CONFIG_CPU_MICROCODE_MULTIPLE_FILES), y)
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-cbfs-files-$(CONFIG_USE_CPU_MICROCODE_CBFS_BINS) += cpu_microcode_blob.bin
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-endif
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-
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-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
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-cbfs-files-y += cpu_microcode_blob.bin
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-cpu_microcode_blob.bin-file = $(objgenerated)/microcode.bin
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-
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-$(objgenerated)/microcode.bin: $(call strip_quotes,$(CONFIG_CPU_MICROCODE_HEADER_FILES))
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- echo " util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin \"$(CONFIG_CPU_MICROCODE_HEADER_FILES)\""
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- util/scripts/ucode_h_to_bin.sh $(objgenerated)/microcode.bin $(CONFIG_CPU_MICROCODE_HEADER_FILES)
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-endif
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-
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-ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_BINS),y)
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-cpu_microcode_bins := $(call strip_quotes,$(CONFIG_CPU_UCODE_BINARIES))
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-endif
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-# otherwise `cpu_microcode_bins` should be filled by platform makefiles
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-
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-# We just mash all microcode binaries together into one binary to rule them all.
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-# This approach assumes that the microcode binaries are properly padded, and
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-# their headers specify the correct size. This works fairly well on isolatied
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-# updates, such as Intel and some AMD microcode, but won't work very well if the
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-# updates are wrapped in a container, like AMD's microcode update container. If
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-# there is only one microcode binary (i.e. one container), then we don't have
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-# this issue, and this rule will continue to work.
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-$(obj)/cpu_microcode_blob.bin: $$(wildcard $$(cpu_microcode_bins))
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- for bin in $(cpu_microcode_bins); do \
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- if [ ! -f "$$bin" ]; then \
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- echo "Microcode error: $$bin does not exist"; \
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- NO_MICROCODE_FILE=1; \
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- fi; \
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- done; \
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- if [ -n "$$NO_MICROCODE_FILE" ]; then \
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- if [ -z "$(CONFIG_USE_BLOBS)" ] && [ -n "$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS)" ]; then \
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- echo "Try enabling binary-only repository in Kconfig 'General setup' menu."; \
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- fi; \
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- false; \
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- fi
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- $(if $^,,false) # fail if no file is given at all
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- @printf " MICROCODE $(subst $(obj)/,,$(@))\n"
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- @echo $(cpu_microcode_bins)
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- cat $^ > $@
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-
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-cpu_microcode_blob.bin-file ?= $(obj)/cpu_microcode_blob.bin
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-cpu_microcode_blob.bin-type := microcode
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-
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-ifneq ($(CONFIG_CPU_MICROCODE_CBFS_LOC),)
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-cpu_microcode_blob.bin-COREBOOT-position := $(CONFIG_CPU_MICROCODE_CBFS_LOC)
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-else
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-cpu_microcode_blob.bin-align := 16
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-endif
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+# No microcode permitted in this version of coreboot.
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diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig
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index ad4f5f4ba6..21150ab1a7 100644
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--- a/src/cpu/amd/family_10h-family_15h/Kconfig
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+++ b/src/cpu/amd/family_10h-family_15h/Kconfig
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@@ -8,7 +8,6 @@ config CPU_AMD_MODEL_10XXX
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select TSC_SYNC_LFENCE
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select UDELAY_LAPIC
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select SUPPORT_CPU_UCODE_IN_CBFS
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- select CPU_MICROCODE_MULTIPLE_FILES
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select CAR_GLOBAL_MIGRATION
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if CPU_AMD_MODEL_10XXX
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diff --git a/src/cpu/amd/family_10h-family_15h/Makefile.inc b/src/cpu/amd/family_10h-family_15h/Makefile.inc
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index 7035323026..e0029f562d 100644
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--- a/src/cpu/amd/family_10h-family_15h/Makefile.inc
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+++ b/src/cpu/amd/family_10h-family_15h/Makefile.inc
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@@ -14,12 +14,4 @@ ramstage-y += ram_calc.c
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ramstage-y += monotonic_timer.c
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ramstage-$(CONFIG_HAVE_ACPI_TABLES) += powernow_acpi.c
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-# Microcode for Family 10h, 11h, 12h, and 14h
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-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd.bin
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-microcode_amd.bin-file := 3rdparty/blobs/cpu/amd/family_10h-family_14h/microcode_amd.bin
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-microcode_amd.bin-type := microcode
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-
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-# Microcode for Family 15h
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-cbfs-files-$(CONFIG_CPU_MICROCODE_CBFS_DEFAULT_BINS) += microcode_amd_fam15h.bin
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-microcode_amd_fam15h.bin-file := 3rdparty/blobs/cpu/amd/family_15h/microcode_amd_fam15h.bin
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-microcode_amd_fam15h.bin-type := microcode
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+# Microcode deleted in this version of coreboot.
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--
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2.25.1
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+32
@@ -0,0 +1,32 @@
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From f0aac7261e16adc8e61eca7a506ff2de5112be47 Mon Sep 17 00:00:00 2001
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From: Leah Rowe <leah@libreboot.org>
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Date: Fri, 7 May 2021 19:43:32 +0100
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Subject: [PATCH 6/6] asus/kgpe-d16: enable lc_cache_partitioning and
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experimental_memory_speed_boost
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This really only benefits 63xx opterons which are less reliable in libreboot due
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to lack of CPU microcode updates, but we might aswell enable this anyway.
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---
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src/mainboard/asus/kgpe-d16/cmos.default | 4 ++--
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1 file changed, 2 insertions(+), 2 deletions(-)
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diff --git a/src/mainboard/asus/kgpe-d16/cmos.default b/src/mainboard/asus/kgpe-d16/cmos.default
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index 7c496a50d7..8a25620e1d 100644
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--- a/src/mainboard/asus/kgpe-d16/cmos.default
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+++ b/src/mainboard/asus/kgpe-d16/cmos.default
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@@ -21,10 +21,10 @@ sata_ahci_mode=Enable
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sata_alpm=Disable
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maximum_p_state_limit=0xf
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probe_filter=Auto
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-l3_cache_partitioning=Disable
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+l3_cache_partitioning=Enable
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ieee1394_controller=Enable
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gart=Enable
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ehci_async_data_cache=Enable
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-experimental_memory_speed_boost=Disable
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+experimental_memory_speed_boost=Enable
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power_on_after_fail=On
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boot_option=Fallback
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--
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2.25.1
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Reference in New Issue
Block a user