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pragmatic system distribution guideline compliance

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osboot is now part of libreboot, and will soon shut down.
libreboot now conforms to osboot policy.
This commit is contained in:
Leah Rowe
2022-11-14 00:51:12 +00:00
parent b5c25efed4
commit 7af9953463
167 changed files with 17806 additions and 1421 deletions
Download Patch File Download Diff File Expand all files Collapse all files
resources/coreboot/default/blobs.list
-22
View File
@@ -1,22 +0,0 @@
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000119.c
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_hotplug.c
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_mcdi.c
3rdparty/arm-trusted-firmware/plat/mediatek/mt8173/drivers/spm/spm_suspend.c
3rdparty/arm-trusted-firmware/plat/rockchip/rk3368/drivers/ddr/rk3368_ddr_reg_resume_V1.05.bin
3rdparty/chromeec/test/legacy_nvmem_dump.h
3rdparty/vboot/tests/futility/data/bios_link_mp.bin
3rdparty/vboot/tests/futility/data/bios_peppy_mp.bin
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500000B.c
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch0500001A.c
src/vendorcode/amd/agesa/f14/Proc/CPU/Family/0x14/F14MicrocodePatch05000029.c
src/vendorcode/amd/agesa/f14/Proc/GNB/Nb/Family/0x14/F14NbSmuFirmware.h
src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieAlibSsdt.h
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Family/0x15/TN/F15TnMicrocodePatch0600111F_Enc.c
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFM2.h
src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieAlibSsdtTNFS1.h
src/vendorcode/amd/agesa/f16kb/Proc/CPU/Family/0x16/KB/F16KbId7001MicrocodePatch.c
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/AlibSsdtKB.h
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSamuPatchKB.h
src/vendorcode/amd/agesa/f16kb/Proc/GNB/Modules/GnbInitKB/GnbSmuFirmwareKB.h
3rdparty/chromeec/third_party/bmi260/accelgyro_bmi260_config_tbin.h
resources/coreboot/default/patches/0009-Revert-cpu-intel-Configure-IA32_FEATURE_CONTROL-for-.patch
-115
View File
@@ -1,115 +0,0 @@
From 8e8704050aec67490a6d1f272840e5a04ee1bcff Mon Sep 17 00:00:00 2001
From: Rodrigo <rm@firemail.cc>
Date: Mon, 23 Aug 2021 02:20:32 -0300
Subject: [PATCH 09/11] Revert "cpu/intel: Configure IA32_FEATURE_CONTROL for
alternative SMRR"
This rendered at least the x200 unable to reboot.
This reverts commit df7aecd92643d207feaf7fd840f8835097346644.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 3 +++
src/cpu/intel/model_1067x/mp_init.c | 26 --------------------
src/cpu/intel/model_106cx/model_106cx_init.c | 3 +++
src/cpu/intel/model_6ex/model_6ex_init.c | 3 +++
src/cpu/intel/model_6fx/model_6fx_init.c | 3 +++
5 files changed, 12 insertions(+), 26 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 3e4de1fa31..ca3ce274fc 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -274,6 +274,9 @@ static void model_1067x_init(struct device *cpu)
/* Initialize the APIC timer */
init_timer();
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states(quad);
diff --git a/src/cpu/intel/model_1067x/mp_init.c b/src/cpu/intel/model_1067x/mp_init.c
index bc53214310..72f40f6762 100644
--- a/src/cpu/intel/model_1067x/mp_init.c
+++ b/src/cpu/intel/model_1067x/mp_init.c
@@ -43,34 +43,8 @@ static void pre_mp_smm_init(void)
smm_initialize();
}
-#define SMRR_SUPPORTED (1 << 11)
-
static void per_cpu_smm_trigger(void)
{
- msr_t mtrr_cap = rdmsr(MTRR_CAP_MSR);
- if (cpu_has_alternative_smrr() && mtrr_cap.lo & SMRR_SUPPORTED) {
- set_feature_ctrl_vmx();
- msr_t ia32_ft_ctrl = rdmsr(IA32_FEATURE_CONTROL);
- /* We don't care if the lock is already setting
- as our smm relocation handler is able to handle
- setups where SMRR is not enabled here. */
- if (ia32_ft_ctrl.lo & (1 << 0)) {
- /* IA32_FEATURE_CONTROL locked. If we set it again we
- get an illegal instruction. */
- printk(BIOS_DEBUG, "IA32_FEATURE_CONTROL already locked\n");
- printk(BIOS_DEBUG, "SMRR status: %senabled\n",
- ia32_ft_ctrl.lo & (1 << 3) ? "" : "not ");
- } else {
- if (!CONFIG(SET_IA32_FC_LOCK_BIT))
- printk(BIOS_INFO,
- "Overriding CONFIG(SET_IA32_FC_LOCK_BIT) to enable SMRR\n");
- ia32_ft_ctrl.lo |= (1 << 3) | (1 << 0);
- wrmsr(IA32_FEATURE_CONTROL, ia32_ft_ctrl);
- }
- } else {
- set_vmx_and_lock();
- }
-
/* Relocate the SMM handler. */
smm_relocate();
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index 278d8dea81..a0917045dd 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -70,6 +70,9 @@ static void model_106cx_init(struct device *cpu)
/* Enable the local CPU APICs */
setup_lapic();
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 34646ad5e9..36cfd51f01 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -109,6 +109,9 @@ static void model_6ex_init(struct device *cpu)
/* Enable the local CPU APICs */
setup_lapic();
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 72ece23935..6f2d6ef599 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -123,6 +123,9 @@ static void model_6fx_init(struct device *cpu)
/* Enable the local CPU APICs */
setup_lapic();
+ /* Set virtualization based on Kconfig option */
+ set_vmx_and_lock();
+
/* Configure C States */
configure_c_states();
--
2.25.1
resources/coreboot/default/patches/0010-Fix-missing-include.patch
-63
View File
@@ -1,63 +0,0 @@
From e6960dec197491941254af48b60f1cf1592bcb2b Mon Sep 17 00:00:00 2001
From: Rodrigo <rm@firemail.cc>
Date: Mon, 23 Aug 2021 03:51:21 -0300
Subject: [PATCH 10/11] Fix missing include
---
src/cpu/intel/model_1067x/model_1067x_init.c | 1 +
src/cpu/intel/model_106cx/model_106cx_init.c | 1 +
src/cpu/intel/model_6ex/model_6ex_init.c | 1 +
src/cpu/intel/model_6fx/model_6fx_init.c | 1 +
4 files changed, 4 insertions(+)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index ca3ce274fc..cc7a5edca9 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -9,6 +9,7 @@
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
#include <cpu/intel/smm_reloc.h>
+#include <cpu/intel/common/common.h>
#include "chip.h"
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index a0917045dd..7b88f19ee0 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -8,6 +8,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 36cfd51f01..793474ffa5 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -8,6 +8,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index 6f2d6ef599..d0031ad741 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -8,6 +8,7 @@
#include <cpu/intel/speedstep.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/name.h>
+#include <cpu/intel/common/common.h>
#define HIGHEST_CLEVEL 3
static void configure_c_states(void)
--
2.25.1
resources/coreboot/default/patches/0012-coreboot-Add-Lenovo-X230-patch-gfx_uma_size-224M-by-.patch
+22
View File
@@ -0,0 +1,22 @@
From 6a8bf6d6a52081c06baab2b49ea571f04d4d6e5d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 20 Dec 2021 01:29:31 +0000
Subject: [PATCH 1/1] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
default
---
src/mainboard/lenovo/x230/cmos.default | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 7314066c2b..2e315d4521 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -16,3 +16,4 @@ backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
me_state=Normal
+gfx_uma_size=224M
--
2.25.1
resources/coreboot/default/patches/0012-fix-speedstep-on-x200-t400-Revert-cpu-intel-model_10.patch
-47
View File
@@ -1,47 +0,0 @@
From 69ae79e6dd11cee4e63e89907177ad199d71d74f Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 1/1] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
Enabling PECI without microcode updates loaded causes the CPUID feature set
to become corrupted. And one consequence is broken SpeedStep. At least, that's
my understanding looking at Intel Errata. This revert is not a fix, because
upstream is correct (upstream assumes microcode updates). We will simply
maintain this revert patch in Libreboot, from now on.
---
src/cpu/intel/model_1067x/model_1067x_init.c | 9 ---------
1 file changed, 9 deletions(-)
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index cc7a5edca9..72983eca4f 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -167,8 +167,6 @@ static void configure_emttm_tables(void)
wrmsr(MSR_EMTTM_CR_TABLE(5), msr);
}
-#define IA32_PECI_CTL 0x5a0
-
static void configure_misc(const int eist, const int tm2, const int emttm)
{
msr_t msr;
@@ -211,13 +209,6 @@ static void configure_misc(const int eist, const int tm2, const int emttm)
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr);
}
-
- /* Enable PECI
- WARNING: due to Erratum AW67 described in Intel document #318733
- the microcode must be updated before this MSR is written to. */
- msr = rdmsr(IA32_PECI_CTL);
- msr.lo |= 1;
- wrmsr(IA32_PECI_CTL, msr);
}
#define PIC_SENS_CFG 0x1aa
--
2.25.1
resources/coreboot/default/patches/0013-lenovo-x230-set-me_state-Disable-in-cmos.default.patch
+38
View File
@@ -0,0 +1,38 @@
From 146a4d6454e72da4a9204cb4c48c4994ba4cdd8d Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 3 Jan 2022 19:06:22 +0000
Subject: [PATCH 1/1] lenovo/x230: set me_state=Disabled in cmos.default
I only recently found out about this. It's possible to use me_cleaner to
do the same thing, but some people might just flash coreboot and not do
anything with the ME region
With this change, the ME is set to disabled. It's my understanding that this
will accomplish more or less the same thing as me_cleaner, without actually
using that. Of course, I still recommend using me_cleaner
I saw this when I audited coreboot's git history, and saw this:
commit 833e9bad4762e0dca6c867d3a18dbaf6d5166be8
Author: Evgeny Zinoviev <me@ch1p.io>
Date: Thu Nov 21 21:47:31 2019 +0300
sb/intel/bd82x6x: Support ME Soft Temporary Disable Mode
---
src/mainboard/lenovo/x230/cmos.default | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default
index 2e315d4521..3585cbd58b 100644
--- a/src/mainboard/lenovo/x230/cmos.default
+++ b/src/mainboard/lenovo/x230/cmos.default
@@ -15,5 +15,5 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
gfx_uma_size=224M
--
2.25.1
resources/coreboot/default/patches/0014-set-me_state-Disabled-on-all-cmos.default-files.patch
+100
View File
@@ -0,0 +1,100 @@
From 75a44087be5da44b95133906b2213d7f234e7d0e Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 2 Mar 2022 21:50:01 +0000
Subject: [PATCH 1/1] set me_state=Disabled on all cmos.default files!
yeah. why the hell isn't this the default
---
src/mainboard/lenovo/l520/cmos.default | 2 +-
src/mainboard/lenovo/t420/cmos.default | 2 +-
src/mainboard/lenovo/t420s/cmos.default | 2 +-
src/mainboard/lenovo/t430/cmos.default | 2 +-
src/mainboard/lenovo/t430s/cmos.default | 2 +-
src/mainboard/lenovo/t520/cmos.default | 2 +-
src/mainboard/lenovo/t530/cmos.default | 2 +-
src/mainboard/lenovo/x220/cmos.default | 2 +-
8 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mainboard/lenovo/l520/cmos.default b/src/mainboard/lenovo/l520/cmos.default
index 681c40e78b..57cdcf9162 100644
--- a/src/mainboard/lenovo/l520/cmos.default
+++ b/src/mainboard/lenovo/l520/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
trackpoint=Enable
backlight=Both
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default
index 8244071b8a..c011867916 100644
--- a/src/mainboard/lenovo/t420/cmos.default
+++ b/src/mainboard/lenovo/t420/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default
index 8244071b8a..c011867916 100644
--- a/src/mainboard/lenovo/t420s/cmos.default
+++ b/src/mainboard/lenovo/t420s/cmos.default
@@ -14,4 +14,4 @@ sticky_fn=Disable
trackpoint=Enable
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430/cmos.default b/src/mainboard/lenovo/t430/cmos.default
index 26795fe5cf..55e1e6c04e 100644
--- a/src/mainboard/lenovo/t430/cmos.default
+++ b/src/mainboard/lenovo/t430/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
backlight=Both
usb_always_on=Disable
hybrid_graphics_mode=Integrated Only
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t430s/cmos.default b/src/mainboard/lenovo/t430s/cmos.default
index 52dbf70377..b16800ca9e 100644
--- a/src/mainboard/lenovo/t430s/cmos.default
+++ b/src/mainboard/lenovo/t430s/cmos.default
@@ -16,4 +16,4 @@ backlight=Both
enable_dual_graphics=Disable
usb_always_on=Disable
f1_to_f12_as_primary=Enable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default
index cf79b391e2..b66f7034dc 100644
--- a/src/mainboard/lenovo/t520/cmos.default
+++ b/src/mainboard/lenovo/t520/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default
index cf79b391e2..b66f7034dc 100644
--- a/src/mainboard/lenovo/t530/cmos.default
+++ b/src/mainboard/lenovo/t530/cmos.default
@@ -15,4 +15,4 @@ trackpoint=Enable
backlight=Both
hybrid_graphics_mode=Integrated Only
usb_always_on=Disable
-me_state=Normal
+me_state=Disabled
diff --git a/src/mainboard/lenovo/x220/cmos.default b/src/mainboard/lenovo/x220/cmos.default
index 6d1d57a795..52f303dfdb 100644
--- a/src/mainboard/lenovo/x220/cmos.default
+++ b/src/mainboard/lenovo/x220/cmos.default
@@ -13,4 +13,4 @@ usb_always_on=Disable
fn_ctrl_swap=Disable
sticky_fn=Disable
trackpoint=Enable
-me_state=Normal
+me_state=Disabled
--
2.25.1