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util/e6400-flash-unlock: Rename to dell-flash-unlock
This more accurately describes the scope of the utility. Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
This commit is contained in:
Nicholas Chin
@@ -0,0 +1,19 @@
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Copyright (c) 2023 Nicholas Chin
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Permission is hereby granted, free of charge, to any person obtaining a copy
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of this software and associated documentation files (the "Software"), to deal
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in the Software without restriction, including without limitation the rights
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to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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copies of the Software, and to permit persons to whom the Software is
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furnished to do so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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@@ -0,0 +1,15 @@
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# SPDX-License-Identifier: MIT
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# SPDX-FileCopyrightText: 2023 Nicholas Chin
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CC=cc
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CFLAGS=-Wall -Wextra -Werror -O2 -pedantic
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ifeq ($(shell uname), OpenBSD)
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CFLAGS += -l$(shell uname -p)
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endif
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SRCS=dell_flash_unlock.c accessors.c
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all: $(SRCS) accessors.h
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$(CC) $(CFLAGS) $(SRCS) -o dell_flash_unlock
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clean:
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rm -f dell_flash_unlock
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@@ -0,0 +1,102 @@
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# Dell Laptop Internal Flashing
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This utility allows you to use flashrom's internal programmer to program the
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entire BIOS flash chip from software while still running the original Dell
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BIOS, which normally restricts software writes to the flash chip. It seems like
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this works on any Dell laptop that has an EC similar to the SMSC MEC5035 on the
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E6400, which mainly seem to be the Latitude and Precision lines starting from
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around 2008 (E6400 era).
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## TL;DR
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Run `make` to compile the utility, and then run `sudo ./dell_flash_unlock` and
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follow the directions it outputs.
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## Confirmed supported devices
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- Latitude E6400
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- Latitude E6410
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- Latitude E4310
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- Latitude E6430
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- Precision M6800
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It is likely that any other Latitude/Precision laptops from the same era as
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devices specifically mentioned in the above list will work as Dell seems to use
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the same ECs in one generation.
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## Detailed device specific behavior
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- On GM45 era laptops, the expected behavior is that you will run the utility
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for the first time, which will tell the EC to set the descriptor override on
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the next boot. Then you will need to shut down the system, after which the
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system will automatically boot up. You should then re-run the utility to
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disable SMM, after which you can run flashrom. Finally, you should run the
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utility a third time to reenable SMM so that shutdown works properly
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afterwards.
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- On 1st Generation Intel Core systems such as the E6410 and newer, run the
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utility and shutdown in the same way as the E6400. However, it seems like the
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EC no longer automatically boots the system. In this case you should manually
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power it on. It also seems that the firmware does not set the BIOS Lock bit
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when the descriptor override is set, making the 2nd run after the reboot
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technically unnecessary. There is no harm in rerunning it though, as the
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utility can detect when the flash is unlocked and perform the correct steps
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as necessary.
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## How it works
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There are several ways the firmware can protect itself from being overwritten.
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One way is the Intel Flash Descriptor (IFD) permissions. On Intel systems, the
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flash image is divided into several regions such as the IFD itself, Gigabit
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Ethernet (GBE) non-volative memory, Management Engine (ME) firmware, Platform
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Data (PD), and the BIOS. The IFD contains a section which specifies the
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read/write permissions for each SPI controller (such as the host system) and
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each region of the flash, which are enforced by the chipset.
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On the Latitude E6400, the host has read-only access to the IFD, no access to
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the ME region, and read-write access to the PD, GBE, and BIOS regions. In order
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for flashrom to write to the entire flash internally, the host needs full
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permissions to all of these regions. Since the IFD is read only, we cannot
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change these permissions unless we directly access the chip using an external
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programmer, which defeats the purpose of internal flashing.
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However, Intel chipsets have a pin strap that allows the flash descriptor
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permissions to be overridden depending on the value of the pin at power on,
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granting RW permissions to all regions. On the ICH9M chipset on the E6400, this
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pin is HDA\_DOCK\_EN/GPIO33, which will enable the override if it is sampled
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low. This pin happens to be connected to a GPIO controlled by the Embedded
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Controller (EC), a small microcontroller on the board which handles things like
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the keyboard, touchpad, LEDs, and other system level tasks. Software can send a
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certain command to the EC, which tells it to pull GPIO33 low on the next boot.
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Although we now have full access according to the IFD permissions, we still
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cannot flash the whole chip, due to another protection the firmware uses.
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Before software can update the BIOS, it must change the BIOS Write Enable
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(BIOSWE) bit in the chipset from 0 to 1. However, if the BIOS Lock Enable (BLE)
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bit is also set to 1, then changing the BIOSWE bit triggers a System Management
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Interrupt (SMI). This causes the processor to enter System Management Mode
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(SMM), a highly privileged x86 execution state which operates transparently to
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the operating system. The code that SMM runs is provided by the BIOS, which
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checks the BIOSWE bit and sets it back to 0 before returning control to the OS.
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This feature is intended to only allow SMM code to update the system firmware.
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As the switch to SMM suspends the execution of the OS, it appears to the OS
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that the BIOSWE bit was never set to 1. Unfortunately, the BLE bit cannot be
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set back to 0 once it is set to 1, so this functionality cannot be disabled
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after it is first enabled by the BIOS.
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Older versions of the E6400 BIOS did not set the BLE bit, allowing flashrom to
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flash the entire flash chip internally after only setting the descriptor
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override. However, more recent versions do set it, so we may have hit a dead
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end unless we force downgrade to an older version (though there is a more
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convenient method, as we are about to see).
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What if there was a way to sidestep the BIOS Lock entirely? As it turns out,
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there is, and it's called the Global SMI Enable (GBL\_SMI\_EN) bit. If it's set
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to 1, then the chipset will generate SMIs, such as when we change BIOSWE with
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BLE set. If it's 0, then no SMI will be generated, even with the BLE bit set.
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On the E6400, GBL\_SMI\_EN is set to 1, and it can be changed back to 0, unlike
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the BLE bit. But there still might be one bit in the way, the SMI\_LOCK bit,
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which prevents modifications to GBL\_SMI\_EN when SMI\_LOCK is 1. Like the BLE
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bit, it cannot be changed back to 0 once it set to 1. But we are in luck, as
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the vendor E6400 BIOS leaves SMI\_LOCK unset at 0, allowing us to clear
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GBL\_SMI\_EN and disable SMIs, bypassing the BIOS Lock protections.
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There are other possible protection mechanisms that the firmware can utilize,
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such as Protected Range Register settings, which apply access permissions to
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address ranges of the flash, similar to the IFD. However, the E6400 vendor
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firmware does not utilize these, so they will not be discussed.
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@@ -0,0 +1,91 @@
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/* SPDX-License-Identifier: MIT */
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/* SPDX-FileCopyrightText: 2023 Nicholas Chin */
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#if defined(__linux__)
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#include <sys/io.h>
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#endif
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#if defined(__OpenBSD__)
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#include <machine/sysarch.h>
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#include <sys/types.h>
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#if defined(__amd64__)
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#include <amd64/pio.h>
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#elif defined(__i386__)
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#include <i386/pio.h>
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#endif /* __i386__ */
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#endif /* __OpenBSD__ */
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#include <errno.h>
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#include "accessors.h"
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uint32_t
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pci_read_32(uint32_t dev, uint8_t reg)
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{
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sys_outl(PCI_CFG_ADDR, dev | reg);
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return sys_inl(PCI_CFG_DATA);
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}
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void
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pci_write_32(uint32_t dev, uint8_t reg, uint32_t value)
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{
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sys_outl(PCI_CFG_ADDR, dev | reg);
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sys_outl(PCI_CFG_DATA, value);
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}
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void
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sys_outb(unsigned int port, uint8_t data)
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{
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#if defined(__linux__)
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outb(data, port);
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#endif
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#if defined(__OpenBSD__)
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outb(port, data);
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#endif
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}
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void
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sys_outl(unsigned int port, uint32_t data)
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{
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#if defined(__linux__)
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outl(data, port);
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#endif
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#if defined(__OpenBSD__)
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outl(port, data);
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#endif
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}
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uint8_t
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sys_inb(unsigned int port)
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{
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#if defined(__linux__) || defined (__OpenBSD__)
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return inb(port);
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#endif
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return 0;
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}
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uint32_t
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sys_inl(unsigned int port)
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{
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#if defined(__linux__) || defined (__OpenBSD__)
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return inl(port);
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#endif
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return 0;
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}
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int
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sys_iopl(int level)
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{
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#if defined(__linux__)
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return iopl(level);
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#endif
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#if defined(__OpenBSD__)
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#if defined(__i386__)
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return i386_iopl(level);
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#elif defined(__amd64__)
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return amd64_iopl(level);
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#endif /* __amd64__ */
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#endif /* __OpenBSD__ */
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errno = ENOSYS;
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return -1;
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}
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@@ -0,0 +1,17 @@
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/* SPDX-License-Identifier: MIT */
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/* SPDX-FileCopyrightText: 2023 Nicholas Chin */
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#include <stdint.h>
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#define PCI_CFG_ADDR 0xcf8
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#define PCI_CFG_DATA 0xcfc
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#define PCI_DEV(bus, dev, func) (1u << 31 | bus << 16 | dev << 11 | func << 8)
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uint32_t pci_read_32(uint32_t dev, uint8_t reg);
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void pci_write_32(uint32_t dev, uint8_t reg, uint32_t value);
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int sys_iopl(int level);
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void sys_outb(unsigned int port, uint8_t data);
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void sys_outl(unsigned int port, uint32_t data);
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uint8_t sys_inb(unsigned int port);
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uint32_t sys_inl(unsigned int port);
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@@ -0,0 +1,217 @@
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/* SPDX-License-Identifier: MIT */
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/* SPDX-FileCopyrightText: 2023 Nicholas Chin */
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#include <sys/mman.h>
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#include <err.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include "accessors.h"
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int get_fdo_status(void);
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int check_lpc_decode(void);
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void ec_set_fdo();
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void write_ec_reg(uint8_t index, uint8_t data);
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void send_ec_cmd(uint8_t cmd);
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int wait_ec(void);
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int check_bios_write_en(void);
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int set_gbl_smi_en(int enable);
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int get_gbl_smi_en(void);
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#define EC_INDEX 0x910
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#define EC_DATA 0x911
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#define EC_ENABLE_FDO 2
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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#define RCBA_MMIO_LEN 0x4000
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/* Register offsets */
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#define SPIBAR 0x3800
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#define HSFS_REG 0x04
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#define SMI_EN_REG 0x30
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volatile uint8_t *rcba_mmio;
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uint16_t pmbase;
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int
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main(int argc, char *argv[])
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{
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int devmemfd;
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(void)argc;
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(void)argv;
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if (sys_iopl(3) == -1)
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err(errno, "Could not access IO ports");
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if ((devmemfd = open("/dev/mem", O_RDONLY)) == -1)
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err(errno, "/dev/mem");
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/* Read RCBA and PMBASE from the LPC config registers */
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long int rcba = pci_read_32(LPC_DEV, 0xf0) & 0xffffc000;
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pmbase = pci_read_32(LPC_DEV, 0x40) & 0xff80;
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/* FDO pin-strap status bit is in RCBA mmio space */
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rcba_mmio = mmap(0, RCBA_MMIO_LEN, PROT_READ, MAP_SHARED, devmemfd,
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rcba);
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if (rcba_mmio == MAP_FAILED)
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err(errno, "Could not map RCBA");
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if (get_fdo_status() == 1) { /* Descriptor not overridden */
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if (check_lpc_decode() == -1)
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err(errno = ECANCELED, "Can't forward I/O to LPC");
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printf("Sending FDO override command to EC:\n");
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ec_set_fdo();
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printf("Flash Descriptor Override enabled.\n"
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"Shut down (don't reboot) now.\n\n"
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"The EC may auto-boot on some systems; if not then "
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"manually power on.\n When the system boots rerun "
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"this utility to finish unlocking.\n");
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} else if (check_bios_write_en() == 0) {
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/* SMI locks in place, try disabling SMIs to bypass them */
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if (set_gbl_smi_en(0)) {
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printf("SMIs disabled. Internal flashing should work "
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"now.\n After flashing, re-run this utility "
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"to enable SMIs.\n (shutdown is buggy when "
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"SMIs are disabled)\n");
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} else {
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err(errno = ECANCELED, "Could not disable SMIs!");
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}
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} else { /* SMI locks not in place or bypassed */
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if (get_gbl_smi_en()) {
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/* SMIs are still enabled, assume this is an Exx10
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* or newer which don't need the SMM bypass */
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printf("Flash is unlocked.\n"
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"Internal flashing should work.\n");
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} else {
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/* SMIs disabled, assume this is an Exx00 after
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* unlocking and flashing */
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set_gbl_smi_en(1);
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printf("SMIs enabled.\n"
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"You can now shutdown the system.\n");
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}
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}
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return errno;
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}
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int
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get_fdo_status(void)
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{
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return (*(uint16_t*)(rcba_mmio + SPIBAR + HSFS_REG) >> 13) & 1;
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}
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int
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check_lpc_decode(void)
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{
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/* Check that at a Generic Decode Range Register is set up to
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* forward I/O ports 0x910 and 0x911 over LPC for the EC */
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int i = 0;
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int gen_dec_free = -1;
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for (; i < 4; i++) {
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uint32_t reg_val = pci_read_32(LPC_DEV, 0x84 + 4*i);
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uint16_t base_addr = reg_val & 0xfffc;
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uint16_t mask = ((reg_val >> 16) & 0xfffc) | 0x3;
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/* Bit 0 is the enable for each decode range. If disabled, note
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* this register as available to add our own range decode */
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if ((reg_val & 1) == 0)
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gen_dec_free = i;
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/* Check if the current range register matches port 0x910.
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* 0x911 doesn't need to be checked as the LPC bridge only
|
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* decodes at the dword level, and thus a check is redundant */
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if ((0x910 & ~mask) == base_addr) {
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return 0;
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}
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}
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|
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/* No matching range found, try setting a range in a free register */
|
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if (gen_dec_free != -1) {
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/* Set up an I/O decode range from 0x910-0x913 */
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pci_write_32(LPC_DEV, 0x84 + 4 * gen_dec_free, 0x911);
|
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return 0;
|
||||
} else {
|
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return -1;
|
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}
|
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}
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|
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void
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ec_set_fdo()
|
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{
|
||||
/* EC FDO command arguments for reference:
|
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* 0 = Query EC FDO status
|
||||
* 2 = Enable FDO for next boot
|
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* 3 = Disable FDO for next boot */
|
||||
write_ec_reg(0x12, EC_ENABLE_FDO);
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send_ec_cmd(0xb8);
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}
|
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|
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void
|
||||
write_ec_reg(uint8_t index, uint8_t data)
|
||||
{
|
||||
sys_outb(EC_INDEX, index);
|
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sys_outb(EC_DATA, data);
|
||||
}
|
||||
|
||||
void
|
||||
send_ec_cmd(uint8_t cmd)
|
||||
{
|
||||
sys_outb(EC_INDEX, 0);
|
||||
sys_outb(EC_DATA, cmd);
|
||||
if (wait_ec() == -1)
|
||||
err(errno = ECANCELED, "Timeout while waiting for EC!");
|
||||
}
|
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|
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int
|
||||
wait_ec(void)
|
||||
{
|
||||
uint8_t busy;
|
||||
int timeout = 1000;
|
||||
do {
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sys_outb(EC_INDEX, 0);
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||||
busy = sys_inb(EC_DATA);
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||||
timeout--;
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||||
usleep(1000);
|
||||
} while (busy && timeout > 0);
|
||||
return timeout > 0 ? 0 : -1;
|
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}
|
||||
|
||||
int
|
||||
check_bios_write_en(void)
|
||||
{
|
||||
uint8_t bios_cntl = pci_read_32(LPC_DEV, 0xdc) & 0xff;
|
||||
/* Bit 5 = SMM BIOS Write Protect Disable (SMM_BWP)
|
||||
* Bit 1 = BIOS Lock Enable (BLE)
|
||||
* If both are 0, then there's no write protection */
|
||||
if ((bios_cntl & 0x22) == 0)
|
||||
return 1;
|
||||
|
||||
/* SMM protection is enabled, but try enabling writes
|
||||
* anyway in case the vendor SMM code doesn't reset it */
|
||||
pci_write_32(LPC_DEV, 0xdc, bios_cntl | 0x1);
|
||||
return pci_read_32(LPC_DEV, 0xdc) & 0x1;
|
||||
}
|
||||
|
||||
int
|
||||
set_gbl_smi_en(int enable)
|
||||
{
|
||||
uint32_t smi_en = sys_inl(pmbase + SMI_EN_REG);
|
||||
if (enable) {
|
||||
smi_en |= 1;
|
||||
} else {
|
||||
smi_en &= ~1;
|
||||
}
|
||||
sys_outl(pmbase + SMI_EN_REG, smi_en);
|
||||
return (get_gbl_smi_en() == enable);
|
||||
}
|
||||
|
||||
int
|
||||
get_gbl_smi_en(void)
|
||||
{
|
||||
return sys_inl(pmbase + SMI_EN_REG) & 1;
|
||||
}
|
||||
Reference in New Issue
Block a user