coreboot/default bump: rev d862695f5f, 12 Oct 2023

Riku's mSATA patch for HP8300USDT was merged upstream, so the
patch has been dropped from lbmk because it is contained within
this new coreboot revision.

Signed-off-by: Leah Rowe <leah@libreboot.org>
This commit is contained in:
Leah Rowe
2023-10-12 23:12:17 +01:00
parent 09881212c3
commit 42068f7ce1
135 changed files with 582 additions and 960 deletions
@@ -1,7 +1,7 @@
From 21270ad036cdd1ee708a04c41ba6c4f279e4e6c0 Mon Sep 17 00:00:00 2001
From e8f5f6c372152c7deddd3080954d0f4fdd39ae2b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@retroboot.org>
Date: Fri, 19 Mar 2021 05:54:58 +0000
Subject: [PATCH 01/19] apple/macbook21: Set default VRAM to 64MiB instead of
Subject: [PATCH 01/22] apple/macbook21: Set default VRAM to 64MiB instead of
8MiB
---
@@ -1,7 +1,7 @@
From 6fa4c1488911b98e29d3e2858be68b9b72182573 Mon Sep 17 00:00:00 2001
From fdd756a8217548981a1eb62e504cc37371c9fd51 Mon Sep 17 00:00:00 2001
From: Vitali64 <5405891-vitali64yt@users.noreply.gitlab.com>
Date: Wed, 27 Oct 2021 13:36:01 +0200
Subject: [PATCH 02/19] add c3 and clockgen to apple/macbook21
Subject: [PATCH 02/22] add c3 and clockgen to apple/macbook21
---
src/mainboard/apple/macbook21/Kconfig | 1 +
@@ -1,7 +1,7 @@
From 79d9155c71f6014ff6adb454fe65466642bc2413 Mon Sep 17 00:00:00 2001
From c8332a8bac4986afec6c639f55c5876f83e50b76 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Sun, 3 Jan 2021 03:34:01 +0000
Subject: [PATCH 03/19] lenovo/x60: 64MiB Video RAM changed to default
Subject: [PATCH 03/22] lenovo/x60: 64MiB Video RAM changed to default
(previously it was 8MiB)
---
@@ -1,7 +1,7 @@
From 51a20e0db3fb9bf26ce138c9a17abe963bb8b289 Mon Sep 17 00:00:00 2001
From 2e3ad35c24a86cb3109f4e5139b9ffba931eb80b Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@osboot.org>
Date: Mon, 22 Feb 2021 22:16:59 +0000
Subject: [PATCH 04/19] lenovo/t60: make 64MiB VRAM the default in cmos.default
Subject: [PATCH 04/22] lenovo/t60: make 64MiB VRAM the default in cmos.default
---
src/mainboard/lenovo/t60/cmos.default | 2 +-
@@ -1,7 +1,7 @@
From 400e23c5149ab53300f57d8334ab25645d27b0c8 Mon Sep 17 00:00:00 2001
From 5fc03fbf8c7fa30588dab93c76b5532ce03b1610 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:10:33 +0100
Subject: [PATCH 05/19] lenovo/t400: set VRAM to 256MiB VRAM by default
Subject: [PATCH 05/22] lenovo/t400: set VRAM to 256MiB VRAM by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
@@ -1,7 +1,7 @@
From 29e6f78973928ad9ae86b26d5cf308a2680c88bf Mon Sep 17 00:00:00 2001
From 93f607fed477b3e63b7929808937436ac2898b34 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:11:59 +0100
Subject: [PATCH 06/19] lenovo/x200: set VRAM to 256MiB by default
Subject: [PATCH 06/22] lenovo/x200: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
@@ -1,7 +1,7 @@
From 9339fbdd36ceed6b1606b7a6ff07404f4f2a2d6d Mon Sep 17 00:00:00 2001
From 9faa780b2ac45bc1bf61aa252364ee3158c4cb10 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:18:26 +0100
Subject: [PATCH 07/19] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
Subject: [PATCH 07/22] gigabyte/ga-g41m-es2l: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
@@ -1,7 +1,7 @@
From 54197e66c6ecf33743489be9ab0352cfc4b1ffe2 Mon Sep 17 00:00:00 2001
From f1c59cd67446303a5cdf9107461247a63f894de3 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Fri, 14 May 2021 13:21:39 +0100
Subject: [PATCH 08/19] acer/g43t-am3: set VRAM to 256MiB by default
Subject: [PATCH 08/22] acer/g43t-am3: set VRAM to 256MiB by default
Signed-off-by: Leah Rowe <leah@libreboot.org>
---
@@ -1,7 +1,7 @@
From bc4ef158c4c6836351a395e8f0ff24f7c6d1f2c6 Mon Sep 17 00:00:00 2001
From 75858ba200a2a5835bca0af9b5f508a52ed978de Mon Sep 17 00:00:00 2001
From: persmule <persmule@gmail.com>
Date: Sun, 31 Oct 2021 23:33:26 +0000
Subject: [PATCH 09/19] lenovo/t400: Enable all SATA ports
Subject: [PATCH 09/22] lenovo/t400: Enable all SATA ports
There are 2 SATA ports on the chassis of t400(s), but at least one dock for
t400 contains a port for (P/S)ATA device, and t400s has a eSATA port on its
@@ -1,7 +1,7 @@
From 5987d9e821931ce097e265c13ca80a2090d3d821 Mon Sep 17 00:00:00 2001
From 2c103a71a37eb4db9d33928b2371a682ca04e65f Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 20 Dec 2021 01:29:31 +0000
Subject: [PATCH 10/19] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
Subject: [PATCH 10/22] coreboot: Add Lenovo X230 patch: gfx_uma_size 224M by
default
---
@@ -1,7 +1,7 @@
From e5a6fac5b3c75c5aa4ae5106ec336a18083fbab0 Mon Sep 17 00:00:00 2001
From 040f15039fa59d70cd54b8fff5d947e155666aa1 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 3 Jan 2022 19:06:22 +0000
Subject: [PATCH 11/19] lenovo/x230: set me_state=Disabled in cmos.default
Subject: [PATCH 11/22] lenovo/x230: set me_state=Disabled in cmos.default
I only recently found out about this. It's possible to use me_cleaner to
do the same thing, but some people might just flash coreboot and not do
@@ -1,7 +1,7 @@
From 03610ab506bdaca92c1623abd18b4812f92273ed Mon Sep 17 00:00:00 2001
From 81febff42c66bd53e44176f14b651339b503a9f3 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 2 Mar 2022 21:50:01 +0000
Subject: [PATCH 12/19] set me_state=Disabled on all cmos.default files!
Subject: [PATCH 12/22] set me_state=Disabled on all cmos.default files!
yeah. why the hell isn't this the default
@@ -1,7 +1,7 @@
From f4e5f11762e4c54829e1d6515d7fd369d86ac9d7 Mon Sep 17 00:00:00 2001
From c73269315626678c191ea494338581abdc417f21 Mon Sep 17 00:00:00 2001
From: Alexander Couzens <lynxis@fe80.eu>
Date: Sat, 19 Mar 2022 13:42:33 +0000
Subject: [PATCH 13/19] lenovo/x230: introduce FHD variant
Subject: [PATCH 13/22] lenovo/x230: introduce FHD variant
There is a modification for the x230 which uses the 2nd DP from the dock
as the integrated panel's connection, which allows using a custom eDP
@@ -1,7 +1,7 @@
From 982734642e0c8a960b99180371a5a12c3851b6e9 Mon Sep 17 00:00:00 2001
From c32229e3f82c00abb2bee4d0f7ddf33d4c7a04dc Mon Sep 17 00:00:00 2001
From: Alexei Sorokin <sor.alexei@meowr.ru>
Date: Sun, 27 Nov 2022 18:36:26 +0300
Subject: [PATCH 14/19] lenovo/x230: fix the data.vbt path for the EDP variant
Subject: [PATCH 14/22] lenovo/x230: fix the data.vbt path for the EDP variant
---
src/mainboard/lenovo/x230/Kconfig | 2 +-
@@ -1,7 +1,7 @@
From 35425512e05c989d2d6789551cc448719ab1ca38 Mon Sep 17 00:00:00 2001
From 38c76afbea4abfed2976bfbe10977e41f21665b0 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Sun, 19 Feb 2023 18:21:43 +0000
Subject: [PATCH 15/19] util/ifdtool: add --nuke flag (all 0xFF on region)
Subject: [PATCH 15/22] util/ifdtool: add --nuke flag (all 0xFF on region)
When this option is used, the region's contents are overwritten
with all ones (0xFF).
@@ -1,7 +1,7 @@
From 929974434bbd627ab7add5ef4ec4eb62e5412f57 Mon Sep 17 00:00:00 2001
From 3ec06fa2393995b87af1dbc0387c5d3255d5c0db Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Wed, 1 Dec 2021 02:53:00 +0000
Subject: [PATCH 16/19] fix speedstep on x200/t400: Revert
Subject: [PATCH 16/22] fix speedstep on x200/t400: Revert
"cpu/intel/model_1067x: enable PECI"
This reverts commit 70fea013c7ebd6d85a7806748233fcfd76802f5f.
@@ -1,7 +1,7 @@
From f5859da443fc1ff2450051d1d88bee56346fe63b Mon Sep 17 00:00:00 2001
From fdde15b69bd5c8bf54339adf3581a32fa992a503 Mon Sep 17 00:00:00 2001
From: Leah Rowe <leah@libreboot.org>
Date: Mon, 17 Apr 2023 15:49:57 +0100
Subject: [PATCH 17/19] GM45-type CPUs: don't enable alternative SMRR
Subject: [PATCH 17/22] GM45-type CPUs: don't enable alternative SMRR
This reverts the changes in coreboot revision:
df7aecd92643d207feaf7fd840f8835097346644
@@ -1,7 +1,7 @@
From 6dc133e52c1ede4dbd3207133dd8ed0eb053fcd0 Mon Sep 17 00:00:00 2001
From a65797a9e7e610b1c916cb4d275b72848622c218 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 6 May 2023 15:53:41 -0600
Subject: [PATCH 18/19] mb/dell/e6400: Enable 01.0 device in devicetree for
Subject: [PATCH 18/22] mb/dell/e6400: Enable 01.0 device in devicetree for
dGPU models
Change-Id: I9b8e5d3cd1e1f64dc87b682b1e045b6342924aed
@@ -1,7 +1,7 @@
From eb0fa411af62bf33cac69f3ba082e2d513bd9ab2 Mon Sep 17 00:00:00 2001
From 7d5452bc3358cf82eea48fde312494bcb4ca8101 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Fri, 12 May 2023 19:55:15 -0600
Subject: [PATCH 19/19] Remove warning for coreboot images built without a
Subject: [PATCH 19/22] Remove warning for coreboot images built without a
payload
I added this in upstream to prevent people from accidentally flashing
@@ -1,7 +1,7 @@
From f4c41a930b777128bd418cbae525ba509e5f19ff Mon Sep 17 00:00:00 2001
From f0db13a15c76c2947eec8919fd121450048914ce Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 27 Aug 2023 17:36:36 -0600
Subject: [PATCH 1/3] ec/dell/mec5035: Add command to enable/disable radios
Subject: [PATCH 20/22] ec/dell/mec5035: Add command to enable/disable radios
These were determined by sniffing the LPC bus while toggling the
hardware wireless switch on the Latitude E6400. To differentiate devices
@@ -57,5 +57,5 @@ index e7a05b64d4..16512e2cc2 100644
#endif /* _EC_DELL_MEC5035_H_ */
--
2.42.0
2.39.2
@@ -1,32 +0,0 @@
From 19ebc65d2c5854d9dea6f4a710ebfa695c80f030 Mon Sep 17 00:00:00 2001
From: Riku Viitanen <riku.viitanen@protonmail.com>
Date: Tue, 22 Aug 2023 20:07:22 +0300
Subject: [PATCH] mb/hp8300usdt: enable mSATA
Enables the mSATA slot on HP Compaq Elite 8300 USDT.
Tested, it works at the same speed as vendor FW (3Gb/s).
Signed-off-by: Riku Viitanen <riku.viitanen@protonmail.com>
---
src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb
index ba4ac6d7f2..f7f321fc83 100644
--- a/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb
+++ b/src/mainboard/hp/compaq_elite_8300_usdt/devicetree.cb
@@ -9,9 +9,9 @@ chip northbridge/intel/sandybridge
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
register "pcie_port_coalesce" = "1"
register "sata_interface_speed_support" = "0x3"
- register "sata_port_map" = "0x3" # 0x1: 2.5" slot
+ register "sata_port_map" = "0x7" # 0x1: 2.5" slot
# 0x2: DVD
- # 0x?: mSATA
+ # 0x4: mSATA
register "spi_lvscc" = "0x2005"
register "spi_uvscc" = "0x2005"
register "superspeed_capable_ports" = "0x0000000f"
--
2.41.0
@@ -1,7 +1,7 @@
From 1b607998e3e7054ce1107ba6af48902f6b6ffb02 Mon Sep 17 00:00:00 2001
From 4537c365dae010645404fdb5d2d4e5f478dede67 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sun, 27 Aug 2023 19:15:37 -0600
Subject: [PATCH 2/3] ec/dell/mec5035: Hook up radio enables to option API
Subject: [PATCH 21/22] ec/dell/mec5035: Hook up radio enables to option API
Change-Id: I52de5ea3d24b400a93adee7a6207a4439eac61db
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
@@ -33,5 +33,5 @@ index e0335a4635..20a33cc0ad 100644
static struct device_operations ops = {
--
2.42.0
2.39.2
@@ -1,7 +1,7 @@
From e4e508c3375d38c434678a2e0652b55e7ea79fc5 Mon Sep 17 00:00:00 2001
From db1cb588b64f17c7ed08201bf1e09ab5393e4b04 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Sat, 19 Aug 2023 16:19:10 -0600
Subject: [PATCH 3/3] mb/dell: Add Latitude E6430 (Ivy Bridge)
Subject: [PATCH 22/22] mb/dell: Add Latitude E6430 (Ivy Bridge)
Mainboard is QAL80/LA-7781P (UMA). The dGPU model was not tested.
This is based on the autoport output with some manual tweaks. The flash
@@ -816,5 +816,5 @@ index 0000000000..31e49802fc
+ .enable_dev = mainboard_enable,
+};
--
2.42.0
2.39.2
+1 -1
View File
@@ -1,4 +1,4 @@
tree="default"
romtype="normal"
rev="d86260a134575b083f35103e1cd5c7c7ad883bce"
rev="d862695f5f432b5c78dada5f16c293a4c3f9fce6"
arch="x86_64"