coreboot/default: use alternative heap size fix

My previous fix to revert didn't fix S3 on GM45, one
of the platforms reported fixed by 78263; I'm merging
that instead, at patch set 10.

It is referenced by 78815/1 which was split from it,
so merge that too (restores overrides of higher values,
on certain platforms that we don't use yet).

https://review.coreboot.org/c/coreboot/+/78623/10
https://review.coreboot.org/c/coreboot/+/78815/1

Accordingly, update configs to match the new default.

Signed-off-by: Leah Rowe <leah@libreboot.org>

config/coreboot/x230_12mb/config/libgfxinit_corebootfb

@@ -211,7 +211,6 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -255,6 +254,7 @@ CONFIG_SMM_TSEG_SIZE=0x800000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_HEAP_SIZE=0x80000
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"

config/coreboot/x230_12mb/config/libgfxinit_txtmode

@@ -209,7 +209,6 @@ CONFIG_PCIEXP_ASPM=y
 # CONFIG_PCIEXP_CLK_PM is not set
 # CONFIG_DRIVERS_UART_8250IO is not set
 CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
-CONFIG_HEAP_SIZE=0x4000
 CONFIG_EC_GPE_SCI=0x50
 # CONFIG_TPM_MEASURED_BOOT is not set
 CONFIG_BOARD_ROMSIZE_KB_12288=y
@@ -253,6 +252,7 @@ CONFIG_SMM_TSEG_SIZE=0x800000
 CONFIG_SMM_RESERVED_SIZE=0x100000
 CONFIG_SMM_MODULE_STACK_SIZE=0x400
 # CONFIG_USE_EXP_X86_64_SUPPORT is not set
+CONFIG_HEAP_SIZE=0x80000
 CONFIG_SERIRQ_CONTINUOUS_MODE=y
 CONFIG_EHCI_BAR=0xfef00000
 CONFIG_ACPI_CPU_STRING="CP%02X"