coreboot/default: use alternative heap size fix

My previous fix to revert didn't fix S3 on GM45, one
of the platforms reported fixed by 78263; I'm merging
that instead, at patch set 10.

It is referenced by 78815/1 which was split from it,
so merge that too (restores overrides of higher values,
on certain platforms that we don't use yet).

https://review.coreboot.org/c/coreboot/+/78623/10
https://review.coreboot.org/c/coreboot/+/78815/1

Accordingly, update configs to match the new default.

Signed-off-by: Leah Rowe <leah@libreboot.org>
This commit is contained in:
Leah Rowe
2023-10-31 08:11:53 +00:00
parent 9606c68c5b
commit 29e9c32e32
117 changed files with 235 additions and 455 deletions
@@ -207,7 +207,6 @@ CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -249,6 +248,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
CONFIG_HEAP_SIZE=0x80000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000
@@ -205,7 +205,6 @@ CONFIG_D3COLD_SUPPORT=y
# CONFIG_PCIEXP_CLK_PM is not set
# CONFIG_DRIVERS_UART_8250IO is not set
CONFIG_PC_CMOS_BASE_PORT_BANK1=0x72
CONFIG_HEAP_SIZE=0x4000
CONFIG_EC_GPE_SCI=0x50
CONFIG_BOARD_ROMSIZE_KB_8192=y
# CONFIG_COREBOOT_ROMSIZE_KB_256 is not set
@@ -247,6 +246,7 @@ CONFIG_VERSTAGE_ADDR=0x2000000
CONFIG_SMM_RESERVED_SIZE=0x100000
CONFIG_SMM_MODULE_STACK_SIZE=0x400
# CONFIG_USE_EXP_X86_64_SUPPORT is not set
CONFIG_HEAP_SIZE=0x80000
CONFIG_EHCI_BAR=0xfef00000
CONFIG_ACPI_CPU_STRING="CP%02X"
CONFIG_STACK_SIZE=0x2000